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stringlengths 6
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int64 1
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int64 137
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stringlengths 137
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stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
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float64 1.51
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| autogenerated
bool 1
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classes | has_no_keywords
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class | has_few_assignments
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|---|---|---|---|---|---|---|---|---|---|---|---|---|
grafi-tt/Maizul
|
src/Unit/FPU/FAdd.vhd
| 1 | 8,300 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FAdd is
port (
clk : in std_logic;
flt_in1 : in std_logic_vector(31 downto 0);
flt_in2 : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end FAdd;
architecture dataflow_pipeline of FAdd is
component FractionLeftTrimming
port (
frc_in : in std_logic_vector(23 downto 0);
nlz : out std_logic_vector( 4 downto 0);
frc_out : out std_logic_vector(22 downto 0));
end component;
component FractionRightShifter is
port (
frc_in : in std_logic_vector(23 downto 0);
len : in std_logic_vector( 4 downto 0);
frc_out : out std_logic_vector(23 downto 0);
fst_over_out : out std_logic;
snd_over_out : out std_logic;
tail_any_out : out std_logic);
end component;
signal s1_sgn1, s1_sgn2 : std_logic;
signal s1_exp1, s1_exp2 : std_logic_vector( 7 downto 0);
signal s1_frc1, s1_frc2 : std_logic_vector(23 downto 0);
signal s1_raw_len_pos_sft, s1_raw_len_neg_sft : std_logic_vector(8 downto 0);
signal s1_len_sft : std_logic_vector(4 downto 0);
signal s1_valid_pos_sft, s1_valid_neg_sft : boolean;
signal s1_pos_sft : boolean;
signal s1_fst_over, s1_snd_over, s1_tail_any : std_logic;
signal s1_sgn_sup, s1_sgn_inf : std_logic;
signal s1_exp_unif : std_logic_vector(7 downto 0);
signal s1_frc_inf : std_logic_vector(23 downto 0);
signal s1_frc_unif_sup, s1_frc_unif_inf : std_logic_vector(23 downto 0);
signal s1_zero_sft, s1_is_add : boolean := false;
signal s2_sgn_sup, s2_sgn_inf : std_logic := '0';
signal s2_exp_unif : std_logic_vector(7 downto 0) := (others => '0');
signal s2_frc_unif_sup, s2_frc_unif_inf : std_logic_vector(23 downto 0) := (others => '0');
signal s2_fst_over, s2_snd_over, s2_tail_any : std_logic := '0';
signal s2_zero_sft, s2_is_add : boolean := false;
signal s2_round_further, s2_round_further_dbl, s2_round_further_hlf : std_logic;
signal s2_frc_out_adder1, s2_frc_out_adder2 : std_logic_vector(24 downto 0);
signal s2_frc_ireg : std_logic_vector(23 downto 0);
signal s2_frc_out_noinf_add : std_logic_vector(22 downto 0);
signal s2_no_flow, s2_no_down, s2_exact : boolean;
signal s3_sgn_sup, s3_sgn_inf : std_logic := '0';
signal s3_exp_unif : std_logic_vector(7 downto 0) := (others => '0');
signal s3_frc_ireg : std_logic_vector(23 downto 0) := (others => '0');
signal s3_frc_out_noinf_add : std_logic_vector(22 downto 0) := (others => '0');
signal s3_no_flow, s3_no_down, s3_exact, s3_zero_sft, s3_is_add : boolean := false;
signal s3_nlz : std_logic_vector(4 downto 0);
signal s3_down_frc : std_logic;
signal s3_exp_out_sub_raw : std_logic_vector(8 downto 0);
signal s3_exp_out_add, s3_exp_out_sub : std_logic_vector(7 downto 0);
signal s3_frc_out_add, s3_frc_out_sub : std_logic_vector(22 downto 0);
signal s3_sgn_out_sub : std_logic;
begin
s1_sgn1 <= flt_in1(31);
s1_exp1 <= flt_in1(30 downto 23);
s1_frc1 <= '0' & flt_in1(22 downto 0) when s1_exp1 = 0 else '1' & flt_in1(22 downto 0);
s1_sgn2 <= flt_in2(31);
s1_exp2 <= flt_in2(30 downto 23);
s1_frc2 <= '0' & flt_in2(22 downto 0) when s1_exp2 = 0 else '1' & flt_in2(22 downto 0);
s1_raw_len_pos_sft <= ('0' & s1_exp1) - ('0' & s1_exp2);
s1_raw_len_neg_sft <= ('0' & s1_exp2) - ('0' & s1_exp1);
s1_valid_pos_sft <= s1_raw_len_pos_sft(8 downto 5) = "0000";
s1_valid_neg_sft <= s1_raw_len_neg_sft(8 downto 5) = "0000";
s1_pos_sft <= s1_raw_len_pos_sft(8) = '0';
s1_len_sft <= s1_raw_len_neg_sft(4 downto 0) when s1_valid_neg_sft else
s1_raw_len_pos_sft(4 downto 0) when s1_valid_pos_sft else
"11111";
s1_sgn_sup <= s1_sgn1 when s1_pos_sft else s1_sgn2;
s1_sgn_inf <= s1_sgn2 when s1_pos_sft else s1_sgn1;
s1_exp_unif <= s1_exp1 when s1_pos_sft else s1_exp2;
s1_frc_unif_sup <= s1_frc1 when s1_pos_sft else s1_frc2;
s1_frc_inf <= s1_frc2 when s1_pos_sft else s1_frc1;
s1_zero_sft <= s1_raw_len_pos_sft(8) = '0' and s1_raw_len_neg_sft(8) = '0';
s1_is_add <= s1_sgn1 = s1_sgn2;
sft_unif_frc_map : FractionRightShifter port map (
frc_in => s1_frc_inf,
len => s1_len_sft,
frc_out => s1_frc_unif_inf,
fst_over_out => s1_fst_over,
snd_over_out => s1_snd_over,
tail_any_out => s1_tail_any);
pipe1: process(clk)
begin
if rising_edge(clk) then
s2_sgn_sup <= s1_sgn_sup;
s2_sgn_inf <= s1_sgn_inf;
s2_exp_unif <= s1_exp_unif;
s2_frc_unif_sup <= s1_frc_unif_sup;
s2_frc_unif_inf <= s1_frc_unif_inf;
s2_fst_over <= s1_fst_over;
s2_snd_over <= s1_snd_over;
s2_tail_any <= s1_tail_any;
s2_zero_sft <= s1_zero_sft;
s2_is_add <= s1_is_add;
end if;
end process;
s2_round_further_hlf <= s2_snd_over and (s2_tail_any or s2_fst_over);
s2_round_further <= s2_fst_over and ((s2_snd_over or s2_tail_any) or (s2_frc_unif_sup(0) xor s2_frc_unif_inf(0)));
s2_round_further_dbl <= (s2_frc_unif_sup(0) and s2_frc_unif_inf(0)) or
( (s2_frc_unif_sup(0) or s2_frc_unif_inf(0)) and
(((s2_fst_over or s2_snd_over) or s2_tail_any) or (s2_frc_unif_sup(1) xor s2_frc_unif_inf(1))));
s2_frc_out_adder1 <= ('0' & s2_frc_unif_sup) + ('0' & s2_frc_unif_inf) + s2_round_further when s2_is_add else
('0' & s2_frc_unif_sup) - ('0' & s2_frc_unif_inf) - s2_round_further;
s2_frc_out_adder2 <= ("00" & (s2_frc_unif_sup(23 downto 1))) + ("00" & (s2_frc_unif_inf(23 downto 1))) + s2_round_further_dbl when s2_is_add else
('0' & s2_frc_unif_inf) - ('0' & s2_frc_unif_sup) - s2_round_further when s2_zero_sft else
('0' & (s2_frc_unif_sup(22 downto 0)) & '0') - ('0' & (s2_frc_unif_inf(22 downto 0) & s2_fst_over)) - s2_round_further_hlf;
s2_no_flow <= s2_frc_out_adder1(24) = '0';
s2_exact <= s2_frc_out_adder2(24) = '0' and s2_no_flow and s2_zero_sft;
s2_no_down <= s2_frc_out_adder1(23) = '1';
s2_frc_ireg <= s2_frc_out_adder1(23 downto 0) when s2_zero_sft and s2_no_flow else
s2_frc_out_adder2(23 downto 0) when s2_zero_sft and not s2_no_flow else
s2_frc_out_adder1(23 downto 0) when s2_no_down else
s2_frc_out_adder2(23 downto 0);
s2_frc_out_noinf_add <= s2_frc_out_adder1(22 downto 0) when s2_no_flow else
s2_frc_out_adder2(22 downto 0);
pipe2: process(clk)
begin
if rising_edge(clk) then
s3_sgn_sup <= s2_sgn_sup;
s3_sgn_inf <= s2_sgn_inf;
s3_exp_unif <= s2_exp_unif;
s3_frc_ireg <= s2_frc_ireg;
s3_frc_out_noinf_add <= s2_frc_out_noinf_add;
s3_no_flow <= s2_no_flow;
s3_exact <= s2_exact;
s3_no_down <= s2_no_down;
s3_zero_sft <= s2_zero_sft;
s3_is_add <= s2_is_add;
end if;
end process;
s3_exp_out_add <= s3_exp_unif when s3_no_flow else s3_exp_unif+1;
s3_frc_out_add <= (others => '0') when s3_exp_out_add = "11111111" else
s3_frc_out_noinf_add;
s3_sgn_out_sub <= '0' when s3_exact else
s3_sgn_sup when not s3_zero_sft or s3_no_flow else
s3_sgn_inf;
pad_frc_ireg_map : FractionLeftTrimming port map (
frc_in => s3_frc_ireg,
nlz => s3_nlz,
frc_out => s3_frc_out_sub);
s3_down_frc <= '0' when s3_zero_sft or s3_no_down else '1';
s3_exp_out_sub_raw <= ('0' & s3_exp_unif) - ("0000" & s3_nlz) - s3_down_frc;
s3_exp_out_sub <= "00000000" when (s3_nlz(4) = '1' and s3_nlz(3) = '1') or s3_exp_out_sub_raw(8) = '1' else
s3_exp_out_sub_raw(7 downto 0);
flt_out <= s3_sgn_sup & s3_exp_out_add & s3_frc_out_add(22 downto 0) when s3_is_add else
s3_sgn_out_sub & s3_exp_out_sub & s3_frc_out_sub(22 downto 0);
end dataflow_pipeline;
|
bsd-2-clause
|
237c95168f84862ae84bbf432d33d2c6
| 0.571084 | 2.588896 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_g8j.vhd
| 1 | 6,769 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_g8j_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_g8j_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000001", 2 to 3=> "00000010", 4 => "00000011",
5 => "00000100", 6 => "00000101", 7 to 8=> "00000110", 9 => "00000111",
10 => "00001000", 11 => "00001001", 12 to 13=> "00001010", 14 => "00001011",
15 => "00001100", 16 => "00001101", 17 to 18=> "00001110", 19 => "00001111",
20 => "00010000", 21 => "00010001", 22 to 23=> "00010010", 24 => "00010011",
25 => "00010100", 26 => "00010101", 27 to 28=> "00010110", 29 => "00010111",
30 => "00011000", 31 => "00011001", 32 to 33=> "00011010", 34 => "00011011",
35 => "00011100", 36 => "00011101", 37 to 38=> "00011110", 39 => "00011111",
40 => "00100000", 41 => "00100001", 42 to 43=> "00100010", 44 => "00100011",
45 => "00100100", 46 => "00100101", 47 to 48=> "00100110", 49 => "00100111",
50 => "00101000", 51 => "00101001", 52 to 53=> "00101010", 54 => "00101011",
55 => "00101100", 56 => "00101101", 57 to 58=> "00101110", 59 => "00101111",
60 => "00110000", 61 => "00110001", 62 to 63=> "00110010", 64 => "00110011",
65 => "00110100", 66 => "00110101", 67 to 68=> "00110110", 69 => "00110111",
70 => "00111000", 71 => "00111001", 72 to 73=> "00111010", 74 => "00111011",
75 => "00111100", 76 => "00111101", 77 to 78=> "00111110", 79 => "00111111",
80 => "01000000", 81 => "01000001", 82 to 83=> "01000010", 84 => "01000011",
85 => "01000100", 86 => "01000101", 87 to 88=> "01000110", 89 => "01000111",
90 => "01001000", 91 => "01001001", 92 to 93=> "01001010", 94 => "01001011",
95 => "01001100", 96 => "01001101", 97 to 98=> "01001110", 99 => "01001111",
100 => "01010000", 101 => "01010001", 102 to 103=> "01010010", 104 => "01010011",
105 => "01010100", 106 => "01010101", 107 to 108=> "01010110", 109 => "01010111",
110 => "01011000", 111 => "01011001", 112 to 113=> "01011010", 114 => "01011011",
115 => "01011100", 116 => "01011101", 117 to 118=> "01011110", 119 => "01011111",
120 => "01100000", 121 => "01100001", 122 to 123=> "01100010", 124 => "01100011",
125 => "01100100", 126 => "01100101", 127 to 128=> "01100110", 129 => "01100111",
130 => "01101000", 131 => "01101001", 132 to 133=> "01101010", 134 => "01101011",
135 => "01101100", 136 => "01101101", 137 to 138=> "01101110", 139 => "01101111",
140 => "01110000", 141 => "01110001", 142 to 143=> "01110010", 144 => "01110011",
145 => "01110100", 146 => "01110101", 147 to 148=> "01110110", 149 => "01110111",
150 => "01111000", 151 => "01111001", 152 to 153=> "01111010", 154 => "01111011",
155 => "01111100", 156 => "01111101", 157 to 158=> "01111110", 159 => "01111111",
160 => "10000000", 161 => "10000001", 162 to 163=> "10000010", 164 => "10000011",
165 => "10000100", 166 => "10000101", 167 to 168=> "10000110", 169 => "10000111",
170 => "10001000", 171 => "10001001", 172 to 173=> "10001010", 174 => "10001011",
175 => "10001100", 176 => "10001101", 177 to 178=> "10001110", 179 => "10001111",
180 => "10010000", 181 => "10010001", 182 to 183=> "10010010", 184 => "10010011",
185 => "10010100", 186 => "10010101", 187 to 188=> "10010110", 189 => "10010111",
190 => "10011000", 191 => "10011001", 192 to 193=> "10011010", 194 => "10011011",
195 => "10011100", 196 => "10011101", 197 to 198=> "10011110", 199 => "10011111",
200 => "10100000", 201 => "10100001", 202 to 203=> "10100010", 204 => "10100011",
205 => "10100100", 206 => "10100101", 207 to 208=> "10100110", 209 => "10100111",
210 => "10101000", 211 => "10101001", 212 to 213=> "10101010", 214 => "10101011",
215 => "10101100", 216 => "10101101", 217 to 218=> "10101110", 219 => "10101111",
220 => "10110000", 221 => "10110001", 222 to 223=> "10110010", 224 => "10110011",
225 => "10110100", 226 => "10110101", 227 to 228=> "10110110", 229 => "10110111",
230 => "10111000", 231 => "10111001", 232 to 233=> "10111010", 234 => "10111011",
235 => "10111100", 236 => "10111101", 237 to 238=> "10111110", 239 => "10111111",
240 => "11000000", 241 => "11000001", 242 to 243=> "11000010", 244 => "11000011",
245 => "11000100", 246 => "11000101", 247 to 248=> "11000110", 249 => "11000111",
250 => "11001000", 251 => "11001001", 252 to 253=> "11001010", 254 => "11001011",
255 => "11001100" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_g8j is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_g8j is
component Loop_loop_height_g8j_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_g8j_rom_U : component Loop_loop_height_g8j_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
9e1af122fd79b0ba83061888b8d85299
| 0.548235 | 3.61206 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
Pipelined_CellLite_Unit.vhd
| 1 | 3,577 |
-------------------------------------------------------------------------------
--
-- Title : Pipelined_CellLite_Unit
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\Pipelined_CellLite_Unit.vhd
-- Generated : Thu Dec 8 14:09:43 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {Pipelined_CellLite_Unit} architecture {structural}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity Pipelined_CellLite_Unit is
port(
full_instruction_data : in std_logic_vector(255 downto 0);
instruction_load_en : in std_logic;
clk : in std_logic;
reg_port0,reg_port1,reg_port2,reg_port3,reg_port4,reg_port5,reg_port6,reg_port7,reg_port8,
reg_port9,reg_port10,reg_port11,reg_port12,reg_port13,reg_port14,reg_port15: out std_logic_vector(63 downto 0)
);
end Pipelined_CellLite_Unit;
--}} End of automatically maintained section
architecture structural of Pipelined_CellLite_Unit is
signal instruction_if_phase, instruction_id_phase : std_logic_vector(15 downto 0);
signal rs1_id_phase, rs2_id_phase : std_logic_vector(63 downto 0);
signal op_code_id_phase, rd_addr_id_phase : std_logic_vector(3 downto 0);
signal rs1_exe_phase, rs2_exe_phase : std_logic_vector(63 downto 0);
signal op_code_exe_phase, rd_address_exe_phase : std_logic_vector(3 downto 0);
signal writeback : std_logic;
signal rd : std_logic_vector(63 downto 0);
signal rd_addr : std_logic_vector(3 downto 0);
begin
instruction_buffer : entity InstructionBuffer
port map(instruction_din => full_instruction_data, instruction_load_enable => instruction_load_en,
clk => clk, instruction_dout => instruction_if_phase);
IF_ID : entity IF_ID_Register
port map(instruction_in => instruction_if_phase, instruction_out => instruction_id_phase, clk => clk);
register_file : entity registerfile_toplevel
port map(instruction => instruction_id_phase, rd_address_writeback => rd_addr,
rd => rd, writeback => writeback, rs1 => rs1_id_phase,
rs2 => rs2_id_phase, op_code => op_code_id_phase, rd_address => rd_addr_id_phase,
reg_port0 => reg_port0,reg_port1 => reg_port1,reg_port2 => reg_port2,reg_port3 => reg_port3,
reg_port4 => reg_port4,reg_port5 => reg_port5,reg_port6 => reg_port6,reg_port7 => reg_port7,
reg_port8 => reg_port8,reg_port9 => reg_port9,reg_port10 => reg_port10,reg_port11 => reg_port11,
reg_port12 => reg_port12, reg_port13 => reg_port13, reg_port14 => reg_port14,reg_port15 => reg_port15,
clk => clk);
ID_EXE : entity ID_EXE_Register
port map(rs1_in => rs1_id_phase, rs2_in => rs2_id_phase,
op_code_in => op_code_id_phase, rd_address_in => rd_addr_id_phase, rs1_out => rs1_exe_phase,
rs2_out => rs2_exe_phase, op_code_out => op_code_exe_phase, rd_address_out => rd_address_exe_phase,
clk => clk);
multimedia_ALU : entity ALU
port map(rs1 => rs1_exe_phase, rs2 => rs2_exe_phase, alu_op => op_code_exe_phase,
rd_address_in => rd_address_exe_phase, writeback => writeback, rd => rd,
rd_address_writeback => rd_addr);
end structural;
|
apache-2.0
|
0d4e25e6af32b0fd72eac20874d1c6a2
| 0.619234 | 3.140474 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/Transmit_Path.vhd
| 2 | 25,089 |
-------------------------------------------------------------------------------
--
-- File: Transmit_Path.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is responsible for buffering the data transfered through DMA,
-- implementing the TX endpoints and sending the packet data on request from
-- the protocol engine state machine request
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
use ieee.numeric_std.all;
use IEEE.std_logic_signed.all;
entity Transmit_Path is
generic (
C_S_AXI_DATA_WIDTH : integer := 3;
MAX_NR_ENDP : integer := 1
);
PORT (
Axi_Resetn : IN STD_LOGIC;
Axi_Clk : IN STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
u_Resetn : IN STD_LOGIC;
u_PE_Endpt_Nr: in std_logic_vector(4 downto 0);
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0); --!!!!! bits need to be synchronised
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
u_Send_Packet : in STD_LOGIC;
u_Tx_Data_En : in STD_LOGIC;
u_Tx_Data : out STD_LOGIC_VECTOR(7 downto 0);
u_Send_Packet_Last : out STD_LOGIC;
u_Endpt_Ready : out STD_LOGIC;
latency_comp_in : in STD_LOGIC;
latency_comp_out : out STD_LOGIC;
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC
);
end Transmit_Path;
architecture Behavioral of Transmit_Path is
COMPONENT blk_mem_gen_1
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT TX_FIFO
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC
);
END COMPONENT;
type a_BRAM_Base_AddrA_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(11 downto 0);
constant a_BRAM_Base_AddrA : a_BRAM_Base_AddrA_Array := ("010000000000","000000000000");
constant u_BRAM_Base_AddrB : a_BRAM_Base_AddrA_Array := ("010000000000","000000000000");
type a_BRAM_Load_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(11 downto 0);
signal a_BRAM_Load_Counter_Array : a_BRAM_Load_Array;
type u_Cnt_Load_Bram_oData_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(11 downto 0);
signal u_Cnt_Load_Bram_oData : u_Cnt_Load_Bram_oData_Array;
type a_Cnt_Load_Bram_iPush_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal a_Cnt_Load_Bram_iPush : a_Cnt_Load_Bram_iPush_Array;
type a_Cnt_Load_Bram_iRdy_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal a_Cnt_Load_Bram_iRdy : a_Cnt_Load_Bram_iRdy_Array;
type u_Cnt_Load_Bram_oValid_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal u_Cnt_Load_Bram_oValid : u_Cnt_Load_Bram_oValid_Array;
type aReset_Handshake_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal aReset_Handshake, aReset_Handshake_Loc : u_Cnt_Load_Bram_oValid_Array;
signal u_Resetn_N : STD_LOGIC;
signal a_BRAM_EnA : STD_LOGIC;
signal a_BRAM_WeA : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal a_BRAM_AddrA, a_BRAM_AddrA_q : STD_LOGIC_VECTOR(11 DOWNTO 0);
signal a_BRAM_Dina : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal u_BRAM_Enb, u_BRAM_Enb_Loc : STD_LOGIC;
signal u_BRAM_AddrB : STD_LOGIC_VECTOR(11 DOWNTO 0);
signal u_BRAM_DoutB, u_BRAM_DoutB_q : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal a_Tx_Fifo_M_Axis_Tvalid : STD_LOGIC;
signal a_Tx_Fifo_M_Axis_Tready : STD_LOGIC;
signal a_Tx_Fifo_M_Axis_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Tx_Fifo_M_Axis_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_Tx_Fifo_M_Axis_Tlast : STD_LOGIC;
signal a_Tx_Fifo_M_Load_Last : STD_LOGIC;
--signal a_Tx_Fifo_M_Axis_Tuser : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_Byte_Index : integer range 0 to C_S_AXI_DATA_WIDTH;
--signal a_Byte_Index_Rst : STD_LOGIC;
signal a_Byte_Index_Inc : STD_LOGIC;
signal a_Cnt_Load_Bram : STD_LOGIC_VECTOR(11 DOWNTO 0);
signal a_Cnt_Load_Bram_Rst : STD_LOGIC;
signal u_Cnt_Read_Bram : STD_LOGIC_VECTOR(11 DOWNTO 0);
signal u_Cnt_Read_Bram_Rst : STD_LOGIC;
signal a_DMA_Transfer_Start, a_DMA_Transfer_Start_Pulse, a_DMA_Transfer_Start_q : STD_LOGIC;
signal a_Tx_Fifo_M_Axis_Tlast_q, a_Tx_Fifo_M_Axis_Tlast_NPulse, a_Tx_Fifo_M_Axis_Tlast_NPulse_q : STD_LOGIC;
signal a_Tx_Fifo_S_Axis_Tlast_q, a_Tx_Fifo_S_Axis_Tlast_NPulse : STD_LOGIC;
signal a_Load_BRAM_Start : STD_LOGIC;
signal u_Send_Packet_Pulse, u_Send_Packet_PulseN, u_Send_Packet_q, u_Send_Packet_Pulse_q : STD_LOGIC;
signal u_Tx_Data_En_q : STD_LOGIC;
signal a_Arb_Endpt_Nr_Int, u_PE_Endpt_Nr_Int : integer range 0 to MAX_NR_ENDP;
--attribute mark_debug : string;
--attribute keep : string;
--attribute mark_debug of a_Tx_Fifo_S_Axis_Tvalid : signal is "true";
--attribute keep of a_Tx_Fifo_S_Axis_Tvalid : signal is "true";
--attribute mark_debug of a_Tx_Fifo_S_Axis_Tdata : signal is "true";
--attribute keep of a_Tx_Fifo_S_Axis_Tdata : signal is "true";
--attribute mark_debug of a_Tx_Fifo_S_Axis_Tready : signal is "true";
--attribute keep of a_Tx_Fifo_S_Axis_Tready : signal is "true";
--attribute mark_debug of a_Tx_Fifo_S_Axis_Tlast : signal is "true";
--attribute keep of a_Tx_Fifo_S_Axis_Tlast : signal is "true";
--attribute mark_debug of a_Tx_Fifo_M_Axis_Tdata : signal is "true";
--attribute keep of a_Tx_Fifo_M_Axis_Tdata : signal is "true";
--attribute mark_debug of a_Tx_Fifo_M_Axis_Tvalid : signal is "true";
--attribute keep of a_Tx_Fifo_M_Axis_Tvalid : signal is "true";
--attribute mark_debug of a_Tx_Fifo_M_Axis_Tkeep : signal is "true";
--attribute keep of a_Tx_Fifo_M_Axis_Tkeep : signal is "true";
--attribute mark_debug of a_Tx_Fifo_M_Axis_Tlast : signal is "true";
--attribute keep of a_Tx_Fifo_M_Axis_Tlast : signal is "true";
--attribute mark_debug of a_Tx_Fifo_M_Axis_Tready : signal is "true";
--attribute keep of a_Tx_Fifo_M_Axis_Tready : signal is "true";
--attribute mark_debug of a_Byte_Index : signal is "true";
--attribute keep of a_Byte_Index : signal is "true";
--attribute mark_debug of a_BRAM_WeA : signal is "true";
--attribute keep of a_BRAM_WeA : signal is "true";
--attribute mark_debug of a_BRAM_AddrA_q : signal is "true";
--attribute keep of a_BRAM_AddrA_q : signal is "true";
--attribute mark_debug of a_BRAM_Dina : signal is "true";
--attribute keep of a_BRAM_Dina : signal is "true";
--attribute mark_debug of u_BRAM_Enb : signal is "true";
--attribute keep of u_BRAM_Enb : signal is "true";
--attribute mark_debug of u_BRAM_AddrB : signal is "true";
--attribute keep of u_BRAM_AddrB : signal is "true";
--attribute mark_debug of u_BRAM_DoutB : signal is "true";
--attribute keep of u_BRAM_DoutB : signal is "true";
--attribute mark_debug of u_BRAM_DoutB_q : signal is "true";
--attribute keep of u_BRAM_DoutB_q : signal is "true";
--attribute mark_debug of u_Send_Packet_Last : signal is "true";
--attribute keep of u_Send_Packet_Last : signal is "true";
--attribute mark_debug of u_Cnt_Read_Bram : signal is "true";
--attribute keep of u_Cnt_Read_Bram : signal is "true";
--attribute mark_debug of a_Tx_Fifo_M_Load_Last : signal is "true";
--attribute keep of a_Tx_Fifo_M_Load_Last : signal is "true";
--attribute mark_debug of a_Arb_Endpt_Nr_Int : signal is "true";
--attribute keep of a_Arb_Endpt_Nr_Int : signal is "true";
--attribute mark_debug of u_PE_Endpt_Nr_Int : signal is "true";
--attribute keep of u_PE_Endpt_Nr_Int : signal is "true";
--attribute mark_debug of a_Tx_Fifo_S_Axis_Tlast_NPulse : signal is "true";
--attribute keep of a_Tx_Fifo_S_Axis_Tlast_NPulse : signal is "true";
--attribute mark_debug of a_Cnt_Load_Bram : signal is "true";
--attribute keep of a_Cnt_Load_Bram : signal is "true";
--attribute mark_debug of u_Send_Packet_Pulse_q : signal is "true";
--attribute keep of u_Send_Packet_Pulse_q : signal is "true";
--attribute mark_debug of a_BRAM_Load_Counter_Array : signal is "true";
--attribute keep of a_BRAM_Load_Counter_Array : signal is "true";
--attribute mark_debug of u_Cnt_Load_Bram_oData : signal is "true";
--attribute keep of u_Cnt_Load_Bram_oData : signal is "true";
--attribute mark_debug of u_Cnt_Load_Bram_oValid : signal is "true";
--attribute keep of u_Cnt_Load_Bram_oValid : signal is "true";
--attribute mark_debug of a_Cnt_Load_Bram_iPush : signal is "true";
--attribute keep of a_Cnt_Load_Bram_iPush : signal is "true";
--attribute mark_debug of a_Cnt_Load_Bram_iRdy : signal is "true";
--attribute keep of a_Cnt_Load_Bram_iRdy : signal is "true";
--attribute mark_debug of aReset_Handshake : signal is "true";
--attribute keep of aReset_Handshake : signal is "true";
--attribute mark_debug of a_Tx_Fifo_M_Axis_Tlast_NPulse : signal is "true";
--attribute keep of a_Tx_Fifo_M_Axis_Tlast_NPulse : signal is "true";
--attribute mark_debug of u_Send_Packet_PulseN : signal is "true";
--attribute keep of u_Send_Packet_PulseN : signal is "true";
--attribute mark_debug of u_Send_Packet : signal is "true";
--attribute keep of u_Send_Packet : signal is "true";
begin
u_Resetn_N <= not u_Resetn;
a_Arb_Endpt_Nr_Int <= to_integer (unsigned (a_Arb_Endpt_Nr(4 downto 1)));
u_PE_Endpt_Nr_Int <= to_integer (unsigned (u_PE_Endpt_Nr(4 downto 1)));
a_BRAM_Dina <= a_Tx_Fifo_M_Axis_Tdata((a_Byte_Index *8 + 7) downto a_Byte_Index * 8);
u_Endpt_Ready <= u_Cnt_Load_Bram_oValid(u_PE_Endpt_Nr_Int);
TX_FIFO_INST: TX_FIFO
PORT MAP (
s_aclk => a_Tx_Fifo_S_Aclk,
s_aresetn => Tx_Fifo_S_Aresetn,
s_axis_tvalid => a_Tx_Fifo_S_Axis_Tvalid,
s_axis_tready => a_Tx_Fifo_S_Axis_Tready,
s_axis_tdata => a_Tx_Fifo_S_Axis_Tdata,
s_axis_tkeep => a_Tx_Fifo_S_Axis_Tkeep,
s_axis_tlast => a_Tx_Fifo_S_Axis_Tlast,
s_axis_tuser => a_Tx_Fifo_S_Axis_Tuser,
m_axis_tvalid => a_Tx_Fifo_M_Axis_Tvalid,
m_axis_tready => a_Tx_Fifo_M_Axis_Tready,
m_axis_tdata => a_Tx_Fifo_M_Axis_Tdata,
m_axis_tkeep => a_Tx_Fifo_M_Axis_Tkeep,
m_axis_tlast => a_Tx_Fifo_M_Axis_Tlast,
m_axis_tuser => open,
axis_overflow => tx_fifo_axis_overflow,
axis_underflow => tx_fifo_axis_underflow
);
BRAM: blk_mem_gen_1
PORT MAP (
clka => Axi_Clk,
ena => a_BRAM_EnA,
wea => a_BRAM_WeA,
addra => a_BRAM_AddrA_q,
dina => a_BRAM_Dina,
clkb => Ulpi_Clk,
enb => u_BRAM_Enb,
addrb => u_BRAM_AddrB,
doutb => u_BRAM_DoutB
);
u_BRAM_Enb <= u_BRAM_Enb_Loc or u_Send_Packet_Pulse_q;
a_BRAM_EnA <= '1';
BYTE_INDEX_PROC: process(Axi_Clk)
begin
if (Axi_Clk 'event and Axi_Clk = '1') then
if ((Axi_Resetn = '0') or (a_Tx_Fifo_M_Axis_Tlast_NPulse_q = '1')) then
a_Byte_Index <= 0;
elsif (a_Byte_Index_Inc = '1') then
if (a_Byte_Index = (C_S_AXI_DATA_WIDTH)) then
a_Byte_Index <= 0;
else
a_Byte_Index <= a_Byte_Index + 1;
end if;
end if;
end if;
end process;
BRAM_WEA_PROC: process(Axi_Clk)
begin
if (Axi_Clk 'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_BRAM_WeA <= "0";
else
if ((a_Tx_Fifo_M_Axis_Tvalid = '1') and (a_Tx_Fifo_M_Axis_Tkeep(a_Byte_Index) = '1')and (a_Load_BRAM_Start = '1')) then
a_BRAM_WeA <= "1";
else
a_BRAM_WeA <= "0";
end if;
end if;
end if;
end process;
BRAM_READY_PROC: process(Axi_Clk)
begin
if (Axi_Clk 'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Tx_Fifo_M_Axis_Tready <= '0';
else
if (a_Byte_Index = (C_S_AXI_DATA_WIDTH-1) ) then --if ((a_Byte_Index = (C_S_AXI_DATA_WIDTH-1)) or (a_Tx_Fifo_S_Axis_Tlast_NPulse = '1')) then
a_Tx_Fifo_M_Axis_Tready <= '1';
else
a_Tx_Fifo_M_Axis_Tready <= '0';
end if;
end if;
end if;
end process;
BYTE_INDEX_INC_PROC: process(Axi_Clk)
begin
if (Axi_Clk 'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Byte_Index_Inc <= '0';
else
if ((a_Tx_Fifo_M_Axis_Tvalid = '1') and (a_Load_BRAM_Start = '1')) then
a_Byte_Index_Inc <= '1';
else
a_Byte_Index_Inc <= '0';
end if;
end if;
end if;
end process;
LOAD_BRAM_START_PROC: process(Axi_Clk)
begin
if (Axi_Clk 'event and Axi_Clk = '1') then
if ((Axi_Resetn = '0') or (a_Tx_Fifo_M_Axis_Tlast_NPulse = '1')) then
a_Load_BRAM_Start <= '0';
else
if (a_Tx_Fifo_S_Axis_Tlast_NPulse = '1') then
a_Load_BRAM_Start <= '1';
end if;
end if;
end if;
end process;
BRAM_ADDRESSA_PROC: process(Axi_Clk)
begin
if (Axi_Clk 'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_BRAM_AddrA <= (others => '0');
a_BRAM_AddrA_q <= (others => '0');
else
a_BRAM_AddrA_q <= a_BRAM_AddrA;
if (a_DMA_Transfer_Start_Pulse = '1') then
a_BRAM_AddrA <= a_BRAM_Base_AddrA(a_Arb_Endpt_Nr_Int);
elsif ((a_Tx_Fifo_M_Axis_Tvalid = '1') and (a_Tx_Fifo_M_Axis_Tkeep(a_Byte_Index) = '1') and (a_Load_BRAM_Start = '1')) then
a_BRAM_AddrA <= std_logic_vector( to_unsigned((to_integer(unsigned(a_BRAM_AddrA)) + 1),12) );
end if;
end if;
end if;
end process;
DMA_TRANSFER_START_PROC: process(Axi_Clk)
begin
if (Axi_Clk 'event and Axi_Clk = '1') then
if (Axi_Resetn = '0' or a_Tx_Fifo_M_Axis_Tlast_q = '1') then
a_DMA_Transfer_Start <= '0';
elsif (a_Tx_Fifo_S_Axis_Tvalid = '1') then
a_DMA_Transfer_Start <= '1';
end if;
end if;
end process;
DMA_TRANSFER_START_PULSE_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_DMA_Transfer_Start_Pulse <= '0';
a_DMA_Transfer_Start_q <= '0';
else
a_DMA_Transfer_Start_q <= a_DMA_Transfer_Start;
a_DMA_Transfer_Start_Pulse <= a_DMA_Transfer_Start and (not a_DMA_Transfer_Start_q);
end if;
end if;
end process;
a_Tx_Fifo_M_Load_Last <= '1' when ((a_Tx_Fifo_M_Axis_Tlast = '1') and (a_Byte_Index = 3)) else '0';
M_LAST_NPULSE_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Tx_Fifo_M_Axis_Tlast_NPulse <= '0';
a_Tx_Fifo_M_Axis_Tlast_NPulse_q <= '0';
a_Tx_Fifo_M_Axis_Tlast_q <= '0';
a_Cnt_Load_Bram_Rst <= '0';
else
a_Tx_Fifo_M_Axis_Tlast_q <= a_Tx_Fifo_M_Load_Last;
a_Tx_Fifo_M_Axis_Tlast_NPulse <= a_Tx_Fifo_M_Load_Last and (not a_Tx_Fifo_M_Axis_Tlast_q);
a_Cnt_Load_Bram_Rst <= a_Tx_Fifo_M_Axis_Tlast_NPulse_q;
a_Tx_Fifo_M_Axis_Tlast_NPulse_q <= a_Tx_Fifo_M_Axis_Tlast_NPulse;
end if;
end if;
end process;
S_LAST_NPULSE_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Tx_Fifo_S_Axis_Tlast_NPulse <= '0';
a_Tx_Fifo_s_Axis_Tlast_q <= '0';
else
a_Tx_Fifo_S_Axis_Tlast_q <= a_Tx_Fifo_S_Axis_Tlast;
a_Tx_Fifo_S_Axis_Tlast_NPulse <= (not a_Tx_Fifo_S_Axis_Tlast) and a_Tx_Fifo_S_Axis_Tlast_q;
end if;
end if;
end process;
BRAM_LOAD_COUNTER_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Axi_Clk' event and Axi_Clk = '1') then
if ((a_Cnt_Load_Bram_Rst = '1') or (Axi_Resetn = '0')) then
a_Cnt_Load_Bram <= (others => '0');
elsif (a_BRAM_WeA = "1") then
a_Cnt_Load_Bram <= a_Cnt_Load_Bram + '1';
end if;
end if;
end process;
BRAM_LOAD_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Axi_Clk' event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_BRAM_Load_Counter_Array <= (others => (others => '0'));
elsif (a_Tx_Fifo_M_Axis_Tlast_NPulse_q = '1') then
a_BRAM_Load_Counter_Array(a_Arb_Endpt_Nr_Int) <= (a_Cnt_Load_Bram - '1');
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
TDATA_PROC: process(u_Tx_Data_En, u_Tx_Data_En_q, u_BRAM_DoutB, u_BRAM_DoutB_q)
begin
if (u_Tx_Data_En = '0') then
u_Tx_Data <= u_BRAM_DoutB_q;
else
u_Tx_Data <= u_BRAM_DoutB;
end if;
end process;
REG_AXIS_TDATA_PROC: process(Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (u_Resetn = '0') then
u_BRAM_DoutB_q <= (others => '0');
latency_comp_out <= '0';
else
latency_comp_out <= latency_comp_in;
if((u_BRAM_Enb = '1') or (u_Cnt_Read_Bram = u_Cnt_Load_Bram_oData(u_PE_Endpt_Nr_Int)) or (u_Send_Packet_Pulse_q = '1')) then
u_BRAM_DoutB_q <= u_BRAM_DoutB;
end if;
end if;
end if;
end process;
SEND_PACKET_PULSE_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (u_Resetn = '0') then
u_Send_Packet_Pulse <= '0';
u_Send_Packet_PulseN <= '0';
u_Send_Packet_q <= '0';
u_Send_Packet_Pulse_q <= '0';
else
u_Send_Packet_q <= u_Send_Packet;
u_Send_Packet_Pulse <= u_Send_Packet and (not u_Send_Packet_q);
u_Send_Packet_PulseN <= (not u_Send_Packet) and u_Send_Packet_q;
u_Send_Packet_Pulse_q <= u_Send_Packet_Pulse;
end if;
end if;
end process;
DELAY_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (u_Resetn = '0') then
u_Tx_Data_En_q <= '0';
else
u_Tx_Data_En_q <= u_Tx_Data_En;
end if;
end if;
end process;
ENB_PROC: process (u_Send_Packet, u_Tx_Data_En, u_Tx_Data_En_q)
begin
--if (Axi_Clk'event and Axi_Clk = '1') then
if (u_Send_Packet = '1') then
if (u_Tx_Data_En = '1') then
u_BRAM_Enb_Loc <= '1';
--elsif ((u_Tx_Data_En = '0') and (u_Tx_Data_En_q = '1')) then
-- u_BRAM_Enb_Loc <= '1';
else
u_BRAM_Enb_Loc <= '0';
end if;
else
u_BRAM_Enb_Loc <= '0';
end if;
--end if;
end process;
BRAM_ADDRESSB_PROC: process(Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (u_Resetn = '0') then
u_BRAM_AddrB <= (others => '0');
else
if (u_Send_Packet_Pulse = '1') then
u_BRAM_AddrB <= u_BRAM_Base_AddrB(u_PE_Endpt_Nr_Int);
elsif ((u_Send_Packet = '1') and (u_BRAM_Enb = '1')) then
u_BRAM_AddrB <= std_logic_vector( to_unsigned((to_integer(unsigned(u_BRAM_AddrB)) + 1),12) );
end if;
end if;
end if;
end process;
u_Cnt_Read_Bram_Rst <= u_Send_Packet_Pulse;
BRAM_READ_COUNTER_PROC: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if ((u_Cnt_Read_Bram_Rst = '1') or (u_Resetn = '0')) then
u_Cnt_Read_Bram <= (others => '0');
elsif (u_BRAM_Enb = '1') then
u_Cnt_Read_Bram <= u_Cnt_Read_Bram + '1';
end if;
end if;
end process;
LAST_PROC: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Resetn = '0') then
u_Send_Packet_Last <= '0';
elsif((u_Send_Packet = '1') and (u_Tx_Data_En = '1')) then
if ((u_Cnt_Load_Bram_oData(u_PE_Endpt_Nr_Int) - '1') = u_Cnt_Read_Bram) then-- std_logic_vector( to_unsigned((to_integer(unsigned(u_Cnt_Read_Bram)) - 3),12))) then
u_Send_Packet_Last <= '1';
else
u_Send_Packet_Last <= '0';
end if;
elsif ((u_Send_Packet_Pulse = '1') and (u_Cnt_Load_Bram_oData(u_PE_Endpt_Nr_Int) = "0000000000000001")) then
u_Send_Packet_Last <= '1';
else
u_Send_Packet_Last <= '0';
end if;
end if;
end process;
-- u_Cnt_Load_Bram_oValid(u_PE_Endpt_Nr_Int)
MULTIPLE_HANDSHAKE : for i in 0 to MAX_NR_ENDP generate
Inst_HandshakeData_Count: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 12)
PORT MAP(
InClk => Axi_Clk,
OutClk => Ulpi_Clk,
iData => a_BRAM_Load_Counter_Array(i),
oData => u_Cnt_Load_Bram_oData(i),
iPush => a_Cnt_Load_Bram_iPush(i),
iRdy => a_Cnt_Load_Bram_iRdy(i),
oAck => u_Cnt_Load_Bram_oValid(i),
oValid => u_Cnt_Load_Bram_oValid(i),
aReset => aReset_Handshake(i)
);
end generate;
--aReset_Handshake <= (u_Resetn_N or (u_Send_Packet_PulseN));
ARESETN_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Resetn = '0') then
aReset_Handshake <= (others => ('1'));
else
for index in 0 to MAX_NR_ENDP loop
aReset_Handshake(index) <= aReset_Handshake_Loc(index) or u_Resetn_N;
end loop;
end if;
end if;
end process;
ARESETN_LOC_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Resetn = '0') then
aReset_Handshake_Loc <= (others => ('0'));
else
aReset_Handshake_Loc(u_PE_Endpt_Nr_Int) <= u_Send_Packet_PulseN;
end if;
end if;
end process;
IPUSH_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Axi_Clk' event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Cnt_Load_Bram_iPush <= (others => ('0'));
else
if ((a_Cnt_Load_Bram_iRdy(a_Arb_Endpt_Nr_Int) = '1') and (a_Tx_Fifo_M_Axis_Tlast_NPulse_q = '1'))then
a_Cnt_Load_Bram_iPush(a_Arb_Endpt_Nr_Int) <= '1';
else
a_Cnt_Load_Bram_iPush(a_Arb_Endpt_Nr_Int) <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
236833c9c212c0722763ecb72babd627
| 0.606481 | 2.962801 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_pro.vhd
| 1 | 51,522 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Loop_loop_height_pro is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_rows_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_loc_empty_n : IN STD_LOGIC;
p_rows_assign_cast_loc_read : OUT STD_LOGIC;
p_cols_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_loc_empty_n : IN STD_LOGIC;
p_cols_assign_cast_loc_read : OUT STD_LOGIC;
img2_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_0_V_full_n : IN STD_LOGIC;
img2_data_stream_0_V_write : OUT STD_LOGIC;
img2_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_1_V_full_n : IN STD_LOGIC;
img2_data_stream_1_V_write : OUT STD_LOGIC;
img2_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_2_V_full_n : IN STD_LOGIC;
img2_data_stream_2_V_write : OUT STD_LOGIC;
img1_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_0_V_empty_n : IN STD_LOGIC;
img1_data_stream_0_V_read : OUT STD_LOGIC;
img1_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_1_V_empty_n : IN STD_LOGIC;
img1_data_stream_1_V_read : OUT STD_LOGIC;
img1_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_2_V_empty_n : IN STD_LOGIC;
img1_data_stream_2_V_read : OUT STD_LOGIC;
sat_dout : IN STD_LOGIC_VECTOR (7 downto 0);
sat_empty_n : IN STD_LOGIC;
sat_read : OUT STD_LOGIC );
end;
architecture behav of Loop_loop_height_pro is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv8_7 : STD_LOGIC_VECTOR (7 downto 0) := "00000111";
constant ap_const_lv8_6 : STD_LOGIC_VECTOR (7 downto 0) := "00000110";
constant ap_const_lv8_5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant ap_const_lv8_4 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal lut_s_1_2_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_1_2_ce0 : STD_LOGIC;
signal lut_s_1_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_n0_2_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_n0_2_ce0 : STD_LOGIC;
signal lut_s_n0_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_0_2_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_0_2_ce0 : STD_LOGIC;
signal lut_s_0_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_0_4_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_0_4_ce0 : STD_LOGIC;
signal lut_s_0_4_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_0_6_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_0_6_ce0 : STD_LOGIC;
signal lut_s_0_6_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_0_8_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_0_8_ce0 : STD_LOGIC;
signal lut_s_0_8_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_1_0_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut_s_1_0_ce0 : STD_LOGIC;
signal lut_s_1_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal p_rows_assign_cast_loc_blk_n : STD_LOGIC;
signal p_cols_assign_cast_loc_blk_n : STD_LOGIC;
signal img2_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal exitcond_i_i_i_reg_478 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 : STD_LOGIC_VECTOR (0 downto 0);
signal img2_data_stream_1_V_blk_n : STD_LOGIC;
signal img2_data_stream_2_V_blk_n : STD_LOGIC;
signal img1_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal img1_data_stream_1_V_blk_n : STD_LOGIC;
signal img1_data_stream_2_V_blk_n : STD_LOGIC;
signal sat_blk_n : STD_LOGIC;
signal t_V_2_reg_252 : STD_LOGIC_VECTOR (10 downto 0);
signal p_rows_assign_cast_lo_reg_406 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_block_state1 : BOOLEAN;
signal p_cols_assign_cast_lo_reg_411 : STD_LOGIC_VECTOR (11 downto 0);
signal sel_tmp_fu_263_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp_reg_416 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_269_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_reg_421 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_fu_275_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_reg_426 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_fu_281_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_reg_432 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_fu_287_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_reg_437 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_reg_443 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_fu_299_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_reg_448 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_fu_305_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_454 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal or_cond2_fu_313_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_reg_459 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond3_fu_317_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond3_reg_464 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond51_i_i_i_fu_327_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal i_V_fu_332_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_473 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_i_i_i_fu_342_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state4_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_i_i_i_reg_478 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_347_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_reg_487 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_reg_487 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_reg_487 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_7_reg_492 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_7_reg_492 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_7_reg_492 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_9_reg_497 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_9_reg_497 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_2_reg_538 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_3_reg_543 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_6_reg_548 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_7_reg_553 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel1_fu_363_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel1_reg_558 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel3_fu_370_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel3_reg_563 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state4 : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal t_V_reg_241 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal tmp_5_i_i_fu_353_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal or_cond1_fu_309_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal t_V_cast_i_i_fu_323_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal t_V_1_cast_i_i_fu_338_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal newSel_fu_376_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel2_fu_381_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel4_fu_386_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel5_fu_392_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component Loop_loop_height_fYi IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_g8j IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_hbi IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_ibs IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_jbC IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_kbM IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_lbW IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
lut_s_1_2_U : component Loop_loop_height_fYi
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut_s_1_2_address0,
ce0 => lut_s_1_2_ce0,
q0 => lut_s_1_2_q0);
lut_s_n0_2_U : component Loop_loop_height_g8j
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut_s_n0_2_address0,
ce0 => lut_s_n0_2_ce0,
q0 => lut_s_n0_2_q0);
lut_s_0_2_U : component Loop_loop_height_hbi
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut_s_0_2_address0,
ce0 => lut_s_0_2_ce0,
q0 => lut_s_0_2_q0);
lut_s_0_4_U : component Loop_loop_height_ibs
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut_s_0_4_address0,
ce0 => lut_s_0_4_ce0,
q0 => lut_s_0_4_q0);
lut_s_0_6_U : component Loop_loop_height_jbC
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut_s_0_6_address0,
ce0 => lut_s_0_6_ce0,
q0 => lut_s_0_6_q0);
lut_s_0_8_U : component Loop_loop_height_kbM
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut_s_0_8_address0,
ce0 => lut_s_0_8_ce0,
q0 => lut_s_0_8_q0);
lut_s_1_0_U : component Loop_loop_height_lbW
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut_s_1_0_address0,
ce0 => lut_s_1_0_ce0,
q0 => lut_s_1_0_q0);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond51_i_i_i_fu_327_p2 = ap_const_lv1_1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state4) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond51_i_i_i_fu_327_p2 = ap_const_lv1_0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state4)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state4);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond51_i_i_i_fu_327_p2 = ap_const_lv1_0))) then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
t_V_2_reg_252_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_fu_342_p2 = ap_const_lv1_0))) then
t_V_2_reg_252 <= j_V_fu_347_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond51_i_i_i_fu_327_p2 = ap_const_lv1_0))) then
t_V_2_reg_252 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_241_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
t_V_reg_241 <= i_V_reg_473;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
t_V_reg_241 <= ap_const_lv11_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_reg_pp0_iter1_exitcond_i_i_i_reg_478 <= exitcond_i_i_i_reg_478;
exitcond_i_i_i_reg_478 <= exitcond_i_i_i_fu_342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 <= ap_reg_pp0_iter1_exitcond_i_i_i_reg_478;
ap_reg_pp0_iter2_tmp_7_reg_492 <= tmp_7_reg_492;
ap_reg_pp0_iter2_tmp_9_reg_497 <= tmp_9_reg_497;
ap_reg_pp0_iter2_tmp_reg_487 <= tmp_reg_487;
ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 <= ap_reg_pp0_iter2_exitcond_i_i_i_reg_478;
ap_reg_pp0_iter3_tmp_7_reg_492 <= ap_reg_pp0_iter2_tmp_7_reg_492;
ap_reg_pp0_iter3_tmp_reg_487 <= ap_reg_pp0_iter2_tmp_reg_487;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond3_reg_464 = ap_const_lv1_1) and (or_cond_reg_454 = ap_const_lv1_1) and (sel_tmp3_reg_448 = ap_const_lv1_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 = ap_const_lv1_0))) then
d_val_2_2_reg_538 <= lut_s_n0_2_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond3_reg_464 = ap_const_lv1_1) and (or_cond_reg_454 = ap_const_lv1_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (sel_tmp3_reg_448 = ap_const_lv1_0))) then
d_val_2_3_reg_543 <= lut_s_0_2_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond2_reg_459 = ap_const_lv1_1) and (sel_tmp4_reg_426 = ap_const_lv1_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (or_cond3_reg_464 = ap_const_lv1_0))) then
d_val_2_6_reg_548 <= lut_s_0_8_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond2_reg_459 = ap_const_lv1_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (or_cond3_reg_464 = ap_const_lv1_0) and (sel_tmp4_reg_426 = ap_const_lv1_0))) then
d_val_2_7_reg_553 <= lut_s_1_0_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_V_reg_473 <= i_V_fu_332_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond3_reg_464 = ap_const_lv1_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (or_cond_reg_454 = ap_const_lv1_0))) then
newSel1_reg_558 <= newSel1_fu_363_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (or_cond3_reg_464 = ap_const_lv1_0) and (or_cond2_reg_459 = ap_const_lv1_0))) then
newSel3_reg_563 <= newSel3_fu_370_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
or_cond2_reg_459 <= or_cond2_fu_313_p2;
or_cond3_reg_464 <= or_cond3_fu_317_p2;
or_cond_reg_454 <= or_cond_fu_305_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((sat_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_lo_reg_411 <= p_cols_assign_cast_loc_dout;
p_rows_assign_cast_lo_reg_406 <= p_rows_assign_cast_loc_dout;
sel_tmp1_reg_443 <= sel_tmp1_fu_293_p2;
sel_tmp2_reg_421 <= sel_tmp2_fu_269_p2;
sel_tmp3_reg_448 <= sel_tmp3_fu_299_p2;
sel_tmp4_reg_426 <= sel_tmp4_fu_275_p2;
sel_tmp6_reg_432 <= sel_tmp6_fu_281_p2;
sel_tmp8_reg_437 <= sel_tmp8_fu_287_p2;
sel_tmp_reg_416 <= sel_tmp_fu_263_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0))) then
tmp_7_reg_492 <= img1_data_stream_1_V_dout;
tmp_9_reg_497 <= img1_data_stream_2_V_dout;
tmp_reg_487 <= img1_data_stream_0_V_dout;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, sat_empty_n, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, exitcond51_i_i_i_fu_327_p2, ap_CS_fsm_state3, exitcond_i_i_i_fu_342_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((sat_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond51_i_i_i_fu_327_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_i_i_i_fu_342_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_i_i_i_fu_342_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)))) then
ap_NS_fsm <= ap_ST_fsm_state9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(3);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state9 <= ap_CS_fsm(4);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter4, exitcond_i_i_i_reg_478, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((img1_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img1_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img1_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)))) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (((img2_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img2_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img2_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter4, exitcond_i_i_i_reg_478, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((img1_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img1_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img1_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)))) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (((img2_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img2_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img2_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter4, exitcond_i_i_i_reg_478, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((img1_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img1_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img1_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)))) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (((img2_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img2_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img2_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, sat_empty_n)
begin
ap_block_state1 <= ((sat_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state4_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter1_assign_proc : process(img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, exitcond_i_i_i_reg_478)
begin
ap_block_state5_pp0_stage0_iter1 <= (((img1_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img1_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img1_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0)));
end process;
ap_block_state6_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter4_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478)
begin
ap_block_state8_pp0_stage0_iter4 <= (((img2_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img2_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)) or ((img2_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0)));
end process;
ap_condition_pp0_exit_iter0_state4_assign_proc : process(exitcond_i_i_i_fu_342_p2)
begin
if ((exitcond_i_i_i_fu_342_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state4 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state4 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond51_i_i_i_fu_327_p2, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond51_i_i_i_fu_327_p2 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3)
begin
if (((ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(exitcond51_i_i_i_fu_327_p2, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond51_i_i_i_fu_327_p2 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
exitcond51_i_i_i_fu_327_p2 <= "1" when (t_V_cast_i_i_fu_323_p1 = p_rows_assign_cast_lo_reg_406) else "0";
exitcond_i_i_i_fu_342_p2 <= "1" when (t_V_1_cast_i_i_fu_338_p1 = p_cols_assign_cast_lo_reg_411) else "0";
i_V_fu_332_p2 <= std_logic_vector(unsigned(t_V_reg_241) + unsigned(ap_const_lv11_1));
img1_data_stream_0_V_blk_n_assign_proc : process(img1_data_stream_0_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_478, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img1_data_stream_0_V_blk_n <= img1_data_stream_0_V_empty_n;
else
img1_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img1_data_stream_0_V_read_assign_proc : process(exitcond_i_i_i_reg_478, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0))) then
img1_data_stream_0_V_read <= ap_const_logic_1;
else
img1_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
img1_data_stream_1_V_blk_n_assign_proc : process(img1_data_stream_1_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_478, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img1_data_stream_1_V_blk_n <= img1_data_stream_1_V_empty_n;
else
img1_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img1_data_stream_1_V_read_assign_proc : process(exitcond_i_i_i_reg_478, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0))) then
img1_data_stream_1_V_read <= ap_const_logic_1;
else
img1_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
img1_data_stream_2_V_blk_n_assign_proc : process(img1_data_stream_2_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_478, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img1_data_stream_2_V_blk_n <= img1_data_stream_2_V_empty_n;
else
img1_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img1_data_stream_2_V_read_assign_proc : process(exitcond_i_i_i_reg_478, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_478 = ap_const_lv1_0))) then
img1_data_stream_2_V_read <= ap_const_logic_1;
else
img1_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
img2_data_stream_0_V_blk_n_assign_proc : process(img2_data_stream_0_V_full_n, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478)
begin
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img2_data_stream_0_V_blk_n <= img2_data_stream_0_V_full_n;
else
img2_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img2_data_stream_0_V_din <= ap_reg_pp0_iter3_tmp_reg_487;
img2_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter4, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0))) then
img2_data_stream_0_V_write <= ap_const_logic_1;
else
img2_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img2_data_stream_1_V_blk_n_assign_proc : process(img2_data_stream_1_V_full_n, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478)
begin
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img2_data_stream_1_V_blk_n <= img2_data_stream_1_V_full_n;
else
img2_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img2_data_stream_1_V_din <= ap_reg_pp0_iter3_tmp_7_reg_492;
img2_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter4, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0))) then
img2_data_stream_1_V_write <= ap_const_logic_1;
else
img2_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img2_data_stream_2_V_blk_n_assign_proc : process(img2_data_stream_2_V_full_n, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478)
begin
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img2_data_stream_2_V_blk_n <= img2_data_stream_2_V_full_n;
else
img2_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img2_data_stream_2_V_din <=
newSel4_fu_386_p3 when (or_cond3_reg_464(0) = '1') else
newSel5_fu_392_p3;
img2_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter4, ap_reg_pp0_iter3_exitcond_i_i_i_reg_478, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 = ap_const_lv1_0))) then
img2_data_stream_2_V_write <= ap_const_logic_1;
else
img2_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_347_p2 <= std_logic_vector(unsigned(t_V_2_reg_252) + unsigned(ap_const_lv11_1));
lut_s_0_2_address0 <= tmp_5_i_i_fu_353_p1(8 - 1 downto 0);
lut_s_0_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut_s_0_2_ce0 <= ap_const_logic_1;
else
lut_s_0_2_ce0 <= ap_const_logic_0;
end if;
end process;
lut_s_0_4_address0 <= tmp_5_i_i_fu_353_p1(8 - 1 downto 0);
lut_s_0_4_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut_s_0_4_ce0 <= ap_const_logic_1;
else
lut_s_0_4_ce0 <= ap_const_logic_0;
end if;
end process;
lut_s_0_6_address0 <= tmp_5_i_i_fu_353_p1(8 - 1 downto 0);
lut_s_0_6_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut_s_0_6_ce0 <= ap_const_logic_1;
else
lut_s_0_6_ce0 <= ap_const_logic_0;
end if;
end process;
lut_s_0_8_address0 <= tmp_5_i_i_fu_353_p1(8 - 1 downto 0);
lut_s_0_8_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut_s_0_8_ce0 <= ap_const_logic_1;
else
lut_s_0_8_ce0 <= ap_const_logic_0;
end if;
end process;
lut_s_1_0_address0 <= tmp_5_i_i_fu_353_p1(8 - 1 downto 0);
lut_s_1_0_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut_s_1_0_ce0 <= ap_const_logic_1;
else
lut_s_1_0_ce0 <= ap_const_logic_0;
end if;
end process;
lut_s_1_2_address0 <= tmp_5_i_i_fu_353_p1(8 - 1 downto 0);
lut_s_1_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut_s_1_2_ce0 <= ap_const_logic_1;
else
lut_s_1_2_ce0 <= ap_const_logic_0;
end if;
end process;
lut_s_n0_2_address0 <= tmp_5_i_i_fu_353_p1(8 - 1 downto 0);
lut_s_n0_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut_s_n0_2_ce0 <= ap_const_logic_1;
else
lut_s_n0_2_ce0 <= ap_const_logic_0;
end if;
end process;
newSel1_fu_363_p3 <=
lut_s_0_4_q0 when (sel_tmp8_reg_437(0) = '1') else
lut_s_0_6_q0;
newSel2_fu_381_p3 <=
d_val_2_6_reg_548 when (sel_tmp4_reg_426(0) = '1') else
d_val_2_7_reg_553;
newSel3_fu_370_p3 <=
lut_s_1_2_q0 when (sel_tmp_reg_416(0) = '1') else
ap_reg_pp0_iter2_tmp_9_reg_497;
newSel4_fu_386_p3 <=
newSel_fu_376_p3 when (or_cond_reg_454(0) = '1') else
newSel1_reg_558;
newSel5_fu_392_p3 <=
newSel2_fu_381_p3 when (or_cond2_reg_459(0) = '1') else
newSel3_reg_563;
newSel_fu_376_p3 <=
d_val_2_2_reg_538 when (sel_tmp3_reg_448(0) = '1') else
d_val_2_3_reg_543;
or_cond1_fu_309_p2 <= (sel_tmp8_reg_437 or sel_tmp6_reg_432);
or_cond2_fu_313_p2 <= (sel_tmp4_reg_426 or sel_tmp2_reg_421);
or_cond3_fu_317_p2 <= (or_cond_fu_305_p2 or or_cond1_fu_309_p2);
or_cond_fu_305_p2 <= (sel_tmp3_reg_448 or sel_tmp1_reg_443);
p_cols_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_cols_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_blk_n <= p_cols_assign_cast_loc_empty_n;
else
p_cols_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_cols_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, sat_empty_n)
begin
if ((not(((sat_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_read <= ap_const_logic_1;
else
p_cols_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
p_rows_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_blk_n <= p_rows_assign_cast_loc_empty_n;
else
p_rows_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_rows_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, sat_empty_n)
begin
if ((not(((sat_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_read <= ap_const_logic_1;
else
p_rows_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
sat_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, sat_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
sat_blk_n <= sat_empty_n;
else
sat_blk_n <= ap_const_logic_1;
end if;
end process;
sat_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, sat_empty_n)
begin
if ((not(((sat_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
sat_read <= ap_const_logic_1;
else
sat_read <= ap_const_logic_0;
end if;
end process;
sel_tmp1_fu_293_p2 <= "1" when (sat_dout = ap_const_lv8_2) else "0";
sel_tmp2_fu_269_p2 <= "1" when (sat_dout = ap_const_lv8_6) else "0";
sel_tmp3_fu_299_p2 <= "1" when (sat_dout = ap_const_lv8_1) else "0";
sel_tmp4_fu_275_p2 <= "1" when (sat_dout = ap_const_lv8_5) else "0";
sel_tmp6_fu_281_p2 <= "1" when (sat_dout = ap_const_lv8_4) else "0";
sel_tmp8_fu_287_p2 <= "1" when (sat_dout = ap_const_lv8_3) else "0";
sel_tmp_fu_263_p2 <= "1" when (sat_dout = ap_const_lv8_7) else "0";
t_V_1_cast_i_i_fu_338_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_2_reg_252),12));
t_V_cast_i_i_fu_323_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_241),12));
tmp_5_i_i_fu_353_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_497),64));
end behav;
|
mit
|
b9af3971c299f5e75b2fb6f9cacf3cdc
| 0.598735 | 2.650309 | false | false | false | false |
pollow/Multi_Cycle_CPU
|
ipcore_dir/Mem_B/example_design/Mem_B_exdes.vhd
| 1 | 4,756 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Mem_B_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Mem_B_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Mem_B_exdes;
ARCHITECTURE xilinx OF Mem_B_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Mem_B IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Mem_B
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
fc6608930dec1b147b77c2a4058a0b4a
| 0.545837 | 4.542502 | false | false | false | false |
mtaygur/vhdl-alu-averagefilter-prng
|
avg_filter.vhd
| 1 | 840 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity avg_filter is
port ( input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
--8-bits are used to represent signed values
clk: in std_logic);
end avg_filter;
architecture Behavioral of avg_filter is
signal inputt3,inputt2,inputt1: std_logic_vector(7 downto 0):="00000000";
begin
process(clk) --samples are received at rising edge of the clock
begin
if rising_edge(clk) then
output<=std_logic_vector(to_signed( (to_integer(signed(inputt3))+to_integer(signed(inputt2))+to_integer(signed(inputt1))+to_integer(signed(input)))/4,8));
--current output is the arithmetical avg. of the current input and previous 3 inputs
inputt3<=inputt2; --shift the values accordingly
inputt2<=inputt1;
inputt1<=input;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
310dedce6c63bec3e3e8d086a4005c50
| 0.764286 | 3.243243 | false | false | false | false |
Digilent/vivado-library
|
ip/rgb2dvi/src/TMDS_Encoder.vhd
| 10 | 7,863 |
-------------------------------------------------------------------------------
--
-- File: TMDS_Encoder.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI output on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements the encoding algorithm outlined in the
-- DVI 1.0 specifications and instantiates the serializer block. The 8-bit data
-- and 3 control signals are encoded and transmitted over the data channel.
-- The sDataOut_p/n ports must connect to top-level ports.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TMDS_Encoder is
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
aRst : in std_logic; --asynchronous reset; must be reset when PixelClk/SerialClk is not within spec
--Encoded parallel data
pDataOutRaw : out std_logic_vector(9 downto 0);
--Unencoded parallel data
pDataOut : in std_logic_vector(7 downto 0);
pC0 : in std_logic;
pC1 : in std_logic;
pVde : in std_logic
);
end TMDS_Encoder;
architecture Behavioral of TMDS_Encoder is
signal pDataOut_1 : std_logic_vector(7 downto 0);
signal q_m_1, q_m_xor_1, q_m_xnor_1, q_m_2: std_logic_vector(8 downto 0);
signal control_token_2, q_out_2: std_logic_vector(9 downto 0);
signal n1d_1, n1q_m_2, n0q_m_2, n1q_m_1 : unsigned(3 downto 0); --range 0-8
signal dc_bias_2, cnt_t_3, cnt_t_2 : signed(4 downto 0) := "00000"; --range -8 - +8 + sign
signal pC0_1, pC1_1, pVde_1, pC0_2, pC1_2, pVde_2 : std_logic;
signal cond_not_balanced_2, cond_balanced_2 : std_logic;
function sum_bits(u : std_logic_vector) return unsigned is
variable sum : unsigned(3 downto 0);
begin
assert u'length < 16 report "sum_bits error";
sum := to_unsigned(0,4);
for i in u'range loop
sum := sum + unsigned(u(i downto i));
end loop;
return sum;
end sum_bits;
begin
----------------------------------------------------------------------------------
-- DVI 1.0 Specs Figure 3-5
-- Pipeline stage 1, minimise transitions
----------------------------------------------------------------------------------
Stage1: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pVde_1 <= pVde;
n1d_1 <= sum_bits(pDataOut(7 downto 0));
pDataOut_1 <= pDataOut; --insert data into the pipeline;
pC0_1 <= pC0; --insert control into the pipeline;
pC1_1 <= pC1;
end if;
end process Stage1;
----------------------------------------------------------------------------------
-- Choose one of the two encoding options based on n1d_1
----------------------------------------------------------------------------------
q_m_xor_1(0) <= pDataOut_1(0);
encode1: for i in 1 to 7 generate
q_m_xor_1(i) <= q_m_xor_1(i-1) xor pDataOut_1(i);
end generate encode1;
q_m_xor_1(8) <= '1';
q_m_xnor_1(0) <= pDataOut_1(0);
encode2: for i in 1 to 7 generate
q_m_xnor_1(i) <= q_m_xnor_1(i-1) xnor pDataOut_1(i);
end generate encode2;
q_m_xnor_1(8) <= '0';
q_m_1 <= q_m_xnor_1 when n1d_1 > 4 or (n1d_1 = 4 and pDataOut_1(0) = '0') else
q_m_xor_1;
n1q_m_1 <= sum_bits(q_m_1(7 downto 0));
----------------------------------------------------------------------------------
-- Pipeline stage 2, balance DC
----------------------------------------------------------------------------------
Stage2: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
n1q_m_2 <= n1q_m_1;
n0q_m_2 <= 8 - n1q_m_1;
q_m_2 <= q_m_1;
pC0_2 <= pC0_1;
pC1_2 <= pC1_1;
pVde_2 <= pVde_1;
end if;
end process Stage2;
cond_balanced_2 <= '1' when cnt_t_3 = 0 or n1q_m_2 = 4 else -- DC balanced output
'0';
cond_not_balanced_2 <= '1' when (cnt_t_3 > 0 and n1q_m_2 > 4) or -- too many 1's
(cnt_t_3 < 0 and n1q_m_2 < 4) else -- too many 0's
'0';
control_token_2 <= kCtlTkn0 when pC1_2 = '0' and pC0_2 = '0' else
kCtlTkn1 when pC1_2 = '0' and pC0_2 = '1' else
kCtlTkn2 when pC1_2 = '1' and pC0_2 = '0' else
kCtlTkn3;
q_out_2 <= control_token_2 when pVde_2 = '0' else --control period
not q_m_2(8) & q_m_2(8) & not q_m_2(7 downto 0) when cond_balanced_2 = '1' and q_m_2(8) = '0' else
not q_m_2(8) & q_m_2(8) & q_m_2(7 downto 0) when cond_balanced_2 = '1' and q_m_2(8) = '1' else
'1' & q_m_2(8) & not q_m_2(7 downto 0) when cond_not_balanced_2 = '1' else
'0' & q_m_2(8) & q_m_2(7 downto 0); --DC balanced
dc_bias_2 <= signed('0' & n0q_m_2) - signed('0' & n1q_m_2);
cnt_t_2 <= to_signed(0, cnt_t_2'length) when pVde_2 = '0' else --control period
cnt_t_3 + dc_bias_2 when cond_balanced_2 = '1' and q_m_2(8) = '0' else
cnt_t_3 - dc_bias_2 when cond_balanced_2 = '1' and q_m_2(8) = '1' else
cnt_t_3 + signed('0' & q_m_2(8 downto 8) & '0') + dc_bias_2 when cond_not_balanced_2 = '1' else
cnt_t_3 - signed('0' & not q_m_2(8 downto 8) & '0') - dc_bias_2;
----------------------------------------------------------------------------------
-- Pipeline stage 3, registered output
----------------------------------------------------------------------------------
Stage3: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
cnt_t_3 <= cnt_t_2;
pDataOutRaw <= q_out_2; --encoded, ready to be serialized
end if;
end process Stage3;
end Behavioral;
|
mit
|
1c5cf47624a547c72b8d196a07cdc40c
| 0.564288 | 3.468461 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/fifo_w8_d1_A.vhd
| 3 | 4,422 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d1_A_shiftReg;
architecture rtl of fifo_w8_d1_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w8_d1_A is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d1_A is
component fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d1_A_shiftReg : fifo_w8_d1_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
44e7c9c6fcf58fced7b601dd4a3c6659
| 0.523971 | 3.451991 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
registerfile_toplevel.vhd
| 1 | 3,140 |
-------------------------------------------------------------------------------
--
-- Title : registerfile_toplevel
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\registerfile_toplevel.vhd
-- Generated : Wed Dec 7 03:59:54 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {registerfile_toplevel} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity registerfile_toplevel is
port(
instruction : in std_logic_vector(15 downto 0);
rd : in std_logic_vector(63 downto 0);
rd_address_writeback : in std_logic_vector(3 downto 0);
writeback : in std_logic;
clk : in std_logic;
rs1, rs2 : out std_logic_vector(63 downto 0);
op_code : out std_logic_vector(3 downto 0);
rd_address : out std_logic_vector(3 downto 0);
reg_port0,reg_port1,reg_port2,reg_port3,reg_port4,reg_port5,reg_port6,reg_port7,reg_port8,
reg_port9,reg_port10,reg_port11,reg_port12,reg_port13,reg_port14,reg_port15: out std_logic_vector(63 downto 0)
);
end registerfile_toplevel;
--}} End of automatically maintained section
architecture behavioral of registerfile_toplevel is
signal rd_addr_sig, rs1_addr_sig, rs2_addr_sig: std_logic_vector(3 downto 0);
signal op_code_sig : std_logic_vector(3 downto 0);
signal load_enable_sig : std_logic;
signal load_addr_sig : std_logic_vector(3 downto 0);
signal load_data_v: std_logic_vector(7 downto 0);
begin
op_code <= op_code_sig;
rd_address <= rd_addr_sig;
decoder : entity regfile_decode
port map(instruction => instruction, rd_addr => rd_addr_sig, rs1_addr => rs1_addr_sig,
rs2_addr => rs2_addr_sig, op_code => op_code_sig);
control : entity register_file_control
port map(op_code => op_code_sig, rd => rd_addr_sig,
rs1 => rs1_addr_sig, rs2 => rs2_addr_sig,
load_enable => load_enable_sig,
load_addr => load_addr_sig);
register_file : entity register_file_operations
port map(rs1_addr => rs1_addr_sig, rs2_addr => rs2_addr_sig, load_data => instruction(11 downto 4),
load_enable => load_enable_sig, load_addr => load_addr_sig, writeback => writeback,
rd_address_writeback => rd_address_writeback, rd => rd, rs1 => rs1,
rs2 => rs2, clk => clk,
reg_port0 => reg_port0,reg_port1 => reg_port1,reg_port2 => reg_port2,reg_port3 => reg_port3,
reg_port4 => reg_port4,reg_port5 => reg_port5,reg_port6 => reg_port6,reg_port7 => reg_port7,
reg_port8 => reg_port8,reg_port9 => reg_port9,reg_port10 => reg_port10,reg_port11 => reg_port11,
reg_port12 => reg_port12, reg_port13 => reg_port13, reg_port14 => reg_port14,reg_port15 => reg_port15);
end behavioral;
|
apache-2.0
|
d64261f2cbdd229f4d3f672b32513297
| 0.600318 | 3.155779 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/ItoF.vhd
| 1 | 3,124 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ItoF is
port (
clk : in std_logic;
i : in std_logic_vector(31 downto 0);
f : out std_logic_vector(31 downto 0) := (others => '0'));
end IToF;
architecture dataflow_pipeline of ItoF is
type u_frc_ary_t is array (4 downto 0) of unsigned(32 downto 0);
signal u_frc_4_pre : unsigned(32 downto 0);
signal sgn_p : std_logic := '0';
signal u_frc : u_frc_ary_t := (others => (others => '0'));
signal x_nlz : std_logic_vector(4 downto 0);
signal u_frc_tmp : unsigned(32 downto 0);
signal tail_any : std_logic;
signal round : std_logic;
signal u_frc_norm : unsigned(23 downto 0);
signal sgn_pp : std_logic := '0';
signal x_nlz_suf : std_logic_vector(4 downto 0) := (others => '0');
signal u_frc_over_guard : unsigned(1 downto 0) := (others => '0');
signal u_frc_norm_suf : unsigned(23 downto 0) := (others => '0');
signal exp_out : std_logic_vector(7 downto 0);
signal frc_out : std_logic_vector(22 downto 0);
begin
u_frc_4_pre <= '0' & unsigned(i) when i(31) = '0' else
'0' & (x"00000000" - unsigned(i));
pipe1 : process(clk)
begin
if rising_edge(clk) then
u_frc(4) <= u_frc_4_pre;
sgn_p <= i(31);
end if;
end process;
x_nlz(4) <= '0' when u_frc(4)(32 downto 17) = 0 else '1';
u_frc(3) <= u_frc(4) sll 16 when u_frc(4)(32 downto 17) = 0 else u_frc(4);
x_nlz(3) <= '0' when u_frc(3)(32 downto 25) = 0 else '1';
u_frc(2) <= u_frc(3) sll 8 when u_frc(3)(32 downto 25) = 0 else u_frc(3);
x_nlz(2) <= '0' when u_frc(2)(32 downto 29) = 0 else '1';
u_frc(1) <= u_frc(2) sll 4 when u_frc(2)(32 downto 29) = 0 else u_frc(2);
x_nlz(1) <= '0' when u_frc(1)(32 downto 31) = 0 else '1';
u_frc(0) <= u_frc(1) sll 2 when u_frc(1)(32 downto 31) = 0 else u_frc(1);
x_nlz(0) <= '0' when u_frc(0)(32 downto 32) = 0 else '1';
u_frc_tmp <= u_frc(0) sll 1 when u_frc(0)(32 downto 32) = 0 else u_frc(0);
tail_any <= '0' when u_frc_tmp(7 downto 0) = 0 else '1';
round <= (u_frc_tmp(8) and tail_any) or (u_frc_tmp(9) and u_frc_tmp(8));
u_frc_norm <= u_frc_tmp(32 downto 9) + (x"00000" & "000" & round);
pipe2 : process(clk)
begin
if rising_edge(clk) then
x_nlz_suf <= x_nlz;
u_frc_over_guard <= u_frc_tmp(32 downto 31);
u_frc_norm_suf <= u_frc_norm;
sgn_pp <= sgn_p;
end if;
end process;
frc_out <= std_logic_vector('0' & u_frc_norm_suf(21 downto 0)) when u_frc_norm_suf(23) = '0' else -- round up or `itof(1)` or `itof(0)`, always 0
std_logic_vector(u_frc_norm_suf(22 downto 0));
exp_out <= "00000000" when u_frc_over_guard = "00" else
"01111111" when u_frc_over_guard = "01" else
"100" & std_logic_vector(unsigned(x_nlz_suf) + 1) when u_frc_norm_suf(23) = '0' else
"100" & x_nlz_suf;
f <= sgn_pp & exp_out & frc_out;
end dataflow_pipeline;
|
bsd-2-clause
|
6fee78d3a9666af7ae7753a964ac6756
| 0.541933 | 2.752423 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/CvtColor_1_sectorncg.vhd
| 1 | 2,646 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CvtColor_1_sectorncg_rom is
generic(
dwidth : integer := 2;
awidth : integer := 3;
mem_size : integer := 6
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of CvtColor_1_sectorncg_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "11", 1 to 2=> "00", 3 => "10", 4 to 5=> "01" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem : signal is "select_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem : signal is "distributed";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity CvtColor_1_sectorncg is
generic (
DataWidth : INTEGER := 2;
AddressRange : INTEGER := 6;
AddressWidth : INTEGER := 3);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of CvtColor_1_sectorncg is
component CvtColor_1_sectorncg_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
CvtColor_1_sectorncg_rom_U : component CvtColor_1_sectorncg_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
2e050f9302864a81d5906473bb37cd68
| 0.553288 | 3.57085 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/EscaladoPrePresentacion.vhd
| 2 | 2,959 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity EscaladoPrePresentacion is
PORT(
entrada_frec: in std_logic_vector (31 downto 0);
salida_frec: out STD_LOGIC_VECTOR(15 downto 0);
salida_uds: out STD_LOGIC_VECTOR (1 downto 0)--introducir variables bcd
);
end EscaladoPrePresentacion;
architecture Behavioral of EscaladoPrePresentacion is
component bcd_g
Port (
entrada_int: in std_logic_vector (31 downto 0);
decenas_millones : out std_logic_vector (3 downto 0);
millones : out std_logic_vector (3 downto 0);
centenas_mill : out std_logic_vector (3 downto 0);
decenas_mill : out std_logic_vector (3 downto 0);
millares : out std_logic_vector (3 downto 0);
centenas : out std_logic_vector (3 downto 0);
decenas : out std_logic_vector (3 downto 0);
unidades : out std_logic_vector (3 downto 0)
);
end component;
signal temp : std_logic_vector (31 downto 0);
constant c1 : integer:=10000;
constant c2 : integer:=10000000;
signal unidades_esc: STD_LOGIC_VECTOR(1 downto 0);
signal sal : std_logic_vector(15 downto 0);
signal decenas_millones : std_logic_vector (3 downto 0);
signal millones : std_logic_vector (3 downto 0);
signal centenas_mill : std_logic_vector (3 downto 0);
signal decenas_mill : std_logic_vector (3 downto 0);
signal millares : std_logic_vector (3 downto 0);
signal centenas : std_logic_vector (3 downto 0);
signal decenas : std_logic_vector (3 downto 0);
signal unidades : std_logic_vector (3 downto 0);
begin
temp<=entrada_frec;
conversor: bcd_g PORT MAP(
entrada_int=>entrada_frec,
decenas_millones=>decenas_millones,
millones=>millones,
centenas_mill=>centenas_mill,
decenas_mill=>decenas_mill,
millares=>millares,
centenas=>centenas,
decenas=>decenas,
unidades=>unidades);
process(temp)
begin
if unsigned(temp)<c1 then
sal<=millares & centenas & decenas & unidades;
unidades_esc<="00";
elsif to_integer(unsigned(temp))>=c1 and to_integer(unsigned(temp))<c2 then
sal<=millones¢enas_mill&decenas_mill&millares;
unidades_esc<="01";
elsif to_integer(unsigned(temp))>=c2 then
unidades_esc<="10";
sal<="00000000" & decenas_millones & millones;
else
unidades_esc<="00";
sal<="0000000000000000";
end if;
end process;
salida_uds<=unidades_esc;
salida_frec<=sal;
end Behavioral;
|
gpl-2.0
|
3a40337e527d205e6cb2d4feef4a2881
| 0.642785 | 3.694132 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
testbench.vhd
| 1 | 3,878 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end testbench;
architecture tb of testbench is
constant period : time := 50ns;
signal clk: std_logic;
signal reg_port0, reg_port1, reg_port2,reg_port3, reg_port4,reg_port5, reg_port6,reg_port7, reg_port8,reg_port9, reg_port10, reg_port11, reg_port12, reg_port13, reg_port14, reg_port15: std_logic_vector(63 downto 0);
signal instruction_data: std_logic_vector(255 downto 0);
signal instruction_load_en: std_logic;
begin
u1:entity Pipelined_CellLite_Unit port map(
full_instruction_data => instruction_data,
instruction_load_en => instruction_load_en ,
clk=>clk,
reg_port0=>reg_port0,
reg_port1=>reg_port1,
reg_port2=>reg_port2,
reg_port3=>reg_port3,
reg_port4=>reg_port4,
reg_port5=>reg_port5,
reg_port6=>reg_port6,
reg_port7=>reg_port7,
reg_port8=>reg_port8,
reg_port9=>reg_port9,
reg_port10=>reg_port10,
reg_port11=>reg_port11,
reg_port12=>reg_port12,
reg_port13=>reg_port13,
reg_port14=>reg_port14,
reg_port15=>reg_port15
);
--clock_gen: process
--begin
-- clk <= '0';
-- wait for period/2;
-- loop
-- clk <= not clk;
-- wait for period/2;
-- end loop;
-- end process;
process
begin
instruction_data(255 downto 240)<="0001110111000010";
instruction_data(239 downto 224)<="0001010101100101";
instruction_data(223 downto 208)<="0001000000011101";
instruction_data(207 downto 192)<="0001001001011000";
instruction_data(191 downto 176)<="0010001001011011";
instruction_data(175 downto 160)<="0101000001011101";
instruction_data(159 downto 144)<="0110101100101110";
instruction_data(143 downto 128)<="0111011011100111";
instruction_data(127 downto 112)<="1000110110000001";
instruction_data(111 downto 96)<="1001000101101111";
instruction_data(95 downto 80)<="1010001001010100";
instruction_data(79 downto 64)<="1011010000011001";
instruction_data(63 downto 48)<="1100011100101100";
instruction_data(47 downto 32)<="1101011011000101";
instruction_data(31 downto 16)<="1110000110000010";
instruction_data(15 downto 0)<="1111010110011101";
instruction_load_en <= '1';
clk<='1';
wait for period/2;
instruction_load_en <= '0';
clk<='0';
wait for period/2;
for i in 0 to 20 loop
clk<='1';
wait for period/2;
clk<='0';
wait for period/2;
if (i = 20) then
exit;
end if;
end loop;
wait;
end process;
end tb;
|
apache-2.0
|
fda0039b72d91b542858b258353fbd84
| 0.43966 | 4.504065 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_streeOg.vhd
| 1 | 2,149 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_streeOg_DSP48_3 is
port (
in0: in std_logic_vector(9 - 1 downto 0);
in1: in std_logic_vector(23 - 1 downto 0);
in2: in std_logic_vector(31 - 1 downto 0);
dout: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of hls_contrast_streeOg_DSP48_3 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(unsigned(in1), 25));
b <= signed(resize(signed(in0), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 32));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_streeOg is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_streeOg is
component hls_contrast_streeOg_DSP48_3 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_streeOg_DSP48_3_U : component hls_contrast_streeOg_DSP48_3
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
mit
|
61662dd54072ff0012f7ac8d1f4b6c89
| 0.570033 | 3.357813 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
serial_addition/srg4.vhd
| 1 | 771 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity srg4 is
Port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end srg4;
architecture Behavioral of srg4 is
signal reg: STD_LOGIC_VECTOR(3 downto 0);
begin
process (CLK, reset)
begin
if RESET='1' then --asynchronous RESET active High
reg <= "0000";
elsif CLK'event and CLK='1' then
REG <= DIN & REG( 3 downto 1 );
end if;
end process;
DOUT <= REG(0);
end Behavioral;
|
mit
|
f373a965d3222161d5c29e0713760aeb
| 0.658885 | 3.134146 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/full_adder.vhd
| 2 | 805 |
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
port
(
in1 : in std_logic;
in2 : in std_logic;
c_in : in std_logic;
sum : out std_logic;
c_out : out std_logic
);
end full_adder;
architecture Behavioral of full_adder is
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;
begin
s1 <= (in1 xor in2);
s2 <= (c_in and s1);
s3 <= (in1 and in2);
sum <= (s1 xor c_in);
c_out <= (s2 or s3);
end Behavioral;
|
mit
|
e33987e2fc49731205c9b0dca0d23da9
| 0.56646 | 3.049242 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_enbkb.vhd
| 1 | 7,269 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hls_saturation_enbkb_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
function max (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end max;
end entity;
architecture rtl of hls_saturation_enbkb_div_u is
constant cal_WIDTH : INTEGER := max(in0_WIDTH, in1_WIDTH);
type in0_vector is array(INTEGER range <>) of UNSIGNED(in0_WIDTH-1 downto 0);
type in1_vector is array(INTEGER range <>) of UNSIGNED(in1_WIDTH-1 downto 0);
type cal_vector is array(INTEGER range <>) of UNSIGNED(cal_WIDTH downto 0);
signal dividend_tmp : in0_vector(0 to in0_WIDTH);
signal divisor_tmp : in1_vector(0 to in0_WIDTH);
signal remd_tmp : in0_vector(0 to in0_WIDTH);
signal comb_tmp : in0_vector(0 to in0_WIDTH-1);
signal cal_tmp : cal_vector(0 to in0_WIDTH-1);
begin
quot <= STD_LOGIC_VECTOR(RESIZE(dividend_tmp(in0_WIDTH), out_WIDTH));
remd <= STD_LOGIC_VECTOR(RESIZE(remd_tmp(in0_WIDTH), out_WIDTH));
tran_tmp_proc : process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(0) <= UNSIGNED(dividend);
divisor_tmp(0) <= UNSIGNED(divisor);
remd_tmp(0) <= (others => '0');
end if;
end if;
end process tran_tmp_proc;
run_proc: for i in 0 to in0_WIDTH-1 generate
begin
comb_tmp(i) <= remd_tmp(i)(in0_WIDTH-2 downto 0) & dividend_tmp(i)(in0_WIDTH-1);
cal_tmp(i) <= ('0' & comb_tmp(i)) - ('0' & divisor_tmp(i));
process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(i+1) <= dividend_tmp(i)(in0_WIDTH-2 downto 0) & (not cal_tmp(i)(cal_WIDTH));
divisor_tmp(i+1) <= divisor_tmp(i);
if cal_tmp(i)(cal_WIDTH) = '1' then
remd_tmp(i+1) <= comb_tmp(i);
else
remd_tmp(i+1) <= cal_tmp(i)(in0_WIDTH-1 downto 0);
end if;
end if;
end if;
end process;
end generate run_proc;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hls_saturation_enbkb_div is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end entity;
architecture rtl of hls_saturation_enbkb_div is
component hls_saturation_enbkb_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end component;
signal dividend0 : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor0 : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal dividend_u : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor_u : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal quot_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal remd_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
begin
hls_saturation_enbkb_div_u_0 : hls_saturation_enbkb_div_u
generic map(
in0_WIDTH => in0_WIDTH,
in1_WIDTH => in1_WIDTH,
out_WIDTH => out_WIDTH)
port map(
clk => clk,
reset => reset,
ce => ce,
dividend => dividend_u,
divisor => divisor_u,
quot => quot_u,
remd => remd_u);
dividend_u <= dividend0;
divisor_u <= divisor0;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
dividend0 <= dividend;
divisor0 <= divisor;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
quot <= quot_u;
remd <= remd_u;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_enbkb is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_enbkb is
component hls_saturation_enbkb_div is
generic (
in0_WIDTH : INTEGER;
in1_WIDTH : INTEGER;
out_WIDTH : INTEGER);
port (
dividend : IN STD_LOGIC_VECTOR;
divisor : IN STD_LOGIC_VECTOR;
quot : OUT STD_LOGIC_VECTOR;
remd : OUT STD_LOGIC_VECTOR;
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
reset : IN STD_LOGIC);
end component;
signal sig_quot : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
signal sig_remd : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
begin
hls_saturation_enbkb_div_U : component hls_saturation_enbkb_div
generic map (
in0_WIDTH => din0_WIDTH,
in1_WIDTH => din1_WIDTH,
out_WIDTH => dout_WIDTH)
port map (
dividend => din0,
divisor => din1,
quot => dout,
remd => sig_remd,
clk => clk,
ce => ce,
reset => reset);
end architecture;
|
mit
|
09722ab169b1a82e9d7e1c112c191bf4
| 0.529371 | 3.542398 | false | false | false | false |
Digilent/vivado-library
|
ip/dvi2rgb/src/TMDS_Clocking.vhd
| 1 | 12,258 |
-------------------------------------------------------------------------------
--
-- File: TMDS_Clocking.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 10 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates all the necessary primitives to obtain a fast
-- serial clock from the TMDS Clock pins to be used for deserializing the TMDS
-- Data channels. Connect this module directly to the top-level TMDS Clock pins
-- and a 200/300 MHz reference clock.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity TMDS_Clocking is
Generic (
kClkRange : natural := 1); -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
Port (
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
RefClk : in std_logic; -- 200MHz reference clock for IDELAY primitives; independent of DVI_Clk!
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
SerialClk : out std_logic;
PixelClk : out std_logic;
aLocked : out std_logic;
dbg_rDlyRst : out std_logic;
dbg_rRdyRst : out std_logic;
dbg_rMMCM_Reset : out std_logic;
dbg_rBUFR_Rst : out std_logic;
dbg_rMMCM_Locked : out std_logic
);
end TMDS_Clocking;
architecture Behavioral of TMDS_Clocking is
constant kDlyRstDelay : natural := 32;
signal aDlyLckd, rDlyRst, rBUFR_Rst, rLockLostRst : std_logic;
signal rDlyRstCnt : natural range 0 to kDlyRstDelay - 1 := kDlyRstDelay - 1;
signal clkfbout_hdmi_clk, CLK_IN_hdmi_clk, CLK_OUT_1x_hdmi_clk, CLK_OUT_5x_hdmi_clk : std_logic;
signal clkout1b_unused, clkout2_unused, clkout2b_unused, clkout3_unused, clkout3b_unused, clkout4_unused, clkout5_unused, clkout6_unused,
drdy_unused, psdone_unused, clkfbstopped_unused, clkinstopped_unused, clkfboutb_unused, clkout0b_unused, clkout1_unused : std_logic;
signal do_unused : std_logic_vector(15 downto 0);
signal LOCKED_int, rRdyRst : std_logic;
signal aMMCM_Locked, rMMCM_Locked_ms, rMMCM_Locked, rMMCM_LckdFallingFlag, rMMCM_LckdRisingFlag : std_logic;
signal rMMCM_Reset_q : std_logic_vector(1 downto 0);
signal rMMCM_Locked_q : std_logic_vector(1 downto 0);
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal rLockLostRst can be used as
-- asynchronous reset for any flip-flop in the RefClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => RefClk,
oRst => rLockLostRst);
--IDELAYCTRL must be reset after configuration or refclk lost for 52ns(K7), 72ns(A7) at least
ResetIDELAYCTRL: process(rLockLostRst, RefClk)
begin
if Rising_Edge(RefClk) then
if (rLockLostRst = '1') then
rDlyRstCnt <= kDlyRstDelay - 1;
rDlyRst <= '1';
elsif (rDlyRstCnt /= 0) then
rDlyRstCnt <= rDlyRstCnt - 1;
else
rDlyRst <= '0';
end if;
end if;
end process;
IDelayCtrlX: IDELAYCTRL
port map (
RDY => aDlyLckd,
REFCLK => RefClk,
RST => rDlyRst);
RdyLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aDlyLckd,
OutClk => RefClk,
oRst => rRdyRst);
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "TMDS_33")
port map
(
O => CLK_IN_hdmi_clk,
I => TMDS_Clk_p,
IB => TMDS_Clk_n);
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- ISERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV and BUFR primitive.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_hdmi_clk,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => CLK_OUT_5x_hdmi_clk,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_hdmi_clk,
CLKIN1 => CLK_IN_hdmi_clk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => aMMCM_Locked,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => rMMCM_Reset_q(0));
-- 5x fast serial clock
SerialClkBuffer: BUFIO
port map (
O => SerialClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
-- 1x slow parallel clock
PixelClkBuffer: BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => PixelClk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => rBUFR_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
rBUFR_Rst <= rMMCM_LckdRisingFlag; --pulse CLR on BUFR once the clock returns
MMCM_Reset: process(rLockLostRst, RefClk)
begin
if (rLockLostRst = '1') then
rMMCM_Reset_q <= (others => '1'); -- MMCM_RSTMINPULSE Minimum Reset Pulse Width 5.00ns = two RefClk periods min
elsif Rising_Edge(RefClk) then
if (rMMCM_LckdFallingFlag = '1') then
rMMCM_Reset_q <= (others => '1');
else
rMMCM_Reset_q <= '0' & rMMCM_Reset_q(rMMCM_Reset_q'high downto 1);
end if;
end if;
end process MMCM_Reset;
MMCM_LockSync: entity work.SyncAsync
port map (
aReset => '0',
aIn => aMMCM_Locked,
OutClk => RefClk,
oOut => rMMCM_Locked);
MMCM_LockedDetect: process(RefClk)
begin
if Rising_Edge(RefClk) then
rMMCM_Locked_q <= rMMCM_Locked & rMMCM_Locked_q(1);
rMMCM_LckdFallingFlag <= rMMCM_Locked_q(1) and not rMMCM_Locked;
rMMCM_LckdRisingFlag <= not rMMCM_Locked_q(1) and rMMCM_Locked;
end if;
end process MMCM_LockedDetect;
GlitchFreeLocked: process(rRdyRst, RefClk)
begin
if (rRdyRst = '1') then
aLocked <= '0';
elsif Rising_Edge(RefClk) then
aLocked <= rMMCM_Locked_q(0);
end if;
end process GlitchFreeLocked;
dbg_rDlyRst <= rDlyRst;
dbg_rRdyRst <= rRdyRst;
dbg_rMMCM_Reset <= rMMCM_Reset_q(0);
dbg_rBUFR_Rst <= rBUFR_Rst;
dbg_rMMCM_Locked <= rMMCM_Locked;
end Behavioral;
|
mit
|
14d669cf8e97ac850d3387d69b075c24
| 0.630609 | 4.022973 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_enhance_AXILiteS_s_axi.vhd
| 1 | 9,273 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_saturation_enhance_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
-- user signals
height :out STD_LOGIC_VECTOR(15 downto 0);
width :out STD_LOGIC_VECTOR(15 downto 0);
sat :out STD_LOGIC_VECTOR(7 downto 0)
);
end entity hls_saturation_enhance_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : reserved
-- 0x04 : reserved
-- 0x08 : reserved
-- 0x0c : reserved
-- 0x10 : Data signal of height
-- bit 15~0 - height[15:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of width
-- bit 15~0 - width[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- 0x20 : Data signal of sat
-- bit 7~0 - sat[7:0] (Read/Write)
-- others - reserved
-- 0x24 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of hls_saturation_enhance_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_HEIGHT_DATA_0 : INTEGER := 16#10#;
constant ADDR_HEIGHT_CTRL : INTEGER := 16#14#;
constant ADDR_WIDTH_DATA_0 : INTEGER := 16#18#;
constant ADDR_WIDTH_CTRL : INTEGER := 16#1c#;
constant ADDR_SAT_DATA_0 : INTEGER := 16#20#;
constant ADDR_SAT_CTRL : INTEGER := 16#24#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_height : UNSIGNED(15 downto 0) := (others => '0');
signal int_width : UNSIGNED(15 downto 0) := (others => '0');
signal int_sat : UNSIGNED(7 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_height(15 downto 0), 32);
when ADDR_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_width(15 downto 0), 32);
when ADDR_SAT_DATA_0 =>
rdata_data <= RESIZE(int_sat(7 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
height <= STD_LOGIC_VECTOR(int_height);
width <= STD_LOGIC_VECTOR(int_width);
sat <= STD_LOGIC_VECTOR(int_sat);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_HEIGHT_DATA_0) then
int_height(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_height(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_WIDTH_DATA_0) then
int_width(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_width(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_SAT_DATA_0) then
int_sat(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_sat(7 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
mit
|
b661f947060fc54622d573e8fd7ca8ec
| 0.471692 | 3.947637 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/Resize_opr_linear.vhd
| 1 | 269,503 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Resize_opr_linear is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_rows_V_read : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_cols_V_read : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of Resize_opr_linear is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_state31 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_state32 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_state33 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_state34 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_state35 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_state36 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_state38 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_state39 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_state40 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_state41 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_state42 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_state43 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_state44 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_state45 : STD_LOGIC_VECTOR (56 downto 0) := "000000000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_state46 : STD_LOGIC_VECTOR (56 downto 0) := "000000000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state47 : STD_LOGIC_VECTOR (56 downto 0) := "000000000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state48 : STD_LOGIC_VECTOR (56 downto 0) := "000000000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state49 : STD_LOGIC_VECTOR (56 downto 0) := "000000001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state50 : STD_LOGIC_VECTOR (56 downto 0) := "000000010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state51 : STD_LOGIC_VECTOR (56 downto 0) := "000000100000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state52 : STD_LOGIC_VECTOR (56 downto 0) := "000001000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state53 : STD_LOGIC_VECTOR (56 downto 0) := "000010000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state54 : STD_LOGIC_VECTOR (56 downto 0) := "000100000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state55 : STD_LOGIC_VECTOR (56 downto 0) := "001000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (56 downto 0) := "010000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state109 : STD_LOGIC_VECTOR (56 downto 0) := "100000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv15_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000000";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv16_FFF6 : STD_LOGIC_VECTOR (15 downto 0) := "1111111111110110";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv33_1FFFF8000 : STD_LOGIC_VECTOR (32 downto 0) := "111111111111111111000000000000000";
constant ap_const_lv26_3FF8000 : STD_LOGIC_VECTOR (25 downto 0) := "11111111111000000000000000";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_FFFF : STD_LOGIC_VECTOR (15 downto 0) := "1111111111111111";
constant ap_const_lv32_10000 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000010000000000000000";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv15_1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_const_lv33_0 : STD_LOGIC_VECTOR (32 downto 0) := "000000000000000000000000000000000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv20_0 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000000";
constant ap_const_lv20_40000 : STD_LOGIC_VECTOR (19 downto 0) := "01000000000000000000";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (56 downto 0) := "000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal p_src_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter42 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal tmp_31_reg_2851 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter41_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_rd_2_reg_3006 : STD_LOGIC_VECTOR (0 downto 0);
signal row_rd_5_reg_3002 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_53_reg_3065 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_55_reg_3069 : STD_LOGIC_VECTOR (0 downto 0);
signal p_src_data_stream_1_V_blk_n : STD_LOGIC;
signal p_src_data_stream_2_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter52 : STD_LOGIC := '0';
signal brmerge_demorgan_reg_3077 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter51_reg : STD_LOGIC_VECTOR (0 downto 0);
signal p_dst_data_stream_1_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_2_V_blk_n : STD_LOGIC;
signal p_Val2_17_reg_546 : STD_LOGIC_VECTOR (14 downto 0);
signal dcols_fu_650_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal dcols_reg_2655 : STD_LOGIC_VECTOR (15 downto 0);
signal drows_fu_654_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal drows_reg_2661 : STD_LOGIC_VECTOR (15 downto 0);
signal srows_fu_658_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal srows_reg_2667 : STD_LOGIC_VECTOR (15 downto 0);
signal scols_fu_662_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal scols_reg_2675 : STD_LOGIC_VECTOR (15 downto 0);
signal row_rate_V_fu_739_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal row_rate_V_reg_2703 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state52 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state52 : signal is "none";
signal col_rate_V_fu_743_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal col_rate_V_reg_2711 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_reg_2719 : STD_LOGIC_VECTOR (0 downto 0);
signal p_lshr_f_reg_2724 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_68_reg_2729 : STD_LOGIC_VECTOR (0 downto 0);
signal p_lshr_f1_reg_2734 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_10_fu_811_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_reg_2739 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state53 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state53 : signal is "none";
signal tmp_65_fu_818_p1 : STD_LOGIC_VECTOR (25 downto 0);
signal tmp_65_reg_2744 : STD_LOGIC_VECTOR (25 downto 0);
signal tmp_14_fu_850_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_reg_2749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_69_fu_857_p1 : STD_LOGIC_VECTOR (25 downto 0);
signal tmp_69_reg_2754 : STD_LOGIC_VECTOR (25 downto 0);
signal rows_fu_960_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal rows_reg_2759 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state54 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state54 : signal is "none";
signal cols_fu_976_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal cols_reg_2764 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_21_fu_983_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_21_reg_2769 : STD_LOGIC_VECTOR (16 downto 0);
signal sx_fu_989_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal sx_reg_2776 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_22_fu_994_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_22_reg_2781 : STD_LOGIC_VECTOR (16 downto 0);
signal sy_fu_1000_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal sy_reg_2787 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_23_fu_1005_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_2792 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_fu_1010_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_reg_2797 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_59_cast_fu_1023_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_cast_reg_2804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_cast_fu_1035_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_cast_reg_2809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_fu_1043_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state55 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state55 : signal is "none";
signal i_fu_1048_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal i_reg_2818 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_28_fu_1054_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_28_reg_2823 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_29_fu_1060_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_2829 : STD_LOGIC_VECTOR (0 downto 0);
signal row_wr_2_fu_1066_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal row_wr_2_reg_2835 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_49_cast_fu_1080_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_cast_reg_2840 : STD_LOGIC_VECTOR (31 downto 0);
signal i_op_assign_cast_fu_1084_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state56_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state57_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state58_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state59_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state60_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state61_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state62_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state63_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state64_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state65_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state66_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_state67_pp0_stage0_iter11 : BOOLEAN;
signal ap_block_state68_pp0_stage0_iter12 : BOOLEAN;
signal ap_block_state69_pp0_stage0_iter13 : BOOLEAN;
signal ap_block_state70_pp0_stage0_iter14 : BOOLEAN;
signal ap_block_state71_pp0_stage0_iter15 : BOOLEAN;
signal ap_block_state72_pp0_stage0_iter16 : BOOLEAN;
signal ap_block_state73_pp0_stage0_iter17 : BOOLEAN;
signal ap_block_state74_pp0_stage0_iter18 : BOOLEAN;
signal ap_block_state75_pp0_stage0_iter19 : BOOLEAN;
signal ap_block_state76_pp0_stage0_iter20 : BOOLEAN;
signal ap_block_state77_pp0_stage0_iter21 : BOOLEAN;
signal ap_block_state78_pp0_stage0_iter22 : BOOLEAN;
signal ap_block_state79_pp0_stage0_iter23 : BOOLEAN;
signal ap_block_state80_pp0_stage0_iter24 : BOOLEAN;
signal ap_block_state81_pp0_stage0_iter25 : BOOLEAN;
signal ap_block_state82_pp0_stage0_iter26 : BOOLEAN;
signal ap_block_state83_pp0_stage0_iter27 : BOOLEAN;
signal ap_block_state84_pp0_stage0_iter28 : BOOLEAN;
signal ap_block_state85_pp0_stage0_iter29 : BOOLEAN;
signal ap_block_state86_pp0_stage0_iter30 : BOOLEAN;
signal ap_block_state87_pp0_stage0_iter31 : BOOLEAN;
signal ap_block_state88_pp0_stage0_iter32 : BOOLEAN;
signal ap_block_state89_pp0_stage0_iter33 : BOOLEAN;
signal ap_block_state90_pp0_stage0_iter34 : BOOLEAN;
signal ap_block_state91_pp0_stage0_iter35 : BOOLEAN;
signal ap_block_state92_pp0_stage0_iter36 : BOOLEAN;
signal ap_block_state93_pp0_stage0_iter37 : BOOLEAN;
signal ap_block_state94_pp0_stage0_iter38 : BOOLEAN;
signal ap_block_state95_pp0_stage0_iter39 : BOOLEAN;
signal ap_block_state96_pp0_stage0_iter40 : BOOLEAN;
signal ap_block_state97_pp0_stage0_iter41 : BOOLEAN;
signal ap_predicate_op564_read_state98 : BOOLEAN;
signal ap_block_state98_pp0_stage0_iter42 : BOOLEAN;
signal ap_block_state99_pp0_stage0_iter43 : BOOLEAN;
signal ap_block_state100_pp0_stage0_iter44 : BOOLEAN;
signal ap_block_state101_pp0_stage0_iter45 : BOOLEAN;
signal ap_block_state102_pp0_stage0_iter46 : BOOLEAN;
signal ap_block_state103_pp0_stage0_iter47 : BOOLEAN;
signal ap_block_state104_pp0_stage0_iter48 : BOOLEAN;
signal ap_block_state105_pp0_stage0_iter49 : BOOLEAN;
signal ap_block_state106_pp0_stage0_iter50 : BOOLEAN;
signal ap_block_state107_pp0_stage0_iter51 : BOOLEAN;
signal ap_block_state108_pp0_stage0_iter52 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal i_op_assign_cast_reg_2845_pp0_iter1_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter2_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter3_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter4_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter5_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter6_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter7_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter8_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter9_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter10_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter11_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter12_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter13_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter14_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter15_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter16_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter17_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter18_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter19_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter20_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter21_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter22_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter23_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter24_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter25_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter26_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter27_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter28_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter29_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter30_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter31_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter32_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter33_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter34_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter35_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter36_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter37_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter38_reg : STD_LOGIC_VECTOR (15 downto 0);
signal i_op_assign_cast_reg_2845_pp0_iter39_reg : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_31_fu_1088_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter5_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter6_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter7_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter8_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter9_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter10_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter11_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter12_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter13_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter14_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter15_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter16_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter17_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter18_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter19_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter20_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter21_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter22_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter23_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter24_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter25_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter26_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter27_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter28_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter29_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter30_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter31_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter32_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter33_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter34_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter35_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter36_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter37_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter38_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter39_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter40_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_reg_2851_pp0_iter42_reg : STD_LOGIC_VECTOR (0 downto 0);
signal j_fu_1093_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_50_fu_1120_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter5_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter6_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter7_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter8_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter9_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter10_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter11_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter12_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter13_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter14_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter15_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter16_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter17_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter18_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter19_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter20_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter21_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter22_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter23_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter24_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter25_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter26_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter27_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter28_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter29_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter30_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter31_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter32_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter33_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter34_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter35_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter36_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter37_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter38_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter39_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_reg_2865_pp0_iter40_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_fu_1126_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877 : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter5_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter6_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter7_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter8_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter9_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter10_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter11_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter12_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter13_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter14_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter15_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter16_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter17_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter18_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter19_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter20_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter21_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter22_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter23_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter24_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter25_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter26_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter27_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter28_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter29_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter30_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter31_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter32_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter33_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter34_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter35_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter36_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter37_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter38_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter39_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_1_reg_2877_pp0_iter40_reg : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_1099_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_33_reg_2882 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1115_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_35_reg_2887 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_71_fu_1132_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_36_fu_1135_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_72_fu_1140_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1147_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_s_reg_2917 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1156_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_1_reg_2922 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_3_fu_1161_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_3_reg_2927 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_2_fu_1165_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_2_reg_2932 : STD_LOGIC_VECTOR (31 downto 0);
signal sx_2_fu_1211_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal sx_2_reg_2937 : STD_LOGIC_VECTOR (15 downto 0);
signal sy_3_fu_1261_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal sy_3_reg_2944 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_41_fu_1289_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_41_reg_2951 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_41_reg_2951_pp0_iter41_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_77_fu_1295_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_77_reg_2956 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_77_reg_2956_pp0_iter41_reg : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_46_fu_1319_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_46_reg_2961 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_46_reg_2961_pp0_iter41_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_46_reg_2961_pp0_iter42_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_78_fu_1325_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_78_reg_2966 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_78_reg_2966_pp0_iter41_reg : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_78_reg_2966_pp0_iter42_reg : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_48_fu_1332_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_reg_2971 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_reg_2971_pp0_iter41_reg : STD_LOGIC_VECTOR (0 downto 0);
signal pre_fx_1_fu_1337_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal pre_fx_1_reg_2976 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_49_fu_1346_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_49_reg_2984 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_49_reg_2984_pp0_iter41_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_49_reg_2984_pp0_iter42_reg : STD_LOGIC_VECTOR (0 downto 0);
signal sy_4_fu_1351_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal sy_4_reg_2989 : STD_LOGIC_VECTOR (15 downto 0);
signal col_wr_fu_1362_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_wr_reg_2997 : STD_LOGIC_VECTOR (0 downto 0);
signal row_rd_5_fu_1442_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal row_rd_5_reg_3002_pp0_iter42_reg : STD_LOGIC_VECTOR (0 downto 0);
signal col_rd_2_fu_1486_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_rd_2_reg_3006_pp0_iter42_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_1501_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_52_reg_3010 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_52_reg_3010_pp0_iter42_reg : STD_LOGIC_VECTOR (63 downto 0);
signal k_buf_val_val_0_0_ad_gep_fu_469_p3 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_0_ad_reg_3047 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_0_ad_reg_3047_pp0_iter42_reg : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_1_ad_gep_fu_476_p3 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_1_ad_reg_3053 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_1_ad_reg_3053_pp0_iter42_reg : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_2_ad_gep_fu_483_p3 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_2_ad_reg_3059 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_2_ad_reg_3059_pp0_iter42_reg : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_53_fu_1517_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_53_reg_3065_pp0_iter42_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_55_fu_1525_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_55_reg_3069_pp0_iter42_reg : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_fu_1533_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_reg_3073 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_reg_3073_pp0_iter42_reg : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_fu_1549_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter42_reg : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter43_reg : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter44_reg : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter45_reg : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter46_reg : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter47_reg : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter48_reg : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter49_reg : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_3077_pp0_iter50_reg : STD_LOGIC_VECTOR (0 downto 0);
signal u1_V_fu_1598_p2 : STD_LOGIC_VECTOR (19 downto 0);
signal u1_V_reg_3081 : STD_LOGIC_VECTOR (19 downto 0);
signal p_u_V_fu_1604_p3 : STD_LOGIC_VECTOR (19 downto 0);
signal p_u_V_reg_3086 : STD_LOGIC_VECTOR (19 downto 0);
signal p_u_V_reg_3086_pp0_iter43_reg : STD_LOGIC_VECTOR (19 downto 0);
signal p_u_V_reg_3086_pp0_iter44_reg : STD_LOGIC_VECTOR (19 downto 0);
signal k_buf_val_val_0_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_0_0_reg_3092 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_val_0_1_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_0_1_reg_3097 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_val_0_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_0_2_reg_3102 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_97_reg_3107 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_98_reg_3112 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_99_reg_3117 : STD_LOGIC_VECTOR (7 downto 0);
signal v1_V_fu_1709_p2 : STD_LOGIC_VECTOR (19 downto 0);
signal v1_V_reg_3122 : STD_LOGIC_VECTOR (19 downto 0);
signal v_V_fu_1715_p3 : STD_LOGIC_VECTOR (19 downto 0);
signal v_V_reg_3128 : STD_LOGIC_VECTOR (19 downto 0);
signal win_val_0_val_1_0_4_reg_3133 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_val_1_1_4_reg_3138 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_val_1_2_4_reg_3143 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_1_0_3_reg_3148 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_1_1_3_reg_3153 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_1_2_3_reg_3158 : STD_LOGIC_VECTOR (7 downto 0);
signal OP2_V_fu_1770_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal OP2_V_reg_3163 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_fu_2451_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_reg_3170 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_fu_2457_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_reg_3175 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_s_fu_2463_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_s_reg_3180 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_1_fu_2469_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_1_reg_3185 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_4_fu_2475_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_4_reg_3190 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_2_fu_2481_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_2_reg_3195 : STD_LOGIC_VECTOR (27 downto 0);
signal OP2_V_1_fu_1800_p1 : STD_LOGIC_VECTOR (47 downto 0);
signal r_V_1_fu_2487_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_1_reg_3212 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_2_fu_2493_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_2_reg_3217 : STD_LOGIC_VECTOR (27 downto 0);
signal OP2_V_6_fu_1821_p1 : STD_LOGIC_VECTOR (47 downto 0);
signal OP2_V_6_reg_3222 : STD_LOGIC_VECTOR (47 downto 0);
signal r_V_1_1_fu_2498_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_1_1_reg_3242 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_2_1_fu_2504_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_2_1_reg_3247 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_1_2_fu_2509_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_1_2_reg_3262 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_2_2_fu_2515_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_2_2_reg_3267 : STD_LOGIC_VECTOR (27 downto 0);
signal OP2_V_5_fu_1884_p1 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1809_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_21_reg_3314 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1827_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_29_reg_3319 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1836_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_40_1_reg_3324 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1851_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_42_1_reg_3329 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1860_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_40_2_reg_3334 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1875_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_42_2_reg_3339 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1887_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_24_reg_3344 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1896_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_28_reg_3349 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp69_fu_1935_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp69_reg_3354 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1904_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_30_1_reg_3359 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1913_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_33_1_reg_3364 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp71_fu_1939_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp71_reg_3369 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1921_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_30_2_reg_3374 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_1930_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_33_2_reg_3379 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp73_fu_1943_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp73_reg_3384 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_30_fu_1951_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_30_reg_3389 : STD_LOGIC_VECTOR (47 downto 0);
signal signbit_reg_3394 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_reg_3394_pp0_iter51_reg : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_31_reg_3401 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_83_reg_3406 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_6_i_i_reg_3411 : STD_LOGIC_VECTOR (3 downto 0);
signal p_Val2_44_1_fu_1996_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_44_1_reg_3417 : STD_LOGIC_VECTOR (47 downto 0);
signal signbit_1_reg_3422 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_1_reg_3422_pp0_iter51_reg : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_s_72_reg_3429 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_87_reg_3434 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_6_i_i1_reg_3439 : STD_LOGIC_VECTOR (3 downto 0);
signal p_Val2_44_2_fu_2041_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_Val2_44_2_reg_3445 : STD_LOGIC_VECTOR (47 downto 0);
signal signbit_2_reg_3450 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_2_reg_3450_pp0_iter51_reg : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_35_reg_3457 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_91_reg_3462 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_6_i_i2_reg_3467 : STD_LOGIC_VECTOR (3 downto 0);
signal p_Val2_32_fu_2092_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_32_reg_3473 : STD_LOGIC_VECTOR (7 downto 0);
signal p_38_i_i_i_fu_2135_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_i_i_reg_3479 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_fu_2141_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_reg_3485 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_33_fu_2156_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_33_reg_3491 : STD_LOGIC_VECTOR (7 downto 0);
signal p_38_i_i_i1_fu_2199_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_i_i1_reg_3497 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i1_fu_2205_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i1_reg_3503 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_36_fu_2220_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_36_reg_3509 : STD_LOGIC_VECTOR (7 downto 0);
signal p_38_i_i_i2_fu_2263_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_i_i2_reg_3515 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i2_fu_2269_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i2_reg_3521 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter11 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter12 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter13 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter14 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter15 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter16 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter17 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter18 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter19 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter20 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter21 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter22 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter23 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter24 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter25 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter26 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter27 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter28 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter29 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter30 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter31 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter32 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter33 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter34 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter35 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter36 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter37 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter38 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter39 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter40 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter41 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter43 : STD_LOGIC := '0';
signal ap_condition_pp0_exit_iter42_state98 : STD_LOGIC;
signal ap_enable_reg_pp0_iter44 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter45 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter46 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter47 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter48 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter49 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter50 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter51 : STD_LOGIC := '0';
signal k_buf_val_val_0_0_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_0_ce0 : STD_LOGIC;
signal k_buf_val_val_0_0_ce1 : STD_LOGIC;
signal k_buf_val_val_0_0_we1 : STD_LOGIC;
signal k_buf_val_val_0_0_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_val_0_1_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_1_ce0 : STD_LOGIC;
signal k_buf_val_val_0_1_ce1 : STD_LOGIC;
signal k_buf_val_val_0_1_we1 : STD_LOGIC;
signal k_buf_val_val_0_1_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_val_0_2_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_0_2_ce0 : STD_LOGIC;
signal k_buf_val_val_0_2_ce1 : STD_LOGIC;
signal k_buf_val_val_0_2_we1 : STD_LOGIC;
signal k_buf_val_val_0_2_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_val_1_0_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_1_0_ce0 : STD_LOGIC;
signal k_buf_val_val_1_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_val_1_0_address1 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_1_0_ce1 : STD_LOGIC;
signal k_buf_val_val_1_0_we1 : STD_LOGIC;
signal k_buf_val_val_1_1_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_1_1_ce0 : STD_LOGIC;
signal k_buf_val_val_1_1_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_val_1_1_address1 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_1_1_ce1 : STD_LOGIC;
signal k_buf_val_val_1_1_we1 : STD_LOGIC;
signal k_buf_val_val_1_2_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_1_2_ce0 : STD_LOGIC;
signal k_buf_val_val_1_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_val_val_1_2_address1 : STD_LOGIC_VECTOR (12 downto 0);
signal k_buf_val_val_1_2_ce1 : STD_LOGIC;
signal k_buf_val_val_1_2_we1 : STD_LOGIC;
signal p_Val2_16_reg_535 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_CS_fsm_state109 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state109 : signal is "none";
signal ap_phi_reg_pp0_iter0_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter1_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter2_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter3_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter4_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter5_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter6_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter7_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter8_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter9_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter10_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter11_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter12_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter13_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter14_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter15_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter16_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter17_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter18_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter19_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter20_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter21_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter22_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter23_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter24_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter25_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter26_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter27_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter28_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter29_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter30_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter31_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter32_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter33_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter34_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter35_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter36_dy_reg_557 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter0_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter1_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter2_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter3_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter4_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter5_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter6_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter7_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter8_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter9_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter10_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter11_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter12_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter13_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter14_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter15_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter16_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter17_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter18_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter19_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter20_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter21_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter22_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter23_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter24_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter25_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter26_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter27_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter28_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter29_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter30_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter31_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter32_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter33_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter34_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter35_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_reg_pp0_iter36_dx_reg_566 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_phi_mux_win_val_val_1_0_2_2_phi_fu_578_p10 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter42_win_val_val_1_0_2_2_reg_575 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_mux_win_val_val_1_0_1_2_phi_fu_598_p10 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter42_win_val_val_1_0_1_2_reg_595 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_mux_win_val_val_1_0_0_2_phi_fu_618_p10 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter42_win_val_val_1_0_0_2_reg_615 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal row_wr_fu_230 : STD_LOGIC_VECTOR (0 downto 0);
signal row_wr_3_fu_1456_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal row_rd_fu_234 : STD_LOGIC_VECTOR (0 downto 0);
signal pre_fx_fu_238 : STD_LOGIC_VECTOR (15 downto 0);
signal pre_fx_5_fu_1474_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal pre_fy_fu_242 : STD_LOGIC_VECTOR (15 downto 0);
signal pre_fy_5_fu_1417_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal x_fu_246 : STD_LOGIC_VECTOR (15 downto 0);
signal x_2_fu_1398_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal x_1_fu_1538_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_fu_250 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_254 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_val_1_0_fu_258 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_val_1_1_fu_262 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_val_1_2_fu_266 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_val_1_0_1_fu_270 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_val_1_1_1_fu_274 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_0_val_1_2_1_fu_278 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_1_0_fu_282 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_1_1_fu_286 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_1_2_fu_290 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_1_0_1_fu_294 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_1_1_1_fu_298 : STD_LOGIC_VECTOR (7 downto 0);
signal win_val_1_val_1_2_1_fu_302 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_fu_306 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_16_fu_666_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_684_p0 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp_42_fu_690_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_708_p0 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_684_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal grp_fu_708_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal p_neg_fu_783_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_lshr_fu_788_p4 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_5_fu_798_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_neg_t_fu_802_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_fu_808_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_neg1_fu_822_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_lshr1_fu_827_p4 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_12_fu_837_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_neg_t1_fu_841_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_fu_847_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_28_cast_fu_867_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal p_Val2_10_cast_fu_876_p2 : STD_LOGIC_VECTOR (25 downto 0);
signal p_Val2_9_fu_870_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_67_fu_891_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_10_fu_881_p4 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_11_fu_899_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_32_cast_fu_909_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal p_Val2_14_cast_fu_918_p2 : STD_LOGIC_VECTOR (25 downto 0);
signal p_Val2_13_fu_912_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_70_fu_933_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_14_fu_923_p4 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_15_fu_941_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_17_fu_951_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_955_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_19_fu_967_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_fu_971_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_20_cast_fu_864_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_13_cast_fu_861_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal p_Val2_18_fu_903_p2 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_25_fu_1015_p3 : STD_LOGIC_VECTOR (25 downto 0);
signal p_Val2_19_fu_945_p2 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_26_fu_1027_p3 : STD_LOGIC_VECTOR (25 downto 0);
signal i_op_assign_15_cast_fu_1039_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_30_fu_1072_p3 : STD_LOGIC_VECTOR (30 downto 0);
signal grp_fu_1099_p0 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_34_fu_1103_p3 : STD_LOGIC_VECTOR (30 downto 0);
signal grp_fu_1115_p0 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_74_fu_1187_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal ret_V_fu_1169_p4 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_37_fu_1191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ret_V_1_fu_1197_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_73_fu_1179_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_6_fu_1203_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_76_fu_1237_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal ret_V_2_fu_1219_p4 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_38_fu_1241_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ret_V_3_fu_1247_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_75_fu_1229_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_7_fu_1253_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_40_fu_1272_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_fu_1269_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_66_cast_fu_1279_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal r_V_7_fu_1283_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_45_fu_1302_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_44_fu_1299_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_72_cast_fu_1309_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal r_V_8_fu_1313_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_76_cast_fu_1329_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_78_cast_fu_1343_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_51_fu_1357_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal sel_tmp4_fu_1405_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal pre_fy_1_sy_fu_1392_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal sel_tmp5_fu_1409_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal not_1_fu_1387_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp66_fu_1431_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp_fu_1437_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal row_wr_1_fu_1383_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal row_wr_4_fu_1449_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal pre_fx_2_fu_1424_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal pre_fx_2_sx_fu_1468_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal not_s_fu_1463_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp67_fu_1481_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_86_cast_fu_1514_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_88_cast_fu_1522_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_90_cast_fu_1530_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal col_wr_2_fu_1491_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_43_fu_1584_p3 : STD_LOGIC_VECTOR (19 downto 0);
signal u_V_fu_1591_p3 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp_47_fu_1695_p3 : STD_LOGIC_VECTOR (19 downto 0);
signal v_V_2_fu_1702_p3 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1809_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1827_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1836_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1851_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1860_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1875_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1887_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1896_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1904_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1913_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1921_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_1930_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal tmp68_fu_1947_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp70_fu_1992_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp72_fu_2037_p2 : STD_LOGIC_VECTOR (47 downto 0);
signal tmp_i_i_fu_2082_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_fu_2097_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_84_fu_2085_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_i_i_fu_2105_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_fu_2111_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_fu_2117_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_fu_2122_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_fu_2127_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i1_fu_2146_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_89_fu_2161_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_88_fu_2149_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_i_i1_fu_2169_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_1_fu_2175_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_1_fu_2181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_1_fu_2186_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_1_fu_2191_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i2_fu_2210_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_93_fu_2225_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_92_fu_2213_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_i_i2_fu_2233_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_2_fu_2239_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_2_fu_2245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_2_fu_2250_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_2_fu_2255_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_i_i_fu_2274_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_not_i_fu_2284_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_not_i_i_fu_2289_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_not_i_fu_2299_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_not_i_i_fu_2294_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_5_fu_2279_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_fu_2304_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_mux_i_i_fu_2310_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_i_i_fu_2317_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_i_i1_fu_2333_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_not_i1_fu_2343_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_not_i_i1_fu_2348_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_not_i_1_fu_2358_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_not_i_i1_fu_2353_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_6_fu_2338_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i1_fu_2363_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_mux_i_i1_fu_2369_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_i_i1_fu_2376_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_i_i2_fu_2392_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_not_i2_fu_2402_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_not_i_i2_fu_2407_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_not_i_2_fu_2417_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_not_i_i2_fu_2412_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_fu_2397_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i2_fu_2422_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_mux_i_i2_fu_2428_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_i_i2_fu_2435_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_fu_2451_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_fu_2451_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_3_fu_2457_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal OP2_V_7_fu_1781_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_fu_2457_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_s_fu_2463_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_s_fu_2463_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_3_1_fu_2469_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_3_1_fu_2469_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_4_fu_2475_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_4_fu_2475_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_3_2_fu_2481_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_3_2_fu_2481_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_1_fu_2487_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal OP2_V_2_fu_1803_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_1_fu_2487_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_2_fu_2493_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_2_fu_2493_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_1_1_fu_2498_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_1_1_fu_2498_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_2_1_fu_2504_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_2_1_fu_2504_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_1_2_fu_2509_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_1_2_fu_2509_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_2_2_fu_2515_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_2_2_fu_2515_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_684_ap_start : STD_LOGIC;
signal grp_fu_684_ap_done : STD_LOGIC;
signal grp_fu_708_ap_start : STD_LOGIC;
signal grp_fu_708_ap_done : STD_LOGIC;
signal grp_fu_1099_ce : STD_LOGIC;
signal grp_fu_1115_ce : STD_LOGIC;
signal grp_fu_1147_ce : STD_LOGIC;
signal grp_fu_1156_ce : STD_LOGIC;
signal grp_fu_1809_ce : STD_LOGIC;
signal grp_fu_1827_ce : STD_LOGIC;
signal grp_fu_1836_ce : STD_LOGIC;
signal grp_fu_1851_ce : STD_LOGIC;
signal grp_fu_1860_ce : STD_LOGIC;
signal grp_fu_1875_ce : STD_LOGIC;
signal grp_fu_1887_ce : STD_LOGIC;
signal grp_fu_1896_ce : STD_LOGIC;
signal grp_fu_1904_ce : STD_LOGIC;
signal grp_fu_1913_ce : STD_LOGIC;
signal grp_fu_1921_ce : STD_LOGIC;
signal grp_fu_1930_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (56 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal grp_fu_1115_p00 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_1_1_fu_2498_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_1_2_fu_2509_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_1_fu_2487_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_2_1_fu_2504_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_2_2_fu_2515_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_2_fu_2493_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_1_fu_2469_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_2_fu_2481_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_3_fu_2457_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_4_fu_2475_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_fu_2451_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_s_fu_2463_p10 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_condition_428 : BOOLEAN;
signal ap_condition_3380 : BOOLEAN;
signal ap_condition_3386 : BOOLEAN;
component video_scaler_sdivhbi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
start : IN STD_LOGIC;
done : OUT STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (47 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (47 downto 0) );
end component;
component video_scaler_udivibs IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (30 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component video_scaler_mul_jbC IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component video_scaler_mul_kbM IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (27 downto 0);
din1 : IN STD_LOGIC_VECTOR (19 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (47 downto 0) );
end component;
component video_scaler_mul_lbW IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (19 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
dout : OUT STD_LOGIC_VECTOR (27 downto 0) );
end component;
component Resize_opr_linearbkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (12 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
k_buf_val_val_0_0_U : component Resize_opr_linearbkb
generic map (
DataWidth => 8,
AddressRange => 4097,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_val_0_0_address0,
ce0 => k_buf_val_val_0_0_ce0,
q0 => k_buf_val_val_0_0_q0,
address1 => k_buf_val_val_0_0_ad_reg_3047_pp0_iter42_reg,
ce1 => k_buf_val_val_0_0_ce1,
we1 => k_buf_val_val_0_0_we1,
d1 => k_buf_val_val_0_0_d1);
k_buf_val_val_0_1_U : component Resize_opr_linearbkb
generic map (
DataWidth => 8,
AddressRange => 4097,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_val_0_1_address0,
ce0 => k_buf_val_val_0_1_ce0,
q0 => k_buf_val_val_0_1_q0,
address1 => k_buf_val_val_0_1_ad_reg_3053_pp0_iter42_reg,
ce1 => k_buf_val_val_0_1_ce1,
we1 => k_buf_val_val_0_1_we1,
d1 => k_buf_val_val_0_1_d1);
k_buf_val_val_0_2_U : component Resize_opr_linearbkb
generic map (
DataWidth => 8,
AddressRange => 4097,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_val_0_2_address0,
ce0 => k_buf_val_val_0_2_ce0,
q0 => k_buf_val_val_0_2_q0,
address1 => k_buf_val_val_0_2_ad_reg_3059_pp0_iter42_reg,
ce1 => k_buf_val_val_0_2_ce1,
we1 => k_buf_val_val_0_2_we1,
d1 => k_buf_val_val_0_2_d1);
k_buf_val_val_1_0_U : component Resize_opr_linearbkb
generic map (
DataWidth => 8,
AddressRange => 4097,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_val_1_0_address0,
ce0 => k_buf_val_val_1_0_ce0,
q0 => k_buf_val_val_1_0_q0,
address1 => k_buf_val_val_1_0_address1,
ce1 => k_buf_val_val_1_0_ce1,
we1 => k_buf_val_val_1_0_we1,
d1 => win_val_1_val_0_0_reg_3092);
k_buf_val_val_1_1_U : component Resize_opr_linearbkb
generic map (
DataWidth => 8,
AddressRange => 4097,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_val_1_1_address0,
ce0 => k_buf_val_val_1_1_ce0,
q0 => k_buf_val_val_1_1_q0,
address1 => k_buf_val_val_1_1_address1,
ce1 => k_buf_val_val_1_1_ce1,
we1 => k_buf_val_val_1_1_we1,
d1 => win_val_1_val_0_1_reg_3097);
k_buf_val_val_1_2_U : component Resize_opr_linearbkb
generic map (
DataWidth => 8,
AddressRange => 4097,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_val_val_1_2_address0,
ce0 => k_buf_val_val_1_2_ce0,
q0 => k_buf_val_val_1_2_q0,
address1 => k_buf_val_val_1_2_address1,
ce1 => k_buf_val_val_1_2_ce1,
we1 => k_buf_val_val_1_2_we1,
d1 => win_val_1_val_0_2_reg_3102);
video_scaler_sdivhbi_U23 : component video_scaler_sdivhbi
generic map (
ID => 1,
NUM_STAGE => 52,
din0_WIDTH => 48,
din1_WIDTH => 32,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
start => grp_fu_684_ap_start,
done => grp_fu_684_ap_done,
din0 => grp_fu_684_p0,
din1 => tmp_16_fu_666_p2,
ce => ap_const_logic_1,
dout => grp_fu_684_p2);
video_scaler_sdivhbi_U24 : component video_scaler_sdivhbi
generic map (
ID => 1,
NUM_STAGE => 52,
din0_WIDTH => 48,
din1_WIDTH => 32,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
start => grp_fu_708_ap_start,
done => grp_fu_708_ap_done,
din0 => grp_fu_708_p0,
din1 => tmp_42_fu_690_p2,
ce => ap_const_logic_1,
dout => grp_fu_708_p2);
video_scaler_udivibs_U25 : component video_scaler_udivibs
generic map (
ID => 1,
NUM_STAGE => 35,
din0_WIDTH => 31,
din1_WIDTH => 32,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1099_p0,
din1 => row_rate_V_reg_2703,
ce => grp_fu_1099_ce,
dout => grp_fu_1099_p2);
video_scaler_udivibs_U26 : component video_scaler_udivibs
generic map (
ID => 1,
NUM_STAGE => 35,
din0_WIDTH => 31,
din1_WIDTH => 32,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1115_p0,
din1 => col_rate_V_reg_2711,
ce => grp_fu_1115_ce,
dout => grp_fu_1115_p2);
video_scaler_mul_jbC_U27 : component video_scaler_mul_jbC
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 32,
din1_WIDTH => 16,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => row_rate_V_reg_2703,
din1 => ap_phi_reg_pp0_iter36_dy_reg_557,
ce => grp_fu_1147_ce,
dout => grp_fu_1147_p2);
video_scaler_mul_jbC_U28 : component video_scaler_mul_jbC
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 32,
din1_WIDTH => 16,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => col_rate_V_reg_2711,
din1 => ap_phi_reg_pp0_iter36_dx_reg_566,
ce => grp_fu_1156_ce,
dout => grp_fu_1156_p2);
video_scaler_mul_kbM_U29 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_reg_3170,
din1 => grp_fu_1809_p1,
ce => grp_fu_1809_ce,
dout => grp_fu_1809_p2);
video_scaler_mul_kbM_U30 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_3_reg_3175,
din1 => grp_fu_1827_p1,
ce => grp_fu_1827_ce,
dout => grp_fu_1827_p2);
video_scaler_mul_kbM_U31 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_s_reg_3180,
din1 => grp_fu_1836_p1,
ce => grp_fu_1836_ce,
dout => grp_fu_1836_p2);
video_scaler_mul_kbM_U32 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_3_1_reg_3185,
din1 => grp_fu_1851_p1,
ce => grp_fu_1851_ce,
dout => grp_fu_1851_p2);
video_scaler_mul_kbM_U33 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_4_reg_3190,
din1 => grp_fu_1860_p1,
ce => grp_fu_1860_ce,
dout => grp_fu_1860_p2);
video_scaler_mul_kbM_U34 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_3_2_reg_3195,
din1 => grp_fu_1875_p1,
ce => grp_fu_1875_ce,
dout => grp_fu_1875_p2);
video_scaler_mul_kbM_U35 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_1_reg_3212,
din1 => grp_fu_1887_p1,
ce => grp_fu_1887_ce,
dout => grp_fu_1887_p2);
video_scaler_mul_kbM_U36 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_2_reg_3217,
din1 => grp_fu_1896_p1,
ce => grp_fu_1896_ce,
dout => grp_fu_1896_p2);
video_scaler_mul_kbM_U37 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_1_1_reg_3242,
din1 => grp_fu_1904_p1,
ce => grp_fu_1904_ce,
dout => grp_fu_1904_p2);
video_scaler_mul_kbM_U38 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_2_1_reg_3247,
din1 => grp_fu_1913_p1,
ce => grp_fu_1913_ce,
dout => grp_fu_1913_p2);
video_scaler_mul_kbM_U39 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_1_2_reg_3262,
din1 => grp_fu_1921_p1,
ce => grp_fu_1921_ce,
dout => grp_fu_1921_p2);
video_scaler_mul_kbM_U40 : component video_scaler_mul_kbM
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 28,
din1_WIDTH => 20,
dout_WIDTH => 48)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_2_2_reg_3267,
din1 => grp_fu_1930_p1,
ce => grp_fu_1930_ce,
dout => grp_fu_1930_p2);
video_scaler_mul_lbW_U41 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_fu_2451_p0,
din1 => r_V_fu_2451_p1,
dout => r_V_fu_2451_p2);
video_scaler_mul_lbW_U42 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_3_fu_2457_p0,
din1 => r_V_3_fu_2457_p1,
dout => r_V_3_fu_2457_p2);
video_scaler_mul_lbW_U43 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_s_fu_2463_p0,
din1 => r_V_s_fu_2463_p1,
dout => r_V_s_fu_2463_p2);
video_scaler_mul_lbW_U44 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_3_1_fu_2469_p0,
din1 => r_V_3_1_fu_2469_p1,
dout => r_V_3_1_fu_2469_p2);
video_scaler_mul_lbW_U45 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_4_fu_2475_p0,
din1 => r_V_4_fu_2475_p1,
dout => r_V_4_fu_2475_p2);
video_scaler_mul_lbW_U46 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_3_2_fu_2481_p0,
din1 => r_V_3_2_fu_2481_p1,
dout => r_V_3_2_fu_2481_p2);
video_scaler_mul_lbW_U47 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_1_fu_2487_p0,
din1 => r_V_1_fu_2487_p1,
dout => r_V_1_fu_2487_p2);
video_scaler_mul_lbW_U48 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_2_fu_2493_p0,
din1 => r_V_2_fu_2493_p1,
dout => r_V_2_fu_2493_p2);
video_scaler_mul_lbW_U49 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_1_1_fu_2498_p0,
din1 => r_V_1_1_fu_2498_p1,
dout => r_V_1_1_fu_2498_p2);
video_scaler_mul_lbW_U50 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_2_1_fu_2504_p0,
din1 => r_V_2_1_fu_2504_p1,
dout => r_V_2_1_fu_2504_p2);
video_scaler_mul_lbW_U51 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_1_2_fu_2509_p0,
din1 => r_V_1_2_fu_2509_p1,
dout => r_V_1_2_fu_2509_p2);
video_scaler_mul_lbW_U52 : component video_scaler_mul_lbW
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => r_V_2_2_fu_2515_p0,
din1 => r_V_2_2_fu_2515_p1,
dout => r_V_2_2_fu_2515_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((tmp_31_fu_1088_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state55) and (tmp_27_fu_1043_p2 = ap_const_lv1_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter11 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter12 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter13 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter14 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter15 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter16 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter17 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter18 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter19 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter20 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter21 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter22 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter23 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter24 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter25 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter25 <= ap_enable_reg_pp0_iter24;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter26 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter26 <= ap_enable_reg_pp0_iter25;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter27 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter27 <= ap_enable_reg_pp0_iter26;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter28 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter28 <= ap_enable_reg_pp0_iter27;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter29 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter29 <= ap_enable_reg_pp0_iter28;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter30 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter30 <= ap_enable_reg_pp0_iter29;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter31 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter31 <= ap_enable_reg_pp0_iter30;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter32 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter32 <= ap_enable_reg_pp0_iter31;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter33 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter33 <= ap_enable_reg_pp0_iter32;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter34_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter34 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter34 <= ap_enable_reg_pp0_iter33;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter35_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter35 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter35 <= ap_enable_reg_pp0_iter34;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter36_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter36 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter36 <= ap_enable_reg_pp0_iter35;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter37_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter37 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter37 <= ap_enable_reg_pp0_iter36;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter38_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter38 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter38 <= ap_enable_reg_pp0_iter37;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter39_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter39 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter39 <= ap_enable_reg_pp0_iter38;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter40_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter40 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter40 <= ap_enable_reg_pp0_iter39;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter41_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter41 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter41 <= ap_enable_reg_pp0_iter40;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter42_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter42 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter42 <= ap_enable_reg_pp0_iter41;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter43_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter43 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter42_state98)) then
ap_enable_reg_pp0_iter43 <= ap_enable_reg_pp0_iter41;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter43 <= ap_enable_reg_pp0_iter42;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter44_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter44 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter44 <= ap_enable_reg_pp0_iter43;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter45_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter45 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter45 <= ap_enable_reg_pp0_iter44;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter46_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter46 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter46 <= ap_enable_reg_pp0_iter45;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter47_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter47 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter47 <= ap_enable_reg_pp0_iter46;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter48_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter48 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter48 <= ap_enable_reg_pp0_iter47;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter49_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter49 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter49 <= ap_enable_reg_pp0_iter48;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter50_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter50 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter50 <= ap_enable_reg_pp0_iter49;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter51_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter51 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter51 <= ap_enable_reg_pp0_iter50;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter52_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter52 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter52 <= ap_enable_reg_pp0_iter51;
elsif (((ap_const_logic_1 = ap_CS_fsm_state55) and (tmp_27_fu_1043_p2 = ap_const_lv1_1))) then
ap_enable_reg_pp0_iter52 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter1_dy_reg_557_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_428)) then
if (((tmp_23_reg_2792 = ap_const_lv1_0) and (tmp_31_fu_1088_p2 = ap_const_lv1_1))) then
ap_phi_reg_pp0_iter1_dy_reg_557 <= tmp_28_reg_2823;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter1_dy_reg_557 <= ap_phi_reg_pp0_iter0_dy_reg_557;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter36_dx_reg_566_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter35 = ap_const_logic_1))) then
if (((tmp_24_reg_2797 = ap_const_lv1_0) and (tmp_31_reg_2851_pp0_iter34_reg = ap_const_lv1_1))) then
ap_phi_reg_pp0_iter36_dx_reg_566 <= tmp_36_fu_1135_p2;
elsif (((tmp_31_reg_2851_pp0_iter34_reg = ap_const_lv1_1) and (tmp_24_reg_2797 = ap_const_lv1_1))) then
ap_phi_reg_pp0_iter36_dx_reg_566 <= tmp_72_fu_1140_p1;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter36_dx_reg_566 <= ap_phi_reg_pp0_iter35_dx_reg_566;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter36_dy_reg_557_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter35 = ap_const_logic_1))) then
if (((tmp_31_reg_2851_pp0_iter34_reg = ap_const_lv1_1) and (tmp_23_reg_2792 = ap_const_lv1_1))) then
ap_phi_reg_pp0_iter36_dy_reg_557 <= tmp_71_fu_1132_p1;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter36_dy_reg_557 <= ap_phi_reg_pp0_iter35_dy_reg_557;
end if;
end if;
end if;
end process;
p_Val2_16_reg_535_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state109)) then
p_Val2_16_reg_535 <= i_reg_2818;
elsif ((ap_const_logic_1 = ap_CS_fsm_state54)) then
p_Val2_16_reg_535 <= ap_const_lv15_0;
end if;
end if;
end process;
p_Val2_17_reg_546_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (tmp_31_fu_1088_p2 = ap_const_lv1_1))) then
p_Val2_17_reg_546 <= j_fu_1093_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state55) and (tmp_27_fu_1043_p2 = ap_const_lv1_1))) then
p_Val2_17_reg_546 <= ap_const_lv15_0;
end if;
end if;
end process;
pre_fx_fu_238_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
pre_fx_fu_238 <= pre_fx_5_fu_1474_p3;
elsif (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
pre_fx_fu_238 <= ap_const_lv16_FFF6;
end if;
end if;
end process;
pre_fy_fu_242_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
pre_fy_fu_242 <= pre_fy_5_fu_1417_p3;
elsif (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
pre_fy_fu_242 <= ap_const_lv16_FFF6;
end if;
end if;
end process;
row_rd_fu_234_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
row_rd_fu_234 <= row_rd_5_fu_1442_p3;
elsif (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
row_rd_fu_234 <= ap_const_lv1_0;
end if;
end if;
end process;
row_wr_fu_230_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
row_wr_fu_230 <= row_wr_3_fu_1456_p3;
elsif (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
row_wr_fu_230 <= ap_const_lv1_0;
end if;
end if;
end process;
win_val_0_val_1_0_fu_258_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1))) then
win_val_0_val_1_0_fu_258 <= p_src_data_stream_0_V_dout;
elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (row_rd_5_reg_3002 = ap_const_lv1_0) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_53_reg_3065 = ap_const_lv1_0) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1)))) then
win_val_0_val_1_0_fu_258 <= k_buf_val_val_0_0_q0;
end if;
end if;
end process;
win_val_0_val_1_1_fu_262_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1))) then
win_val_0_val_1_1_fu_262 <= p_src_data_stream_1_V_dout;
elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (row_rd_5_reg_3002 = ap_const_lv1_0) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_53_reg_3065 = ap_const_lv1_0) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1)))) then
win_val_0_val_1_1_fu_262 <= k_buf_val_val_0_1_q0;
end if;
end if;
end process;
win_val_0_val_1_2_fu_266_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1))) then
win_val_0_val_1_2_fu_266 <= p_src_data_stream_2_V_dout;
elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (row_rd_5_reg_3002 = ap_const_lv1_0) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_53_reg_3065 = ap_const_lv1_0) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1)))) then
win_val_0_val_1_2_fu_266 <= k_buf_val_val_0_2_q0;
end if;
end if;
end process;
x_fu_246_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
x_fu_246 <= x_1_fu_1538_p2;
elsif (((col_rd_2_fu_1486_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
x_fu_246 <= x_2_fu_1398_p3;
elsif (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
x_fu_246 <= ap_const_lv16_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (brmerge_demorgan_reg_3077_pp0_iter43_reg = ap_const_lv1_1))) then
OP2_V_6_reg_3222(47 downto 2) <= OP2_V_6_fu_1821_p1(47 downto 2);
r_V_1_1_reg_3242 <= r_V_1_1_fu_2498_p2;
r_V_1_2_reg_3262 <= r_V_1_2_fu_2509_p2;
r_V_1_reg_3212 <= r_V_1_fu_2487_p2;
r_V_2_1_reg_3247 <= r_V_2_1_fu_2504_p2;
r_V_2_2_reg_3267 <= r_V_2_2_fu_2515_p2;
r_V_2_reg_3217 <= r_V_2_fu_2493_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (brmerge_demorgan_reg_3077_pp0_iter42_reg = ap_const_lv1_1))) then
OP2_V_reg_3163(27 downto 2) <= OP2_V_fu_1770_p1(27 downto 2);
r_V_3_1_reg_3185 <= r_V_3_1_fu_2469_p2;
r_V_3_2_reg_3195 <= r_V_3_2_fu_2481_p2;
r_V_3_reg_3175 <= r_V_3_fu_2457_p2;
r_V_4_reg_3190 <= r_V_4_fu_2475_p2;
r_V_reg_3170 <= r_V_fu_2451_p2;
r_V_s_reg_3180 <= r_V_s_fu_2463_p2;
win_val_0_val_1_0_4_reg_3133 <= win_val_0_val_1_0_1_fu_270;
win_val_0_val_1_1_4_reg_3138 <= win_val_0_val_1_1_1_fu_274;
win_val_0_val_1_2_4_reg_3143 <= win_val_0_val_1_2_1_fu_278;
win_val_1_val_1_0_3_reg_3148 <= win_val_1_val_1_0_fu_282;
win_val_1_val_1_1_3_reg_3153 <= win_val_1_val_1_1_fu_286;
win_val_1_val_1_2_3_reg_3158 <= win_val_1_val_1_2_fu_290;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter9 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter10_dx_reg_566 <= ap_phi_reg_pp0_iter9_dx_reg_566;
ap_phi_reg_pp0_iter10_dy_reg_557 <= ap_phi_reg_pp0_iter9_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter10 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter11_dx_reg_566 <= ap_phi_reg_pp0_iter10_dx_reg_566;
ap_phi_reg_pp0_iter11_dy_reg_557 <= ap_phi_reg_pp0_iter10_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter11 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter12_dx_reg_566 <= ap_phi_reg_pp0_iter11_dx_reg_566;
ap_phi_reg_pp0_iter12_dy_reg_557 <= ap_phi_reg_pp0_iter11_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter12 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter13_dx_reg_566 <= ap_phi_reg_pp0_iter12_dx_reg_566;
ap_phi_reg_pp0_iter13_dy_reg_557 <= ap_phi_reg_pp0_iter12_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter13 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter14_dx_reg_566 <= ap_phi_reg_pp0_iter13_dx_reg_566;
ap_phi_reg_pp0_iter14_dy_reg_557 <= ap_phi_reg_pp0_iter13_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter14 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter15_dx_reg_566 <= ap_phi_reg_pp0_iter14_dx_reg_566;
ap_phi_reg_pp0_iter15_dy_reg_557 <= ap_phi_reg_pp0_iter14_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter15 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter16_dx_reg_566 <= ap_phi_reg_pp0_iter15_dx_reg_566;
ap_phi_reg_pp0_iter16_dy_reg_557 <= ap_phi_reg_pp0_iter15_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter16 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter17_dx_reg_566 <= ap_phi_reg_pp0_iter16_dx_reg_566;
ap_phi_reg_pp0_iter17_dy_reg_557 <= ap_phi_reg_pp0_iter16_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter17 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter18_dx_reg_566 <= ap_phi_reg_pp0_iter17_dx_reg_566;
ap_phi_reg_pp0_iter18_dy_reg_557 <= ap_phi_reg_pp0_iter17_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter18 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter19_dx_reg_566 <= ap_phi_reg_pp0_iter18_dx_reg_566;
ap_phi_reg_pp0_iter19_dy_reg_557 <= ap_phi_reg_pp0_iter18_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_reg_pp0_iter1_dx_reg_566 <= ap_phi_reg_pp0_iter0_dx_reg_566;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter19 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter20_dx_reg_566 <= ap_phi_reg_pp0_iter19_dx_reg_566;
ap_phi_reg_pp0_iter20_dy_reg_557 <= ap_phi_reg_pp0_iter19_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter20 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter21_dx_reg_566 <= ap_phi_reg_pp0_iter20_dx_reg_566;
ap_phi_reg_pp0_iter21_dy_reg_557 <= ap_phi_reg_pp0_iter20_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter21 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter22_dx_reg_566 <= ap_phi_reg_pp0_iter21_dx_reg_566;
ap_phi_reg_pp0_iter22_dy_reg_557 <= ap_phi_reg_pp0_iter21_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter22 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter23_dx_reg_566 <= ap_phi_reg_pp0_iter22_dx_reg_566;
ap_phi_reg_pp0_iter23_dy_reg_557 <= ap_phi_reg_pp0_iter22_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter23 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter24_dx_reg_566 <= ap_phi_reg_pp0_iter23_dx_reg_566;
ap_phi_reg_pp0_iter24_dy_reg_557 <= ap_phi_reg_pp0_iter23_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter25_dx_reg_566 <= ap_phi_reg_pp0_iter24_dx_reg_566;
ap_phi_reg_pp0_iter25_dy_reg_557 <= ap_phi_reg_pp0_iter24_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter25 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter26_dx_reg_566 <= ap_phi_reg_pp0_iter25_dx_reg_566;
ap_phi_reg_pp0_iter26_dy_reg_557 <= ap_phi_reg_pp0_iter25_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter26 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter27_dx_reg_566 <= ap_phi_reg_pp0_iter26_dx_reg_566;
ap_phi_reg_pp0_iter27_dy_reg_557 <= ap_phi_reg_pp0_iter26_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter27 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter28_dx_reg_566 <= ap_phi_reg_pp0_iter27_dx_reg_566;
ap_phi_reg_pp0_iter28_dy_reg_557 <= ap_phi_reg_pp0_iter27_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter28 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter29_dx_reg_566 <= ap_phi_reg_pp0_iter28_dx_reg_566;
ap_phi_reg_pp0_iter29_dy_reg_557 <= ap_phi_reg_pp0_iter28_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter2_dx_reg_566 <= ap_phi_reg_pp0_iter1_dx_reg_566;
ap_phi_reg_pp0_iter2_dy_reg_557 <= ap_phi_reg_pp0_iter1_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter29 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter30_dx_reg_566 <= ap_phi_reg_pp0_iter29_dx_reg_566;
ap_phi_reg_pp0_iter30_dy_reg_557 <= ap_phi_reg_pp0_iter29_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter30 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter31_dx_reg_566 <= ap_phi_reg_pp0_iter30_dx_reg_566;
ap_phi_reg_pp0_iter31_dy_reg_557 <= ap_phi_reg_pp0_iter30_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter31 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter32_dx_reg_566 <= ap_phi_reg_pp0_iter31_dx_reg_566;
ap_phi_reg_pp0_iter32_dy_reg_557 <= ap_phi_reg_pp0_iter31_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter32 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter33_dx_reg_566 <= ap_phi_reg_pp0_iter32_dx_reg_566;
ap_phi_reg_pp0_iter33_dy_reg_557 <= ap_phi_reg_pp0_iter32_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter33 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter34_dx_reg_566 <= ap_phi_reg_pp0_iter33_dx_reg_566;
ap_phi_reg_pp0_iter34_dy_reg_557 <= ap_phi_reg_pp0_iter33_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter34 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter35_dx_reg_566 <= ap_phi_reg_pp0_iter34_dx_reg_566;
ap_phi_reg_pp0_iter35_dy_reg_557 <= ap_phi_reg_pp0_iter34_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter3_dx_reg_566 <= ap_phi_reg_pp0_iter2_dx_reg_566;
ap_phi_reg_pp0_iter3_dy_reg_557 <= ap_phi_reg_pp0_iter2_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter4_dx_reg_566 <= ap_phi_reg_pp0_iter3_dx_reg_566;
ap_phi_reg_pp0_iter4_dy_reg_557 <= ap_phi_reg_pp0_iter3_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter5_dx_reg_566 <= ap_phi_reg_pp0_iter4_dx_reg_566;
ap_phi_reg_pp0_iter5_dy_reg_557 <= ap_phi_reg_pp0_iter4_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter6_dx_reg_566 <= ap_phi_reg_pp0_iter5_dx_reg_566;
ap_phi_reg_pp0_iter6_dy_reg_557 <= ap_phi_reg_pp0_iter5_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter6 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter7_dx_reg_566 <= ap_phi_reg_pp0_iter6_dx_reg_566;
ap_phi_reg_pp0_iter7_dy_reg_557 <= ap_phi_reg_pp0_iter6_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter7 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter8_dx_reg_566 <= ap_phi_reg_pp0_iter7_dx_reg_566;
ap_phi_reg_pp0_iter8_dy_reg_557 <= ap_phi_reg_pp0_iter7_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter8 = ap_const_logic_1))) then
ap_phi_reg_pp0_iter9_dx_reg_566 <= ap_phi_reg_pp0_iter8_dx_reg_566;
ap_phi_reg_pp0_iter9_dy_reg_557 <= ap_phi_reg_pp0_iter8_dy_reg_557;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
brmerge_demorgan_reg_3077 <= brmerge_demorgan_fu_1549_p2;
col_rd_2_reg_3006 <= col_rd_2_fu_1486_p2;
row_rd_5_reg_3002 <= row_rd_5_fu_1442_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
brmerge_demorgan_reg_3077_pp0_iter42_reg <= brmerge_demorgan_reg_3077;
brmerge_demorgan_reg_3077_pp0_iter43_reg <= brmerge_demorgan_reg_3077_pp0_iter42_reg;
brmerge_demorgan_reg_3077_pp0_iter44_reg <= brmerge_demorgan_reg_3077_pp0_iter43_reg;
brmerge_demorgan_reg_3077_pp0_iter45_reg <= brmerge_demorgan_reg_3077_pp0_iter44_reg;
brmerge_demorgan_reg_3077_pp0_iter46_reg <= brmerge_demorgan_reg_3077_pp0_iter45_reg;
brmerge_demorgan_reg_3077_pp0_iter47_reg <= brmerge_demorgan_reg_3077_pp0_iter46_reg;
brmerge_demorgan_reg_3077_pp0_iter48_reg <= brmerge_demorgan_reg_3077_pp0_iter47_reg;
brmerge_demorgan_reg_3077_pp0_iter49_reg <= brmerge_demorgan_reg_3077_pp0_iter48_reg;
brmerge_demorgan_reg_3077_pp0_iter50_reg <= brmerge_demorgan_reg_3077_pp0_iter49_reg;
brmerge_demorgan_reg_3077_pp0_iter51_reg <= brmerge_demorgan_reg_3077_pp0_iter50_reg;
col_rd_2_reg_3006_pp0_iter42_reg <= col_rd_2_reg_3006;
col_wr_1_reg_2877_pp0_iter10_reg <= col_wr_1_reg_2877_pp0_iter9_reg;
col_wr_1_reg_2877_pp0_iter11_reg <= col_wr_1_reg_2877_pp0_iter10_reg;
col_wr_1_reg_2877_pp0_iter12_reg <= col_wr_1_reg_2877_pp0_iter11_reg;
col_wr_1_reg_2877_pp0_iter13_reg <= col_wr_1_reg_2877_pp0_iter12_reg;
col_wr_1_reg_2877_pp0_iter14_reg <= col_wr_1_reg_2877_pp0_iter13_reg;
col_wr_1_reg_2877_pp0_iter15_reg <= col_wr_1_reg_2877_pp0_iter14_reg;
col_wr_1_reg_2877_pp0_iter16_reg <= col_wr_1_reg_2877_pp0_iter15_reg;
col_wr_1_reg_2877_pp0_iter17_reg <= col_wr_1_reg_2877_pp0_iter16_reg;
col_wr_1_reg_2877_pp0_iter18_reg <= col_wr_1_reg_2877_pp0_iter17_reg;
col_wr_1_reg_2877_pp0_iter19_reg <= col_wr_1_reg_2877_pp0_iter18_reg;
col_wr_1_reg_2877_pp0_iter20_reg <= col_wr_1_reg_2877_pp0_iter19_reg;
col_wr_1_reg_2877_pp0_iter21_reg <= col_wr_1_reg_2877_pp0_iter20_reg;
col_wr_1_reg_2877_pp0_iter22_reg <= col_wr_1_reg_2877_pp0_iter21_reg;
col_wr_1_reg_2877_pp0_iter23_reg <= col_wr_1_reg_2877_pp0_iter22_reg;
col_wr_1_reg_2877_pp0_iter24_reg <= col_wr_1_reg_2877_pp0_iter23_reg;
col_wr_1_reg_2877_pp0_iter25_reg <= col_wr_1_reg_2877_pp0_iter24_reg;
col_wr_1_reg_2877_pp0_iter26_reg <= col_wr_1_reg_2877_pp0_iter25_reg;
col_wr_1_reg_2877_pp0_iter27_reg <= col_wr_1_reg_2877_pp0_iter26_reg;
col_wr_1_reg_2877_pp0_iter28_reg <= col_wr_1_reg_2877_pp0_iter27_reg;
col_wr_1_reg_2877_pp0_iter29_reg <= col_wr_1_reg_2877_pp0_iter28_reg;
col_wr_1_reg_2877_pp0_iter2_reg <= col_wr_1_reg_2877_pp0_iter1_reg;
col_wr_1_reg_2877_pp0_iter30_reg <= col_wr_1_reg_2877_pp0_iter29_reg;
col_wr_1_reg_2877_pp0_iter31_reg <= col_wr_1_reg_2877_pp0_iter30_reg;
col_wr_1_reg_2877_pp0_iter32_reg <= col_wr_1_reg_2877_pp0_iter31_reg;
col_wr_1_reg_2877_pp0_iter33_reg <= col_wr_1_reg_2877_pp0_iter32_reg;
col_wr_1_reg_2877_pp0_iter34_reg <= col_wr_1_reg_2877_pp0_iter33_reg;
col_wr_1_reg_2877_pp0_iter35_reg <= col_wr_1_reg_2877_pp0_iter34_reg;
col_wr_1_reg_2877_pp0_iter36_reg <= col_wr_1_reg_2877_pp0_iter35_reg;
col_wr_1_reg_2877_pp0_iter37_reg <= col_wr_1_reg_2877_pp0_iter36_reg;
col_wr_1_reg_2877_pp0_iter38_reg <= col_wr_1_reg_2877_pp0_iter37_reg;
col_wr_1_reg_2877_pp0_iter39_reg <= col_wr_1_reg_2877_pp0_iter38_reg;
col_wr_1_reg_2877_pp0_iter3_reg <= col_wr_1_reg_2877_pp0_iter2_reg;
col_wr_1_reg_2877_pp0_iter40_reg <= col_wr_1_reg_2877_pp0_iter39_reg;
col_wr_1_reg_2877_pp0_iter4_reg <= col_wr_1_reg_2877_pp0_iter3_reg;
col_wr_1_reg_2877_pp0_iter5_reg <= col_wr_1_reg_2877_pp0_iter4_reg;
col_wr_1_reg_2877_pp0_iter6_reg <= col_wr_1_reg_2877_pp0_iter5_reg;
col_wr_1_reg_2877_pp0_iter7_reg <= col_wr_1_reg_2877_pp0_iter6_reg;
col_wr_1_reg_2877_pp0_iter8_reg <= col_wr_1_reg_2877_pp0_iter7_reg;
col_wr_1_reg_2877_pp0_iter9_reg <= col_wr_1_reg_2877_pp0_iter8_reg;
i_op_assign_cast_reg_2845_pp0_iter10_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter9_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter11_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter10_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter12_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter11_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter13_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter12_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter14_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter13_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter15_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter14_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter16_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter15_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter17_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter16_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter18_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter17_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter19_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter18_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter20_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter19_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter21_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter20_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter22_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter21_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter23_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter22_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter24_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter23_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter25_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter24_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter26_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter25_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter27_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter26_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter28_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter27_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter29_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter28_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter2_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter1_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter30_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter29_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter31_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter30_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter32_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter31_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter33_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter32_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter34_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter33_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter35_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter34_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter36_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter35_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter37_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter36_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter38_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter37_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter39_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter38_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter3_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter2_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter4_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter3_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter5_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter4_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter6_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter5_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter7_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter6_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter8_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter7_reg(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter9_reg(14 downto 0) <= i_op_assign_cast_reg_2845_pp0_iter8_reg(14 downto 0);
k_buf_val_val_0_0_ad_reg_3047_pp0_iter42_reg <= k_buf_val_val_0_0_ad_reg_3047;
k_buf_val_val_0_1_ad_reg_3053_pp0_iter42_reg <= k_buf_val_val_0_1_ad_reg_3053;
k_buf_val_val_0_2_ad_reg_3059_pp0_iter42_reg <= k_buf_val_val_0_2_ad_reg_3059;
p_u_V_reg_3086_pp0_iter43_reg(19 downto 2) <= p_u_V_reg_3086(19 downto 2);
p_u_V_reg_3086_pp0_iter44_reg(19 downto 2) <= p_u_V_reg_3086_pp0_iter43_reg(19 downto 2);
row_rd_5_reg_3002_pp0_iter42_reg <= row_rd_5_reg_3002;
signbit_1_reg_3422_pp0_iter51_reg <= signbit_1_reg_3422;
signbit_2_reg_3450_pp0_iter51_reg <= signbit_2_reg_3450;
signbit_reg_3394_pp0_iter51_reg <= signbit_reg_3394;
tmp_31_reg_2851_pp0_iter10_reg <= tmp_31_reg_2851_pp0_iter9_reg;
tmp_31_reg_2851_pp0_iter11_reg <= tmp_31_reg_2851_pp0_iter10_reg;
tmp_31_reg_2851_pp0_iter12_reg <= tmp_31_reg_2851_pp0_iter11_reg;
tmp_31_reg_2851_pp0_iter13_reg <= tmp_31_reg_2851_pp0_iter12_reg;
tmp_31_reg_2851_pp0_iter14_reg <= tmp_31_reg_2851_pp0_iter13_reg;
tmp_31_reg_2851_pp0_iter15_reg <= tmp_31_reg_2851_pp0_iter14_reg;
tmp_31_reg_2851_pp0_iter16_reg <= tmp_31_reg_2851_pp0_iter15_reg;
tmp_31_reg_2851_pp0_iter17_reg <= tmp_31_reg_2851_pp0_iter16_reg;
tmp_31_reg_2851_pp0_iter18_reg <= tmp_31_reg_2851_pp0_iter17_reg;
tmp_31_reg_2851_pp0_iter19_reg <= tmp_31_reg_2851_pp0_iter18_reg;
tmp_31_reg_2851_pp0_iter20_reg <= tmp_31_reg_2851_pp0_iter19_reg;
tmp_31_reg_2851_pp0_iter21_reg <= tmp_31_reg_2851_pp0_iter20_reg;
tmp_31_reg_2851_pp0_iter22_reg <= tmp_31_reg_2851_pp0_iter21_reg;
tmp_31_reg_2851_pp0_iter23_reg <= tmp_31_reg_2851_pp0_iter22_reg;
tmp_31_reg_2851_pp0_iter24_reg <= tmp_31_reg_2851_pp0_iter23_reg;
tmp_31_reg_2851_pp0_iter25_reg <= tmp_31_reg_2851_pp0_iter24_reg;
tmp_31_reg_2851_pp0_iter26_reg <= tmp_31_reg_2851_pp0_iter25_reg;
tmp_31_reg_2851_pp0_iter27_reg <= tmp_31_reg_2851_pp0_iter26_reg;
tmp_31_reg_2851_pp0_iter28_reg <= tmp_31_reg_2851_pp0_iter27_reg;
tmp_31_reg_2851_pp0_iter29_reg <= tmp_31_reg_2851_pp0_iter28_reg;
tmp_31_reg_2851_pp0_iter2_reg <= tmp_31_reg_2851_pp0_iter1_reg;
tmp_31_reg_2851_pp0_iter30_reg <= tmp_31_reg_2851_pp0_iter29_reg;
tmp_31_reg_2851_pp0_iter31_reg <= tmp_31_reg_2851_pp0_iter30_reg;
tmp_31_reg_2851_pp0_iter32_reg <= tmp_31_reg_2851_pp0_iter31_reg;
tmp_31_reg_2851_pp0_iter33_reg <= tmp_31_reg_2851_pp0_iter32_reg;
tmp_31_reg_2851_pp0_iter34_reg <= tmp_31_reg_2851_pp0_iter33_reg;
tmp_31_reg_2851_pp0_iter35_reg <= tmp_31_reg_2851_pp0_iter34_reg;
tmp_31_reg_2851_pp0_iter36_reg <= tmp_31_reg_2851_pp0_iter35_reg;
tmp_31_reg_2851_pp0_iter37_reg <= tmp_31_reg_2851_pp0_iter36_reg;
tmp_31_reg_2851_pp0_iter38_reg <= tmp_31_reg_2851_pp0_iter37_reg;
tmp_31_reg_2851_pp0_iter39_reg <= tmp_31_reg_2851_pp0_iter38_reg;
tmp_31_reg_2851_pp0_iter3_reg <= tmp_31_reg_2851_pp0_iter2_reg;
tmp_31_reg_2851_pp0_iter40_reg <= tmp_31_reg_2851_pp0_iter39_reg;
tmp_31_reg_2851_pp0_iter41_reg <= tmp_31_reg_2851_pp0_iter40_reg;
tmp_31_reg_2851_pp0_iter42_reg <= tmp_31_reg_2851_pp0_iter41_reg;
tmp_31_reg_2851_pp0_iter4_reg <= tmp_31_reg_2851_pp0_iter3_reg;
tmp_31_reg_2851_pp0_iter5_reg <= tmp_31_reg_2851_pp0_iter4_reg;
tmp_31_reg_2851_pp0_iter6_reg <= tmp_31_reg_2851_pp0_iter5_reg;
tmp_31_reg_2851_pp0_iter7_reg <= tmp_31_reg_2851_pp0_iter6_reg;
tmp_31_reg_2851_pp0_iter8_reg <= tmp_31_reg_2851_pp0_iter7_reg;
tmp_31_reg_2851_pp0_iter9_reg <= tmp_31_reg_2851_pp0_iter8_reg;
tmp_41_reg_2951_pp0_iter41_reg <= tmp_41_reg_2951;
tmp_46_reg_2961_pp0_iter41_reg <= tmp_46_reg_2961;
tmp_46_reg_2961_pp0_iter42_reg <= tmp_46_reg_2961_pp0_iter41_reg;
tmp_48_reg_2971_pp0_iter41_reg <= tmp_48_reg_2971;
tmp_49_reg_2984_pp0_iter41_reg <= tmp_49_reg_2984;
tmp_49_reg_2984_pp0_iter42_reg <= tmp_49_reg_2984_pp0_iter41_reg;
tmp_50_reg_2865_pp0_iter10_reg <= tmp_50_reg_2865_pp0_iter9_reg;
tmp_50_reg_2865_pp0_iter11_reg <= tmp_50_reg_2865_pp0_iter10_reg;
tmp_50_reg_2865_pp0_iter12_reg <= tmp_50_reg_2865_pp0_iter11_reg;
tmp_50_reg_2865_pp0_iter13_reg <= tmp_50_reg_2865_pp0_iter12_reg;
tmp_50_reg_2865_pp0_iter14_reg <= tmp_50_reg_2865_pp0_iter13_reg;
tmp_50_reg_2865_pp0_iter15_reg <= tmp_50_reg_2865_pp0_iter14_reg;
tmp_50_reg_2865_pp0_iter16_reg <= tmp_50_reg_2865_pp0_iter15_reg;
tmp_50_reg_2865_pp0_iter17_reg <= tmp_50_reg_2865_pp0_iter16_reg;
tmp_50_reg_2865_pp0_iter18_reg <= tmp_50_reg_2865_pp0_iter17_reg;
tmp_50_reg_2865_pp0_iter19_reg <= tmp_50_reg_2865_pp0_iter18_reg;
tmp_50_reg_2865_pp0_iter20_reg <= tmp_50_reg_2865_pp0_iter19_reg;
tmp_50_reg_2865_pp0_iter21_reg <= tmp_50_reg_2865_pp0_iter20_reg;
tmp_50_reg_2865_pp0_iter22_reg <= tmp_50_reg_2865_pp0_iter21_reg;
tmp_50_reg_2865_pp0_iter23_reg <= tmp_50_reg_2865_pp0_iter22_reg;
tmp_50_reg_2865_pp0_iter24_reg <= tmp_50_reg_2865_pp0_iter23_reg;
tmp_50_reg_2865_pp0_iter25_reg <= tmp_50_reg_2865_pp0_iter24_reg;
tmp_50_reg_2865_pp0_iter26_reg <= tmp_50_reg_2865_pp0_iter25_reg;
tmp_50_reg_2865_pp0_iter27_reg <= tmp_50_reg_2865_pp0_iter26_reg;
tmp_50_reg_2865_pp0_iter28_reg <= tmp_50_reg_2865_pp0_iter27_reg;
tmp_50_reg_2865_pp0_iter29_reg <= tmp_50_reg_2865_pp0_iter28_reg;
tmp_50_reg_2865_pp0_iter2_reg <= tmp_50_reg_2865_pp0_iter1_reg;
tmp_50_reg_2865_pp0_iter30_reg <= tmp_50_reg_2865_pp0_iter29_reg;
tmp_50_reg_2865_pp0_iter31_reg <= tmp_50_reg_2865_pp0_iter30_reg;
tmp_50_reg_2865_pp0_iter32_reg <= tmp_50_reg_2865_pp0_iter31_reg;
tmp_50_reg_2865_pp0_iter33_reg <= tmp_50_reg_2865_pp0_iter32_reg;
tmp_50_reg_2865_pp0_iter34_reg <= tmp_50_reg_2865_pp0_iter33_reg;
tmp_50_reg_2865_pp0_iter35_reg <= tmp_50_reg_2865_pp0_iter34_reg;
tmp_50_reg_2865_pp0_iter36_reg <= tmp_50_reg_2865_pp0_iter35_reg;
tmp_50_reg_2865_pp0_iter37_reg <= tmp_50_reg_2865_pp0_iter36_reg;
tmp_50_reg_2865_pp0_iter38_reg <= tmp_50_reg_2865_pp0_iter37_reg;
tmp_50_reg_2865_pp0_iter39_reg <= tmp_50_reg_2865_pp0_iter38_reg;
tmp_50_reg_2865_pp0_iter3_reg <= tmp_50_reg_2865_pp0_iter2_reg;
tmp_50_reg_2865_pp0_iter40_reg <= tmp_50_reg_2865_pp0_iter39_reg;
tmp_50_reg_2865_pp0_iter4_reg <= tmp_50_reg_2865_pp0_iter3_reg;
tmp_50_reg_2865_pp0_iter5_reg <= tmp_50_reg_2865_pp0_iter4_reg;
tmp_50_reg_2865_pp0_iter6_reg <= tmp_50_reg_2865_pp0_iter5_reg;
tmp_50_reg_2865_pp0_iter7_reg <= tmp_50_reg_2865_pp0_iter6_reg;
tmp_50_reg_2865_pp0_iter8_reg <= tmp_50_reg_2865_pp0_iter7_reg;
tmp_50_reg_2865_pp0_iter9_reg <= tmp_50_reg_2865_pp0_iter8_reg;
tmp_52_reg_3010_pp0_iter42_reg <= tmp_52_reg_3010;
tmp_53_reg_3065_pp0_iter42_reg <= tmp_53_reg_3065;
tmp_55_reg_3069_pp0_iter42_reg <= tmp_55_reg_3069;
tmp_56_reg_3073_pp0_iter42_reg <= tmp_56_reg_3073;
tmp_77_reg_2956_pp0_iter41_reg <= tmp_77_reg_2956;
tmp_78_reg_2966_pp0_iter41_reg <= tmp_78_reg_2966;
tmp_78_reg_2966_pp0_iter42_reg <= tmp_78_reg_2966_pp0_iter41_reg;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state52)) then
col_rate_V_reg_2711 <= col_rate_V_fu_743_p1;
p_lshr_f1_reg_2734 <= grp_fu_708_p2(31 downto 1);
p_lshr_f_reg_2724 <= grp_fu_684_p2(31 downto 1);
row_rate_V_reg_2703 <= row_rate_V_fu_739_p1;
tmp_54_reg_2719 <= grp_fu_684_p2(31 downto 31);
tmp_68_reg_2729 <= grp_fu_708_p2(31 downto 31);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_24_reg_2797 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (tmp_31_fu_1088_p2 = ap_const_lv1_1))) then
col_wr_1_reg_2877 <= col_wr_1_fu_1126_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
col_wr_1_reg_2877_pp0_iter1_reg <= col_wr_1_reg_2877;
i_op_assign_cast_reg_2845(14 downto 0) <= i_op_assign_cast_fu_1084_p1(14 downto 0);
i_op_assign_cast_reg_2845_pp0_iter1_reg(14 downto 0) <= i_op_assign_cast_reg_2845(14 downto 0);
tmp_31_reg_2851 <= tmp_31_fu_1088_p2;
tmp_31_reg_2851_pp0_iter1_reg <= tmp_31_reg_2851;
tmp_50_reg_2865_pp0_iter1_reg <= tmp_50_reg_2865;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_31_reg_2851_pp0_iter39_reg = ap_const_lv1_1) and (tmp_24_reg_2797 = ap_const_lv1_1))) then
col_wr_reg_2997 <= col_wr_fu_1362_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state54)) then
cols_reg_2764 <= cols_fu_976_p3;
rows_reg_2759 <= rows_fu_960_p3;
sx_reg_2776 <= sx_fu_989_p2;
sy_reg_2787 <= sy_fu_1000_p2;
tmp_21_reg_2769 <= tmp_21_fu_983_p2;
tmp_22_reg_2781 <= tmp_22_fu_994_p2;
tmp_23_reg_2792 <= tmp_23_fu_1005_p2;
tmp_24_reg_2797 <= tmp_24_fu_1010_p2;
tmp_59_cast_reg_2804(31 downto 6) <= tmp_59_cast_fu_1023_p1(31 downto 6);
tmp_61_cast_reg_2809(31 downto 6) <= tmp_61_cast_fu_1035_p1(31 downto 6);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
dcols_reg_2655 <= dcols_fu_650_p1;
drows_reg_2661 <= drows_fu_654_p1;
scols_reg_2675 <= scols_fu_662_p1;
srows_reg_2667 <= srows_fu_658_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state55)) then
i_reg_2818 <= i_fu_1048_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (row_rd_5_fu_1442_p3 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
k_buf_val_val_0_0_ad_reg_3047 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
k_buf_val_val_0_1_ad_reg_3053 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
k_buf_val_val_0_2_ad_reg_3059 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
tmp_53_reg_3065 <= tmp_53_fu_1517_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (brmerge_demorgan_reg_3077_pp0_iter50_reg = ap_const_lv1_1))) then
p_38_i_i_i1_reg_3497 <= p_38_i_i_i1_fu_2199_p2;
p_38_i_i_i2_reg_3515 <= p_38_i_i_i2_fu_2263_p2;
p_38_i_i_i_reg_3479 <= p_38_i_i_i_fu_2135_p2;
p_39_demorgan_i_i_i1_reg_3503 <= p_39_demorgan_i_i_i1_fu_2205_p2;
p_39_demorgan_i_i_i2_reg_3521 <= p_39_demorgan_i_i_i2_fu_2269_p2;
p_39_demorgan_i_i_i_reg_3485 <= p_39_demorgan_i_i_i_fu_2141_p2;
p_Val2_32_reg_3473 <= p_Val2_32_fu_2092_p2;
p_Val2_33_reg_3491 <= p_Val2_33_fu_2156_p2;
p_Val2_36_reg_3509 <= p_Val2_36_fu_2220_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (brmerge_demorgan_reg_3077_pp0_iter49_reg = ap_const_lv1_1))) then
p_Result_6_i_i1_reg_3439 <= p_Val2_44_1_fu_1996_p2(47 downto 44);
p_Result_6_i_i2_reg_3467 <= p_Val2_44_2_fu_2041_p2(47 downto 44);
p_Result_6_i_i_reg_3411 <= p_Val2_30_fu_1951_p2(47 downto 44);
p_Val2_30_reg_3389 <= p_Val2_30_fu_1951_p2;
p_Val2_31_reg_3401 <= p_Val2_30_fu_1951_p2(43 downto 36);
p_Val2_35_reg_3457 <= p_Val2_44_2_fu_2041_p2(43 downto 36);
p_Val2_44_1_reg_3417 <= p_Val2_44_1_fu_1996_p2;
p_Val2_44_2_reg_3445 <= p_Val2_44_2_fu_2041_p2;
p_Val2_s_72_reg_3429 <= p_Val2_44_1_fu_1996_p2(43 downto 36);
signbit_1_reg_3422 <= p_Val2_44_1_fu_1996_p2(47 downto 47);
signbit_2_reg_3450 <= p_Val2_44_2_fu_2041_p2(47 downto 47);
signbit_reg_3394 <= p_Val2_30_fu_1951_p2(47 downto 47);
tmp_83_reg_3406 <= p_Val2_30_fu_1951_p2(35 downto 35);
tmp_87_reg_3434 <= p_Val2_44_1_fu_1996_p2(35 downto 35);
tmp_91_reg_3462 <= p_Val2_44_2_fu_2041_p2(35 downto 35);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_31_reg_2851_pp0_iter37_reg = ap_const_lv1_1))) then
p_Val2_1_reg_2922 <= grp_fu_1156_p2;
p_Val2_s_reg_2917 <= grp_fu_1147_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (brmerge_demorgan_reg_3077_pp0_iter47_reg = ap_const_lv1_1))) then
p_Val2_21_reg_3314 <= grp_fu_1809_p2;
p_Val2_29_reg_3319 <= grp_fu_1827_p2;
p_Val2_40_1_reg_3324 <= grp_fu_1836_p2;
p_Val2_40_2_reg_3334 <= grp_fu_1860_p2;
p_Val2_42_1_reg_3329 <= grp_fu_1851_p2;
p_Val2_42_2_reg_3339 <= grp_fu_1875_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (brmerge_demorgan_reg_3077_pp0_iter48_reg = ap_const_lv1_1))) then
p_Val2_24_reg_3344 <= grp_fu_1887_p2;
p_Val2_28_reg_3349 <= grp_fu_1896_p2;
p_Val2_30_1_reg_3359 <= grp_fu_1904_p2;
p_Val2_30_2_reg_3374 <= grp_fu_1921_p2;
p_Val2_33_1_reg_3364 <= grp_fu_1913_p2;
p_Val2_33_2_reg_3379 <= grp_fu_1930_p2;
tmp69_reg_3354 <= tmp69_fu_1935_p2;
tmp71_reg_3369 <= tmp71_fu_1939_p2;
tmp73_reg_3384 <= tmp73_fu_1943_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_31_reg_2851_pp0_iter38_reg = ap_const_lv1_1))) then
p_Val2_2_reg_2932 <= p_Val2_2_fu_1165_p2;
p_Val2_3_reg_2927 <= p_Val2_3_fu_1161_p2;
sx_2_reg_2937 <= sx_2_fu_1211_p3;
sy_3_reg_2944 <= sy_3_fu_1261_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1))) then
p_u_V_reg_3086(19 downto 2) <= p_u_V_fu_1604_p3(19 downto 2);
u1_V_reg_3081(19 downto 2) <= u1_V_fu_1598_p2(19 downto 2);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_31_reg_2851_pp0_iter39_reg = ap_const_lv1_1))) then
pre_fx_1_reg_2976 <= pre_fx_1_fu_1337_p3;
sy_4_reg_2989 <= sy_4_fu_1351_p3;
tmp_41_reg_2951 <= tmp_41_fu_1289_p2;
tmp_46_reg_2961 <= tmp_46_fu_1319_p2;
tmp_48_reg_2971 <= tmp_48_fu_1332_p2;
tmp_49_reg_2984 <= tmp_49_fu_1346_p2;
tmp_77_reg_2956 <= tmp_77_fu_1295_p1;
tmp_78_reg_2966 <= tmp_78_fu_1325_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state55) and (tmp_27_fu_1043_p2 = ap_const_lv1_1))) then
row_wr_2_reg_2835 <= row_wr_2_fu_1066_p2;
tmp_28_reg_2823 <= tmp_28_fu_1054_p2;
tmp_29_reg_2829 <= tmp_29_fu_1060_p2;
tmp_49_cast_reg_2840(30 downto 16) <= tmp_49_cast_fu_1080_p1(30 downto 16);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state53)) then
tmp_10_reg_2739 <= tmp_10_fu_811_p3;
tmp_14_reg_2749 <= tmp_14_fu_850_p3;
tmp_65_reg_2744 <= tmp_65_fu_818_p1;
tmp_69_reg_2754 <= tmp_69_fu_857_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1))) then
tmp_1_fu_254 <= p_src_data_stream_1_V_dout;
tmp_2_fu_306 <= p_src_data_stream_0_V_dout;
tmp_fu_250 <= p_src_data_stream_2_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_31_reg_2851_pp0_iter33_reg = ap_const_lv1_1) and (tmp_23_reg_2792 = ap_const_lv1_1))) then
tmp_33_reg_2882 <= grp_fu_1099_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_31_reg_2851_pp0_iter33_reg = ap_const_lv1_1) and (tmp_24_reg_2797 = ap_const_lv1_1))) then
tmp_35_reg_2887 <= grp_fu_1115_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (tmp_31_fu_1088_p2 = ap_const_lv1_1))) then
tmp_50_reg_2865 <= tmp_50_fu_1120_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
tmp_52_reg_3010 <= tmp_52_fu_1501_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_53_fu_1517_p2 = ap_const_lv1_1) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (row_rd_5_fu_1442_p3 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))) then
tmp_55_reg_3069 <= tmp_55_fu_1525_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (((tmp_55_fu_1525_p2 = ap_const_lv1_0) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (row_rd_5_fu_1442_p3 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1)) or ((tmp_53_fu_1517_p2 = ap_const_lv1_0) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (row_rd_5_fu_1442_p3 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1))))) then
tmp_56_reg_3073 <= tmp_56_fu_1533_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_97_reg_3107 <= p_src_data_stream_0_V_dout;
tmp_98_reg_3112 <= p_src_data_stream_1_V_dout;
tmp_99_reg_3117 <= p_src_data_stream_2_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1))) then
v1_V_reg_3122(19 downto 2) <= v1_V_fu_1709_p2(19 downto 2);
v_V_reg_3128(19 downto 2) <= v_V_fu_1715_p3(19 downto 2);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1))) then
win_val_0_val_1_0_1_fu_270 <= win_val_0_val_1_0_fu_258;
win_val_0_val_1_1_1_fu_274 <= win_val_0_val_1_1_fu_262;
win_val_0_val_1_2_1_fu_278 <= win_val_0_val_1_2_fu_266;
win_val_1_val_1_0_1_fu_294 <= win_val_1_val_1_0_fu_282;
win_val_1_val_1_0_fu_282 <= ap_phi_mux_win_val_val_1_0_0_2_phi_fu_618_p10;
win_val_1_val_1_1_1_fu_298 <= win_val_1_val_1_1_fu_286;
win_val_1_val_1_1_fu_286 <= ap_phi_mux_win_val_val_1_0_1_2_phi_fu_598_p10;
win_val_1_val_1_2_1_fu_302 <= win_val_1_val_1_2_fu_290;
win_val_1_val_1_2_fu_290 <= ap_phi_mux_win_val_val_1_0_2_2_phi_fu_578_p10;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1))) then
win_val_1_val_0_0_reg_3092 <= k_buf_val_val_0_0_q0;
win_val_1_val_0_1_reg_3097 <= k_buf_val_val_0_1_q0;
win_val_1_val_0_2_reg_3102 <= k_buf_val_val_0_2_q0;
end if;
end if;
end process;
tmp_59_cast_reg_2804(5 downto 0) <= "000000";
tmp_61_cast_reg_2809(5 downto 0) <= "000000";
tmp_49_cast_reg_2840(15 downto 0) <= "0000000000000000";
tmp_49_cast_reg_2840(31) <= '0';
i_op_assign_cast_reg_2845(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter1_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter2_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter3_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter4_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter5_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter6_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter7_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter8_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter9_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter10_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter11_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter12_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter13_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter14_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter15_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter16_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter17_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter18_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter19_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter20_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter21_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter22_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter23_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter24_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter25_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter26_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter27_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter28_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter29_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter30_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter31_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter32_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter33_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter34_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter35_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter36_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter37_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter38_reg(15) <= '0';
i_op_assign_cast_reg_2845_pp0_iter39_reg(15) <= '0';
u1_V_reg_3081(1 downto 0) <= "00";
p_u_V_reg_3086(1 downto 0) <= "00";
p_u_V_reg_3086_pp0_iter43_reg(1 downto 0) <= "00";
p_u_V_reg_3086_pp0_iter44_reg(1 downto 0) <= "00";
v1_V_reg_3122(1 downto 0) <= "00";
v_V_reg_3128(1 downto 0) <= "00";
OP2_V_reg_3163(1 downto 0) <= "00";
OP2_V_6_reg_3222(1 downto 0) <= "00";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter52, tmp_27_fu_1043_p2, ap_CS_fsm_state55, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter41, ap_enable_reg_pp0_iter43, ap_enable_reg_pp0_iter51)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state10;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when ap_ST_fsm_state20 =>
ap_NS_fsm <= ap_ST_fsm_state21;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state27;
when ap_ST_fsm_state27 =>
ap_NS_fsm <= ap_ST_fsm_state28;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state29;
when ap_ST_fsm_state29 =>
ap_NS_fsm <= ap_ST_fsm_state30;
when ap_ST_fsm_state30 =>
ap_NS_fsm <= ap_ST_fsm_state31;
when ap_ST_fsm_state31 =>
ap_NS_fsm <= ap_ST_fsm_state32;
when ap_ST_fsm_state32 =>
ap_NS_fsm <= ap_ST_fsm_state33;
when ap_ST_fsm_state33 =>
ap_NS_fsm <= ap_ST_fsm_state34;
when ap_ST_fsm_state34 =>
ap_NS_fsm <= ap_ST_fsm_state35;
when ap_ST_fsm_state35 =>
ap_NS_fsm <= ap_ST_fsm_state36;
when ap_ST_fsm_state36 =>
ap_NS_fsm <= ap_ST_fsm_state37;
when ap_ST_fsm_state37 =>
ap_NS_fsm <= ap_ST_fsm_state38;
when ap_ST_fsm_state38 =>
ap_NS_fsm <= ap_ST_fsm_state39;
when ap_ST_fsm_state39 =>
ap_NS_fsm <= ap_ST_fsm_state40;
when ap_ST_fsm_state40 =>
ap_NS_fsm <= ap_ST_fsm_state41;
when ap_ST_fsm_state41 =>
ap_NS_fsm <= ap_ST_fsm_state42;
when ap_ST_fsm_state42 =>
ap_NS_fsm <= ap_ST_fsm_state43;
when ap_ST_fsm_state43 =>
ap_NS_fsm <= ap_ST_fsm_state44;
when ap_ST_fsm_state44 =>
ap_NS_fsm <= ap_ST_fsm_state45;
when ap_ST_fsm_state45 =>
ap_NS_fsm <= ap_ST_fsm_state46;
when ap_ST_fsm_state46 =>
ap_NS_fsm <= ap_ST_fsm_state47;
when ap_ST_fsm_state47 =>
ap_NS_fsm <= ap_ST_fsm_state48;
when ap_ST_fsm_state48 =>
ap_NS_fsm <= ap_ST_fsm_state49;
when ap_ST_fsm_state49 =>
ap_NS_fsm <= ap_ST_fsm_state50;
when ap_ST_fsm_state50 =>
ap_NS_fsm <= ap_ST_fsm_state51;
when ap_ST_fsm_state51 =>
ap_NS_fsm <= ap_ST_fsm_state52;
when ap_ST_fsm_state52 =>
ap_NS_fsm <= ap_ST_fsm_state53;
when ap_ST_fsm_state53 =>
ap_NS_fsm <= ap_ST_fsm_state54;
when ap_ST_fsm_state54 =>
ap_NS_fsm <= ap_ST_fsm_state55;
when ap_ST_fsm_state55 =>
if (((tmp_27_fu_1043_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state55))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (ap_enable_reg_pp0_iter43 = ap_const_logic_0) and (ap_enable_reg_pp0_iter41 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) and not(((ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (ap_enable_reg_pp0_iter51 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (ap_enable_reg_pp0_iter51 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (ap_enable_reg_pp0_iter43 = ap_const_logic_0) and (ap_enable_reg_pp0_iter41 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)))) then
ap_NS_fsm <= ap_ST_fsm_state109;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state109 =>
ap_NS_fsm <= ap_ST_fsm_state55;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
OP2_V_1_fu_1800_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(v1_V_reg_3122),48));
OP2_V_2_fu_1803_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(v1_V_reg_3122),28));
OP2_V_5_fu_1884_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(p_u_V_reg_3086_pp0_iter44_reg),48));
OP2_V_6_fu_1821_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(v_V_reg_3128),48));
OP2_V_7_fu_1781_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(p_u_V_reg_3086),28));
OP2_V_fu_1770_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(u1_V_reg_3081),28));
Range1_all_ones_1_fu_2181_p2 <= "1" when (p_Result_6_i_i1_reg_3439 = ap_const_lv4_F) else "0";
Range1_all_ones_2_fu_2245_p2 <= "1" when (p_Result_6_i_i2_reg_3467 = ap_const_lv4_F) else "0";
Range1_all_ones_fu_2117_p2 <= "1" when (p_Result_6_i_i_reg_3411 = ap_const_lv4_F) else "0";
Range1_all_zeros_1_fu_2186_p2 <= "1" when (p_Result_6_i_i1_reg_3439 = ap_const_lv4_0) else "0";
Range1_all_zeros_2_fu_2250_p2 <= "1" when (p_Result_6_i_i2_reg_3467 = ap_const_lv4_0) else "0";
Range1_all_zeros_fu_2122_p2 <= "1" when (p_Result_6_i_i_reg_3411 = ap_const_lv4_0) else "0";
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(55);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state109 <= ap_CS_fsm(56);
ap_CS_fsm_state52 <= ap_CS_fsm(51);
ap_CS_fsm_state53 <= ap_CS_fsm(52);
ap_CS_fsm_state54 <= ap_CS_fsm(53);
ap_CS_fsm_state55 <= ap_CS_fsm(54);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter52, brmerge_demorgan_reg_3077_pp0_iter51_reg, ap_predicate_op564_read_state98)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (((p_dst_data_stream_2_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)) or ((p_dst_data_stream_1_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)) or ((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)))) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter52, brmerge_demorgan_reg_3077_pp0_iter51_reg, ap_predicate_op564_read_state98)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (((p_dst_data_stream_2_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)) or ((p_dst_data_stream_1_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)) or ((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)))) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter52, brmerge_demorgan_reg_3077_pp0_iter51_reg, ap_predicate_op564_read_state98)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (((p_dst_data_stream_2_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)) or ((p_dst_data_stream_1_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)) or ((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)))) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_state100_pp0_stage0_iter44 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state101_pp0_stage0_iter45 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state102_pp0_stage0_iter46 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state103_pp0_stage0_iter47 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state104_pp0_stage0_iter48 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state105_pp0_stage0_iter49 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state106_pp0_stage0_iter50 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state107_pp0_stage0_iter51 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state108_pp0_stage0_iter52_assign_proc : process(p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, brmerge_demorgan_reg_3077_pp0_iter51_reg)
begin
ap_block_state108_pp0_stage0_iter52 <= (((p_dst_data_stream_2_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)) or ((p_dst_data_stream_1_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)) or ((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1)));
end process;
ap_block_state56_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state66_pp0_stage0_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state67_pp0_stage0_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state68_pp0_stage0_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state69_pp0_stage0_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state70_pp0_stage0_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state71_pp0_stage0_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state72_pp0_stage0_iter16 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state73_pp0_stage0_iter17 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state74_pp0_stage0_iter18 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state75_pp0_stage0_iter19 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state76_pp0_stage0_iter20 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state77_pp0_stage0_iter21 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state78_pp0_stage0_iter22 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state79_pp0_stage0_iter23 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state80_pp0_stage0_iter24 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state81_pp0_stage0_iter25 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state82_pp0_stage0_iter26 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state83_pp0_stage0_iter27 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state84_pp0_stage0_iter28 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state85_pp0_stage0_iter29 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state86_pp0_stage0_iter30 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state87_pp0_stage0_iter31 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state88_pp0_stage0_iter32 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state89_pp0_stage0_iter33 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state90_pp0_stage0_iter34 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state91_pp0_stage0_iter35 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state92_pp0_stage0_iter36 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state93_pp0_stage0_iter37 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state94_pp0_stage0_iter38 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state95_pp0_stage0_iter39 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state96_pp0_stage0_iter40 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state97_pp0_stage0_iter41 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state98_pp0_stage0_iter42_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, ap_predicate_op564_read_state98)
begin
ap_block_state98_pp0_stage0_iter42 <= (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_block_state99_pp0_stage0_iter43 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_3380_assign_proc : process(ap_block_pp0_stage0, tmp_31_reg_2851_pp0_iter40_reg, col_rd_2_fu_1486_p2, ap_enable_reg_pp0_iter41)
begin
ap_condition_3380 <= ((ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0));
end process;
ap_condition_3386_assign_proc : process(ap_block_pp0_stage0, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, tmp_53_reg_3065_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
ap_condition_3386 <= ((ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0));
end process;
ap_condition_428_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
begin
ap_condition_428 <= ((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
end process;
ap_condition_pp0_exit_iter42_state98_assign_proc : process(ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter41)
begin
if (((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (ap_enable_reg_pp0_iter41 = ap_const_logic_0))) then
ap_condition_pp0_exit_iter42_state98 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter42_state98 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, tmp_27_fu_1043_p2, ap_CS_fsm_state55)
begin
if ((((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1)) or ((tmp_27_fu_1043_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state55)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter42, ap_enable_reg_pp0_iter52, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter11, ap_enable_reg_pp0_iter12, ap_enable_reg_pp0_iter13, ap_enable_reg_pp0_iter14, ap_enable_reg_pp0_iter15, ap_enable_reg_pp0_iter16, ap_enable_reg_pp0_iter17, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter20, ap_enable_reg_pp0_iter21, ap_enable_reg_pp0_iter22, ap_enable_reg_pp0_iter23, ap_enable_reg_pp0_iter24, ap_enable_reg_pp0_iter25, ap_enable_reg_pp0_iter26, ap_enable_reg_pp0_iter27, ap_enable_reg_pp0_iter28, ap_enable_reg_pp0_iter29, ap_enable_reg_pp0_iter30, ap_enable_reg_pp0_iter31, ap_enable_reg_pp0_iter32, ap_enable_reg_pp0_iter33, ap_enable_reg_pp0_iter34, ap_enable_reg_pp0_iter35, ap_enable_reg_pp0_iter36, ap_enable_reg_pp0_iter37, ap_enable_reg_pp0_iter38, ap_enable_reg_pp0_iter39, ap_enable_reg_pp0_iter40, ap_enable_reg_pp0_iter41, ap_enable_reg_pp0_iter43, ap_enable_reg_pp0_iter44, ap_enable_reg_pp0_iter45, ap_enable_reg_pp0_iter46, ap_enable_reg_pp0_iter47, ap_enable_reg_pp0_iter48, ap_enable_reg_pp0_iter49, ap_enable_reg_pp0_iter50, ap_enable_reg_pp0_iter51)
begin
if (((ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter52 = ap_const_logic_0) and (ap_enable_reg_pp0_iter51 = ap_const_logic_0) and (ap_enable_reg_pp0_iter50 = ap_const_logic_0) and (ap_enable_reg_pp0_iter49 = ap_const_logic_0) and (ap_enable_reg_pp0_iter48 = ap_const_logic_0) and (ap_enable_reg_pp0_iter47 = ap_const_logic_0) and (ap_enable_reg_pp0_iter46 = ap_const_logic_0) and (ap_enable_reg_pp0_iter45 = ap_const_logic_0) and (ap_enable_reg_pp0_iter44 = ap_const_logic_0) and (ap_enable_reg_pp0_iter43 = ap_const_logic_0) and (ap_enable_reg_pp0_iter41 = ap_const_logic_0) and (ap_enable_reg_pp0_iter40 = ap_const_logic_0) and (ap_enable_reg_pp0_iter39 = ap_const_logic_0) and (ap_enable_reg_pp0_iter38 = ap_const_logic_0) and (ap_enable_reg_pp0_iter37 = ap_const_logic_0) and (ap_enable_reg_pp0_iter36 = ap_const_logic_0) and (ap_enable_reg_pp0_iter35 = ap_const_logic_0) and (ap_enable_reg_pp0_iter34 = ap_const_logic_0) and (ap_enable_reg_pp0_iter33 = ap_const_logic_0) and (ap_enable_reg_pp0_iter42 = ap_const_logic_0) and (ap_enable_reg_pp0_iter32 = ap_const_logic_0) and (ap_enable_reg_pp0_iter31 = ap_const_logic_0) and (ap_enable_reg_pp0_iter30 = ap_const_logic_0) and (ap_enable_reg_pp0_iter29 = ap_const_logic_0) and (ap_enable_reg_pp0_iter28 = ap_const_logic_0) and (ap_enable_reg_pp0_iter27 = ap_const_logic_0) and (ap_enable_reg_pp0_iter26 = ap_const_logic_0) and (ap_enable_reg_pp0_iter25 = ap_const_logic_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_0) and (ap_enable_reg_pp0_iter23 = ap_const_logic_0) and (ap_enable_reg_pp0_iter22 = ap_const_logic_0) and (ap_enable_reg_pp0_iter21 = ap_const_logic_0) and (ap_enable_reg_pp0_iter20 = ap_const_logic_0) and (ap_enable_reg_pp0_iter19 = ap_const_logic_0) and (ap_enable_reg_pp0_iter18 = ap_const_logic_0) and (ap_enable_reg_pp0_iter17 = ap_const_logic_0) and (ap_enable_reg_pp0_iter16 = ap_const_logic_0) and (ap_enable_reg_pp0_iter15 = ap_const_logic_0) and (ap_enable_reg_pp0_iter14 = ap_const_logic_0) and (ap_enable_reg_pp0_iter13 = ap_const_logic_0) and (ap_enable_reg_pp0_iter12 = ap_const_logic_0) and (ap_enable_reg_pp0_iter11 = ap_const_logic_0) and (ap_enable_reg_pp0_iter10 = ap_const_logic_0) and (ap_enable_reg_pp0_iter9 = ap_const_logic_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_0) and (ap_enable_reg_pp0_iter6 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_win_val_val_1_0_0_2_phi_fu_618_p10_assign_proc : process(ap_enable_reg_pp0_iter42, ap_block_pp0_stage0, tmp_31_reg_2851_pp0_iter41_reg, col_rd_2_reg_3006, row_rd_5_reg_3002, tmp_53_reg_3065, tmp_55_reg_3069, tmp_56_reg_3073, k_buf_val_val_0_0_q0, k_buf_val_val_1_0_q0, ap_phi_reg_pp0_iter42_win_val_val_1_0_0_2_reg_615)
begin
if ((((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_53_reg_3065 = ap_const_lv1_0) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((tmp_56_reg_3073 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_0) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_0) and (tmp_56_reg_3073 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)))) then
ap_phi_mux_win_val_val_1_0_0_2_phi_fu_618_p10 <= k_buf_val_val_0_0_q0;
elsif (((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (row_rd_5_reg_3002 = ap_const_lv1_0) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_phi_mux_win_val_val_1_0_0_2_phi_fu_618_p10 <= k_buf_val_val_1_0_q0;
else
ap_phi_mux_win_val_val_1_0_0_2_phi_fu_618_p10 <= ap_phi_reg_pp0_iter42_win_val_val_1_0_0_2_reg_615;
end if;
end process;
ap_phi_mux_win_val_val_1_0_1_2_phi_fu_598_p10_assign_proc : process(ap_enable_reg_pp0_iter42, ap_block_pp0_stage0, tmp_31_reg_2851_pp0_iter41_reg, col_rd_2_reg_3006, row_rd_5_reg_3002, tmp_53_reg_3065, tmp_55_reg_3069, tmp_56_reg_3073, k_buf_val_val_0_1_q0, k_buf_val_val_1_1_q0, ap_phi_reg_pp0_iter42_win_val_val_1_0_1_2_reg_595)
begin
if ((((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_53_reg_3065 = ap_const_lv1_0) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((tmp_56_reg_3073 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_0) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_0) and (tmp_56_reg_3073 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)))) then
ap_phi_mux_win_val_val_1_0_1_2_phi_fu_598_p10 <= k_buf_val_val_0_1_q0;
elsif (((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (row_rd_5_reg_3002 = ap_const_lv1_0) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_phi_mux_win_val_val_1_0_1_2_phi_fu_598_p10 <= k_buf_val_val_1_1_q0;
else
ap_phi_mux_win_val_val_1_0_1_2_phi_fu_598_p10 <= ap_phi_reg_pp0_iter42_win_val_val_1_0_1_2_reg_595;
end if;
end process;
ap_phi_mux_win_val_val_1_0_2_2_phi_fu_578_p10_assign_proc : process(ap_enable_reg_pp0_iter42, ap_block_pp0_stage0, tmp_31_reg_2851_pp0_iter41_reg, col_rd_2_reg_3006, row_rd_5_reg_3002, tmp_53_reg_3065, tmp_55_reg_3069, tmp_56_reg_3073, k_buf_val_val_0_2_q0, k_buf_val_val_1_2_q0, ap_phi_reg_pp0_iter42_win_val_val_1_0_2_2_reg_575)
begin
if ((((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_53_reg_3065 = ap_const_lv1_0) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((tmp_56_reg_3073 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_0) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_0) and (tmp_56_reg_3073 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)))) then
ap_phi_mux_win_val_val_1_0_2_2_phi_fu_578_p10 <= k_buf_val_val_0_2_q0;
elsif (((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (row_rd_5_reg_3002 = ap_const_lv1_0) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
ap_phi_mux_win_val_val_1_0_2_2_phi_fu_578_p10 <= k_buf_val_val_1_2_q0;
else
ap_phi_mux_win_val_val_1_0_2_2_phi_fu_578_p10 <= ap_phi_reg_pp0_iter42_win_val_val_1_0_2_2_reg_575;
end if;
end process;
ap_phi_reg_pp0_iter0_dx_reg_566 <= "XXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter0_dy_reg_557 <= "XXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter42_win_val_val_1_0_0_2_reg_615 <= "XXXXXXXX";
ap_phi_reg_pp0_iter42_win_val_val_1_0_1_2_reg_595 <= "XXXXXXXX";
ap_phi_reg_pp0_iter42_win_val_val_1_0_2_2_reg_575 <= "XXXXXXXX";
ap_predicate_op564_read_state98_assign_proc : process(tmp_31_reg_2851_pp0_iter41_reg, col_rd_2_reg_3006, row_rd_5_reg_3002, tmp_53_reg_3065, tmp_55_reg_3069)
begin
ap_predicate_op564_read_state98 <= ((tmp_55_reg_3069 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1));
end process;
ap_ready_assign_proc : process(tmp_27_fu_1043_p2, ap_CS_fsm_state55)
begin
if (((tmp_27_fu_1043_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state55))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
brmerge_demorgan_fu_1549_p2 <= (row_wr_3_fu_1456_p3 and col_wr_2_fu_1491_p3);
brmerge_i_i1_fu_2363_p2 <= (p_39_demorgan_i_not_i_1_fu_2358_p2 or neg_src_not_i_i1_fu_2348_p2);
brmerge_i_i2_fu_2422_p2 <= (p_39_demorgan_i_not_i_2_fu_2417_p2 or neg_src_not_i_i2_fu_2407_p2);
brmerge_i_i_fu_2304_p2 <= (p_39_demorgan_i_not_i_fu_2299_p2 or neg_src_not_i_i_fu_2289_p2);
brmerge_i_i_not_i_i1_fu_2353_p2 <= (p_39_demorgan_i_i_i1_reg_3503 and neg_src_not_i_i1_fu_2348_p2);
brmerge_i_i_not_i_i2_fu_2412_p2 <= (p_39_demorgan_i_i_i2_reg_3521 and neg_src_not_i_i2_fu_2407_p2);
brmerge_i_i_not_i_i_fu_2294_p2 <= (p_39_demorgan_i_i_i_reg_3485 and neg_src_not_i_i_fu_2289_p2);
carry_1_fu_2175_p2 <= (tmp_88_fu_2149_p3 and tmp_4_i_i1_fu_2169_p2);
carry_2_fu_2239_p2 <= (tmp_92_fu_2213_p3 and tmp_4_i_i2_fu_2233_p2);
carry_fu_2111_p2 <= (tmp_84_fu_2085_p3 and tmp_4_i_i_fu_2105_p2);
col_rate_V_fu_743_p1 <= grp_fu_708_p2(32 - 1 downto 0);
col_rd_2_fu_1486_p2 <= (tmp_50_reg_2865_pp0_iter40_reg or tmp67_fu_1481_p2);
col_wr_1_fu_1126_p2 <= "0" when (p_Val2_17_reg_546 = ap_const_lv15_0) else "1";
col_wr_2_fu_1491_p3 <=
col_wr_reg_2997 when (tmp_24_reg_2797(0) = '1') else
col_wr_1_reg_2877_pp0_iter40_reg;
col_wr_fu_1362_p2 <= "1" when (pre_fx_1_fu_1337_p3 = tmp_51_fu_1357_p2) else "0";
cols_fu_976_p3 <=
scols_reg_2675 when (tmp_19_fu_967_p2(0) = '1') else
tmp_20_fu_971_p2;
dcols_fu_650_p1 <= p_dst_cols_V_read(16 - 1 downto 0);
deleted_zeros_1_fu_2191_p3 <=
Range1_all_ones_1_fu_2181_p2 when (carry_1_fu_2175_p2(0) = '1') else
Range1_all_zeros_1_fu_2186_p2;
deleted_zeros_2_fu_2255_p3 <=
Range1_all_ones_2_fu_2245_p2 when (carry_2_fu_2239_p2(0) = '1') else
Range1_all_zeros_2_fu_2250_p2;
deleted_zeros_fu_2127_p3 <=
Range1_all_ones_fu_2117_p2 when (carry_fu_2111_p2(0) = '1') else
Range1_all_zeros_fu_2122_p2;
drows_fu_654_p1 <= p_dst_rows_V_read(16 - 1 downto 0);
grp_fu_1099_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1099_ce <= ap_const_logic_1;
else
grp_fu_1099_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1099_p0 <= tmp_49_cast_reg_2840(31 - 1 downto 0);
grp_fu_1115_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1115_ce <= ap_const_logic_1;
else
grp_fu_1115_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1115_p0 <= grp_fu_1115_p00(31 - 1 downto 0);
grp_fu_1115_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_34_fu_1103_p3),32));
grp_fu_1147_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1147_ce <= ap_const_logic_1;
else
grp_fu_1147_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1156_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1156_ce <= ap_const_logic_1;
else
grp_fu_1156_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1809_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1809_ce <= ap_const_logic_1;
else
grp_fu_1809_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1809_p1 <= OP2_V_1_fu_1800_p1(20 - 1 downto 0);
grp_fu_1827_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1827_ce <= ap_const_logic_1;
else
grp_fu_1827_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1827_p1 <= OP2_V_6_fu_1821_p1(20 - 1 downto 0);
grp_fu_1836_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1836_ce <= ap_const_logic_1;
else
grp_fu_1836_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1836_p1 <= OP2_V_1_fu_1800_p1(20 - 1 downto 0);
grp_fu_1851_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1851_ce <= ap_const_logic_1;
else
grp_fu_1851_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1851_p1 <= OP2_V_6_fu_1821_p1(20 - 1 downto 0);
grp_fu_1860_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1860_ce <= ap_const_logic_1;
else
grp_fu_1860_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1860_p1 <= OP2_V_1_fu_1800_p1(20 - 1 downto 0);
grp_fu_1875_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1875_ce <= ap_const_logic_1;
else
grp_fu_1875_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1875_p1 <= OP2_V_6_fu_1821_p1(20 - 1 downto 0);
grp_fu_1887_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1887_ce <= ap_const_logic_1;
else
grp_fu_1887_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1887_p1 <= OP2_V_5_fu_1884_p1(20 - 1 downto 0);
grp_fu_1896_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1896_ce <= ap_const_logic_1;
else
grp_fu_1896_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1896_p1 <= OP2_V_6_reg_3222(20 - 1 downto 0);
grp_fu_1904_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1904_ce <= ap_const_logic_1;
else
grp_fu_1904_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1904_p1 <= OP2_V_5_fu_1884_p1(20 - 1 downto 0);
grp_fu_1913_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1913_ce <= ap_const_logic_1;
else
grp_fu_1913_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1913_p1 <= OP2_V_6_reg_3222(20 - 1 downto 0);
grp_fu_1921_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1921_ce <= ap_const_logic_1;
else
grp_fu_1921_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1921_p1 <= OP2_V_5_fu_1884_p1(20 - 1 downto 0);
grp_fu_1930_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1930_ce <= ap_const_logic_1;
else
grp_fu_1930_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_1930_p1 <= OP2_V_6_reg_3222(20 - 1 downto 0);
grp_fu_684_ap_start_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
grp_fu_684_ap_start <= ap_const_logic_1;
else
grp_fu_684_ap_start <= ap_const_logic_0;
end if;
end process;
grp_fu_684_p0 <= (srows_fu_658_p1 & ap_const_lv32_0);
grp_fu_708_ap_start_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
grp_fu_708_ap_start <= ap_const_logic_1;
else
grp_fu_708_ap_start <= ap_const_logic_0;
end if;
end process;
grp_fu_708_p0 <= (scols_fu_662_p1 & ap_const_lv32_0);
i_fu_1048_p2 <= std_logic_vector(unsigned(p_Val2_16_reg_535) + unsigned(ap_const_lv15_1));
i_op_assign_15_cast_fu_1039_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Val2_16_reg_535),16));
i_op_assign_cast_fu_1084_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Val2_17_reg_546),16));
j_fu_1093_p2 <= std_logic_vector(unsigned(p_Val2_17_reg_546) + unsigned(ap_const_lv15_1));
k_buf_val_val_0_0_ad_gep_fu_469_p3 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
k_buf_val_val_0_0_address0_assign_proc : process(row_rd_5_fu_1442_p3, tmp_52_fu_1501_p1, k_buf_val_val_0_0_ad_gep_fu_469_p3, ap_condition_3380)
begin
if ((ap_const_boolean_1 = ap_condition_3380)) then
if ((row_rd_5_fu_1442_p3 = ap_const_lv1_1)) then
k_buf_val_val_0_0_address0 <= k_buf_val_val_0_0_ad_gep_fu_469_p3;
elsif ((row_rd_5_fu_1442_p3 = ap_const_lv1_0)) then
k_buf_val_val_0_0_address0 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
else
k_buf_val_val_0_0_address0 <= "XXXXXXXXXXXXX";
end if;
else
k_buf_val_val_0_0_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
k_buf_val_val_0_0_ce0_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter40_reg, row_rd_5_fu_1442_p3, col_rd_2_fu_1486_p2, ap_enable_reg_pp0_iter41)
begin
if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (row_rd_5_fu_1442_p3 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1)) or ((row_rd_5_fu_1442_p3 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1)))) then
k_buf_val_val_0_0_ce0 <= ap_const_logic_1;
else
k_buf_val_val_0_0_ce0 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_0_0_ce1_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, tmp_53_reg_3065_pp0_iter42_reg, tmp_55_reg_3069_pp0_iter42_reg, tmp_56_reg_3073_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)) or ((tmp_56_reg_3073_pp0_iter42_reg = ap_const_lv1_0) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)))) then
k_buf_val_val_0_0_ce1 <= ap_const_logic_1;
else
k_buf_val_val_0_0_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_0_0_d1_assign_proc : process(tmp_55_reg_3069_pp0_iter42_reg, tmp_56_reg_3073_pp0_iter42_reg, tmp_97_reg_3107, tmp_2_fu_306, ap_condition_3386)
begin
if ((ap_const_boolean_1 = ap_condition_3386)) then
if ((tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_1)) then
k_buf_val_val_0_0_d1 <= tmp_97_reg_3107;
elsif (((tmp_56_reg_3073_pp0_iter42_reg = ap_const_lv1_0) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_0))) then
k_buf_val_val_0_0_d1 <= tmp_2_fu_306;
else
k_buf_val_val_0_0_d1 <= "XXXXXXXX";
end if;
else
k_buf_val_val_0_0_d1 <= "XXXXXXXX";
end if;
end process;
k_buf_val_val_0_0_we1_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, tmp_53_reg_3065_pp0_iter42_reg, tmp_55_reg_3069_pp0_iter42_reg, tmp_56_reg_3073_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)) or ((tmp_56_reg_3073_pp0_iter42_reg = ap_const_lv1_0) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)))) then
k_buf_val_val_0_0_we1 <= ap_const_logic_1;
else
k_buf_val_val_0_0_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_0_1_ad_gep_fu_476_p3 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
k_buf_val_val_0_1_address0_assign_proc : process(row_rd_5_fu_1442_p3, tmp_52_fu_1501_p1, k_buf_val_val_0_1_ad_gep_fu_476_p3, ap_condition_3380)
begin
if ((ap_const_boolean_1 = ap_condition_3380)) then
if ((row_rd_5_fu_1442_p3 = ap_const_lv1_1)) then
k_buf_val_val_0_1_address0 <= k_buf_val_val_0_1_ad_gep_fu_476_p3;
elsif ((row_rd_5_fu_1442_p3 = ap_const_lv1_0)) then
k_buf_val_val_0_1_address0 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
else
k_buf_val_val_0_1_address0 <= "XXXXXXXXXXXXX";
end if;
else
k_buf_val_val_0_1_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
k_buf_val_val_0_1_ce0_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter40_reg, row_rd_5_fu_1442_p3, col_rd_2_fu_1486_p2, ap_enable_reg_pp0_iter41)
begin
if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (row_rd_5_fu_1442_p3 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1)) or ((row_rd_5_fu_1442_p3 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1)))) then
k_buf_val_val_0_1_ce0 <= ap_const_logic_1;
else
k_buf_val_val_0_1_ce0 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_0_1_ce1_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, tmp_53_reg_3065_pp0_iter42_reg, tmp_55_reg_3069_pp0_iter42_reg, tmp_56_reg_3073_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)) or ((tmp_56_reg_3073_pp0_iter42_reg = ap_const_lv1_0) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)))) then
k_buf_val_val_0_1_ce1 <= ap_const_logic_1;
else
k_buf_val_val_0_1_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_0_1_d1_assign_proc : process(tmp_55_reg_3069_pp0_iter42_reg, tmp_56_reg_3073_pp0_iter42_reg, tmp_98_reg_3112, tmp_1_fu_254, ap_condition_3386)
begin
if ((ap_const_boolean_1 = ap_condition_3386)) then
if ((tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_1)) then
k_buf_val_val_0_1_d1 <= tmp_98_reg_3112;
elsif (((tmp_56_reg_3073_pp0_iter42_reg = ap_const_lv1_0) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_0))) then
k_buf_val_val_0_1_d1 <= tmp_1_fu_254;
else
k_buf_val_val_0_1_d1 <= "XXXXXXXX";
end if;
else
k_buf_val_val_0_1_d1 <= "XXXXXXXX";
end if;
end process;
k_buf_val_val_0_1_we1_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, tmp_53_reg_3065_pp0_iter42_reg, tmp_55_reg_3069_pp0_iter42_reg, tmp_56_reg_3073_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)) or ((tmp_56_reg_3073_pp0_iter42_reg = ap_const_lv1_0) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)))) then
k_buf_val_val_0_1_we1 <= ap_const_logic_1;
else
k_buf_val_val_0_1_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_0_2_ad_gep_fu_483_p3 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
k_buf_val_val_0_2_address0_assign_proc : process(row_rd_5_fu_1442_p3, tmp_52_fu_1501_p1, k_buf_val_val_0_2_ad_gep_fu_483_p3, ap_condition_3380)
begin
if ((ap_const_boolean_1 = ap_condition_3380)) then
if ((row_rd_5_fu_1442_p3 = ap_const_lv1_1)) then
k_buf_val_val_0_2_address0 <= k_buf_val_val_0_2_ad_gep_fu_483_p3;
elsif ((row_rd_5_fu_1442_p3 = ap_const_lv1_0)) then
k_buf_val_val_0_2_address0 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
else
k_buf_val_val_0_2_address0 <= "XXXXXXXXXXXXX";
end if;
else
k_buf_val_val_0_2_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
k_buf_val_val_0_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter40_reg, row_rd_5_fu_1442_p3, col_rd_2_fu_1486_p2, ap_enable_reg_pp0_iter41)
begin
if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (row_rd_5_fu_1442_p3 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1)) or ((row_rd_5_fu_1442_p3 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1) and (col_rd_2_fu_1486_p2 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter40_reg = ap_const_lv1_1)))) then
k_buf_val_val_0_2_ce0 <= ap_const_logic_1;
else
k_buf_val_val_0_2_ce0 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_0_2_ce1_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, tmp_53_reg_3065_pp0_iter42_reg, tmp_55_reg_3069_pp0_iter42_reg, tmp_56_reg_3073_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)) or ((tmp_56_reg_3073_pp0_iter42_reg = ap_const_lv1_0) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)))) then
k_buf_val_val_0_2_ce1 <= ap_const_logic_1;
else
k_buf_val_val_0_2_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_0_2_d1_assign_proc : process(tmp_55_reg_3069_pp0_iter42_reg, tmp_56_reg_3073_pp0_iter42_reg, tmp_99_reg_3117, tmp_fu_250, ap_condition_3386)
begin
if ((ap_const_boolean_1 = ap_condition_3386)) then
if ((tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_1)) then
k_buf_val_val_0_2_d1 <= tmp_99_reg_3117;
elsif (((tmp_56_reg_3073_pp0_iter42_reg = ap_const_lv1_0) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_0))) then
k_buf_val_val_0_2_d1 <= tmp_fu_250;
else
k_buf_val_val_0_2_d1 <= "XXXXXXXX";
end if;
else
k_buf_val_val_0_2_d1 <= "XXXXXXXX";
end if;
end process;
k_buf_val_val_0_2_we1_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, tmp_53_reg_3065_pp0_iter42_reg, tmp_55_reg_3069_pp0_iter42_reg, tmp_56_reg_3073_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
if ((((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)) or ((tmp_56_reg_3073_pp0_iter42_reg = ap_const_lv1_0) and (tmp_55_reg_3069_pp0_iter42_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (tmp_53_reg_3065_pp0_iter42_reg = ap_const_lv1_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1)))) then
k_buf_val_val_0_2_we1 <= ap_const_logic_1;
else
k_buf_val_val_0_2_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_1_0_address0 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
k_buf_val_val_1_0_address1 <= tmp_52_reg_3010_pp0_iter42_reg(13 - 1 downto 0);
k_buf_val_val_1_0_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter41)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1))) then
k_buf_val_val_1_0_ce0 <= ap_const_logic_1;
else
k_buf_val_val_1_0_ce0 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_1_0_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter43)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1))) then
k_buf_val_val_1_0_ce1 <= ap_const_logic_1;
else
k_buf_val_val_1_0_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_1_0_we1_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1))) then
k_buf_val_val_1_0_we1 <= ap_const_logic_1;
else
k_buf_val_val_1_0_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_1_1_address0 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
k_buf_val_val_1_1_address1 <= tmp_52_reg_3010_pp0_iter42_reg(13 - 1 downto 0);
k_buf_val_val_1_1_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter41)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1))) then
k_buf_val_val_1_1_ce0 <= ap_const_logic_1;
else
k_buf_val_val_1_1_ce0 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_1_1_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter43)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1))) then
k_buf_val_val_1_1_ce1 <= ap_const_logic_1;
else
k_buf_val_val_1_1_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_1_1_we1_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1))) then
k_buf_val_val_1_1_we1 <= ap_const_logic_1;
else
k_buf_val_val_1_1_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_1_2_address0 <= tmp_52_fu_1501_p1(13 - 1 downto 0);
k_buf_val_val_1_2_address1 <= tmp_52_reg_3010_pp0_iter42_reg(13 - 1 downto 0);
k_buf_val_val_1_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter41)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter41 = ap_const_logic_1))) then
k_buf_val_val_1_2_ce0 <= ap_const_logic_1;
else
k_buf_val_val_1_2_ce0 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_1_2_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter43)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1))) then
k_buf_val_val_1_2_ce1 <= ap_const_logic_1;
else
k_buf_val_val_1_2_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_val_val_1_2_we1_assign_proc : process(ap_block_pp0_stage0_11001, tmp_31_reg_2851_pp0_iter42_reg, row_rd_5_reg_3002_pp0_iter42_reg, col_rd_2_reg_3006_pp0_iter42_reg, ap_enable_reg_pp0_iter43)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter43 = ap_const_logic_1) and (col_rd_2_reg_3006_pp0_iter42_reg = ap_const_lv1_1) and (row_rd_5_reg_3002_pp0_iter42_reg = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter42_reg = ap_const_lv1_1))) then
k_buf_val_val_1_2_we1 <= ap_const_logic_1;
else
k_buf_val_val_1_2_we1 <= ap_const_logic_0;
end if;
end process;
neg_src_5_fu_2279_p2 <= (tmp_5_i_i_fu_2274_p2 and signbit_reg_3394_pp0_iter51_reg);
neg_src_6_fu_2338_p2 <= (tmp_5_i_i1_fu_2333_p2 and signbit_1_reg_3422_pp0_iter51_reg);
neg_src_fu_2397_p2 <= (tmp_5_i_i2_fu_2392_p2 and signbit_2_reg_3450_pp0_iter51_reg);
neg_src_not_i_i1_fu_2348_p2 <= (signbit_not_i1_fu_2343_p2 or p_38_i_i_i1_reg_3497);
neg_src_not_i_i2_fu_2407_p2 <= (signbit_not_i2_fu_2402_p2 or p_38_i_i_i2_reg_3515);
neg_src_not_i_i_fu_2289_p2 <= (signbit_not_i_fu_2284_p2 or p_38_i_i_i_reg_3479);
not_1_fu_1387_p2 <= "0" when (sy_4_reg_2989 = pre_fy_fu_242) else "1";
not_s_fu_1463_p2 <= "0" when (pre_fx_1_reg_2976 = pre_fx_2_fu_1424_p3) else "1";
p_38_i_i_i1_fu_2199_p2 <= (carry_1_fu_2175_p2 and Range1_all_ones_1_fu_2181_p2);
p_38_i_i_i2_fu_2263_p2 <= (carry_2_fu_2239_p2 and Range1_all_ones_2_fu_2245_p2);
p_38_i_i_i_fu_2135_p2 <= (carry_fu_2111_p2 and Range1_all_ones_fu_2117_p2);
p_39_demorgan_i_i_i1_fu_2205_p2 <= (signbit_1_reg_3422 or deleted_zeros_1_fu_2191_p3);
p_39_demorgan_i_i_i2_fu_2269_p2 <= (signbit_2_reg_3450 or deleted_zeros_2_fu_2255_p3);
p_39_demorgan_i_i_i_fu_2141_p2 <= (signbit_reg_3394 or deleted_zeros_fu_2127_p3);
p_39_demorgan_i_not_i_1_fu_2358_p2 <= (p_39_demorgan_i_i_i1_reg_3503 xor ap_const_lv1_1);
p_39_demorgan_i_not_i_2_fu_2417_p2 <= (p_39_demorgan_i_i_i2_reg_3521 xor ap_const_lv1_1);
p_39_demorgan_i_not_i_fu_2299_p2 <= (p_39_demorgan_i_i_i_reg_3485 xor ap_const_lv1_1);
p_6_fu_1203_p3 <=
ret_V_fu_1169_p4 when (tmp_37_fu_1191_p2(0) = '1') else
ret_V_1_fu_1197_p2;
p_7_fu_1253_p3 <=
ret_V_2_fu_1219_p4 when (tmp_38_fu_1241_p2(0) = '1') else
ret_V_3_fu_1247_p2;
p_Val2_10_cast_fu_876_p2 <= std_logic_vector(signed(ap_const_lv26_3FF8000) + signed(tmp_65_reg_2744));
p_Val2_10_fu_881_p4 <= p_Val2_10_cast_fu_876_p2(25 downto 6);
p_Val2_13_fu_912_p2 <= std_logic_vector(signed(ap_const_lv33_1FFFF8000) + signed(tmp_32_cast_fu_909_p1));
p_Val2_14_cast_fu_918_p2 <= std_logic_vector(signed(ap_const_lv26_3FF8000) + signed(tmp_69_reg_2754));
p_Val2_14_fu_923_p4 <= p_Val2_14_cast_fu_918_p2(25 downto 6);
p_Val2_18_fu_903_p2 <= std_logic_vector(unsigned(p_Val2_10_fu_881_p4) + unsigned(tmp_11_fu_899_p1));
p_Val2_19_fu_945_p2 <= std_logic_vector(unsigned(p_Val2_14_fu_923_p4) + unsigned(tmp_15_fu_941_p1));
p_Val2_2_fu_1165_p2 <= std_logic_vector(unsigned(p_Val2_1_reg_2922) + unsigned(tmp_61_cast_reg_2809));
p_Val2_30_fu_1951_p2 <= std_logic_vector(unsigned(tmp69_reg_3354) + unsigned(tmp68_fu_1947_p2));
p_Val2_32_fu_2092_p2 <= std_logic_vector(unsigned(p_Val2_31_reg_3401) + unsigned(tmp_i_i_fu_2082_p1));
p_Val2_33_fu_2156_p2 <= std_logic_vector(unsigned(p_Val2_s_72_reg_3429) + unsigned(tmp_i_i1_fu_2146_p1));
p_Val2_36_fu_2220_p2 <= std_logic_vector(unsigned(p_Val2_35_reg_3457) + unsigned(tmp_i_i2_fu_2210_p1));
p_Val2_3_fu_1161_p2 <= std_logic_vector(unsigned(p_Val2_s_reg_2917) + unsigned(tmp_59_cast_reg_2804));
p_Val2_44_1_fu_1996_p2 <= std_logic_vector(unsigned(tmp71_reg_3369) + unsigned(tmp70_fu_1992_p2));
p_Val2_44_2_fu_2041_p2 <= std_logic_vector(unsigned(tmp73_reg_3384) + unsigned(tmp72_fu_2037_p2));
p_Val2_9_fu_870_p2 <= std_logic_vector(signed(ap_const_lv33_1FFFF8000) + signed(tmp_28_cast_fu_867_p1));
p_dst_data_stream_0_V_blk_n_assign_proc : process(p_dst_data_stream_0_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter52, brmerge_demorgan_reg_3077_pp0_iter51_reg)
begin
if (((ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
p_dst_data_stream_0_V_blk_n <= p_dst_data_stream_0_V_full_n;
else
p_dst_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_0_V_din <=
p_mux_i_i_fu_2310_p3 when (brmerge_i_i_fu_2304_p2(0) = '1') else
p_i_i_fu_2317_p3;
p_dst_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter52, brmerge_demorgan_reg_3077_pp0_iter51_reg, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1))) then
p_dst_data_stream_0_V_write <= ap_const_logic_1;
else
p_dst_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_1_V_blk_n_assign_proc : process(p_dst_data_stream_1_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter52, brmerge_demorgan_reg_3077_pp0_iter51_reg)
begin
if (((ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
p_dst_data_stream_1_V_blk_n <= p_dst_data_stream_1_V_full_n;
else
p_dst_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_1_V_din <=
p_mux_i_i1_fu_2369_p3 when (brmerge_i_i1_fu_2363_p2(0) = '1') else
p_i_i1_fu_2376_p3;
p_dst_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter52, brmerge_demorgan_reg_3077_pp0_iter51_reg, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1))) then
p_dst_data_stream_1_V_write <= ap_const_logic_1;
else
p_dst_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_2_V_blk_n_assign_proc : process(p_dst_data_stream_2_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter52, brmerge_demorgan_reg_3077_pp0_iter51_reg)
begin
if (((ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
p_dst_data_stream_2_V_blk_n <= p_dst_data_stream_2_V_full_n;
else
p_dst_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_2_V_din <=
p_mux_i_i2_fu_2428_p3 when (brmerge_i_i2_fu_2422_p2(0) = '1') else
p_i_i2_fu_2435_p3;
p_dst_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter52, brmerge_demorgan_reg_3077_pp0_iter51_reg, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter52 = ap_const_logic_1) and (brmerge_demorgan_reg_3077_pp0_iter51_reg = ap_const_lv1_1))) then
p_dst_data_stream_2_V_write <= ap_const_logic_1;
else
p_dst_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
p_i_i1_fu_2376_p3 <=
ap_const_lv8_0 when (neg_src_6_fu_2338_p2(0) = '1') else
p_Val2_33_reg_3491;
p_i_i2_fu_2435_p3 <=
ap_const_lv8_0 when (neg_src_fu_2397_p2(0) = '1') else
p_Val2_36_reg_3509;
p_i_i_fu_2317_p3 <=
ap_const_lv8_0 when (neg_src_5_fu_2279_p2(0) = '1') else
p_Val2_32_reg_3473;
p_lshr1_fu_827_p4 <= p_neg1_fu_822_p2(31 downto 1);
p_lshr_fu_788_p4 <= p_neg_fu_783_p2(31 downto 1);
p_mux_i_i1_fu_2369_p3 <=
p_Val2_33_reg_3491 when (brmerge_i_i_not_i_i1_fu_2353_p2(0) = '1') else
ap_const_lv8_FF;
p_mux_i_i2_fu_2428_p3 <=
p_Val2_36_reg_3509 when (brmerge_i_i_not_i_i2_fu_2412_p2(0) = '1') else
ap_const_lv8_FF;
p_mux_i_i_fu_2310_p3 <=
p_Val2_32_reg_3473 when (brmerge_i_i_not_i_i_fu_2294_p2(0) = '1') else
ap_const_lv8_FF;
p_neg1_fu_822_p2 <= std_logic_vector(unsigned(ap_const_lv32_0) - unsigned(col_rate_V_reg_2711));
p_neg_fu_783_p2 <= std_logic_vector(unsigned(ap_const_lv32_0) - unsigned(row_rate_V_reg_2703));
p_neg_t1_fu_841_p2 <= std_logic_vector(unsigned(ap_const_lv32_0) - unsigned(tmp_12_fu_837_p1));
p_neg_t_fu_802_p2 <= std_logic_vector(unsigned(ap_const_lv32_0) - unsigned(tmp_5_fu_798_p1));
p_src_data_stream_0_V_blk_n_assign_proc : process(p_src_data_stream_0_V_empty_n, ap_enable_reg_pp0_iter42, ap_block_pp0_stage0, tmp_31_reg_2851_pp0_iter41_reg, col_rd_2_reg_3006, row_rd_5_reg_3002, tmp_53_reg_3065, tmp_55_reg_3069)
begin
if (((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
p_src_data_stream_0_V_blk_n <= p_src_data_stream_0_V_empty_n;
else
p_src_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_0_V_read_assign_proc : process(ap_enable_reg_pp0_iter42, ap_predicate_op564_read_state98, ap_block_pp0_stage0_11001)
begin
if (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1))) then
p_src_data_stream_0_V_read <= ap_const_logic_1;
else
p_src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_1_V_blk_n_assign_proc : process(p_src_data_stream_1_V_empty_n, ap_enable_reg_pp0_iter42, ap_block_pp0_stage0, tmp_31_reg_2851_pp0_iter41_reg, col_rd_2_reg_3006, row_rd_5_reg_3002, tmp_53_reg_3065, tmp_55_reg_3069)
begin
if (((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
p_src_data_stream_1_V_blk_n <= p_src_data_stream_1_V_empty_n;
else
p_src_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_1_V_read_assign_proc : process(ap_enable_reg_pp0_iter42, ap_predicate_op564_read_state98, ap_block_pp0_stage0_11001)
begin
if (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1))) then
p_src_data_stream_1_V_read <= ap_const_logic_1;
else
p_src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_2_V_blk_n_assign_proc : process(p_src_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter42, ap_block_pp0_stage0, tmp_31_reg_2851_pp0_iter41_reg, col_rd_2_reg_3006, row_rd_5_reg_3002, tmp_53_reg_3065, tmp_55_reg_3069)
begin
if (((ap_enable_reg_pp0_iter42 = ap_const_logic_1) and (tmp_55_reg_3069 = ap_const_lv1_1) and (tmp_53_reg_3065 = ap_const_lv1_1) and (row_rd_5_reg_3002 = ap_const_lv1_1) and (col_rd_2_reg_3006 = ap_const_lv1_1) and (tmp_31_reg_2851_pp0_iter41_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
p_src_data_stream_2_V_blk_n <= p_src_data_stream_2_V_empty_n;
else
p_src_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_2_V_read_assign_proc : process(ap_enable_reg_pp0_iter42, ap_predicate_op564_read_state98, ap_block_pp0_stage0_11001)
begin
if (((ap_predicate_op564_read_state98 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter42 = ap_const_logic_1))) then
p_src_data_stream_2_V_read <= ap_const_logic_1;
else
p_src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
p_u_V_fu_1604_p3 <=
ap_const_lv20_0 when (tmp_48_reg_2971_pp0_iter41_reg(0) = '1') else
u_V_fu_1591_p3;
pre_fx_1_fu_1337_p3 <=
sx_reg_2776 when (tmp_48_fu_1332_p2(0) = '1') else
sx_2_reg_2937;
pre_fx_2_fu_1424_p3 <=
ap_const_lv16_FFF6 when (tmp_50_reg_2865_pp0_iter40_reg(0) = '1') else
pre_fx_fu_238;
pre_fx_2_sx_fu_1468_p3 <=
ap_const_lv16_FFF6 when (tmp_50_reg_2865_pp0_iter40_reg(0) = '1') else
pre_fx_1_reg_2976;
pre_fx_5_fu_1474_p3 <=
pre_fx_2_fu_1424_p3 when (tmp_24_reg_2797(0) = '1') else
pre_fx_2_sx_fu_1468_p3;
pre_fy_1_sy_fu_1392_p3 <=
pre_fy_fu_242 when (tmp_29_reg_2829(0) = '1') else
sy_4_reg_2989;
pre_fy_5_fu_1417_p3 <=
sel_tmp5_fu_1409_p3 when (tmp_50_reg_2865_pp0_iter40_reg(0) = '1') else
pre_fy_fu_242;
r_V_1_1_fu_2498_p0 <= OP2_V_2_fu_1803_p1(20 - 1 downto 0);
r_V_1_1_fu_2498_p1 <= r_V_1_1_fu_2498_p10(8 - 1 downto 0);
r_V_1_1_fu_2498_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_1_val_1_1_3_reg_3153),28));
r_V_1_2_fu_2509_p0 <= OP2_V_2_fu_1803_p1(20 - 1 downto 0);
r_V_1_2_fu_2509_p1 <= r_V_1_2_fu_2509_p10(8 - 1 downto 0);
r_V_1_2_fu_2509_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_1_val_1_2_3_reg_3158),28));
r_V_1_fu_2487_p0 <= OP2_V_2_fu_1803_p1(20 - 1 downto 0);
r_V_1_fu_2487_p1 <= r_V_1_fu_2487_p10(8 - 1 downto 0);
r_V_1_fu_2487_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_1_val_1_0_3_reg_3148),28));
r_V_2_1_fu_2504_p0 <= OP2_V_reg_3163(20 - 1 downto 0);
r_V_2_1_fu_2504_p1 <= r_V_2_1_fu_2504_p10(8 - 1 downto 0);
r_V_2_1_fu_2504_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_0_val_1_1_4_reg_3138),28));
r_V_2_2_fu_2515_p0 <= OP2_V_reg_3163(20 - 1 downto 0);
r_V_2_2_fu_2515_p1 <= r_V_2_2_fu_2515_p10(8 - 1 downto 0);
r_V_2_2_fu_2515_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_0_val_1_2_4_reg_3143),28));
r_V_2_fu_2493_p0 <= OP2_V_reg_3163(20 - 1 downto 0);
r_V_2_fu_2493_p1 <= r_V_2_fu_2493_p10(8 - 1 downto 0);
r_V_2_fu_2493_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_0_val_1_0_4_reg_3133),28));
r_V_3_1_fu_2469_p0 <= OP2_V_7_fu_1781_p1(20 - 1 downto 0);
r_V_3_1_fu_2469_p1 <= r_V_3_1_fu_2469_p10(8 - 1 downto 0);
r_V_3_1_fu_2469_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_0_val_1_1_fu_262),28));
r_V_3_2_fu_2481_p0 <= OP2_V_7_fu_1781_p1(20 - 1 downto 0);
r_V_3_2_fu_2481_p1 <= r_V_3_2_fu_2481_p10(8 - 1 downto 0);
r_V_3_2_fu_2481_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_0_val_1_2_fu_266),28));
r_V_3_fu_2457_p0 <= OP2_V_7_fu_1781_p1(20 - 1 downto 0);
r_V_3_fu_2457_p1 <= r_V_3_fu_2457_p10(8 - 1 downto 0);
r_V_3_fu_2457_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_0_val_1_0_fu_258),28));
r_V_4_fu_2475_p0 <= OP2_V_fu_1770_p1(20 - 1 downto 0);
r_V_4_fu_2475_p1 <= r_V_4_fu_2475_p10(8 - 1 downto 0);
r_V_4_fu_2475_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_1_val_1_2_1_fu_302),28));
r_V_7_fu_1283_p2 <= std_logic_vector(signed(tmp_39_fu_1269_p1) - signed(tmp_66_cast_fu_1279_p1));
r_V_8_fu_1313_p2 <= std_logic_vector(signed(tmp_44_fu_1299_p1) - signed(tmp_72_cast_fu_1309_p1));
r_V_fu_2451_p0 <= OP2_V_fu_1770_p1(20 - 1 downto 0);
r_V_fu_2451_p1 <= r_V_fu_2451_p10(8 - 1 downto 0);
r_V_fu_2451_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_1_val_1_0_1_fu_294),28));
r_V_s_fu_2463_p0 <= OP2_V_fu_1770_p1(20 - 1 downto 0);
r_V_s_fu_2463_p1 <= r_V_s_fu_2463_p10(8 - 1 downto 0);
r_V_s_fu_2463_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(win_val_1_val_1_1_1_fu_298),28));
ret_V_1_fu_1197_p2 <= std_logic_vector(unsigned(ap_const_lv16_1) + unsigned(ret_V_fu_1169_p4));
ret_V_2_fu_1219_p4 <= p_Val2_3_fu_1161_p2(31 downto 16);
ret_V_3_fu_1247_p2 <= std_logic_vector(unsigned(ap_const_lv16_1) + unsigned(ret_V_2_fu_1219_p4));
ret_V_fu_1169_p4 <= p_Val2_2_fu_1165_p2(31 downto 16);
row_rate_V_fu_739_p1 <= grp_fu_684_p2(32 - 1 downto 0);
row_rd_5_fu_1442_p3 <=
sel_tmp_fu_1437_p2 when (tmp_50_reg_2865_pp0_iter40_reg(0) = '1') else
row_rd_fu_234;
row_wr_1_fu_1383_p2 <= "1" when (sy_4_reg_2989 = tmp_28_reg_2823) else "0";
row_wr_2_fu_1066_p2 <= "0" when (p_Val2_16_reg_535 = ap_const_lv15_0) else "1";
row_wr_3_fu_1456_p3 <=
row_wr_4_fu_1449_p3 when (tmp_50_reg_2865_pp0_iter40_reg(0) = '1') else
row_wr_fu_230;
row_wr_4_fu_1449_p3 <=
row_wr_1_fu_1383_p2 when (sel_tmp4_fu_1405_p2(0) = '1') else
row_wr_2_reg_2835;
rows_fu_960_p3 <=
srows_reg_2667 when (tmp_17_fu_951_p2(0) = '1') else
tmp_18_fu_955_p2;
scols_fu_662_p1 <= p_src_cols_V_read(16 - 1 downto 0);
sel_tmp4_fu_1405_p2 <= (tmp_50_reg_2865_pp0_iter40_reg and tmp_23_reg_2792);
sel_tmp5_fu_1409_p3 <=
pre_fy_fu_242 when (sel_tmp4_fu_1405_p2(0) = '1') else
pre_fy_1_sy_fu_1392_p3;
sel_tmp_fu_1437_p2 <= (tmp_29_reg_2829 or tmp66_fu_1431_p2);
signbit_not_i1_fu_2343_p2 <= (signbit_1_reg_3422_pp0_iter51_reg xor ap_const_lv1_1);
signbit_not_i2_fu_2402_p2 <= (signbit_2_reg_3450_pp0_iter51_reg xor ap_const_lv1_1);
signbit_not_i_fu_2284_p2 <= (signbit_reg_3394_pp0_iter51_reg xor ap_const_lv1_1);
srows_fu_658_p1 <= p_src_rows_V_read(16 - 1 downto 0);
sx_2_fu_1211_p3 <=
p_6_fu_1203_p3 when (tmp_73_fu_1179_p3(0) = '1') else
ret_V_fu_1169_p4;
sx_fu_989_p2 <= std_logic_vector(signed(ap_const_lv16_FFFF) + signed(scols_reg_2675));
sy_3_fu_1261_p3 <=
p_7_fu_1253_p3 when (tmp_75_fu_1229_p3(0) = '1') else
ret_V_2_fu_1219_p4;
sy_4_fu_1351_p3 <=
sy_reg_2787 when (tmp_49_fu_1346_p2(0) = '1') else
sy_3_reg_2944;
sy_fu_1000_p2 <= std_logic_vector(signed(ap_const_lv16_FFFF) + signed(srows_reg_2667));
tmp66_fu_1431_p2 <= (sel_tmp4_fu_1405_p2 or not_1_fu_1387_p2);
tmp67_fu_1481_p2 <= (tmp_24_reg_2797 or not_s_fu_1463_p2);
tmp68_fu_1947_p2 <= std_logic_vector(unsigned(p_Val2_24_reg_3344) + unsigned(p_Val2_28_reg_3349));
tmp69_fu_1935_p2 <= std_logic_vector(unsigned(p_Val2_21_reg_3314) + unsigned(p_Val2_29_reg_3319));
tmp70_fu_1992_p2 <= std_logic_vector(unsigned(p_Val2_30_1_reg_3359) + unsigned(p_Val2_33_1_reg_3364));
tmp71_fu_1939_p2 <= std_logic_vector(unsigned(p_Val2_40_1_reg_3324) + unsigned(p_Val2_42_1_reg_3329));
tmp72_fu_2037_p2 <= std_logic_vector(unsigned(p_Val2_30_2_reg_3374) + unsigned(p_Val2_33_2_reg_3379));
tmp73_fu_1943_p2 <= std_logic_vector(unsigned(p_Val2_40_2_reg_3334) + unsigned(p_Val2_42_2_reg_3339));
tmp_10_fu_811_p3 <=
p_neg_t_fu_802_p2 when (tmp_54_reg_2719(0) = '1') else
tmp_9_fu_808_p1;
tmp_11_fu_899_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_67_fu_891_p3),20));
tmp_12_fu_837_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_lshr1_fu_827_p4),32));
tmp_13_cast_fu_861_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(srows_reg_2667),17));
tmp_13_fu_847_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_lshr_f1_reg_2734),32));
tmp_14_fu_850_p3 <=
p_neg_t1_fu_841_p2 when (tmp_68_reg_2729(0) = '1') else
tmp_13_fu_847_p1;
tmp_15_fu_941_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_70_fu_933_p3),20));
tmp_16_fu_666_p2 <= std_logic_vector(shift_left(unsigned(p_dst_rows_V_read),to_integer(unsigned('0' & ap_const_lv32_10(31-1 downto 0)))));
tmp_17_fu_951_p2 <= "1" when (signed(srows_reg_2667) > signed(drows_reg_2661)) else "0";
tmp_18_fu_955_p2 <= std_logic_vector(unsigned(ap_const_lv16_1) + unsigned(drows_reg_2661));
tmp_19_fu_967_p2 <= "1" when (signed(scols_reg_2675) > signed(dcols_reg_2655)) else "0";
tmp_20_cast_fu_864_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(scols_reg_2675),17));
tmp_20_fu_971_p2 <= std_logic_vector(unsigned(ap_const_lv16_1) + unsigned(dcols_reg_2655));
tmp_21_fu_983_p2 <= std_logic_vector(signed(ap_const_lv17_1FFFF) + signed(tmp_20_cast_fu_864_p1));
tmp_22_fu_994_p2 <= std_logic_vector(signed(ap_const_lv17_1FFFF) + signed(tmp_13_cast_fu_861_p1));
tmp_23_fu_1005_p2 <= "1" when (signed(row_rate_V_reg_2703) > signed(ap_const_lv32_10000)) else "0";
tmp_24_fu_1010_p2 <= "1" when (signed(col_rate_V_reg_2711) > signed(ap_const_lv32_10000)) else "0";
tmp_25_fu_1015_p3 <= (p_Val2_18_fu_903_p2 & ap_const_lv6_0);
tmp_26_fu_1027_p3 <= (p_Val2_19_fu_945_p2 & ap_const_lv6_0);
tmp_27_fu_1043_p2 <= "1" when (signed(i_op_assign_15_cast_fu_1039_p1) < signed(rows_reg_2759)) else "0";
tmp_28_cast_fu_867_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_10_reg_2739),33));
tmp_28_fu_1054_p2 <= std_logic_vector(unsigned(i_op_assign_15_cast_fu_1039_p1) + unsigned(ap_const_lv16_FFFF));
tmp_29_fu_1060_p2 <= "1" when (p_Val2_16_reg_535 = ap_const_lv15_0) else "0";
tmp_30_fu_1072_p3 <= (p_Val2_16_reg_535 & ap_const_lv16_0);
tmp_31_fu_1088_p2 <= "1" when (signed(i_op_assign_cast_fu_1084_p1) < signed(cols_reg_2764)) else "0";
tmp_32_cast_fu_909_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_14_reg_2749),33));
tmp_34_fu_1103_p3 <= (p_Val2_17_reg_546 & ap_const_lv16_0);
tmp_36_fu_1135_p2 <= std_logic_vector(unsigned(i_op_assign_cast_reg_2845_pp0_iter34_reg) + unsigned(ap_const_lv16_FFFF));
tmp_37_fu_1191_p2 <= "1" when (tmp_74_fu_1187_p1 = ap_const_lv16_0) else "0";
tmp_38_fu_1241_p2 <= "1" when (tmp_76_fu_1237_p1 = ap_const_lv16_0) else "0";
tmp_39_fu_1269_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(p_Val2_2_reg_2932),33));
tmp_40_fu_1272_p3 <= (sx_2_reg_2937 & ap_const_lv16_0);
tmp_41_fu_1289_p2 <= "1" when (signed(r_V_7_fu_1283_p2) > signed(ap_const_lv33_0)) else "0";
tmp_42_fu_690_p2 <= std_logic_vector(shift_left(unsigned(p_dst_cols_V_read),to_integer(unsigned('0' & ap_const_lv32_10(31-1 downto 0)))));
tmp_43_fu_1584_p3 <= (tmp_77_reg_2956_pp0_iter41_reg & ap_const_lv2_0);
tmp_44_fu_1299_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(p_Val2_3_reg_2927),33));
tmp_45_fu_1302_p3 <= (sy_3_reg_2944 & ap_const_lv16_0);
tmp_46_fu_1319_p2 <= "1" when (signed(r_V_8_fu_1313_p2) > signed(ap_const_lv33_0)) else "0";
tmp_47_fu_1695_p3 <= (tmp_78_reg_2966_pp0_iter42_reg & ap_const_lv2_0);
tmp_48_fu_1332_p2 <= "1" when (signed(tmp_76_cast_fu_1329_p1) > signed(tmp_21_reg_2769)) else "0";
tmp_49_cast_fu_1080_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_30_fu_1072_p3),32));
tmp_49_fu_1346_p2 <= "1" when (signed(tmp_78_cast_fu_1343_p1) > signed(tmp_22_reg_2781)) else "0";
tmp_4_i_i1_fu_2169_p2 <= (tmp_89_fu_2161_p3 xor ap_const_lv1_1);
tmp_4_i_i2_fu_2233_p2 <= (tmp_93_fu_2225_p3 xor ap_const_lv1_1);
tmp_4_i_i_fu_2105_p2 <= (tmp_85_fu_2097_p3 xor ap_const_lv1_1);
tmp_50_fu_1120_p2 <= "1" when (p_Val2_17_reg_546 = ap_const_lv15_0) else "0";
tmp_51_fu_1357_p2 <= std_logic_vector(signed(ap_const_lv16_FFFF) + signed(i_op_assign_cast_reg_2845_pp0_iter39_reg));
tmp_52_fu_1501_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(x_2_fu_1398_p3),64));
tmp_53_fu_1517_p2 <= "1" when (signed(tmp_86_cast_fu_1514_p1) < signed(tmp_22_reg_2781)) else "0";
tmp_55_fu_1525_p2 <= "1" when (signed(tmp_88_cast_fu_1522_p1) < signed(tmp_21_reg_2769)) else "0";
tmp_56_fu_1533_p2 <= "1" when (signed(tmp_90_cast_fu_1530_p1) < signed(tmp_21_reg_2769)) else "0";
tmp_59_cast_fu_1023_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_25_fu_1015_p3),32));
tmp_5_fu_798_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_lshr_fu_788_p4),32));
tmp_5_i_i1_fu_2333_p2 <= (p_38_i_i_i1_reg_3497 xor ap_const_lv1_1);
tmp_5_i_i2_fu_2392_p2 <= (p_38_i_i_i2_reg_3515 xor ap_const_lv1_1);
tmp_5_i_i_fu_2274_p2 <= (p_38_i_i_i_reg_3479 xor ap_const_lv1_1);
tmp_61_cast_fu_1035_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_26_fu_1027_p3),32));
tmp_65_fu_818_p1 <= tmp_10_fu_811_p3(26 - 1 downto 0);
tmp_66_cast_fu_1279_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_40_fu_1272_p3),33));
tmp_67_fu_891_p3 <= p_Val2_9_fu_870_p2(5 downto 5);
tmp_69_fu_857_p1 <= tmp_14_fu_850_p3(26 - 1 downto 0);
tmp_70_fu_933_p3 <= p_Val2_13_fu_912_p2(5 downto 5);
tmp_71_fu_1132_p1 <= tmp_33_reg_2882(16 - 1 downto 0);
tmp_72_cast_fu_1309_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_45_fu_1302_p3),33));
tmp_72_fu_1140_p1 <= tmp_35_reg_2887(16 - 1 downto 0);
tmp_73_fu_1179_p3 <= p_Val2_2_fu_1165_p2(31 downto 31);
tmp_74_fu_1187_p1 <= p_Val2_2_fu_1165_p2(16 - 1 downto 0);
tmp_75_fu_1229_p3 <= p_Val2_3_fu_1161_p2(31 downto 31);
tmp_76_cast_fu_1329_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(sx_2_reg_2937),17));
tmp_76_fu_1237_p1 <= p_Val2_3_fu_1161_p2(16 - 1 downto 0);
tmp_77_fu_1295_p1 <= r_V_7_fu_1283_p2(18 - 1 downto 0);
tmp_78_cast_fu_1343_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(sy_3_reg_2944),17));
tmp_78_fu_1325_p1 <= r_V_8_fu_1313_p2(18 - 1 downto 0);
tmp_84_fu_2085_p3 <= p_Val2_30_reg_3389(43 downto 43);
tmp_85_fu_2097_p3 <= p_Val2_32_fu_2092_p2(7 downto 7);
tmp_86_cast_fu_1514_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(sy_4_reg_2989),17));
tmp_88_cast_fu_1522_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(pre_fx_1_reg_2976),17));
tmp_88_fu_2149_p3 <= p_Val2_44_1_reg_3417(43 downto 43);
tmp_89_fu_2161_p3 <= p_Val2_33_fu_2156_p2(7 downto 7);
tmp_90_cast_fu_1530_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(pre_fx_1_reg_2976),17));
tmp_92_fu_2213_p3 <= p_Val2_44_2_reg_3445(43 downto 43);
tmp_93_fu_2225_p3 <= p_Val2_36_fu_2220_p2(7 downto 7);
tmp_9_fu_808_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_lshr_f_reg_2724),32));
tmp_i_i1_fu_2146_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_87_reg_3434),8));
tmp_i_i2_fu_2210_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_91_reg_3462),8));
tmp_i_i_fu_2082_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_83_reg_3406),8));
u1_V_fu_1598_p2 <= std_logic_vector(unsigned(ap_const_lv20_40000) - unsigned(u_V_fu_1591_p3));
u_V_fu_1591_p3 <=
tmp_43_fu_1584_p3 when (tmp_41_reg_2951_pp0_iter41_reg(0) = '1') else
ap_const_lv20_0;
v1_V_fu_1709_p2 <= std_logic_vector(unsigned(ap_const_lv20_40000) - unsigned(v_V_2_fu_1702_p3));
v_V_2_fu_1702_p3 <=
tmp_47_fu_1695_p3 when (tmp_46_reg_2961_pp0_iter42_reg(0) = '1') else
ap_const_lv20_0;
v_V_fu_1715_p3 <=
ap_const_lv20_0 when (tmp_49_reg_2984_pp0_iter42_reg(0) = '1') else
v_V_2_fu_1702_p3;
x_1_fu_1538_p2 <= std_logic_vector(signed(x_2_fu_1398_p3) + signed(ap_const_lv16_1));
x_2_fu_1398_p3 <=
ap_const_lv16_0 when (tmp_50_reg_2865_pp0_iter40_reg(0) = '1') else
x_fu_246;
end behav;
|
mit
|
3cc5369055613610c6bb4a9aa5717a53
| 0.607151 | 2.630273 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/start_for_CvtColomb6.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_CvtColomb6_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_CvtColomb6_shiftReg;
architecture rtl of start_for_CvtColomb6_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_CvtColomb6 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_CvtColomb6 is
component start_for_CvtColomb6_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_CvtColomb6_shiftReg : start_for_CvtColomb6_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
52730f94630199e988ba345783ddc576
| 0.532962 | 3.571997 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/DMA_Operations.vhd
| 2 | 18,504 |
-------------------------------------------------------------------------------
--
-- File: DMA_Operations.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is responsible with implementing the S2MM and MM2S frameworks for the DMA engine
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DMA_Operations is
generic (
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := "0100000000";
C_M_AXI_ADDR_WIDTH : integer := 10;
C_M_AXI_DATA_WIDTH : integer := 32;
C_M_TRANSACTIONS_NUM : integer := 4
);
Port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0);
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
dma_transfer_complete : out std_logic;
start_dma_s2mm : in STD_LOGIC;
start_dma_mm2s : in STD_LOGIC;
dma_source_dest_address : in STD_LOGIC_VECTOR(31 downto 0);
dma_transfer_length : in STD_LOGIC_VECTOR(31 downto 0)
);
end DMA_Operations;
architecture Behavioral of DMA_Operations is
COMPONENT axi_master
PORT(
M_AXI_ACLK : IN std_logic;
M_AXI_ARESETN : IN std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BRESP : IN std_logic_vector(1 downto 0);
M_AXI_BVALID : IN std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RDATA : IN std_logic_vector(31 downto 0);
M_AXI_RRESP : IN std_logic_vector(1 downto 0);
M_AXI_RVALID : IN std_logic;
INIT_WRITE : IN std_logic;
INIT_READ : IN std_logic;
WRITE_DATA : IN std_logic_vector(31 downto 0);
WRITE_ADDRESS : IN std_logic_vector(9 downto 0);
READ_ADDRESS : IN std_logic_vector(9 downto 0);
M_AXI_AWADDR : OUT std_logic_vector(9 downto 0);
M_AXI_AWPROT : OUT std_logic_vector(2 downto 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_WDATA : OUT std_logic_vector(31 downto 0);
M_AXI_WSTRB : OUT std_logic_vector(3 downto 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_BREADY : OUT std_logic;
M_AXI_ARADDR : OUT std_logic_vector(9 downto 0);
M_AXI_ARPROT : OUT std_logic_vector(2 downto 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_RREADY : OUT std_logic;
WRITE_COMPLETE : OUT std_logic;
READ_COMPLETE : OUT std_logic;
READ_DATA : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
type state_type is (IDLE, S2MM_WRITE_DMASR, MM2S_WRITE_DMASR, S2MM_READ_STATUS1, S2MM_READ_STATUS2, WRITE_S2MM_DMACR, WRITE_S2MM_SA, INIT_S2MM_WRITE_LENGTH, MM2S_READ_STATUS1, MM2S_READ_STATUS2, WRITE_MM2S_DMACR, WRITE_MM2S_SA, INIT_MM2S_WRITE_LENGTH);
signal state, next_state : state_type;
-- signal state_ind_dma : STD_LOGIC_VECTOR(4 downto 0);
signal init_write_dma : STD_LOGIC;
signal init_read_dma : STD_LOGIC;
signal init_write_dma_reg : STD_LOGIC;
signal init_read_dma_reg : STD_LOGIC;
signal dma_reg_write_address : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal dma_reg_read_address : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal dma_reg_write_data : STD_LOGIC_VECTOR(31 downto 0);
signal dma_reg_read_data : STD_LOGIC_VECTOR(31 downto 0);
signal dma_reg_write_complete : STD_LOGIC;
signal dma_reg_read_complete : STD_LOGIC;
signal clear_first_transfer_s2mm : STD_LOGIC;
signal is_first_transfer_s2mm : STD_LOGIC;
signal clear_first_transfer_mm2s : STD_LOGIC;
signal is_first_transfer_mm2s : STD_LOGIC;
signal dma_transfer_complete_fsm : STD_LOGIC;
signal start_dma_mm2s_r : STD_LOGIC;
signal start_dma_s2mm_r : STD_LOGIC;
signal start_dma_mm2s_pulse : STD_LOGIC;
signal start_dma_s2mm_pulse : STD_LOGIC;
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of state_ind_dma : signal is "true";
-- attribute keep of state_ind_dma : signal is "true";
-- attribute mark_debug of dma_reg_read_complete : signal is "true";
-- attribute keep of dma_reg_read_complete : signal is "true";
-- attribute mark_debug of is_first_transfer_s2mm : signal is "true";
-- attribute keep of is_first_transfer_s2mm : signal is "true";
begin
DEBUG_REG_DATA <= dma_reg_read_data;
dma_transfer_complete <= dma_transfer_complete_fsm;
Inst_axi_master: axi_master PORT MAP(
M_AXI_ACLK => CLK,
M_AXI_ARESETN => RESETN,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
INIT_WRITE => init_write_dma_reg,
INIT_READ => init_read_dma_reg,
WRITE_COMPLETE => dma_reg_write_complete,
READ_COMPLETE => dma_reg_read_complete,
WRITE_DATA => dma_reg_write_data,
WRITE_ADDRESS => dma_reg_write_address,
READ_DATA => dma_reg_read_data,
READ_ADDRESS => dma_reg_read_address
);
MM2S_PULSE_PROC: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
start_dma_mm2s_r <= '0';
start_dma_mm2s_pulse <= '0';
else
start_dma_mm2s_r <= start_dma_mm2s;
start_dma_mm2s_pulse <= start_dma_mm2s and (not start_dma_mm2s_r);
end if;
end if;
end process;
S2MM_PULSE_PROC: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
start_dma_s2mm_r <= '0';
start_dma_s2mm_pulse <= '0';
else
start_dma_s2mm_r <= start_dma_s2mm;
start_dma_s2mm_pulse <= start_dma_s2mm and (not start_dma_s2mm_r);
end if;
end if;
end process;
FIRST_DMA_TRANSFER_S2MM: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
is_first_transfer_s2mm <= '1';
elsif (clear_first_transfer_s2mm = '1') then
is_first_transfer_s2mm <= '0';
end if;
end if;
end process;
FIRST_DMA_TRANSFER_MM2S: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
is_first_transfer_mm2s <= '1';
elsif (clear_first_transfer_mm2s = '1') then
is_first_transfer_mm2s <= '0';
end if;
end if;
end process;
SYNC_PROC: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
state <= IDLE;
init_write_dma_reg <= '0';
init_read_dma_reg <= '0';
else
state <= next_state;
init_write_dma_reg <= init_write_dma;
init_read_dma_reg <= init_read_dma;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (state, dma_reg_write_complete, dma_reg_read_complete, dma_transfer_length, is_first_transfer_mm2s, is_first_transfer_s2mm, start_dma_s2mm_pulse, dma_reg_read_data, start_dma_mm2s_pulse, dma_source_dest_address)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
state_ind_dma <= "00000";
dma_transfer_complete_fsm <= '0';
init_write_dma <= '0';
init_read_dma <= '0';
dma_reg_write_address <= (others=>'0');
dma_reg_read_address <= (others=>'0');
dma_reg_write_data <= (others=>'0');
clear_first_transfer_s2mm <= '0';
clear_first_transfer_mm2s <= '0';
--insert statements to decode next_state
--below is a simple example
case state is
when IDLE =>
state_ind_dma <= "00000";
--init_write_dma <= '1';
if (start_dma_s2mm_pulse = '1') then
init_read_dma <= '1'; -- initiate axi_master read
next_state <= S2MM_READ_STATUS1;
elsif (start_dma_mm2s_pulse = '1') then
init_read_dma <= '1'; -- initiate axi_master read
next_state <= MM2S_READ_STATUS1;
end if;
when S2MM_READ_STATUS1 =>
state_ind_dma <= "00001";
init_write_dma <= '0';
dma_reg_read_address <= "0000110100";
--dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_read_complete = '1') then
if (dma_reg_read_data(1) = '1' or (dma_reg_read_data(1) = '0' and is_first_transfer_s2mm = '1')) then --DMA controller idle
init_write_dma <= '1'; -- initiate axi_master write
next_state <= WRITE_S2MM_DMACR;
else
init_read_dma <= '1';
next_state <= S2MM_READ_STATUS1;
end if;
end if;
when WRITE_S2MM_DMACR =>
state_ind_dma <= "00010";
init_write_dma <= '0';
dma_reg_write_address <= "0000110000";
dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_write_complete = '1') then
init_write_dma <= '1';
next_state <= WRITE_S2MM_SA;
else
next_state <= WRITE_S2MM_DMACR;
end if;
when WRITE_S2MM_SA =>
state_ind_dma <= "00011";
init_write_dma <= '0';
dma_reg_write_address <= "0001001000";
dma_reg_write_data <= dma_source_dest_address;
if (dma_reg_write_complete = '1') then
init_write_dma <= '1';
next_state <= INIT_S2MM_WRITE_LENGTH;
end if;
when INIT_S2MM_WRITE_LENGTH =>
state_ind_dma <= "00100";
clear_first_transfer_s2mm <= '1';
dma_reg_write_address <= "0001011000";
dma_reg_write_data <= dma_transfer_length;
if (dma_reg_write_complete = '1') then
init_read_dma <= '1';
next_state <= S2MM_READ_STATUS2;
end if;
when S2MM_READ_STATUS2 =>
state_ind_dma <= "00101";
dma_reg_read_address <= "0000110100";
---dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_read_complete = '1') then
if (dma_reg_read_data(12) = '1' and dma_reg_read_data(1) = '1') then --IOC detected
--dma_transfer_complete_fsm <= '1';
init_write_dma <= '1';
next_state <= S2MM_WRITE_DMASR;
else
init_read_dma <= '1';
next_state <= S2MM_READ_STATUS2;
end if;
end if;
when S2MM_WRITE_DMASR =>
state_ind_dma <= "00110";
dma_reg_write_address <= "0000110100";
dma_reg_write_data <= "00000000000000000001000000000000";
if (dma_reg_write_complete = '1') then
dma_transfer_complete_fsm <= '1';
next_state <= IDLE;
end if;
when MM2S_READ_STATUS1 =>
state_ind_dma <= "00111";
init_write_dma <= '0';
dma_reg_read_address <= "0000000100";
--dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_read_complete = '1') then
if (dma_reg_read_data(1) = '1' or (dma_reg_read_data(1) = '0' and is_first_transfer_mm2s = '1')) then
init_write_dma <= '1'; -- initiate axi_master write
next_state <= WRITE_MM2S_DMACR;
else
init_read_dma <= '1';
next_state <= MM2S_READ_STATUS1;
end if;
end if;
when WRITE_MM2S_DMACR =>
state_ind_dma <= "01000";
init_write_dma <= '0';
dma_reg_write_address <= "0000000000";
dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_write_complete = '1') then
init_write_dma <= '1';
next_state <= WRITE_MM2S_SA;
else
next_state <= WRITE_MM2S_DMACR;
end if;
when WRITE_MM2S_SA =>
state_ind_dma <= "01001";
init_write_dma <= '0';
dma_reg_write_address <= "0000011000";
dma_reg_write_data <= dma_source_dest_address;
if (dma_reg_write_complete = '1') then
init_write_dma <= '1';
next_state <= INIT_MM2S_WRITE_LENGTH;
end if;
when INIT_MM2S_WRITE_LENGTH =>
state_ind_dma <= "01010";
clear_first_transfer_mm2s <= '1';
dma_reg_write_address <= "0000101000";
dma_reg_write_data <= dma_transfer_length;
if (dma_reg_write_complete = '1') then
init_read_dma <= '1';
next_state <= MM2S_READ_STATUS2;
end if;
when MM2S_READ_STATUS2 =>
state_ind_dma <= "01011";
dma_reg_read_address <= "0000000100";
--dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_read_complete = '1') then
if (dma_reg_read_data(12) = '1' and dma_reg_read_data(1) = '1') then --IOC detected
--dma_transfer_complete_fsm <= '1';
init_write_dma <= '1';
next_state <= MM2S_WRITE_DMASR;
else
init_read_dma <= '1';
next_state <= MM2S_READ_STATUS2;
end if;
end if;
when MM2S_WRITE_DMASR =>
state_ind_dma <= "01100";
dma_reg_write_address <= "0000000100";
dma_reg_write_data <= "00000000000000000001000000000000";
if (dma_reg_write_complete = '1') then
dma_transfer_complete_fsm <= '1';
next_state <= IDLE;
end if;
when others =>
next_state <= IDLE;
end case;
end process;
end Behavioral;
|
mit
|
d911a2bbc7a745682ceddcc902d83056
| 0.533614 | 3.646827 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/InputBuffer.vhd
| 1 | 3,692 |
-------------------------------------------------------------------------------
--
-- File: InputBuffer.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the input buffers of the required I/O standard
-- for the LP(1:0) and HS pins. The D-PHY lane is expected to be connected
-- to the FPGA according to Xilinx App Note 894:
-- http://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputBuffer is
Generic (
kNoLP : boolean := false
);
Port (
HS_p : in std_logic;
HS_n : in std_logic;
LP_n : in std_logic;
LP_p : in std_logic;
aHS : out std_logic;
aLP : out std_logic_vector(1 downto 0)
);
end InputBuffer;
architecture Behavioral of InputBuffer is
begin
LaneHighSpeed: IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => aHS, -- Buffer output
I => HS_p, -- Diff_p buffer input (connect directly to top-level port)
IB => HS_n -- Diff_n buffer input (connect directly to top-level port)
);
LaneWithLP: if not kNoLP generate
LaneLowPower0: IBUF
generic map (
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "HSUL_12")
port map (
O => aLP(0), -- Buffer output
I => LP_n -- Buffer input (connect directly to top-level port)
);
LaneLowPower1: IBUF
generic map (
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "HSUL_12")
port map (
O => aLP(1), -- Buffer output
I => LP_p -- Buffer input (connect directly to top-level port)
);
end generate LaneWithLP;
LaneWithoutLP: if kNoLP generate
aLP <= "11";
end generate LaneWithoutLP;
end Behavioral;
|
mit
|
91ccb4868b4960ab3f11aa2e1d543db0
| 0.650867 | 4.167043 | false | false | false | false |
SLongofono/digital-design-final-project
|
accel.vhd
| 1 | 4,328 |
----------------------------------------------------------------------------------
-- Engineer: Longofono
-- Create Date: 04/25/2017 09:59:28 PM
-- Description: Accelerometer Interface Circuit
--
-- The circuit makes use of the accelerometer driver and its internal SPI
-- controller to continuously poll the accelerometer for movement. When
-- movement beyond a threshold is detected along any axis of motion, the
-- erase signal is asserted, signalling upstream that the canvas should be
-- erased (equivalent to system reset).
--
-- As is, the accelerometer module outputs a 12 bit 2's complement number
-- representing the acceleration in the x, y, and z directions. We don't
-- necessarily care what direction it is changing in, only that it is not
-- stationary. The accelerometer is quite sensitive, so we look at the
-- two highest bits in each return value to judge movement.
--
-- Written for use with the SPI interface and ADXL362Ctrl modules provided on
-- the Nexys4 Github site. Accessed 4/25/2017:
-- https://github.com/Digilent/Nexys4/tree/master/Projects/User_Demo/src/hdl
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity accel is
generic(system_freq : integer := 100000000; -- System clock speed
serial_freq : integer := 1000000; -- SPI clock speed
average_window : integer := 16; -- Average this many samples
update_frequency : integer := 100); -- Update at this rate
port(clk, rst : in std_logic;
shaking : out std_logic; -- Output to upstream
SCLK : out std_logic; -- SPI clock
MOSI : out std_logic; -- SPI Master output
MISO : in std_logic; -- SPI Master input
SS : out std_logic); -- SPI Slave select
end accel;
architecture behave of accel is
-- Accelerometer control module
component ADXL362Ctrl
generic(SYSCLK_FREQUENCY_HZ : integer := 100000000;
SCLK_FREQUENCY_HZ : integer := 1000000;
NUM_READS_AVG : integer := 16;
UPDATE_FREQUENCY_HZ : integer := 1000);
port(SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
-- Accelerometer data signals
ACCEL_X : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Y : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Z : out STD_LOGIC_VECTOR (11 downto 0);
-- Accumulator for temporary sum (averaging)
ACCEL_TMP : out STD_LOGIC_VECTOR (11 downto 0);
-- Flag data is ready to read
Data_Ready : out STD_LOGIC;
--SPI Interface Signals for internal SPI controller
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
SS : out STD_LOGIC
);
end component;
-- Catch return values from accelerometer
signal x_val : std_logic_vector(11 downto 0);
signal y_val : std_logic_vector(11 downto 0);
signal z_val : std_logic_vector(11 downto 0);
-- Used for averaging as an accumulator
signal acc_tmp : std_logic_vector(11 downto 0);
-- Catch value of hightest two acceleration bits
signal out_val : std_logic;
-- Catch interrupt that data is ready to read
signal s_data : std_logic;
begin -- architecture
-- Accelerometer unit
ACC_UNIT: ADXL362Ctrl
generic map(SYSCLK_FREQUENCY_HZ => system_freq,
SCLK_FREQUENCY_HZ => serial_freq,
NUM_READS_AVG => average_window,
UPDATE_FREQUENCY_HZ => update_frequency)
port map(SYSCLK => clk,
RESET => rst,
ACCEL_X => x_val,
ACCEL_Y => y_val,
ACCEL_Z => z_val,
ACCEL_TMP => acc_tmp,
Data_Ready => s_data,
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO,
SS => SS);
-- Poll s_data, then gather values
process(s_data, rst)
begin
if('1' = rst) then
out_val <= '0';
elsif('1' = s_data) then
-- Negative logic...
out_val <= not( ( (x_val(10) and x_val(9)) or
(y_val(10) and y_val(9)) or
(z_val(10) and z_val(9)) ) );
end if;
end process;
-- Assign output value for upstream modules
shaking <= out_val;
end behave;
|
mit
|
dd150c3c3b58a5ff463444298b8c1d2f
| 0.588494 | 3.867739 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_enhance.vhd
| 1 | 63,772 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_enhance is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC );
end;
architecture behav of hls_saturation_enhance is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"hls_saturation_enhance,hls_ip_2017_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.670000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=7,HLS_SYN_DSP=8,HLS_SYN_FF=7965,HLS_SYN_LUT=7349}";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant C_S_AXI_WSTRB_WIDTH : INTEGER range 63 downto 0 := 4;
constant C_S_AXI_ADDR_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv24_0 : STD_LOGIC_VECTOR (23 downto 0) := "000000000000000000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_logic_0 : STD_LOGIC := '0';
signal ap_rst_n_inv : STD_LOGIC;
signal height : STD_LOGIC_VECTOR (15 downto 0);
signal width : STD_LOGIC_VECTOR (15 downto 0);
signal sat : STD_LOGIC_VECTOR (7 downto 0);
signal Block_Mat_exit1573_p_U0_ap_start : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_start_full_n : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_ap_done : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_ap_continue : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_ap_idle : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_ap_ready : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_start_out : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_start_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img0_rows_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img0_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img0_cols_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img0_cols_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img2_rows_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img2_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img2_cols_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img2_cols_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img3_rows_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img3_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img3_cols_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img3_cols_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din : STD_LOGIC_VECTOR (11 downto 0);
signal Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din : STD_LOGIC_VECTOR (11 downto 0);
signal Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_sat_out_din : STD_LOGIC_VECTOR (7 downto 0);
signal Block_Mat_exit1573_p_U0_sat_out_write : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal AXIvideo2Mat_U0_start_out : STD_LOGIC;
signal AXIvideo2Mat_U0_start_write : STD_LOGIC;
signal AXIvideo2Mat_U0_stream_in_TREADY : STD_LOGIC;
signal AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC;
signal AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_rows_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal AXIvideo2Mat_U0_img_rows_V_out_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_cols_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal AXIvideo2Mat_U0_img_cols_V_out_write : STD_LOGIC;
signal CvtColor_U0_ap_start : STD_LOGIC;
signal CvtColor_U0_ap_done : STD_LOGIC;
signal CvtColor_U0_ap_continue : STD_LOGIC;
signal CvtColor_U0_ap_idle : STD_LOGIC;
signal CvtColor_U0_ap_ready : STD_LOGIC;
signal CvtColor_U0_p_src_rows_V_read : STD_LOGIC;
signal CvtColor_U0_p_src_cols_V_read : STD_LOGIC;
signal CvtColor_U0_p_src_data_stream_0_V_read : STD_LOGIC;
signal CvtColor_U0_p_src_data_stream_1_V_read : STD_LOGIC;
signal CvtColor_U0_p_src_data_stream_2_V_read : STD_LOGIC;
signal CvtColor_U0_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_U0_p_dst_data_stream_0_V_write : STD_LOGIC;
signal CvtColor_U0_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_U0_p_dst_data_stream_1_V_write : STD_LOGIC;
signal CvtColor_U0_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_U0_p_dst_data_stream_2_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_start : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_done : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_continue : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_idle : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_ready : STD_LOGIC;
signal Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img2_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Loop_loop_height_pro_U0_img2_data_stream_0_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_img2_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Loop_loop_height_pro_U0_img2_data_stream_1_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_img2_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Loop_loop_height_pro_U0_img2_data_stream_2_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_img1_data_stream_0_V_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img1_data_stream_1_V_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img1_data_stream_2_V_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_sat_read : STD_LOGIC;
signal CvtColor_1_U0_ap_start : STD_LOGIC;
signal CvtColor_1_U0_ap_done : STD_LOGIC;
signal CvtColor_1_U0_ap_continue : STD_LOGIC;
signal CvtColor_1_U0_ap_idle : STD_LOGIC;
signal CvtColor_1_U0_ap_ready : STD_LOGIC;
signal CvtColor_1_U0_p_src_rows_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_src_cols_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_src_data_stream_0_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_src_data_stream_1_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_src_data_stream_2_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_1_U0_p_dst_data_stream_0_V_write : STD_LOGIC;
signal CvtColor_1_U0_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_1_U0_p_dst_data_stream_1_V_write : STD_LOGIC;
signal CvtColor_1_U0_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_1_U0_p_dst_data_stream_2_V_write : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TDATA : STD_LOGIC_VECTOR (23 downto 0);
signal Mat2AXIvideo_U0_stream_out_TVALID : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TKEEP : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TSTRB : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TID : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal img0_rows_V_c_full_n : STD_LOGIC;
signal img0_rows_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_rows_V_c_empty_n : STD_LOGIC;
signal img0_cols_V_c_full_n : STD_LOGIC;
signal img0_cols_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_cols_V_c_empty_n : STD_LOGIC;
signal img2_rows_V_c_full_n : STD_LOGIC;
signal img2_rows_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img2_rows_V_c_empty_n : STD_LOGIC;
signal img2_cols_V_c_full_n : STD_LOGIC;
signal img2_cols_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img2_cols_V_c_empty_n : STD_LOGIC;
signal img3_rows_V_c_full_n : STD_LOGIC;
signal img3_rows_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img3_rows_V_c_empty_n : STD_LOGIC;
signal img3_cols_V_c_full_n : STD_LOGIC;
signal img3_cols_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img3_cols_V_c_empty_n : STD_LOGIC;
signal p_cols_assign_cast_lo_full_n : STD_LOGIC;
signal p_cols_assign_cast_lo_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_cols_assign_cast_lo_empty_n : STD_LOGIC;
signal p_rows_assign_cast_lo_full_n : STD_LOGIC;
signal p_rows_assign_cast_lo_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_rows_assign_cast_lo_empty_n : STD_LOGIC;
signal sat_c_full_n : STD_LOGIC;
signal sat_c_dout : STD_LOGIC_VECTOR (7 downto 0);
signal sat_c_empty_n : STD_LOGIC;
signal img0_data_stream_0_s_full_n : STD_LOGIC;
signal img0_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img0_data_stream_0_s_empty_n : STD_LOGIC;
signal img0_data_stream_1_s_full_n : STD_LOGIC;
signal img0_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img0_data_stream_1_s_empty_n : STD_LOGIC;
signal img0_data_stream_2_s_full_n : STD_LOGIC;
signal img0_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img0_data_stream_2_s_empty_n : STD_LOGIC;
signal img0_rows_V_c83_full_n : STD_LOGIC;
signal img0_rows_V_c83_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_rows_V_c83_empty_n : STD_LOGIC;
signal img0_cols_V_c84_full_n : STD_LOGIC;
signal img0_cols_V_c84_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_cols_V_c84_empty_n : STD_LOGIC;
signal img1_data_stream_0_s_full_n : STD_LOGIC;
signal img1_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img1_data_stream_0_s_empty_n : STD_LOGIC;
signal img1_data_stream_1_s_full_n : STD_LOGIC;
signal img1_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img1_data_stream_1_s_empty_n : STD_LOGIC;
signal img1_data_stream_2_s_full_n : STD_LOGIC;
signal img1_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img1_data_stream_2_s_empty_n : STD_LOGIC;
signal img2_data_stream_0_s_full_n : STD_LOGIC;
signal img2_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img2_data_stream_0_s_empty_n : STD_LOGIC;
signal img2_data_stream_1_s_full_n : STD_LOGIC;
signal img2_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img2_data_stream_1_s_empty_n : STD_LOGIC;
signal img2_data_stream_2_s_full_n : STD_LOGIC;
signal img2_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img2_data_stream_2_s_empty_n : STD_LOGIC;
signal img3_data_stream_0_s_full_n : STD_LOGIC;
signal img3_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img3_data_stream_0_s_empty_n : STD_LOGIC;
signal img3_data_stream_1_s_full_n : STD_LOGIC;
signal img3_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img3_data_stream_1_s_empty_n : STD_LOGIC;
signal img3_data_stream_2_s_full_n : STD_LOGIC;
signal img3_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img3_data_stream_2_s_empty_n : STD_LOGIC;
signal start_for_Loop_loop_height_pro_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Loop_loop_height_pro_U0_full_n : STD_LOGIC;
signal start_for_Loop_loop_height_pro_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Loop_loop_height_pro_U0_empty_n : STD_LOGIC;
signal start_for_CvtColor_1_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_CvtColor_1_U0_full_n : STD_LOGIC;
signal start_for_CvtColor_1_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_CvtColor_1_U0_empty_n : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_full_n : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_empty_n : STD_LOGIC;
signal start_for_CvtColor_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_CvtColor_U0_full_n : STD_LOGIC;
signal start_for_CvtColor_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_CvtColor_U0_empty_n : STD_LOGIC;
signal CvtColor_U0_start_full_n : STD_LOGIC;
signal CvtColor_U0_start_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_start_full_n : STD_LOGIC;
signal Loop_loop_height_pro_U0_start_write : STD_LOGIC;
signal CvtColor_1_U0_start_full_n : STD_LOGIC;
signal CvtColor_1_U0_start_write : STD_LOGIC;
signal Mat2AXIvideo_U0_start_full_n : STD_LOGIC;
signal Mat2AXIvideo_U0_start_write : STD_LOGIC;
component Block_Mat_exit1573_p IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
height : IN STD_LOGIC_VECTOR (15 downto 0);
width : IN STD_LOGIC_VECTOR (15 downto 0);
sat : IN STD_LOGIC_VECTOR (7 downto 0);
img0_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_rows_V_out_full_n : IN STD_LOGIC;
img0_rows_V_out_write : OUT STD_LOGIC;
img0_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_cols_V_out_full_n : IN STD_LOGIC;
img0_cols_V_out_write : OUT STD_LOGIC;
img2_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_rows_V_out_full_n : IN STD_LOGIC;
img2_rows_V_out_write : OUT STD_LOGIC;
img2_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_cols_V_out_full_n : IN STD_LOGIC;
img2_cols_V_out_write : OUT STD_LOGIC;
img3_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_rows_V_out_full_n : IN STD_LOGIC;
img3_rows_V_out_write : OUT STD_LOGIC;
img3_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_cols_V_out_full_n : IN STD_LOGIC;
img3_cols_V_out_write : OUT STD_LOGIC;
p_cols_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_out_out_full_n : IN STD_LOGIC;
p_cols_assign_cast_out_out_write : OUT STD_LOGIC;
p_rows_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_out_out_full_n : IN STD_LOGIC;
p_rows_assign_cast_out_out_write : OUT STD_LOGIC;
sat_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
sat_out_full_n : IN STD_LOGIC;
sat_out_write : OUT STD_LOGIC );
end component;
component AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC;
img_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_out_full_n : IN STD_LOGIC;
img_rows_V_out_write : OUT STD_LOGIC;
img_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_out_full_n : IN STD_LOGIC;
img_cols_V_out_write : OUT STD_LOGIC );
end component;
component CvtColor IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component Loop_loop_height_pro IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_rows_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_loc_empty_n : IN STD_LOGIC;
p_rows_assign_cast_loc_read : OUT STD_LOGIC;
p_cols_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_loc_empty_n : IN STD_LOGIC;
p_cols_assign_cast_loc_read : OUT STD_LOGIC;
img2_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_0_V_full_n : IN STD_LOGIC;
img2_data_stream_0_V_write : OUT STD_LOGIC;
img2_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_1_V_full_n : IN STD_LOGIC;
img2_data_stream_1_V_write : OUT STD_LOGIC;
img2_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_2_V_full_n : IN STD_LOGIC;
img2_data_stream_2_V_write : OUT STD_LOGIC;
img1_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_0_V_empty_n : IN STD_LOGIC;
img1_data_stream_0_V_read : OUT STD_LOGIC;
img1_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_1_V_empty_n : IN STD_LOGIC;
img1_data_stream_1_V_read : OUT STD_LOGIC;
img1_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_2_V_empty_n : IN STD_LOGIC;
img1_data_stream_2_V_read : OUT STD_LOGIC;
sat_dout : IN STD_LOGIC_VECTOR (7 downto 0);
sat_empty_n : IN STD_LOGIC;
sat_read : OUT STD_LOGIC );
end component;
component CvtColor_1 IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC;
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component fifo_w16_d1_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (15 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (15 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w16_d4_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (15 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (15 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w16_d5_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (15 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (15 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w12_d3_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w8_d3_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w8_d1_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Loop_lotde IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_CvtColoudo IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Mat2AXIvdy IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_CvtColowdI IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component hls_saturation_enhance_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
height : OUT STD_LOGIC_VECTOR (15 downto 0);
width : OUT STD_LOGIC_VECTOR (15 downto 0);
sat : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
hls_saturation_enhance_AXILiteS_s_axi_U : component hls_saturation_enhance_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
height => height,
width => width,
sat => sat);
Block_Mat_exit1573_p_U0 : component Block_Mat_exit1573_p
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Block_Mat_exit1573_p_U0_ap_start,
start_full_n => Block_Mat_exit1573_p_U0_start_full_n,
ap_done => Block_Mat_exit1573_p_U0_ap_done,
ap_continue => Block_Mat_exit1573_p_U0_ap_continue,
ap_idle => Block_Mat_exit1573_p_U0_ap_idle,
ap_ready => Block_Mat_exit1573_p_U0_ap_ready,
start_out => Block_Mat_exit1573_p_U0_start_out,
start_write => Block_Mat_exit1573_p_U0_start_write,
height => height,
width => width,
sat => sat,
img0_rows_V_out_din => Block_Mat_exit1573_p_U0_img0_rows_V_out_din,
img0_rows_V_out_full_n => img0_rows_V_c_full_n,
img0_rows_V_out_write => Block_Mat_exit1573_p_U0_img0_rows_V_out_write,
img0_cols_V_out_din => Block_Mat_exit1573_p_U0_img0_cols_V_out_din,
img0_cols_V_out_full_n => img0_cols_V_c_full_n,
img0_cols_V_out_write => Block_Mat_exit1573_p_U0_img0_cols_V_out_write,
img2_rows_V_out_din => Block_Mat_exit1573_p_U0_img2_rows_V_out_din,
img2_rows_V_out_full_n => img2_rows_V_c_full_n,
img2_rows_V_out_write => Block_Mat_exit1573_p_U0_img2_rows_V_out_write,
img2_cols_V_out_din => Block_Mat_exit1573_p_U0_img2_cols_V_out_din,
img2_cols_V_out_full_n => img2_cols_V_c_full_n,
img2_cols_V_out_write => Block_Mat_exit1573_p_U0_img2_cols_V_out_write,
img3_rows_V_out_din => Block_Mat_exit1573_p_U0_img3_rows_V_out_din,
img3_rows_V_out_full_n => img3_rows_V_c_full_n,
img3_rows_V_out_write => Block_Mat_exit1573_p_U0_img3_rows_V_out_write,
img3_cols_V_out_din => Block_Mat_exit1573_p_U0_img3_cols_V_out_din,
img3_cols_V_out_full_n => img3_cols_V_c_full_n,
img3_cols_V_out_write => Block_Mat_exit1573_p_U0_img3_cols_V_out_write,
p_cols_assign_cast_out_out_din => Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din,
p_cols_assign_cast_out_out_full_n => p_cols_assign_cast_lo_full_n,
p_cols_assign_cast_out_out_write => Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write,
p_rows_assign_cast_out_out_din => Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din,
p_rows_assign_cast_out_out_full_n => p_rows_assign_cast_lo_full_n,
p_rows_assign_cast_out_out_write => Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write,
sat_out_din => Block_Mat_exit1573_p_U0_sat_out_din,
sat_out_full_n => sat_c_full_n,
sat_out_write => Block_Mat_exit1573_p_U0_sat_out_write);
AXIvideo2Mat_U0 : component AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => AXIvideo2Mat_U0_ap_start,
start_full_n => start_for_CvtColor_U0_full_n,
ap_done => AXIvideo2Mat_U0_ap_done,
ap_continue => AXIvideo2Mat_U0_ap_continue,
ap_idle => AXIvideo2Mat_U0_ap_idle,
ap_ready => AXIvideo2Mat_U0_ap_ready,
start_out => AXIvideo2Mat_U0_start_out,
start_write => AXIvideo2Mat_U0_start_write,
stream_in_TDATA => stream_in_TDATA,
stream_in_TVALID => stream_in_TVALID,
stream_in_TREADY => AXIvideo2Mat_U0_stream_in_TREADY,
stream_in_TKEEP => stream_in_TKEEP,
stream_in_TSTRB => stream_in_TSTRB,
stream_in_TUSER => stream_in_TUSER,
stream_in_TLAST => stream_in_TLAST,
stream_in_TID => stream_in_TID,
stream_in_TDEST => stream_in_TDEST,
img_rows_V_dout => img0_rows_V_c_dout,
img_rows_V_empty_n => img0_rows_V_c_empty_n,
img_rows_V_read => AXIvideo2Mat_U0_img_rows_V_read,
img_cols_V_dout => img0_cols_V_c_dout,
img_cols_V_empty_n => img0_cols_V_c_empty_n,
img_cols_V_read => AXIvideo2Mat_U0_img_cols_V_read,
img_data_stream_0_V_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => img0_data_stream_0_s_full_n,
img_data_stream_0_V_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => img0_data_stream_1_s_full_n,
img_data_stream_1_V_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => img0_data_stream_2_s_full_n,
img_data_stream_2_V_write => AXIvideo2Mat_U0_img_data_stream_2_V_write,
img_rows_V_out_din => AXIvideo2Mat_U0_img_rows_V_out_din,
img_rows_V_out_full_n => img0_rows_V_c83_full_n,
img_rows_V_out_write => AXIvideo2Mat_U0_img_rows_V_out_write,
img_cols_V_out_din => AXIvideo2Mat_U0_img_cols_V_out_din,
img_cols_V_out_full_n => img0_cols_V_c84_full_n,
img_cols_V_out_write => AXIvideo2Mat_U0_img_cols_V_out_write);
CvtColor_U0 : component CvtColor
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => CvtColor_U0_ap_start,
ap_done => CvtColor_U0_ap_done,
ap_continue => CvtColor_U0_ap_continue,
ap_idle => CvtColor_U0_ap_idle,
ap_ready => CvtColor_U0_ap_ready,
p_src_rows_V_dout => img0_rows_V_c83_dout,
p_src_rows_V_empty_n => img0_rows_V_c83_empty_n,
p_src_rows_V_read => CvtColor_U0_p_src_rows_V_read,
p_src_cols_V_dout => img0_cols_V_c84_dout,
p_src_cols_V_empty_n => img0_cols_V_c84_empty_n,
p_src_cols_V_read => CvtColor_U0_p_src_cols_V_read,
p_src_data_stream_0_V_dout => img0_data_stream_0_s_dout,
p_src_data_stream_0_V_empty_n => img0_data_stream_0_s_empty_n,
p_src_data_stream_0_V_read => CvtColor_U0_p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout => img0_data_stream_1_s_dout,
p_src_data_stream_1_V_empty_n => img0_data_stream_1_s_empty_n,
p_src_data_stream_1_V_read => CvtColor_U0_p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout => img0_data_stream_2_s_dout,
p_src_data_stream_2_V_empty_n => img0_data_stream_2_s_empty_n,
p_src_data_stream_2_V_read => CvtColor_U0_p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din => CvtColor_U0_p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n => img1_data_stream_0_s_full_n,
p_dst_data_stream_0_V_write => CvtColor_U0_p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din => CvtColor_U0_p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n => img1_data_stream_1_s_full_n,
p_dst_data_stream_1_V_write => CvtColor_U0_p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din => CvtColor_U0_p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n => img1_data_stream_2_s_full_n,
p_dst_data_stream_2_V_write => CvtColor_U0_p_dst_data_stream_2_V_write);
Loop_loop_height_pro_U0 : component Loop_loop_height_pro
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Loop_loop_height_pro_U0_ap_start,
ap_done => Loop_loop_height_pro_U0_ap_done,
ap_continue => Loop_loop_height_pro_U0_ap_continue,
ap_idle => Loop_loop_height_pro_U0_ap_idle,
ap_ready => Loop_loop_height_pro_U0_ap_ready,
p_rows_assign_cast_loc_dout => p_rows_assign_cast_lo_dout,
p_rows_assign_cast_loc_empty_n => p_rows_assign_cast_lo_empty_n,
p_rows_assign_cast_loc_read => Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read,
p_cols_assign_cast_loc_dout => p_cols_assign_cast_lo_dout,
p_cols_assign_cast_loc_empty_n => p_cols_assign_cast_lo_empty_n,
p_cols_assign_cast_loc_read => Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read,
img2_data_stream_0_V_din => Loop_loop_height_pro_U0_img2_data_stream_0_V_din,
img2_data_stream_0_V_full_n => img2_data_stream_0_s_full_n,
img2_data_stream_0_V_write => Loop_loop_height_pro_U0_img2_data_stream_0_V_write,
img2_data_stream_1_V_din => Loop_loop_height_pro_U0_img2_data_stream_1_V_din,
img2_data_stream_1_V_full_n => img2_data_stream_1_s_full_n,
img2_data_stream_1_V_write => Loop_loop_height_pro_U0_img2_data_stream_1_V_write,
img2_data_stream_2_V_din => Loop_loop_height_pro_U0_img2_data_stream_2_V_din,
img2_data_stream_2_V_full_n => img2_data_stream_2_s_full_n,
img2_data_stream_2_V_write => Loop_loop_height_pro_U0_img2_data_stream_2_V_write,
img1_data_stream_0_V_dout => img1_data_stream_0_s_dout,
img1_data_stream_0_V_empty_n => img1_data_stream_0_s_empty_n,
img1_data_stream_0_V_read => Loop_loop_height_pro_U0_img1_data_stream_0_V_read,
img1_data_stream_1_V_dout => img1_data_stream_1_s_dout,
img1_data_stream_1_V_empty_n => img1_data_stream_1_s_empty_n,
img1_data_stream_1_V_read => Loop_loop_height_pro_U0_img1_data_stream_1_V_read,
img1_data_stream_2_V_dout => img1_data_stream_2_s_dout,
img1_data_stream_2_V_empty_n => img1_data_stream_2_s_empty_n,
img1_data_stream_2_V_read => Loop_loop_height_pro_U0_img1_data_stream_2_V_read,
sat_dout => sat_c_dout,
sat_empty_n => sat_c_empty_n,
sat_read => Loop_loop_height_pro_U0_sat_read);
CvtColor_1_U0 : component CvtColor_1
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => CvtColor_1_U0_ap_start,
ap_done => CvtColor_1_U0_ap_done,
ap_continue => CvtColor_1_U0_ap_continue,
ap_idle => CvtColor_1_U0_ap_idle,
ap_ready => CvtColor_1_U0_ap_ready,
p_src_rows_V_dout => img2_rows_V_c_dout,
p_src_rows_V_empty_n => img2_rows_V_c_empty_n,
p_src_rows_V_read => CvtColor_1_U0_p_src_rows_V_read,
p_src_cols_V_dout => img2_cols_V_c_dout,
p_src_cols_V_empty_n => img2_cols_V_c_empty_n,
p_src_cols_V_read => CvtColor_1_U0_p_src_cols_V_read,
p_src_data_stream_0_V_dout => img2_data_stream_0_s_dout,
p_src_data_stream_0_V_empty_n => img2_data_stream_0_s_empty_n,
p_src_data_stream_0_V_read => CvtColor_1_U0_p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout => img2_data_stream_1_s_dout,
p_src_data_stream_1_V_empty_n => img2_data_stream_1_s_empty_n,
p_src_data_stream_1_V_read => CvtColor_1_U0_p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout => img2_data_stream_2_s_dout,
p_src_data_stream_2_V_empty_n => img2_data_stream_2_s_empty_n,
p_src_data_stream_2_V_read => CvtColor_1_U0_p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din => CvtColor_1_U0_p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n => img3_data_stream_0_s_full_n,
p_dst_data_stream_0_V_write => CvtColor_1_U0_p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din => CvtColor_1_U0_p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n => img3_data_stream_1_s_full_n,
p_dst_data_stream_1_V_write => CvtColor_1_U0_p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din => CvtColor_1_U0_p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n => img3_data_stream_2_s_full_n,
p_dst_data_stream_2_V_write => CvtColor_1_U0_p_dst_data_stream_2_V_write);
Mat2AXIvideo_U0 : component Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Mat2AXIvideo_U0_ap_start,
ap_done => Mat2AXIvideo_U0_ap_done,
ap_continue => Mat2AXIvideo_U0_ap_continue,
ap_idle => Mat2AXIvideo_U0_ap_idle,
ap_ready => Mat2AXIvideo_U0_ap_ready,
img_rows_V_dout => img3_rows_V_c_dout,
img_rows_V_empty_n => img3_rows_V_c_empty_n,
img_rows_V_read => Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_dout => img3_cols_V_c_dout,
img_cols_V_empty_n => img3_cols_V_c_empty_n,
img_cols_V_read => Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => img3_data_stream_0_s_dout,
img_data_stream_0_V_empty_n => img3_data_stream_0_s_empty_n,
img_data_stream_0_V_read => Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => img3_data_stream_1_s_dout,
img_data_stream_1_V_empty_n => img3_data_stream_1_s_empty_n,
img_data_stream_1_V_read => Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => img3_data_stream_2_s_dout,
img_data_stream_2_V_empty_n => img3_data_stream_2_s_empty_n,
img_data_stream_2_V_read => Mat2AXIvideo_U0_img_data_stream_2_V_read,
stream_out_TDATA => Mat2AXIvideo_U0_stream_out_TDATA,
stream_out_TVALID => Mat2AXIvideo_U0_stream_out_TVALID,
stream_out_TREADY => stream_out_TREADY,
stream_out_TKEEP => Mat2AXIvideo_U0_stream_out_TKEEP,
stream_out_TSTRB => Mat2AXIvideo_U0_stream_out_TSTRB,
stream_out_TUSER => Mat2AXIvideo_U0_stream_out_TUSER,
stream_out_TLAST => Mat2AXIvideo_U0_stream_out_TLAST,
stream_out_TID => Mat2AXIvideo_U0_stream_out_TID,
stream_out_TDEST => Mat2AXIvideo_U0_stream_out_TDEST);
img0_rows_V_c_U : component fifo_w16_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img0_rows_V_out_din,
if_full_n => img0_rows_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img0_rows_V_out_write,
if_dout => img0_rows_V_c_dout,
if_empty_n => img0_rows_V_c_empty_n,
if_read => AXIvideo2Mat_U0_img_rows_V_read);
img0_cols_V_c_U : component fifo_w16_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img0_cols_V_out_din,
if_full_n => img0_cols_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img0_cols_V_out_write,
if_dout => img0_cols_V_c_dout,
if_empty_n => img0_cols_V_c_empty_n,
if_read => AXIvideo2Mat_U0_img_cols_V_read);
img2_rows_V_c_U : component fifo_w16_d4_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img2_rows_V_out_din,
if_full_n => img2_rows_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img2_rows_V_out_write,
if_dout => img2_rows_V_c_dout,
if_empty_n => img2_rows_V_c_empty_n,
if_read => CvtColor_1_U0_p_src_rows_V_read);
img2_cols_V_c_U : component fifo_w16_d4_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img2_cols_V_out_din,
if_full_n => img2_cols_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img2_cols_V_out_write,
if_dout => img2_cols_V_c_dout,
if_empty_n => img2_cols_V_c_empty_n,
if_read => CvtColor_1_U0_p_src_cols_V_read);
img3_rows_V_c_U : component fifo_w16_d5_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img3_rows_V_out_din,
if_full_n => img3_rows_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img3_rows_V_out_write,
if_dout => img3_rows_V_c_dout,
if_empty_n => img3_rows_V_c_empty_n,
if_read => Mat2AXIvideo_U0_img_rows_V_read);
img3_cols_V_c_U : component fifo_w16_d5_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img3_cols_V_out_din,
if_full_n => img3_cols_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img3_cols_V_out_write,
if_dout => img3_cols_V_c_dout,
if_empty_n => img3_cols_V_c_empty_n,
if_read => Mat2AXIvideo_U0_img_cols_V_read);
p_cols_assign_cast_lo_U : component fifo_w12_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din,
if_full_n => p_cols_assign_cast_lo_full_n,
if_write => Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write,
if_dout => p_cols_assign_cast_lo_dout,
if_empty_n => p_cols_assign_cast_lo_empty_n,
if_read => Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read);
p_rows_assign_cast_lo_U : component fifo_w12_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din,
if_full_n => p_rows_assign_cast_lo_full_n,
if_write => Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write,
if_dout => p_rows_assign_cast_lo_dout,
if_empty_n => p_rows_assign_cast_lo_empty_n,
if_read => Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read);
sat_c_U : component fifo_w8_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_sat_out_din,
if_full_n => sat_c_full_n,
if_write => Block_Mat_exit1573_p_U0_sat_out_write,
if_dout => sat_c_dout,
if_empty_n => sat_c_empty_n,
if_read => Loop_loop_height_pro_U0_sat_read);
img0_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
if_full_n => img0_data_stream_0_s_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
if_dout => img0_data_stream_0_s_dout,
if_empty_n => img0_data_stream_0_s_empty_n,
if_read => CvtColor_U0_p_src_data_stream_0_V_read);
img0_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
if_full_n => img0_data_stream_1_s_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
if_dout => img0_data_stream_1_s_dout,
if_empty_n => img0_data_stream_1_s_empty_n,
if_read => CvtColor_U0_p_src_data_stream_1_V_read);
img0_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
if_full_n => img0_data_stream_2_s_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_2_V_write,
if_dout => img0_data_stream_2_s_dout,
if_empty_n => img0_data_stream_2_s_empty_n,
if_read => CvtColor_U0_p_src_data_stream_2_V_read);
img0_rows_V_c83_U : component fifo_w16_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_rows_V_out_din,
if_full_n => img0_rows_V_c83_full_n,
if_write => AXIvideo2Mat_U0_img_rows_V_out_write,
if_dout => img0_rows_V_c83_dout,
if_empty_n => img0_rows_V_c83_empty_n,
if_read => CvtColor_U0_p_src_rows_V_read);
img0_cols_V_c84_U : component fifo_w16_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_cols_V_out_din,
if_full_n => img0_cols_V_c84_full_n,
if_write => AXIvideo2Mat_U0_img_cols_V_out_write,
if_dout => img0_cols_V_c84_dout,
if_empty_n => img0_cols_V_c84_empty_n,
if_read => CvtColor_U0_p_src_cols_V_read);
img1_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_U0_p_dst_data_stream_0_V_din,
if_full_n => img1_data_stream_0_s_full_n,
if_write => CvtColor_U0_p_dst_data_stream_0_V_write,
if_dout => img1_data_stream_0_s_dout,
if_empty_n => img1_data_stream_0_s_empty_n,
if_read => Loop_loop_height_pro_U0_img1_data_stream_0_V_read);
img1_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_U0_p_dst_data_stream_1_V_din,
if_full_n => img1_data_stream_1_s_full_n,
if_write => CvtColor_U0_p_dst_data_stream_1_V_write,
if_dout => img1_data_stream_1_s_dout,
if_empty_n => img1_data_stream_1_s_empty_n,
if_read => Loop_loop_height_pro_U0_img1_data_stream_1_V_read);
img1_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_U0_p_dst_data_stream_2_V_din,
if_full_n => img1_data_stream_2_s_full_n,
if_write => CvtColor_U0_p_dst_data_stream_2_V_write,
if_dout => img1_data_stream_2_s_dout,
if_empty_n => img1_data_stream_2_s_empty_n,
if_read => Loop_loop_height_pro_U0_img1_data_stream_2_V_read);
img2_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_loop_height_pro_U0_img2_data_stream_0_V_din,
if_full_n => img2_data_stream_0_s_full_n,
if_write => Loop_loop_height_pro_U0_img2_data_stream_0_V_write,
if_dout => img2_data_stream_0_s_dout,
if_empty_n => img2_data_stream_0_s_empty_n,
if_read => CvtColor_1_U0_p_src_data_stream_0_V_read);
img2_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_loop_height_pro_U0_img2_data_stream_1_V_din,
if_full_n => img2_data_stream_1_s_full_n,
if_write => Loop_loop_height_pro_U0_img2_data_stream_1_V_write,
if_dout => img2_data_stream_1_s_dout,
if_empty_n => img2_data_stream_1_s_empty_n,
if_read => CvtColor_1_U0_p_src_data_stream_1_V_read);
img2_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_loop_height_pro_U0_img2_data_stream_2_V_din,
if_full_n => img2_data_stream_2_s_full_n,
if_write => Loop_loop_height_pro_U0_img2_data_stream_2_V_write,
if_dout => img2_data_stream_2_s_dout,
if_empty_n => img2_data_stream_2_s_empty_n,
if_read => CvtColor_1_U0_p_src_data_stream_2_V_read);
img3_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_1_U0_p_dst_data_stream_0_V_din,
if_full_n => img3_data_stream_0_s_full_n,
if_write => CvtColor_1_U0_p_dst_data_stream_0_V_write,
if_dout => img3_data_stream_0_s_dout,
if_empty_n => img3_data_stream_0_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_0_V_read);
img3_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_1_U0_p_dst_data_stream_1_V_din,
if_full_n => img3_data_stream_1_s_full_n,
if_write => CvtColor_1_U0_p_dst_data_stream_1_V_write,
if_dout => img3_data_stream_1_s_dout,
if_empty_n => img3_data_stream_1_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_1_V_read);
img3_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_1_U0_p_dst_data_stream_2_V_din,
if_full_n => img3_data_stream_2_s_full_n,
if_write => CvtColor_1_U0_p_dst_data_stream_2_V_write,
if_dout => img3_data_stream_2_s_dout,
if_empty_n => img3_data_stream_2_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_2_V_read);
start_for_Loop_lotde_U : component start_for_Loop_lotde
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Loop_loop_height_pro_U0_din,
if_full_n => start_for_Loop_loop_height_pro_U0_full_n,
if_write => Block_Mat_exit1573_p_U0_start_write,
if_dout => start_for_Loop_loop_height_pro_U0_dout,
if_empty_n => start_for_Loop_loop_height_pro_U0_empty_n,
if_read => Loop_loop_height_pro_U0_ap_ready);
start_for_CvtColoudo_U : component start_for_CvtColoudo
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_CvtColor_1_U0_din,
if_full_n => start_for_CvtColor_1_U0_full_n,
if_write => Block_Mat_exit1573_p_U0_start_write,
if_dout => start_for_CvtColor_1_U0_dout,
if_empty_n => start_for_CvtColor_1_U0_empty_n,
if_read => CvtColor_1_U0_ap_ready);
start_for_Mat2AXIvdy_U : component start_for_Mat2AXIvdy
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Mat2AXIvideo_U0_din,
if_full_n => start_for_Mat2AXIvideo_U0_full_n,
if_write => Block_Mat_exit1573_p_U0_start_write,
if_dout => start_for_Mat2AXIvideo_U0_dout,
if_empty_n => start_for_Mat2AXIvideo_U0_empty_n,
if_read => Mat2AXIvideo_U0_ap_ready);
start_for_CvtColowdI_U : component start_for_CvtColowdI
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_CvtColor_U0_din,
if_full_n => start_for_CvtColor_U0_full_n,
if_write => AXIvideo2Mat_U0_start_write,
if_dout => start_for_CvtColor_U0_dout,
if_empty_n => start_for_CvtColor_U0_empty_n,
if_read => CvtColor_U0_ap_ready);
AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
AXIvideo2Mat_U0_ap_start <= ap_const_logic_1;
Block_Mat_exit1573_p_U0_ap_continue <= ap_const_logic_1;
Block_Mat_exit1573_p_U0_ap_start <= ap_const_logic_1;
Block_Mat_exit1573_p_U0_start_full_n <= (start_for_Mat2AXIvideo_U0_full_n and start_for_Loop_loop_height_pro_U0_full_n and start_for_CvtColor_1_U0_full_n);
CvtColor_1_U0_ap_continue <= ap_const_logic_1;
CvtColor_1_U0_ap_start <= start_for_CvtColor_1_U0_empty_n;
CvtColor_1_U0_start_full_n <= ap_const_logic_1;
CvtColor_1_U0_start_write <= ap_const_logic_0;
CvtColor_U0_ap_continue <= ap_const_logic_1;
CvtColor_U0_ap_start <= start_for_CvtColor_U0_empty_n;
CvtColor_U0_start_full_n <= ap_const_logic_1;
CvtColor_U0_start_write <= ap_const_logic_0;
Loop_loop_height_pro_U0_ap_continue <= ap_const_logic_1;
Loop_loop_height_pro_U0_ap_start <= start_for_Loop_loop_height_pro_U0_empty_n;
Loop_loop_height_pro_U0_start_full_n <= ap_const_logic_1;
Loop_loop_height_pro_U0_start_write <= ap_const_logic_0;
Mat2AXIvideo_U0_ap_continue <= ap_const_logic_1;
Mat2AXIvideo_U0_ap_start <= start_for_Mat2AXIvideo_U0_empty_n;
Mat2AXIvideo_U0_start_full_n <= ap_const_logic_1;
Mat2AXIvideo_U0_start_write <= ap_const_logic_0;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sync_continue <= ap_const_logic_0;
start_for_CvtColor_1_U0_din <= (0=>ap_const_logic_1, others=>'-');
start_for_CvtColor_U0_din <= (0=>ap_const_logic_1, others=>'-');
start_for_Loop_loop_height_pro_U0_din <= (0=>ap_const_logic_1, others=>'-');
start_for_Mat2AXIvideo_U0_din <= (0=>ap_const_logic_1, others=>'-');
stream_in_TREADY <= AXIvideo2Mat_U0_stream_in_TREADY;
stream_out_TDATA <= Mat2AXIvideo_U0_stream_out_TDATA;
stream_out_TDEST <= Mat2AXIvideo_U0_stream_out_TDEST;
stream_out_TID <= Mat2AXIvideo_U0_stream_out_TID;
stream_out_TKEEP <= Mat2AXIvideo_U0_stream_out_TKEEP;
stream_out_TLAST <= Mat2AXIvideo_U0_stream_out_TLAST;
stream_out_TSTRB <= Mat2AXIvideo_U0_stream_out_TSTRB;
stream_out_TUSER <= Mat2AXIvideo_U0_stream_out_TUSER;
stream_out_TVALID <= Mat2AXIvideo_U0_stream_out_TVALID;
end behav;
|
mit
|
972978b5b473f649ff2b8350495c542e
| 0.617293 | 2.703578 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/start_for_CvtColokbM.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_CvtColokbM_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_CvtColokbM_shiftReg;
architecture rtl of start_for_CvtColokbM_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_CvtColokbM is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_CvtColokbM is
component start_for_CvtColokbM_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_CvtColokbM_shiftReg : start_for_CvtColokbM_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
008786344bb1447fafebdd02c08975fb
| 0.532962 | 3.594876 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/Resize.vhd
| 1 | 27,025 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Resize is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_rows_V_empty_n : IN STD_LOGIC;
p_dst_rows_V_read : OUT STD_LOGIC;
p_dst_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_cols_V_empty_n : IN STD_LOGIC;
p_dst_cols_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC;
p_dst_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
p_dst_rows_V_out_full_n : IN STD_LOGIC;
p_dst_rows_V_out_write : OUT STD_LOGIC;
p_dst_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
p_dst_cols_V_out_full_n : IN STD_LOGIC;
p_dst_cols_V_out_write : OUT STD_LOGIC );
end;
architecture behav of Resize is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal p_src_rows_V_blk_n : STD_LOGIC;
signal p_src_cols_V_blk_n : STD_LOGIC;
signal p_dst_rows_V_blk_n : STD_LOGIC;
signal p_dst_cols_V_blk_n : STD_LOGIC;
signal p_dst_rows_V_out_blk_n : STD_LOGIC;
signal p_dst_cols_V_out_blk_n : STD_LOGIC;
signal p_dst_rows_V_read_reg_248 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_state1 : BOOLEAN;
signal p_dst_cols_V_read_reg_253 : STD_LOGIC_VECTOR (31 downto 0);
signal p_src_rows_V_read_reg_258 : STD_LOGIC_VECTOR (31 downto 0);
signal p_src_cols_V_read_reg_263 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_Resize_opr_linear_fu_224_ap_start : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_ap_done : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_ap_idle : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_ap_ready : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_p_src_data_stream_0_V_read : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_p_src_data_stream_1_V_read : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_p_src_data_stream_2_V_read : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal grp_Resize_opr_linear_fu_224_p_dst_data_stream_0_V_write : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal grp_Resize_opr_linear_fu_224_p_dst_data_stream_1_V_write : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal grp_Resize_opr_linear_fu_224_p_dst_data_stream_2_V_write : STD_LOGIC;
signal grp_Resize_opr_linear_fu_224_ap_start_reg : STD_LOGIC := '0';
signal ap_block_state1_ignore_call18 : BOOLEAN;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
component Resize_opr_linear IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_rows_V_read : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_cols_V_read : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end component;
begin
grp_Resize_opr_linear_fu_224 : component Resize_opr_linear
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_Resize_opr_linear_fu_224_ap_start,
ap_done => grp_Resize_opr_linear_fu_224_ap_done,
ap_idle => grp_Resize_opr_linear_fu_224_ap_idle,
ap_ready => grp_Resize_opr_linear_fu_224_ap_ready,
p_src_rows_V_read => p_src_rows_V_read_reg_258,
p_src_cols_V_read => p_src_cols_V_read_reg_263,
p_src_data_stream_0_V_dout => p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n => p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read => grp_Resize_opr_linear_fu_224_p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout => p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n => p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read => grp_Resize_opr_linear_fu_224_p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout => p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n => p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read => grp_Resize_opr_linear_fu_224_p_src_data_stream_2_V_read,
p_dst_rows_V_read => p_dst_rows_V_read_reg_248,
p_dst_cols_V_read => p_dst_cols_V_read_reg_253,
p_dst_data_stream_0_V_din => grp_Resize_opr_linear_fu_224_p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n => p_dst_data_stream_0_V_full_n,
p_dst_data_stream_0_V_write => grp_Resize_opr_linear_fu_224_p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din => grp_Resize_opr_linear_fu_224_p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n => p_dst_data_stream_1_V_full_n,
p_dst_data_stream_1_V_write => grp_Resize_opr_linear_fu_224_p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din => grp_Resize_opr_linear_fu_224_p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n => p_dst_data_stream_2_V_full_n,
p_dst_data_stream_2_V_write => grp_Resize_opr_linear_fu_224_p_dst_data_stream_2_V_write);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (grp_Resize_opr_linear_fu_224_ap_done = ap_const_logic_1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
grp_Resize_opr_linear_fu_224_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_Resize_opr_linear_fu_224_ap_start_reg <= ap_const_logic_0;
else
if ((not(((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
grp_Resize_opr_linear_fu_224_ap_start_reg <= ap_const_logic_1;
elsif ((grp_Resize_opr_linear_fu_224_ap_ready = ap_const_logic_1)) then
grp_Resize_opr_linear_fu_224_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_dst_cols_V_read_reg_253 <= p_dst_cols_V_dout;
p_dst_rows_V_read_reg_248 <= p_dst_rows_V_dout;
p_src_cols_V_read_reg_263 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_258 <= p_src_rows_V_dout;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, p_dst_rows_V_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_out_full_n, p_dst_cols_V_out_full_n, grp_Resize_opr_linear_fu_224_ap_done, ap_CS_fsm_state2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (grp_Resize_opr_linear_fu_224_ap_done = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_block_state1_assign_proc : process(real_start, ap_done_reg, p_src_rows_V_empty_n, p_src_cols_V_empty_n, p_dst_rows_V_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_out_full_n, p_dst_cols_V_out_full_n)
begin
ap_block_state1 <= ((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state1_ignore_call18_assign_proc : process(real_start, ap_done_reg, p_src_rows_V_empty_n, p_src_cols_V_empty_n, p_dst_rows_V_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_out_full_n, p_dst_cols_V_out_full_n)
begin
ap_block_state1_ignore_call18 <= ((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(ap_done_reg, grp_Resize_opr_linear_fu_224_ap_done, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (grp_Resize_opr_linear_fu_224_ap_done = ap_const_logic_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= internal_ap_ready;
grp_Resize_opr_linear_fu_224_ap_start <= grp_Resize_opr_linear_fu_224_ap_start_reg;
internal_ap_ready_assign_proc : process(grp_Resize_opr_linear_fu_224_ap_done, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (grp_Resize_opr_linear_fu_224_ap_done = ap_const_logic_1))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
p_dst_cols_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_dst_cols_V_empty_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_dst_cols_V_blk_n <= p_dst_cols_V_empty_n;
else
p_dst_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_cols_V_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_dst_cols_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_dst_cols_V_out_blk_n <= p_dst_cols_V_out_full_n;
else
p_dst_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_cols_V_out_din <= p_dst_cols_V_dout;
p_dst_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, p_dst_rows_V_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_out_full_n, p_dst_cols_V_out_full_n)
begin
if ((not(((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_dst_cols_V_out_write <= ap_const_logic_1;
else
p_dst_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
p_dst_cols_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, p_dst_rows_V_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_out_full_n, p_dst_cols_V_out_full_n)
begin
if ((not(((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_dst_cols_V_read <= ap_const_logic_1;
else
p_dst_cols_V_read <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_0_V_din <= grp_Resize_opr_linear_fu_224_p_dst_data_stream_0_V_din;
p_dst_data_stream_0_V_write_assign_proc : process(grp_Resize_opr_linear_fu_224_p_dst_data_stream_0_V_write, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_dst_data_stream_0_V_write <= grp_Resize_opr_linear_fu_224_p_dst_data_stream_0_V_write;
else
p_dst_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_1_V_din <= grp_Resize_opr_linear_fu_224_p_dst_data_stream_1_V_din;
p_dst_data_stream_1_V_write_assign_proc : process(grp_Resize_opr_linear_fu_224_p_dst_data_stream_1_V_write, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_dst_data_stream_1_V_write <= grp_Resize_opr_linear_fu_224_p_dst_data_stream_1_V_write;
else
p_dst_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_2_V_din <= grp_Resize_opr_linear_fu_224_p_dst_data_stream_2_V_din;
p_dst_data_stream_2_V_write_assign_proc : process(grp_Resize_opr_linear_fu_224_p_dst_data_stream_2_V_write, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_dst_data_stream_2_V_write <= grp_Resize_opr_linear_fu_224_p_dst_data_stream_2_V_write;
else
p_dst_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_rows_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_dst_rows_V_empty_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_dst_rows_V_blk_n <= p_dst_rows_V_empty_n;
else
p_dst_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_rows_V_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_dst_rows_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_dst_rows_V_out_blk_n <= p_dst_rows_V_out_full_n;
else
p_dst_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_rows_V_out_din <= p_dst_rows_V_dout;
p_dst_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, p_dst_rows_V_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_out_full_n, p_dst_cols_V_out_full_n)
begin
if ((not(((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_dst_rows_V_out_write <= ap_const_logic_1;
else
p_dst_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
p_dst_rows_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, p_dst_rows_V_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_out_full_n, p_dst_cols_V_out_full_n)
begin
if ((not(((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_dst_rows_V_read <= ap_const_logic_1;
else
p_dst_rows_V_read <= ap_const_logic_0;
end if;
end process;
p_src_cols_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_src_cols_V_empty_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_blk_n <= p_src_cols_V_empty_n;
else
p_src_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_cols_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, p_dst_rows_V_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_out_full_n, p_dst_cols_V_out_full_n)
begin
if ((not(((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_read <= ap_const_logic_1;
else
p_src_cols_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_0_V_read_assign_proc : process(grp_Resize_opr_linear_fu_224_p_src_data_stream_0_V_read, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_src_data_stream_0_V_read <= grp_Resize_opr_linear_fu_224_p_src_data_stream_0_V_read;
else
p_src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_1_V_read_assign_proc : process(grp_Resize_opr_linear_fu_224_p_src_data_stream_1_V_read, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_src_data_stream_1_V_read <= grp_Resize_opr_linear_fu_224_p_src_data_stream_1_V_read;
else
p_src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_2_V_read_assign_proc : process(grp_Resize_opr_linear_fu_224_p_src_data_stream_2_V_read, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_src_data_stream_2_V_read <= grp_Resize_opr_linear_fu_224_p_src_data_stream_2_V_read;
else
p_src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
p_src_rows_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_blk_n <= p_src_rows_V_empty_n;
else
p_src_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_rows_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, p_dst_rows_V_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_out_full_n, p_dst_cols_V_out_full_n)
begin
if ((not(((p_dst_cols_V_out_full_n = ap_const_logic_0) or (p_dst_rows_V_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_dst_cols_V_empty_n = ap_const_logic_0) or (p_dst_rows_V_empty_n = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_read <= ap_const_logic_1;
else
p_src_rows_V_read <= ap_const_logic_0;
end if;
end process;
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
end behav;
|
mit
|
e4fe045c3dd06f0af62a2989cc7c0976
| 0.603515 | 2.59009 | false | false | false | false |
SLongofono/digital-design-final-project
|
controller.vhd
| 1 | 3,023 |
----------------------------------------------------------------------------------
-- Engineer: Gibbons
-- Create Date: 04/30/2017 11:58:17 AM
-- Description: Controller for user input to track location on board.
-- Updates memory based on location and if write is enabled.
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY controller IS
PORT(
clk : in std_logic;
rst : in std_logic;
btn_up : in std_logic;
btn_down : in std_logic;
btn_left : in std_logic;
btn_right : in std_logic;
btn_mode_switch : in std_logic;
addr : out integer;
en_write : out std_logic);
END controller;
ARCHITECTURE behavioral OF controller IS
component button is
port(
clk : in std_logic; -- system clock, assumed 100 MHz
rst : in std_logic; -- system reset
hw_in : in std_logic; -- input from physical button
button_assert : out std_logic);--debounced signal
end component;
constant FRAME_WIDTH : natural := 640;
constant FRAME_HEIGHT : natural := 480;
signal xpos, ypos : integer := 0;
signal mode : std_logic := '1'; -- Move/ Draw mode (0 = 'move', 1 = 'draw')
signal mode_switch, last_mode_switch, up, down, left, right : std_logic := '0';
-- Speed control for input
signal frame_counter : std_logic_vector(20 downto 0) := (others => '0');
signal frame_clk : std_logic;
BEGIN
-- Human friendly clock for responding to input
frame_clk <= frame_counter(20);
process(clk, rst)
begin
if('1' = rst) then
frame_counter <= (others => '0');
elsif(rising_edge(clk)) then
frame_counter <= frame_counter + 1;
end if;
end process;
uut_mode : button
port map(clk, rst, btn_mode_switch, mode_switch);
uut_up : button
port map(clk, rst, btn_up, up);
uut_down : button
port map(clk, rst, btn_down, down);
uut_left : button
port map(clk, rst, btn_left, left);
uut_right : button
port map(clk, rst, btn_right, right);
PROCESS (frame_clk)
BEGIN
xpos <= xpos;
ypos <= ypos;
IF (rst = '1') THEN
xpos <= 0;
ypos <= 0;
mode <= '0';
ELSIF rising_edge(frame_clk) THEN
IF (mode_switch = '1' AND last_mode_switch = '0') THEN
mode <= not(mode);
END IF;
last_mode_switch <= mode_switch;
IF (left = '1' AND xpos > 0) THEN
xpos <= xpos - 1;
ELSIF (right = '1' AND xpos < FRAME_WIDTH-1) THEN
xpos <= xpos + 1;
END IF;
IF (up = '1' AND ypos > 0) THEN
ypos <= ypos - 1;
ELSIF (down = '1' AND ypos < FRAME_HEIGHT-1) THEN
ypos <= ypos + 1;
END IF;
END IF;
END process;
addr <= xpos+ypos*FRAME_WIDTH;
en_write <= mode;
END behavioral;
|
mit
|
a5bbffd5994e64f8972433358e4d70de
| 0.533907 | 3.490762 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/tb/ClockGen_I2C_DataCheck.vhd
| 1 | 8,724 |
-------------------------------------------------------------------------------
--
-- File: ClockGen_I2C_DataCheck.vhd
-- Author: Elod Gyorgy, Robert Bocos
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This modules checks the data sent over I2C by the ConfigClockGen module
-- and compares it with the actual configuration data. Sends out an ERROR
-- when there is a mismatch.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use work.PkgZmodDigitizer.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ClockGen_I2C_DataCheck is
Generic (
kSampleClkFreqInMHz : natural := 100;
kSlaveAddress : std_logic_vector(7 downto 1) := "1101000";
kFreqSel : integer range 0 to 7 := 0
);
Port (
SampleClk : in STD_LOGIC; --at least fSCL*10
sRst : in std_logic;
sI2C_DataOut : out std_logic_vector(7 downto 0);
-- two-wire interface
aSDA_I : in STD_LOGIC;
aSDA_O : out STD_LOGIC;
aSDA_T : out STD_LOGIC;
aSCL_I : in STD_LOGIC;
aSCL_O : out STD_LOGIC;
aSCL_T : out STD_LOGIC);
end ClockGen_I2C_DataCheck;
architecture Behavioral of ClockGen_I2C_DataCheck is
signal sState, sNstate : FsmStatesI2C_t := stIdle;
signal sI2C_DataIn : std_logic_vector(7 downto 0);
signal sI2C_Stb, sI2C_Done, sI2C_End, sI2C_RdWrn : std_logic;
signal sCmdCnt : unsigned(6 downto 0) := (others => '0');
signal sIncCmdCnt : std_logic := '0';
signal sRstCmdCnt : std_logic := '0';
begin
-- Instantiate the I2C Slave Receiver
I2C_SlaveController: entity work.TWI_SlaveCtl
generic map (
SLAVE_ADDRESS => kSlaveAddress & '0',
kSampleClkFreqInMHz => kSampleClkFreqInMHz)
port map (
D_I => (others => '0'),
D_O => sI2C_DataIn,
RD_WRN_O => sI2C_RdWrn,
END_O => sI2C_End,
DONE_O => sI2C_Done,
STB_I => sI2C_Stb,
SampleClk => SampleClk,
SRST => sRst,
--two-wire interface
SDA_I => aSDA_I,
SDA_O => aSDA_O,
SDA_T => aSDA_T,
SCL_I => aSCL_I,
SCL_O => aSCL_O,
SCL_T => aSCL_T);
RegisteredOutputs: process (SampleClk)
begin
if (sRst = '1') then
sRstCmdCnt <= '0';
elsif Rising_Edge(SampleClk) then
if (sI2C_Done = '1') then
if (sState = stRegAddress_H or sState = stRegAddress_L or sState = stRegData_H or sState = stRegData_L) then
sI2C_DataOut <= sI2C_DataIn;
sRstCmdCnt <= '1';
elsif (sState = stCheckCmdCnt) then
sRstCmdCnt <= '1';
end if;
elsif (sI2C_End = '1') then
sRstCmdCnt <= '0';
end if;
end if;
end process RegisteredOutputs;
ProcCmdCheck: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sI2C_Done = '1') then
if (sState = stRegAddress_H) then
assert sI2C_DataIn = CDCE_I2C_Cmds(kFreqSel)(to_integer(sCmdCnt))(31 downto 24)
report "Mismatch between sent CDCE I2C commands and received CDCE I2C commands" & LF & HT & HT
severity ERROR;
elsif (sState = stRegAddress_L) then
assert sI2C_DataIn = CDCE_I2C_Cmds(kFreqSel)(to_integer(sCmdCnt))(23 downto 16)
report "Mismatch between sent CDCE I2C commands and received CDCE I2C commands" & LF & HT & HT
severity ERROR;
elsif (sState = stRegData_H) then
assert sI2C_DataIn = CDCE_I2C_Cmds(kFreqSel)(to_integer(sCmdCnt))(15 downto 8)
report "Mismatch between sent CDCE I2C commands and received CDCE I2C commands" & LF & HT & HT
severity ERROR;
elsif (sState = stRegData_L) then
assert sI2C_DataIn = CDCE_I2C_Cmds(kFreqSel)(to_integer(sCmdCnt))(7 downto 0)
report "Mismatch between sent CDCE I2C commands and received CDCE I2C commands" & LF & HT & HT
severity ERROR;
end if;
end if;
end if;
end process ProcCmdCheck;
-- Counter used to track the number of successfully received commands.
ProcCmdCounter: process (SampleClk, sRst)
begin
if (sRst = '1') then
sCmdCnt <= (others => '0');
elsif (rising_edge(SampleClk)) then
if (sRstCmdCnt = '0') then
sCmdCnt <= (others => '0');
elsif (sIncCmdCnt = '1') then
sCmdCnt <= sCmdCnt + 1;
end if;
end if;
end process;
-- State machine synchronous process.
SyncProc: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sRst = '1') then
sState <= stIdle;
else
sState <= sNstate;
end if;
end if;
end process SyncProc;
--MOORE State-Machine - Outputs based on state only
sI2C_Stb <= '1' when (sState = stRegAddress_H or sState = stRegAddress_L or sState = stRegData_H or sState = stRegData_L) else '0';
sIncCmdCnt <= '1' when (sState = StCheckCmdCnt) else '0';
NextStateDecode: process (sState, sI2C_Done, sI2C_End, sI2C_RdWrn)
begin
--declare default state for next_state to avoid latches
sNstate <= sState;
case (sState) is
when stIdle =>
if (sI2C_Done = '1') then
if (sI2C_RdWrn = '1') then
sNstate <= stIdle;
else
sNstate <= stRegAddress_H;
end if;
end if;
when stRegAddress_H =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stRegAddress_L;
end if;
when stRegAddress_L =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stRegData_H;
end if;
when stRegData_H =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= stRegData_L;
end if;
when stRegData_L =>
if (sI2C_End = '1') then
sNstate <= stIdle;
elsif (sI2C_Done = '1') then
sNstate <= StCheckCmdCnt;
end if;
when StCheckCmdCnt =>
if (sI2C_End = '1') then
sNstate <= stIdle;
else
sNstate <= stRegAddress_H;
end if;
when others =>
sNstate <= stIdle;
end case;
end process NextStateDecode;
end Behavioral;
|
mit
|
d72d4426e4680b634f9d15cd5f16e6ae
| 0.597088 | 4.08427 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/tb/tb_MIPI_CSI2.vhd
| 1 | 9,406 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/13/2017 06:22:52 PM
-- Design Name:
-- Module Name: tb_MIPI_CSI2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_MIPI_CSI2 is
-- Port ( );
end tb_MIPI_CSI2;
architecture Behavioral of tb_MIPI_CSI2 is
component MIPI_CSI2_Rx is
Generic (
kTargetDT : string := "RAW10";
kDebug : boolean := true;
--PPI
kLaneCount : natural range 1 to 4 := 2; --[1,2,4]
--Video Format
C_M_AXIS_COMPONENT_WIDTH : natural := 10; -- [8,10]
C_M_AXIS_TDATA_WIDTH : natural := 40;
C_M_MAX_SAMPLES_PER_CLOCK : natural := 4
);
Port (
--PPI
RxByteClkHS : in STD_LOGIC;
aClkStopstate : in std_logic;
aRxClkActiveHS : in std_logic;
rbRxDataHS : in STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
rbRxSyncHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
rbRxValidHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
rbRxActiveHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
aDEnable : out STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
aClkEnable : out STD_LOGIC;
--axi stream signals
m_axis_video_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_video_tvalid : out std_logic;
m_axis_video_tready : in std_logic;
m_axis_video_tlast : out std_logic;
m_axis_video_tuser : out std_logic_vector(0 downto 0);
video_aresetn : in std_logic;
video_aclk : in std_logic;
vEnable : in std_logic --TODO proper buffer flushing on disable, perhaps waiting on active transfer to end
);
end component MIPI_CSI2_Rx;
constant kTargetDT : string := "RAW10";
constant kLaneCount : natural := 2;
constant C_M_AXIS_COMPONENT_WIDTH : natural := 10; -- [8,10]
constant C_M_AXIS_TDATA_WIDTH : natural := 40;
constant C_M_MAX_SAMPLES_PER_CLOCK : natural := 4;
constant kRxClkPeriod : time := 10 ns;
constant kVidClkPeriod : time := 20ns;
signal mRst_n : std_logic;
signal RxByteClkHS : STD_LOGIC := '0';
signal rbRxDataHS : STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
signal rbRxSyncHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbRxValidHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbRxActiveHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal aDEnable : std_logic_vector(kLaneCount - 1 downto 0);
signal aClkEnable : std_logic;
signal mAxisTdata : std_logic_vector(C_M_AXIS_TDATA_WIDTH - 1 downto 0);
signal mAxisTvalid, mAxisTready, mAxisTlast : std_logic;
signal mAxisTuser : std_logic_vector(0 downto 0);
signal MAxisClk : std_logic := '0';
procedure Idle(signal RxValidHS : out std_logic; signal RxSyncHS : out std_logic;
signal RxActiveHS : out std_logic; signal RxDataHS : out std_logic_vector) is
begin
RxValidHS <= '0';
RxSyncHS <= '0';
RxActiveHS <= '0';
RxDataHS <= (others => '-');
end procedure;
type mem is array (natural range <>) of std_logic_vector(7 downto 0);
--LSByte first
constant fs_err : mem := (x"00", x"01", x"C0", x"1A", x"EF", x"BE"); --frame start with two ECC errors and extra bytes (if no EoT processing is done in PHY)
constant fs : mem := (x"00", x"01", x"00", x"1A"); --frame start with no ECC errors
constant long_err : mem := (x"2B", x"FF", x"FF", x"00", x"00", x"00", x"00", x"00", x"E4", x"E4", x"E4", x"E4"); --uncorrectable error
constant length_err : mem := (x"2B", x"FF", x"FF", x"2D", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"); --correct header, incorrect length
constant longRAW10_err : mem := (x"2B", x"0A", x"80", x"2E", x"00", x"00", x"00", x"00", x"E4", x"01", x"01", x"01", x"01", x"E4", x"E9", x"FB", x"EF", x"BE", x"AD", x"DE"); --active line RAW8, error in third byte 00, extra bytes
constant fe : mem := (x"01", x"01", x"00", x"0D"); --frame end with one ECC error (error in last byte 1D)
begin
RxByteClkHS <= not RxByteClkHS after kRxClkPeriod / 2 when aClkEnable = '1' else
'0';
MAxisClk <= not MAxisClk after kVidClkPeriod / 2;
ResetGen: process
begin
mRst_n <= '0';
-- Reset of 16 clock periods is recommended for AXI IP
for i in 1 to 16 loop
wait until Rising_Edge(MAxisClk);
end loop;
mRst_n <= '1';
wait;
end process;
WriteProc: process
procedure SendPacket(test_vect : in mem) is
variable iLane : natural range test_vect'range := 0;
begin
--Put all lanes in idle then activate them
for iLane in 0 to kLaneCount - 1 loop
Idle(rbRxValidHS(iLane), rbRxSyncHS(iLane), rbRxActiveHS(iLane), rbRxDataHS((iLane+1)*8-1 downto iLane*8));
end loop;
wait for 100ns;
for iLane in 0 to kLaneCount - 1 loop
rbRxActiveHS(iLane) <= '1';
rbRxSyncHS(iLane) <= '1' ;
end loop;
wait until Rising_Edge(RxByteClkHS);
for iLane in 0 to kLaneCount - 1 loop
rbRxSyncHS(iLane) <= '0';
end loop;
iLane := 0;
SendData: for i in test_vect'range loop
rbRxDataHS((iLane+1)*8-1 downto iLane*8) <= test_vect(i);
rbRxValidHS(iLane) <= '1';
if (iLane = kLaneCount - 1) then
iLane := 0;
wait until Rising_Edge(RxByteClkHS);
else
iLane := iLane + 1;
end if;
end loop SendData;
-- EoT on remainder lanes for last packet
for i in iLane to kLaneCount - 1 loop
rbRxValidHS(i) <= '0';
rbRxActiveHS(i) <= '0';
end loop;
wait until Rising_Edge(RxByteClkHS);
-- EoT on all lanes
for iLane in 0 to kLaneCount - 1 loop
Idle(rbRxValidHS(iLane), rbRxSyncHS(iLane), rbRxActiveHS(iLane), rbRxDataHS((iLane+1)*8-1 downto iLane*8));
end loop;
wait until Rising_Edge(RxByteClkHS);
end procedure;
begin
for iLane in 0 to kLaneCount - 1 loop
Idle(rbRxValidHS(iLane), rbRxSyncHS(iLane), rbRxActiveHS(iLane), rbRxDataHS((iLane+1)*8-1 downto iLane*8));
end loop;
wait until aDEnable = "11";
SendPacket(fs_err);
SendPacket(long_err);
SendPacket(length_err);
SendPacket(fs);
SendPacket(longRAW10_err);
SendPacket(long_err);
SendPacket(fe);
wait;
end process;
ReadProc: process
begin
mAxisTready <= '1';
wait until Rising_Edge(MAxisClk) and mAxisTready = '1' and mAxisTvalid = '1';
assert (unsigned(mAxisTdata)=to_unsigned(0,C_M_AXIS_TDATA_WIDTH)) report "Expected throw-away data has unexpected value" severity failure;
for i in 0 to 8 - 1 loop
if (i mod C_M_MAX_SAMPLES_PER_CLOCK = 0) then
wait until Rising_Edge(MAxisClk) and mAxisTready = '1' and mAxisTvalid = '1';
end if;
if (i/C_M_MAX_SAMPLES_PER_CLOCK = 0) then
assert(mAxisTuser="1") report "Tuser not asserted at SOF" severity failure;
else
assert(mAxisTuser="0") report "Tuser asserted mid-frame" severity failure;
end if;
assert (to_unsigned(i,10)=unsigned(mAxisTdata(((i mod C_M_MAX_SAMPLES_PER_CLOCK)+1)*10-1 downto (i mod C_M_MAX_SAMPLES_PER_CLOCK)*10))) report "Output data does not match input" severity failure;
if (i/C_M_MAX_SAMPLES_PER_CLOCK = (8-1)/C_M_MAX_SAMPLES_PER_CLOCK) then
assert(mAxisTlast='1') report "Tlast not asserted at EOL" severity failure;
else
assert(mAxisTlast='0') report "Tlast asserted mid-line" severity failure;
end if;
end loop;
report "Testbench executed successfully" severity note;
wait;
end process;
DUT: MIPI_CSI2_Rx
Generic map(
kTargetDT => kTargetDT,
kDebug => false,
--PPI
kLaneCount => kLaneCount, --[1,2,4]
--Video Format
C_M_AXIS_COMPONENT_WIDTH => C_M_AXIS_COMPONENT_WIDTH, -- [8,10]
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_MAX_SAMPLES_PER_CLOCK => C_M_MAX_SAMPLES_PER_CLOCK
)
Port map(
--PPI
RxByteClkHS => RxByteClkHS,
aClkStopstate => '0',
aRxClkActiveHS => '1',
rbRxDataHS => rbRxDataHS,
rbRxSyncHS => rbRxSyncHS,
rbRxValidHS => rbRxValidHS,
rbRxActiveHS => rbRxActiveHS,
aDEnable => aDEnable,
aClkEnable => aClkEnable,
--axi stream signals
m_axis_video_tdata => mAxisTdata,
m_axis_video_tvalid => mAxisTvalid,
m_axis_video_tready => mAxisTready,
m_axis_video_tlast => mAxisTlast,
m_axis_video_tuser => mAxisTuser,
video_aresetn => mRst_n,
video_aclk => MAxisClk,
vEnable => '1'
);
end Behavioral;
|
mit
|
970dc5ef1cfa3b3635393a5fdd8b06b1
| 0.600255 | 3.700236 | false | false | false | false |
Digilent/vivado-library
|
ip/axi_ps2_1.0/src/Ps2Interface.vhd
| 1 | 36,423 |
------------------------------------------------------------------------------
--
-- File: Ps2Interface.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI PS2
-- Date: 10 October 2017
--
-------------------------------------------------------------------------------
--Copyright (c) 2017 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is responsible for implementing the PS/2 protocol (as host).
-- At its core there is a FSM which, depending on its inputs, performs the
-- necessary PS/2 transactions, either for transmitting or receiving data. Data
-- is also serialized or deserialized inside the FSM, the parity is checked, and
-- its validity is established. It also governs auxiliary processes such as the
-- delays needed to meet PS/2 specific timming. If any errors have occured they
-- will be signaled using either err_par or err_nack.
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file contains the implementation of a generic bidirectional
-- ps/2 interface.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- the ps/2 protocol works.
-- http://www.computer-engineering.org/ps2protocol/
-- This module implements a generic bidirectional ps/2 interface. It can
-- be used with any ps/2 compatible device. It offers its clients a
-- convenient way to exchange data with the device. The interface
-- transparently wraps the byte to be sent into a ps/2 frame, generates
-- parity for byte and sends the frame one bit at a time to the device.
-- Similarly, when receiving data from the ps2 device, the interface
-- receives the frame, checks for parity, and extract the usefull data
-- and forwards it to the client. If an error occurs during receiving
-- or sending a byte, the client is informed by settings the err output
-- line high. This way, the client can resend the data or can issue
-- a resend command to the device.
-- The physical ps/2 interface uses 4 lines
-- For the 6-pin connector pins are assigned as follows:
-- 1 - Data
-- 2 - Not Implemented
-- 3 - Ground
-- 4 - Vcc (+5V)
-- 5 - Clock
-- 6 - Not Implemented
-- The clock line carries the device generated clock which has a
-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
-- it is placed in high impedance. The clock is only generated when
-- device is sending or receiving data.
-- The Data and Clock lines are both open-collector with pullup
-- resistors to Vcc. An "open-collector" interface has two possible
-- states: low('0') or high impedance('Z').
-- When device wants to send a byte, it pulls the clock line low and the
-- host(i.e. this interfaces) recognizes that the device is sending data
-- When the host wants to send data, it makes a request to send. This
-- is done by holding the clock line low for at least 100us, then with
-- the clock line low, the data line is brought low. Next the clock line
-- is released (placed in high impedance). The devices begins generating
-- clock signal on clock line.
-- When receiving data, bits are read from the data line (ps2_data) on
-- the falling edge of the clock (ps2_clk). When sending data, the
-- device reads the bits from the data line on the rising edge of the
-- clock.
-- A frame for sending a byte is comprised of 11 bits as shown bellow:
-- bits 10 9 8 7 6 5 4 3 2 1 0
-- -------------------------------------------------------------
-- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
-- -------------------------------------------------------------
-- STOP - stop bit, always '1'
-- PAR - parity bit, odd parity for the 8 data bits.
-- - select in such way that the number of bits of '1' in the data
-- - bits together with parity bit is odd.
-- D0-7 - data bits.
-- START - start bit, always '0'
--
-- Frame is sent bit by bit starting with the least significant bit
-- (starting bit) and is received the same way. This is done, when
-- receiving, by shifting the frame register to the left when a bit
-- is available and placing the bit on data line on the most significant
-- bit. This way the first bit sent will reach the least significant bit
-- of the frame when all the bits have been received. When sending data
-- the least significant bit of the frame is placed on the data line
-- and the frame is shifted to the right when another bit needs to be
-- sent. During the request to send, when releasing the clock line,
-- the device reads the data line and interprets the data on it as the
-- first bit of the frame. Data line is low at that time, at this is the
-- way the start bit('0') is sent. Because of this, when sending, only
-- 10 shifts of the frame will be made.
-- While the interface is sending or receiving data, the busy output
-- signal goes high. When interface is idle, busy is low.
-- After sending all the bits in the frame, the device must acknowledge
-- the data sent. This is done by the host releasing and data line
-- (clock line is already released) after the last bit is sent. The
-- devices brings the data line and the clock line low, in this order,
-- to acknowledge the data. If data line is high when clock line goes
-- low after last bit, the device did not acknowledge the data and
-- err output is set.
-- A FSM is used to manage the transitions the set all the command
-- signals. States that begin with "rx_" are used to receive data
-- from device and states begining with "tx_" are used to send data
-- to the device.
-- For the parity bit, a ROM holds the parity bit for all possible
-- data (256 possible values, since 8 bits of data). The ROM has
-- dimensions 256x1bit. For obtaining the parity bit of a value,
-- the bit at the data value address is read. Ex: to find the parity
-- bit of 174, the bit at address 174 is read.
-- For generating the necessary delay, counters are used. For example,
-- to generate the 100us delay a 14 bit counter is used that has the
-- upper limit for counting 10000. The interface is designed to run
-- at 100MHz. Thus, 10000x10ns = 100us.
-----------------------------------------------------------------------
-- If using the interface at different frequency than 100MHz, adjusting
-- the delay counters is necessary!!!
-----------------------------------------------------------------------
-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
-- debouncer for the transitions of the clock and data to be clean.
-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
-- value of the clock and data line to the system clock(clk).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- ps2_clk - inout pin, clock line of the ps/2 interface
-- ps2_data - inout pin, data line of the ps/2 interface
-- clk - input pin, system clock signal
-- rst - input pin, system reset signal
-- tx_data - input pin, 8 bits, from client
-- - data to be sent to the device
-- write_data - input pin, from client
-- - should be active for one clock period when the
-- - client wants to send data to the device and
-- - data to be sent is valid on tx_data
-- rx_data - output pin, 8 bits, to client
-- - data received from device
-- read - output pin, to client
-- - active for one clock period when new data is
-- - available from device
-- busy - output pin, to client
-- - active while sending or receiving data.
-- err - output pin, to client
-- - active for one clock period when an error occurred
-- - during sending or receiving.
------------------------------------------------------------------------
-- Revision History:
-- 2016-10-13(SergiuA): added ACK, ERR_PAR, ERR_NACK to module port; fixed DEBOUNCE_DELAY, ; added RESER_STATE to FSM;
-- 2014-12-17(ElodG): added synchronizers on PS/2 interface
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the ps2interface entity declaration
-- read above for behavioral description and port definitions.
entity Ps2Interface is
port(
PS2_Data_I : in std_logic;
PS2_Data_O : out std_logic;
PS2_Data_T : out std_logic;
PS2_Clk_I : in std_logic;
PS2_Clk_O : out std_logic;
PS2_Clk_T : out std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read_data : out std_logic;
ack : out std_logic;
busy : out std_logic;
err_par : out std_logic;
err_nack : out std_logic
);
-- forces the extraction of distributed ram for
-- the parity rom memory.
-- please remove if block ram is preffered.
attribute rom_extract : string;
attribute rom_extract of Ps2Interface: entity is "yes";
attribute rom_style : string;
attribute rom_style of Ps2Interface: entity is "distributed";
end Ps2Interface;
architecture Behavioral of Ps2Interface is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- Values are valid for a 100MHz clk. Please adjust for other
-- frequencies if necessary!
-- upper limit for 100us delay counter.
-- 10000 * 10ns = 100us
constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
-- 10000 clock periods
-- upper limit for 20us delay counter.
-- 2000 * 10ns = 20us
constant DELAY_20US : std_logic_vector(10 downto 0) := "11111010000";
-- 2000 clock periods
-- upper limit for 63clk delay counter.
constant DELAY_63CLK : std_logic_vector(6 downto 0) := "1111111";
-- 63 clock periods
-- delay from debouncing ps2_clk and ps2_data signals
constant DEBOUNCE_DELAY : std_logic_vector(6 downto 0) := "1111111";
-- number of bits in a frame
constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
-- parity bit position in frame
constant PARITY_BIT: positive := 9;
-- (odd) parity bit ROM
-- Used instead of logic because this way speed is far greater
-- 256x1bit rom
-- If the odd parity bit for a 8 bits number, x, is needed
-- the bit at address x is the parity bit.
type ROM is array(0 to 255) of std_logic;
constant parityrom : ROM := (
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1'
);
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- 14 bits counter
-- max value DELAY_100US
-- used to wait 100us
signal delay_100us_count: std_logic_vector(13 downto 0) := (others => '0');
-- 11 bits counter
-- max value DELAY_20US
-- used to wait 20us
signal delay_20us_count: std_logic_vector(10 downto 0) := (others => '0');
-- 11 bits counter
-- max value DELAY_63CLK
-- used to wait 63 clock periods
signal delay_63clk_count: std_logic_vector(6 downto 0) := (others => '0');
-- done signal for the couters above
-- when a counter reaches max value,the corresponding done signal is set
signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
-- enable signal for 100us delay counter
signal delay_100us_counter_enable: std_logic := '0';
-- enable signal for 20us delay counter
signal delay_20us_counter_enable : std_logic := '0';
-- enable signal for 63clk delay counter
signal delay_63clk_counter_enable: std_logic := '0';
-- synchronzed input for ps2_clk and ps2_data
signal ps2_clk_s,ps2_data_s: std_logic := '1';
-- control the output of ps2_clk and ps2_data
-- if 1 then corresponding signal (ps2_clk or ps2_data) is
-- put in high impedance ('Z').
signal ps2_clk_h,ps2_data_h: std_logic := '1';
-- states of the FSM for controlling the communcation with the device
-- states that begin with "rx_" are used when receiving data
-- states that begin with "tx_" are used when transmiting data
type fsm_state is
(
idle,reset_state,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
tx_force_clk_l,tx_bring_data_down,tx_release_clk,
tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
tx_error_no_ack
);
-- the signal that holds the current state of the FSM
-- implicitly state is idle.
signal state: fsm_state := idle;
-- register that holds the frame received or the one to be sent.
-- Its contents are shifted in from the bus one bit at a time
-- from left to right when receiving data and are shifted on the
-- bus (ps2_data) one bit at a time to the right when sending data
signal frame: std_logic_vector(10 downto 0) := (others => '0');
-- how many bits have been sent or received.
signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
-- when active the bit counter is reset.
signal reset_bit_count: std_logic := '0';
-- when active the contents of the frame is shifted to the right
-- and the most significant bit of frame is loaded with ps2_data.
signal shift_frame: std_logic := '0';
-- parity of the byte that was received from the device.
-- must match the parity bit received, else error occurred.
signal rx_parity: std_logic := '0';
-- parity bit that is sent with the frame, representing the
-- odd parity of the byte currently being sent
signal tx_parity: std_logic := '0';
-- when active bits 8 downto 1 from frame are loaded into
-- rx_data register. This is the byte received from the device.
signal load_rx_data: std_logic := '0';
-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
-- debounce counter for the ps2_clk input and the ps2_data input.
signal clk_count,data_count: std_logic_vector(6 downto 0);
-- last value on ps2_clk and ps2_data.
signal clk_inter,data_inter: std_logic := '1';
-- synchronized signals
signal ps2_clk, ps2_data : std_logic;
--signal PS2_Clk_I, PS2_Clk_O, PS2_Clk_T : std_logic;
--signal PS2_Data_I, PS2_Data_O, PS2_Data_T : std_logic;
signal ctl_PS2_Clk_O, ctl_PS2_Data_O : std_logic;
-- reset signal generated by the FSM
signal reset_flag : std_logic := '0';
begin
-- Generic tristate I/O Buffers for PS/2 clock and data
--PS2_Clk_IO <= PS2_Clk_O when PS2_Clk_T = '0' else 'Z';
--PS2_Clk_I <= PS2_Clk_IO;
--PS2_Data_IO <= PS2_Data_O when PS2_Data_T = '0' else 'Z';
--PS2_Data_I <= PS2_Data_IO;
-- Open-drain interface drives '0' and floats '1'
PS2_Clk_T <= ctl_PS2_Clk_O;
PS2_Clk_O <= ctl_PS2_Clk_O;
PS2_Data_O <= ctl_PS2_Data_O;
PS2_Data_T <= ctl_PS2_Data_O;
-- Asynchronous input synchronizers
-- Sync aPS2_Clk signal into the clk domain
SyncAsyncClk: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => PS2_Clk_I,
OutClk => clk,
oOut => ps2_clk);
-- Sync aPS2_Data signal into the clk domain
SyncAsyncData: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => PS2_Data_I,
OutClk => clk,
oOut => ps2_data);
---------------------------------------------------------------------
-- FLAGS and PS2 CLOCK AND DATA LINES
---------------------------------------------------------------------
-- clean ps2_clk signal (debounce)
-- note that this introduces a delay in ps2_clk of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
if reset_flag = '1' then
ps2_clk_clean <= '1';
clk_inter <= '1';
-- if the current bit on ps2_clk is different
-- from the last value, then reset counter
-- and retain value
elsif(ps2_clk /= clk_inter) then
clk_inter <= ps2_clk;
clk_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(clk_count = DEBOUNCE_DELAY) then
ps2_clk_clean <= clk_inter;
-- ps2_clk did not change, but counter did not
-- reach limit. Increment counter
else
clk_count <= clk_count + 1;
end if;
end if;
end process;
-- clean ps2_data signal (debounce)
-- note that this introduces a delay in ps2_data of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_data is different
-- from the last value, then reset counter
-- and retain value
if(ps2_data /= data_inter) then
data_inter <= ps2_data;
data_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(data_count = DEBOUNCE_DELAY) then
ps2_data_clean <= data_inter;
-- ps2_data did not change, but counter did not
-- reach limit. Increment counter
else
data_count <= data_count + 1;
end if;
end if;
end process;
-- Synchronize ps2 entries
ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
ps2_data_s <= ps2_data_clean when rising_edge(clk);
-- Assign parity from frame bits 8 downto 1, this is the parity
-- that should be received inside the frame on PARITY_BIT position
rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
when rising_edge(clk);
-- The parity for the data to be sent
tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
-- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ctl_PS2_Clk_O <= ps2_clk_h;
-- Force ps2_data to '0' if ps2_data_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ctl_PS2_Data_O <= ps2_data_h;
-- Control busy flag. Interface is not busy while in idle state.
busy <= '0' when state = idle else '1';
-- reset the bit counter when in idle state.
reset_bit_count <= '1' when state = idle else '0';
-- Control shifting of the frame
-- When receiving from device, data is read
-- on the falling edge of ps2_clk
-- When sending to device, data is read by device
-- on the rising edge of ps2_clk
shift_frame <= '1' when state = rx_down_edge or
state = tx_clk_l else
'0';
---------------------------------------------------------------------
-- FINITE STATE MACHINE
---------------------------------------------------------------------
-- For the current state establish next state
-- and give necessary commands
manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write_data,tx_data,
bit_count,rx_parity,frame,delay_100us_done,
delay_20us_done,delay_63clk_done)
begin
-- if reset occurs, go to idle state.
if(rst = '1') then
state <= reset_state;
elsif(rising_edge(clk)) then
-- default values for these signals
-- ensures signals are reset to default value
-- when coditions for their activation are no
-- longer applied (transition to other state,
-- where signal should not be active)
-- Idle value for ps2_clk and ps2_data is 'Z'
ps2_clk_h <= '1';
ps2_data_h <= '1';
load_rx_data <= '0';
read_data <= '0';
err_nack <= '0';
err_par <='0';
ack <= '0';
case state is
-- wait for the device to begin a transmission
-- by pulling the clock line low and go to state
-- rx_down_edge or, if write is high, the
-- client of this interface wants to send a byte
-- to the device and a transition is made to state
-- tx_force_clk_l
when idle =>
ack <= '0';
reset_flag <= '0';
if(ps2_clk_s = '0') then
state <= rx_down_edge;
elsif(write_data = '1') then
state <= tx_force_clk_l;
else
state <= idle;
end if;
-- ps2_clk is high, check if all the bits have been read
-- if, last bit read, check parity, and if parity ok
-- load received data into rx_data.
-- else if more bits left, then wait for the ps2_clk to
-- go low
when rx_clk_h =>
if(bit_count = NUMBITS) then
if(not (rx_parity = frame(PARITY_BIT))) then
state <= rx_error_parity;
else
load_rx_data <= '1';
state <= rx_data_ready;
end if;
elsif(ps2_clk_s = '0') then
state <= rx_down_edge;
else
state <= rx_clk_h;
end if;
-- data must be read into frame in this state
-- the ps2_clk just transitioned from high to low
when rx_down_edge =>
state <= rx_clk_l;
-- ps2_clk line is low, wait for it to go high
when rx_clk_l =>
if(ps2_clk_s = '1') then
state <= rx_clk_h;
else
state <= rx_clk_l;
end if;
-- parity bit received is invalid
-- signal error and go back to idle.
when rx_error_parity =>
err_par <= '1';
state <= idle;
-- parity bit received was good
-- set read signal for the client to know
-- a new byte was received and is available on rx_data
when rx_data_ready =>
read_data <= '1';
state <= idle;
-- the client wishes to transmit a byte to the device
-- this is done by holding ps2_clk down for at least 100us
-- bringing down ps2_data, wait 20us and then releasing
-- the ps2_clk.
-- This constitutes a request to send command.
-- In this state, the ps2_clk line is held down and
-- the counter for waiting 100us is eanbled.
-- when the counter reached upper limit, transition
-- to tx_bring_data_down
when tx_force_clk_l =>
if reset_flag = '1' then
if(delay_100us_done = '1') then
ps2_clk_h <= '1';
ps2_data_h <= '1';
state <= idle;
else
state <= tx_force_clk_l;
ps2_clk_h <= '0';
end if;
else
ps2_clk_h <= '0';
if(delay_100us_done = '1') then
state <= tx_bring_data_down;
else
state <= tx_force_clk_l;
end if;
end if;
-- with the ps2_clk line low bring ps2_data low
-- wait for 20us and then go to tx_release_clk
when tx_bring_data_down =>
-- keep clock line low
ps2_clk_h <= '0';
-- set data line low
-- when clock is released in the next state
-- the device will read bit 0 on data line
-- and this bit represents the start bit.
ps2_data_h <= '0'; -- start bit = '0'
if(delay_20us_done = '1') then
state <= tx_release_clk;
else
state <= tx_bring_data_down;
end if;
-- release the ps2_clk line
-- keep holding data line low
when tx_release_clk =>
ps2_clk_h <= '1';
-- must maintain data low,
-- otherwise will be released by default value
ps2_data_h <= '0';
if(ps2_clk_s = '1') then
state <= tx_first_wait_down_edge;
else
state <= tx_release_clk;
end if;
-- state is necessary because the clock signal
-- is not released instantaneously and, because of debounce,
-- delay is even greater.
-- Wait 63 clock periods for the clock line to release
-- then if clock is low then go to tx_clk_l
-- else wait until ps2_clk goes low.
when tx_first_wait_down_edge =>
ps2_data_h <= '0';
if(delay_63clk_done = '1') then --- problem
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_first_wait_down_edge;
end if;
else
state <= tx_first_wait_down_edge;
end if;
-- place the least significant bit from frame
-- on the data line
-- During this state the frame is shifted one
-- bit to the right
when tx_clk_l =>
ps2_data_h <= frame(0);
state <= tx_wait_up_edge;
-- wait for the clock to go high
-- this is the edge on which the device reads the data
-- on ps2_data.
-- keep holding ps2_data on frame(0) because else
-- will be released by default value.
-- Check if sent the last bit and if so, release data line
-- and go to state that wait for acknowledge
when tx_wait_up_edge =>
ps2_data_h <= frame(0);
-- NUMBITS - 1 because first (start bit = 0) bit was read
-- when the clock line was released in the request to
-- send command (see tx_bring_data_down state).
if(bit_count = NUMBITS-1) then
ps2_data_h <= '1';
state <= tx_wait_up_edge_before_ack;
-- if more bits to send, wait for the up edge
-- of ps2_clk
elsif(ps2_clk_s = '1') then
state <= tx_clk_h;
else
state <= tx_wait_up_edge;
end if;
-- ps2_clk is released, wait for down edge
-- and go to tx_clk_l when arrived
when tx_clk_h =>
ps2_data_h <= frame(0);
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_clk_h;
end if;
-- release ps2_data and wait for rising edge of ps2_clk
-- once this occurs, transition to tx_wait_ack
when tx_wait_up_edge_before_ack =>
ps2_data_h <= '1';
if(ps2_clk_s = '1') then
state <= tx_wait_ack;
else
state <= tx_wait_up_edge_before_ack;
end if;
-- wait for the falling edge of the clock line
-- if data line is low when this occurs, the
-- ack is received
-- else if data line is high, the device did not
-- acknowledge the transimission
when tx_wait_ack =>
if(ps2_clk_s = '0') then
if(ps2_data_s = '0') then
-- acknowledge received
state <= tx_received_ack;
else
-- acknowledge not received
state <= tx_error_no_ack;
end if;
else
state <= tx_wait_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
when tx_received_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
ack <= '1';
state <= idle;
else
state <= tx_received_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
-- signal error for not receiving ack
when tx_error_no_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
err_nack <= '1';
state <= idle;
else
state <= tx_error_no_ack;
end if;
when reset_state =>
reset_flag <= '1';
state <= tx_force_clk_l;
-- if invalid transition occurred, signal error and
-- go back to idle state
when others =>
state <= idle;
end case;
end if;
end process manage_fsm;
---------------------------------------------------------------------
-- DELAY COUNTERS
---------------------------------------------------------------------
-- Enable the 100us counter only when state is tx_force_clk_l
delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
-- Counter for a 100us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_100us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_100us_counter_enable = '1') then
if(delay_100us_count = (DELAY_100US)) then
delay_100us_count <= delay_100us_count;
delay_100us_done <= '1';
else
delay_100us_count <= delay_100us_count + 1;
delay_100us_done <= '0';
end if;
else
delay_100us_count <= (others => '0');
delay_100us_done <= '0';
end if;
end if;
end process delay_100us_counter;
-- Enable the 20us counter only when state is tx_bring_data_down
delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
-- Counter for a 20us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_20us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_20us_counter_enable = '1') then
if(delay_20us_count = (DELAY_20US)) then
delay_20us_count <= delay_20us_count;
delay_20us_done <= '1';
else
delay_20us_count <= delay_20us_count + 1;
delay_20us_done <= '0';
end if;
else
delay_20us_count <= (others => '0');
delay_20us_done <= '0';
end if;
end if;
end process delay_20us_counter;
-- Enable the 63clk counter only when state is tx_first_wait_down_edge
delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
-- Counter for a 63 clock periods delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_63clk_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_63clk_counter_enable = '1') then
if(delay_63clk_count = (DELAY_63CLK)) then
delay_63clk_count <= delay_63clk_count;
delay_63clk_done <= '1';
else
delay_63clk_count <= delay_63clk_count + 1;
delay_63clk_done <= '0';
end if;
else
delay_63clk_count <= (others => '0');
delay_63clk_done <= '0';
end if;
end if;
end process delay_63clk_counter;
---------------------------------------------------------------------
-- BIT COUNTER AND FRAME SHIFTING LOGIC
---------------------------------------------------------------------
-- counts the number of bits shifted into the frame
-- or out of the frame.
bit_counter: process(clk)
begin
if(rising_edge(clk)) then
if(reset_bit_count = '1') then
bit_count <= (others => '0');
elsif(shift_frame = '1') then
bit_count <= bit_count + 1;
end if;
end if;
end process bit_counter;
-- shifts frame with one bit to right when shift_frame is acitve
-- and loads data into frame from tx_data then write_data is high
load_tx_data_into_frame: process(clk)
begin
if(rising_edge(clk)) then
if(write_data = '1') then
frame(8 downto 1) <= tx_data; -- byte to send
frame(0) <= '0'; -- start bit
frame(10) <= '1'; -- stop bit
frame(9) <= tx_parity; -- parity bit
elsif(shift_frame = '1') then
-- shift right 1 bit
frame(9 downto 0) <= frame(10 downto 1);
-- shift in from the ps2_data line
frame(10) <= ps2_data_s;
end if;
end if;
end process load_tx_data_into_frame;
-- Loads data from frame into rx_data output when data is ready
do_load_rx_data: process(clk)
begin
if(rising_edge(clk)) then
if(load_rx_data = '1') then
rx_data <= frame(8 downto 1);
end if;
end if;
end process do_load_rx_data;
end Behavioral;
|
mit
|
48da53bba003c4d6ee24d7afbbefc249
| 0.542624 | 3.953435 | false | false | false | false |
grafi-tt/Maizul
|
src/Hardware/U232CSend.vhd
| 1 | 1,570 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity U232CSend is
generic (
wTime : std_logic_vector(15 downto 0) := x"1ADB");
port (
clk : in std_logic;
go : in std_logic;
data : in std_logic_vector (7 downto 0);
tx_pin : out std_logic;
sent : out std_logic);
end U232CSend;
architecture statemachine of U232CSend is
signal countdown : std_logic_vector(15 downto 0) := wTime;
signal buf : std_logic_vector(8 downto 0) := (others => '1');
signal state : integer range 0 to 10 := 10;
begin
sent <= '1' when state = 10 else '0';
tx_pin <= buf(0);
statemachine : process(clk)
begin
if rising_edge(clk) then
case state is
when 10 =>
if go = '1' then
buf <= data&"0";
countdown <= wTime;
state <= state-1;
end if;
when 0 =>
if countdown = 0 then
state <= 10;
else
countdown <= countdown-1;
end if;
when others =>
if countdown = 0 then
buf <= "1"&buf(8 downto 1);
countdown <= wTime;
state <= state-1;
else
countdown <= countdown-1;
end if;
end case;
end if;
end process;
end statemachine;
|
bsd-2-clause
|
6ad9b53ebf3f77569550588eaded8ea4
| 0.443312 | 4.485714 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/tb_TestDataPath_all.vhd
| 2 | 6,005 |
-------------------------------------------------------------------------------
--
-- File: tb_TestDataPath_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to test the DataPath & ADC_Calibration modules
-- with static/dynamic calibration and in normal operation/test mode
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_TestDataPath_all is
-- Port ( );
end tb_TestDataPath_all;
architecture Behavioral of tb_TestDataPath_all is
constant kADC_Width : integer range 10 to 16 := 14;
constant kCh1LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
constant kCh1LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
constant kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010100010";
constant kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111000101";
constant kCh2LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010010010";
constant kCh2LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101101010101";
constant kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101000110010";
constant kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010001";
begin
-- Test the DataPath & ADC_Calibration modules with static calibration and in normal operation.
InstDataPathStaticCalib: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => false,
kSimTestMode => '0',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with dynamic calibration and in normal operation.
InstDataPathExtCalib: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => true,
kSimTestMode => '0',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with static calibration and in test mode.
InstDataPathStaticCalibTestMode: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => false,
kSimTestMode => '1',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with dynamic calibration and in test mode.
InstDataPathExtCalibTestMode: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => true,
kSimTestMode => '1',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
end Behavioral;
|
mit
|
719efb6a38b4a62dc3723f2b4e128d3f
| 0.710908 | 4.946458 | false | true | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
comparator/com_dataflow_2/com_dataflow_2.vhd
| 1 | 869 |
-- Device to compare two binary inputs.
--
entity COM is
-- generic (D:time);
port (N1, N0, M1, M0: in BIT;
GE, LE, E, G, L: out BIT);
end COM;
--
-- Optimum two-level product of sums data flow model.
-- Converted to two-level-nor data flow model.
--
architecture NORDF of COM is
signal Z1,Z0: BIT;
begin
-- process (N1, N0, M1, M0)
-- begin
Z1 <= not(not(not N0 or M1 or M0) or not(not N1 or M1)
or not(not N1 or not N0 or M0));
Z0 <= not(not(N1 or N0 or not M0) or not(N1 or not M1)
or not(N0 or not M1 or not M0));
LE <= Z1;-- after D;
GE <= Z0;-- after D;
E <= not(not Z1 or not Z0);-- after D;
G <= not(not Z0 or Z1);-- after D;
L <= not(not Z1 or Z0);-- after D;
-- end process;
end NORDF;
---Figure 8.13 Another VHDL description of a data flow model for device COM.
|
mit
|
33c01edd731b9f516e1fa1261a256cb9
| 0.570771 | 2.633333 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/Context.vhd
| 2 | 16,973 |
-------------------------------------------------------------------------------
--
-- File: Context.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements the context memory (Queue Heads, Transfer Descriptors)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Context is
generic (
MAX_NR_ENDP : integer := 1
);
Port ( CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
ENDPT_NR : in integer range 0 to (MAX_NR_ENDP*2+1);
-- ENDPT_NR_PD : in integer range 0 to 22;
RD_EN : in STD_LOGIC;
WR_EN : in STD_LOGIC;
dTD_TOTAL_BYTES_WR_EN : in STD_LOGIC;
dTD_STATUS_WR_EN : in STD_LOGIC;
dQH_CURRENT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_NEXT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_SETUP_BUFFER_wr_EN : in STD_LOGIC;
--READ
dQH_MULT_rd : out STD_LOGIC_VECTOR (1 downto 0);
dQH_ZLT_rd : out STD_LOGIC;
-- pe_dQH_ZLT_rd : out STD_LOGIC;
dQH_MAX_PACKET_LENGTH_rd : out STD_LOGIC_VECTOR (10 downto 0);
-- dQH_MAX_PACKET_LENGTH_rd_pd : out STD_LOGIC_VECTOR (10 downto 0);
dQH_IOS_rd : out STD_LOGIC;
dQH_CURRENT_dTD_POINTER_rd : out STD_LOGIC_VECTOR (26 downto 0);
dQH_NEXT_dTD_POINTER_rd : out STD_LOGIC_VECTOR (26 downto 0);
dQH_T_rd : out STD_LOGIC;
dQH_SETUP_BUFFER_BYTES_3_0_rd : out STD_LOGIC_VECTOR (31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : out STD_LOGIC_VECTOR (31 downto 0);
dTD_TOTAL_BYTES_rd : out STD_LOGIC_VECTOR (14 downto 0);
dTD_IOC_rd : out STD_LOGIC;
dTD_C_PAGE_rd : out STD_LOGIC_VECTOR (2 downto 0);
dTD_MULT_rd : out STD_LOGIC_VECTOR (1 downto 0);
dTD_STATUS_rd : out STD_LOGIC_VECTOR (7 downto 0);
dTD_PAGE0_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE1_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE2_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE3_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE4_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_CURRENT_OFFSET_rd : out STD_LOGIC_VECTOR (11 downto 0);
--WRITE
dQH_MULT_wr : in STD_LOGIC_VECTOR (1 downto 0);
dQH_ZLT_wr : in STD_LOGIC;
dQH_MAX_PACKET_LENGTH_wr : in STD_LOGIC_VECTOR (10 downto 0);
dQH_IOS_wr : in STD_LOGIC;
dQH_CURRENT_dTD_POINTER_wr : in STD_LOGIC_VECTOR (26 downto 0);
dQH_NEXT_dTD_POINTER_wr : in STD_LOGIC_VECTOR (26 downto 0);
dQH_T_wr : in STD_LOGIC;
dQH_SETUP_BUFFER_BYTES_3_0_wr : in STD_LOGIC_VECTOR (31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : in STD_LOGIC_VECTOR (31 downto 0);
dTD_TOTAL_BYTES_wr : in STD_LOGIC_VECTOR (14 downto 0);
dTD_IOC_wr : in STD_LOGIC;
dTD_C_PAGE_wr : in STD_LOGIC_VECTOR (2 downto 0);
dTD_MULT_wr : in STD_LOGIC_VECTOR (1 downto 0);
dTD_STATUS_wr : in STD_LOGIC_VECTOR (7 downto 0);
dTD_PAGE0_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE1_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE2_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE3_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE4_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_CURRENT_OFFSET_wr : in STD_LOGIC_VECTOR (11 downto 0)
);
end Context;
architecture Behavioral of Context is
type dQH is
record
dQH_MULT : STD_LOGIC_VECTOR (1 downto 0);
dQH_ZLT : STD_LOGIC;
dQH_MAX_PACKET_LENGTH : STD_LOGIC_VECTOR (10 downto 0);
dQH_IOS : STD_LOGIC;
dQH_CURRENT_dTD_POINTER : STD_LOGIC_VECTOR (26 downto 0);
dQH_NEXT_dTD_POINTER : STD_LOGIC_VECTOR (26 downto 0);
dQH_T : STD_LOGIC;
dQH_SETUP_BUFFER_BYTES_3_0 : STD_LOGIC_VECTOR (31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4 : STD_LOGIC_VECTOR (31 downto 0);
dTD_TOTAL_BYTES : STD_LOGIC_VECTOR (14 downto 0);
dTD_IOC : STD_LOGIC;
dTD_C_PAGE : STD_LOGIC_VECTOR (2 downto 0);
dTD_MULT : STD_LOGIC_VECTOR (1 downto 0);
dTD_STATUS : STD_LOGIC_VECTOR (7 downto 0);
dTD_PAGE0 : STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE1 : STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE2 : STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE3 : STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE4 : STD_LOGIC_VECTOR (19 downto 0);
dTD_CURRENT_OFFSET : STD_LOGIC_VECTOR (11 downto 0);
end record;
type array_DQH is array ((MAX_NR_ENDP*2+1) downto 0) of dQH;
signal dQH_reg : array_DQH;
signal byte_index : integer;
signal dQH_MULT_rd_mux : STD_LOGIC_VECTOR (1 downto 0);
signal dQH_ZLT_rd_mux : STD_LOGIC;
signal dQH_MAX_PACKET_LENGTH_rd_mux : STD_LOGIC_VECTOR (10 downto 0);
signal dQH_IOS_rd_mux : STD_LOGIC;
signal dQH_CURRENT_dTD_POINTER_rd_mux : STD_LOGIC_VECTOR (26 downto 0);
signal dQH_NEXT_dTD_POINTER_rd_mux : STD_LOGIC_VECTOR (26 downto 0);
signal dQH_T_rd_mux : STD_LOGIC;
signal dQH_SETUP_BUFFER_BYTES_3_0_rd_mux : STD_LOGIC_VECTOR (31 downto 0);
signal dQH_SETUP_BUFFER_BYTES_7_4_rd_mux : STD_LOGIC_VECTOR (31 downto 0);
signal dTD_TOTAL_BYTES_rd_mux : STD_LOGIC_VECTOR (14 downto 0);
signal dTD_IOC_rd_mux : STD_LOGIC;
signal dTD_C_PAGE_rd_mux : STD_LOGIC_VECTOR (2 downto 0);
signal dTD_MULT_rd_mux : STD_LOGIC_VECTOR (1 downto 0);
signal dTD_STATUS_rd_mux : STD_LOGIC_VECTOR (7 downto 0);
signal dTD_PAGE0_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_PAGE1_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_PAGE2_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_PAGE3_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_PAGE4_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_CURRENT_OFFSET_rd_mux : STD_LOGIC_VECTOR (11 downto 0);
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of dQH_reg : signal is "true";
-- attribute keep of dQH_reg : signal is "true";
begin
dQH_MULT_rd <= dQH_MULT_rd_mux;
dQH_ZLT_rd <= dQH_ZLT_rd_mux;
dQH_MAX_PACKET_LENGTH_rd <= dQH_MAX_PACKET_LENGTH_rd_mux;
dQH_IOS_rd <= dQH_IOS_rd_mux;
dQH_CURRENT_dTD_POINTER_rd <= dQH_CURRENT_dTD_POINTER_rd_mux;
dQH_NEXT_dTD_POINTER_rd <= dQH_NEXT_dTD_POINTER_rd_mux;
dQH_T_rd <= dQH_T_rd_mux;
dQH_SETUP_BUFFER_BYTES_3_0_rd <= dQH_SETUP_BUFFER_BYTES_3_0_rd_mux;
dQH_SETUP_BUFFER_BYTES_7_4_rd <= dQH_SETUP_BUFFER_BYTES_7_4_rd_mux;
dTD_TOTAL_BYTES_rd <= dTD_TOTAL_BYTES_rd_mux;
dTD_IOC_rd <= dTD_IOC_rd_mux;
dTD_C_PAGE_rd <= dTD_C_PAGE_rd_mux;
dTD_MULT_rd <= dTD_MULT_rd_mux;
dTD_STATUS_rd <= dTD_STATUS_rd_mux;
dTD_PAGE0_rd <= dTD_PAGE0_rd_mux;
dTD_PAGE1_rd <= dTD_PAGE1_rd_mux;
dTD_PAGE2_rd <= dTD_PAGE2_rd_mux;
dTD_PAGE3_rd <= dTD_PAGE3_rd_mux;
dTD_PAGE4_rd <= dTD_PAGE4_rd_mux;
dTD_CURRENT_OFFSET_rd <= dTD_CURRENT_OFFSET_rd_mux;
process(CLK)
begin
if (rising_edge (CLK)) then
if (RESETN = '0') then
dQH_MULT_rd_mux <= (others => '0');
dQH_ZLT_rd_mux <= '0';
dQH_MAX_PACKET_LENGTH_rd_mux <= (others => '0');
dQH_IOS_rd_mux <= '0';
dQH_CURRENT_dTD_POINTER_rd_mux <= (others => '0');
dQH_NEXT_dTD_POINTER_rd_mux <= (others => '0');
dQH_T_rd_mux <= '0';
dQH_SETUP_BUFFER_BYTES_3_0_rd_mux <= (others => '0');
dQH_SETUP_BUFFER_BYTES_7_4_rd_mux <= (others => '0');
dTD_TOTAL_BYTES_rd_mux <= (others => '0');
dTD_IOC_rd_mux <= '0';
dTD_C_PAGE_rd_mux <= (others => '0');
dTD_MULT_rd_mux <= (others => '0');
dTD_STATUS_rd_mux <= (others => '0');
dTD_PAGE0_rd_mux <= (others => '0');
dTD_PAGE1_rd_mux <= (others => '0');
dTD_PAGE2_rd_mux <= (others => '0');
dTD_PAGE3_rd_mux <= (others => '0');
dTD_PAGE4_rd_mux <= (others => '0');
dTD_CURRENT_OFFSET_rd_mux <= (others => '0');
-- pe_dQH_ZLT_rd <= '0';
-- dQH_MAX_PACKET_LENGTH_rd_pd <= (others => '0');
else
dQH_MULT_rd_mux <= dQH_reg(ENDPT_NR).dQH_MULT;
dQH_ZLT_rd_mux <= dQH_reg(ENDPT_NR). dQH_ZLT;
dQH_MAX_PACKET_LENGTH_rd_mux <= dQH_reg(ENDPT_NR). dQH_MAX_PACKET_LENGTH;
dQH_IOS_rd_mux <= dQH_reg(ENDPT_NR). dQH_IOS;
dQH_CURRENT_dTD_POINTER_rd_mux <= dQH_reg(ENDPT_NR). dQH_CURRENT_dTD_POINTER;
dQH_NEXT_dTD_POINTER_rd_mux <= dQH_reg(ENDPT_NR). dQH_NEXT_dTD_POINTER;
dQH_T_rd_mux <= dQH_reg(ENDPT_NR). dQH_T;
dQH_SETUP_BUFFER_BYTES_3_0_rd_mux <= dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_3_0;
dQH_SETUP_BUFFER_BYTES_7_4_rd_mux <= dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_7_4;
dTD_TOTAL_BYTES_rd_mux <= dQH_reg(ENDPT_NR). dTD_TOTAL_BYTES;
dTD_IOC_rd_mux <= dQH_reg(ENDPT_NR). dTD_IOC;
dTD_C_PAGE_rd_mux <= dQH_reg(ENDPT_NR). dTD_C_PAGE;
dTD_MULT_rd_mux <= dQH_reg(ENDPT_NR). dTD_MULT;
dTD_STATUS_rd_mux <= dQH_reg(ENDPT_NR). dTD_STATUS;
dTD_PAGE0_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE0;
dTD_PAGE1_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE1;
dTD_PAGE2_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE2;
dTD_PAGE3_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE3;
dTD_PAGE4_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE4;
dTD_CURRENT_OFFSET_rd_mux <= dQH_reg(ENDPT_NR). dTD_CURRENT_OFFSET;
-- pe_dQH_ZLT_rd <= dQH_reg(ENDPT_NR_PD). dQH_ZLT;
-- dQH_MAX_PACKET_LENGTH_rd_pd <= dQH_reg(ENDPT_NR_PD). dQH_MAX_PACKET_LENGTH;
end if;
end if;
end process;
process(CLK)
begin
if (rising_edge (CLK)) then
if (RESETN = '0') then
for index in 0 to (MAX_NR_ENDP*2+1) loop
dQH_reg(index). dQH_MULT <= (others => '0');
dQH_reg(index). dQH_ZLT <= '0';
dQH_reg(index). dQH_MAX_PACKET_LENGTH <= (others => '0');
dQH_reg(index). dQH_IOS <= '0';
dQH_reg(index). dQH_CURRENT_dTD_POINTER <= (others => '0');
dQH_reg(index). dQH_NEXT_dTD_POINTER <= (others => '0');
dQH_reg(index). dQH_T <= '0';
dQH_reg(index). dQH_SETUP_BUFFER_BYTES_3_0 <= (others => '0');
dQH_reg(index). dQH_SETUP_BUFFER_BYTES_7_4 <= (others => '0');
dQH_reg(index). dTD_TOTAL_BYTES <= (others => '0');
dQH_reg(index). dTD_IOC <= '0';
dQH_reg(index). dTD_C_PAGE <= (others => '0');
dQH_reg(index). dTD_MULT <= (others => '0');
dQH_reg(index). dTD_STATUS <= (others => '0');
dQH_reg(index). dTD_PAGE0 <= (others => '0');
dQH_reg(index). dTD_PAGE1 <= (others => '0');
dQH_reg(index). dTD_PAGE2 <= (others => '0');
dQH_reg(index). dTD_PAGE3 <= (others => '0');
dQH_reg(index). dTD_PAGE4 <= (others => '0');
dQH_reg(index). dTD_CURRENT_OFFSET <= (others => '0');
end loop;
elsif (WR_EN = '1') then
dQH_reg(ENDPT_NR). dQH_MULT <= dQH_MULT_wr;
dQH_reg(ENDPT_NR). dQH_ZLT <= dQH_ZLT_wr;
dQH_reg(ENDPT_NR). dQH_MAX_PACKET_LENGTH <= dQH_MAX_PACKET_LENGTH_wr;
dQH_reg(ENDPT_NR). dQH_IOS <= dQH_IOS_wr;
--dQH_reg(ENDPT_NR). dQH_CURRENT_dTD_POINTER <= dQH_CURRENT_dTD_POINTER_wr;
dQH_reg(ENDPT_NR). dQH_NEXT_dTD_POINTER <= dQH_NEXT_dTD_POINTER_wr;
dQH_reg(ENDPT_NR). dQH_T <= dQH_T_wr;
dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_3_0 <= dQH_SETUP_BUFFER_BYTES_3_0_wr;
dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_7_4 <= dQH_SETUP_BUFFER_BYTES_7_4_wr;
dQH_reg(ENDPT_NR). dTD_TOTAL_BYTES <= dTD_TOTAL_BYTES_wr;
dQH_reg(ENDPT_NR). dTD_IOC <= dTD_IOC_wr;
dQH_reg(ENDPT_NR). dTD_C_PAGE <= dTD_C_PAGE_wr;
dQH_reg(ENDPT_NR). dTD_MULT <= dTD_MULT_wr;
dQH_reg(ENDPT_NR). dTD_STATUS <= dTD_STATUS_wr;
dQH_reg(ENDPT_NR). dTD_PAGE0 <= dTD_PAGE0_wr;
dQH_reg(ENDPT_NR). dTD_PAGE1 <= dTD_PAGE1_wr;
dQH_reg(ENDPT_NR). dTD_PAGE2 <= dTD_PAGE2_wr;
dQH_reg(ENDPT_NR). dTD_PAGE3 <= dTD_PAGE3_wr;
dQH_reg(ENDPT_NR). dTD_PAGE4 <= dTD_PAGE4_wr;
dQH_reg(ENDPT_NR). dTD_CURRENT_OFFSET <= dTD_CURRENT_OFFSET_wr;
elsif (dTD_TOTAL_BYTES_WR_EN = '1') then
dQH_reg(ENDPT_NR). dTD_TOTAL_BYTES <= dTD_TOTAL_BYTES_wr;
elsif (dQH_CURRENT_dTD_POINTER_wr_EN = '1') then
dQH_reg(ENDPT_NR). dQH_CURRENT_dTD_POINTER <= dQH_CURRENT_dTD_POINTER_wr;
elsif (dQH_NEXT_dTD_POINTER_wr_EN = '1') then
dQH_reg(ENDPT_NR). dQH_NEXT_dTD_POINTER <= dQH_NEXT_dTD_POINTER_wr;
elsif (dTD_STATUS_WR_EN = '1') then
dQH_reg(ENDPT_NR). dTD_STATUS <= dTD_STATUS_wr;
elsif (dQH_SETUP_BUFFER_wr_EN = '1') then
dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_3_0 <= dQH_SETUP_BUFFER_BYTES_3_0_wr;
dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_7_4 <= dQH_SETUP_BUFFER_BYTES_7_4_wr;
end if;
end if;
end process;
end Behavioral;
|
mit
|
1f1cbd348487761d7c6918c3daeb97f1
| 0.539268 | 3.475225 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/MIPI_DPHY_Receiver.vhd
| 1 | 23,806 |
-------------------------------------------------------------------------------
--
-- File: MIPI_DPHY_Receiver.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- The MIPI_DPHY_Receiver IP is an implementation of a subset of the PHY-level
-- protocol of the MIPI D-PHY 1.0 specification. It bundles a SCNN clock lane
-- and one or more SFEN data lanes to implement the reciever end of a Lane
-- Interconnect. In an FPGA implementation of the communication stack
-- it occupies the lowest level. On top of it, over the PHY-Protocol Interface
-- (PPI) connects the protocol layer specific to the application, like the Camera
-- Serial Interface (CSI).
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
use work.DPHY_types.ALL;
use work.DebugLib.all;
entity MIPI_DPHY_Receiver is
generic (
-- Users to add parameters here
kVersionMajor : natural := 0; -- TCL-propagated from VLNV
kVersionMinor : natural := 0; -- TCL-propagated from VLNV
kNoOfDataLanes : natural range 1 to 2:= 2;
kGenerateMMCM : boolean := false;
kGenerateAXIL : boolean := false;
kAddDelayClk_ps : integer := 0;
kAddDelayData0_ps : integer := 0;
kAddDelayData1_ps : integer := 0;
kRefClkFreqHz : integer := 200_000_000; -- TCL-propagated
kDebug : boolean := true;
kLPFromLane0 : boolean := true;
kSharedLogic : boolean := true;
-- Parameters of Axi Slave Bus Interface S_AXI_LITE
C_S_AXI_LITE_DATA_WIDTH : integer := 32;
C_S_AXI_LITE_ADDR_WIDTH : integer := 4;
C_S_AXI_LITE_FREQ_HZ : integer := 100_000_000 -- TCL-propagated
);
port (
-- Users to add ports here
dphy_clk_hs_p : in std_logic;
dphy_clk_hs_n : in std_logic;
dphy_clk_lp_p : in std_logic;
dphy_clk_lp_n : in std_logic;
dphy_data_hs_p : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_hs_n : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_lp_p : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_lp_n : in std_logic_vector(kNoOfDataLanes-1 downto 0);
RefClk : in std_logic; --200MHz
aRst : in std_logic; --Only to be de-asserted when RefClk is valid
rDlyCtrlLockedIn : in std_logic; --if IDELAYCTRL instantiated externally, input its locked signal
rDlyCtrlLockedOut : out std_logic; --if IDELAYCTRL instantiated internally, output its locked signal
--PHY-Protocol Interface (PPI)
--Clock lane
RxDDRClkHS : out std_logic; --Receiver DDR Clock (may be used by the protocol)
aRxClkActiveHS : out std_logic; --Receiver Clock Active
aClkStopstate : out std_logic; --Lane is in Stop state
aClkEnable : in std_logic; --Enable Lane Module
aClkUlpsActiveNot : out std_logic; --ULP State (not) Active
aRxUlpsClkNot : out std_logic; --Receive Ultra-Low Power State on Clock Lane
aClkForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
aClkErrControl : out std_logic; --Control Error
RxByteClkHS : out std_logic; --High-Speed Receive Byte Clock
--Data lane 0
aD0Stopstate : out std_logic; --Lane is in Stop state
aD0Enable : in std_logic; --Enable Lane Module
aD0UlpsActiveNot : out std_logic; --ULP State (not) Active
rbD0RxDataHS : out std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbD0RxValidHS : out std_logic; --High-Speed Receive Data Valid
rbD0RxActiveHS : out std_logic; --High-Speed Reception Active
rbD0RxSyncHS : out std_logic; --Receiver Synchronization Observed (pulse)
rbD0ErrSotHS : out std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbD0ErrSotSyncHS : out std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD0ForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
D0RxClkEsc : out std_logic; --Escape mode Receive Clock (not periodic)
aD0RxDataEsc : out std_logic_vector(7 downto 0); --Escape mode Receive Data
aD0RxValidEsc : out std_logic; --Escape mode Receive Data Valid
aD0RxLpdtEsc : out std_logic; --Escape Low-Power Data Receive Mode
aD0RxUlpsEsc : out std_logic; --Escape Ultra-Low Power (Receive) mode
aD0RxTriggerEsc : out std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aD0ErrEsc : out std_logic; --Escape Entry Error
aD0ErrControl : out std_logic; --Control Error
--Data lane 1
aD1Stopstate : out std_logic; --Lane is in Stop state
aD1Enable : in std_logic; --Enable Lane Module
aD1UlpsActiveNot : out std_logic; --ULP State (not) Active
rbD1RxDataHS : out std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbD1RxValidHS : out std_logic; --High-Speed Receive Data Valid
rbD1RxActiveHS : out std_logic; --High-Speed Reception Active
rbD1RxSyncHS : out std_logic; --Receiver Synchronization Observed (pulse)
rbD1ErrSotHS : out std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbD1ErrSotSyncHS : out std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD1ForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
D1RxClkEsc : out std_logic; --Escape mode Receive Clock (not periodic)
aD1RxDataEsc : out std_logic_vector(7 downto 0); --Escape mode Receive Data
aD1RxValidEsc : out std_logic; --Escape mode Receive Data Valid
aD1RxLpdtEsc : out std_logic; --Escape Low-Power Data Receive Mode
aD1RxUlpsEsc : out std_logic; --Escape Ultra-Low Power (Receive) mode
aD1RxTriggerEsc : out std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aD1ErrEsc : out std_logic; --Escape Entry Error
aD1ErrControl : out std_logic; --Control Error
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_awprot : in std_logic_vector(2 downto 0);
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_wstrb : in std_logic_vector((C_S_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_arprot : in std_logic_vector(2 downto 0);
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic
);
end MIPI_DPHY_Receiver;
architecture arch_imp of MIPI_DPHY_Receiver is
function MIN(LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end;
constant kDlyRstDelay : natural := 32;
constant kGenerateIDELAYCTRL : boolean := kSharedLogic;
constant kCtlClkFreqHz : natural := kRefClkFreqHz;
--make all delays positive
constant kDelayAdjust : integer := MIN(kAddDelayClk_ps, MIN(kAddDelayData0_ps, kAddDelayData1_ps));
constant kAddAdjDelayClk_ps : integer := kAddDelayClk_ps - kDelayAdjust;
constant kAddAdjDelayData0_ps : integer := kAddDelayData0_ps - kDelayAdjust;
constant kAddAdjDelayData1_ps : integer := kAddDelayData1_ps - kDelayAdjust;
type dataLaneHSType is array(kNoOfDataLanes-1 downto 0) of std_logic;
type dataLaneLPType is array(kNoOfDataLanes-1 downto 0) of std_logic_vector(1 downto 0);
type dataLaneWordType is array(kNoOfDataLanes-1 downto 0) of std_logic_vector(7 downto 0);
type dLP_int_t is array (kNoOfDataLanes-1 downto 0) of std_logic_vector(7 downto 0);
signal dLP0_in, dLP1_in, dLP0_out, dLP1_out : dLP_int_t;
signal HS_Clock : std_logic;
signal HS_Data : dataLaneHSType;
signal LP_Clock : std_logic_vector(1 downto 0);
signal aLPBuf, cLP_in, cLP_out : dataLaneLPType;
signal dDataWord : dataLaneWordType;
signal dDataAligned : dataLaneHSType;
signal RxDDRClkHS_int, RxByteClkHS_int, aRxClkActiveHS_int : std_logic;
signal cHSClkLocked : std_logic;
signal xEnable, xSoftRst : std_logic;
signal rDlyLckd, rDlyRst, rExtRst, rSoftRst, rSoftEnable, rIntRst : std_logic;
signal rDlyRstCnt : natural range 0 to kDlyRstDelay - 1 := kDlyRstDelay - 1;
signal aLaneSCNNEnable : std_logic;
signal aLaneSFENEnable : std_logic_vector(kNoOfDataLanes-1 downto 0);
type PPIRxLaneType is record
aStopstate : std_logic; --Lane is in Stop state
aEnable : std_logic; --Enable Lane Module
aUlpsActiveNot : std_logic; --ULP State (not) Active
rbRxDataHS : std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbRxValidHS : std_logic; --High-Speed Receive Data Valid
rbRxActiveHS : std_logic; --High-Speed Reception Active
rbRxSyncHS : std_logic; --Receiver Synchronization Observed (pulse)
rbErrSotHS : std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbErrSotSyncHS : std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aForceRxmode : std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
RxClkEsc : std_logic; --Escape mode Receive Clock (not periodic)
aRxDataEsc : std_logic_vector(7 downto 0); --Escape mode Receive Data
aRxValidEsc : std_logic; --Escape mode Receive Data Valid
aRxLpdtEsc : std_logic; --Escape Low-Power Data Receive Mode
aRxUlpsEsc : std_logic; --Escape Ultra-Low Power (Receive) mode
aRxTriggerEsc : std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aErrEsc : std_logic; --Escape Entry Error
aErrControl : std_logic; --Control Error
end record PPIRxLaneType;
type PPIRxType is array(kNoOfDataLanes-1 downto 0) of PPIRxLaneType;
signal SFEN_Lanes : PPIRxType;
signal debugSCNN : DebugSCNN_Type;
type DebugSFEN_Lanes_Type is array(kNoOfDataLanes-1 downto 0) of DebugSFEN_Type;
signal debugSFEN : DebugSFEN_Lanes_Type;
signal rTrigOut : std_logic;
signal rTrigInAck, rSFEN_TrigOut, rbSFEN_TrigOut, rbSFEN_TrigInAck, rSFEN_TrigInAck : std_logic_vector(kNoOfDataLanes-1 downto 0);
begin
-------------------------------------------------------------------------------
-- Map PPI ports to array type signals for easier module instantiation below
-------------------------------------------------------------------------------
PPIGen1: if kNoOfDataLanes >= 1 generate
aD0Stopstate <= SFEN_Lanes(0).aStopstate;
SFEN_Lanes(0).aEnable <= aD0Enable;
aD0UlpsActiveNot <= SFEN_Lanes(0).aUlpsActiveNot;
rbD0RxDataHS <= SFEN_Lanes(0).rbRxDataHS;
rbD0RxValidHS <= SFEN_Lanes(0).rbRxValidHS;
rbD0RxActiveHS <= SFEN_Lanes(0).rbRxActiveHS;
rbD0RxSyncHS <= SFEN_Lanes(0).rbRxSyncHS;
rbD0ErrSotHS <= SFEN_Lanes(0).rbErrSotHS;
rbD0ErrSotSyncHS <= SFEN_Lanes(0).rbErrSotSyncHS;
SFEN_Lanes(0).aForceRxmode <= aD0ForceRxmode;
D0RxClkEsc <= SFEN_Lanes(0).RxClkEsc;
aD0RxDataEsc <= SFEN_Lanes(0).aRxDataEsc;
aD0RxValidEsc <= SFEN_Lanes(0).aRxValidEsc;
aD0RxLpdtEsc <= SFEN_Lanes(0).aRxLpdtEsc;
aD0RxUlpsEsc <= SFEN_Lanes(0).aRxUlpsEsc;
aD0RxTriggerEsc <= SFEN_Lanes(0).aRxTriggerEsc;
aD0ErrEsc <= SFEN_Lanes(0).aErrEsc;
aD0ErrControl <= SFEN_Lanes(0).aErrControl;
end generate;
PPIGen2: if kNoOfDataLanes >= 2 generate
aD1Stopstate <= SFEN_Lanes(1).aStopstate;
SFEN_Lanes(1).aEnable <= aD1Enable;
aD1UlpsActiveNot <= SFEN_Lanes(1).aUlpsActiveNot;
rbD1RxDataHS <= SFEN_Lanes(1).rbRxDataHS;
rbD1RxValidHS <= SFEN_Lanes(1).rbRxValidHS;
rbD1RxActiveHS <= SFEN_Lanes(1).rbRxActiveHS;
rbD1RxSyncHS <= SFEN_Lanes(1).rbRxSyncHS;
rbD1ErrSotHS <= SFEN_Lanes(1).rbErrSotHS;
rbD1ErrSotSyncHS <= SFEN_Lanes(1).rbErrSotSyncHS;
SFEN_Lanes(1).aForceRxmode <= aD1ForceRxmode;
D1RxClkEsc <= SFEN_Lanes(1).RxClkEsc;
aD1RxDataEsc <= SFEN_Lanes(1).aRxDataEsc;
aD1RxValidEsc <= SFEN_Lanes(1).aRxValidEsc;
aD1RxLpdtEsc <= SFEN_Lanes(1).aRxLpdtEsc;
aD1RxUlpsEsc <= SFEN_Lanes(1).aRxUlpsEsc;
aD1RxTriggerEsc <= SFEN_Lanes(1).aRxTriggerEsc;
aD1ErrEsc <= SFEN_Lanes(1).aErrEsc;
aD1ErrControl <= SFEN_Lanes(1).aErrControl;
end generate;
-------------------------------------------------------------------------------
-- AXI-Lite interface for control and status
-------------------------------------------------------------------------------
YesAXILITE: if kGenerateAXIL generate
AXI_Lite_Control: entity work.MIPI_DPHY_Receiver_S_AXI_Lite
generic map (
kVersionMajor => kVersionMajor,
kVersionMinor => kVersionMinor,
C_S_AXI_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH
)
port map (
xEnable => xEnable,
xRst => xSoftRst,
S_AXI_ACLK => s_axi_lite_aclk,
S_AXI_ARESETN => s_axi_lite_aresetn,
S_AXI_AWADDR => s_axi_lite_awaddr,
S_AXI_AWPROT => s_axi_lite_awprot,
S_AXI_AWVALID => s_axi_lite_awvalid,
S_AXI_AWREADY => s_axi_lite_awready,
S_AXI_WDATA => s_axi_lite_wdata,
S_AXI_WSTRB => s_axi_lite_wstrb,
S_AXI_WVALID => s_axi_lite_wvalid,
S_AXI_WREADY => s_axi_lite_wready,
S_AXI_BRESP => s_axi_lite_bresp,
S_AXI_BVALID => s_axi_lite_bvalid,
S_AXI_BREADY => s_axi_lite_bready,
S_AXI_ARADDR => s_axi_lite_araddr,
S_AXI_ARPROT => s_axi_lite_arprot,
S_AXI_ARVALID => s_axi_lite_arvalid,
S_AXI_ARREADY => s_axi_lite_arready,
S_AXI_RDATA => s_axi_lite_rdata,
S_AXI_RRESP => s_axi_lite_rresp,
S_AXI_RVALID => s_axi_lite_rvalid,
S_AXI_RREADY => s_axi_lite_rready
);
CoreSoftReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => xSoftRst,
OutClk => RefClk,
oRst => rSoftRst);
SyncAsyncClkEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0', --lane-level enable
aIn => xEnable,
OutClk => RefClk,
oOut => rSoftEnable);
end generate;
NoAXILITE: if not kGenerateAXIL generate
rSoftEnable <= '1';
rSoftRst <= '0';
end generate;
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal rExtRst can be used as
-- asynchronous reset for any flip-flop in the RefClk domain, since it will be de-asserted
-- synchronously.
CoreAsyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => RefClk,
oRst => rExtRst);
rIntRst <= rSoftRst or rExtRst;
-------------------------------------------------------------------------------
-- IDELAYCTRL needed by the IDELAYE2 primitives on the data lanes
-------------------------------------------------------------------------------
GenIDELAYCTRL: if (kGenerateIDELAYCTRL) generate
--IDELAYCTRL must be reset after configuration or refclk lost for 52ns(K7), 72ns(A7) at least
ResetIDELAYCTRL: process(rIntRst, RefClk)
begin
if Rising_Edge(RefClk) then
if (rIntRst = '1') then
rDlyRstCnt <= kDlyRstDelay - 1;
rDlyRst <= '1';
elsif (rDlyRstCnt /= 0) then
rDlyRstCnt <= rDlyRstCnt - 1;
else
rDlyRst <= '0';
end if;
end if;
end process;
IDelayCtrlX: IDELAYCTRL
port map (
RDY => rDlyLckd,
REFCLK => RefClk,
RST => rDlyRst);
rDlyCtrlLockedOut <= rDlyLckd;
end generate GenIDELAYCTRL;
GenNoIDELAYCTRL: if (not kGenerateIDELAYCTRL) generate
rDlyLckd <= not rIntRst and rDlyCtrlLockedIn;
end generate GenNoIDELAYCTRL;
-------------------------------------------------------------------------------
-- Clock lane modules: enable, input buffer, D-PHY SCNN module
-------------------------------------------------------------------------------
aLaneSCNNEnable <= aClkEnable and rSoftEnable and rDlyLckd;
ClockInputBuffer: entity work.InputBuffer
Port map (
HS_p => dphy_clk_hs_p,
HS_n => dphy_clk_hs_n,
LP_n => dphy_clk_lp_n,
LP_p => dphy_clk_lp_p,
aHS => HS_Clock,
aLP => LP_Clock
);
ClockLane: entity work.DPHY_LaneSCNN
Generic map (
kGenerateMMCM => false,
kRefClkFreqHz => kRefClkFreqHz,
kAddDelay_ps => kAddAdjDelayClk_ps
)
Port map (
aLP => LP_Clock,
aHS => HS_Clock,
RefClk => RefClk,
RxDDRClkHS => RxDDRClkHS_int,
RxByteClkHS => RxByteClkHS_int,
aRxClkActiveHS => aRxClkActiveHS_int,
aForceRxmode => aClkForceRxmode,
aStopstate => aClkStopstate,
aEnable => aLaneSCNNEnable,
aRxUlpsClkNot => aRxUlpsClkNot,
aUlpsActiveNot => aClkUlpsActiveNot,
debug => debugSCNN
);
-------------------------------------------------------------------------------
-- Date lane modules: enable, input buffer, D-PHY SFEN module
-------------------------------------------------------------------------------
DataLaneGen: for i in kNoOfDataLanes-1 downto 0 generate
InputBufferDataX: entity work.InputBuffer
Generic map (
kNoLP => kLPFromLane0 and i /= 0
)
Port map (
HS_p => dphy_data_hs_p(i),
HS_n => dphy_data_hs_n(i),
LP_n => dphy_data_lp_n(i),
LP_p => dphy_data_lp_p(i),
aHS => HS_Data(i),
aLP => aLPBuf(i)
);
aLaneSFENEnable(i) <= SFEN_Lanes(i).aEnable and rSoftEnable and rDlyLckd;
DPHY_LaneSFEN_X: entity work.DPHY_LaneSFEN
Generic map (
kRefClkFreqHz => kRefClkFreqHz,
kAddDelay_ps => kAddAdjDelayData0_ps,
kNoLP => kLPFromLane0 and i /= 0
)
Port map (
dLP0_in => dLP0_in(i),
dLP1_in => dLP1_in(i),
dLP0_out => dLP0_out(i),
dLP1_out => dLP1_out(i),
cLP_in => cLP_in(i),
cLP_out => cLP_out(i),
aLP => aLPBuf(i),
aHS => HS_Data(i),
RefClk => RefClk,
SerClkHS => RxDDRClkHS_int,
DivClk => RxByteClkHS_int,
aRxClkActiveHS => aRxClkActiveHS_int,
--PPI
RxByteClkHS => open, --see RxByteClkHS_int below
rbRxDataHS => SFEN_Lanes(i).rbRxDataHS,
rbRxValidHS => SFEN_Lanes(i).rbRxValidHS,
rbRxActiveHS => SFEN_Lanes(i).rbRxActiveHS,
rbRxSyncHS => SFEN_Lanes(i).rbRxSyncHS,
rbErrSotHS => SFEN_Lanes(i).rbErrSotHS,
rbErrSotSyncHS => SFEN_Lanes(i).rbErrSotSyncHS,
aEnable => aLaneSFENEnable(i),
aStopstate => SFEN_Lanes(i).aStopstate,
aForceRxmode => SFEN_Lanes(i).aForceRxmode,
aErrEsc => SFEN_Lanes(i).aErrEsc,
aErrControl => SFEN_Lanes(i).aErrControl,
debug => debugSFEN(i)
);
ShareLPFromOtherLane: if kLPFromLane0 and i /= 0 generate
dLP0_in(i) <= dLP0_out(0);
dLP1_in(i) <= dLP0_out(0);
cLP_in(i) <= cLP_out(0);
end generate ShareLPFromOtherLane;
--D0RxClkEsc <=
--aD0RxDataEsc <=
--aD0RxValidEsc <=
--aD0RxLpdtEsc <=
--aD0RxUlpsEsc <=
--aD0RxTriggerEsc <=
end generate DataLaneGen;
-- We output a single divided clock common for all data lanes
RxByteClkHS <= RxByteClkHS_int;
RxDDRClkHS <= RxDDRClkHS_int;
aRxClkActiveHS <= aRxClkActiveHS_int;
----------------------------------------------------------------------------------
-- Debug modules
----------------------------------------------------------------------------------
GenerateDebug: if kDebug generate
ILA_SCNN_RefClkX : ila_scnn_refclk
PORT MAP (
clk => RefClk,
trig_out => rTrigOut,
trig_out_ack => rTrigInAck(0),
probe0(0) => debugSCNN.cIntRst,
probe1 => debugSCNN.cLP,
probe2(0) => debugSCNN.cHSRst,
probe3(0) => debugSCNN.cHSClkLocked,
probe4 => debugSCNN.state,
probe5(0) => debugSCNN.cClkSettleTout,
probe6(0) => debugSCNN.cBUFR_Rst,
probe7(0) => debugSCNN.cMMCM_Rst,
probe8(0) => debugSCNN.cMMCM_RstTout,
probe9(0) => debugSCNN.cMMCM_Locked
);
ILA_SFEN_Gen: for i in kNoOfDataLanes-1 downto 0 generate
ILA_SFEN_RefClkX : ila_sfen_refclk
PORT MAP (
clk => RefClk,
trig_out => rSFEN_TrigOut(i),
trig_out_ack => rSFEN_TrigInAck(i),
trig_in => rTrigOut,
trig_in_ack => rTrigInAck(i),
probe0(0) => debugSFEN(i).cIntRst,
probe1 => debugSFEN(i).cLP,
probe2 => debugSFEN(i).state,
probe3(0) => debugSFEN(i).cHSClkRst,
probe4(0) => debugSFEN(i).cForceRxmode,
probe5(0) => debugSFEN(i).cInitTout,
probe6(0) => debugSFEN(i).cHSSettleTout,
probe7(0) => debugSFEN(i).cHSSettled,
probe8(0) => debugSFEN(i).cHSReset
);
SyncAsyncTrigAck: entity work.SyncAsync
port map (
aReset => '0',
aIn => rbSFEN_TrigInAck(i),
OutClk => RefClk,
oOut => rSFEN_TrigInAck(i));
SyncAsyncTrigOut: entity work.SyncAsync
port map (
aReset => '0',
aIn => rSFEN_TrigOut(i),
OutClk => RxByteClkHS_int,
oOut => rbSFEN_TrigOut(i));
ILA_SFEN_RxClkX : ila_sfen_rxclk
PORT MAP (
clk => RxByteClkHS_int,
trig_in => rbSFEN_TrigOut(i),
trig_in_ack => rbSFEN_TrigInAck(i),
probe0(0) => debugSFEN(i).dSyncHard,
probe1(0) => debugSFEN(i).dSyncSoft,
probe2(0) => debugSFEN(i).dSyncErr,
probe3(0) => SFEN_Lanes(i).rbRxActiveHS,
probe4(0) => SFEN_Lanes(i).rbRxSyncHS,
probe5(0) => SFEN_Lanes(i).rbRxValidHS,
probe6(0) => SFEN_Lanes(i).rbErrSotHS,
probe7(0) => SFEN_Lanes(i).rbErrSotSyncHS,
probe8 => SFEN_Lanes(i).rbRxDataHS
);
end generate ILA_SFEN_Gen;
end generate;
end arch_imp;
|
mit
|
db037ec69d54b53c344fec6fd7dc061c
| 0.629085 | 3.805915 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
segment/segment.vhdl
| 1 | 1,446 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segment is
Port
(
clock : in std_logic;
segment_data : out std_logic_vector( 7 downto 0 )
);
end segment;
architecture Behavioral of segment is
signal number:std_logic_vector( 3 downto 0 ); -- decimal 0 to 15
signal count:std_logic_vector( 15 downto 0 );
begin
process( clock ) begin
if clock'event and clock = '1' then
count <= count + 1;
if count = 0 then
number <= number + 1;
end if;
end if;
end process;
segment_data <=
"01000000" when number = 0 else --0
"01111001" when number = 1 else --1
"00100100" when number = 2 else --2
"00110000" when number = 3 else --3
"00011001" when number = 4 else --4
"00010010" when number = 5 else --5
"00000010" when number = 6 else --6
"01111000" when number = 7 else --7
"00000000" when number = 8 else --8
"00010000" when number = 9 else --9
"00001000" when number = 10 else --A
"00000011" when number = 11 else --B
"01000110" when number = 12 else --C
"00100001" when number = 13 else --D
"00000110" when number = 14 else --E
"00001110"; --F
end Behavioral;
|
mit
|
3893a69d057e14d760f9afc522b1dbd3
| 0.632089 | 3.12311 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_strecud.vhd
| 1 | 2,151 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_strecud_DSP48_1 is
port (
in0: in std_logic_vector(8 - 1 downto 0);
in1: in std_logic_vector(20 - 1 downto 0);
in2: in std_logic_vector(29 - 1 downto 0);
dout: out std_logic_vector(29 - 1 downto 0));
end entity;
architecture behav of hls_contrast_strecud_DSP48_1 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(unsigned(in1), 25));
b <= signed(resize(unsigned(in0), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 29));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_strecud is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_strecud is
component hls_contrast_strecud_DSP48_1 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_strecud_DSP48_1_U : component hls_contrast_strecud_DSP48_1
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
mit
|
e017ed0289686aa11bd7ece614e21bcb
| 0.570432 | 3.360938 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/fadd-grafi/fadd/u232c_send.vhd
| 1 | 1,225 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity U232C_SEND is
generic (
WTIME : std_logic_vector(15 downto 0) := x"1ADB");
port (
CLK : in std_logic;
GO : in std_logic;
DATA : in std_logic_vector (7 downto 0);
TX : out std_logic;
SENT : out std_logic);
end U232C_SEND;
architecture blackbox of U232C_SEND is
signal countdown : std_logic_vector(15 downto 0) := WTIME;
signal sendbuf : std_logic_vector(8 downto 0) := (others => '1');
signal state : integer range 0 to 10 := 10;
signal sig_sent : std_logic := '1';
begin
SENT <= sig_sent;
TX <= sendbuf(0);
statemachine : process(CLK)
begin
if rising_edge(CLK) then
case state is
when 10 =>
if GO = '1' then
sendbuf <= DATA&"0";
sig_sent <= '0';
countdown <= WTIME;
state <= state-1;
end if;
when 0 =>
if countdown = 0 then
sig_sent <= '1';
state <= 10;
else
countdown <= countdown-1;
end if;
when others =>
if countdown = 0 then
sendbuf <= "1"&sendbuf(8 downto 1);
countdown <= WTIME;
state <= state-1;
else
countdown <= countdown-1;
end if;
end case;
end if;
end process;
end blackbox;
|
bsd-2-clause
|
83001d6ff61659c16c0279f88d1d4ce4
| 0.595918 | 2.902844 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/DPHY_LaneSCNN.vhd
| 1 | 9,673 |
-------------------------------------------------------------------------------
--
-- File: DPHY_LaneSCNN.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements a MIPI D-PHY 1.0 CIL-SCNN lane: slave (receiver) clock.
-- It is architecture-independent by itself, but the instantiated HS-Clocking has
-- its own requirements. The D-PHY physical interface is assumed to be de-multiplexed
-- into low-power LP(1:0) and high-speed HS inputs by external circuitry (outside
-- the FPGA). On the logic side data is forwarded via the PPI interface as
-- described in the D-PHY spec Annex A.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
use work.DebugLib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DPHY_LaneSCNN is
Generic (
kGenerateMMCM : boolean := false;
kRefClkFreqHz : natural := 200_000_000;
kAddDelay_ps : integer := 0
);
Port (
aLP : in STD_LOGIC_VECTOR (1 downto 0);
aHS : in STD_LOGIC;
RefClk : in STD_LOGIC; --200MHz
RxDDRClkHS : out STD_LOGIC;
RxByteClkHS : out STD_LOGIC;
aRxClkActiveHS : out STD_LOGIC;
aForceRxmode : in STD_LOGIC;
aStopstate : out STD_LOGIC;
aEnable : in STD_LOGIC;
aRxUlpsClkNot : out std_logic; --Receive Ultra-Low Power State on Clock Lane.
aUlpsActiveNot : out std_logic; --ULP State (not) Active.
debug : out DebugSCNN_Type
);
end DPHY_LaneSCNN;
architecture Behavioral of DPHY_LaneSCNN is
function MAX(LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end;
type state_type is (stInit, stStop, stHS_Prpr, stHS_Term, stHS_Clk, stHS_End, stULPS, stULPS_Exit, stULPS_Rqst);
signal state, nstate : state_type := stInit;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one_hot";
signal cLP, cLPGlitch : std_logic_vector(1 downto 0);
signal cIntRst : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of cLP: signal is "TRUE";
alias CtlClk : std_logic is RefClk;
alias kCtlClkFreqHz : natural is kRefClkFreqHz;
constant kTInit : natural := natural(ceil(100.0 / 10.0**6 * real(kCtlClkFreqHz))); --100us
constant kTClkTermEn : natural := natural(ceil(38.0 / 10.0**9 * real(kCtlClkFreqHz))); --38ns
constant kTClkSettle : natural := natural(ceil(95.0 / 10.0**9 * real(kCtlClkFreqHz))); --95ns min
constant kTMinRx : natural := natural(ceil(20.0 / 10.0**9 * real(kCtlClkFreqHz))); --20ns
signal cClkSettleTout : std_logic;
signal cDelayCnt : natural range 0 to MAX(kTInit,MAX(kTClkTermEn, kTClkSettle)) := 0;
signal aClkLocked, cClkLocked, cHSRst, cDelayCntEn, aHSClkLocked, cHSClkLocked, cHSClkLocked_q, cHSClkLost : std_logic;
signal cEnable : std_logic;
begin
debug.cIntRst <= cIntRst;
debug.cLP <= cLP;
debug.cHSRst <= cHSRst;
debug.cHSClkLocked <= cHSClkLocked;
debug.state <= std_logic_vector(to_unsigned(state_type'pos(state), 4));
debug.cClkSettleTout <= cClkSettleTout;
SyncAsyncEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => aEnable,
OutClk => CtlClk,
oOut => cEnable);
cIntRst <= not cEnable;
aStopstate <= '1' when state = stStop else
'0';
aRxUlpsClkNot <= '0' when state = stULPS or state = stULPS_Exit else
'1';
aUlpsActiveNot <= '0' when state = stULPS else
'1';
aRxClkActiveHS <= aHSClkLocked;
-------------------------------------------------------------------------------
-- Synchronize LP signals into the CtlClk domain, then filter glitches
-------------------------------------------------------------------------------
GenSyncLP: for i in 0 to 1 generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => aLP(i),
OutClk => CtlClk,
oOut => cLPGlitch(i));
--TODO: LP 0 not in sync with LP 1; OK? because on HS-entry LPs don't change
-- simultaneously, only on HS-exit, where they both rise to 1 together.
-- On HS-exit only the "11" condition is used, so this skew at most delays exit.
GlitchFilterLP: entity work.GlitchFilter
generic map (
kNoOfPeriodsToFilter => kTMinRx)
port map (
SampleClk => CtlClk,
sIn => cLPGlitch(i),
sOut => cLP(i),
sRst => cIntRst);
end generate GenSyncLP;
DelayCounter: process(CtlClk)
begin
if Rising_Edge(CtlClk) then
if (cDelayCntEn = '0') then
cDelayCnt <= 0;
elsif (cDelayCntEn = '1') then
cDelayCnt <= cDelayCnt + 1;
end if;
end if;
end process DelayCounter;
cClkSettleTout <= '1' when cDelayCnt = kTClkSettle-1
else '0';
--Outputs
cDelayCntEn <= '1' when state = stHS_Term else
'0';
ModeFSM_SyncProc: process (CtlClk)
begin
if Rising_Edge(CtlClk) then
if (cIntRst = '1') then
state <= stInit;
else
state <= nstate;
end if;
end if;
end process;
cHSRst <= '0' when state = stHS_Clk and cIntRst = '0' else
'1';
ModeFSM_NextStateProc: process (state, cLP, cClkSettleTout, cClkLocked, cHSClkLost)
begin
nstate <= state;
case (state) is
when stInit =>
if cLP = "11" then
nstate <= stStop;
end if;
when stStop =>
if cLP = "01" then -- HS-Rqst
nstate <= stHS_Prpr;
elsif cLP = "10" then -- ULPS-Rqst
nstate <= stULPS_Rqst;
end if;
when stULPS_Rqst =>
if (cLP = "11" or cLP = "01") then
nstate <= stStop;
elsif (cLP = "00") then
nstate <= stULPS;
end if;
when stULPS =>
if (cLP = "10") then
nstate <= stULPS_Exit;
end if;
when stULPS_Exit =>
if (cLP = "11") then
nstate <= stStop;
end if;
when stHS_Prpr =>
if (cLP = "11") then
nstate <= stStop;
elsif cLP = "00" then -- Bridge
nstate <= stHS_Term;
end if;
when stHS_Term =>
if (cLP = "11") then
nstate <= stStop;
elsif (cLP = "00" and cClkSettleTout = '1') then -- Bridge
nstate <= stHS_Clk;
end if;
when stHS_Clk =>
if (cHSClkLost = '1') then --Clock lost
nstate <= stHS_End;
elsif (cLP = "11") then -- Stop, we might not have seen the loss of clock
nstate <= stStop;
end if;
when stHS_End =>
if (cLP = "11") then -- Stop
nstate <= stStop;
end if;
end case;
end process;
HSClockingX: entity work.HS_Clocking
Generic map (
kGenerateMMCM => kGenerateMMCM,
kCtlClkFreqHz => kCtlClkFreqHz,
kRefClkFreqHz => kRefClkFreqHz,
kAddDelay_ps => kAddDelay_ps
)
Port map (
HS_Clock => aHS,
HS_SerClk => RxDDRClkHS,
HS_Div4Clk => RxByteClkHS,
CtlClk => CtlClk,
cRst => cHSRst,
aLocked => aHSClkLocked,
dbg_cBUFR_Rst => debug.cBUFR_Rst,
dbg_cMMCM_Rst => debug.cMMCM_Rst,
dbg_cMMCM_RstTout => debug.cMMCM_RstTout,
dbg_cMMCM_Locked => debug.cMMCM_Locked
);
SyncAsyncLocked: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => cHSRst,
aIn => aHSClkLocked,
OutClk => CtlClk,
oOut => cHSClkLocked);
process(CtlClk)
begin
if Rising_Edge(CtlClk) then
cHSClkLocked_q <= cHSClkLocked;
end if;
end process;
cHSClkLost <= cHSClkLocked_q and not cHSClkLocked;
end Behavioral;
|
mit
|
265be489a8a948a5045c6dcad25d71eb
| 0.5902 | 4.171194 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/HandshakeData.vhd
| 2 | 6,814 |
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 18 December 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module passes parallel data from the input clock domain (InClk) to the
-- output clock domain (OutClk) by the means of handshake signals. A
-- low-to-high transition on iPush will register iData inside the module
-- and will start propagating the handshake signals towards the output domain.
-- The data will appear on oData and is valid when oValid pulses high.
-- The reception of data by the receiver on the OutClk domain is signaled
-- by a pulse on oAck. This will propagate back to the input domain and
-- assert iRdy signaling to the sender that a new data can be pushed though.
-- If oData is always read when oValid pulses, oAck may be tied permanently
-- high.
-- Only assert iPush when iRdy is high!
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aReset : in std_logic);
end HandshakeData;
architecture Behavioral of HandshakeData is
signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of aReset: signal is "TRUE";
begin
DetectPush: process(aReset, InClk)
begin
if (aReset = '1') then
iPush_q <= '0';
elsif Rising_Edge(InClk) then
iPush_q <= iPush;
end if;
end process DetectPush;
iPushRising <= iPush and not iPush_q;
-- Register data when iPush is rising and toggle internal flag
LatchData: process(aReset, InClk)
begin
if (aReset = '1') then
iData_int <= (others => '0');
iPushT <= '0';
elsif Rising_Edge(InClk) then
if (iPushRising = '1') then
iData_int <= iData;
iPushT <= not iPushT;
end if;
end if;
end process;
-- Cross toggle flag through synchronizer
SyncAsyncPushT: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => iPushT,
OutClk => OutClk,
oOut => oPushT);
-- Detect a push edge in the OutClk domain
-- If receiver acknowledges receipt, we can propagate the push signal back
-- towards the input, where it will be used to generate iRdy
DetectToggle: process(aReset, OutClk)
begin
if (aReset = '1') then
oPushT_q <= '0';
oPushTBack <= '0';
elsif Rising_Edge(OutClk) then
oPushT_q <= oPushT;
if (oAck = '1') then
oPushTBack <= oPushT_q;
end if;
end if;
end process DetectToggle;
oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
-- Cross data from InClk domain reg (iData_in) to OutClk domain
-- The enable for this register is the propagated and sync'd to the OutClk domain
-- We assume here that the time it took iPush to propagate to oPushTChanged is
-- more than the time it takes iData_int to propagate to the oData register's D pin
OutputData: process (aReset, OutClk)
begin
if (aReset = '1') then
oData <= (others => '0');
oValid <= '0';
elsif Rising_Edge(OutClk) then
if (oPushTChanged = '1') then
oData <= iData_int;
oValid <= '1';
end if;
end if;
end process OutputData;
-- Cross toggle flag back through synchronizer
SyncAsyncPushTBack: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => oPushTBack,
OutClk => InClk,
oOut => iPushTBack);
-- Synchronize aReset into the InClk domain
-- We need it to keep iRdy low, when aReset de-asserts
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aReset,
OutClk => InClk,
oRst => iReset);
ReadySignal: process(aReset, InClk)
begin
if (aReset = '1') then
iRdy <= '0';
elsif Rising_Edge(InClk) then
iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
end if;
end process ReadySignal;
end Behavioral;
|
mit
|
b7eb2c55abb17b0c6d4bb76cdb62f459
| 0.657323 | 4.329098 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/tb_divisorfrec.vhd
| 1 | 1,396 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_divisorfrec IS
END tb_divisorfrec;
ARCHITECTURE behavior OF tb_divisorfrec IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT divisorfrec
PORT(
clk : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal salida : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: divisorfrec PORT MAP (
clk => clk,
reset => reset,
salida => salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait for 50 ns; --FUNCIONA PERO LA SIMULACION NO SE MANTIENE
reset <= '1'; --EL TIEMPO NECESARIO. CAMBIAR FRECUENCIA DEL
wait for 95 ns; --DIVISOR PARA COMPROBAR.
reset <= '0';
wait for 110 ns;
reset <= '1';
wait for 25 ns;
reset <= '0';
wait;
end process;
END;
|
gpl-3.0
|
1b1aaffe53e2b49e78e7462c164b8f8e
| 0.596705 | 3.516373 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/FFlr.vhd
| 1 | 1,567 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FFlr is
port (
clk : in std_logic;
f : in std_logic_vector(31 downto 0);
g : out std_logic_vector(31 downto 0) := (others => '0'));
end FFlr;
architecture dataflow of FFlr is
signal len_raw : unsigned(8 downto 0);
signal len : unsigned(4 downto 0);
signal x_mask, incr : unsigned(30 downto 0);
signal f_masked, f_incr : unsigned(30 downto 0);
signal f_out : unsigned(30 downto 0);
signal res : unsigned(31 downto 0);
signal g_pipe : std_logic_vector(31 downto 0) := (others => '0');
begin
len_raw <= unsigned('0' & f(30 downto 23)) - "001111111";
len <= "00000" when len_raw(8) = '1' else
"11111" when len_raw(7 downto 5) /= "000" else
len_raw(4 downto 0);
x_mask <= shift_right("000" & x"07FFFFF", to_integer(len));
incr <= (x_mask(29 downto 0) & '1') xor x_mask;
f_masked <= unsigned(f(30 downto 0)) and not x_mask;
f_incr <= f_masked + incr;
f_out <= f_masked when f(31) = '0' or unsigned(f(30 downto 0)) = f_masked else
f_incr;
res <= f(31) & "00000000" & f_out(22 downto 0) when (f(31) = '0' or f(30 downto 23) = "00000000") and len_raw(8) = '1' else
f(31) & "01111111" & f_out(22 downto 0) when f(31) = '1' and len_raw(8) = '1' else
f(31) & f_out;
pipe : process(clk)
begin
if rising_edge(clk) then
g_pipe <= std_logic_vector(res);
g <= g_pipe;
end if;
end process;
end dataflow;
|
bsd-2-clause
|
1636b1d92b2da152f1afcdb4b51eee2f
| 0.566688 | 3.013462 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
IF_ID_Register.vhd
| 1 | 1,548 |
-------------------------------------------------------------------------------
--
-- Title : IF_ID_Register
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\IF_ID_Register.vhd
-- Generated : Wed Dec 7 14:30:02 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {IF_ID_Register} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity IF_ID_Register is
port (
instruction_in : in std_logic_vector(15 downto 0);
clk : in std_logic;
instruction_out : out std_logic_vector(15 downto 0)
);
end IF_ID_Register;
architecture behavioral of IF_ID_Register is
begin
process(clk)
variable instruction_in_reg : std_logic_vector(15 downto 0) := "0000000000000000";
variable instruction_out_reg : std_logic_vector(15 downto 0) := "0000000000000000";
begin
if rising_edge(clk) then
instruction_out_reg := instruction_in_reg;
instruction_in_reg := instruction_in;
end if;
instruction_out <= instruction_out_reg;
end process;
end behavioral;
|
apache-2.0
|
4683482e5a61cd4016b5deae4d65fb9e
| 0.510982 | 4 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/crc5.vhd
| 2 | 2,174 |
-- Copyright (C) 2009 OutputLogic.com
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-------------------------------------------------------------------------------
-- CRC module for data(7:0)
-- lfsr(4:0)=1+x^2+x^5;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity crc5 is
port ( data_in : in std_logic_vector (10 downto 0);
-- crc_en , rst, clk : in std_logic;
crc_out : out std_logic_vector (4 downto 0));
end crc5;
architecture imp_crc5 of crc5 is
signal lfsr_q: std_logic_vector (4 downto 0);
signal lfsr_c: std_logic_vector (4 downto 0);
signal crc_out_buf: std_logic_vector (4 downto 0);
begin
crc_out_buf <= lfsr_c;
crc_out(4) <= not crc_out_buf(0);
crc_out(3) <= not crc_out_buf(1);
crc_out(2) <= not crc_out_buf(2);
crc_out(1) <= not crc_out_buf(3);
crc_out(0) <= not crc_out_buf(4);
lfsr_q <= b"11111";
lfsr_c(0) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(4) xor data_in(0) xor data_in(3) xor data_in(5) xor data_in(6) xor data_in(9) xor data_in(10);
lfsr_c(1) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(4) xor data_in(1) xor data_in(4) xor data_in(6) xor data_in(7) xor data_in(10);
lfsr_c(2) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(4) xor data_in(0) xor data_in(2) xor data_in(3) xor data_in(6) xor data_in(7) xor data_in(8) xor data_in(9) xor data_in(10);
lfsr_c(3) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(4) xor data_in(1) xor data_in(3) xor data_in(4) xor data_in(7) xor data_in(8) xor data_in(9) xor data_in(10);
lfsr_c(4) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(4) xor data_in(2) xor data_in(4) xor data_in(5) xor data_in(8) xor data_in(9) xor data_in(10);
end imp_crc5;
|
mit
|
63902e1eb591d0a8233a2b4ccfac0a15
| 0.609476 | 2.816062 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/mux2t1.vhd
| 1 | 1,534 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:26:54 07/12/05
-- Design Name:
-- Module Name: mux2t1 - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux2t1 is
Port
(
-- G1_adder_shift : in std_logic_vector(8 downto 0);
-- G2_adder_shift : in std_logic_vector(8 downto 0);
-- sele : in std_logic;
-- G_bar : out std_logic_vector(8 downto 0)
In1 : in std_logic;
In2 : in std_logic;
sel : in std_logic;
Output : out std_logic
);
end mux2t1;
architecture Behavioral of mux2t1 is
begin
-- process(G1_adder_shift, G2_adder_shift, sele)
-- begin
-- if (sele = '0') then
-- G_bar <= G1_adder_shift;
-- elsif (sele = '1') then
-- G_bar <= G2_adder_shift;
-- end if;
-- end process;
process( In1, In2, sel )
begin
if ( sel = '0' ) then
Output <= In1;
elsif (sel = '1') then
Output <= In2;
end if;
end process;
end Behavioral;
|
mit
|
c667fec12b905ae8cc0ca5fb8ba9bcac
| 0.532595 | 3.007843 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/clk.vhd
| 2 | 803 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk200Hz is
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end clk200Hz;
architecture Behavioral of clk200Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 124999 := 0;
begin
divisor_frecuencia: process (reset, entrada) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = 124999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;
salida <= temporal;
end Behavioral;
|
gpl-2.0
|
18d8cf9a625890af87df55848e2f3f23
| 0.526775 | 4.271277 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/fifo_w16_d4_A.vhd
| 2 | 4,437 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w16_d4_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w16_d4_A_shiftReg;
architecture rtl of fifo_w16_d4_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w16_d4_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w16_d4_A is
component fifo_w16_d4_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w16_d4_A_shiftReg : fifo_w16_d4_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
d188d6ab5b0e85ba0427b9056935a59b
| 0.52558 | 3.4637 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/SimpleFIFO.vhd
| 1 | 4,376 |
-------------------------------------------------------------------------------
--
-- File: SimpleFIFO.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SimpleFIFO is
Generic (
kDataWidth : natural
);
Port (
InClk : in std_logic;
iRst : in std_logic;
iDataIn : in std_logic_vector(kDataWidth-1 downto 0);
iWrEn : in std_logic;
iRdEn : in std_logic;
iFull : out std_logic;
iEmpty : out std_logic;
iDataOut : out std_logic_vector(kDataWidth-1 downto 0)
);
end SimpleFIFO;
architecture Behavioral of SimpleFIFO is
constant kFIFO_Depth : natural := 2**5; --implementation assumes power of 2
subtype FIFO_data_t is std_logic_vector(kDataWidth-1 downto 0);
type FIFO_t is array (0 to kFIFO_Depth-1) of FIFO_data_t;
signal FIFO : FIFO_t;
signal iRdA, iWrA : natural range 0 to kFIFO_Depth-1; --read and write addresses
signal iFullInt, iEmptyInt : std_logic := '1';
begin
-- The process below should result in a dual-port distributed RAM
FIFOProc: process (InClk)
begin
if Rising_Edge(InClk) then
if (iWrEn = '1') then
FIFO(iWrA) <= iDataIn;
end if;
end if;
end process FIFOProc;
iDataOut <= FIFO(iRdA);
-- FIFO address counters
FIFO_WrA: process (InClk)
begin
if Rising_Edge(InClk) then
if (iRst = '1') then
iWrA <= 0;
elsif (iFullInt = '0' or iWrEn = '1') then
if (iWrA = kFIFO_Depth - 1) then
iWrA <= 0;
else
iWrA <= iWrA + 1;
end if;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (InClk)
begin
if Rising_Edge(InClk) then
if (iRst = '1') then
iRdA <= 0;
elsif (iRdEn = '1' and iEmptyInt = '0') then
if (iRdA = kFIFO_Depth - 1) then
iRdA <= 0;
else
iRdA <= iRdA + 1;
end if;
end if;
end if;
end process FIFO_RdA;
FullFlag: process (InClk)
begin
if Rising_Edge(InClk) then
if (iRst = '1') then
iFullInt <= '1';
elsif (iEmptyInt = '1') then
iFullInt <= '0';
elsif (iFullInt = '1' and iRdEn = '1') then
iFullInt <= '0';
elsif (((iWrA + 1) mod kFIFO_Depth = iRdA) and iWrEn = '1' and iRdEn = '0') then
iFullInt <= '1';
end if;
end if;
end process;
EmptyFlag: process (InClk)
begin
if Rising_Edge(InClk) then
if (iRst = '1') then
iEmptyInt <= '1';
elsif (iWrEn = '1') then
iEmptyInt <= '0';
elsif (((iRdA + 1) mod kFIFO_Depth = iWrA) and iRdEn = '1' and iWrEn = '0') then
iEmptyInt <= '1';
end if;
end if;
end process;
iFull <= iFullInt;
iEmpty <= iEmptyInt;
end Behavioral;
|
mit
|
1594d032a824e1bae84be29f8d4cc188
| 0.608318 | 3.869142 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_eneOg.vhd
| 1 | 1,686 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_eneOg_DSP48_1 is
port (
a: in std_logic_vector(20 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(28 - 1 downto 0));
end entity;
architecture behav of hls_saturation_eneOg_DSP48_1 is
signal a_cvt: unsigned(20 - 1 downto 0);
signal b_cvt: unsigned(8 - 1 downto 0);
signal p_cvt: unsigned(28 - 1 downto 0);
attribute keep : string;
attribute keep of a_cvt : signal is "true";
attribute keep of b_cvt : signal is "true";
attribute keep of p_cvt : signal is "true";
begin
a_cvt <= unsigned(a);
b_cvt <= unsigned(b);
p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 28));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_eneOg is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_eneOg is
component hls_saturation_eneOg_DSP48_1 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_saturation_eneOg_DSP48_1_U : component hls_saturation_eneOg_DSP48_1
port map (
a => din0,
b => din1,
p => dout);
end architecture;
|
mit
|
2dccc05a37521f739bf560fca5c9694f
| 0.616845 | 3.305882 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_strefYi.vhd
| 1 | 8,653 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hls_contrast_strefYi_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
sign_i : in STD_LOGIC_VECTOR(1 downto 0);
sign_o : out STD_LOGIC_VECTOR(1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
function max (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end max;
end entity;
architecture rtl of hls_contrast_strefYi_div_u is
constant cal_WIDTH : INTEGER := max(in0_WIDTH, in1_WIDTH);
type in0_vector is array(INTEGER range <>) of UNSIGNED(in0_WIDTH-1 downto 0);
type in1_vector is array(INTEGER range <>) of UNSIGNED(in1_WIDTH-1 downto 0);
type cal_vector is array(INTEGER range <>) of UNSIGNED(cal_WIDTH downto 0);
type sign_vector is array(INTEGER range <>) of UNSIGNED(1 downto 0);
signal dividend_tmp : in0_vector(0 to in0_WIDTH);
signal divisor_tmp : in1_vector(0 to in0_WIDTH);
signal remd_tmp : in0_vector(0 to in0_WIDTH);
signal comb_tmp : in0_vector(0 to in0_WIDTH-1);
signal cal_tmp : cal_vector(0 to in0_WIDTH-1);
signal sign_tmp : sign_vector(0 to in0_WIDTH);
begin
quot <= STD_LOGIC_VECTOR(RESIZE(dividend_tmp(in0_WIDTH), out_WIDTH));
remd <= STD_LOGIC_VECTOR(RESIZE(remd_tmp(in0_WIDTH), out_WIDTH));
sign_o <= STD_LOGIC_VECTOR(sign_tmp(in0_WIDTH));
tran_tmp_proc : process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(0) <= UNSIGNED(dividend);
divisor_tmp(0) <= UNSIGNED(divisor);
sign_tmp(0) <= UNSIGNED(sign_i);
remd_tmp(0) <= (others => '0');
end if;
end if;
end process tran_tmp_proc;
run_proc: for i in 0 to in0_WIDTH-1 generate
begin
comb_tmp(i) <= remd_tmp(i)(in0_WIDTH-2 downto 0) & dividend_tmp(i)(in0_WIDTH-1);
cal_tmp(i) <= ('0' & comb_tmp(i)) - ('0' & divisor_tmp(i));
process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(i+1) <= dividend_tmp(i)(in0_WIDTH-2 downto 0) & (not cal_tmp(i)(cal_WIDTH));
divisor_tmp(i+1) <= divisor_tmp(i);
sign_tmp(i+1) <= sign_tmp(i);
if cal_tmp(i)(cal_WIDTH) = '1' then
remd_tmp(i+1) <= comb_tmp(i);
else
remd_tmp(i+1) <= cal_tmp(i)(in0_WIDTH-1 downto 0);
end if;
end if;
end if;
end process;
end generate run_proc;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hls_contrast_strefYi_div is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end entity;
architecture rtl of hls_contrast_strefYi_div is
component hls_contrast_strefYi_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
sign_i : in STD_LOGIC_VECTOR(1 downto 0);
sign_o : out STD_LOGIC_VECTOR(1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end component;
signal dividend0 : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor0 : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal dividend_u : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor_u : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal quot_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal remd_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal sign_i : STD_LOGIC_VECTOR(1 downto 0);
signal sign_o : STD_LOGIC_VECTOR(1 downto 0);
begin
hls_contrast_strefYi_div_u_0 : hls_contrast_strefYi_div_u
generic map(
in0_WIDTH => in0_WIDTH,
in1_WIDTH => in1_WIDTH,
out_WIDTH => out_WIDTH)
port map(
clk => clk,
reset => reset,
ce => ce,
dividend => dividend_u,
divisor => divisor_u,
sign_i => sign_i,
sign_o => sign_o,
quot => quot_u,
remd => remd_u);
sign_i <= (dividend0(in0_WIDTH-1) xor divisor0(in1_WIDTH-1)) & dividend0(in0_WIDTH-1);
dividend_u <= STD_LOGIC_VECTOR(UNSIGNED(not dividend0) + 1) when dividend0(in0_WIDTH-1) = '1' else dividend0;
divisor_u <= STD_LOGIC_VECTOR(UNSIGNED(not divisor0) + 1) when divisor0(in1_WIDTH-1) = '1' else divisor0;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
dividend0 <= dividend;
divisor0 <= divisor;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
if (sign_o(1) = '1') then
quot <= STD_LOGIC_VECTOR(UNSIGNED(not quot_u) + 1);
else
quot <= quot_u;
end if;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
if (sign_o(0) = '1') then
remd <= STD_LOGIC_VECTOR(UNSIGNED(not remd_u) + 1);
else
remd <= remd_u;
end if;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_strefYi is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_strefYi is
component hls_contrast_strefYi_div is
generic (
in0_WIDTH : INTEGER;
in1_WIDTH : INTEGER;
out_WIDTH : INTEGER);
port (
dividend : IN STD_LOGIC_VECTOR;
divisor : IN STD_LOGIC_VECTOR;
quot : OUT STD_LOGIC_VECTOR;
remd : OUT STD_LOGIC_VECTOR;
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
reset : IN STD_LOGIC);
end component;
signal sig_quot : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
signal sig_remd : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
begin
hls_contrast_strefYi_div_U : component hls_contrast_strefYi_div
generic map (
in0_WIDTH => din0_WIDTH,
in1_WIDTH => din1_WIDTH,
out_WIDTH => dout_WIDTH)
port map (
dividend => din0,
divisor => din1,
quot => dout,
remd => sig_remd,
clk => clk,
ce => ce,
reset => reset);
end architecture;
|
mit
|
29f8f5d328d4ee27bcd4996f5399e2a8
| 0.528256 | 3.482093 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_jbC.vhd
| 1 | 6,941 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_jbC_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_jbC_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000010", 2 => "00000011", 3 => "00000101",
4 => "00000110", 5 => "00001000", 6 => "00001010", 7 => "00001011",
8 => "00001101", 9 => "00001110", 10 => "00010000", 11 => "00010001",
12 => "00010011", 13 => "00010100", 14 => "00010110", 15 => "00010111",
16 => "00011001", 17 => "00011011", 18 => "00011100", 19 => "00011110",
20 => "00011111", 21 => "00100001", 22 => "00100010", 23 => "00100100",
24 => "00100101", 25 => "00100111", 26 => "00101000", 27 => "00101001",
28 => "00101011", 29 => "00101100", 30 => "00101110", 31 => "00101111",
32 => "00110001", 33 => "00110010", 34 => "00110100", 35 => "00110101",
36 => "00110111", 37 => "00111000", 38 => "00111001", 39 => "00111011",
40 => "00111100", 41 => "00111110", 42 => "00111111", 43 => "01000000",
44 => "01000010", 45 => "01000011", 46 => "01000101", 47 => "01000110",
48 => "01000111", 49 => "01001001", 50 => "01001010", 51 => "01001011",
52 => "01001101", 53 => "01001110", 54 => "01010000", 55 => "01010001",
56 => "01010010", 57 => "01010100", 58 => "01010101", 59 => "01010110",
60 => "01011000", 61 => "01011001", 62 => "01011010", 63 => "01011011",
64 => "01011101", 65 => "01011110", 66 => "01011111", 67 => "01100001",
68 => "01100010", 69 => "01100011", 70 => "01100100", 71 => "01100110",
72 => "01100111", 73 => "01101000", 74 => "01101010", 75 => "01101011",
76 => "01101100", 77 => "01101101", 78 => "01101110", 79 => "01110000",
80 => "01110001", 81 => "01110010", 82 => "01110011", 83 => "01110101",
84 => "01110110", 85 => "01110111", 86 => "01111000", 87 => "01111001",
88 => "01111011", 89 => "01111100", 90 => "01111101", 91 => "01111110",
92 => "01111111", 93 => "10000000", 94 => "10000010", 95 => "10000011",
96 => "10000100", 97 => "10000101", 98 => "10000110", 99 => "10000111",
100 => "10001000", 101 => "10001010", 102 => "10001011", 103 => "10001100",
104 => "10001101", 105 => "10001110", 106 => "10001111", 107 => "10010000",
108 => "10010001", 109 => "10010010", 110 => "10010100", 111 => "10010101",
112 => "10010110", 113 => "10010111", 114 => "10011000", 115 => "10011001",
116 => "10011010", 117 => "10011011", 118 => "10011100", 119 => "10011101",
120 => "10011110", 121 => "10011111", 122 => "10100000", 123 => "10100001",
124 => "10100010", 125 => "10100011", 126 => "10100100", 127 => "10100101",
128 => "10100110", 129 => "10100111", 130 => "10101000", 131 => "10101001",
132 => "10101010", 133 => "10101011", 134 => "10101100", 135 => "10101101",
136 => "10101110", 137 => "10101111", 138 => "10110000", 139 => "10110001",
140 => "10110010", 141 => "10110011", 142 => "10110100", 143 => "10110101",
144 => "10110110", 145 to 146=> "10110111", 147 => "10111000", 148 => "10111001",
149 => "10111010", 150 => "10111011", 151 => "10111100", 152 => "10111101",
153 => "10111110", 154 to 155=> "10111111", 156 => "11000000", 157 => "11000001",
158 => "11000010", 159 => "11000011", 160 => "11000100", 161 to 162=> "11000101",
163 => "11000110", 164 => "11000111", 165 => "11001000", 166 => "11001001",
167 to 168=> "11001010", 169 => "11001011", 170 => "11001100", 171 => "11001101",
172 to 173=> "11001110", 174 => "11001111", 175 => "11010000", 176 to 177=> "11010001",
178 => "11010010", 179 => "11010011", 180 => "11010100", 181 to 182=> "11010101",
183 => "11010110", 184 to 185=> "11010111", 186 => "11011000", 187 => "11011001",
188 to 189=> "11011010", 190 => "11011011", 191 to 192=> "11011100", 193 => "11011101",
194 => "11011110", 195 to 196=> "11011111", 197 => "11100000", 198 to 199=> "11100001",
200 => "11100010", 201 to 202=> "11100011", 203 to 204=> "11100100", 205 => "11100101",
206 to 207=> "11100110", 208 => "11100111", 209 to 210=> "11101000", 211 to 212=> "11101001",
213 => "11101010", 214 to 215=> "11101011", 216 to 217=> "11101100", 218 => "11101101",
219 to 220=> "11101110", 221 to 222=> "11101111", 223 to 224=> "11110000", 225 to 226=> "11110001",
227 to 228=> "11110010", 229 => "11110011", 230 to 231=> "11110100", 232 to 233=> "11110101",
234 to 235=> "11110110", 236 to 237=> "11110111", 238 to 240=> "11111000", 241 to 242=> "11111001",
243 to 244=> "11111010", 245 to 246=> "11111011", 247 to 248=> "11111100", 249 to 251=> "11111101",
252 to 253=> "11111110", 254 to 255=> "11111111" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_jbC is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_jbC is
component Loop_loop_height_jbC_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_jbC_rom_U : component Loop_loop_height_jbC_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
3e44668ef2822a40812ff86f2da5372d
| 0.544446 | 3.657007 | false | false | false | false |
NickTGraham/Traffic-Light-Controller
|
Traffic.vhd
| 1 | 7,749 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Traffic IS
PORT ( SW : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
Clock_50 : IN STD_LOGIC;
LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 6);
LEDG : OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END Traffic;
ARCHITECTURE Behavior OF Traffic IS
COMPONENT CONTROL
PORT( S:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
a, b, c, d, e, f, g, h :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M :OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT;
COMPONENT LIGHT
PORT(C :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
COLOR :OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
COMPONENT UpCounter
PORT( myClock : IN STD_LOGIC;
O : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
COMPONENT Clockz
Generic (N : INTEGER);
PORT ( Clock_50 : IN STD_LOGIC;
C : BUFFER STD_LOGIC);
END COMPONENT;
COMPONENT WALK
PORT (Blink : IN STD_LOGIC;
LSTATUS: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
WSTATUS : OUT STD_LOGIC);
END COMPONENT;
COMPONENT MODCLOCK
Generic (N : INTEGER);
PORT ( Clock_50, Trigger : IN STD_LOGIC;
Light : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
C : BUFFER STD_LOGIC);
END COMPONENT;
SIGNAL R, G, Y, A, B, C, D : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL WA, WB, WC, WD : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL S : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL L, T, L1, L2, Bl : STD_LOGIC;
BEGIN
G <= "00";
Y <= "01";
R <= "10";
T <= SW(5) OR SW(4) OR SW(1);
L0: Clockz Generic Map (50000000) --dropped a zero for testing
PORT MAP (Clock_50, L1);
B9: Clockz Generic Map (25000000) --droped a zero for testing
PORT MAP (Clock_50, Bl);
L5: ModClock Generic Map (50000000)
PORT MAP (Clock_50, T, A, L2);
L <= (Not SW(6) And L1) OR (SW(6) And L2);
S0: UpCounter PORT MAP(L, S); --Run through the Select options
A0: CONTROL PORT MAP (S, R, G, G, Y, R, R, R, R, A); --Light 1's State
B0: LIGHT PORT MAP (A, LEDR(17 DOWNTO 15)); --Control Light 1
WA(0) <= (NOT SW(2)) OR (SW(2) AND A(0)); --set up the Walk signal connected to light 1
WA(1) <= (NOT SW(2)) OR (SW(2) AND A(1)); --such that it displays Don't walk until the request is given, then it waits until it is safe to switch to walk
W0: WALK PORT MAP (Bl, WA, LEDG(0)); --control the Walk Sign.
C0: CONTROL PORT MAP (S, R, R, R, R, R, G, G, Y, B); --Set up for second Light and its Walk sign
D0: LIGHT PORT MAP (B, LEDR(14 DOWNTO 12));
WB(0) <= (NOT SW(1)) OR (SW(1) AND B(0));
WB(1) <= (NOT SW(1)) OR (SW(1) AND B(1));
W1: WALK PORT MAP (Bl, WB, LEDG(1));
E0: CONTROL PORT MAP (S, R, G, G, Y, R, R, R, R, C); --Set up for third Light and its Walk sign
F0: LIGHT PORT MAP (C, LEDR(11 DOWNTO 9));
WC(0) <= (NOT SW(2)) OR (SW(2) AND C(0));
WC(1) <= (NOT SW(2)) OR (SW(2) AND C(1));
W2: WALK PORT MAP (Bl, WC, LEDG(2));
G0: CONTROL PORT MAP (S, R, R, R, R, R, G, G, Y, D); --Set up for third Light and its Walk sign
H0: LIGHT PORT MAP (D, LEDR(8 DOWNTO 6));
WD(0) <= (NOT SW(1)) OR (SW(1) AND D(0));
WD(1) <= (NOT SW(1)) OR (SW(1) AND D(1));
W3: WALK PORT MAP (Bl, WD, LEDG(3));
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- implements a 2-bit wide 8-to-1 multiplexer
ENTITY CONTROL IS
PORT ( S : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
a, b, c, d, e, f, g, h : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END CONTROL;
ARCHITECTURE Behavior OF CONTROL IS
signal OUTPUT1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT3 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT4 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT5 : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal OUTPUT6 : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
--LEDR <= SW;
--bit 0
OUTPUT1(0) <= ((NOT S(0) And a(0)) OR (S(0) And b(0)));
OUTPUT2(0) <= ((NOT S(0) And c(0)) OR (S(0) And d(0)));
OUTPUT3(0) <= ((NOT S(0) And e(0)) OR (S(0) And f(0)));
OUTPUT4(0) <= ((NOT S(0) And g(0)) OR (S(0) And h(0)));
OUTPUT5(0) <= ((NOT S(1) And OUTPUT1(0)) OR (S(1) And OUTPUT2(0)));
OUTPUT6(0) <= ((NOT S(1) And OUTPUT3(0)) OR (S(1) And OUTPUT4(0)));
M(0) <= ((NOT S(2) And OUTPUT5(0)) OR (S(2) And OUTPUT6(0)));
--bit 1
OUTPUT1(1) <= ((NOT S(0) And a(1)) OR (S(0) And b(1)));
OUTPUT2(1) <= ((NOT S(0) And c(1)) OR (S(0) And d(1)));
OUTPUT3(1) <= ((NOT S(0) And e(1)) OR (S(0) And f(1)));
OUTPUT4(1) <= ((NOT S(0) And g(1)) OR (S(0) And h(1)));
OUTPUT5(1) <= ((NOT S(1) And OUTPUT1(1)) OR (S(1) And OUTPUT2(1)));
OUTPUT6(1) <= ((NOT S(1) And OUTPUT3(1)) OR (S(1) And OUTPUT4(1)));
M(1) <= ((NOT S(2) And OUTPUT5(1)) OR (S(2) And OUTPUT6(1)));
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY LIGHT IS
PORT (C: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
COLOR : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END LIGHT;
ARCHITECTURE Behavior OF LIGHT IS
BEGIN
COLOR(0) <= NOT(C(1)) AND NOT(C(0)); --green light
COLOR(1) <= NOT(C(1)) AND C(0); --yellow light
COLOR(2) <= C(1); --red light
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY WALK IS
PORT (Blink : IN STD_LOGIC;
LSTATUS: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
WSTATUS : OUT STD_LOGIC);
END WALK;
ARCHITECTURE Behavior OF WALK IS
BEGIN
WITH LSTATUS SELECT
WSTATUS <= '1' WHEN "00",
Blink WHEN "01",
'0' WHEN OTHERS;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Clockz IS
Generic (N : INTEGER);
PORT ( Clock_50 : IN STD_LOGIC;
C : BUFFER STD_LOGIC);
END Clockz;
ARCHITECTURE Behavior OF Clockz IS --clock behavior
Signal Count : INTEGER RANGE 0 to N; --clock frequency
BEGIN
PROCESS
BEGIN
wait until Clock_50='1';
Count<=Count+1;
if (Count = N) Then --dropped a zero for testing
Count<=0;
C <= Not C;
end if;
END PROCESS;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY myflipflop IS --flip flop behavior
PORT ( D, Clock : IN STD_LOGIC ;
Q :BUFFER STD_LOGIC );
END myflipflop;
ARCHITECTURE Behavior OF myflipflop IS --wait until clock event and then push D to Q
BEGIN
Process
Begin
Wait until Clock'Event And Clock='1' AND D='1';
Q <= NOT(Q);
End Process;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY UpCounter IS
PORT(myClock : IN STD_LOGIC;
O : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END UpCounter;
ARCHITECTURE Behavior OF UpCounter IS
COMPONENT myflipflop
PORT(D, Clock :IN STD_LOGIC;
Q :OUT STD_LOGIC);
END COMPONENT;
SIGNAL X, Y, Z, V, W : STD_LOGIC;
BEGIN
W <= myClock;
X0 : myflipflop PORT MAP ('1', W, X);
O(0) <= X; --LSB (Bit 0)
Y0 : myflipflop PORT MAP (X, W, Y);
O(1) <= Y; --Bit 1
V <= X AND Y;
Z0 : myflipflop PORT MAP (V, W, Z);
O(2) <= Z; --MSB (Bit 2)
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ModClock IS
GENERIC (N : integer);
PORT ( Clock_50, Trigger : IN STD_LOGIC;
Light : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
C : BUFFER STD_LOGIC);
END ModClock;
ARCHITECTURE Behavior OF ModClock IS --clock behavior
Signal Count : INTEGER RANGE 0 to N; --clock frequency
BEGIN
PROCESS
BEGIN
wait until Clock_50='1';
Count<=Count+1;
if (Count = N) Then
Count<=0;
if (Not (Light = "00")) Then
C<= NOT C;
elsif (Trigger = '1') Then
C <= Not C;
else
C <= C;
end if;
end if;
END PROCESS;
END Behavior;
|
gpl-2.0
|
8b3028fc402efd6eb0892250d8e2ba72
| 0.581107 | 2.855195 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_eOg.vhd
| 1 | 14,256 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_eOg_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_eOg_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00000011", 2 => "00000100", 3 => "00000110",
4 => "00001000", 5 => "00001010", 6 => "00001011", 7 => "00001101",
8 => "00001110", 9 => "00010000", 10 => "00010001", 11 => "00010011",
12 => "00010100", 13 => "00010101", 14 => "00010111", 15 => "00011000",
16 => "00011001", 17 => "00011011", 18 => "00011100", 19 => "00011101",
20 => "00011111", 21 => "00100000", 22 => "00100001", 23 => "00100010",
24 => "00100100", 25 => "00100101", 26 => "00100110", 27 => "00100111",
28 => "00101000", 29 => "00101010", 30 => "00101011", 31 => "00101100",
32 => "00101101", 33 => "00101110", 34 => "00110000", 35 => "00110001",
36 => "00110010", 37 => "00110011", 38 => "00110100", 39 => "00110101",
40 => "00110110", 41 => "00111000", 42 => "00111001", 43 => "00111010",
44 => "00111011", 45 => "00111100", 46 => "00111101", 47 => "00111110",
48 => "00111111", 49 => "01000001", 50 => "01000010", 51 => "01000011",
52 => "01000100", 53 => "01000101", 54 => "01000110", 55 => "01000111",
56 => "01001000", 57 => "01001001", 58 => "01001010", 59 => "01001011",
60 => "01001100", 61 => "01001101", 62 => "01001110", 63 => "01010000",
64 => "01010001", 65 => "01010010", 66 => "01010011", 67 => "01010100",
68 => "01010101", 69 => "01010110", 70 => "01010111", 71 => "01011000",
72 => "01011001", 73 => "01011010", 74 => "01011011", 75 => "01011100",
76 => "01011101", 77 => "01011110", 78 => "01011111", 79 => "01100000",
80 => "01100001", 81 => "01100010", 82 => "01100011", 83 => "01100100",
84 => "01100101", 85 => "01100110", 86 => "01100111", 87 => "01101000",
88 => "01101001", 89 => "01101010", 90 => "01101011", 91 => "01101100",
92 => "01101101", 93 => "01101110", 94 => "01101111", 95 => "01110000",
96 => "01110001", 97 => "01110010", 98 => "01110011", 99 => "01110100",
100 => "01110101", 101 => "01110110", 102 => "01110111", 103 => "01111000",
104 => "01111001", 105 => "01111010", 106 => "01111011", 107 => "01111100",
108 => "01111101", 109 => "01111110", 110 => "01111111", 111 to 112=> "10000000",
113 => "10000001", 114 => "10000010", 115 => "10000011", 116 => "10000100",
117 => "10000101", 118 => "10000110", 119 => "10000111", 120 => "10001000",
121 => "10001001", 122 => "10001010", 123 => "10001011", 124 => "10001100",
125 => "10001101", 126 => "10001110", 127 => "10001111", 128 => "10010000",
129 to 130=> "10010001", 131 => "10010010", 132 => "10010011", 133 => "10010100",
134 => "10010101", 135 => "10010110", 136 => "10010111", 137 => "10011000",
138 => "10011001", 139 => "10011010", 140 => "10011011", 141 => "10011100",
142 to 143=> "10011101", 144 => "10011110", 145 => "10011111", 146 => "10100000",
147 => "10100001", 148 => "10100010", 149 => "10100011", 150 => "10100100",
151 => "10100101", 152 => "10100110", 153 => "10100111", 154 to 155=> "10101000",
156 => "10101001", 157 => "10101010", 158 => "10101011", 159 => "10101100",
160 => "10101101", 161 => "10101110", 162 => "10101111", 163 => "10110000",
164 to 165=> "10110001", 166 => "10110010", 167 => "10110011", 168 => "10110100",
169 => "10110101", 170 => "10110110", 171 => "10110111", 172 => "10111000",
173 to 174=> "10111001", 175 => "10111010", 176 => "10111011", 177 => "10111100",
178 => "10111101", 179 => "10111110", 180 => "10111111", 181 => "11000000",
182 to 183=> "11000001", 184 => "11000010", 185 => "11000011", 186 => "11000100",
187 => "11000101", 188 => "11000110", 189 => "11000111", 190 to 191=> "11001000",
192 => "11001001", 193 => "11001010", 194 => "11001011", 195 => "11001100",
196 => "11001101", 197 => "11001110", 198 to 199=> "11001111", 200 => "11010000",
201 => "11010001", 202 => "11010010", 203 => "11010011", 204 => "11010100",
205 to 206=> "11010101", 207 => "11010110", 208 => "11010111", 209 => "11011000",
210 => "11011001", 211 => "11011010", 212 to 213=> "11011011", 214 => "11011100",
215 => "11011101", 216 => "11011110", 217 => "11011111", 218 => "11100000",
219 to 220=> "11100001", 221 => "11100010", 222 => "11100011", 223 => "11100100",
224 => "11100101", 225 => "11100110", 226 to 227=> "11100111", 228 => "11101000",
229 => "11101001", 230 => "11101010", 231 => "11101011", 232 => "11101100",
233 to 234=> "11101101", 235 => "11101110", 236 => "11101111", 237 => "11110000",
238 => "11110001", 239 to 240=> "11110010", 241 => "11110011", 242 => "11110100",
243 => "11110101", 244 => "11110110", 245 to 246=> "11110111", 247 => "11111000",
248 => "11111001", 249 => "11111010", 250 => "11111011", 251 to 252=> "11111100",
253 => "11111101", 254 => "11111110", 255 => "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00000011", 2 => "00000100", 3 => "00000110",
4 => "00001000", 5 => "00001010", 6 => "00001011", 7 => "00001101",
8 => "00001110", 9 => "00010000", 10 => "00010001", 11 => "00010011",
12 => "00010100", 13 => "00010101", 14 => "00010111", 15 => "00011000",
16 => "00011001", 17 => "00011011", 18 => "00011100", 19 => "00011101",
20 => "00011111", 21 => "00100000", 22 => "00100001", 23 => "00100010",
24 => "00100100", 25 => "00100101", 26 => "00100110", 27 => "00100111",
28 => "00101000", 29 => "00101010", 30 => "00101011", 31 => "00101100",
32 => "00101101", 33 => "00101110", 34 => "00110000", 35 => "00110001",
36 => "00110010", 37 => "00110011", 38 => "00110100", 39 => "00110101",
40 => "00110110", 41 => "00111000", 42 => "00111001", 43 => "00111010",
44 => "00111011", 45 => "00111100", 46 => "00111101", 47 => "00111110",
48 => "00111111", 49 => "01000001", 50 => "01000010", 51 => "01000011",
52 => "01000100", 53 => "01000101", 54 => "01000110", 55 => "01000111",
56 => "01001000", 57 => "01001001", 58 => "01001010", 59 => "01001011",
60 => "01001100", 61 => "01001101", 62 => "01001110", 63 => "01010000",
64 => "01010001", 65 => "01010010", 66 => "01010011", 67 => "01010100",
68 => "01010101", 69 => "01010110", 70 => "01010111", 71 => "01011000",
72 => "01011001", 73 => "01011010", 74 => "01011011", 75 => "01011100",
76 => "01011101", 77 => "01011110", 78 => "01011111", 79 => "01100000",
80 => "01100001", 81 => "01100010", 82 => "01100011", 83 => "01100100",
84 => "01100101", 85 => "01100110", 86 => "01100111", 87 => "01101000",
88 => "01101001", 89 => "01101010", 90 => "01101011", 91 => "01101100",
92 => "01101101", 93 => "01101110", 94 => "01101111", 95 => "01110000",
96 => "01110001", 97 => "01110010", 98 => "01110011", 99 => "01110100",
100 => "01110101", 101 => "01110110", 102 => "01110111", 103 => "01111000",
104 => "01111001", 105 => "01111010", 106 => "01111011", 107 => "01111100",
108 => "01111101", 109 => "01111110", 110 => "01111111", 111 to 112=> "10000000",
113 => "10000001", 114 => "10000010", 115 => "10000011", 116 => "10000100",
117 => "10000101", 118 => "10000110", 119 => "10000111", 120 => "10001000",
121 => "10001001", 122 => "10001010", 123 => "10001011", 124 => "10001100",
125 => "10001101", 126 => "10001110", 127 => "10001111", 128 => "10010000",
129 to 130=> "10010001", 131 => "10010010", 132 => "10010011", 133 => "10010100",
134 => "10010101", 135 => "10010110", 136 => "10010111", 137 => "10011000",
138 => "10011001", 139 => "10011010", 140 => "10011011", 141 => "10011100",
142 to 143=> "10011101", 144 => "10011110", 145 => "10011111", 146 => "10100000",
147 => "10100001", 148 => "10100010", 149 => "10100011", 150 => "10100100",
151 => "10100101", 152 => "10100110", 153 => "10100111", 154 to 155=> "10101000",
156 => "10101001", 157 => "10101010", 158 => "10101011", 159 => "10101100",
160 => "10101101", 161 => "10101110", 162 => "10101111", 163 => "10110000",
164 to 165=> "10110001", 166 => "10110010", 167 => "10110011", 168 => "10110100",
169 => "10110101", 170 => "10110110", 171 => "10110111", 172 => "10111000",
173 to 174=> "10111001", 175 => "10111010", 176 => "10111011", 177 => "10111100",
178 => "10111101", 179 => "10111110", 180 => "10111111", 181 => "11000000",
182 to 183=> "11000001", 184 => "11000010", 185 => "11000011", 186 => "11000100",
187 => "11000101", 188 => "11000110", 189 => "11000111", 190 to 191=> "11001000",
192 => "11001001", 193 => "11001010", 194 => "11001011", 195 => "11001100",
196 => "11001101", 197 => "11001110", 198 to 199=> "11001111", 200 => "11010000",
201 => "11010001", 202 => "11010010", 203 => "11010011", 204 => "11010100",
205 to 206=> "11010101", 207 => "11010110", 208 => "11010111", 209 => "11011000",
210 => "11011001", 211 => "11011010", 212 to 213=> "11011011", 214 => "11011100",
215 => "11011101", 216 => "11011110", 217 => "11011111", 218 => "11100000",
219 to 220=> "11100001", 221 => "11100010", 222 => "11100011", 223 => "11100100",
224 => "11100101", 225 => "11100110", 226 to 227=> "11100111", 228 => "11101000",
229 => "11101001", 230 => "11101010", 231 => "11101011", 232 => "11101100",
233 to 234=> "11101101", 235 => "11101110", 236 => "11101111", 237 => "11110000",
238 => "11110001", 239 to 240=> "11110010", 241 => "11110011", 242 => "11110100",
243 => "11110101", 244 => "11110110", 245 to 246=> "11110111", 247 => "11111000",
248 => "11111001", 249 => "11111010", 250 => "11111011", 251 to 252=> "11111100",
253 => "11111101", 254 => "11111110", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_eOg is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_eOg is
component Loop_loop_height_eOg_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_eOg_rom_U : component Loop_loop_height_eOg_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
mit
|
b560827f56df2071f831618ae99e29dd
| 0.542929 | 3.64324 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
lab4_20_key/lab4_20_key.vhd
| 1 | 4,117 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lab4_20_key is
Port (
row : in std_logic_vector( 4 downto 0 );
column : out std_logic_vector( 3 downto 0 );
clock : in std_logic;
selector : out std_logic_vector( 2 downto 0 );
segment : out std_logic_vector( 7 downto 0 )
);
end lab4_20_key;
architecture Behavioral of lab4_20_key is
signal segment_register : std_logic_vector( 47 downto 0 ) := "000000000000000000000000000000000000000000000000";
signal number : std_logic_vector( 2 downto 0 ) := "000";-- decimal 0 to 7
signal press : std_logic_vector( 7 downto 0 ) := "00000000";
signal count_scan : std_logic_vector( 1 downto 0 ) := "00";
signal clock_time : std_logic_vector( 15 downto 0 ) := "0000000000000000";
begin
process( clock ) begin
if clock'event and clock = '1' then
clock_time <= clock_time + 1 ;
if clock_time = 0 then
count_scan <= count_scan + 1;
if count_scan = 0 then
--column <= "1110";
column <= "1101";
if row = "11110" then
press <= "11000000"; -- 0
elsif row = "11101" then
press <= "11111001"; -- 1
elsif row = "11011" then
press <= "10100100"; -- 2
elsif row = "10111" then
press <= "10110000"; -- 3
elsif row = "01111" then
press <= "10011001"; -- 4
end if;
--segment_register <= segment_register(39 downto 0) & press;
elsif count_scan = 1 then
--column <= "1101";
column <= "1011";
if row = "11110" then
press <= "10010010"; -- 5
elsif row = "11101" then
press <= "10000010"; -- 6
elsif row = "11011" then
press <= "11111000"; -- 7
elsif row = "10111" then
press <= "10000000"; -- 8
elsif row = "01111" then
press <= "10010000"; -- 9
end if;
--segment_register <= segment_register(39 downto 0) & press;
elsif count_scan = 2 then
--column <= "1011";
column <= "0111";
if row = "11110" then
press <= "10001000"; -- A
elsif row = "11101" then
press <= "10000011"; -- B
elsif row = "11011" then
press <= "11000110"; -- C
elsif row = "10111" then
press <= "10100001"; -- D
elsif row = "01111" then
press <= "10000110"; -- E
end if;
--segment_register <= segment_register(39 downto 0) & press;
elsif count_scan = 3 then
-- column <= "0111";
column <= "1110";
if row = "11110" then
press <= "10001110"; -- F
elsif row = "11101" then
press <= "00010000"; -- G
elsif row = "11011" then
press <= "10001001"; -- H
elsif row = "10111" then
press <= "01111001"; -- I
elsif row = "01111" then
press <= "01110001"; -- J
end if;
--segment_register <= segment_register(39 downto 0) & press;
end if;
number <= number + 1;
if number = 0 then
selector <= "000";
segment <= segment_register(7 downto 0);
elsif number = 1 then
selector <= "001";
segment <= segment_register(15 downto 8);
elsif number = 2 then
selector <= "010";
segment <= segment_register(23 downto 16);
elsif number = 3 then
selector <= "011";
segment <= segment_register(31 downto 24);
elsif number = 4 then
selector <= "100";
segment <= segment_register(39 downto 32);
elsif number = 5 then
selector <= "101";
segment <= segment_register(47 downto 40);
end if;
end if; -- if clock_time = 0 then
end if; -- if clock'event and clock = '1' then
end process;
process( press ) begin
segment_register <= segment_register(39 downto 0) & press;
end process;
end Behavioral;
|
mit
|
0d082c22a8857c49b1e7c1b79678bd86
| 0.552344 | 3.586237 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/tb_gestor_display.vhd
| 1 | 2,109 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gestor_display IS
END tb_gestor_display;
ARCHITECTURE behavior OF tb_gestor_display IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gestor_display
PORT(
CLK : IN std_logic;
piso_now : IN std_logic_vector(1 downto 0);
piso_obj : IN std_logic_vector(1 downto 0);
piso_seleccionado : OUT std_logic_vector(1 downto 0);
piso_actual : OUT std_logic_vector(1 downto 0);
accion : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal piso_now : std_logic_vector(1 downto 0) := (others => '0');
signal piso_obj : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal piso_seleccionado : std_logic_vector(1 downto 0);
signal piso_actual : std_logic_vector(1 downto 0);
signal accion : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gestor_display PORT MAP (
CLK => CLK,
piso_now => piso_now,
piso_obj => piso_obj,
piso_seleccionado => piso_seleccionado,
piso_actual => piso_actual,
accion => accion
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
WAIT FOR 2 ns;
piso_now <= "01";
piso_obj <= "11";
WAIT FOR 20 ns;
piso_now <= "10";
WAIT FOR 20 ns;
piso_now <= "11";
WAIT FOR 20 ns;
piso_obj <= "00";
WAIT FOR 20 ns;
piso_now <= "10";
WAIT FOR 20 ns;
piso_obj <= "01";
WAIT FOR 20 ns;
piso_now <= "11";
WAIT FOR 20 ns;
piso_now <= "00";
WAIT FOR 20 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
|
gpl-3.0
|
20a5e82dce61310787989f5dbe198653
| 0.57468 | 3.446078 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_stredEe.vhd
| 1 | 2,151 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_stredEe_DSP48_2 is
port (
in0: in std_logic_vector(8 - 1 downto 0);
in1: in std_logic_vector(23 - 1 downto 0);
in2: in std_logic_vector(29 - 1 downto 0);
dout: out std_logic_vector(30 - 1 downto 0));
end entity;
architecture behav of hls_contrast_stredEe_DSP48_2 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(unsigned(in1), 25));
b <= signed(resize(unsigned(in0), 18));
c <= signed(resize(unsigned(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 30));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_stredEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_stredEe is
component hls_contrast_stredEe_DSP48_2 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_stredEe_DSP48_2_U : component hls_contrast_stredEe_DSP48_2
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
mit
|
7d02a5a5ca3c1b3715807d6dab31dcd5
| 0.570432 | 3.360938 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/S_AXI_Lite.vhd
| 1 | 15,074 |
-------------------------------------------------------------------------------
--
-- File: InputBuffer.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MIPI_DPHY_Receiver_S_AXI_Lite is
generic (
-- Users to add parameters here
kVersionMajor : natural := 0;
kVersionMinor : natural := 0;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
xEnable : out std_logic;
xRst : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end MIPI_DPHY_Receiver_S_AXI_Lite;
architecture arch_imp of MIPI_DPHY_Receiver_S_AXI_Lite is
constant kCTRL_EN : natural := 1;
constant kCTRL_RST : natural := 0;
constant kVersion : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(kVersionMajor,16)) & std_logic_vector(to_unsigned(kVersionMinor,16));
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 1
signal control_reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
control_reg <= (kCTRL_RST => '0', kCTRL_EN => '1', others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
control_reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
control_reg <= control_reg;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (control_reg, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= control_reg;
when b"11" =>
reg_data_out <= kVersion;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
xEnable <= control_reg(kCTRL_EN);
xRst <= control_reg(kCTRL_RST);
-- User logic ends
end arch_imp;
|
mit
|
e28b05f2906c4536e0cfbc97d7a4cd31
| 0.636858 | 3.582224 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/fifo_w8_d2_A.vhd
| 1 | 4,586 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d2_A_shiftReg;
architecture rtl of fifo_w8_d2_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fifo_w8_d2_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d2_A is
component fifo_w8_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2);
if (mOutPtr = conv_std_logic_vector(0, 2)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d2_A_shiftReg : fifo_w8_d2_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
f810f9c87718fb47cda3b36ecdf8bcaf
| 0.531836 | 3.412202 | false | false | false | false |
Digilent/vivado-library
|
module/synchronizers/SyncBase.vhd
| 2 | 4,873 |
-------------------------------------------------------------------------------
--
-- File: SyncBase.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes a signal (iIn) in one clock domain (InClk) with
-- another clock domain (OutClk) and provides it on oOut.
-- The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous resets (aiReset and aoReset) with
-- synchronous deassertion are always active-high, and they should not be
-- asserted independently.
--
-- Constraints:
-- # Replace <InstSyncBase> with path to SyncAsync instance, keep rest unchanged
-- # Begin scope to SyncBase instance
-- current_instance [get_cells <InstSyncBase>]
-- # Input to synchronizer ignored for timing analysis
-- set_false_path -through [get_pins SyncAsyncx/aIn]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells SyncAsyncx/oSyncStages_reg[*]] -to [get_cells SyncAsyncx/oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to SyncBase instance
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncBase is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aiReset : in STD_LOGIC; -- active-high asynchronous reset
InClk : in std_logic;
iIn : in STD_LOGIC;
aoReset : in STD_LOGIC; -- active-high asynchronous reset
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of SyncBase : entity is "yes";
end SyncBase;
architecture Behavioral of SyncBase is
signal iIn_q : std_logic;
begin
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aiReset, InClk)
begin
if (aiReset = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aoReset => aoReset,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
mit
|
58b1f0d627d5bb780df0325d5d0ea50f
| 0.682742 | 4.524605 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
fourbit_submodule.vhd
| 1 | 2,462 |
-------------------------------------------------------------------------------
--
-- Title : fourbit_submodule
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\fourbit_submodule.vhd
-- Generated : Thu Nov 17 11:48:45 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {fourbit_submodule} architecture {structural}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fourbit_submodule is
port(
a: in std_logic_vector (3 downto 0);
b: in std_logic_vector (3 downto 0);
c0: in std_logic;
s: out std_logic_vector (3 downto 0);
Pi: out std_logic;
Gi: out std_logic
);
end fourbit_submodule;
--}} End of automatically maintained section
architecture structural of fourbit_submodule is
signal p0, p1, p2, p3, g0, g1, g2, g3, c1, c2, c3: std_logic;
begin
u1: entity xor_2_structural port map(i1 => a(0), i2 => b(0), o1 => p0);
u2: entity xor_2_structural port map(i1 => a(1), i2 => b(1), o1 => p1);
u3: entity xor_2_structural port map(i1 => a(2), i2 => b(2), o1 => p2);
u4: entity xor_2_structural port map(i1 => a(3), i2 => b(3), o1 => p3);
Pi <= p0 and p1 and p2 and p3;
u5: entity and_2 port map(i1 => a(0), i2 => b(0), o1 => g0);
u6: entity and_2 port map(i1 => a(1), i2 => b(1), o1 => g1);
u7: entity and_2 port map(i1 => a(2), i2 => b(2), o1 => g2);
u8: entity and_2 port map(i1 => a(3), i2 => b(3), o1 => g3);
Gi <= g3 or (p3 and g2) or (p3 and p2 and g1) or (p3 and p2 and p1 and g0);
c1 <= g0 or (p0 and c0);
c2 <= g1 or (p1 and g0) or (p1 and p0 and c0);
c3 <= g2 or (p2 and g1) or (p2 and p1 and g0) or (p2 and p1 and p0 and c0);
u13: entity xor_2_structural port map(i1 => p0, i2 => c0, o1 => s(0));
u14: entity xor_2_structural port map(i1 => p1, i2 => c1, o1 => s(1));
u15: entity xor_2_structural port map(i1 => p2, i2 => c2, o1 => s(2));
u16: entity xor_2_structural port map(i1 => p3, i2 => c3, o1 => s(3));
end structural;
|
apache-2.0
|
9b34ebd0b8fa24c72f2808cc03921c3b
| 0.506905 | 2.82016 | false | false | false | false |
Digilent/vivado-library
|
ip/AXI_DPTI_1.0/src/AXI_DPTI_v1_0_AXI_LITE.vhd
| 1 | 19,080 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dpti_v1_0_AXI_LITE is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
lAXI_LiteLengthReg : out std_logic_vector (31 downto 0);
lAXI_LiteControlReg : out std_logic_vector (31 downto 0);
lAXI_LiteStatusReg : out std_logic_vector (31 downto 0);
lPushLength : out std_logic;
lPushControl : out std_logic;
lRdyLength : in std_logic;
lRdyControl : in std_logic;
lAckLength : in std_logic;
lAckControl : in std_logic;
TxLengthEmpty : in std_logic;
RxLengthEmpty : in std_logic;
prog_spien : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_dpti_v1_0_AXI_LITE;
architecture arch_imp of axi_dpti_v1_0_AXI_LITE is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
------------------------------------------------------------------------
--User signals
------------------------------------------------------------------------
signal StatusReg : std_logic_vector(31 downto 0);
signal clearResetFlag : std_logic;
signal lOneshotTriggerLength : std_logic := '0'; -- used to generate LENGTH handshakedata IPUSH signal
signal lOneshotTriggerControl : std_logic := '0'; -- used to generate CONTROL handshakedata IPUSH signal
signal lCtlPushLength : std_logic ;
signal lCtlPushControl : std_logic ;
signal lLengthTrig : std_logic := '0';
signal lControlTrig : std_logic := '0';
signal lLengthFlag : std_logic := '0';
signal lControlFlag : std_logic := '0';
begin
lAXI_LiteStatusReg <= slv_reg2;
StatusReg(0) <= TxLengthEmpty;
StatusReg(16) <= RxLengthEmpty;
lPushLength <= lCtlPushLength;
lPushControl <= lCtlPushControl;
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
lAXI_LiteLengthReg <= slv_reg0; -- LENGTH register
lAXI_LiteControlReg <= slv_reg1; -- CONTROL register
--slv_reg2 <= StatusReg; -- STATUS register
--Latch prog_spien. This is used to detect when it has been hotplugged in software.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if(prog_spien='1')then
StatusReg(1) <= '1';
else if (slv_reg1(2) ='1')then
StatusReg(1) <= '0';
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
lOneshotTriggerLength <= '0';
lOneshotTriggerControl <= '0';
else
slv_reg2 <= StatusReg;
lOneshotTriggerLength <= '0';
lOneshotTriggerControl <= '0';
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
lOneshotTriggerLength <= '1'; -- oneshot
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
lOneshotTriggerControl <= '1'; -- oneshot
end if;
end loop;
when b"10" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 2
-- slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= StatusReg;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
--------------------------------------------------------------------------------------------------------------------------
GEN_lPushLength: process (S_AXI_ACLK)
variable count : integer range 0 to 1;
begin
if rising_edge (S_AXI_ACLK) then
if lOneshotTriggerLength = '1' and lLengthFlag = '0' then
lLengthTrig <= '1';
end if;
if lLengthTrig = '0' or lRdyLength = '0' or lControlTrig = '1' then
count := 1;
lCtlPushLength <= '0';
elsif count = 1 and lRdyControl = '1' then
lCtlPushLength <= '1';
count := 0;
else
lCtlPushLength <= '0';
end if;
if lCtlPushLength = '1' then
lLengthTrig <= '0';
lLengthFlag <= '1';
end if;
if lAckLength = '1' then
lLengthFlag <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
GEN_lPushControl: process (S_AXI_ACLK)
variable count : integer range 0 to 1;
begin
if rising_edge (S_AXI_ACLK) then
if lOneshotTriggerControl = '1' and lControlFlag = '0' then
lControlTrig <= '1';
end if;
if lControlTrig = '0' or lRdyControl = '0' then
count := 1;
lCtlPushControl <= '0';
elsif count = 1 then
lCtlPushControl <= '1';
count := 0;
elsif count = 0 then
lCtlPushControl <= '0';
end if;
if lCtlPushControl = '1' then
lControlTrig <= '0';
lControlFlag <= '1';
end if;
if lAckControl = '1' then
lControlFlag <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
-- User logic ends
end arch_imp;
|
mit
|
2fe06b56c97bde028a2167fbca03e87d
| 0.594235 | 3.643307 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/clkTB.vhd
| 2 | 1,619 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clkTB IS
END clkTB;
ARCHITECTURE behavior OF clkTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clk_mod
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada : std_logic := '0';
signal reset : std_logic := '0';
-- Salidas
signal salida : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: clk_mod PORT MAP (
entrada => entrada,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada <= '0';
wait for entrada_t / 2;
entrada <= '1';
wait for entrada_t / 2;
end process;
-- Procesamiento de estímulos.
estimulos: process
begin
reset <= '1'; -- Condiciones iniciales.
wait for 100 ns;
reset <= '0'; -- ¡A trabajar!
wait;
end process;
END;
|
gpl-2.0
|
79a3a9d39e6b301c81b9f7215d51fb8d
| 0.518839 | 4.509749 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
absdb.vhd
| 1 | 1,868 |
-------------------------------------------------------------------------------
--
-- Title : absdb
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\absdb.vhd
-- Generated : Tue Dec 6 14:07:10 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {absdb} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity absdb is
port(
rs1: in std_logic_vector(63 downto 0);
rs2: in std_logic_vector(63 downto 0);
rd: out std_logic_vector (63 downto 0)
);
end absdb;
--}} End of automatically maintained section
architecture behavioral of absdb is
begin
process(rs1,rs2)
variable diff: unsigned(7 downto 0);
variable larger: unsigned(7 downto 0);
variable smaller: unsigned(7 downto 0);
begin
diff:=to_unsigned(0,8) ;
for j in 0 to 7 loop
if(rs1((j*8+7) downto j*8)>rs2((j*8+7) downto j*8)) then
larger:= unsigned(rs1((j*8+7) downto j*8));
smaller:=unsigned(rs2((j*8+7) downto j*8));
else
larger:= unsigned(rs2((j*8+7) downto j*8));
smaller:=unsigned(rs1((j*8+7) downto j*8));
end if;
diff:= larger-smaller;
rd(j*8+7 downto j*8)<=std_logic_vector(diff);
end loop;
end process;
end behavioral;
|
apache-2.0
|
5b4906bdc7d65ecc83634f547a556868
| 0.474839 | 3.537879 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/src/ZmodAWG_1411_Controller.vhd
| 1 | 19,392 |
-------------------------------------------------------------------------------
--
-- File: ZmodAWG1411_Controller.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 15 January 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module interfaces directly with the Zmod AWG 1411. It configures the Zmod's
-- DAC gain based on user options, writes an initial configuration to the AD9717
-- (also performing a self calibration sequence), manages the DAC's SPI interface
-- and encodes the samples received on the two input data channels in the format
-- requested by AD9717.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
use work.PkgZmodDAC.all;
entity ZmodAWG_1411_Controller is
generic (
-- Parameter identifying the Zmod:
-- 7 -> Zmod AWG 1411 - (AD9717)
kZmodID : integer range 7 to 7 := 7;
-- DAC resolution (number of bits).
kDAC_Width : integer range 10 to 16 := 14;
-- DAC dynamic/static calibration.
kExtCalibEn : boolean := false;
-- Scale dynamic/static calibration.
kExtScaleConfigEn : boolean := false;
-- Enable/Disable SPI Indirect Access Port.
kExtCmdInterfaceEn : boolean := false;
-- Channel1 low gain multiplicative (gain) compensation coefficient parameter.
kCh1LgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel1 low gain additive (offset) compensation coefficient parameter.
kCh1LgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter.
kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel1 high gain additive (offset) compensation coefficient parameter.
kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel2 low gain multiplicative (gain) compensation coefficient parameter.
kCh2LgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel2 low gain additive (offset) compensation coefficient parameter.
kCh2LgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter.
kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel2 high gain additive (offset) compensation coefficient parameter.
kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel1 Scale select satic control: 0 -> Low Gain; 1 -> High Gain;
kCh1ScaleStatic : std_logic := '0';
-- Channel2 Scale select satic control: 0 -> Low Gain; 1 -> High Gain;
kCh2ScaleStatic : std_logic := '0'
);
Port (
-- 100MHZ clock input.
SysClk100 : in std_logic;
-- Data Interface (AXI Stream) synchronous clock input.
DAC_InIO_Clk : in std_logic;
-- Input clock used to generate the DAC's DCLKIO. It shouls have the same
-- frequency and a 90 degree phase shift with respect to DAC_InIO_Clk.
DAC_Clk : in std_logic;
-- Asynchronous active low reset.
aRst_n : in std_logic;
-- sTestMode is used to bypass the calibration block. When this signal
-- is asserted, raw samples are provided on the data interface.
sTestMode : in std_logic;
-- Initialization done active low indicator.
sInitDoneDAC : out std_logic := '0';
-- DAC initialization error signaling.
sConfigError : out STD_LOGIC := '0';
-- Axi Stream Data Interface (Salve).
cDataAxisTvalid: in STD_LOGIC;
cDataAxisTready: out STD_LOGIC;
cDataAxisTdata: in STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Zmod output relay control input signal.
sDAC_EnIn : in std_logic;
-- Channel1 scale select (dynamic) control input.
sExtCh1Scale : in std_logic;
-- Channel2 scale select (dynamic) control input.
sExtCh2Scale : in std_logic;
-- Calibration
-- Channel1 low gain multiplicative (gain) compensation coefficient external port.
cExtCh1LgMultCoef : in std_logic_vector (17 downto 0);
-- Channel1 low gain additive (offset) compensation coefficient external port.
cExtCh1LgAddCoef : in std_logic_vector (17 downto 0);
-- Channel1 high gain multiplicative (gain) compensation coefficient external port.
cExtCh1HgMultCoef : in std_logic_vector (17 downto 0);
-- Channel1 high gain additive (offset) compensation coefficient external port.
cExtCh1HgAddCoef : in std_logic_vector (17 downto 0);
-- Channel2 low gain multiplicative (gain) compensation coefficient external port.
cExtCh2LgMultCoef : in std_logic_vector (17 downto 0);
-- Channel2 low gain additive (offset) compensation coefficient external port.
cExtCh2LgAddCoef : in std_logic_vector (17 downto 0);
-- Channel2 high gain multiplicative (gain) compensation coefficient external port.
cExtCh2HgMultCoef : in std_logic_vector (17 downto 0);
-- Channel2 high gain additive (offset) compensation coefficient external port.
cExtCh2HgAddCoef : in std_logic_vector (17 downto 0);
-- SPI Indirect access port; it provides the means to indirectly access
-- the DAC registers. It is designed to interface with 2 AXI StreamFIFOs,
-- one that stores commands to be transmitted and one to store the received data.
-- TX command AXI stream interface
sCmdTxAxisTvalid: IN STD_LOGIC;
sCmdTxAxisTready: OUT STD_LOGIC := '0';
sCmdTxAxisTdata: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- RX command AXI stream interface
sCmdRxAxisTvalid: OUT STD_LOGIC := '0';
sCmdRxAxisTready: IN STD_LOGIC;
sCmdRxAxisTdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Zmod AWG 1411 external inteface
--AD9717 interface
sZmodDAC_CS : out std_logic;
sZmodDAC_SCLK : out std_logic;
sZmodDAC_SDIO : inout std_logic;
sZmodDAC_Reset : out std_logic;
ZmodDAC_ClkIO : out std_logic;
ZmodDAC_ClkIn : out std_logic;
dZmodDAC_Data : out std_logic_vector(13 downto 0);
-- Channel1 scale select output control signal.
sZmodDAC_SetFS1 : out std_logic := '0';
-- Channel2 scale select output control signal.
sZmodDAC_SetFS2 : out std_logic := '0';
-- Zmod output relay control (output) signal
sZmodDAC_EnOut : out std_logic := '0'
);
end ZmodAWG_1411_Controller;
architecture Behavioral of ZmodAWG_1411_Controller is
signal DAC_ClkInODDR, DAC_ClkIO_ODDR : std_logic;
signal asRst_n, acRst_n, adRst_n : std_logic;
signal asRst, acRst, adRst : std_logic;
signal cTestMode : std_logic;
signal sCh1ScaleState, sCh2ScaleState : std_logic;
signal cCh1ScaleState, cCh2ScaleState : std_logic;
signal sInitDoneDAC_Loc :std_logic;
signal cCh1In, cCh2In : std_logic_vector(kDAC_Width-1 downto 0);
signal cODDR_D1, cODDR_D2 : std_logic_vector(13 downto 0);
signal cCh1Calib, cCh2Calib : std_logic_vector(15 downto 0);
begin
-- The asynchronous reset input is converted to an RSD (reset with synchronous
-- de-assertion) in the SysClk100 domain, in the DacClk domain and in the
-- DAC_InIO_Clk domain.
InstDacSysReset : entity work.ResetBridge
Generic map(
kPolarity => '0')
Port map(
aRst => aRst_n,
OutClk => SysClk100,
aoRst => asRst_n);
asRst <= not asRst_n;
InstDacSamplingReset : entity work.ResetBridge
Generic map(
kPolarity => '0')
Port map(
aRst => aRst_n,
OutClk => DAC_InIO_Clk,
aoRst => acRst_n);
acRst <= not acRst_n;
InstDacClkReset : entity work.ResetBridge
Generic map(
kPolarity => '0')
Port map(
aRst => aRst_n,
OutClk => DAC_Clk,
aoRst => adRst_n);
adRst <= not adRst_n;
------------------------------------------------------------------------------------------
-- Zmod AWG 1411 scale select logic
------------------------------------------------------------------------------------------
--Select Static or dynamic control for scale select (output port or IP parameter)
sCh1ScaleState <= sExtCh1Scale when kExtScaleConfigEn = true else kCh1ScaleStatic;
sCh2ScaleState <= sExtCh2Scale when kExtScaleConfigEn = true else kCh2ScaleStatic;
sZmodDAC_SetFS1 <= sCh1ScaleState;
sZmodDAC_SetFS2 <= sCh2ScaleState;
-- Synchronize the sChxScaleState signal into DAC_InIO_Clk clock domain
-- The sCh1ScaleState will be used by the GainOffsetCalib module to apply the correct
-- calibration coefficients.
InstDacCh1ScaleSync: entity work.SyncBase
generic map (
kResetTo => '0',
kStages => 2)
port map (
aiReset => asRst,
InClk => SysClk100,
iIn => sCh1ScaleState,
aoReset => acRst,
OutClk => DAC_InIO_Clk,
oOut => cCh1ScaleState);
InstDacCh2ScaleSync: entity work.SyncBase
generic map (
kResetTo => '0',
kStages => 2)
port map (
aiReset => asRst,
InClk => SysClk100,
iIn => sCh2ScaleState,
aoReset => acRst,
OutClk => DAC_InIO_Clk,
oOut => cCh2ScaleState);
------------------------------------------------------------------------------------------
-- DAC (AD9717) configuration
------------------------------------------------------------------------------------------
--AD9717 reset signal generation
ProcDAC_Reset: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sZmodDAC_Reset <= '1';
elsif (rising_edge(SysClk100)) then
sZmodDAC_Reset <= '0';
end if;
end process;
InstConfigDAC: entity work.ConfigDAC
Generic Map (
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map (
SysClk100 => SysClk100,
asRst_n => asRst_n,
sInitDoneDAC => sInitDoneDAC_Loc,
sConfigError => sConfigError,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata,
sZmodDAC_CS => sZmodDAC_CS,
sZmodDAC_SCLK => sZmodDAC_SCLK,
sZmodDAC_SDIO => sZmodDAC_SDIO
);
sInitDoneDAC <= sInitDoneDAC_Loc;
-- Zmod AWG 1411 output relay control
ProcDAC_En: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sZmodDAC_EnOut <= '0';
elsif (rising_edge (SysClk100)) then
--enable output once initialization is complete and external enable port is set
sZmodDAC_EnOut <= sInitDoneDAC_Loc and sDAC_EnIn;
end if;
end process;
------------------------------------------------------------------------------------------
-- AD9717 clock (DCLKIO and CLKIN) generation
------------------------------------------------------------------------------------------
InstDAC_ClkIO_ODDR : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => DAC_ClkIO_ODDR, -- 1-bit DDR output
C => DAC_Clk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => adRst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Obuf instantiation is necessary so that the timing analysis for the output data
-- bus (sZmodData) accounts for the output buffers of both clock (ZmodDAC_ClkIO)
-- and data signals (-prop_thru_buffers is used with the set_output_delay constraint
-- for the data signals, so the output buffers are not explicitely instantiated for this sZmodData).
InstObufDAC_ClkIO : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST")
port map (
O => ZmodDAC_ClkIO, -- Buffer output (connect directly to top-level port)
I => DAC_ClkIO_ODDR -- Buffer input
);
InstDAC_ClkinODDR : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => DAC_ClkInODDR, -- 1-bit DDR output
C => DAC_Clk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => adRst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
InstObufDAC_ClkIn : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST")
port map (
O => ZmodDAC_ClkIn, -- Buffer output (connect directly to top-level port)
I => DAC_ClkInODDR -- Buffer input
);
------------------------------------------------------------------------------------------
-- Input Data interface
------------------------------------------------------------------------------------------
-- This IP processes the input samples in real time, so it can accept samples on the Data
-- Interface at any time.
cDataAxisTready <= '1';
ProcCh1Ch2Data : process (DAC_InIO_Clk, acRst_n)
begin
if (acRst_n = '0') then
cCh1In <= (others => '0');
cCh2In <= (others => '0');
elsif(rising_edge(DAC_InIO_Clk)) then
if (cDataAxisTvalid = '1') then
cCh1In <= cDataAxisTdata(31 downto 32-kDAC_Width);
cCh2In <= cDataAxisTdata(15 downto 16-kDAC_Width);
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Calibration
------------------------------------------------------------------------------------------
-- Synchronize sTestMode in the DAC_InIO_Clk domain.
InstDacTestModeSync: entity work.SyncBase
generic map (
kResetTo => '0',
kStages => 2)
port map (
aiReset => asRst,
InClk => SysClk100,
iIn => sTestMode,
aoReset => acRst,
OutClk => DAC_InIO_Clk,
oOut => cTestMode);
-- Apply the gain and offset calibration coefficients to the
-- samples received on the input Data Interface.
InstCh1DAC_Calibration : entity work.GainOffsetCalib
Generic Map(
kWidth => kDAC_Width,
kExtCalibEn => kExtCalibEn,
kInvert => false,
kLgMultCoefStatic => kCh1LgMultCoefStatic,
kLgAddCoefStatic => kCh1LgAddCoefStatic,
kHgMultCoefStatic => kCh1HgMultCoefStatic,
kHgAddCoefStatic => kCh1HgAddCoefStatic
)
Port Map
(
SamplingClk => DAC_InIO_Clk,
acRst_n => acRst_n,
cTestMode => cTestMode,
cExtLgMultCoef => cExtCh1LgMultCoef,
cExtLgAddCoef => cExtCh1LgAddCoef,
cExtHgMultCoef => cExtCh1HgMultCoef,
cExtHgAddCoef => cExtCh1HgAddCoef,
cGainState => cCh1ScaleState,
cDataRaw => cCh1In,
cDataInValid => '1',
cCalibDataOut => cCh1Calib,
cDataCalibValid => open
);
InstCh2DAC_Calibration : entity work.GainOffsetCalib
Generic Map(
kWidth => kDAC_Width,
kExtCalibEn => kExtCalibEn,
kInvert => false,
kLgMultCoefStatic => kCh2LgMultCoefStatic,
kLgAddCoefStatic => kCh2LgAddCoefStatic,
kHgMultCoefStatic => kCh2HgMultCoefStatic,
kHgAddCoefStatic => kCh2HgAddCoefStatic
)
Port Map
(
SamplingClk => DAC_InIO_Clk,
acRst_n => acRst_n,
cTestMode => cTestMode,
cExtLgMultCoef => cExtCh2LgMultCoef,
cExtLgAddCoef => cExtCh2LgAddCoef,
cExtHgMultCoef => cExtCh2HgMultCoef,
cExtHgAddCoef => cExtCh2HgAddCoef,
cGainState => cCh2ScaleState,
cDataRaw => cCh2In,
cDataInValid => '1',
cCalibDataOut => cCh2Calib,
cDataCalibValid => open
);
cODDR_D1 <= cCh1Calib(15 downto 2);
cODDR_D2 <= cCh2Calib(15 downto 2);
------------------------------------------------------------------------------------------
-- Output Data interface
------------------------------------------------------------------------------------------
-- The AD9717 DAC features a 14bit wide double data rate interface. The configuration
-- of the ODDR primitives used to encode the data on this interface assumes the following
-- settings have been applied to the Data Control register (address 0x02) of the AD9717:
-- IRISING = 1 and IFIRST = 1. Thus, the AD9717 should capture the I channel samples on
-- the rising edge of ZmodDAC_ClkIO (DCLKIO).
ForDAC_Data: for i in 0 to 13 generate
InstDataODDR : ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => dZmodDAC_Data(i), -- 1-bit DDR output
C => DAC_InIO_Clk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => cODDR_D1(i), -- 1-bit data input (positive edge)
D2 => cODDR_D2(i), -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate;
end Behavioral;
|
mit
|
552b1af882020b297fb8b8b5075d76e5
| 0.61742 | 4.466145 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/divisorfrec.vhd
| 1 | 682 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity divisorfrec is
PORT (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
salida:out STD_LOGIC
);
end divisorfrec;
architecture Behavioral of divisorfrec is
signal temporal: std_logic;
signal contador: integer range 0 to 299999 :=0; --De 50Mhz a 83Hz
begin
divisorfrec:process(clk,reset)
begin
if (reset='1') then
temporal <='0';
contador <=0;
elsif rising_edge(clk) then
if (contador=299999) then
temporal<= NOT (temporal);
contador <=0;
else
contador <= contador+1;
end if;
end if;
end process;
salida <=temporal;
end Behavioral;
|
gpl-3.0
|
dbe5621ed2e1a9c6792bc3c129626420
| 0.696481 | 3.004405 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/CLK_escalado_y_CountDown.vhd
| 2 | 2,203 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CLK_escalado_y_CountDown IS
END CLK_escalado_y_CountDown;
ARCHITECTURE behavior OF CLK_escalado_y_CountDown IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CountEventsDown
PORT(
entrada_clk : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
COMPONENT clk_mod
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal entrada_clk : std_logic := '0';
signal reset_clk : std_logic := '0';
--Outputs
signal salida : std_logic;
signal salida_clk : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clk_mod PORT MAP (
entrada => entrada_clk,
reset => reset_clk,
salida => salida_clk
);
uut2: CountEventsDown PORT MAP (
entrada_clk => salida_clk,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada_clk <= '0';
wait for entrada_t / 2;
entrada_clk <= '1';
wait for entrada_t / 2;
end process;
-- Stimulus process
stim_proc: process
begin
reset<='1';
reset_clk<='1';-- hold reset state for 100 ns.
wait for 100 ns;
reset_clk<='0';
wait for 100 ns;
reset<='0';
wait for entrada_t*20;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
c118155c73ae3edb429b0a79d969cbeb
| 0.525647 | 4.371032 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/DMA_Transfer_Manager.vhd
| 2 | 77,140 |
-------------------------------------------------------------------------------
--
-- File: DMA_Transfer_Manager.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module manages all transfers from main memory to local buffers through
-- DMA, both control data (Queue Heads, Transfer Descriptors)and packet data.
-- Control registers are visible to this module.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
entity DMA_Transfer_Manager is
generic (
-- The master will start generating data from the C_M_START_DATA_VALUE value
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
-- The master requires a target slave base address.
-- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := "0100000000";
-- Width of M_AXI address bus.
-- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
C_M_AXI_ADDR_WIDTH : integer := 10;
-- Width of M_AXI data bus.
-- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
C_M_AXI_DATA_WIDTH : integer := 32;
-- Transaction number is the number of write
-- and read transactions the master will perform as a part of this example memory test.
C_M_TRANSACTIONS_NUM : integer := 4;
C_FIFO_SIZE : integer := 64
);
port (
Axi_Clk : IN std_logic;
Axi_Resetn : IN std_logic;
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0); --debug purposes
state_ind_arb : out std_logic_vector(5 downto 0); --debug purposes
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0); --debug purposes
ind_statte_axistream : out std_logic_vector(4 downto 0); --debug purposes
--AXI Lite Master for DMA control
a_M_Axi_Awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
a_M_Axi_Awprot : out std_logic_vector(2 downto 0);
a_M_Axi_Awvalid : out std_logic;
a_M_Axi_Awready : in std_logic;
a_M_Axi_Wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
a_M_Axi_Wstrb : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
a_M_Axi_Wvalid : out std_logic;
a_M_Axi_Wready : in std_logic;
a_M_Axi_Bresp : in std_logic_vector(1 downto 0);
a_M_Axi_Bvalid : in std_logic;
a_M_Axi_Bready : out std_logic;
a_M_Axi_Araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
a_M_Axi_Arprot : out std_logic_vector(2 downto 0);
a_M_Axi_Arvalid : out std_logic;
a_M_Axi_Arready : in std_logic;
a_M_Axi_Rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
a_M_Axi_Rresp : in std_logic_vector(1 downto 0);
a_M_Axi_Rvalid : in std_logic;
a_M_Axi_Rready : out std_logic;
--AXI Stream interface taht enables the DMA to write/read to/from the Context Memory
a_S_Axis_MM2S_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_S_Axis_MM2S_Tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a_S_Axis_MM2S_Tvalid : IN STD_LOGIC;
a_S_Axis_MM2S_Tready : OUT STD_LOGIC;
a_S_Axis_MM2S_Tlast : IN STD_LOGIC;
a_M_Axis_S2MM_Tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_M_Axis_S2MM_Tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a_M_Axis_S2MM_Tvalid : OUT STD_LOGIC;
a_M_Axis_S2MM_Tready : IN STD_LOGIC;
a_M_Axis_S2MM_Tlast : OUT STD_LOGIC;
--Command FIFO; used to keep track of received OUT transactions
RX_COMMAND_FIFO_RD_EN : OUT std_logic;
RX_COMMAND_FIFO_DOUT : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
RX_COMMAND_FIFO_EMPTY : IN std_logic;
RX_COMMAND_FIFO_VALID : IN std_logic;
--FIFO control signals
arb_tx_fifo_s_aresetn : OUT std_logic;
--multiplex between FIFO access and Context memory access
a_Axis_MM2S_Mux_Ctrl : OUT STD_LOGIC;
a_Axis_S2MM_Mux_Ctrl : OUT STD_LOGIC;
--Protocol_Engine interface
a_Send_Zero_Length_Packet_Set : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Set_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Clear_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --Setup packets are stored in these registers before being copied into the dQH
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --Setup packets are stored in these registers before being copied into the dQH
a_In_Packet_Complete_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --a bit is set when the corresponding endpoint has completed an IN transaction
a_In_Packet_Complete_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --In_Packet_Complete Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Packet_Complete_Clear_En : OUT STD_LOGIC; --In_Packet_Complete Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Token_Received_Rd : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- a bit is set when the corresponding endpoint has received an IN token
a_In_Token_Received_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --In_Token_Received_Clear Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Token_Received_Clear_En : OUT STD_LOGIC; --In_Token_Received_Clear Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Cnt_Bytes_Sent : in std_logic_vector(12 downto 0); --number of bytes sent in response to an IN token
a_Cnt_Bytes_Sent_oValid : IN std_logic;
a_Resend : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --indicates that the endpoint corresponding to set bits need to resend a packet
a_Resend_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --Resend Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Resend_Clear_En : OUT STD_LOGIC; --Resend Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Pe_Endpt_Nr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the lower layers (ULPI, Packet_Decoder)
a_Arb_Endpt_Nr : OUT std_logic_vector(4 downto 0); --endpoint accessed by the DMA_Transfer_Manager
--Control_Registers interface
a_USBSTS_Wr_UI : OUT std_logic;
a_USBSTS_Wr_en_UI : OUT std_logic;
a_USBMODE_Rd : in std_logic_vector(31 downto 0);
a_USBCMD_SUTW_Wr : out std_logic;
a_USBCMD_SUTW_Wr_En : out std_logic;
a_USBCMD_ATDTW_Wr : out std_logic;
a_USBCMD_ATDTW_Wr_En : out std_logic;
a_EMDPTFLUSH_Rd : in std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set : out std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set_En : out std_logic;
a_ENDPTPRIME_Rd : in std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear_En : out std_logic;
a_ENDPTPRIME_Set : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Set_En : out std_logic;
a_ENDPTSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr_En : out std_logic;
a_ENDPTSETUPSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTSETUPSTAT_Wr_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Rd : in std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear : out std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Ack : in std_logic;
a_ENDPOINTLISTADDR_Rd : in std_logic_vector(31 downto 0)
);
end DMA_Transfer_Manager;
architecture implementation of DMA_Transfer_Manager is
COMPONENT DMA_Operations
PORT(
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0);
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0);
M_AXI_AWREADY : IN std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BRESP : IN std_logic_vector(1 downto 0);
M_AXI_BVALID : IN std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RDATA : IN std_logic_vector(31 downto 0);
M_AXI_RRESP : IN std_logic_vector(1 downto 0);
M_AXI_RVALID : IN std_logic;
M_AXI_AWADDR : OUT std_logic_vector(9 downto 0);
M_AXI_AWPROT : OUT std_logic_vector(2 downto 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_WDATA : OUT std_logic_vector(31 downto 0);
M_AXI_WSTRB : OUT std_logic_vector(3 downto 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_BREADY : OUT std_logic;
M_AXI_ARADDR : OUT std_logic_vector(9 downto 0);
M_AXI_ARPROT : OUT std_logic_vector(2 downto 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_RREADY : OUT std_logic;
dma_transfer_complete : OUT std_logic;
start_dma_s2mm : IN std_logic;
start_dma_mm2s : IN std_logic;
dma_transfer_length : in STD_LOGIC_VECTOR(31 downto 0);
dma_source_dest_address : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Context
PORT(
CLK : IN std_logic;
RESETN : IN std_logic;
ENDPT_NR : in integer range 0 to 22;
-- ENDPT_NR_PD : in integer range 0 to 22;
RD_EN : IN std_logic;
WR_EN : IN std_logic;
dTD_TOTAL_BYTES_WR_EN : IN std_logic;
dTD_STATUS_WR_EN : IN std_logic;
dQH_CURRENT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_NEXT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_SETUP_BUFFER_wr_EN : in STD_LOGIC;
dQH_MULT_wr : IN std_logic_vector(1 downto 0);
dQH_ZLT_wr : IN std_logic;
dQH_MAX_PACKET_LENGTH_wr : IN std_logic_vector(10 downto 0);
dQH_IOS_wr : IN std_logic;
dQH_CURRENT_dTD_POINTER_wr : IN std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_wr : IN std_logic_vector(26 downto 0);
dQH_T_wr : IN std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_wr : IN std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : IN std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_wr : IN std_logic_vector(14 downto 0);
dTD_IOC_wr : IN std_logic;
dTD_C_PAGE_wr : IN std_logic_vector(2 downto 0);
dTD_MULT_wr : IN std_logic_vector(1 downto 0);
dTD_STATUS_wr : IN std_logic_vector(7 downto 0);
dTD_PAGE0_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE1_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE2_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE3_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE4_wr : IN std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_wr : IN std_logic_vector(11 downto 0);
dQH_MULT_rd : OUT std_logic_vector(1 downto 0);
dQH_ZLT_rd : OUT std_logic;
-- pe_dQH_ZLT_rd : OUT STD_LOGIC;
dQH_MAX_PACKET_LENGTH_rd : OUT std_logic_vector(10 downto 0);
dQH_IOS_rd : OUT std_logic;
dQH_CURRENT_dTD_POINTER_rd : OUT std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_rd : OUT std_logic_vector(26 downto 0);
dQH_T_rd : OUT std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_rd : OUT std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : OUT std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_rd : OUT std_logic_vector(14 downto 0);
dTD_IOC_rd : OUT std_logic;
dTD_C_PAGE_rd : OUT std_logic_vector(2 downto 0);
dTD_MULT_rd : OUT std_logic_vector(1 downto 0);
dTD_STATUS_rd : OUT std_logic_vector(7 downto 0);
dTD_PAGE0_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE1_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE2_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE3_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE4_rd : OUT std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_rd : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT Context_to_Stream
PORT(
CLK : IN std_logic;
RESETN : IN std_logic;
ind_statte_axistream : out std_logic_vector(4 downto 0);
dQH_RD : IN std_logic;
dQH_WR : IN std_logic;
dTD_RD : IN std_logic;
dTD_WR : IN std_logic;
SETUP_WR : IN STD_LOGIC;
dQH_WR_EN : out STD_LOGIC;
s_axis_mm2s_tdata : IN std_logic_vector(31 downto 0);
s_axis_mm2s_tkeep : IN std_logic_vector(3 downto 0);
s_axis_mm2s_tvalid : IN std_logic;
s_axis_mm2s_tlast : IN std_logic;
m_axis_s2mm_tready : IN std_logic;
dQH_MULT_rd : IN std_logic_vector(1 downto 0);
dQH_ZLT_rd : IN std_logic;
dQH_MAX_PACKET_LENGTH_rd : IN std_logic_vector(10 downto 0);
dQH_IOS_rd : IN std_logic;
dQH_CURRENT_dTD_POINTER_rd : IN std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_rd : IN std_logic_vector(26 downto 0);
dQH_T_rd : IN std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_rd : IN std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : IN std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_rd : IN std_logic_vector(14 downto 0);
dTD_IOC_rd : IN std_logic;
dTD_C_PAGE_rd : IN std_logic_vector(2 downto 0);
dTD_MULT_rd : IN std_logic_vector(1 downto 0);
dTD_STATUS_rd : IN std_logic_vector(7 downto 0);
dTD_PAGE0_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE1_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE2_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE3_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE4_rd : IN std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_rd : IN std_logic_vector(11 downto 0);
s_axis_mm2s_tready : OUT std_logic;
m_axis_s2mm_tdata : OUT std_logic_vector(31 downto 0);
m_axis_s2mm_tkeep : OUT std_logic_vector(3 downto 0);
m_axis_s2mm_tvalid : OUT std_logic;
m_axis_s2mm_tlast : OUT std_logic;
dQH_MULT_wr : OUT std_logic_vector(1 downto 0);
dQH_ZLT_wr : OUT std_logic;
dQH_MAX_PACKET_LENGTH_wr : OUT std_logic_vector(10 downto 0);
dQH_IOS_wr : OUT std_logic;
dQH_CURRENT_dTD_POINTER_wr : OUT std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_wr : OUT std_logic_vector(26 downto 0);
dQH_T_wr : OUT std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_wr : OUT std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : OUT std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_wr : OUT std_logic_vector(14 downto 0);
dTD_IOC_wr : OUT std_logic;
dTD_C_PAGE_wr : OUT std_logic_vector(2 downto 0);
dTD_MULT_wr : OUT std_logic_vector(1 downto 0);
dTD_STATUS_wr : OUT std_logic_vector(7 downto 0);
dTD_PAGE0_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE1_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE2_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE3_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE4_wr : OUT std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_wr : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
constant ATDTW : integer := 14;
constant SUTW : integer := 13;
constant SLOM : integer := 3;
type state_type is (IDLE, PRIME_MM2S_DQH, PRIME_WAIT0, PRIME_MM2S_DTD, PRIME_WAIT1, PRIME_WAIT2, PRIME_FILL_FIFO, PRIME_FILL_FIFO_1, IN_HANDSHAKE, PRIME_FILL_FIFO_2, SETUP_LOCKOUT_TRIPWIRE, SETUP_UPDATE_SETUP_BYTES, SETUP_WAIT1, SETUP_S2MM, SETUP_UPDATE_ENDPTSETUP_RECEIVED, SETUP_WAIT2, START_OUT_FRAMEWORK, OUT_START_TRANSFER, OUT_TRANSFER_S2MM, OUT_WAIT1, OUT_CHECK_COMPLETE, OUT_TRANSFER_COMPLETE, OUT_FETCH_NEXT_DTD, OUT_WAIT2,START_IN_FRAMEWORK, IN_TRANSFER_MM2S, IN_RELOAD_BUFFER, IN_WAIT0, IN_WAIT1, IN_CHECK_COMPLETE, IN_TRANSACTION_COMPLETE, IN_FETCH_NEXT_DTD, IN_WAIT2);
signal state, next_state : state_type;
type DMA_CURRENT_TRANSFER_ADDRESS is array (11 downto 0) of std_logic_vector(31 downto 0);
signal a_DMA_Current_Transfer_Addr_Array, a_DMA_Current_Transfer_Addr_Array_q : DMA_CURRENT_TRANSFER_ADDRESS;
signal a_Context_Mux_Ctrl : std_logic;
signal a_Read_dQH : std_logic;
signal a_Read_dQH_Fsm : std_logic;
signal a_Read_dQH_q : std_logic;
signal a_Write_dQH : std_logic;
signal a_Write_dQH_Fsm : std_logic;
signal a_Write_dQH_q : std_logic;
signal a_Read_dTD : std_logic;
signal a_Read_dTD_Fsm : std_logic;
signal a_Read_dTD_q : std_logic;
signal write_dTD : std_logic;
signal a_Write_Setup_Bytes, a_Write_Setup_Bytes_q, a_Write_Setup_Bytes_FSM : std_logic;
signal a_dQH_Wr_En_Mux_Stream : std_logic;
signal a_dQH_Wr_En_Mux_Out : std_logic;
signal a_dQH_Wr_En_Mux_Arb : std_logic;
signal a_Start_DMA_S2MM : std_logic;
signal a_Start_DMA_MM2S : std_logic;
signal a_DMA_Source_Dest_Addr : std_logic_vector(31 downto 0);
signal a_DMA_Transfer_Length : std_logic_vector(31 downto 0);
signal a_DMA_Current_Transfer_Addr_Fsm : std_logic_vector (31 downto 0);
signal a_DMA_Current_Transfer_Addr_Le : std_logic;
signal a_DMA_Transfer_Complete : STD_LOGIC;
signal a_Aux_Addr_Register : std_logic_vector (31 downto 0);
signal a_DMA_In_Transfer_Length : std_logic_vector (31 downto 0);
signal a_DMA_In_Transfer_Length_Le : std_logic;
signal a_Axis_MM2S_Mux_Ctrl_Fsm , a_Axis_S2MM_Mux_Ctrl_Fsm : STD_LOGIC;
signal a_Arb_dQH_MULT_Wr : STD_LOGIC_VECTOR (1 downto 0); --not used
signal a_Arb_dQH_ZLT_Wr : STD_LOGIC; --not used
signal a_Arb_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0); --not used
signal a_Arb_dQH_IOS_Wr : STD_LOGIC; --not used
signal a_Arb_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Arb_dQH_Current_dTD_Pointer_Wr_En : STD_LOGIC;
signal a_Arb_dQH_Next_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0); --not used
signal a_Arb_dQH_Next_dTD_Pointer_Wr_En : STD_LOGIC; --not used
signal a_Arb_dQH_T_Wr : STD_LOGIC; --not used
signal a_Arb_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_Arb_dTD_Total_Bytes_Wr_En : STD_LOGIC;
signal a_Arb_dTD_IOC_Wr : STD_LOGIC; --not used
signal a_Arb_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0); --not used
signal a_Arb_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0); --not used
signal a_Arb_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0); --not used
signal a_Arb_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page4_wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0); --not used
signal a_Stream_dQH_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_Stream_dQH_Zlt_Wr : STD_LOGIC;
signal a_Stream_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0);
signal a_Stream_dQH_IOS_Wr : STD_LOGIC;
signal a_Stream_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Stream_dQH_Next_dTD_Pointer_wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Stream_dQH_T_Wr : STD_LOGIC;
signal a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_Stream_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_Stream_dTD_IOC_Wr : STD_LOGIC;
signal a_Stream_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0);
signal a_Stream_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_Stream_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0);
signal a_Stream_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page4_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0);
signal a_dQH_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_dQH_ZLT_Wr : STD_LOGIC;
signal a_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0);
signal a_dQH_IOS_Wr : STD_LOGIC;
signal a_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_Next_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_T_Wr : STD_LOGIC;
signal a_dQH_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_dQH_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_dTD_IOC_Wr : STD_LOGIC;
signal a_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0);
signal a_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0);
signal a_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page4_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0);
signal a_dQH_Setup_Buffer_Wr_En : std_logic;
signal a_dTD_Status_Wr_En : STD_LOGIC;
signal a_dQH_MULT_Rd : STD_LOGIC_VECTOR (1 downto 0);
signal a_dQH_ZLT_Rd : STD_LOGIC;
signal a_dQH_Max_Packet_Length_Rd : STD_LOGIC_VECTOR (10 downto 0);
signal a_dQH_IOS_Rd : STD_LOGIC;
signal a_dQH_Current_dTD_Pointer_Rd : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_Next_dTD_Pointer_Rd : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_T_Rd : STD_LOGIC;
signal a_dQH_Setup_Buffer_Bytes_3_0_Rd : STD_LOGIC_VECTOR (31 downto 0);
signal a_dQH_Setup_Buffer_Bytes_7_4_Rd : STD_LOGIC_VECTOR (31 downto 0);
signal a_dTD_Total_Bytes_Rd : STD_LOGIC_VECTOR (14 downto 0);
signal a_dTD_IOC_Rd : STD_LOGIC;
signal a_dTD_C_Page_Rd : STD_LOGIC_VECTOR (2 downto 0);
signal a_dTD_Mult_Rd : STD_LOGIC_VECTOR (1 downto 0);
signal a_dTD_Status_Rd : STD_LOGIC_VECTOR (7 downto 0);
signal a_dTD_Page0_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page1_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page2_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page3_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page4_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Current_Offset_Rd : STD_LOGIC_VECTOR (11 downto 0);
signal a_Out_Transfer_Byte_Count_Le1 : STD_LOGIC;
signal a_Out_Transfer_Byte_Count_Le2 : STD_LOGIC;
signal a_Out_Transfer_Byte_Count : std_logic_vector (12 downto 0);
signal a_Endpointlistaddr_Loc : std_logic_vector(20 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En_Fsm : std_logic;
signal a_ENDPTSETUPSTAT_Wr_Fsm : std_logic_vector(31 downto 0);
signal a_USBSTS_Wr_UI_Fsm : std_logic;
signal a_USBSTS_Wr_En_UI_Fsm : std_logic;
signal a_ENDPTSTAT_Set : std_logic_vector(31 downto 0);
signal a_ENDPTSTAT_Set_En : std_logic;
signal a_ENDPTSTAT_clear : std_logic_vector(31 downto 0);
signal a_ENDPTSTAT_Clear_En : std_logic;
signal a_ENDPTSTAT_Wr_Loc : std_logic_vector(31 downto 0);
signal tx_fifo_resetn : std_logic;
signal a_Prime : STD_LOGIC;
signal a_Setup_Received : STD_LOGIC;
signal a_In_Token_Received : STD_LOGIC;
signal a_Endpt_Nr_Int : integer range 0 to 23;
signal a_Endpt_Nr_Fsm : integer range 0 to 23;
signal a_Endpt_Nr_Le : STD_LOGIC;
signal a_Endpt_Nr : std_logic_vector(4 downto 0);
signal a_Endpt_Nr_4b : integer range 0 to 27;
signal a_Endpt_Nr_Prime : integer range 0 to 23;
signal a_Endpt_Nr_Setup : integer range 0 to 23;
signal a_Endpt_Nr_In_Token : integer range 0 to 23;
signal a_Endpt_In_Out : STD_LOGIC;
signal a_Bit_Index : integer range 0 to 27;
signal a_Cnt_Bytes_Sent_Loc : std_logic_vector (12 downto 0);
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of state_ind_arb : signal is "true";
-- attribute keep of state_ind_arb : signal is "true";
-- attribute mark_debug of a_ENDPTCOMPLETE_Wr_En : signal is "true";
-- attribute keep of a_ENDPTCOMPLETE_Wr_En : signal is "true";
-- attribute mark_debug of a_ENDPTCOMPLETE_Wr : signal is "true";
-- attribute keep of a_ENDPTCOMPLETE_Wr : signal is "true";
-- attribute mark_debug of a_Setup_Received : signal is "true";
-- attribute keep of a_Setup_Received : signal is "true";
-- attribute mark_debug of a_Cnt_Bytes_Sent_Loc : signal is "true";
-- attribute keep of a_Cnt_Bytes_Sent_Loc : signal is "true";
-- attribute mark_debug of a_In_Packet_Complete_Rd : signal is "true";
-- attribute keep of a_In_Packet_Complete_Rd : signal is "true";
-- attribute mark_debug of a_In_Token_Received : signal is "true";
-- attribute keep of a_In_Token_Received : signal is "true";
-- attribute mark_debug of a_Arb_ENDPTSETUP_RECEIVED_Rd : signal is "true";
-- attribute keep of a_Arb_ENDPTSETUP_RECEIVED_Rd : signal is "true";
-- attribute mark_debug of a_Bit_Index : signal is "true";
-- attribute keep of a_Bit_Index : signal is "true";
-- attribute mark_debug of a_Endpt_Nr_Prime : signal is "true";
-- attribute keep of a_Endpt_Nr_Prime : signal is "true";
-- attribute mark_debug of a_Endpt_Nr : signal is "true";
-- attribute keep of a_Endpt_Nr : signal is "true";
-- attribute mark_debug of a_Endpt_In_Out : signal is "true";
-- attribute keep of a_Endpt_In_Out : signal is "true";
-- attribute mark_debug of a_In_Token_Received_Rd : signal is "true";
-- attribute keep of a_In_Token_Received_Rd : signal is "true";
-- attribute mark_debug of a_dTD_Total_Bytes_Rd : signal is "true";
-- attribute keep of a_dTD_Total_Bytes_Rd : signal is "true";
-- attribute mark_debug of a_Prime : signal is "true";
-- attribute keep of a_Prime : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Wr_Loc : signal is "true";
-- attribute keep of a_ENDPTSTAT_Wr_Loc : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Set_En : signal is "true";
-- attribute keep of a_ENDPTSTAT_Set_En : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Set : signal is "true";
-- attribute keep of a_ENDPTSTAT_Set : signal is "true";
-- attribute mark_debug of a_EMDPTFLUSH_Rd : signal is "true";
-- attribute keep of a_EMDPTFLUSH_Rd : signal is "true";
-- attribute mark_debug of a_Endpt_Nr_Int : signal is "true";
-- attribute keep of a_Endpt_Nr_Int : signal is "true";
begin
a_Aux_Addr_Register <= a_dTD_Page0_Rd & a_dTD_Current_Offset_Rd;
arb_tx_fifo_s_aresetn <= tx_fifo_resetn;
a_Axis_MM2S_Mux_Ctrl <= a_Axis_MM2S_Mux_Ctrl_Fsm;
a_Axis_S2MM_Mux_Ctrl <= a_Axis_S2MM_Mux_Ctrl_Fsm;
a_Endpointlistaddr_Loc <= a_ENDPOINTLISTADDR_Rd(31 downto 11);
-- This module is responsible with implementing the S2MM and MM2S frameworks for the DMA engine
Inst_DMA_Operations: DMA_Operations PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
state_ind_dma => state_ind_dma,
DEBUG_REG_DATA => DEBUG_REG_DATA,
M_AXI_AWADDR => a_M_Axi_Awaddr,
M_AXI_AWPROT => a_M_Axi_Awprot,
M_AXI_AWVALID => a_M_Axi_Awvalid,
M_AXI_AWREADY => a_M_Axi_Awready,
M_AXI_WDATA => a_M_Axi_Wdata,
M_AXI_WSTRB => a_M_Axi_Wstrb,
M_AXI_WVALID => a_M_Axi_Wvalid,
M_AXI_WREADY => a_M_Axi_Wready,
M_AXI_BRESP => a_M_Axi_Bresp,
M_AXI_BVALID => a_M_Axi_Bvalid,
M_AXI_BREADY => a_M_Axi_Bready,
M_AXI_ARADDR => a_M_Axi_Araddr,
M_AXI_ARPROT => a_M_Axi_Arprot,
M_AXI_ARVALID => a_M_Axi_Arvalid,
M_AXI_ARREADY => a_M_Axi_Arready,
M_AXI_RDATA => a_M_Axi_Rdata,
M_AXI_RRESP => a_M_Axi_Rresp,
M_AXI_RVALID => a_M_Axi_Rvalid,
M_AXI_RREADY => a_M_Axi_Rready,
dma_transfer_complete => a_DMA_Transfer_Complete,
start_dma_s2mm => a_Start_DMA_S2MM,
start_dma_mm2s => a_Start_DMA_MM2S,
dma_source_dest_address => a_DMA_Source_Dest_Addr,
dma_transfer_length => a_DMA_Transfer_Length
);
-- This module implements the context memory (Queue Heads, Transfer Descriptors)
Inst_Context: Context PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
ENDPT_NR => a_Endpt_Nr_Int,
RD_EN => '0',
WR_EN => a_dQH_Wr_En_Mux_Out,
dQH_CURRENT_dTD_POINTER_wr_EN => a_Arb_dQH_Current_dTD_Pointer_Wr_En,
dQH_NEXT_dTD_POINTER_wr_en => a_Arb_dQH_Next_dTD_Pointer_Wr_En,
dTD_TOTAL_BYTES_WR_EN => a_Arb_dTD_Total_Bytes_Wr_En,
dTD_STATUS_WR_EN => a_dTD_Status_Wr_En,
dQH_SETUP_BUFFER_wr_EN => a_dQH_Setup_Buffer_Wr_En,
dQH_MULT_rd => a_dQH_MULT_Rd,
dQH_ZLT_rd => a_dQH_ZLT_Rd,
dQH_MAX_PACKET_LENGTH_rd => a_dQH_Max_Packet_Length_Rd,
dQH_IOS_rd => a_dQH_IOS_Rd,
dQH_CURRENT_dTD_POINTER_rd => a_dQH_Current_dTD_Pointer_Rd,
dQH_NEXT_dTD_POINTER_rd => a_dQH_Next_dTD_Pointer_Rd,
dQH_T_rd => a_dQH_T_Rd,
dQH_SETUP_BUFFER_BYTES_3_0_rd => a_dQH_Setup_Buffer_Bytes_3_0_Rd,
dQH_SETUP_BUFFER_BYTES_7_4_rd => a_dQH_Setup_Buffer_Bytes_7_4_Rd,
dTD_TOTAL_BYTES_rd => a_dTD_Total_Bytes_Rd,
dTD_IOC_rd => a_dTD_IOC_Rd,
dTD_C_PAGE_rd => a_dTD_C_Page_Rd,
dTD_MULT_rd => a_dTD_Mult_Rd,
dTD_STATUS_rd => a_dTD_Status_Rd,
dTD_PAGE0_rd => a_dTD_Page0_Rd ,
dTD_PAGE1_rd => a_dTD_Page1_Rd,
dTD_PAGE2_rd => a_dTD_Page2_Rd,
dTD_PAGE3_rd => a_dTD_Page3_Rd,
dTD_PAGE4_rd => a_dTD_Page4_Rd,
dTD_CURRENT_OFFSET_rd => a_dTD_Current_Offset_Rd,
dQH_MULT_wr => a_dQH_Mult_Wr,
dQH_ZLT_wr => a_dQH_ZLT_Wr,
dQH_MAX_PACKET_LENGTH_wr => a_dQH_Max_Packet_Length_Wr,
dQH_IOS_wr => a_dQH_IOS_Wr,
dQH_CURRENT_dTD_POINTER_wr => a_dQH_Current_dTD_Pointer_Wr,
dQH_NEXT_dTD_POINTER_wr => a_dQH_Next_dTD_Pointer_Wr,
dQH_T_wr => a_dQH_T_Wr,
dQH_SETUP_BUFFER_BYTES_3_0_wr => a_dQH_Setup_Buffer_Bytes_3_0_Wr,
dQH_SETUP_BUFFER_BYTES_7_4_wr => a_dQH_Setup_Buffer_Bytes_7_4_Wr,
dTD_TOTAL_BYTES_wr => a_dTD_Total_Bytes_Wr,
dTD_IOC_wr => a_dTD_IOC_Wr,
dTD_C_PAGE_wr => a_dTD_C_Page_Wr,
dTD_MULT_wr => a_dTD_Mult_Wr,
dTD_STATUS_wr => a_dTD_Status_Wr,
dTD_PAGE0_wr => a_dTD_Page0_Wr,
dTD_PAGE1_wr => a_dTD_Page1_Wr,
dTD_PAGE2_wr => a_dTD_Page2_Wr,
dTD_PAGE3_wr => a_dTD_Page3_Wr,
dTD_PAGE4_wr => a_dTD_Page4_Wr,
dTD_CURRENT_OFFSET_wr => a_dTD_Current_Offset_Wr
);
-- This module handles control data transfers (Setup packets, dTD, dQH, Status) through the DMA module
Inst_Context_to_Stream: Context_to_Stream PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
ind_statte_axistream => ind_statte_axistream,
dQH_RD => a_Read_dQH,
dQH_WR => a_Write_dQH,
dTD_RD => a_Read_dTD,
dTD_WR => write_dTD,
SETUP_WR => a_Write_Setup_Bytes,
dQH_WR_EN => a_dQH_Wr_En_Mux_Stream,
s_axis_mm2s_tdata => a_S_Axis_MM2S_Tdata,
s_axis_mm2s_tkeep => a_S_Axis_MM2S_Tkeep,
s_axis_mm2s_tvalid => a_S_Axis_MM2S_Tvalid,
s_axis_mm2s_tready => a_S_Axis_MM2S_Tready,
s_axis_mm2s_tlast => a_S_Axis_MM2S_Tlast,
m_axis_s2mm_tdata => a_M_Axis_S2MM_Tdata,
m_axis_s2mm_tkeep => a_M_Axis_S2MM_Tkeep,
m_axis_s2mm_tvalid => a_M_Axis_S2MM_Tvalid,
m_axis_s2mm_tready => a_M_Axis_S2MM_Tready,
m_axis_s2mm_tlast => a_M_Axis_S2MM_Tlast,
dQH_MULT_rd => a_dQH_MULT_Rd,
dQH_ZLT_rd => a_dQH_ZLT_Rd,
dQH_MAX_PACKET_LENGTH_rd => a_dQH_Max_Packet_Length_Rd,
dQH_IOS_rd => a_dQH_IOS_Rd,
dQH_CURRENT_dTD_POINTER_rd => a_dQH_Current_dTD_Pointer_Rd,
dQH_NEXT_dTD_POINTER_rd => a_dQH_Next_dTD_Pointer_Rd,
dQH_T_rd => a_dQH_T_Rd,
dQH_SETUP_BUFFER_BYTES_3_0_rd => a_dQH_Setup_Buffer_Bytes_3_0_Rd,
dQH_SETUP_BUFFER_BYTES_7_4_rd => a_dQH_Setup_Buffer_Bytes_7_4_Rd,
dTD_TOTAL_BYTES_rd => a_dTD_Total_Bytes_Rd,
dTD_IOC_rd => a_dTD_IOC_Rd,
dTD_C_PAGE_rd => a_dTD_C_Page_Rd,
dTD_MULT_rd => a_dTD_Mult_Rd,
dTD_STATUS_rd => a_dTD_Status_Rd,
dTD_PAGE0_rd => a_dTD_Page0_Rd,
dTD_PAGE1_rd => a_dTD_Page1_Rd,
dTD_PAGE2_rd => a_dTD_Page2_Rd,
dTD_PAGE3_rd => a_dTD_Page3_Rd,
dTD_PAGE4_rd => a_dTD_Page4_Rd,
dTD_CURRENT_OFFSET_rd => a_dTD_Current_Offset_Rd,
dQH_MULT_wr => a_Stream_dQH_Mult_Wr,
dQH_ZLT_wr => a_Stream_dQH_Zlt_Wr,
dQH_MAX_PACKET_LENGTH_wr => a_Stream_dQH_Max_Packet_Length_Wr,
dQH_IOS_wr => a_Stream_dQH_IOS_Wr,
dQH_CURRENT_dTD_POINTER_wr => a_Stream_dQH_Current_dTD_Pointer_Wr,
dQH_NEXT_dTD_POINTER_wr => a_Stream_dQH_Next_dTD_Pointer_wr,
dQH_T_wr => a_Stream_dQH_T_Wr,
dQH_SETUP_BUFFER_BYTES_3_0_wr => a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr,
dQH_SETUP_BUFFER_BYTES_7_4_wr => a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr,
dTD_TOTAL_BYTES_wr => a_Stream_dTD_Total_Bytes_Wr,
dTD_IOC_wr => a_Stream_dTD_IOC_Wr,
dTD_C_PAGE_wr => a_Stream_dTD_C_Page_Wr,
dTD_MULT_wr => a_Stream_dTD_Mult_Wr,
dTD_STATUS_wr => a_Stream_dTD_Status_Wr,
dTD_PAGE0_wr => a_Stream_dTD_Page0_Wr,
dTD_PAGE1_wr => a_Stream_dTD_Page1_Wr,
dTD_PAGE2_wr => a_Stream_dTD_Page2_Wr,
dTD_PAGE3_wr => a_Stream_dTD_Page3_Wr,
dTD_PAGE4_wr => a_Stream_dTD_Page4_Wr,
dTD_CURRENT_OFFSET_wr => a_Stream_dTD_Current_Offset_Wr
);
--Both DMA Engine and the DMA_Transfer_MAnager can read/write to the context memory. The MUX is implemented below
--DMA_Transfer_MAnager controls this MUX
a_dQH_Mult_Wr <= a_Stream_dQH_Mult_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_MULT_Wr ;
a_dQH_ZLT_Wr <= a_Stream_dQH_Zlt_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_ZLT_Wr;
a_dQH_Max_Packet_Length_Wr <= a_Stream_dQH_Max_Packet_Length_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Max_Packet_Length_Wr;
a_dQH_IOS_Wr <= a_Stream_dQH_IOS_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_IOS_Wr;
a_dQH_Current_dTD_Pointer_Wr <= a_Stream_dQH_Current_dTD_Pointer_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Current_dTD_Pointer_Wr;
a_dQH_Next_dTD_Pointer_Wr <= a_Stream_dQH_Next_dTD_Pointer_wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Next_dTD_Pointer_Wr;
a_dQH_T_Wr <= a_Stream_dQH_T_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_T_Wr;
a_dQH_Setup_Buffer_Bytes_3_0_Wr <= a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr;
a_dQH_Setup_Buffer_Bytes_7_4_Wr <= a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr;
a_dTD_Total_Bytes_Wr <= a_Stream_dTD_Total_Bytes_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Total_Bytes_Wr;
a_dTD_IOC_Wr <= a_Stream_dTD_IOC_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_IOC_Wr;
a_dTD_C_Page_Wr <= a_Stream_dTD_C_Page_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_C_Page_Wr;
a_dTD_Mult_Wr <= a_Stream_dTD_Mult_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Mult_Wr;
a_dTD_Status_Wr <= a_Stream_dTD_Status_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Status_Wr;
a_dTD_Page0_Wr <= a_Stream_dTD_Page0_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page0_Wr;
a_dTD_Page1_Wr <= a_Stream_dTD_Page1_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page1_Wr;
a_dTD_Page2_Wr <= a_Stream_dTD_Page2_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page2_Wr;
a_dTD_Page3_Wr <= a_Stream_dTD_Page3_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page3_Wr;
a_dTD_Page4_Wr <= a_Stream_dTD_Page4_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page4_wr;
a_dTD_Current_Offset_Wr <= a_Stream_dTD_Current_Offset_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Current_Offset_Wr;
a_dQH_Wr_En_Mux_Out <= a_dQH_Wr_En_Mux_Stream when (a_Context_Mux_Ctrl = '0') else
a_dQH_Wr_En_Mux_Arb;
--Generate control signals for Context_to_Stream module. Control signals
--must be pulses
IMPULSE_WRITE_DQH: process (Axi_Clk, a_Write_dQH_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Write_dQH <= '0';
a_Write_dQH_q <= '0';
else
a_Write_dQH_q <= a_Write_dQH_Fsm;
a_Write_dQH <= a_Write_dQH_Fsm and (not a_Write_dQH_q);
end if;
end if;
end process;
IMPULSE_WRITE_SETUP: process (Axi_Clk, a_Write_Setup_Bytes_FSM)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Write_Setup_Bytes <= '0';
a_Write_Setup_Bytes_q <= '0';
else
a_Write_Setup_Bytes_q <= a_Write_Setup_Bytes_FSM;
a_Write_Setup_Bytes <= a_Write_Setup_Bytes_FSM and (not a_Write_Setup_Bytes_q);
end if;
end if;
end process;
IMPULSE_READ_DQH: process (Axi_Clk, a_Read_dQH_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Read_dQH <= '0';
a_Read_dQH_q <= '0';
else
a_Read_dQH_q <= a_Read_dQH_Fsm;
a_Read_dQH <= a_Read_dQH_Fsm and (not a_Read_dQH_q);
end if;
end if;
end process;
IMPULSE_READ_DTD_PROC: process (Axi_Clk, a_Read_dTD_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Read_dTD <= '0';
a_Read_dTD_q <= '0';
else
a_Read_dTD_q <= a_Read_dTD_Fsm;
a_Read_dTD <= a_Read_dTD_Fsm and (not a_Read_dTD_q);
end if;
end if;
end process;
--combinational signals generated by the state machine are registered
REGISTER_Q_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_ENDPTSETUPSTAT_Wr_En <= '0';
a_ENDPTSETUPSTAT_Wr <= (others => '0');
a_USBSTS_Wr_UI <= '0';
a_USBSTS_Wr_en_UI <= '0';
else
a_ENDPTSETUPSTAT_Wr_En <= a_ENDPTSETUPSTAT_Wr_En_Fsm;
a_ENDPTSETUPSTAT_Wr <= a_ENDPTSETUPSTAT_Wr_Fsm;
a_USBSTS_Wr_UI <= a_USBSTS_Wr_UI_Fsm;
a_USBSTS_Wr_en_UI <= a_USBSTS_Wr_En_UI_Fsm;
end if;
end if;
end process;
a_ENDPTSTAT_Wr <= a_ENDPTSTAT_Wr_Loc;
--generate the ENDPTSTAT register
ENDPTSTAT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_ENDPTSTAT_Wr_Loc <= (others => '0');
elsif (a_ENDPTSTAT_Set_En = '1') then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc or a_ENDPTSTAT_Set;
elsif (a_ENDPTSTAT_Clear_En = '1') then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc and a_ENDPTSTAT_clear;
elsif (a_EMDPTFLUSH_Rd /= "00000000000000000000000000000000") then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc and (not(a_EMDPTFLUSH_Rd));
end if;
end if;
end process;
a_Cnt_Bytes_Sent_Loc <= a_Cnt_Bytes_Sent;
-- a_Arb_Endpt_Nr is the endpoint the DMA_Transfer_Manager work on in integer format
ENDPT_NR_INT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Int <= 0;
elsif (a_Endpt_Nr_Le = '1') then
a_Endpt_Nr_Int <= a_Endpt_Nr_Fsm;
end if;
end if;
end process;
a_Endpt_Nr <= std_logic_vector(to_unsigned(a_Endpt_Nr_Int,5));
-- a_Arb_Endpt_Nr is the endpoint the DMA_Transfer_Manager work on. Lower layers need to be aware of this
ARB_ENDPT_NR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Arb_Endpt_Nr <= (others => '0');
else
a_Arb_Endpt_Nr <= a_Endpt_Nr;
end if;
end if;
end process;
--determin the endpoint type
DET_ENDPTTYPE: process (Axi_Resetn, a_Endpt_Nr)
begin
if (a_Endpt_Nr(0) = '0') then
a_Endpt_In_Out <= '0';
else
a_Endpt_In_Out <= '1';
end if;
end process;
a_Endpt_Nr_4b <= to_integer(unsigned(a_Endpt_Nr(4 downto 1)));
-- Control registers usually have bits [27:16] referring to IN endpoints asnd bits[11:0] referring to OUT endpoint
DET_INDEX: process (Axi_Resetn, a_Endpt_Nr_4b, a_Endpt_In_Out)
begin
if (a_Endpt_In_Out = '0') then
a_Bit_Index <= a_Endpt_Nr_4b;
else
a_Bit_Index <= a_Endpt_Nr_4b + 16;
end if;
end process;
-- Determin the endpoint selected for priming from endptprime register
DET_PRIME_ENDPTNR_PROC: process (Axi_Clk, a_ENDPTPRIME_Rd)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Prime <= 0;
a_Prime <= '0';
elsif(a_ENDPTPRIME_Rd /= "00000000000000000000000000000000") then
a_Prime <= '1';
for endptprime_index in 0 to 27 loop
if (endptprime_index < 12) then
if (a_ENDPTPRIME_Rd(endptprime_index) = '1') then
a_Endpt_Nr_Prime <= endptprime_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (endptprime_index >= 16) then
if (a_ENDPTPRIME_Rd(endptprime_index) = '1') then
a_Endpt_Nr_Prime <= (endptprime_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_Prime <= 0;
a_Prime <= '0';
end if;
end if;
end process;
--Determin the endpoint number from setup_received register
DET_SETUP_ENDPTNR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Setup <= 0;
a_Setup_Received <= '0';
elsif(a_Arb_ENDPTSETUP_RECEIVED_Rd /= "00000000000000000000000000000000") then
a_Setup_Received <= '1';
for setup_index in 0 to 27 loop
if (setup_index < 12) then
if (a_Arb_ENDPTSETUP_RECEIVED_Rd(setup_index) = '1') then
a_Endpt_Nr_Setup <= setup_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (setup_index >= 16) then
if (a_Arb_ENDPTSETUP_RECEIVED_Rd(setup_index) = '1') then
a_Endpt_Nr_Setup <= (setup_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_Setup <= 0;
a_Setup_Received <= '0';
end if;
end if;
end process;
--Determin the endpoint number from token_in_received register
DET_TOKEN_IN_ENDPTNR_PROC: process (Axi_Clk, a_In_Token_Received_Rd)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_In_Token <= 0;
a_In_Token_Received <= '0';
elsif((a_In_Token_Received_Rd and a_ENDPTSTAT_Wr_Loc) /= "00000000000000000000000000000000") then
a_In_Token_Received <= '1';
for token_in_index in 0 to 27 loop
if (token_in_index < 12) then
if (a_In_Token_Received_Rd(token_in_index) = '1') then
a_Endpt_Nr_In_Token <= token_in_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (token_in_index >= 16) then
if (a_In_Token_Received_Rd(token_in_index) = '1') then
a_Endpt_Nr_In_Token <= (token_in_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_In_Token <= 0;
a_In_Token_Received <= '0';
end if;
end if;
end process;
OUT_TRANSFER_BYTE_COUNT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Out_Transfer_Byte_Count <= (others => '0');
elsif (a_Out_Transfer_Byte_Count_Le1 = '1') then
a_Out_Transfer_Byte_Count <= RX_COMMAND_FIFO_DOUT(23 downto 11);
elsif (a_Out_Transfer_Byte_Count_Le2 = '1') then
a_Out_Transfer_Byte_Count <= std_logic_vector( to_unsigned((to_integer(unsigned(RX_COMMAND_FIFO_DOUT(23 downto 11))) - to_integer(unsigned(a_dTD_Total_Bytes_Rd))),13) );
end if;
end if;
end process;
DMA_TRANSFER_ADDR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_DMA_Current_Transfer_Addr_Array <= (others =>(others => '0'));
a_DMA_Current_Transfer_Addr_Array_q <= (others =>(others => '0'));
elsif (a_DMA_Current_Transfer_Addr_Le = '1') then
a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b) <= a_DMA_Current_Transfer_Addr_Fsm;
a_DMA_Current_Transfer_Addr_Array_q(a_Endpt_Nr_4b) <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
end if;
end if;
end process;
------------------------------------------------------------------------------------------------------
DECIDE_LENGTH_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_DMA_In_Transfer_Length <= (others => '0');
else
if (a_DMA_In_Transfer_Length_Le = '1') then
if (to_integer(unsigned(a_dTD_Total_Bytes_Rd)) < C_FIFO_SIZE) then
a_DMA_In_Transfer_Length <= "00000000000000000" & a_dTD_Total_Bytes_Rd;
else
a_DMA_In_Transfer_Length <= std_logic_vector(to_unsigned(C_FIFO_SIZE,32));
end if;
end if;
end if;
end if;
end process;
--DMA_Transfer_Manager State Machine
SYNC_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (state, a_dQH_Next_dTD_Pointer_Rd, a_Arb_ENDPTSETUP_RECEIVED_Ack, a_Cnt_Bytes_Sent_oValid, a_Send_Zero_Length_Packet_Ack_Rd, a_DMA_Current_Transfer_Addr_Array, a_Prime, RX_COMMAND_FIFO_VALID, a_dTD_Page0_Rd, a_dTD_Current_Offset_Rd,a_Endpt_Nr_4b, a_Endpt_Nr_Int, a_Aux_Addr_Register, a_In_Packet_Complete_Rd, a_Endpt_Nr_In_Token, RX_COMMAND_FIFO_EMPTY, a_Endpt_Nr_Setup, a_USBMODE_Rd, a_Bit_Index, RX_COMMAND_FIFO_DOUT, a_Out_Transfer_Byte_Count, a_Cnt_Bytes_Sent_Loc, a_dTD_Total_Bytes_Rd, a_dQH_Current_dTD_Pointer_Rd, a_dQH_T_Rd, a_Endpt_Nr_Prime, a_In_Token_Received, a_Endpt_In_Out, a_Setup_Received, a_DMA_Transfer_Complete, a_Endpointlistaddr_Loc)
begin
--declare default state for next_state to avoid latches
next_state <= state;
state_ind_arb <= "000000";
a_Context_Mux_Ctrl <= '0';
a_dQH_Wr_En_Mux_Arb <= '0';
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '0';
a_Arb_dTD_Total_Bytes_Wr_En <= '0';
a_Arb_dQH_Next_dTD_Pointer_Wr_En <= '0';
a_dQH_Setup_Buffer_Wr_En <= '0';
a_dTD_Status_Wr_En <= '0';
a_Read_dQH_Fsm <= '0';
a_Write_dQH_Fsm <= '0';
a_Read_dTD_Fsm <= '0';
write_dTD <= '0';
a_Write_Setup_Bytes_FSM <= '0';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO as a DEFAULT; FIFO connected to DMA only when data ready
a_Axis_S2MM_Mux_Ctrl_Fsm <= '1';
a_Start_DMA_S2MM <= '0';
a_Start_DMA_MM2S <= '0';
a_DMA_Source_Dest_Addr <= (others => '0');
a_DMA_Transfer_Length <= (others => '0');
tx_fifo_resetn <= '1';
a_Endpt_Nr_Fsm <= 0;
a_Endpt_Nr_Le <= '0';
RX_COMMAND_FIFO_RD_EN <= '0';
a_Out_Transfer_Byte_Count_Le1 <= '0';
a_Out_Transfer_Byte_Count_Le2 <= '0';
a_DMA_Current_Transfer_Addr_Fsm <= (others => '0');
a_DMA_Current_Transfer_Addr_Le <= '0';
-- pe_setup_received_rst <= '1';
a_Arb_dQH_MULT_Wr <= (others => '0');
a_Arb_dQH_ZLT_Wr <= '0';
a_Arb_dQH_Max_Packet_Length_Wr <= (others => '0');
a_Arb_dQH_IOS_Wr <= '0';
a_Arb_dQH_Current_dTD_Pointer_Wr <= (others => '0');
a_Arb_dQH_Next_dTD_Pointer_Wr <= (others => '0');
a_Arb_dQH_T_Wr <= '0';
a_Arb_dTD_Total_Bytes_Wr <= (others => '0');
a_Arb_dTD_IOC_Wr <= '0';
a_Arb_dTD_C_Page_Wr <= (others => '0');
a_Arb_dTD_Mult_Wr <= (others => '0');
a_Arb_dTD_Status_Wr <= (others => '0');
a_Arb_dTD_Page0_Wr <= (others => '0');
a_Arb_dTD_Page1_Wr <= (others => '0');
a_Arb_dTD_Page2_Wr <= (others => '0');
a_Arb_dTD_Page3_Wr <= (others => '0');
a_Arb_dTD_Page4_wr <= (others => '0');
a_Arb_dTD_Current_Offset_Wr <= (others => '0');
a_USBSTS_Wr_UI_Fsm <= '0';
a_USBSTS_Wr_En_UI_Fsm <= '0';
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '0';
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '0';
a_ENDPTPRIME_Clear <= (others => '1');
a_ENDPTPRIME_Clear_En <= '0';
a_ENDPTPRIME_Set <= (others => '0');
a_ENDPTPRIME_Set_En <= '0';
a_ENDPTCOMPLETE_Wr <= (others => '0');
a_ENDPTCOMPLETE_Wr_En <= '0';
a_ENDPTSETUPSTAT_Wr_Fsm <= (others => '0');
a_ENDPTSETUPSTAT_Wr_En_Fsm <= '0';
a_Arb_ENDPTSETUP_RECEIVED_Clear <= (others => '1');
a_Arb_ENDPTSETUP_RECEIVED_Clear_En <= '0';
a_ENDPTSTAT_Set <= (others => '0');
a_ENDPTSTAT_Set_En <= '0';
a_ENDPTSTAT_clear <= (others => '1');
a_ENDPTSTAT_Clear_En <= '0';
a_EMDPTFLUSH_Set <= (others => '0');
a_EMDPTFLUSH_Set_En <= '0';
a_In_Packet_Complete_Clear_En <= '0';
a_In_Packet_Complete_Clear <= (others => '1');
a_Send_Zero_Length_Packet_Set <= (others => '0');
a_Send_Zero_Length_Packet_Set_En <= '0';
a_Send_Zero_Length_Packet_Ack_Clear <= (others => '1');
a_Send_Zero_Length_Packet_Ack_Clear_En <= '0';
a_In_Token_Received_Clear <= (others => '1');
a_In_Token_Received_Clear_En <= '0';
a_Resend_Clear_En <= '0';
a_Resend_Clear <= (others => '1');
a_DMA_In_Transfer_Length_Le <= '0';
case state is -- state machine triggered by 2 conditions: priming of an endpoint or setup packet arrival; setup packets processed separately; OUT framework not tested
when IDLE =>
state_ind_arb <= "000000";
if (a_Prime = '1') then
a_Endpt_Nr_Fsm <= a_Endpt_Nr_Prime;
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Endpt_Nr_Le <= '1';
next_state <= PRIME_MM2S_DQH;
elsif (a_Setup_Received = '1') then
a_Context_Mux_Ctrl <= '1';
a_Endpt_Nr_Fsm <= a_Endpt_Nr_Setup;
a_Endpt_Nr_Le <= '1';
next_state <= SETUP_LOCKOUT_TRIPWIRE;
elsif (a_In_Token_Received = '1') then
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Endpt_Nr_Fsm <= a_Endpt_Nr_In_Token;
a_Endpt_Nr_Le <= '1';
next_state <= START_IN_FRAMEWORK;
elsif (RX_COMMAND_FIFO_EMPTY /= '1' and RX_COMMAND_FIFO_VALID = '1') then
RX_COMMAND_FIFO_RD_EN <= '1';
next_state <= START_OUT_FRAMEWORK;
end if;
------------------SETUP PACKET PROCESSING--------------------------
when SETUP_LOCKOUT_TRIPWIRE =>
state_ind_arb <= "000001";
a_Context_Mux_Ctrl <= '1';
if (a_USBMODE_Rd(SLOM) = '0') then
next_state <= IDLE;
else
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_In_Token_Received_Clear(a_Bit_Index + 16) <= '0';
a_In_Token_Received_Clear_En <= '1';
a_EMDPTFLUSH_Set(a_Bit_Index + 16) <= '1';
a_EMDPTFLUSH_Set_En <= '1';
next_state <= SETUP_UPDATE_SETUP_BYTES;
end if;
when SETUP_UPDATE_SETUP_BYTES =>
state_ind_arb <= "000010";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_dQH_Setup_Buffer_Wr_En <= '1';
next_state <= SETUP_WAIT1;
when SETUP_WAIT1 => --wait for dqh to be updated in context memory
state_ind_arb <= "000011";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
next_state <= SETUP_S2MM;
when SETUP_S2MM =>
state_ind_arb <= "000100";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_Setup_Bytes_FSM <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned(((a_Endpt_Nr_Int*64)+40),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(8,32)); --dQH = 2*4 Bytes
if (a_DMA_Transfer_Complete = '1') then
a_Write_Setup_Bytes_FSM <= '0';
a_ENDPTSETUPSTAT_Wr_Fsm(a_Bit_Index) <= '1';
a_ENDPTSETUPSTAT_Wr_En_Fsm <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= SETUP_UPDATE_ENDPTSETUP_RECEIVED;
end if;
when SETUP_UPDATE_ENDPTSETUP_RECEIVED =>
state_ind_arb <= "000101";
a_Arb_ENDPTSETUP_RECEIVED_Clear(a_Bit_Index) <= '0';
a_Arb_ENDPTSETUP_RECEIVED_Clear_En <= '1';
if (a_Arb_ENDPTSETUP_RECEIVED_Ack = '1') then
next_state <= SETUP_WAIT2;
end if;
when SETUP_WAIT2 =>
next_state <= IDLE;
------------------------------ PRIME FRAMEWORK -----------------------------------------
when PRIME_MM2S_DQH => --read DQH from main memory
state_ind_arb <= "000110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dQH_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= PRIME_WAIT0;
end if;
when PRIME_WAIT0 =>
state_ind_arb <= "000000";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
next_state <= PRIME_MM2S_DTD;
when PRIME_MM2S_DTD => --read DQH from main memory
state_ind_arb <= "100110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dTD = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_DMA_Current_Transfer_Addr_Fsm <= a_dTD_Page0_Rd & a_dTD_Current_Offset_Rd; --initialize the transfer address with PAGE0
a_DMA_Current_Transfer_Addr_Le <= '1';
if (a_Endpt_In_Out = '1') then --IN endpoint, FIFO needs to be prepared with transmit data
tx_fifo_resetn <= '0'; -- flush fifo;
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
next_state <= PRIME_FILL_FIFO;
else --OUT endpoint
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
next_state <= PRIME_WAIT1;
end if;
end if;
when PRIME_FILL_FIFO => --extract necessary data to fill TX fifo
state_ind_arb <= "000111";
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Send_Zero_Length_Packet_Set(a_Bit_Index) <= '1';
a_Send_Zero_Length_Packet_Set_En <= '1';
next_state <= PRIME_WAIT1;
else
if (to_integer(unsigned(a_dTD_Total_Bytes_Rd)) < C_FIFO_SIZE) then
next_state <= PRIME_FILL_FIFO_1;
else
next_state <= PRIME_FILL_FIFO_2;
end if;
end if;
when PRIME_FILL_FIFO_1 =>
state_ind_arb <= "001000";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= "00000000000000000" & a_dTD_Total_Bytes_Rd;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + unsigned(a_dTD_Total_Bytes_Rd)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
next_state <= PRIME_WAIT1;
end if;
when PRIME_FILL_FIFO_2 =>
state_ind_arb <= "001001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(C_FIFO_SIZE,32));
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_Aux_Addr_Register) + (C_FIFO_SIZE));
a_DMA_Current_Transfer_Addr_Le <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + (C_FIFO_SIZE)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
next_state <= PRIME_WAIT1;
end if;
when PRIME_WAIT1 =>
state_ind_arb <= "001010";
next_state <= PRIME_WAIT2;
when PRIME_WAIT2 =>
state_ind_arb <= "001011";
next_state <= IDLE;
---------OUT_TOKEN_FRAMEWORK (RX_PACKET)---------------------------------------------------------------------------
when START_OUT_FRAMEWORK =>
state_ind_arb <= "001100";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_Out_Transfer_Byte_Count_Le1 <= '1';
a_Endpt_Nr_Fsm <= to_integer(unsigned(RX_COMMAND_FIFO_DOUT(10 downto 7)));
a_Endpt_Nr_Le <= '1';
next_state <= OUT_START_TRANSFER;
when OUT_START_TRANSFER =>
state_ind_arb <= "001101";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
if (a_Out_Transfer_Byte_Count <= a_dTD_Total_Bytes_Rd)then
next_state <= OUT_TRANSFER_S2MM;
else
next_state <= IDLE; --ERROR
end if;
when OUT_TRANSFER_S2MM =>
state_ind_arb <= "001110";
a_Axis_S2MM_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_DMA_Transfer_Length <= "0000000000000000000" & a_Out_Transfer_Byte_Count; --transfer the received packet in main memory
a_Start_DMA_S2MM <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dTD_Total_Bytes_Wr <= std_logic_vector(unsigned(a_dTD_Total_Bytes_Rd)- unsigned(a_Out_Transfer_Byte_Count)); --update the number of bytes left to transfer
a_Arb_dTD_Total_Bytes_Wr_En <= '1'; -- update dTD_TOTAL_BYTES
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b)) + unsigned(a_Out_Transfer_Byte_Count)); --update the memory address for the s2mm transfer
a_DMA_Current_Transfer_Addr_Le <= '1';
next_state <= OUT_WAIT1;
end if;
when OUT_WAIT1 =>
state_ind_arb <= "001111";
next_state <= OUT_CHECK_COMPLETE;
when OUT_CHECK_COMPLETE =>
state_ind_arb <= "010000";
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_ENDPTPRIME_Set(a_Bit_Index) <= '1';
a_ENDPTPRIME_Set_En <= '1';
next_state <= OUT_TRANSFER_COMPLETE;
else
next_state <= IDLE;
end if;
when OUT_TRANSFER_COMPLETE =>
state_ind_arb <= "010001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_dQH_Fsm <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
if (a_DMA_Transfer_Complete = '1') then
a_Write_dQH_Fsm <= '0';
if (a_dQH_T_Rd = '0') then
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= OUT_FETCH_NEXT_DTD;
else
a_ENDPTCOMPLETE_Wr(a_Bit_Index) <= '1';
a_ENDPTCOMPLETE_Wr_En <= '1';
next_state <= IDLE;
end if;
end if;
when OUT_FETCH_NEXT_DTD =>
state_ind_arb <= "010010";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dQH = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
next_state <= OUT_WAIT2;
end if;
when OUT_WAIT2 =>
state_ind_arb <= "010011";
next_state <= IDLE;
---------IN_TOKEN_FRAMEWORK (TX_PACKET)---------------------------------------------------------------------------
when START_IN_FRAMEWORK =>
state_ind_arb <= "010100";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; --context memory connected to DMA stream port, not FIFO if 0 fifo will assert tvalid for 1 ck cycle
a_Context_Mux_Ctrl <= '0';
a_In_Token_Received_Clear(a_Bit_Index) <= '0';
a_In_Token_Received_Clear_En <= '1';
if (a_In_Packet_Complete_Rd(a_Bit_Index) = '1') then
a_In_Packet_Complete_Clear(a_Bit_Index) <= '0';
a_In_Packet_Complete_Clear_En <= '1';
next_state <= IN_HANDSHAKE;
elsif (a_Resend(a_Bit_Index) = '1') then
tx_fifo_resetn <= '0'; -- flush fifo;
next_state <= IN_HANDSHAKE;
end if;
when IN_HANDSHAKE =>
state_ind_arb <= "010101";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '1';
if (a_Cnt_Bytes_Sent_oValid = '1') then
if (a_Resend(a_Bit_Index) = '0') then
a_Arb_dTD_Total_Bytes_Wr <= std_logic_vector(unsigned(a_dTD_Total_Bytes_Rd)- unsigned(a_Cnt_Bytes_Sent_Loc)); --update the number of bytes left to transfer
a_Arb_dTD_Total_Bytes_Wr_En <= '1'; -- update dTD_TOTAL_BYTES
end if;
next_state <= IN_WAIT0;
end if;
when IN_WAIT0 =>
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
state_ind_arb <= "010111";
if (a_Resend(a_Bit_Index) = '0') then
next_state <= IN_CHECK_COMPLETE;
else
a_Resend_Clear(a_Bit_Index) <= '0';
a_Resend_Clear_En <= '1';
next_state <= IN_RELOAD_BUFFER;
end if;
when IN_CHECK_COMPLETE =>
state_ind_arb <= "011000";
a_DMA_In_Transfer_Length_Le <= '1';
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_dTD_Status_Wr_En <= '1'; --write 0 to active bit
next_state <= IN_TRANSACTION_COMPLETE;
else
next_state <= IN_TRANSFER_MM2S;
end if;
when IN_TRANSFER_MM2S =>
state_ind_arb <= "010110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= a_DMA_In_Transfer_Length;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= IN_WAIT1;
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_Aux_Addr_Register) + unsigned(a_Cnt_Bytes_Sent_Loc));
a_DMA_Current_Transfer_Addr_Le <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + unsigned(a_Cnt_Bytes_Sent_Loc)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
end if;
when IN_RELOAD_BUFFER =>
state_ind_arb <= "111011";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= a_DMA_In_Transfer_Length;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array_q(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= IN_WAIT1;
end if;
when IN_WAIT1 =>
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
state_ind_arb <= "010111";
next_state <= IDLE;
when IN_TRANSACTION_COMPLETE => --copy dQH back to main memory with status updated
state_ind_arb <= "011001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_dQH_Fsm <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
if (a_DMA_Transfer_Complete = '1' or a_Send_Zero_Length_Packet_Ack_Rd(a_Bit_Index) = '1') then
a_Write_dQH_Fsm <= '0';
a_Send_Zero_Length_Packet_Ack_Clear(a_Bit_Index) <= '1';
a_Send_Zero_Length_Packet_Ack_Clear_En <= '1';
if (a_dQH_T_Rd = '1') then
a_ENDPTCOMPLETE_Wr(a_Bit_Index) <= '1';
a_ENDPTCOMPLETE_Wr_En <= '1';
a_ENDPTSTAT_clear(a_Bit_Index) <= '0';
a_ENDPTSTAT_Clear_En <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= IDLE;
else
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '1';
a_ENDPTPRIME_Set(a_Bit_Index) <= '1';
a_ENDPTPRIME_Set_En <= '1';
next_state <= IN_FETCH_NEXT_DTD;
end if;
end if;
when IN_FETCH_NEXT_DTD =>
state_ind_arb <= "011010";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dQH = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
next_state <= IN_WAIT2;
end if;
when IN_WAIT2 =>
state_ind_arb <= "011011";
next_state <= IDLE;
when others =>
state_ind_arb <= "011100";
next_state <= IDLE;
end case;
end process;
end implementation;
|
mit
|
be1ce7ed706053b22c1cf9f959595abf
| 0.567565 | 3.242539 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
wired_or/wired_or.vhd
| 1 | 974 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wired_or is
Port (
C : out std_logic);
end wired_or;
architecture Behavioral of wired_or is
type TS is( '0', '1', 'Z');
type TSV is array( NATURAL range <> ) of TS;
signal arg : TSV( 3 downto 0 ):= "0100";
--function wired_or( S : TSV ) return TS is
-- variable resolved_value : TS := 'Z';
function wired_or( S : TSV ) return std_logic is
variable resolved_value : std_logic := 'Z';
begin
for I in S'range loop
if S( I ) = '1' then
resolved_value := '1';
exit;
elsif S( I ) = '0' then
resolved_value := '0';
end if;
end loop;
return resolved_value;
end wired_or;
begin
c <= wired_or( arg );
end Behavioral;
|
mit
|
3e9e806dc81b1cb7e392e8fbaee47867
| 0.637577 | 2.98773 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/fadd-grafi/gate.vhd
| 1 | 769 |
entity PGMerger is
port (
phi: in std_logic;
ghi: in std_logic;
plo: in std_logic;
glo: in std_logic;
pout: out std_logic;
gout: out std_logic;
);
end PropagateGenerateMerger;
entity HalfAdder is
port (
x1: in std_logic;
x2: in std_logic;
p: out std_logic;
g: out std_logic;
);
end HalfAdder;
entity FullAdder is
port (
x1: in std_logic;
x2: in std_logic;
x3: in std_logic;
p: out std_logic;
g: out std_logic;
);
end FullAdder;
architecture PGMGate of PGMerger is
begin
pout <= phi and plo
gout <= (phi and glo) or ghi
end PGMGate;
architecture HAGate is
begin
p <= x1 xor x2;
g <= x1 and x2;
end HAGate;
architecture FAGate is
begin
p <= (x1 xor x2) xor x3;
g <= ((x1 and x2) or (x2 and x3)) or (x3 and x1);
end FAGate;
|
bsd-2-clause
|
7f462e9e490c589302b9adf7e1658478
| 0.652796 | 2.344512 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_lbW.vhd
| 1 | 6,394 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_lbW_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_lbW_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000010", 2 => "00000100", 3 => "00000110",
4 => "00001000", 5 => "00001010", 6 => "00001100", 7 => "00001110",
8 => "00010000", 9 => "00010010", 10 => "00010100", 11 => "00010110",
12 => "00010111", 13 => "00011001", 14 => "00011011", 15 => "00011101",
16 => "00011111", 17 => "00100001", 18 => "00100011", 19 => "00100101",
20 => "00100110", 21 => "00101000", 22 => "00101010", 23 => "00101100",
24 => "00101110", 25 => "00110000", 26 => "00110001", 27 => "00110011",
28 => "00110101", 29 => "00110111", 30 => "00111000", 31 => "00111010",
32 => "00111100", 33 => "00111110", 34 => "00111111", 35 => "01000001",
36 => "01000011", 37 => "01000101", 38 => "01000110", 39 => "01001000",
40 => "01001010", 41 => "01001011", 42 => "01001101", 43 => "01001111",
44 => "01010000", 45 => "01010010", 46 => "01010100", 47 => "01010101",
48 => "01010111", 49 => "01011001", 50 => "01011010", 51 => "01011100",
52 => "01011101", 53 => "01011111", 54 => "01100001", 55 => "01100010",
56 => "01100100", 57 => "01100101", 58 => "01100111", 59 => "01101000",
60 => "01101010", 61 => "01101011", 62 => "01101101", 63 => "01101110",
64 => "01110000", 65 => "01110001", 66 => "01110011", 67 => "01110100",
68 => "01110110", 69 => "01110111", 70 => "01111001", 71 => "01111010",
72 => "01111100", 73 => "01111101", 74 => "01111111", 75 => "10000000",
76 => "10000001", 77 => "10000011", 78 => "10000100", 79 => "10000110",
80 => "10000111", 81 => "10001000", 82 => "10001010", 83 => "10001011",
84 => "10001100", 85 => "10001110", 86 => "10001111", 87 => "10010000",
88 => "10010010", 89 => "10010011", 90 => "10010100", 91 => "10010110",
92 => "10010111", 93 => "10011000", 94 => "10011001", 95 => "10011011",
96 => "10011100", 97 => "10011101", 98 => "10011110", 99 => "10100000",
100 => "10100001", 101 => "10100010", 102 => "10100011", 103 => "10100100",
104 => "10100110", 105 => "10100111", 106 => "10101000", 107 => "10101001",
108 => "10101010", 109 => "10101011", 110 => "10101101", 111 => "10101110",
112 => "10101111", 113 => "10110000", 114 => "10110001", 115 => "10110010",
116 => "10110011", 117 => "10110100", 118 => "10110101", 119 => "10110110",
120 => "10111000", 121 => "10111001", 122 => "10111010", 123 => "10111011",
124 => "10111100", 125 => "10111101", 126 => "10111110", 127 => "10111111",
128 => "11000000", 129 => "11000001", 130 => "11000010", 131 => "11000011",
132 => "11000100", 133 => "11000101", 134 => "11000110", 135 to 136=> "11000111",
137 => "11001000", 138 => "11001001", 139 => "11001010", 140 => "11001011",
141 => "11001100", 142 => "11001101", 143 => "11001110", 144 => "11001111",
145 to 146=> "11010000", 147 => "11010001", 148 => "11010010", 149 => "11010011",
150 => "11010100", 151 to 152=> "11010101", 153 => "11010110", 154 => "11010111",
155 => "11011000", 156 to 157=> "11011001", 158 => "11011010", 159 => "11011011",
160 to 161=> "11011100", 162 => "11011101", 163 => "11011110", 164 to 165=> "11011111",
166 => "11100000", 167 to 168=> "11100001", 169 => "11100010", 170 to 171=> "11100011",
172 => "11100100", 173 to 174=> "11100101", 175 => "11100110", 176 to 177=> "11100111",
178 to 179=> "11101000", 180 => "11101001", 181 to 182=> "11101010", 183 to 184=> "11101011",
185 to 186=> "11101100", 187 to 188=> "11101101", 189 to 190=> "11101110", 191 to 192=> "11101111",
193 to 194=> "11110000", 195 to 196=> "11110001", 197 to 198=> "11110010", 199 to 200=> "11110011",
201 to 203=> "11110100", 204 to 205=> "11110101", 206 to 208=> "11110110", 209 to 211=> "11110111",
212 to 214=> "11111000", 215 to 217=> "11111001", 218 to 221=> "11111010", 222 to 225=> "11111011",
226 to 229=> "11111100", 230 to 235=> "11111101", 236 to 243=> "11111110", 244 to 255=> "11111111" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_lbW is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_lbW is
component Loop_loop_height_lbW_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_lbW_rom_U : component Loop_loop_height_lbW_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
cba30329f675b6e2f618206f888402f9
| 0.543947 | 3.643305 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU.vhd
| 1 | 7,237 |
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity FPU is
port (
clk : in std_logic;
code : in std_logic_vector(5 downto 0);
tagD : in tag_t;
valA : in value_t;
valB : in value_t;
tag1 : buffer tag_t := (others => '0');
tag2 : buffer tag_t := (others => '0');
emitTag : out tag_t := (others => '0');
emitVal : out value_t);
end FPU;
architecture twoproc_pipeline of FPU is
component FAdd
port (
clk : in std_logic;
flt_in1 : in std_logic_vector(31 downto 0);
flt_in2 : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end component;
component FMul
port (
clk : in std_logic;
flt_in1 : in std_logic_vector(31 downto 0);
flt_in2 : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end component;
component FInv
port (
clk : in std_logic;
flt_in : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end component;
component FSqr
port (
clk : in std_logic;
flt_in : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end component;
component ItoF
port (
clk : in std_logic;
i : in std_logic_vector(31 downto 0);
f : out std_logic_vector(31 downto 0));
end component;
component FtoI2 is
port (
clk : in std_logic;
f : in std_logic_vector(31 downto 0);
i : out std_logic_vector(31 downto 0));
end component;
component FFlr
port (
clk : in std_logic;
f : in std_logic_vector(31 downto 0);
g : out std_logic_vector(31 downto 0));
end component;
constant z_exp : std_logic_vector(7 downto 0) := (others => '0');
constant h_exp : std_logic_vector(7 downto 0) := (others => '1');
constant z_frc : std_logic_vector(22 downto 0) := (others => '0');
constant o_frc : std_logic_vector(22 downto 0) := x"00000" & "001";
signal code1, code1_out, code2, code3 : std_logic_vector(2 downto 0) := (others => '0');
signal funct1, funct2, funct3 : std_logic_vector(1 downto 0) := (others => '0');
signal a1, b1, d1, d2, d3 : std_logic_vector(31 downto 0) := (others => '0');
signal b_fadd, d_fadd, d_fmul, d_finv, d_fsqr, d_fflr, d_itof, d_ftoi : std_logic_vector(31 downto 0);
begin
sequential1 : process(clk)
begin
if rising_edge(clk) then
a1 <= std_logic_vector(valA);
b1 <= std_logic_vector(valB);
code1 <= code(2 downto 0);
funct1 <= code(5 downto 4);
tag1 <= tagD;
end if;
end process;
fadd_map : FAdd port map (
clk => clk,
flt_in1 => a1,
flt_in2 => b_fadd,
flt_out => d_fadd);
b_fadd <= (b1(31) xor code1(0)) & b1(30 downto 0);
fmul_map : FMul port map (
clk => clk,
flt_in1 => a1,
flt_in2 => b1,
flt_out => d_fmul);
finv_map : FInv port map (
clk => clk,
flt_in => a1,
flt_out => d_finv);
fsqr_map : FSqr port map (
clk => clk,
flt_in => a1,
flt_out => d_fsqr);
fflr_map : FFlr port map (
clk => clk,
f => a1,
g => d_fflr);
itof_map : ItoF port map (
clk => clk,
i => a1,
f => d_itof);
ftoi2_map : FtoI2 port map (
clk => clk,
f => b1,
i => d_ftoi);
combinatorial1 : process(a1, b1, code1)
variable a_sgn, b_sgn : std_logic;
variable a_exp, b_exp : std_logic_vector(7 downto 0);
variable a_frc, b_frc : std_logic_vector(22 downto 0);
begin
a_sgn := a1(31);
b_sgn := b1(31);
a_exp := a1(30 downto 23);
b_exp := b1(30 downto 23);
a_frc := a1(22 downto 0);
b_frc := b1(22 downto 0);
case code1 is
when "000" =>
if b_exp /= h_exp then
d1 <= a_sgn & h_exp & a_frc;
elsif b_exp /= h_exp then
d1 <= b_sgn & h_exp & b_frc;
else
d1 <= (a_sgn and b_sgn) & h_exp & (a_frc or b_frc or (x"00000" & "00" & (a_sgn xor b_sgn)));
end if;
when "001" =>
if b_exp /= h_exp then
d1 <= a_sgn & h_exp & a_frc;
elsif b_exp /= h_exp then
d1 <= not b_sgn & h_exp & b_frc;
else
d1 <= (a_sgn and not b_sgn) & h_exp & (a_frc or b_frc or (x"00000" & "00" & (a_sgn xor (not b_sgn))));
end if;
when "010" =>
if a_exp = z_exp or b_exp = z_exp then
d1 <= (a_sgn xor b_sgn) & h_exp & o_frc;
else
d1 <= (a_sgn xor b_sgn) & h_exp & (a_frc or b_frc);
end if;
when "011" =>
if a_frc = z_frc then
d1 <= a_sgn & z_exp & z_frc;
else
d1 <= a_sgn & h_exp & o_frc;
end if;
when "100" =>
d1 <= a_sgn & a_exp & (a_frc or (x"00000" & "00" & a_sgn));
when "101" =>
d1 <= a1;
when "110" =>
d1 <= a1;
when others =>
d1 <= a1;
end case;
if (a_exp = h_exp or b_exp = h_exp) and code1 /= "111" then
code1_out <= "101";
else
code1_out <= code1;
end if;
end process;
sequential2 : process(clk)
begin
if rising_edge(clk) then
d2 <= d1;
code2 <= code1_out;
funct2 <= funct1;
tag2 <= tag1;
end if;
end process;
sequential3 : process(clk)
begin
if rising_edge(clk) then
d3 <= d2;
code3 <= code2;
funct3 <= funct2;
emitTag <= tag2;
end if;
end process;
combinatorial3 : process(code3, funct3, d_fadd, d_fmul, d_finv, d_fsqr, d3, d_fflr, d_itof, d_ftoi)
variable d_out : std_logic_vector(31 downto 0);
begin
case code3 is
when "000" => d_out := d_fadd;
when "001" => d_out := d_fadd;
when "010" => d_out := d_fmul;
when "011" => d_out := d_finv;
when "100" => d_out := d_fsqr;
when "101" => d_out := d3;
when "110" => d_out := d_fflr;
when "111" => d_out := d_itof or d_ftoi;
when others => assert false;
end case;
case funct3 is
when "00" => emitVal <= value_t(d_out);
when "01" => emitVal <= value_t(not d_out(31) & d_out(30 downto 0));
when "10" => emitVal <= value_t('0' & d_out(30 downto 0));
when "11" => emitVal <= value_t('1' & d_out(30 downto 0));
when others => assert false;
end case;
end process;
end twoproc_pipeline;
|
bsd-2-clause
|
e981c410ba6fd8a8e46cd8ddccf4eee5
| 0.461517 | 3.319725 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/tb_motor_puerta.vhd
| 1 | 2,072 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_motor_puerta IS
END tb_motor_puerta;
ARCHITECTURE behavior OF tb_motor_puerta IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT motor_puerta
PORT(
CLK : IN std_logic;
RST : IN std_logic;
nivel : IN std_logic;
celula : IN std_logic;
accionar_puerta : IN std_logic;
actuador_puerta : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal nivel : std_logic := '0';
signal celula : std_logic := '0';
signal accionar_puerta : std_logic := '0';
--Outputs
signal actuador_puerta : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: motor_puerta PORT MAP (
CLK => CLK,
RST => RST,
nivel => nivel,
celula => celula,
accionar_puerta => accionar_puerta,
actuador_puerta => actuador_puerta
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RST <= '0';
celula <= '0';
WAIT FOR 3 ns;
accionar_puerta <= '0';
WAIT FOR 20 ns;
celula <= '0';
WAIT FOR 5 ns;
accionar_puerta <= '1';
WAIT FOR 10 ns;
RST <= '1';
WAIT FOR 5 ns;
RST <= '0';
WAIT FOR 5 ns;
celula <= '1';
WAIT FOR 5 ns;
accionar_puerta <= '1';
WAIT FOR 20 ns;
celula <= '1';
WAIT FOR 5 ns;
accionar_puerta <= '0';
WAIT FOR 10 ns;
nivel <= '1';
WAIT FOR 10 ns;
celula <= '0';
WAIT FOR 5 ns;
accionar_puerta <= '0';
WAIT FOR 5 ns;
nivel <= '0';
WAIT FOR 15 ns;
ASSERT false
REPORT "Simulacion finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
|
gpl-3.0
|
43772fa7e7d0bc9b33095b15afe0258a
| 0.54778 | 3.453333 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/decoder.vhd
| 1 | 1,503 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY decoder IS
PORT(
CLK : IN std_logic;
RST : IN std_logic;
code : IN std_logic_vector(1 DOWNTO 0);
action : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
led : OUT std_logic_vector(6 DOWNTO 0);
dig_ctrl : OUT std_logic_vector(3 DOWNTO 0)
);
END ENTITY decoder;
ARCHITECTURE Behavioral OF decoder IS
signal seg_reg0 : std_logic_vector(6 DOWNTO 0);
signal seg_reg1 : std_logic_vector(6 DOWNTO 0);
shared variable digit : bit := '0';
BEGIN
seg_write:process(CLK,RST)
begin
if RST = '1' then
seg_reg0 <= "0000000";
seg_reg1 <= "0000000";
digit := '0';
led <= "0000000";
dig_ctrl <= "0000";
elsif rising_edge(CLK) then
if digit='0' then
case (code) is
when "01" =>
seg_reg0 <= "0000001";
when "10" =>
seg_reg0 <= "1001111";
when "11" =>
seg_reg0 <= "0010010";
when others =>
seg_reg0 <= "1111110";
end case;
digit := '1';
dig_ctrl <= "1110";
led <= seg_reg0;
elsif digit='1' then
case (action) is
when "11" => --Subiendo
seg_reg1 <= "0011101";
digit := '1';
when "00" => --Bajando
seg_reg1 <= "1100011";
digit := '1';
when others => --Parado
seg_reg1 <= "1111110";
digit := '1';
end case;
digit := '0';
dig_ctrl <= "0111";
led <= seg_reg1;
end if;
end if;
end process;
END ARCHITECTURE Behavioral;
|
gpl-3.0
|
28ffd8dbf618a868f28eb928847c9eb2
| 0.568197 | 2.851992 | false | false | false | false |
hangmann/fpga-heater
|
simple_timebase_v1_00_a/hdl/vhdl/simple_timebase.vhd
| 1 | 11,626 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library simple_timebase_v1_00_a;
use simple_timebase_v1_00_a.user_logic;
entity simple_timebase is
generic
(
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
);
port
(
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity simple_timebase;
architecture IMP of simple_timebase is
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR,
ZERO_ADDR_PAD & USER_SLV_HIGHADDR
);
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG)
);
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
USER_LOGIC_I : entity simple_timebase_v1_00_a.user_logic
generic map
(
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
mit
|
067dff9be565f9d5430b1275e185a713
| 0.460606 | 3.764896 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/Interpolation.vhd
| 1 | 19,548 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity INTERPOLATION is
generic
(
width : integer := 8
);
port
(
Clock : in std_logic;
----------------------------------------------------
B31 : in std_logic_vector( width downto 0 );
B33 : in std_logic_vector( width downto 0 );
B35 : in std_logic_vector( width downto 0 );
G32 : in std_logic_vector( width downto 0 );
G34 : in std_logic_vector( width downto 0 );
------------------------------------------------------
B13 : in std_logic_vector( width downto 0 );
B53 : in std_logic_vector( width downto 0 );
G23 : in std_logic_vector( width downto 0 );
G43 : in std_logic_vector( width downto 0 );
----------------------------------------------------
-- Dhor42
G41 : in std_logic_vector( width downto 0 ); -- G41
-- G43 : in std_logic_vector( width downto 0 ); -- G43
R40 : in std_logic_vector( width downto 0 ); -- R40
R42 : in std_logic_vector( width downto 0 ); -- R42
R44 : in std_logic_vector( width downto 0 ); -- R44
-- R42 : in std_logic_vector( width downto 0 ); -- R42
-- Dver42
-- G32 : in std_logic_vector( width downto 0 ); -- G32
G52 : in std_logic_vector( width downto 0 ); -- G52
R22 : in std_logic_vector( width downto 0 ); -- R22
-- R42 : in std_logic_vector( width downto 0 ); -- R42
R62 : in std_logic_vector( width downto 0 ); -- R62
-- R42 : in std_logic_vector( width downto 0 ); -- R42
-- Dhor44
-- G43 : in std_logic_vector( width downto 0 ); -- G43
G45 : in std_logic_vector( width downto 0 ); -- G45
-- R42 : in std_logic_vector( width downto 0 ); -- R42
-- R44 : in std_logic_vector( width downto 0 ); -- R44
R46 : in std_logic_vector( width downto 0 ); -- R46
-- R44 : in std_logic_vector( width downto 0 ); -- R44
-- Dver44
-- G34 : in std_logic_vector( width downto 0 ); -- G34
G54 : in std_logic_vector( width downto 0 ); -- G54
R24 : in std_logic_vector( width downto 0 ); -- R24
-- R44 : in std_logic_vector( width downto 0 ); -- R44
R64 : in std_logic_vector( width downto 0 ); -- R64
-- R44 : in std_logic_vector( width downto 0 ); -- R44
G22 : in std_logic_vector( width downto 0 ); -- G22
-- G23 : in std_logic_vector( width downto 0 ); -- G23
-- G43 : in std_logic_vector( width downto 0 ); -- G43
G24 : in std_logic_vector( width downto 0 ); -- G24
---------------------------------------------------------------------------------------
-- EdgeHorizontal : in std_logic_vector( width downto 0 );
-- EdgeVertical : in std_logic_vector( width downto 0 );
EdgeHorizontalTest : out std_logic_vector( 18 downto 0 );
EdgeVerticalTest : out std_logic_vector( 18 downto 0 );
-- BarG42 : out std_logic_vector( width downto 0 );
-- BarG44 : out std_logic_vector( width downto 0 );
-------------------------------------------------------------
G : out std_logic_vector( width downto 0 )
);
end INTERPOLATION;
architecture TABLE of INTERPOLATION is
type Column is array( 0 to 6 ) of std_logic_vector( width downto 0 );
type Matrix is array ( 0 to 6 ) of Column;
constant TestMatrix : Matrix :=
(
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" ),
( "111000000", "111000000", "111000000", "111000000", "111000000", "111000000", "111000000" )
);
signal BayerPattern : Matrix;
component CSAFullAdder is
generic
(
width : integer := 8
);
port
(
x_1 : in std_logic_vector( width downto 0 );
x_2 : in std_logic_vector( width downto 0 );
x_3 : in std_logic_vector( width downto 0 );
Sum : out std_logic_vector( width downto 0 );
Carry : out std_logic_vector( width downto 0 )
);
end component;
component CSAHalfAdder is
generic
(
width : integer := 8
);
port
(
x_1 : in std_logic_vector( width downto 0 );
x_2 : in std_logic_vector( width downto 0 );
Sum : out std_logic_vector( width downto 0 );
Carry : out std_logic_vector( width downto 0 )
);
end component;
component CSAEdgeHalfAdder is
generic
(
width : integer := 18
);
port
(
x_1 : in std_logic_vector( width downto 0 );
x_2 : in std_logic_vector( width downto 0 );
Sum : out std_logic_vector( width downto 0 );
Carry : out std_logic_vector( width downto 0 )
);
end component;
component absolute
generic
(
width : integer := 8
);
Port
(
x : in std_logic_vector( width downto 0 );
y : out std_logic_vector( width downto 0)
);
end component;
component CalculateG
generic
(
width : integer := 8
);
port
(
Difference0 : in std_logic_vector( 18 downto 0 );
Difference01 : in std_logic_vector( 18 downto 0 );
IHorizontal : in std_logic_vector( width downto 0 );
IVertical : in std_logic_vector( width downto 0 );
Difference7 : in std_logic_vector( width downto 0 );
DifferenceDver : in std_logic_vector( width + 2 downto 0 );
DifferenceDhor : in std_logic_vector( width + 2 downto 0 );
ElementG : out std_logic_vector( width downto 0 )
);
end component;
component Gout
Port
(
-- Dhor42
g1 : in std_logic_vector( width downto 0 ); -- G41
g2 : in std_logic_vector( width downto 0 ); -- G43
b1 : in std_logic_vector( width downto 0 ); -- R40
b2 : in std_logic_vector( width downto 0 ); -- R42
b3 : in std_logic_vector( width downto 0 ); -- R44
b4 : in std_logic_vector( width downto 0 ); -- R42
-- Dver42
g1_2 : in std_logic_vector( width downto 0 ); -- G32
g2_2 : in std_logic_vector( width downto 0 ); -- G52
b1_2 : in std_logic_vector( width downto 0 ); -- R22
b2_2 : in std_logic_vector( width downto 0 ); -- R42
b3_2 : in std_logic_vector( width downto 0 ); -- R62
b4_2 : in std_logic_vector( width downto 0 ); -- R42
-- Dhor44
g3 : in std_logic_vector( width downto 0 ); -- G43
g4 : in std_logic_vector( width downto 0 ); -- G45
b5 : in std_logic_vector( width downto 0 ); -- R42
b6 : in std_logic_vector( width downto 0 ); -- R44
b7 : in std_logic_vector( width downto 0 ); -- R46
b8 : in std_logic_vector( width downto 0 ); -- R44
-- Dver44
g3_2 : in std_logic_vector( width downto 0 ); -- G34
g4_2 : in std_logic_vector( width downto 0 ); -- G54
b5_2 : in std_logic_vector( width downto 0 ); -- R24
b6_2 : in std_logic_vector( width downto 0 ); -- R44
b7_2 : in std_logic_vector( width downto 0 ); -- R64
b8_2 : in std_logic_vector( width downto 0 ); -- R44
G_bar1 : out std_logic_vector( width downto 0 ); -- ~G42
G_bar2 : out std_logic_vector( width downto 0 ) -- ~G44
-- E_in1 : in std_logic_vector( width downto 0 ); -- G22
-- E_in2 : in std_logic_vector( width downto 0 ); -- G23
-- E_in3 : in std_logic_vector( width downto 0 ); -- G43
-- E_in4 : in std_logic_vector( width downto 0 ); -- G24
-- E : out std_logic_vector( 18 downto 0 )
);
end component;
component combine_E_out_G_in
Port
(
G1 : in std_logic_vector( 8 downto 0 );
G_bar1 : in std_logic_vector(8 downto 0);
G2 : in std_logic_vector(8 downto 0);
G3 : in std_logic_vector(8 downto 0);
G4 : in std_logic_vector(8 downto 0);
G_bar2 : in std_logic_vector(8 downto 0);
E : out std_logic_vector(18 downto 0)
);
end component;
-----------------------------------------------------------------------------------------------------------------
signal G_bar1 : std_logic_vector( width downto 0 ); -- ~G42
signal G_bar2 : std_logic_vector( width downto 0 ); -- ~G44
signal EdgeHorizontal : std_logic_vector( 18 downto 0 );
signal EdgeVertical : std_logic_vector( 18 downto 0 );
-- Ehor - Ever
signal Neg0 : std_logic_vector( 18 downto 0 );
signal Sum0 : std_logic_vector( 18 downto 0 );
signal Carry0: std_logic_vector( 18 downto 0 );
signal DifferenceSum0 : std_logic_vector( 19 downto 0 );
signal Difference0 : std_logic_vector( 18 downto 0 );
-- Ever - Ehor
signal Difference01 : std_logic_vector( 18 downto 0 );
-----------------------------------------------------------------------------------------------
signal NegB33 : std_logic_vector( width downto 0 );
-- | B31 - B33 |
signal Sum1 : std_logic_vector( width downto 0 );
signal Carry1: std_logic_vector( width downto 0 );
signal DifferenceSum1 : std_logic_vector( width + 1 downto 0 );
signal Difference1 : std_logic_vector( width downto 0 );
signal Value1 : std_logic_vector( width downto 0 );
-- | B35 - B33 |
signal Sum2 : std_logic_vector( width downto 0 );
signal Carry2: std_logic_vector( width downto 0 );
signal DifferenceSum2 : std_logic_vector( width + 1 downto 0 );
signal Difference2 : std_logic_vector( width downto 0 );
signal Value2 : std_logic_vector( width downto 0 );
-- | G32 - G34 |
signal Neg3 : std_logic_vector( width downto 0 );
signal Sum3 : std_logic_vector( width downto 0 );
signal Carry3: std_logic_vector( width downto 0 );
signal DifferenceSum3 : std_logic_vector( width + 1 downto 0 );
signal Difference3 : std_logic_vector( width downto 0 );
signal Value3 : std_logic_vector( width downto 0 );
signal SumDhor : std_logic_vector( width downto 0 );
signal CarryDhor : std_logic_vector( width downto 0 );
signal DifferenceSumDhor : std_logic_vector( width + 1 downto 0 );
signal DifferenceDhor : std_logic_vector( width + 2 downto 0 );
---------------------------------------------------------------------------------------------------
-- | B13 - B33 |
signal Sum4 : std_logic_vector( width downto 0 );
signal Carry4: std_logic_vector( width downto 0 );
signal DifferenceSum4 : std_logic_vector( width + 1 downto 0 );
signal Difference4 : std_logic_vector( width downto 0 );
signal Value4 : std_logic_vector( width downto 0 );
-- | B53 - B33 |
signal Sum5 : std_logic_vector( width downto 0 );
signal Carry5: std_logic_vector( width downto 0 );
signal DifferenceSum5 : std_logic_vector( width + 1 downto 0 );
signal Difference5 : std_logic_vector( width downto 0 );
signal Value5 : std_logic_vector( width downto 0 );
-- | G23 - G43 |
signal Neg6 : std_logic_vector( width downto 0 );
signal Sum6 : std_logic_vector( width downto 0 );
signal Carry6: std_logic_vector( width downto 0 );
signal DifferenceSum6 : std_logic_vector( width + 1 downto 0 );
signal Difference6 : std_logic_vector( width downto 0 );
signal Value6 : std_logic_vector( width downto 0 );
signal SumDver : std_logic_vector( width downto 0 );
signal CarryDver : std_logic_vector( width downto 0 );
signal DifferenceSumDver : std_logic_vector( width + 1 downto 0 );
signal DifferenceDver : std_logic_vector( width + 2 downto 0 );
------------------------------------------------------------------------------------------------------
-- calculate IHorizontal
-- ( G32 + G34 ) / 2
signal SumIhor1 : std_logic_vector( width downto 0 );
signal CarryIhor1 : std_logic_vector( width downto 0 );
signal IhorSum1 : std_logic_vector( width + 1 downto 0 );
signal IHorizontal1 : std_logic_vector( width downto 0 );
-- B33 / 4
signal IHorizontal2 : std_logic_vector( width downto 0 );
-- ( B31 + B35 ) / 8
signal SumIhor3 : std_logic_vector( width downto 0 );
signal CarryIhor3 : std_logic_vector( width downto 0 );
signal IhorSum30 : std_logic_vector( width + 1 downto 0 );
signal IhorSum31 : std_logic_vector( width downto 0 );
signal IHorizontal3 : std_logic_vector( width downto 0 );
-- ( G32 + G34 ) / 2 + B33 / 4 + ( B31 + B35 ) / 8
signal SumIhor : std_logic_vector( width downto 0 );
signal CarryIhor : std_logic_vector( width downto 0 );
signal IhorSum : std_logic_vector( width + 1 downto 0 );
signal IHorizontal : std_logic_vector( width downto 0 );
-- calculate IVertical
-- ( G23 + G43 ) / 2
signal SumIver1 : std_logic_vector( width downto 0 );
signal CarryIver1 : std_logic_vector( width downto 0 );
signal IverSum1 : std_logic_vector( width + 1 downto 0 );
signal IVertical1 : std_logic_vector( width downto 0 );
-- B33 / 4
signal IVertical2 : std_logic_vector( width downto 0 );
-- ( B13 + B53 ) / 8
signal SumIver3 : std_logic_vector( width downto 0 );
signal CarryIver3 : std_logic_vector( width downto 0 );
signal IverSum30 : std_logic_vector( width + 1 downto 0 );
signal IverSum31 : std_logic_vector( width downto 0 );
signal IVertical3 : std_logic_vector( width downto 0 );
-- ( G32 + G34 ) / 2 + B33 / 4 + ( B31 + B35 ) / 8
signal SumIver : std_logic_vector( width downto 0 );
signal CarryIver : std_logic_vector( width downto 0 );
signal IverSum : std_logic_vector( width + 1 downto 0 );
signal IVertical : std_logic_vector( width downto 0 );
----------------------------------------------------------------------------------------
-- ( Ihor + Iver ) / 2
signal Sum7 : std_logic_vector( width downto 0 );
signal Carry7: std_logic_vector( width downto 0 );
signal DifferenceSum7 : std_logic_vector( width + 1 downto 0 );
signal Difference7 : std_logic_vector( width downto 0 );
signal ElementG : std_logic_vector( width downto 0 );
begin
BayerPattern( 6 )( 6 ) <= "000000011";
--mytest <= BayerPattern( 6 )( 6 );
EdgeHorizontalTest <= EdgeHorizontal;
EdgeVerticalTest <= EdgeVertical;
-- BarG42 <= G_bar1;
-- BarG44 <= G_bar2;
BarG42G44 : Gout port map
(
-- Dhor42
G41, G43, R40, R42, R44, R42,
-- Dver42
G32, G52, R22, R42, R62, R42,
-- Dhor44
G43, G45, R42, R44, R46, R44,
-- Dver44
G34, G54, R24, R44, R64, R44,
-- ~G42
G_bar1,
-- ~G44
G_bar2
-- G22,
-- G23,
-- G43,
-- G24,
-- EdgeHorizontal
);
-- Ehor = ( | G22 - ~G42 | + 2 * | G23 - G43 | + | G24 - ~G44 | * 256 / ( G23 + G43 )
Ehor : combine_E_out_G_in port map
(
G22,
G_bar1, -- ~G42
G23,
G43,
G24,
G_bar2, -- ~G44
EdgeHorizontal
);
-- Ever = ( | G22 - G24 | + 2 * | G32 - G34 | + | ~G42 - ~G44 | * 256 / ( G32 + G34 )
Ever : combine_E_out_G_in port map
(
G22,
G24,
G32,
G34,
G_bar1, -- ~G42
G_bar2, -- ~G44
EdgeVertical
);
-- Ehor - Ever
Neg0 <= not EdgeVertical + '1';
Diff0 : CSAEdgeHalfAdder port map( EdgeHorizontal, Neg0, Sum0, Carry0 );
DifferenceSum0 <= ( Carry0 & '0' ) + Sum0;
Difference0 <= DifferenceSum0( 18 downto 0 );
-- Ever - Ehor
Difference01 <= not Difference0 + '1';
---------------------------------------------------------------------------------------------------------------------
NegB33 <= not B33 + '1';
-- | B31 - B33 |
Diff1 : CSAHalfAdder port map( B31, NegB33, Sum1, Carry1 );
DifferenceSum1 <= ( Carry1 & '0' ) + Sum1;
Difference1 <= DifferenceSum1( width downto 0 );
absoulte1 : absolute port map( Difference1, Value1 );
-- | B35 - B33 |
Diff2 : CSAHalfAdder port map( B35, NegB33, Sum2, Carry2 );
DifferenceSum2 <= ( Carry2 & '0' ) + Sum2;
Difference2 <= DifferenceSum2( width downto 0 );
absoulte2 : absolute port map( Difference2, Value2 );
-- | G32 - G34 |
Neg3 <= not G34 + '1';
Diff3 : CSAHalfAdder port map( G32, Neg3, Sum3, Carry3 );
DifferenceSum3 <= ( Carry3 & '0' ) + Sum3;
Difference3 <= DifferenceSum3( width downto 0 );
absoulte3 : absolute port map( Difference3, Value3 );
-- Dver = | B31 - B33 | + | B35 - B33 | + | G32 - G34 |
Dhor : CSAFullAdder port map( Value1, Value2, Value3, SumDhor, CarryDhor );
DifferenceSumDhor <= ( CarryDhor & '0' ) + SumDhor;
DifferenceDhor <= "00" & DifferenceSumDhor( width downto 0 );
---------------------------------------------------------------------------------------------------------------------
-- | B13 - B33 |
Diff4 : CSAHalfAdder port map( B13, NegB33, Sum4, Carry4 );
DifferenceSum4 <= ( Carry4 & '0' ) + Sum4;
Difference4 <= DifferenceSum4( width downto 0 );
absoulte4 : absolute port map( Difference4, Value4 );
-- | B53 - B33 |
Diff5 : CSAHalfAdder port map( B53, NegB33, Sum5, Carry5 );
DifferenceSum5 <= ( Carry5 & '0' ) + Sum5;
Difference5 <= DifferenceSum5( width downto 0 );
absoulte5 : absolute port map( Difference5, Value5 );
-- | G23 - G43 |
Neg6 <= not G43 + '1';
Diff6 : CSAHalfAdder port map( G23, Neg6, Sum6, Carry6 );
DifferenceSum6 <= ( Carry6 & '0' ) + Sum6;
Difference6 <= DifferenceSum6( width downto 0 );
absoulte6 : absolute port map( Difference6, Value6 );
-- Dver = | B13 - B33 | + | B53 - B33 | + | G23 - G43 |
Dver : CSAFullAdder port map( Value4, Value5, Value6, SumDver, CarryDver );
DifferenceSumDver <= ( CarryDver & '0' ) + SumDver;
DifferenceDver <= "00" & DifferenceSumDver( width downto 0 );
-------------------------------------------------------------------------------------------------------------------
-- calculate IHorizontal value
-- ( G32 + G34 ) / 2
Ihor1 : CSAHalfAdder port map( G32, G34, SumIhor1, CarryIhor1 );
IhorSum1 <= ( CarryIhor1 & '0' ) + SumIhor1;
IHorizontal1 <= IhorSum1( width + 1 downto 1 );
-- B33 / 4
IHorizontal2 <= "00" & B33( width downto 2 );
-- ( B31 + B35 ) / 8
Ihor3 : CSAHalfAdder port map( B31, B35, SumIhor3, CarryIhor3 );
IhorSum30 <= ( CarryIhor3 & '0' ) + SumIhor3;
IhorSum31 <= "00" & IhorSum30( width + 1 downto 3 );
IHorizontal3 <= not IhorSum31 + '1';
-- ( G32 + G34 ) / 2 + B33 / 4 + ( B31 + B35 ) / 8
Ihor : CSAFullAdder port map( IHorizontal1, IHorizontal2, IHorizontal3, SumIhor, CarryIhor );
IhorSum <= ( CarryIhor & '0' ) + SumIhor;
IHorizontal <= IhorSum( width downto 0 );
---------------------------------------------------------------------------------------------------------------------
-- calculate IVertical value
-- ( G23 + G43 ) / 2
Iver1 : CSAHalfAdder port map( G23, G43, SumIver1, CarryIver1 );
IverSum1 <= ( CarryIver1 & '0' ) + SumIver1;
IVertical1 <= IverSum1( width + 1 downto 1 );
-- B33 / 4
IVertical2 <= IHorizontal2;
-- ( B13 + B53 ) / 8
Iver3 : CSAHalfAdder port map( B13, B53, SumIver3, CarryIver3 );
IverSum30 <= ( CarryIver3 & '0' ) + SumIver3;
IverSum31 <= "00" & IverSum30( width + 1 downto 3 );
IVertical3 <= not IverSum31 + '1';
-- ( G23 + G43 ) / 2 + B33 / 4 + ( B13 + B53 ) / 8
Iver : CSAFullAdder port map( IVertical1, IVertical2, IVertical3, SumIver, CarryIver );
IverSum <= ( CarryIver & '0' ) + SumIver;
IVertical <= IverSum( width downto 0 );
----------------------------------------------------------------------------------------------------------------
-- ( Ihor + Iver ) / 2
Diff7 : CSAHalfAdder port map( IHorizontal, IVertical, Sum7, Carry7 );
DifferenceSum7 <= ( Carry7 & '0' ) + Sum7;
Difference7 <= DifferenceSum7( width + 1 downto 1 );
PartG : CalculateG port map( Difference0, Difference01, IHorizontal, IVertical, Difference7, DifferenceDver, DifferenceDhor, ElementG );
G <= ElementG;
end TABLE;
|
mit
|
04ac67e1db700760e459a2db3f15f6d6
| 0.580673 | 3.218308 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/fifo_w32_d2_A.vhd
| 1 | 4,597 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w32_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w32_d2_A_shiftReg;
architecture rtl of fifo_w32_d2_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fifo_w32_d2_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w32_d2_A is
component fifo_w32_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2);
if (mOutPtr = conv_std_logic_vector(0, 2)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w32_d2_A_shiftReg : fifo_w32_d2_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
6ce168007d6a1e320bbd0535f23c79e1
| 0.532956 | 3.420387 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/tb/tb_LLP.vhd
| 1 | 6,660 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/23/2017 08:00:19 PM
-- Design Name:
-- Module Name: tb_LLP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.mypkg.all;
entity tb_LLP is
-- Port ( );
end tb_LLP;
architecture Behavioral of tb_LLP is
component LLP is
Generic(
kMaxLaneCount : natural := 4;
--PPI
kLaneCount : natural range 1 to 4 := 2 --[1,2,4]
);
Port (
SAxisClk : in STD_LOGIC;
--Slave AXI-Stream
sAxisTdata : in std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
sAxisTkeep : in std_logic_vector(kMaxLaneCount - 1 downto 0);
sAxisTvalid : in std_logic;
sAxisTready : out std_logic;
sAxisTlast : in std_logic;
--TODO: sAxisTdest : in std_logic;
MAxisClk : in std_logic;
--Master AXI-Stream
mAxisTdata : out std_logic_vector(40 - 1 downto 0);
mAxisTvalid : out std_logic;
mAxisTready : in std_logic;
mAxisTlast : out std_logic;
mAxisTuser : out std_logic_vector(0 downto 0);
sOverflow : out std_logic;
aRst : in std_logic
);
end component LLP;
constant kSClkPeriod : time := 10ns;
constant kMClkPeriod : time := 13ns;
constant kMaxLaneCount : natural := 4;
constant kPixPerBeat : natural := 4;
type mem is array (natural range <>) of std_logic_vector(7 downto 0);
--LSByte first
constant fs_err : mem := (x"00", x"01", x"C0", x"1A", x"EF", x"BE"); --frame start with two ECC errors and extra bytes (if no EoT processing is done in PHY)
constant fs : mem := (x"00", x"01", x"00", x"1A"); --frame start with no ECC errors
constant longRAW10_cnt_err : mem := (x"2B", x"01", x"00", x"0D", x"00", x"00", x"00"); --shorter line
constant longRAW10_err : mem := (x"2B", x"0A", x"80", x"2E", x"00", x"00", x"00", x"00", x"E4", x"01", x"01", x"01", x"01", x"E4", x"E9", x"FB", x"EF", x"BE", x"AD", x"DE"); --active line RAW8, error in third byte 00, extra bytes
constant fe : mem := (x"01", x"01", x"00", x"0D"); --frame end with one ECC error (error in last byte 1D)
signal sAxisTdata : std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
signal sAxisTkeep : std_logic_vector(kMaxLaneCount - 1 downto 0);
signal sAxisTvalid, sAxisTready, sAxisTlast : std_logic;
signal MAxisClk, SAxisClk : std_logic := '0';
signal mAxisTdata : std_logic_vector(kPixPerBeat*10 - 1 downto 0);
signal mAxisTvalid, mAxisTready, mAxisTlast : std_logic;
signal mAxisTuser : std_logic_vector(0 downto 0);
signal aRst : std_logic;
begin
--TODO generate for all lane counts
SAxisClk <= not SAxisClk after kSClkPeriod / 2;
MAxisClk <= not MAxisClk after kMClkPeriod / 2;
WriteProc: process
variable iLane : natural := 0;
procedure SendPacket(test_vect : in mem) is
begin
sAxisTkeep <= (others => '0');
sAxisTlast <= '0';
iLane := 0;
for i in 0 to test_vect'length - 1 loop
sAxisTdata((iLane+1)*8-1 downto iLane*8) <= test_vect(i);
sAxisTkeep(iLane) <= '1';
if (iLane = 3 or i = test_vect'length - 1) then
sAxisTvalid <= '1';
if (i = test_vect'length - 1) then
sAxisTlast <= '1';
end if;
wait until Rising_Edge(SAxisClk) and sAxisTready = '1';
iLane := 0;
sAxisTkeep <= (others => '0');
else
iLane := iLane + 1;
end if;
end loop;
sAxisTvalid <= '0';
end procedure;
begin
sAxisTvalid <= '0';
sAxisTdata <= (others => '0');
sAxisTkeep <= (others => '0');
aRst <= '1';
wait for max(kSclkPeriod, kMClkPeriod)*5;
aRst <= '1';
wait for max(kSclkPeriod, kMClkPeriod)*5;
aRst <= '0';
wait until Rising_Edge(SAxisClk) and sAxisTready = '1'; --wait for LLP to complete reset
SendPacket(fs_err);
--switch to low-power state between packets
wait until Rising_Edge(SAxisClk);
wait until Rising_Edge(SAxisClk);
SendPacket(fs);
wait until Rising_Edge(SAxisClk);
wait until Rising_Edge(SAxisClk);
SendPacket(longRAW10_cnt_err);
wait until Rising_Edge(SAxisClk);
wait until Rising_Edge(SAxisClk);
SendPacket(longRAW10_err);
wait until Rising_Edge(SAxisClk);
wait until Rising_Edge(SAxisClk);
SendPacket(fe);
wait;
end process;
ReadProc: process
begin
mAxisTready <= '0';
wait until sAxisTvalid = '1' and sAxisTready = '1' and Rising_Edge(SAxisClk); --first write
mAxisTready <= '1';
for i in 0 to 8 - 1 loop
if (i mod kPixPerBeat = 0) then
wait until Rising_Edge(MAxisClk) and mAxisTready = '1' and mAxisTvalid = '1';
end if;
if (i/kPixPerBeat = 0) then
assert(mAxisTuser="1") report "Tuser not asserted at SOF" severity failure;
else
assert(mAxisTuser="0") report "Tuser asserted mid-frame" severity failure;
end if;
assert (to_unsigned(i,10)=unsigned(mAxisTdata(((i mod kPixPerBeat)+1)*10-1 downto (i mod kPixPerBeat)*10))) report "Output data does not match input" severity failure;
if (i/kPixPerBeat = (8-1)/kPixPerBeat) then
assert(mAxisTlast='1') report "Tlast not asserted at EOL" severity failure;
else
assert(mAxisTlast='0') report "Tlast asserted mid-line" severity failure;
end if;
end loop;
end process;
DUT: LLP
Generic map(
kMaxLaneCount => 4,
kLaneCount => 2 --[1,2,4]
)
Port map(
SAxisClk => SAxisClk,
--Slave AXI-Stream
sAxisTdata => sAxisTdata,
sAxisTkeep => sAxisTkeep,
sAxisTvalid => sAxisTvalid,
sAxisTready => sAxisTready,
sAxisTlast => sAxisTlast,
MAxisClk => MAxisClk,
--Master AXI-Stream
mAxisTdata => mAxisTdata,
mAxisTvalid => mAxisTvalid,
mAxisTready => mAxisTready,
mAxisTlast => mAxisTlast,
mAxisTuser => mAxisTuser,
sOverflow => open,
aRst => aRst
);
end Behavioral;
|
mit
|
0cfcd82009e0138209df4d24538a264d
| 0.598348 | 3.825388 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/fifo_w12_d2_A.vhd
| 1 | 4,437 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w12_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w12_d2_A_shiftReg;
architecture rtl of fifo_w12_d2_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w12_d2_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w12_d2_A is
component fifo_w12_d2_A_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w12_d2_A_shiftReg : fifo_w12_d2_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
3f758873792aa582134296a6a20811d7
| 0.52558 | 3.4637 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/Branch.vhd
| 1 | 2,343 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity Branch is
port (
clk : in std_logic;
d : in branch_in_t;
q : out branch_out_t := (
emit_tag => (others => '0'),
emit_link => (others => '0'),
emit_target => (others => '0')));
end Branch;
architecture twoproc of Branch is
signal c : std_logic_vector(2 downto 0) := "000";
signal a : value_t := (others => '0');
signal b : value_t := (others => '0');
signal target : blkram_addr := (others => '0');
signal link : blkram_addr := (others => '0');
begin
sequential : process(clk)
begin
if rising_edge(clk) then
c <= d.code; -- eliminating redundant bit
a <= d.val_a;
b <= d.val_b;
q.emit_tag <= d.tag_l;
q.emit_link <= d.val_l;
target <= d.val_t;
link <= d.val_l;
end if;
end process;
combinatorial : process(c, a, b, target, link)
variable ieq, ilt, feq, flt : boolean;
variable tmp_lt, tmp_z_a, tmp_z_b : boolean;
variable result : boolean;
constant z31 : std_logic_vector(30 downto 0) := (others => '0');
begin
tmp_lt := unsigned(a(30 downto 0)) < unsigned(b(30 downto 0));
tmp_z_a := a(30 downto 0) = z31;
tmp_z_b := b(30 downto 0) = z31;
ieq := a = b;
ilt := (a(31) = '1' and b(31) = '0') or
((a(31) = b(31)) and tmp_lt);
feq := ieq or (tmp_z_a and tmp_z_b);
flt := (a(31) = '1' and b(31) = '0') or
(a(31) = '0' and b(31) = '0' and tmp_lt) or
(a(31) = '1' and b(31) = '1' and not tmp_lt);
case c is
when "000" => result := ieq;
when "001" => result := not ieq;
when "010" => result := ilt;
when "011" => result := not ilt and not ieq;
when "100" => result := feq;
when "101" => result := not feq;
when "110" => result := flt and not feq;
when "111" => result := not flt and not feq;
when others => assert false;
end case;
if result then
q.emit_target <= target;
else
q.emit_target <= link;
end if;
end process;
end twoproc;
|
bsd-2-clause
|
09e71cd734a392fb879325cb8190714f
| 0.475032 | 3.249653 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/fifo_w16_d5_A.vhd
| 2 | 4,437 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w16_d5_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 6);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w16_d5_A_shiftReg;
architecture rtl of fifo_w16_d5_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w16_d5_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 6);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w16_d5_A is
component fifo_w16_d5_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 6);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w16_d5_A_shiftReg : fifo_w16_d5_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
622251fe982f3037cf9d00f49a349338
| 0.52558 | 3.4637 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
second_level_CLA.vhd
| 1 | 1,803 |
-------------------------------------------------------------------------------
--
-- Title : second_level_CLA
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\second_level_CLA.vhd
-- Generated : Sun Nov 20 16:59:32 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {second_level_CLA} architecture {structural}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity second_level_CLA is
port(
c0: in std_logic;
Pi: in std_logic_vector (3 downto 0);
Gi: in std_logic_vector (3 downto 0);
Ci: out std_logic_vector (4 downto 1);
P64bit: out std_logic;
G64bit: out std_logic
);
end second_level_CLA;
--}} End of automatically maintained section
architecture structural of second_level_CLA is
begin
Ci(1) <= Gi(0) or (Pi(0) and c0); --C1 = c4
Ci(2) <= Gi(1) or (Pi(1) and Gi(0)) or (Pi(1) and Pi(0) and c0); --C2 = c8
Ci(3) <= Gi(2) or (Pi(2) and Gi(1)) or (Pi(2) and Pi(1) and Gi(0)) or (Pi(2) and Pi(1) and Pi(0) and c0); --C3 == c12
Ci(4) <= Gi(3) or (Pi(3) and Gi(2)) or (Pi(3) and Pi(2) and Gi(1)) or (Pi(3) and Pi(2) and Pi(1) and Gi(0)) or (Pi(3) and Pi(2) and Pi(1) and Pi(0) and c0); --C4 ==c16
P64bit <= Pi(3) and Pi(2) and Pi(1) and Pi(0);
G64bit <= Gi(3) and Gi(2) and Gi(1) and Gi(0);
end structural;
|
apache-2.0
|
204d3df415591942ddddbbdb984dcf34
| 0.480311 | 3.066327 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
xor_2.vhd
| 1 | 1,435 |
-------------------------------------------------------------------------------
--
-- Title : xor_2_structural
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\xor_2.vhd
-- Generated : Thu Nov 17 10:25:39 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {xor_2_structural} architecture {struct}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity xor_2_structural is
port(
i1, i2: in std_logic;
o1: out std_logic
);
end xor_2_structural;
--}} End of automatically maintained section
architecture struct of xor_2_structural is
signal inv1, inv2, and1, and2: std_logic;
begin
u1: entity inv port map(i1 => i1, o1 => inv1);
u2: entity inv port map(i1 => i2, o1 => inv2);
u3: entity and_2 port map(i1 => inv1, i2 => i2, o1 => and1);
u4: entity and_2 port map(i1 => i1, i2 => inv2, o1 => and2);
u5: entity or_2 port map(i1=> and1, i2 => and2, o1 => o1);
end struct;
|
apache-2.0
|
ab6f8a0de7e7220d8e93544b2d1ece56
| 0.469686 | 3.5 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/CountEventsUP.vhd
| 1 | 1,726 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CountEventsUP IS
END CountEventsUP;
ARCHITECTURE behavior OF CountEventsUP IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CountEvents
PORT(
Entrada : IN std_logic;
Reset : IN std_logic;
Output : OUT std_logic_vector(0 to 31)
);
END COMPONENT;
--Inputs
signal Entrada : std_logic := '0';
signal Reset : std_logic := '0';
--Outputs
signal Output : std_logic_vector(0 to 31);
constant Entrada_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CountEvents PORT MAP (
Entrada => Entrada,
Reset => Reset,
Output => Output
);
-- Clock process definitions
Entrada_process :process
begin
Entrada <= '0';
wait for Entrada_period/2;
Entrada <= '1';
wait for Entrada_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Reset <= '1';
wait for 100 ns;
Reset <= '0';
wait for Entrada_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
122a33b02f95dd265d73ffcd44fd02bb
| 0.543453 | 4.652291 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/top_TB.vhd
| 2 | 2,202 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_TB IS
END top_TB;
ARCHITECTURE behavior OF top_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
entrada : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
led : OUT std_logic_vector(6 downto 0);
led_unidades : OUT std_logic_vector(1 downto 0);
selector : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal led : std_logic_vector(6 downto 0);
signal led_unidades : std_logic_vector(1 downto 0);
signal selector : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns; --50MHZ
constant s_entrada_period : time := 8 us; --125KHZ
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
entrada => entrada,
clk => clk,
reset => reset,
led => led,
led_unidades => led_unidades,
selector => selector
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
s_entrada_process :process
begin
entrada <= '0';
wait for s_entrada_period/2;
entrada <= '1';
wait for s_entrada_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset<='1';
wait for 100 ns;
reset<='0';
wait for 2000ms;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
2fe437c585da0b469e59a8a2b14e5111
| 0.561762 | 4.025594 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/start_for_Loop_lojbC.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Loop_lojbC_shiftReg;
architecture rtl of start_for_Loop_lojbC_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Loop_lojbC is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Loop_lojbC is
component start_for_Loop_lojbC_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Loop_lojbC_shiftReg : start_for_Loop_lojbC_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
4daf46a6be0843caedc3fee171624c36
| 0.53118 | 3.549407 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/src/PkgZmodDigitizer.vhd
| 1 | 77,106 |
-------------------------------------------------------------------------------
--
-- File: PkgZmodDigitizer.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: ZmodScopeController
-- Date: 2021
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This package contains the constants and functions used for the
-- ZmodDigitizerController IP
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PkgZmodDigitizer is
-- Zmod Scope variants identifier
constant kZmodDigitizer1430_105 : integer := 0; -- Zmod Digitizer 1430 - 105 (AD9648)
constant kZmodDigitizer1030_40 : integer := 1; -- Zmod Digitizer 1030 - 40 (AD9204)
constant kZmodDigitizer1030_125 : integer := 2; -- Zmod Digitizer 1030 - 125 (AD9608)
constant kZmodDigitizer1230_40 : integer := 3; -- Zmod Digitizer 1230 - 40 (AD9231)
constant kZmodDigitizer1230_125 : integer := 4; -- Zmod Digitizer 1230 - 125 (AD9628)
constant kZmodDigitizer1430_40 : integer := 5; -- Zmod Digitizer 1430 - 40 (AD9251)
constant kZmodDigitizer1430_125 : integer := 6; -- Zmod Digitizer 1430 - 125 (AD9648)
--Timing parameters
constant kSysClkPeriod : time := 10ns; -- System Clock Period
constant ktS : time := 2 ns; -- Setup time between CSB and SCLK
constant ktH : time := 2 ns; -- Hold time between CSB and SCLK
constant ktDS : time := 2 ns; -- Setup time between the data and the rising edge of SCLK
constant ktDH : time := 2 ns; -- Hold time between the data and the rising edge of SCLK
constant ktclk : time := 40 ns; -- minimum period of the SCLK
constant kSclkHigh : time := 10 ns; -- SCLK pulse width high (min)
constant kSclkLow : time := 10 ns; -- SCLK pulse width low (min)
--constant kSclkT_Max : time := 10 ns; -- SCLK pulse width low (min)
constant kSclkT_Min : time := 50 ns; -- SCLK pulse width low (min)
constant kTdcoMax : time := 4.4 ns;
constant kRelayConfigTime : time := 3ms; -- relay set and reset signals
--ADC Model Registers
constant aReg00_Mask : std_logic_vector(7 downto 0) := "01100110";
--Implementation constants
constant kCS_PulseWidthHigh : integer := 31; --CS pulse width high not specified in AD9648
constant kSPI_DataWidth : integer := 8; --ADI_SPI module data width
constant kSPI_CommandWidth : integer := 16; --ADI_SPI module command width
constant kSPI_AddrWidth : integer := kSPI_CommandWidth - 3; --ADI_SPI module command width
constant kSPI_SysClkDiv : integer := 4; --ADI_SPI module system clock divide constant
--No minimum SPI clock frequency specified by AD9648. The maximum frequency is 25MHz.
type ADC_SPI_Commands_t is array (19 downto 0) of std_logic_vector(23 downto 0);
type ADC_SPI_Readback_t is array (19 downto 0) of std_logic_vector(7 downto 0);
constant kAD96xx_SPI_Cmd : ADC_SPI_Commands_t := (x"000500", --19 Device index: none
x"000800", --18 Power modes: Normal operation
x"000502", --17 Device index: B
x"000800", --16 Power modes: Normal operation
x"000501", --15 Device index: A
x"003A02", --14 Sync control : continuous | sync enable | 0
x"001781", --13 Output Delay; DCO delay enabled; 1.12ns
x"001511", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"002A00", --11 Overrange control: output disable
x"000B03", --10 Clck Divide: 4
x"001680", --9 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"000500", --8 Device index: none
x"001421", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"000803", --6 Power modes: digital reset
x"000502", --5 Device index: B
x"001431", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"000803", --3 Power modes: digital reset
x"000501", --2 Device index: A
x"000100", --1 Chip ID: read chip ID
x"00003C" --0 SPI Port Config: soft reset
);
constant kAD96xx_SPI_Rdbck : ADC_SPI_Readback_t:= (x"00", --19 Device index: none
x"00", --18 Power modes: Normal operation
x"02", --17 Device index: B
x"00", --16 Power modes: Normal operation
x"01", --15 Device index: A
x"02", --14 Sync control : continuous | sync enable | 0
x"81", --13 Output Delay; DCO delay enabled; 1.12ns
x"11", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"00", --11 Overrange control: output disable
x"03", --10 Clck Divide: 4
x"80", --9 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"00", --8 Device index: none
x"21", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"03", --6 Power modes: digital reset
x"02", --5 Device index: B
x"31", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"03", --3 Power modes: digital reset
x"01", --2 Device index: A
x"88", --1 Chip ID expected value:88
x"18" --0 SPI Port Config: soft reset
);
constant kAD92xx_SPI_Cmd : ADC_SPI_Commands_t := (x"000500", --19 Device index: none
x"000800", --18 Power modes: Normal operation
x"000502", --17 Device index: B
x"000800", --16 Power modes: Normal operation
x"000501", --15 Device index: A
x"010002", --14 Sync control : continuous | sync enable | 0
x"001781", --13 Output Delay; DCO delay enabled; 1.12ns
x"001511", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"002A00", --11 Overrange control: output disable
x"000B03", --10 Clck Divide: 4
x"000500", --9 Device index: none
x"001680", --8 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"001421", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"000803", --6 Power modes: digital reset
x"000502", --5 Device index: B
x"001431", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"000803", --3 Power modes: digital reset
x"000501", --2 Device index: A
x"000100", --1 Chip ID: read chip ID
x"00003C" --0 SPI Port Config: soft reset
);
constant kAD92xx_SPI_Rdbck : ADC_SPI_Readback_t:= (x"00", --19 Device index: none
x"00", --18 Power modes: Normal operation
x"02", --17 Device index: B
x"00", --16 Power modes: Normal operation
x"01", --15 Device index: A
x"02", --14 Sync control : continuous | sync enable | 0
x"81", --13 Output Delay; DCO delay enabled; 1.12ns
x"11", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"00", --11 Overrange control: output disable
x"03", --10 Clck Divide: 4
x"00", --9 Device index: none
x"80", --8 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"21", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"03", --6 Power modes: digital reset
x"02", --5 Device index: B
x"31", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"03", --3 Power modes: digital reset
x"01", --2 Device index: A
x"88", --1 Chip ID expected value:88
x"18" --0 SPI Port Config: soft reset
);
constant kSetTrsfReg : std_logic_vector(23 downto 0) := x"00FF01";
--ADC Register addresses
constant kDevIndex : std_logic_vector(12 downto 0) := "00000" & x"05";
constant kPwrModes : std_logic_vector(12 downto 0) := "00000" & x"08";
constant kSyncCtrll : std_logic_vector(12 downto 0) := "00000" & x"3A";
constant kOutDly : std_logic_vector(12 downto 0) := "00000" & x"17";
constant kOutAdj : std_logic_vector(12 downto 0) := "00000" & x"15";
constant kOvrrCtrl : std_logic_vector(12 downto 0) := "00000" & x"2A";
constant kClkPhCtrl : std_logic_vector(12 downto 0) := "00000" & x"16";
constant kClkDiv : std_logic_vector(12 downto 0) := "00000" & x"0B";
constant kOutMode : std_logic_vector(12 downto 0) := "00000" & x"14";
constant kChipID : std_logic_vector(12 downto 0) := "00000" & x"01";
constant kSPI_PortCfg : std_logic_vector(12 downto 0) := "00000" & x"01";
--ID Register value for supported Zmods
constant AD9648_ID : std_logic_vector(7 downto 0) := x"88";
constant AD9204_ID : std_logic_vector(7 downto 0) := x"25";
constant AD9608_ID : std_logic_vector(7 downto 0) := x"9C";
constant AD9231_ID : std_logic_vector(7 downto 0) := x"24";
constant AD9628_ID : std_logic_vector(7 downto 0) := x"89";
constant AD9251_ID : std_logic_vector(7 downto 0) := x"23";
constant AD9648_Grade : std_logic_vector(7 downto 0) := x"40";
constant AD9204_Grade : std_logic_vector(7 downto 0) := x"10";
constant AD9608_Grade : std_logic_vector(7 downto 0) := x"50";
constant AD9231_Grade : std_logic_vector(7 downto 0) := x"10";
constant AD9628_Grade : std_logic_vector(7 downto 0) := x"50";
constant AD9251_Grade : std_logic_vector(7 downto 0) := x"10";
-- Constant indicating the number of configurable registers present in the CDCE6214-Q1
constant kCDCE_RegisterNr : integer := 86;
constant kCDCE_RegNrZeroBased : integer := (kCDCE_RegisterNr-1);
-- Constant indicating the number of frequency configs for the CDCE6214-Q1
constant kCDCE_FreqCfgsNr : integer := 7;
type CDCE_TWI_Masks_t is array (0 to 85) of std_logic_vector(15 downto 0);
type CDCE_TWI_Commands_t is array (0 to 85) of std_logic_vector(31 downto 0);
type CDCE_I2C_Cmd_Array_t is array (0 to (kCDCE_FreqCfgsNr - 1)) of CDCE_TWI_Commands_t;
constant CDCE_I2C_Cmds : CDCE_I2C_Cmd_Array_t := (
(x"00550000",
x"00540000",
x"00530000",
x"00520000",
x"00510004",
x"00500000",
x"004F0208",
x"004E0000",
x"004D0000",
x"004C0188",
x"004B8008",
x"004AA181",
x"00491000",
x"00480004",
x"00470006",
x"00460008",
x"0045A181",
x"00441000",
x"00430004",
x"00420006",
x"00410008",
x"0040A181",
x"003F1000",
x"003E0004",
x"003D0000",
x"003C6008",
x"003B0008",
x"003A502C",
x"00391000",
x"00380004",
x"0037001E",
x"00363400",
x"00350069",
x"00345000",
x"003340C0",
x"003207C0",
x"0031001F",
x"0030180A",
x"002F0528",
x"002E0000",
x"002D4F80",
x"002C0318",
x"002B0051",
x"002A0002",
x"00290000",
x"00280000",
x"00270000",
x"00260000",
x"00250000",
x"00240000",
x"00230000",
x"00220000",
x"00212710",
x"00200000",
x"001F0000",
x"001E0040",
x"001D0000",
x"001C0000",
x"001B0004",
x"001A0000",
x"00190401",
x"00188718",
x"00170000",
x"00160000",
x"00150000",
x"00140000",
x"00130000",
x"00120000",
x"001126C4",
x"0010921F",
x"000FA037",
x"000E0000",
x"000D0000",
x"000C0000",
x"000B0000",
x"000A0000",
x"00090000",
x"00080000",
x"00070000",
x"00060000",
x"00050008",
x"00040070",
x"00030000",
x"00020002",
x"00012222",
x"00003004"
),--122.88M
(x"00550000",
x"00540000",
x"00530000",
x"00520000",
x"00510004",
x"00500000",
x"004F0208",
x"004E0000",
x"004D0000",
x"004C0188",
x"004B8008",
x"004AA181",
x"00491000",
x"00480008",
x"00470006",
x"00460008",
x"0045A181",
x"00441000",
x"00430008",
x"00420006",
x"00410008",
x"0040A181",
x"003F1000",
x"003E0008",
x"003D0000",
x"003C6008",
x"003B0008",
x"003A502C",
x"00391000",
x"00380008",
x"0037001E",
x"00363400",
x"00350069",
x"00345000",
x"003340C0",
x"003207C0",
x"0031001F",
x"0030300A",
x"002F0550",
x"002E0000",
x"002D4F80",
x"002C0318",
x"002B0051",
x"002A0002",
x"00290000",
x"00280000",
x"00270000",
x"00260000",
x"00250000",
x"00240000",
x"00230000",
x"00220000",
x"00212710",
x"00200000",
x"001F0000",
x"001E007D",
x"001D0000",
x"001C0000",
x"001B0004",
x"001A0000",
x"00190402",
x"00188718",
x"00170000",
x"00160000",
x"00150000",
x"00140000",
x"00130000",
x"00120000",
x"001126C4",
x"0010921F",
x"000FA037",
x"000E0000",
x"000D0000",
x"000C0000",
x"000B0000",
x"000A0000",
x"00090000",
x"00080000",
x"00070000",
x"00060000",
x"00050008",
x"00040070",
x"00030000",
x"00020002",
x"00012222",
x"00003004"
),--50M
(x"00550000",
x"00540000",
x"00530000",
x"00520000",
x"00510004",
x"00500000",
x"004F0208",
x"004E0000",
x"004D0000",
x"004C0188",
x"004B8008",
x"004AA181",
x"00491000",
x"00480006",
x"00470006",
x"00460008",
x"0045A181",
x"00441000",
x"00430006",
x"00420006",
x"00410008",
x"0040A181",
x"003F1000",
x"003E0006",
x"003D0000",
x"003C6008",
x"003B0008",
x"003A502C",
x"00391000",
x"00380006",
x"0037001E",
x"00363400",
x"00350069",
x"00345000",
x"003340C0",
x"003207C0",
x"0031001F",
x"0030300A",
x"002F0528",
x"002E0000",
x"002D4F80",
x"002C0318",
x"002B0051",
x"002A0002",
x"00290000",
x"00280000",
x"00270000",
x"00260000",
x"00250000",
x"00240000",
x"00230000",
x"00220000",
x"00212710",
x"00200000",
x"001F0000",
x"001E007D",
x"001D0000",
x"001C0000",
x"001B0004",
x"001A0000",
x"00190402",
x"00188718",
x"00170000",
x"00160000",
x"00150000",
x"00140000",
x"00130000",
x"00120000",
x"001126C4",
x"0010921F",
x"000FA037",
x"000E0000",
x"000D0000",
x"000C0000",
x"000B0000",
x"000A0000",
x"00090000",
x"00080000",
x"00070000",
x"00060000",
x"00050008",
x"00040070",
x"00030000",
x"00020002",
x"00012222",
x"00003004"
),--80M
(x"00550000",
x"00540000",
x"00530000",
x"00520000",
x"00510004",
x"00500000",
x"004F0208",
x"004E0000",
x"004D0000",
x"004C0188",
x"004B8008",
x"004AA181",
x"00491000",
x"00480004",
x"00470006",
x"00460008",
x"0045A181",
x"00441000",
x"00430004",
x"00420006",
x"00410008",
x"0040A181",
x"003F1000",
x"003E0004",
x"003D0000",
x"003C6008",
x"003B0008",
x"003A502C",
x"00391000",
x"00380004",
x"0037001E",
x"00363400",
x"00350069",
x"00345000",
x"003340C0",
x"003207C0",
x"0031001F",
x"0030300A",
x"002F0550",
x"002E0000",
x"002D4F80",
x"002C0318",
x"002B0051",
x"002A0002",
x"00290000",
x"00280000",
x"00270000",
x"00260000",
x"00250000",
x"00240000",
x"00230000",
x"00220000",
x"00212710",
x"00200000",
x"001F0000",
x"001E007D",
x"001D0000",
x"001C0000",
x"001B0004",
x"001A0000",
x"00190402",
x"00188718",
x"00170000",
x"00160000",
x"00150000",
x"00140000",
x"00130000",
x"00120000",
x"001126C4",
x"0010921F",
x"000FA037",
x"000E0000",
x"000D0000",
x"000C0000",
x"000B0000",
x"000A0000",
x"00090000",
x"00080000",
x"00070000",
x"00060000",
x"00050008",
x"00040070",
x"00030000",
x"00020002",
x"00012222",
x"00003004"
),--100M
(x"00550000",
x"00540000",
x"00530000",
x"00520000",
x"00510004",
x"00500000",
x"004F0208",
x"004E0000",
x"004D0000",
x"004C0188",
x"004B8008",
x"004AA181",
x"00491000",
x"00480006",
x"00470006",
x"00460008",
x"0045A181",
x"00441000",
x"00430006",
x"00420006",
x"00410008",
x"0040A181",
x"003F1000",
x"003E0006",
x"003D0000",
x"003C6008",
x"003B0008",
x"003A502C",
x"00391000",
x"00380005",
x"0037001E",
x"00363400",
x"00350069",
x"00345000",
x"003340C0",
x"003207C0",
x"0031001F",
x"0030200A",
x"002F0500",
x"002E0000",
x"002D4F80",
x"002C0318",
x"002B0051",
x"002A0002",
x"00290000",
x"00280000",
x"00270000",
x"00260000",
x"00250000",
x"00240000",
x"00230000",
x"00220000",
x"00212710",
x"00200000",
x"001F0000",
x"001E0044",
x"001D0000",
x"001C0000",
x"001B0004",
x"001A0000",
x"00190401",
x"00188718",
x"00170000",
x"00160000",
x"00150000",
x"00140000",
x"00130000",
x"00120000",
x"001126C4",
x"0010921F",
x"000FA037",
x"000E0000",
x"000D0000",
x"000C0000",
x"000B0000",
x"000A0000",
x"00090000",
x"00080000",
x"00070000",
x"00060000",
x"00050008",
x"00040070",
x"00030000",
x"00020002",
x"00012222",
x"00003004"
),--108.8M
(x"00550000",
x"00540000",
x"00530000",
x"00520000",
x"00510004",
x"00500000",
x"004F0208",
x"004E0000",
x"004D0000",
x"004C0188",
x"004B8008",
x"004AA181",
x"00491000",
x"00480004",
x"00470006",
x"00460008",
x"0045A181",
x"00441000",
x"00430004",
x"00420006",
x"00410008",
x"0040A181",
x"003F1000",
x"003E0004",
x"003D0000",
x"003C6008",
x"003B0008",
x"003A502C",
x"00391000",
x"00380004",
x"0037001E",
x"00363400",
x"00350069",
x"00345000",
x"003340C0",
x"003207C0",
x"0031001F",
x"0030300A",
x"002F0528",
x"002E0000",
x"002D4F80",
x"002C0318",
x"002B0051",
x"002A0002",
x"00290000",
x"00280000",
x"00270000",
x"00260000",
x"00250000",
x"00240000",
x"00230000",
x"00220000",
x"00212710",
x"00200000",
x"001F0000",
x"001E007D",
x"001D0000",
x"001C0000",
x"001B0004",
x"001A0000",
x"00190402",
x"00188718",
x"00170000",
x"00160000",
x"00150000",
x"00140000",
x"00130000",
x"00120000",
x"001126C4",
x"0010921F",
x"000FA037",
x"000E0000",
x"000D0000",
x"000C0000",
x"000B0000",
x"000A0000",
x"00090000",
x"00080000",
x"00070000",
x"00060000",
x"00050008",
x"00040070",
x"00030000",
x"00020002",
x"00012222",
x"00003004"
),--120M
(x"00550000",
x"00540000",
x"00530000",
x"00520000",
x"00510004",
x"00500000",
x"004F0208",
x"004E0000",
x"004D0000",
x"004C0188",
x"004B8008",
x"004AA181",
x"00491000",
x"00480005",
x"00470006",
x"00460008",
x"0045A181",
x"00441000",
x"00430005",
x"00420006",
x"00410008",
x"0040A181",
x"003F1000",
x"003E0005",
x"003D0000",
x"003C6008",
x"003B0008",
x"003A502C",
x"00391000",
x"00380005",
x"0037001E",
x"00363400",
x"00350069",
x"00345000",
x"003340C0",
x"003207C0",
x"0031001F",
x"0030180A",
x"002F0500",
x"002E0000",
x"002D4F80",
x"002C0318",
x"002B0051",
x"002A0002",
x"00290000",
x"00280000",
x"00270000",
x"00260000",
x"00250000",
x"00240000",
x"00230000",
x"00220000",
x"00212710",
x"00200000",
x"001F0000",
x"001E0041",
x"001D0000",
x"001C0000",
x"001B0004",
x"001A0000",
x"00190401",
x"00188718",
x"00170000",
x"00160000",
x"00150000",
x"00140000",
x"00130000",
x"00120000",
x"001126C4",
x"0010921F",
x"000FA037",
x"000E0000",
x"000D0000",
x"000C0000",
x"000B0000",
x"000A0000",
x"00090000",
x"00080000",
x"00070000",
x"00060000",
x"00050008",
x"00040070",
x"00030000",
x"00020002",
x"00012222",
x"00003004"
)--124.8M
);
constant CDCE_I2C_Masks : CDCE_TWI_Masks_t := (
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000001000",
"0000000000000000",
"0000001000001111",
"0001000000000000",
"0000000000000011",
"0000001111111111",
"1111100000001000",
"0000000000000000",
"0011001111111011",
"1111111111111111",
"0000011000111111",
"0000100000000000",
"0000000000000000",
"0011001111111011",
"1111111111111111",
"0000000000111111",
"0110100000001000",
"0000000000000000",
"0011001111111011",
"1111111111111111",
"0000000000000000",
"1111110000111111",
"1111100000001000",
"0000000000000000",
"0101001111111011",
"1111111111111111",
"0000001111000000",
"0000000000000000",
"0000000001001000",
"0000000000000000",
"0000010001000000",
"0000011100000000",
"0000000000011111",
"0111111111111111",
"0001111111111000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"1111111111111111",
"0000000000101110",
"1000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000011111111",
"1111111111111111",
"0000000011111111",
"1111111111111111",
"0111111111111111",
"0000000000000000",
"0000000000000000",
"0000000000000011",
"0000000000000000",
"0111111011111111",
"1001111100111111",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"1111000000100000",
"1111111111111111",
"0000000000111111",
"0000000000000000",
"0000000000111111",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000111111110",
"0000000011111111",
"0010001001111000",
"0000001111111111",
"1111111111111111",
"1111010100001011"
);
-- number of commands to load in the TX command FIFO for the CommandFIFO module
constant kCmdFIFO_NoWrCmds : integer := 3;
-- command list loaded in the TX command FIFO of the CommandFIFO module
type CmdFIFO_WrCmdList_t is array (kCmdFIFO_NoWrCmds downto 0) of std_logic_vector(23 downto 0);
constant kCmdFIFO_WrList : CmdFIFO_WrCmdList_t := (x"800200", -- read chip grade
x"800100", -- read chip ID
x"00003C", -- write SPI Port Config
x"000000" -- dummy
);
-- number of commands expected to be returned and loaded in the RX command FIFO of
-- the CommandFIFO module by the AD9648_SPI_Module in the tb_TestConfigADC test bench.
-- It should be equal to the number of read commands in the kCmdFIFO_WrList.
constant kCmdFIFO_NoRdCmds : integer := 2;
-- data expected in return after sending the kCmdFIFO_WrList commands by the CommandFIFO module
type CmdFIFO_RdCmdList_t is array (kCmdFIFO_NoRdCmds-1 downto 0) of std_logic_vector(7 downto 0);
constant kCmdFIFO_Timeout : unsigned (23 downto 0) := x"000600";
type CalibCoef_t is record
LgMultCoef : std_logic_vector (17 downto 0);
LgAddCoef : std_logic_vector (17 downto 0);
HgMultCoef : std_logic_vector (17 downto 0);
HgAddCoef : std_logic_vector (17 downto 0);
end record;
type RelayConfig_t is record
CouplingConfig : std_logic;
GainConfig : std_logic;
end record;
constant kCmdWrTotal_AD9648 : integer := 19;
constant kCmdWrTotal_AD9204 : integer := 19;
constant kCmdWrTotal_AD9608 : integer := 19;
constant kCmdWrTotal_AD9231 : integer := 19;
constant kCmdWrTotal_AD9628 : integer := 19;
constant kCmdWrTotal_AD9251 : integer := 19;
constant kCmdReadID_Index : integer := 1; --Read ID command index in kADC_SPI_Cmd and kADC_SPI_Rdbck arrays
constant kCmdClkDivIndex : integer := 10; --Clock Divide command index in kADC_SPI_Cmd and kADC_SPI_Rdbck arrays
-- Constant used to measure 290ms (with a clock frequency of 100MHz) to allow the ADC's
-- transition from power down to normal operation (ConfigADC.vhd).
-- 290ms value is computed from:
-- https://www.analog.com/media/en/technical-documentation/data-sheets/ad9648.pdf page 40,
-- "The pseudo code sequence for a digital reset":
-- 2.9e6 sample clock cycles @ 10MHz minimum sampling clock frequency (for ZmodScope) = 290ms
constant kCountResetResume : unsigned := to_unsigned (28999999, 25);
-- Smaller version of the kCountResetResume, used only for simulation purposes.
-- (999 + 1) clock cycles @ 100MHz frequency means 10us.
constant kCountResetResumeSim : unsigned := to_unsigned (999, 25);
-- Constant used to measure 4ms (with a clock frequency of 100MHz) that allows to
-- determine the timing intervals for the relay drive signals (ConfigRelays.vhd)
constant kCount4ms : unsigned := to_unsigned (399999, 24);
-- Smaller version of the kCount4ms, used only for simulation purposes.
-- (399 + 1) clock cycles @ 100MHz frequency means 4us.
constant kCount4msSim : unsigned := to_unsigned (399, 24);
-- Constant used to measure 5ms with a clock frequency of 100MHz
-- Used to determine the ADC calibration timeout condition (tb_TestConfigADC.vhd and tb_TestTop.vhd)
constant kCount5ms : integer := 500000;
-- Constant used to measure 291ms (with a clock frequency of 100MHz) that determines a
-- timeout condition on the ADC's SPI interface (ConfigADC.vhd)
-- This value has to be larger than kCountResetResume, otherwise false timeouts on the ADC
-- SPI interface will occur (i.e. after an ADC soft reset is performed).
constant kCfgTimeout : unsigned := to_unsigned (29099999, 25);
type FsmStatesADC_t is (StStart, StCheckCmdCnt, StWriteSoftReset, StWaitDoneRst, StReadPortConfig,
StCheckResetDone, StReadID, StWaitDoneID, StWriteControlReg, StWaitDoneWriteReg,
StWaitDoneReadReg, StReadControlReg, StResetTimer, StWaitRecover, StInitDone, StIdle,
StError, StExtSPI_RdCmd, StExtSPI_WrCmd, StWaitDoneExtWrReg,
StWaitDoneExtRdReg, StRegExtRxData, StSetTrsfReg, StWaitDoneTrsfReg, StReadTrsfReg, StWaitDoneTrsfRegRd);
type FsmStatesRelays_t is (StStart, StConfigCouplingCh1, StConfigCouplingCh1Rst, StConfigCouplingCh2,
StConfigCouplingCh2Rst, StConfigGainCh1, StConfigGainCh1Rst, StConfigGainCh2,
StConfigGainCh2Rst, StPushInitDone, StWaitRdy, StIdle, StError, StWaitAckCouplingCh1,
StChangeCouplingCh1, StWaitAckCouplingCh2, StChangeCouplingCh2, StWaitAckGainCh1,
StChangeGainCh1, StWaitAckGainCh2, StChangeGainCh2, StRstCfgPulse);
type FsmStatesSPI_t is (StIdle, StWrite, StRead1, StRead2, StRead3, StDone, StAssertCS);
type FsmStatesI2C_t is (stIdle, stCheckCmdCnt, stCheckConfigDone, stRegAddress_H, stRegAddress_L, stRegData_H, stRegData_L,
stReadBackAddress_H, stReadBackAddress_L, stReadBackData_H, stReadBackData_L, stCheckReadBackError, stCheckReadBackDone);
constant kRangeLg : real := 26.25;
constant kRangeHg : real := 1.086;
constant kRangeIdealLg : real := 25.0;
constant kRangeIdealHg : real := 1.0;
-- Function used to determine the Chip ID based on the ZmodIC parameter
-- that identifies the Zmod.
function SelADC_ID(ZmodIC:integer)
return std_logic_vector;
-- Function used to determine the Chip grade based on the ZmodIC parameter
-- that identifies the Zmod.
function SelADC_Grade(ZmodIC:integer)
return std_logic_vector;
-- Function used to determine the Clock devide ratio field of register 0x0B
-- based on the kADC_ClkDiv generic
function DetClkDiv(ADC_ClkDiv:integer)
return std_logic_vector;
-- The initiaization command list is different depending on which Zmod is targeted.
-- The SelCmdList function is used to select the appropriate command list based on
-- the ZmodIC parameter.
function SelCmdList(ZmodIC:integer)
return ADC_SPI_Commands_t;
-- The initiaization command readback list is different depending on which Zmod is
-- targeted. The SelCmdList function is used to select the appropriate command list
-- based on the ZmodIC parameter.
function SelRdbkList(ZmodIC:integer)
return ADC_SPI_Readback_t;
-- The OverwriteClkDiv function is used to overwrite the Clock divide ratio field of commad list
-- (CmdList) sent as parameter based on ADC_ClkDiv. It is important to note that the "write
-- Clock Divide register" (address 0x0B) command shares the same position (kCmdClkDivIndex) in
-- the command list for the currently supported Zmods.
function OverwriteClkDiv(CmdList:ADC_SPI_Commands_t; ADC_ClkDiv:integer)
return ADC_SPI_Commands_t;
-- The OverWriteID_ClkDiv function is used to overwrite the ADC chip ID field of the
-- command readback list (RdbkList) based on the ZmodIC parameter.
function OverWriteID_ClkDiv(ZmodIC:integer; RdbkList:ADC_SPI_Readback_t; ADC_ClkDiv:integer)
return ADC_SPI_Readback_t;
-- The SelCmdWrListLength function is used to detrmine the command list
-- length based on the ZmodIC parameter.
function SelCmdWrListLength(ZmodIC:integer)
return integer;
-- Function used to determine the ADC resolution (kADC_Width) based on the ZmodIC parameter.
-- Used in the top level test bench.
function SelADC_Width(ZmodIC:integer)
return integer;
-- Function used to compute the IDDR sampling clock phase as a function of the sampling
-- period. This is necessary so the clock phase is always an integer multiple of
-- (45 degrees/output clock division factor) of the MMCM which generates it.
function IDDR_ClockPhase(SamplingPeriod:real)
return real;
function DCO_ClockPeriod(CDCE_FreqSel:integer)
return integer;
end PkgZmodDigitizer;
package body PkgZmodDigitizer is
function SelADC_ID(ZmodIC:integer)
return std_logic_vector is
begin
case ZmodIC is
when kZmodDigitizer1430_105 =>
return AD9648_ID;
when kZmodDigitizer1030_40 =>
return AD9204_ID;
when kZmodDigitizer1030_125 =>
return AD9608_ID;
when kZmodDigitizer1230_40 =>
return AD9231_ID;
when kZmodDigitizer1230_125 =>
return AD9628_ID;
when kZmodDigitizer1430_40 =>
return AD9251_ID;
when kZmodDigitizer1430_125 =>
return AD9648_ID;
when others =>
return x"00";
end case;
end function;
function SelADC_Grade(ZmodIC:integer)
return std_logic_vector is
begin
case ZmodIC is
when kZmodDigitizer1430_105 =>
return AD9648_Grade;
when kZmodDigitizer1030_40 =>
return AD9204_Grade;
when kZmodDigitizer1030_125 =>
return AD9608_Grade;
when kZmodDigitizer1230_40 =>
return AD9231_Grade;
when kZmodDigitizer1230_125 =>
return AD9628_Grade;
when kZmodDigitizer1430_40 =>
return AD9251_Grade;
when kZmodDigitizer1430_125 =>
return AD9648_Grade;
when others =>
return x"00";
end case;
end function;
function DetClkDiv(ADC_ClkDiv:integer)
return std_logic_vector is
begin
if (ADC_ClkDiv = 1) then
return x"00";
elsif (ADC_ClkDiv = 2) then
return x"01";
elsif (ADC_ClkDiv = 3) then
return x"02";
elsif (ADC_ClkDiv = 4) then
return x"03";
elsif (ADC_ClkDiv = 5) then
return x"04";
elsif (ADC_ClkDiv = 6) then
return x"05";
elsif (ADC_ClkDiv = 7) then
return x"06";
elsif (ADC_ClkDiv = 8) then
return x"07";
else
return x"00";
end if;
end function;
function SelCmdList(ZmodIC:integer)
return ADC_SPI_Commands_t is
variable CmdListV : ADC_SPI_Commands_t := kAD96xx_SPI_Cmd;
begin
case ZmodIC is
when kZmodDigitizer1430_105 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when kZmodDigitizer1030_40 =>
CmdListV := kAD92xx_SPI_Cmd;
return CmdListV;
when kZmodDigitizer1030_125 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when kZmodDigitizer1230_40 =>
CmdListV := kAD92xx_SPI_Cmd;
return CmdListV;
when kZmodDigitizer1230_125 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when kZmodDigitizer1430_40 =>
CmdListV := kAD92xx_SPI_Cmd;
return CmdListV;
when kZmodDigitizer1430_125 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when others =>
CmdListV := (others => (others => '0'));
return CmdListV;
end case;
end function;
function SelRdbkList(ZmodIC:integer)
return ADC_SPI_Readback_t is
variable RdbkListV : ADC_SPI_Readback_t := kAD96xx_SPI_Rdbck;
begin
case ZmodIC is
when kZmodDigitizer1430_105 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when kZmodDigitizer1030_40 =>
RdbkListV := kAD92xx_SPI_Rdbck;
return RdbkListV;
when kZmodDigitizer1030_125 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when kZmodDigitizer1230_40 =>
RdbkListV := kAD92xx_SPI_Rdbck;
return RdbkListV;
when kZmodDigitizer1230_125 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when kZmodDigitizer1430_40 =>
RdbkListV := kAD92xx_SPI_Rdbck;
return RdbkListV;
when kZmodDigitizer1430_125 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when others =>
RdbkListV := (others => (others => '0'));
return RdbkListV;
end case;
end function;
function OverwriteClkDiv(CmdList:ADC_SPI_Commands_t; ADC_ClkDiv:integer)
return ADC_SPI_Commands_t is
variable CmdListV : ADC_SPI_Commands_t := CmdList;
begin
CmdListV(kCmdClkDivIndex) := CmdList(kCmdClkDivIndex)(23 downto 8) & DetClkDiv(ADC_ClkDiv);
return CmdListV;
end function;
function OverWriteID_ClkDiv(ZmodIC:integer; RdbkList:ADC_SPI_Readback_t; ADC_ClkDiv:integer)
return ADC_SPI_Readback_t is
variable RdbkListV : ADC_SPI_Readback_t := RdbkList;
begin
RdbkListV(kCmdClkDivIndex) := DetClkDiv(ADC_ClkDiv);
case ZmodIC is
when kZmodDigitizer1430_105 =>
RdbkListV(kCmdReadID_Index) := AD9648_ID;
return RdbkListV;
when kZmodDigitizer1030_40 =>
RdbkListV(kCmdReadID_Index) := AD9204_ID;
return RdbkListV;
when kZmodDigitizer1030_125 =>
RdbkListV(kCmdReadID_Index) := AD9608_ID;
return RdbkListV;
when kZmodDigitizer1230_40 =>
RdbkListV(kCmdReadID_Index) := AD9231_ID;
return RdbkListV;
when kZmodDigitizer1230_125 =>
RdbkListV(kCmdReadID_Index) := AD9628_ID;
return RdbkListV;
when kZmodDigitizer1430_40 =>
RdbkListV(kCmdReadID_Index) := AD9251_ID;
return RdbkListV;
when kZmodDigitizer1430_125 =>
RdbkListV(kCmdReadID_Index) := AD9648_ID;
return RdbkListV;
when others =>
RdbkListV(kCmdReadID_Index) := x"00";
return RdbkListV;
end case;
end function;
function SelCmdWrListLength(ZmodIC:integer)
return integer is
begin
case ZmodIC is
when kZmodDigitizer1430_105 =>
return kCmdWrTotal_AD9648;
when kZmodDigitizer1030_40 =>
return kCmdWrTotal_AD9204;
when kZmodDigitizer1030_125 =>
return kCmdWrTotal_AD9608;
when kZmodDigitizer1230_40 =>
return kCmdWrTotal_AD9231;
when kZmodDigitizer1230_125 =>
return kCmdWrTotal_AD9628;
when kZmodDigitizer1430_40 =>
return kCmdWrTotal_AD9251;
when kZmodDigitizer1430_125 =>
return kCmdWrTotal_AD9648;
when others =>
return 0;
end case;
end function;
function SelADC_Width(ZmodIC:integer)
return integer is
begin
case ZmodIC is
when kZmodDigitizer1430_105 =>
return 14;
when kZmodDigitizer1030_40 =>
return 10;
when kZmodDigitizer1030_125 =>
return 10;
when kZmodDigitizer1230_40 =>
return 12;
when kZmodDigitizer1230_125 =>
return 12;
when kZmodDigitizer1430_40 =>
return 14;
when kZmodDigitizer1430_125 =>
return 14;
when others =>
return 14;
end case;
end function;
function IDDR_ClockPhase(SamplingPeriod:real)
return real is
begin
--400MHz to 200MHz
if ((SamplingPeriod > 2.5) and (SamplingPeriod <= 5.0)) then
return 120.0;
--200MHz to 111MHz
elsif ((SamplingPeriod > 5.0) and (SamplingPeriod <= 9.0)) then
return 127.5;
--111MHz to 100MHz
elsif ((SamplingPeriod > 9.0) and (SamplingPeriod <= 10.0)) then
return 120.0;
--100MHz to 50MHz
elsif ((SamplingPeriod > 10.0) and (SamplingPeriod <= 20.0)) then
return 123.75;
--50MHz to 25MHz
elsif ((SamplingPeriod > 20.0) and (SamplingPeriod <= 40.0)) then
return 125.625;
--25MHz to 12.5MHz
elsif ((SamplingPeriod > 40.0) and (SamplingPeriod <= 80.0)) then
return 125.625;
--12.5MHz to 10MHz
elsif (SamplingPeriod > 80.0) then
return 125.859375;
--Out of specifications;
else
return 1.0;
end if;
end function;
function DCO_ClockPeriod(CDCE_FreqSel:integer)
return integer is
begin
--122.88MHz
if (CDCE_FreqSel = 0) then
return 8138;--Clock Period in ps
--50MHz
elsif (CDCE_FreqSel = 1) then
return 20000;--Clock Period in ps
--80MHz
elsif (CDCE_FreqSel = 2) then
return 12500;--Clock Period in ps
--100MHz
elsif (CDCE_FreqSel = 3) then
return 10000;--Clock Period in ps
--110MHz
elsif (CDCE_FreqSel = 4) then
return 9090;--Clock Period in ps
--120MHz
elsif (CDCE_FreqSel = 5) then
return 8333;--Clock Period in ps
--125MHz
elsif (CDCE_FreqSel = 6) then
return 8000;--Clock Period in ps
--Out of specifications;
else
return 8138;--Clock Period in ps
end if;
end function;
end PkgZmodDigitizer;
|
mit
|
8fd3aa469bd6bb81ed7ae5d18f6ab1c4
| 0.329507 | 6.817507 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/tb_TestSPI.vhd
| 1 | 6,086 |
-------------------------------------------------------------------------------
--
-- File: tb_TestSPI.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to illustrate the ADI_SPI module behavior.
-- A register read and a register write operations are performed. Multiple
-- back to back register read and write operation behavior are tested as part
-- of the tests carried out in the tb_TestConfigADC test bench.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodADC.all;
entity tb_TestSPI is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0
);
end tb_TestSPI;
architecture Behavioral of tb_TestSPI is
signal sRst_n : std_logic := '0';
signal sSPI_Clk, sSDIO : std_logic := 'X';
signal sCS : std_logic := '1';
signal sRdData : std_logic_vector(7 downto 0);
signal sWrData : std_logic_vector(7 downto 0) := (others => 'X');
signal sAddr : std_logic_vector(12 downto 0) := (others => 'X');
signal sWidth : std_logic_vector(1 downto 0) := (others => 'X');
signal sRdWr : std_logic;
signal sAPStart : std_logic;
signal sDone : std_logic;
signal sBusy : std_logic;
constant kSysClkPeriod : time := 10ns; -- System Clock Period
signal SysClk100 : std_logic := '1';
begin
ADI_SPI_inst: entity work.ADI_SPI
Port Map(
--
SysClk100 => SysClk100,
asRst_n => sRst_n,
sSPI_Clk => sSPI_Clk,
sSDIO => sSDIO,
sCS => sCS,
sApStart => sApStart,
sRdData => sRdData,
sWrData => sWrData,
sAddr => sAddr,
sWidth => sWidth,
sRdWr => sRdWr,
sDone => sDone,
sBusy => sBusy
);
AD96xx_92xx_inst: entity work.AD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => sRst_n,
InsertError => '0',
sSPI_Clk => sSPI_Clk,
sSDIO => sSDIO,
sCS => sCS
);
Clock: process
begin
for i in 0 to 1000 loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
Main: process
begin
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
sRst_n <= '0';
sWrData <= x"00";
sAddr <= "0000000000000";
sWidth <= "00";
sRdWr <= '0';
sApStart <= '0';
wait for 10 * kSysClkPeriod;
-- Perform a register write operation.
-- Signals are assigned at test bench level on the falling edge of SysClk100
wait until falling_edge(SysClk100);
sRst_n <= '1';
sWrData <= x"AA";
sAddr <= "0000000001011";
sWidth <= "00";
-- Trigger register write operation.
sApStart <= '1';
-- Wait until SPI transaction is completed.
wait until sDone = '1';
wait until falling_edge(SysClk100);
sApStart <= '0';
-- Wait until ADI_SPI module returns to idle state.
wait until sBusy = '0';
wait for 10*kSysClkPeriod;
-- Perform a register read operation.
wait until falling_edge(SysClk100);
sWrData <= x"AA";
sAddr <= "0000000000001";
sWidth <= "00";
sRdWr <= '1';
-- Trigger register read operation.
sApStart <= '1';
-- Wait until SPI transaction is completed.
wait until sDone = '1';
wait until falling_edge(SysClk100);
sApStart <= '0';
-- Wait until ADI_SPI module returns to idle state.
wait until sBusy = '0';
wait;
end process;
end Behavioral;
|
mit
|
878f8eac081f423fd0f082d048effe42
| 0.622576 | 4.304102 | false | true | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/axi_master.vhd
| 2 | 36,155 |
-------------------------------------------------------------------------------
--
-- File: top.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements an AXI Lite master. It is responsible for passing
-- commands/reading status information to/from the DMA controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_master is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- The master will start generating data from the C_M_START_DATA_VALUE value
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
-- The master requires a target slave base address.
-- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := "0000000000";
-- Width of M_AXI address bus.
-- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
C_M_AXI_ADDR_WIDTH : integer := 10;
-- Width of M_AXI data bus.
-- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
C_M_AXI_DATA_WIDTH : integer := 32;
-- Transaction number is the number of write
-- and read transactions the master will perform as a part of this example memory test.
C_M_TRANSACTIONS_NUM : integer := 4
);
port (
-- Users to add ports here
M_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
M_AXI_ARESETN : in std_logic;
-- AXI clock signal
-- s_axi_clk = m_axi_clk--M_AXI_ACLK : out std_logic;
-- AXI active low reset signal
--M_AXI_ARESETN : in std_logic;
-- Master Interface Write Address Channel ports. Write address (issued by master)
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type.
-- This signal indicates the privilege and security level of the transaction,
-- and whether the transaction is a data access or an instruction access.
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
-- Write address valid.
-- This signal indicates that the master signaling valid write address and control information.
M_AXI_AWVALID : out std_logic;
-- Write address ready.
-- This signal indicates that the slave is ready to accept an address and associated control signals.
M_AXI_AWREADY : in std_logic;
-- Master Interface Write Data Channel ports. Write data (issued by master)
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes.
-- This signal indicates which byte lanes hold valid data.
-- There is one write strobe bit for each eight bits of the write data bus.
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
-- Write valid. This signal indicates that valid write data and strobes are available.
M_AXI_WVALID : out std_logic;
-- Write ready. This signal indicates that the slave can accept the write data.
M_AXI_WREADY : in std_logic;
-- Master Interface Write Response Channel ports.
-- This signal indicates the status of the write transaction.
M_AXI_BRESP : in std_logic_vector(1 downto 0);
-- Write response valid.
-- This signal indicates that the channel is signaling a valid write response
M_AXI_BVALID : in std_logic;
-- Response ready. This signal indicates that the master can accept a write response.
M_AXI_BREADY : out std_logic;
-- Master Interface Read Address Channel ports. Read address (issued by master)
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type.
-- This signal indicates the privilege and security level of the transaction,
-- and whether the transaction is a data access or an instruction access.
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
-- Read address valid.
-- This signal indicates that the channel is signaling valid read address and control information.
M_AXI_ARVALID : out std_logic;
-- Read address ready.
-- This signal indicates that the slave is ready to accept an address and associated control signals.
M_AXI_ARREADY : in std_logic;
-- Master Interface Read Data Channel ports. Read data (issued by slave)
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the read transfer.
M_AXI_RRESP : in std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is signaling the required read data.
M_AXI_RVALID : in std_logic;
-- Read ready. This signal indicates that the master can accept the read data and response information.
M_AXI_RREADY : out std_logic;
INIT_WRITE : in std_logic;
INIT_READ : in std_logic;
WRITE_COMPLETE : out std_logic;
READ_COMPLETE : out std_logic;
WRITE_DATA : in std_logic_vector(31 downto 0);
WRITE_ADDRESS : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
READ_DATA : out std_logic_vector(31 downto 0);
READ_ADDRESS : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)
);
end axi_master;
architecture implementation of axi_master is
-- function called clogb2 that returns an integer which has the
-- value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
-- Example user application signals
-- TRANS_NUM_BITS is the width of the index counter for
-- number of write or read transaction..
constant TRANS_NUM_BITS : integer := clogb2(C_M_TRANSACTIONS_NUM-1);
-- Example State machine to initialize counter, initialize write transactions,
-- initialize read transactions and comparison of read data with the
-- written data words.
type state is ( FSM_IDLE, -- This state initiates AXI4Lite transaction
-- after the state machine changes state to INIT_WRITE
-- when there is 0 to 1 transition on INIT_AXI_TXN
FSM_INIT_WRITE, -- This state initializes write transaction,
-- once writes are done, the state machine
-- changes state to INIT_READ
FSM_INIT_READ -- This state initializes read transaction
-- once reads are done, the state machine
-- changes state to INIT_COMPARE
);-- This state issues the status of comparison
-- of the written data with the read data
signal mst_exec_state : state ;
-- AXI4LITE signals
--write address valid
signal axi_awvalid : std_logic;
--write data valid
signal axi_wvalid : std_logic;
--read address valid
signal axi_arvalid : std_logic;
--read data acceptance
signal axi_rready : std_logic;
--write response acceptance
signal axi_bready : std_logic;
--write address
signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
--write data
signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--read addresss
signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_rdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--Asserts when there is a write response error
signal write_resp_error : std_logic;
--Asserts when there is a read response error
signal read_resp_error : std_logic;
--A pulse to initiate a write transaction
signal start_single_write : std_logic;
--A pulse to initiate a read transaction
signal start_single_read : std_logic;
--Asserts when a single beat write transaction is issued and remains asserted till the completion of write trasaction.
signal write_issued : std_logic;
--Asserts when a single beat read transaction is issued and remains asserted till the completion of read trasaction.
signal read_issued : std_logic;
--flag that marks the completion of write trasactions. The number of write transaction is user selected by the parameter C_M_TRANSACTIONS_NUM.
signal writes_done : std_logic;
--flag that marks the completion of read trasactions. The number of read transaction is user selected by the parameter C_M_TRANSACTIONS_NUM
signal reads_done : std_logic;
begin
-- I/O Connections assignments
WRITE_COMPLETE <= writes_done;
READ_COMPLETE <= reads_done;
--Adding the offset address to the base addr of the slave
M_AXI_AWADDR <= std_logic_vector (unsigned(C_M_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_awaddr));
--AXI 4 write data
M_AXI_WDATA <= axi_wdata;
M_AXI_AWPROT <= "000";
M_AXI_AWVALID <= axi_awvalid;
--Write Data(W)
M_AXI_WVALID <= axi_wvalid;
--Set all byte strobes in this example
M_AXI_WSTRB <= "1111";
--Write Response (B)
M_AXI_BREADY <= axi_bready;
--Read Address (AR)
M_AXI_ARADDR <= std_logic_vector(unsigned(C_M_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_araddr));
M_AXI_ARVALID <= axi_arvalid;
M_AXI_ARPROT <= "001";
--Read and Read Response (R)
M_AXI_RREADY <= axi_rready;
----------------------
--Write Address Channel
----------------------
process( M_AXI_ACLK)
begin
if (rising_edge ( M_AXI_ACLK)) then
--Only VALID signals must be deasserted during reset per AXI spec
--Consider inverting then registering active-low reset for higher fmax
if (M_AXI_ARESETN = '0') then
axi_awvalid <= '0';
else
--Signal a new address/data command is available by user logic
if (start_single_write = '1') then
axi_awaddr <= WRITE_ADDRESS;
axi_awvalid <= '1';
elsif (M_AXI_AWREADY = '1' and axi_awvalid = '1') then
--Address accepted by interconnect/slave (issue of M_AXI_AWREADY by slave)
axi_awvalid <= '0';
end if;
end if;
end if;
end process;
----------------------
--Write Data Channel
----------------------
--The write data channel is for transfering the actual data.
--The data generation is speific to the example design, and
--so only the WVALID/WREADY handshake is shown here
process( M_AXI_ACLK)
begin
if (rising_edge ( M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' ) then
axi_wvalid <= '0';
else
if (start_single_write = '1') then
--Signal a new address/data command is available by user logic
axi_wdata <= WRITE_DATA;
axi_wvalid <= '1';
elsif (M_AXI_WREADY = '1' and axi_wvalid = '1') then
--Data accepted by interconnect/slave (issue of M_AXI_WREADY by slave)
axi_wvalid <= '0';
end if;
end if;
end if;
end process;
------------------------------
--Write Response (B) Channel
------------------------------
--The write response channel provides feedback that the write has committed
--to memory. BREADY will occur after both the data and the write address
--has arrived and been accepted by the slave, and can guarantee that no
--other accesses launched afterwards will be able to be reordered before it.
--The BRESP bit [1] is used indicate any errors from the interconnect or
--slave for the entire write burst. This example will capture the error.
--While not necessary per spec, it is advisable to reset READY signals in
--case of differing reset latencies between master/slave.
process( M_AXI_ACLK)
begin
if (rising_edge ( M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0') then
axi_bready <= '0';
else
if (M_AXI_BVALID = '1' and axi_bready = '0') then
-- accept/acknowledge bresp with axi_bready by the master
-- when M_AXI_BVALID is asserted by slave
axi_bready <= '1';
elsif (axi_bready = '1') then
-- deassert after one clock cycle
axi_bready <= '0';
end if;
end if;
end if;
end process;
--Flag write errors
write_resp_error <= (axi_bready and M_AXI_BVALID and M_AXI_BRESP(1));
------------------------------
--Read Address Channel
------------------------------
-- A new axi_arvalid is asserted when there is a valid read address
-- available by the master. start_single_read triggers a new read
-- transaction
process( M_AXI_ACLK)
begin
if (rising_edge ( M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0') then
axi_arvalid <= '0';
else
axi_araddr <= READ_ADDRESS;
if (start_single_read = '1') then
--Signal a new read address command is available by user logic
axi_arvalid <= '1';
elsif (M_AXI_ARREADY = '1' and axi_arvalid = '1') then
--RAddress accepted by interconnect/slave (issue of M_AXI_ARREADY by slave)
axi_arvalid <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--Read Data (and Response) Channel
----------------------------------
--The Read Data channel returns the results of the read request
--The master will accept the read data by asserting axi_rready
--when there is a valid read data available.
--While not necessary per spec, it is advisable to reset READY signals in
--case of differing reset latencies between master/slave.
process( M_AXI_ACLK)
begin
if (rising_edge ( M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0') then
axi_rready <= '1';
else
if (M_AXI_RVALID = '1' and axi_rready = '0') then
-- accept/acknowledge rdata/rresp with axi_rready by the master
-- when M_AXI_RVALID is asserted by slave
axi_rready <= '1';
elsif (axi_rready = '1') then
-- deassert after one clock cycle
axi_rready <= '0';
end if;
end if;
end if;
end process;
--Flag write errors
read_resp_error <= (axi_rready and M_AXI_RVALID and M_AXI_RRESP(1));
----------------------------------
--User Logic
----------------------------------
--Address/Data Stimulus
--Address/data pairs for this example. The read and write values should
--match.
--Modify these as desired for different address patterns.
-- Expected read data
process( M_AXI_ACLK)
begin
if (rising_edge ( M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' ) then
READ_DATA <= (others=>'0');
elsif (M_AXI_RVALID = '1' and axi_rready = '1') then
-- Signals a new write address/ write data is
-- available by user logic
READ_DATA <= M_AXI_RDATA;
end if;
end if;
end process;
--implement master command interface state machine
MASTER_EXECUTION_PROC:process( M_AXI_ACLK)
begin
if (rising_edge ( M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' ) then
-- reset condition
-- All the signals are ed default values under reset condition
mst_exec_state <= FSM_IDLE;
start_single_write <= '0';
write_issued <= '0';
start_single_read <= '0';
read_issued <= '0';
--ERROR <= '0';
else
-- state transition
case (mst_exec_state) is
when FSM_IDLE =>
-- This state is responsible to initiate
-- AXI transaction when init_txn_pulse is asserted
if( init_write = '1') then --( init_txn_pulse = '1') then
mst_exec_state <= FSM_INIT_WRITE;
--ERROR <= '0';
elsif( init_read = '1') then
mst_exec_state <= FSM_INIT_READ;
--ERROR <= '0';
else
mst_exec_state <= FSM_IDLE;
end if;
when FSM_INIT_WRITE =>
-- This state is responsible to issue start_single_write pulse to
-- initiate a write transaction. Write transactions will be
-- issued until last_write signal is asserted.
-- write controller
if (writes_done = '1') then
mst_exec_state <= FSM_IDLE;
else
mst_exec_state <= FSM_INIT_WRITE;
if (axi_awvalid = '0' and axi_wvalid = '0' and M_AXI_BVALID = '0'
and start_single_write = '0' and write_issued = '0') then
start_single_write <= '1';
write_issued <= '1';
elsif (axi_bready = '1') then
write_issued <= '0';
else
start_single_write <= '0'; --Negate to generate a pulse
end if;
end if;
when FSM_INIT_READ =>
if (reads_done = '1') then
mst_exec_state <= FSM_IDLE;
else
mst_exec_state <= FSM_INIT_READ;
if (axi_arvalid = '0' and M_AXI_RVALID = '0' and
start_single_read = '0' and read_issued = '0') then
start_single_read <= '1';
read_issued <= '1';
elsif (axi_rready = '1') then
read_issued <= '0';
else
start_single_read <= '0'; --Negate to generate a pulse
end if;
end if;
when others =>
mst_exec_state <= FSM_IDLE;
end case ;
end if;
end if;
end process;
--/*
-- Check for last write completion.
--
-- This logic is to qualify the last write count with the final write
-- response. This demonstrates how to confirm that a write has been
-- committed.
-- */
process( M_AXI_ACLK)
begin
if (rising_edge ( M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0') then
-- reset condition
writes_done <= '0';
elsif (writes_done = '1') then
writes_done <= '0';
elsif (M_AXI_BVALID = '1' and axi_bready = '1') then--if (last_write = '1' and M_AXI_BVALID = '1' and axi_bready = '1') then
--The writes_done should be associated with a bready response
writes_done <= '1';
end if;
end if;
end process;
--------------
--Read example
--------------
-- Check for last read completion.
--
-- This logic is to qualify the last read count with the final read
-- response/data.
-- */
process( M_AXI_ACLK)
begin
if (rising_edge ( M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0') then
-- reset condition
axi_rdata <= (others => '0');
reads_done <= '0';
elsif (reads_done = '1') then
reads_done <= '0';
elsif ( M_AXI_RVALID = '1' and axi_rready = '1') then
--The writes_done should be associated with a bready response
axi_rdata <= M_AXI_RDATA;
reads_done <= '1';
end if;
end if;
end process;
------------------------------/
--Example design error register
------------------------------/
end implementation;
|
mit
|
e8f9b49dd30c3d2c822108f36b3b5603
| 0.360559 | 6.349666 | false | false | false | false |
igormacedo/vhdlstudy
|
counter.vhdl
| 1 | 608 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
clk, rst : in std_logic;
q : out std_logic_vector(15 downto 0)
);
end entity;
architecture behavior of counter is
--signal tmp_q : std_logic_vector(15 downto 0);
begin
process(clk, rst)
variable tmp_q : std_logic_vector(15 downto 0);
begin
if rst = '0' then
tmp_q := (others => '0');
-- tmp_q <= (others => '0');
elsif rising_edge(clk) then
tmp_q := tmp_q + 1;
-- tmp_q <= tmp_q + 1;
end if;
q <= tmp_q;
end process;
-- q <= tmp_q;
end architecture;
|
mit
|
4ae82336b313485a1c7617aaba6ff69c
| 0.598684 | 2.881517 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/FtoI2.vhd
| 1 | 2,829 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FtoI2 is
port (
clk : in std_logic;
f : in std_logic_vector(31 downto 0);
i : out std_logic_vector(31 downto 0));
end FtoI2;
architecture dataflow_pipeline of FtoI2 is
signal x_len_pre : std_logic_vector(8 downto 0);
signal u_frc_4_pre : unsigned(31 downto 0);
signal sgn_p : std_logic := '0';
signal x_len : std_logic_vector(8 downto 0) := (others => '0');
signal u_frc_4 : unsigned(31 downto 0) := (others => '0');
signal u_frc_3, u_frc_2, u_frc_1, u_frc_0, u_frc_o, u_frc_v2 : unsigned(31 downto 0);
signal any_3, any_2, any_1, any_0, any_o : std_logic;
signal round : std_logic;
signal i_err : std_logic_vector(31 downto 0);
signal err : boolean;
signal sgn_pp : std_logic := '0';
signal round_suf : std_logic := '0';
signal u_frc_v : unsigned(31 downto 0) := (others => '0');
signal i_err_suf : std_logic_vector(31 downto 0) := (others => '0');
signal err_suf : boolean := false;
begin
x_len_pre <= std_logic_vector(unsigned('0' & f(30 downto 23)) - "001111110");
u_frc_4_pre <= unsigned('1' & f(22 downto 0) & "00000000");
pipe2 : process(clk)
begin
if rising_edge(clk) then
sgn_p <= f(31);
x_len <= x_len_pre;
u_frc_4 <= u_frc_4_pre;
end if;
end process;
any_3 <= '1' when x_len(4) = '0' and u_frc_4(15 downto 0) /= 0 else '0';
u_frc_3 <= u_frc_4 srl 16 when x_len(4) = '0' else u_frc_4;
any_2 <= '1' when x_len(3) = '0' and u_frc_3( 7 downto 0) /= 0 else any_3;
u_frc_2 <= u_frc_3 srl 8 when x_len(3) = '0' else u_frc_3;
any_1 <= '1' when x_len(2) = '0' and u_frc_2( 3 downto 0) /= 0 else any_2;
u_frc_1 <= u_frc_2 srl 4 when x_len(2) = '0' else u_frc_2;
any_0 <= '1' when x_len(1) = '0' and u_frc_1( 1 downto 0) /= 0 else any_1;
u_frc_0 <= u_frc_1 srl 2 when x_len(1) = '0' else u_frc_1;
any_o <= '1' when x_len(0) = '0' and u_frc_0( 0 downto 0) /= 0 else any_0;
u_frc_o <= u_frc_0 srl 1 when x_len(0) = '0' else u_frc_0;
round <= (u_frc_o(0) and any_o) or (u_frc_o(1) and u_frc_o(0));
i_err <= x"00000000" when x_len(8) = '1' else
x"7FFFFFFF" when sgn_p = '0' else
x"80000000";
err <= x_len(8) = '1' or x_len(7 downto 5) /= "000";
pipe3 : process(clk)
begin
if rising_edge(clk) then
sgn_pp <= sgn_p;
round_suf <= round;
u_frc_v <= u_frc_o srl 1;
i_err_suf <= i_err;
err_suf <= err;
end if;
end process;
u_frc_v2 <= u_frc_v when sgn_pp = '0' else not u_frc_v;
i <= i_err_suf when err_suf else
std_logic_vector(u_frc_v2 + unsigned'(0 => sgn_pp xor round_suf));
end dataflow_pipeline;
|
bsd-2-clause
|
be4bf8946a240229d450341f40a1df46
| 0.54012 | 2.619444 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_my_part/CalculateG.vhd
| 1 | 1,521 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity CalculateG is
generic
(
width : integer := 8
);
port
(
-- Difference0 : in std_logic_vector( width + 3 downto 0 );
-- Difference01 : in std_logic_vector( width + 3 downto 0 );
Difference0 : in std_logic_vector( width downto 0 );
Difference01 : in std_logic_vector( width downto 0 );
IHorizontal : in std_logic_vector( width downto 0 );
IVertical : in std_logic_vector( width downto 0 );
Difference7 : in std_logic_vector( width downto 0 );
DifferenceDver : in std_logic_vector( width + 2 downto 0 );
DifferenceDhor : in std_logic_vector( width + 2 downto 0 );
ElementG : out std_logic_vector( width downto 0 )
);
end CalculateG;
architecture Behavioral of CalculateG is
signal PosThreshold : std_logic_vector( 10 downto 0 ) := "01111111111"; -- 1023
begin
process( Difference0, Difference01, IHorizontal, IVertical, Difference7, DifferenceDver, DifferenceDhor )
begin
if( Difference0( width ) /= '1' ) and ( Difference0>= PosThreshold ) then
ElementG <= IHorizontal;
elsif( Difference01( width ) /= '1' ) and ( Difference01 >= PosThreshold ) then
ElementG <= IVertical;
elsif DifferenceDhor < DifferenceDver then
ElementG <= IHorizontal;
elsif DifferenceDhor > DifferenceDver then
ElementG <= IVertical;
else
ElementG <= Difference7;
end if;
end process;
end Behavioral;
|
mit
|
87a0d3497bdaa2ac5e2e84c8ea81d2ec
| 0.673241 | 3.66506 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/Mat2AXIvideo.vhd
| 1 | 66,846 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Mat2AXIvideo is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC;
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of Mat2AXIvideo is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv3_7 : STD_LOGIC_VECTOR (2 downto 0) := "111";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv33_1FFFFFFFF : STD_LOGIC_VECTOR (32 downto 0) := "111111111111111111111111111111111";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal AXI_video_strm_V_data_V_1_data_out : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_payload_A : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_1_payload_B : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_1_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_load_A : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_load_B : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_data_V_1_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_data_out : STD_LOGIC_VECTOR (2 downto 0);
signal AXI_video_strm_V_keep_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_keep_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_strb_V_1_data_out : STD_LOGIC_VECTOR (2 downto 0);
signal AXI_video_strm_V_strb_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_strb_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_user_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_1_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_1_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_load_A : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_load_B : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_user_V_1_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_1_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_1_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_load_A : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_load_B : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_last_V_1_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_id_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_id_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_dest_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_dest_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_dest_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal img_rows_V_blk_n : STD_LOGIC;
signal img_cols_V_blk_n : STD_LOGIC;
signal img_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal exitcond_i_reg_326 : STD_LOGIC_VECTOR (0 downto 0);
signal img_data_stream_1_V_blk_n : STD_LOGIC;
signal img_data_stream_2_V_blk_n : STD_LOGIC;
signal stream_out_TDATA_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal exitcond_i_reg_326_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
signal t_V_1_reg_218 : STD_LOGIC_VECTOR (31 downto 0);
signal rows_V_reg_302 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_state1 : BOOLEAN;
signal cols_V_reg_307 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_fu_233_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal r_V_reg_312 : STD_LOGIC_VECTOR (32 downto 0);
signal exitcond3_i_fu_244_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_block_state2 : BOOLEAN;
signal i_V_fu_249_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_V_reg_321 : STD_LOGIC_VECTOR (31 downto 0);
signal exitcond_i_fu_255_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state4_io : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state5_io : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal j_V_fu_260_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal axi_last_V_fu_270_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_reg_335 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_data_V_fu_279_p4 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal t_V_reg_207 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal tmp_user_V_fu_144 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal lhs_V_cast_i_fu_229_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_cast_i_fu_266_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
begin
AXI_video_strm_V_data_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_out))) then
AXI_video_strm_V_data_V_1_sel_rd <= not(AXI_video_strm_V_data_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in))) then
AXI_video_strm_V_data_V_1_sel_wr <= not(AXI_video_strm_V_data_V_1_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out)))) then
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in)))) then
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_data_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in)))) then
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_dest_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_dest_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_out))) then
AXI_video_strm_V_dest_V_1_sel_rd <= not(AXI_video_strm_V_dest_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_dest_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out)))) then
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_in)))) then
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_in)))) then
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_id_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_id_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_out))) then
AXI_video_strm_V_id_V_1_sel_rd <= not(AXI_video_strm_V_id_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_id_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out)))) then
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_in)))) then
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_id_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_in)))) then
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_keep_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_keep_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_out))) then
AXI_video_strm_V_keep_V_1_sel_rd <= not(AXI_video_strm_V_keep_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_keep_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out)))) then
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_in)))) then
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_keep_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_in)))) then
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_out))) then
AXI_video_strm_V_last_V_1_sel_rd <= not(AXI_video_strm_V_last_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in))) then
AXI_video_strm_V_last_V_1_sel_wr <= not(AXI_video_strm_V_last_V_1_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out)))) then
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in)))) then
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in)))) then
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_strb_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_strb_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_out))) then
AXI_video_strm_V_strb_V_1_sel_rd <= not(AXI_video_strm_V_strb_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_strb_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out)))) then
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_in)))) then
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_strb_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_in)))) then
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_out))) then
AXI_video_strm_V_user_V_1_sel_rd <= not(AXI_video_strm_V_user_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in))) then
AXI_video_strm_V_user_V_1_sel_wr <= not(AXI_video_strm_V_user_V_1_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out)))) then
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in)))) then
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in)))) then
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond3_i_fu_244_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond3_i_fu_244_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond3_i_fu_244_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
t_V_1_reg_218_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_255_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
t_V_1_reg_218 <= j_V_fu_260_p2;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond3_i_fu_244_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
t_V_1_reg_218 <= ap_const_lv32_0;
end if;
end if;
end process;
t_V_reg_207_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
t_V_reg_207 <= i_V_reg_321;
elsif ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
t_V_reg_207 <= ap_const_lv32_0;
end if;
end if;
end process;
tmp_user_V_fu_144_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
tmp_user_V_fu_144 <= ap_const_lv1_0;
elsif ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_user_V_fu_144 <= ap_const_lv1_1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_load_A)) then
AXI_video_strm_V_data_V_1_payload_A <= tmp_data_V_fu_279_p4;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_load_B)) then
AXI_video_strm_V_data_V_1_payload_B <= tmp_data_V_fu_279_p4;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_load_A)) then
AXI_video_strm_V_last_V_1_payload_A <= axi_last_V_reg_335;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_load_B)) then
AXI_video_strm_V_last_V_1_payload_B <= axi_last_V_reg_335;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_load_A)) then
AXI_video_strm_V_user_V_1_payload_A <= tmp_user_V_fu_144;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_load_B)) then
AXI_video_strm_V_user_V_1_payload_B <= tmp_user_V_fu_144;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_255_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
axi_last_V_reg_335 <= axi_last_V_fu_270_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
cols_V_reg_307 <= img_cols_V_dout;
r_V_reg_312 <= r_V_fu_233_p2;
rows_V_reg_302 <= img_rows_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
exitcond_i_reg_326 <= exitcond_i_fu_255_p2;
exitcond_i_reg_326_pp0_iter1_reg <= exitcond_i_reg_326;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
i_V_reg_321 <= i_V_fu_249_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, exitcond3_i_fu_244_p2, ap_CS_fsm_state2, exitcond_i_fu_255_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond3_i_fu_244_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state1;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond3_i_fu_244_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((exitcond_i_fu_255_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((exitcond_i_fu_255_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
AXI_video_strm_V_data_V_1_ack_in <= AXI_video_strm_V_data_V_1_state(1);
AXI_video_strm_V_data_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_data_V_1_data_out_assign_proc : process(AXI_video_strm_V_data_V_1_payload_A, AXI_video_strm_V_data_V_1_payload_B, AXI_video_strm_V_data_V_1_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_sel)) then
AXI_video_strm_V_data_V_1_data_out <= AXI_video_strm_V_data_V_1_payload_B;
else
AXI_video_strm_V_data_V_1_data_out <= AXI_video_strm_V_data_V_1_payload_A;
end if;
end process;
AXI_video_strm_V_data_V_1_load_A <= (not(AXI_video_strm_V_data_V_1_sel_wr) and AXI_video_strm_V_data_V_1_state_cmp_full);
AXI_video_strm_V_data_V_1_load_B <= (AXI_video_strm_V_data_V_1_state_cmp_full and AXI_video_strm_V_data_V_1_sel_wr);
AXI_video_strm_V_data_V_1_sel <= AXI_video_strm_V_data_V_1_sel_rd;
AXI_video_strm_V_data_V_1_state_cmp_full <= '0' when (AXI_video_strm_V_data_V_1_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_data_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_data_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_data_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_data_V_1_vld_out <= AXI_video_strm_V_data_V_1_state(0);
AXI_video_strm_V_dest_V_1_ack_in <= AXI_video_strm_V_dest_V_1_state(1);
AXI_video_strm_V_dest_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_dest_V_1_data_out <= ap_const_lv1_0;
AXI_video_strm_V_dest_V_1_sel <= AXI_video_strm_V_dest_V_1_sel_rd;
AXI_video_strm_V_dest_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_dest_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_dest_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_dest_V_1_vld_out <= AXI_video_strm_V_dest_V_1_state(0);
AXI_video_strm_V_id_V_1_ack_in <= AXI_video_strm_V_id_V_1_state(1);
AXI_video_strm_V_id_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_id_V_1_data_out <= ap_const_lv1_0;
AXI_video_strm_V_id_V_1_sel <= AXI_video_strm_V_id_V_1_sel_rd;
AXI_video_strm_V_id_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_id_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_id_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_id_V_1_vld_out <= AXI_video_strm_V_id_V_1_state(0);
AXI_video_strm_V_keep_V_1_ack_in <= AXI_video_strm_V_keep_V_1_state(1);
AXI_video_strm_V_keep_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_keep_V_1_data_out <= ap_const_lv3_7;
AXI_video_strm_V_keep_V_1_sel <= AXI_video_strm_V_keep_V_1_sel_rd;
AXI_video_strm_V_keep_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_keep_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_keep_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_keep_V_1_vld_out <= AXI_video_strm_V_keep_V_1_state(0);
AXI_video_strm_V_last_V_1_ack_in <= AXI_video_strm_V_last_V_1_state(1);
AXI_video_strm_V_last_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_last_V_1_data_out_assign_proc : process(AXI_video_strm_V_last_V_1_payload_A, AXI_video_strm_V_last_V_1_payload_B, AXI_video_strm_V_last_V_1_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_sel)) then
AXI_video_strm_V_last_V_1_data_out <= AXI_video_strm_V_last_V_1_payload_B;
else
AXI_video_strm_V_last_V_1_data_out <= AXI_video_strm_V_last_V_1_payload_A;
end if;
end process;
AXI_video_strm_V_last_V_1_load_A <= (not(AXI_video_strm_V_last_V_1_sel_wr) and AXI_video_strm_V_last_V_1_state_cmp_full);
AXI_video_strm_V_last_V_1_load_B <= (AXI_video_strm_V_last_V_1_state_cmp_full and AXI_video_strm_V_last_V_1_sel_wr);
AXI_video_strm_V_last_V_1_sel <= AXI_video_strm_V_last_V_1_sel_rd;
AXI_video_strm_V_last_V_1_state_cmp_full <= '0' when (AXI_video_strm_V_last_V_1_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_last_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_last_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_last_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_last_V_1_vld_out <= AXI_video_strm_V_last_V_1_state(0);
AXI_video_strm_V_strb_V_1_ack_in <= AXI_video_strm_V_strb_V_1_state(1);
AXI_video_strm_V_strb_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_strb_V_1_data_out <= ap_const_lv3_0;
AXI_video_strm_V_strb_V_1_sel <= AXI_video_strm_V_strb_V_1_sel_rd;
AXI_video_strm_V_strb_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_strb_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_strb_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_strb_V_1_vld_out <= AXI_video_strm_V_strb_V_1_state(0);
AXI_video_strm_V_user_V_1_ack_in <= AXI_video_strm_V_user_V_1_state(1);
AXI_video_strm_V_user_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_user_V_1_data_out_assign_proc : process(AXI_video_strm_V_user_V_1_payload_A, AXI_video_strm_V_user_V_1_payload_B, AXI_video_strm_V_user_V_1_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_sel)) then
AXI_video_strm_V_user_V_1_data_out <= AXI_video_strm_V_user_V_1_payload_B;
else
AXI_video_strm_V_user_V_1_data_out <= AXI_video_strm_V_user_V_1_payload_A;
end if;
end process;
AXI_video_strm_V_user_V_1_load_A <= (not(AXI_video_strm_V_user_V_1_sel_wr) and AXI_video_strm_V_user_V_1_state_cmp_full);
AXI_video_strm_V_user_V_1_load_B <= (AXI_video_strm_V_user_V_1_state_cmp_full and AXI_video_strm_V_user_V_1_sel_wr);
AXI_video_strm_V_user_V_1_sel <= AXI_video_strm_V_user_V_1_sel_rd;
AXI_video_strm_V_user_V_1_state_cmp_full <= '0' when (AXI_video_strm_V_user_V_1_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_user_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_user_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_user_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_user_V_1_vld_out <= AXI_video_strm_V_user_V_1_state(0);
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state6 <= ap_CS_fsm(3);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter1, exitcond_i_reg_326)
begin
ap_block_pp0_stage0_01001 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_0_V_empty_n = ap_const_logic_0))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_enable_reg_pp0_iter2, ap_block_state4_io, ap_block_state5_io)
begin
ap_block_pp0_stage0_11001 <= (((ap_const_boolean_1 = ap_block_state5_io) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and ((ap_const_boolean_1 = ap_block_state4_io) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_enable_reg_pp0_iter2, ap_block_state4_io, ap_block_state5_io)
begin
ap_block_pp0_stage0_subdone <= (((ap_const_boolean_1 = ap_block_state5_io) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and ((ap_const_boolean_1 = ap_block_state4_io) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, img_rows_V_empty_n, img_cols_V_empty_n)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state2_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in)
begin
ap_block_state2 <= ((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_io_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, exitcond_i_reg_326)
begin
ap_block_state4_io <= ((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in));
end process;
ap_block_state4_pp0_stage0_iter1_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, exitcond_i_reg_326)
begin
ap_block_state4_pp0_stage0_iter1 <= (((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (img_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_block_state5_io_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, exitcond_i_reg_326_pp0_iter1_reg)
begin
ap_block_state5_io <= ((exitcond_i_reg_326_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in));
end process;
ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_i_fu_255_p2)
begin
if ((exitcond_i_fu_255_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in, exitcond3_i_fu_244_p2, ap_CS_fsm_state2)
begin
if ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond3_i_fu_244_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter0)
begin
if (((ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in, exitcond3_i_fu_244_p2, ap_CS_fsm_state2)
begin
if ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond3_i_fu_244_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
axi_last_V_fu_270_p2 <= "1" when (tmp_cast_i_fu_266_p1 = r_V_reg_312) else "0";
exitcond3_i_fu_244_p2 <= "1" when (t_V_reg_207 = rows_V_reg_302) else "0";
exitcond_i_fu_255_p2 <= "1" when (t_V_1_reg_218 = cols_V_reg_307) else "0";
i_V_fu_249_p2 <= std_logic_vector(unsigned(t_V_reg_207) + unsigned(ap_const_lv32_1));
img_cols_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_blk_n <= img_cols_V_empty_n;
else
img_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_read <= ap_const_logic_1;
else
img_cols_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_0_V_blk_n_assign_proc : process(img_data_stream_0_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_326)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_0_V_blk_n <= img_data_stream_0_V_empty_n;
else
img_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_0_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_0_V_read <= ap_const_logic_1;
else
img_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_blk_n_assign_proc : process(img_data_stream_1_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_326)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_1_V_blk_n <= img_data_stream_1_V_empty_n;
else
img_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_1_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_1_V_read <= ap_const_logic_1;
else
img_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_blk_n_assign_proc : process(img_data_stream_2_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_326)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_2_V_blk_n <= img_data_stream_2_V_empty_n;
else
img_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_2_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_326, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_2_V_read <= ap_const_logic_1;
else
img_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
img_rows_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_blk_n <= img_rows_V_empty_n;
else
img_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_read <= ap_const_logic_1;
else
img_rows_V_read <= ap_const_logic_0;
end if;
end process;
j_V_fu_260_p2 <= std_logic_vector(unsigned(t_V_1_reg_218) + unsigned(ap_const_lv32_1));
lhs_V_cast_i_fu_229_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(img_cols_V_dout),33));
r_V_fu_233_p2 <= std_logic_vector(unsigned(lhs_V_cast_i_fu_229_p1) + unsigned(ap_const_lv33_1FFFFFFFF));
stream_out_TDATA <= AXI_video_strm_V_data_V_1_data_out;
stream_out_TDATA_blk_n_assign_proc : process(AXI_video_strm_V_data_V_1_state, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_326, ap_enable_reg_pp0_iter2, exitcond_i_reg_326_pp0_iter1_reg)
begin
if ((((exitcond_i_reg_326_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((exitcond_i_reg_326 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
stream_out_TDATA_blk_n <= AXI_video_strm_V_data_V_1_state(1);
else
stream_out_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
stream_out_TDEST <= AXI_video_strm_V_dest_V_1_data_out;
stream_out_TID <= AXI_video_strm_V_id_V_1_data_out;
stream_out_TKEEP <= AXI_video_strm_V_keep_V_1_data_out;
stream_out_TLAST <= AXI_video_strm_V_last_V_1_data_out;
stream_out_TSTRB <= AXI_video_strm_V_strb_V_1_data_out;
stream_out_TUSER <= AXI_video_strm_V_user_V_1_data_out;
stream_out_TVALID <= AXI_video_strm_V_dest_V_1_state(0);
tmp_cast_i_fu_266_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_1_reg_218),33));
tmp_data_V_fu_279_p4 <= ((img_data_stream_2_V_dout & img_data_stream_1_V_dout) & img_data_stream_0_V_dout);
end behav;
|
mit
|
e9d7219a80cbc1ddfed0f0d254df8788
| 0.60237 | 2.537235 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/TBFMul.vhd
| 1 | 2,331 |
library ieee;
use ieee.std_logic_1164.ALL;
entity TBFMul is
end TBFMul;
architecture testbench of TBFMul is
component TBCommon
port (
clk : buffer std_logic;
a : out std_logic_vector(31 downto 0);
b : out std_logic_vector(31 downto 0);
d : in std_logic_vector(31 downto 0));
end component;
component FMul
port (
clk : in std_logic;
flt_in1 : in std_logic_vector(31 downto 0);
flt_in2 : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end component;
signal clk : std_logic;
signal a1, b1, d1 : std_logic_vector(31 downto 0);
signal a2, b2, d2 : std_logic_vector(31 downto 0) := (others => '0');
signal a3, b3, d3 : std_logic_vector(31 downto 0) := (others => '0');
signal d_out, d_fmul : std_logic_vector(31 downto 0);
signal x1 : boolean;
signal x2, x3 : boolean := false;
signal a_sgn, b_sgn : std_logic;
signal a_exp, b_exp : std_logic_vector(7 downto 0);
signal a_frc, b_frc : std_logic_vector(22 downto 0);
constant z_exp : std_logic_vector(7 downto 0) := (others => '0');
constant h_exp : std_logic_vector(7 downto 0) := (others => '1');
constant z_frc : std_logic_vector(22 downto 0) := (others => '0');
constant o_frc : std_logic_vector(22 downto 0) := x"00000" & "001";
begin
tbcommon_map : TBCommon port map (
clk => clk,
a => a1,
b => b1,
d => d_out);
fmul_map : FMul port map (
clk => clk,
flt_in1 => a1,
flt_in2 => b1,
flt_out => d_fmul);
main : process(clk)
begin
if rising_edge(clk) then
a2 <= a1;
b2 <= b1;
d2 <= d1;
x2 <= x1;
a3 <= a2;
b3 <= b2;
d3 <= d2;
x3 <= x2;
end if;
end process;
a_sgn <= a1(31);
b_sgn <= b1(31);
a_exp <= a1(30 downto 23);
b_exp <= b1(30 downto 23);
a_frc <= a1(22 downto 0);
b_frc <= b1(22 downto 0);
d1 <= (a_sgn xor b_sgn) & h_exp & o_frc when a_exp = z_exp or b_exp = z_exp else
(a_sgn xor b_sgn) & h_exp & (a_frc or b_frc);
x1 <= a_exp = h_exp or b_exp = h_exp;
d_out <= d3 when x3 else d_fmul;
end testbench;
|
bsd-2-clause
|
7498d136d726d1b66c9f1dcac8b55778
| 0.520807 | 3.01943 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/src/ConfigClockGen.vhd
| 1 | 18,309 |
----------------------------------------------------------------------------------
-- Company: digilent.com
-- Engineer: Robert Bocos
--
-- Create Date: 2021
-- Design Name:
-- Module Name: ConfigClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions: 2021.1
-- Description:
--
-- Dependencies: PkgZmodDigitizer.vhd, TWI_Ctl.vhd, ResetBridge.vhd, SyncAsync.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------------
--
-- This module configures the CDCE6214-Q1 clock generator over I2C.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use work.PkgTWI_Utils.ALL;
use work.PkgZmodDigitizer.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ConfigClockGen is
Generic(
-- Clock Generator I2C shortened config for simulation
kCDCE_SimulationConfig : boolean := false;
-- Clock Generator I2C shortened configuration number of commands to send over I2C for simulation (zero based)
kCDCE_SimulationCmdTotal : integer range 0 to kCDCE_RegNrZeroBased := kCDCE_RegNrZeroBased;
-- Clock Generator I2C 8 bit config address (0xCE(Fall-Back Mode), 0xD0(Default Mode), 0xD2)
kCDCEI2C_Addr : std_logic_vector(7 downto 0) := x"CE";
-- Clock Generator input reference clock selection parameter ('0' selects SECREF(XTAL) and '1' selects PRIREF(FPGA))
kRefSel : std_logic := '0';
-- Clock Generator EEPROM Page selection parameter ('0' selects Page 0 and '1' selects Page 1)
kHwSwCtrlSel : std_logic := '1';
-- Parameter identifying the CDCE output frequency with SECREF(XTAL) as reference frequency:
-- 0 -> 122.88MHz
-- 1 -> 50MHz
-- 2 -> 80MHz
-- 3 -> 100MHz
-- 4 -> 110MHz
-- 5 -> 120MHz
-- 6 -> 125MHz
kFreqSel : integer range 0 to CDCE_I2C_Cmds'length := 0
);
Port (
-- 100MHZ clock input.
RefClk : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in RefClk domain).
arRst : in std_logic;
-- Clock Generator configuration done succesful signal
rInitConfigDoneClockGen : out std_logic;
-- Clock Generator PLL lock signal sent via the GPIO1 or GPIO4 port
aCG_PLL_Lock : in std_logic;
-- Clock Generator PLL lock signal sent via the GPIO1 or GPIO4 port and synchronized in the RefClk domain
rPLL_LockClockGen : out std_logic;
-- rConfigADCEnable is used to hold the ConfigADC module in reset until the Clock Generator is configured and locked
rConfigADCEnable : out std_logic;
-- Clock Generator reference selection signal ('0' selects SECREF(XTAL) and '1' selects PRIREF(FPGA))
aREFSEL : out std_logic;
-- Clock Generator EEPROM Page selection signal
aHW_SW_CTRL : out std_logic;
-- Clock Generator power down signal, passthrough output
rPDNout_n : out std_logic;
----------------------------------------------------------------------------------
-- IIC bus signals
----------------------------------------------------------------------------------
s_scl_i : in std_logic; -- IIC Serial Clock Input from 3-state buffer (required)
s_scl_o : out std_logic; -- IIC Serial Clock Output to 3-state buffer (required)
s_scl_t : out std_logic; -- IIC Serial Clock Output Enable to 3-state buffer (required)
s_sda_i : in std_logic; -- IIC Serial Data Input from 3-state buffer (required)
s_sda_o : out std_logic; -- IIC Serial Data Output to 3-state buffer (required)
s_sda_t : out std_logic -- IIC Serial Data Output Enable to 3-state buffer (required)
);
end ConfigClockGen;
architecture Behavioral of ConfigClockGen is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of s_scl_i: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO of s_scl_o: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO of s_scl_t: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SCL_T";
ATTRIBUTE X_INTERFACE_INFO of s_sda_i: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO of s_sda_o: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO of s_sda_t: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SDA_T";
signal rRst : std_logic;
signal rI2C_ErrorType : error_type;
signal rCmdCnt : unsigned(6 downto 0) := (others => '0');
signal rIncCmdCnt, rConfigDone, rReadBackDone : std_logic := '0';
signal rRstCmdCnt : std_logic := '0';
signal rPLL_LockClockGen_Loc : std_logic := '0';
signal rConfigADCEnable_Loc : std_logic := '0';
signal rReadBackErr : std_logic := '0';
constant kCmdTotal : integer range 0 to ((CDCE_I2C_Cmds(kFreqSel)'length)-1) := ((CDCE_I2C_Cmds(kFreqSel)'length)-1);
constant kReadBackInt : integer range 0 to ((CDCE_I2C_Cmds(kFreqSel)'length)-1) := 83;
signal rState : FsmStatesI2C_t := stIdle;
signal rNState : FsmStatesI2C_t;
signal rI2C_DataIn, rI2C_DataOut, rI2C_Address : std_logic_vector(7 downto 0);
signal rI2C_Stb, rI2C_Done, rI2C_Error, rI2C_Msg, rI2C_Stp : std_logic;
signal aREFSEL_TriStateCtl : std_logic;
signal aHW_SW_CTRL_TriStateCtl : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of rCmdCnt, rIncCmdCnt, rConfigDone, rReadBackDone, rConfigADCEnable_Loc, rRstCmdCnt, rReadBackErr, rState, rNState, rI2C_DataIn, rI2C_DataOut, rI2C_Address, rI2C_Stb, rI2C_Stp, rI2C_Done, rI2C_Error, rI2C_Msg : signal is "TRUE";
begin
OBUFT_REFSEL_inst : OBUFT
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => aREFSEL, -- Buffer output (connect directly to top-level port)
I => kRefSel, -- Buffer input
T => aREFSEL_TriStateCtl -- 3-state enable input
);
OBUFT_HWSWCTRL_inst : OBUFT
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => aHW_SW_CTRL, -- Buffer output (connect directly to top-level port)
I => kHwSwCtrlSel, -- Buffer input
T => aHW_SW_CTRL_TriStateCtl -- 3-state enable input
);
-- Instantiate the I2C Master Transmitter
TWI_Inst: entity work.TWI_Ctl
Generic Map(
CLOCKFREQ => 100
)
Port Map(
MSG_I => rI2C_Msg,
STB_I => rI2C_Stb,
STP_I => rI2C_Stp,
A_I => rI2C_Address,
D_I => rI2C_DataIn,
D_O => rI2C_DataOut,
DONE_O => rI2C_Done,
ERR_O => rI2C_Error,
ERRTYPE_O => rI2C_ErrorType,
CLK => RefClk,
SRST => rRst,
----------------------------------------------------------------------------------
-- TWI bus signals
----------------------------------------------------------------------------------
s_scl_i => s_scl_i,
s_scl_o => s_scl_o,
s_scl_t => s_scl_t,
s_sda_i => s_sda_i,
s_sda_o => s_sda_o,
s_sda_t => s_sda_t
);
TWI_Ctl_Reset_Synchro: entity work.ResetBridge
Generic map(
kPolarity => '1')
Port map(
aRst => arRst,
OutClk => RefClk,
aoRst => rRst);
Synchro_CDCE_PLL: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => arRst,
aIn => aCG_PLL_Lock,
OutClk => RefClk,
oOut => rPLL_LockClockGen_Loc);
rPLL_LockClockGen <= rPLL_LockClockGen_Loc;
rConfigADCEnable <= rConfigADCEnable_Loc;
--Configuration of the ADC over SPI should be done after rConfigADCEnable is asserted which only happens after the CDCE clock generator is configured
--and the PLL inside the CDCE is locked, otherwise the ADC should be reset and reconfigured
ConfigADC_Enable: process (RefClk, arRst, rConfigDone, rReadBackDone, rPLL_LockClockGen_Loc)
begin
if (arRst = '1') then
rConfigADCEnable_Loc <= '0';
elsif (rising_edge(RefClk)) then
if (rPLL_LockClockGen_Loc = '1' and rConfigDone = '1' and kCDCE_SimulationConfig = true) then
rConfigADCEnable_Loc <= '1';
elsif (rPLL_LockClockGen_Loc = '1' and rConfigDone = '1' and rReadBackDone = '1') then
rConfigADCEnable_Loc <= '1';
else
rConfigADCEnable_Loc <= '0';
end if;
end if;
end process ConfigADC_Enable;
--Registered Clock Generator configuration done succesfully signal output
ConfigClockGenDone: process (RefClk, arRst, rConfigDone, rReadBackDone)
begin
if (arRst = '1') then
rInitConfigDoneClockGen <= '0';
elsif (rising_edge(RefClk)) then
if (rConfigDone = '1' and kCDCE_SimulationConfig = true) then
rInitConfigDoneClockGen <= '1';
elsif (rConfigDone = '1' and rReadBackDone = '1') then
rInitConfigDoneClockGen <= '1';
else
rInitConfigDoneClockGen <= '0';
end if;
end if;
end process ConfigClockGenDone;
-- ROM/RAM sync output
RegisteredOutput: process (RefClk, arRst)
begin
if (arRst = '1') then
rI2C_DataIn <= (others => '0');
rConfigDone <= '0';
rRstCmdCnt <= '0';
rReadBackErr <= '0';
rReadBackDone <= '0';
rPDNout_n <= '0';
elsif Rising_Edge(RefClk) then
if(rState = stRegAddress_H) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(to_integer(rCmdCnt))(31 downto 24);--Register Address High
rRstCmdCnt <= '1';
elsif (rState = stRegAddress_L) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(to_integer(rCmdCnt))(23 downto 16);--Register Address Low
rRstCmdCnt <= '1';
elsif (rState = stRegData_H) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(to_integer(rCmdCnt))(15 downto 8);--Register Data High
rRstCmdCnt <= '1';
elsif (rState = stRegData_L) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(to_integer(rCmdCnt))(7 downto 0);--Register Data Low
rRstCmdCnt <= '1';
elsif (rState = StCheckCmdCnt) then
rRstCmdCnt <= '1';
if (kCDCE_SimulationConfig = true) then
if (rCmdCnt = kCDCE_SimulationCmdTotal) then
rConfigDone <= '1';
rRstCmdCnt <= '0';
end if;
elsif (rCmdCnt = kCmdTotal) then
rConfigDone <= '1';
rRstCmdCnt <= '0';
else
rRstCmdCnt <= '1';
rConfigDone <= '0';
end if;
elsif (rState = stIdle) then
rReadBackErr <= '0';
rRstCmdCnt <= '0';
rPDNout_n <= '1';
elsif (rState = stReadBackAddress_H) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(kReadBackInt)(31 downto 24);--Register Address High
elsif (rState = stReadBackAddress_L) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(kReadBackInt)(23 downto 16);--Register Address Low
elsif (rState = stReadBackData_H) then
if (rI2C_Done = '1' and rI2C_Error = '0') then
if CDCE_I2C_Cmds(kFreqSel)(kReadBackInt)(15 downto 8) /= (rI2C_DataOut and CDCE_I2C_Masks(kReadBackInt)(15 downto 8)) then
rReadBackErr <= '1';
end if;
end if;
elsif (rState = stReadBackData_L) then
if (rI2C_Done = '1' and rI2C_Error = '0') then
if CDCE_I2C_Cmds(kFreqSel)(kReadBackInt)(7 downto 0) /= (rI2C_DataOut and CDCE_I2C_Masks(kReadBackInt)(7 downto 0)) then
rReadBackErr <= '1';
end if;
end if;
elsif (rState = stCheckReadBackError) then
if (rReadBackErr = '1') then
rConfigDone <= '0';
rReadBackDone <= '0';
else
rReadBackDone <= '1';
end if;
end if;
end if;
end process RegisteredOutput;
-- Counter used to track the number of successfully sent commands.
ProcCmdCounter: process (RefClk, arRst)
begin
if (arRst = '1') then
rCmdCnt <= (others => '0');
elsif (rising_edge(RefClk)) then
if (rRstCmdCnt = '0') then
rCmdCnt <= (others => '0');
elsif (rIncCmdCnt = '1') then
rCmdCnt <= rCmdCnt + 1;
end if;
end if;
end process;
-- State machine synchronous process.
ProcSyncFsm: process (RefClk, arRst)
begin
if (arRst = '1') then
rState <= stIdle;
elsif (rising_edge(RefClk)) then
rState <= rNState;
end if;
end process;
--MOORE State-Machine - Outputs based on state only
rI2C_Stb <= '1' when (rState = stRegAddress_H or rState = stRegAddress_L or rState = stRegData_H or rState = stRegData_L) else
'1' when (rState = stReadBackAddress_H or rState = stReadBackAddress_L or rState = stReadBackData_H or rState = stReadBackData_L) else
'0';
rI2C_Msg <= '1' when (rState = stRegAddress_H or rState = stReadBackAddress_H) else
'1' when (rState = stReadBackData_H) else
'0';
rI2C_Stp <= '1' when (rState = stRegAddress_H or rState = stReadBackAddress_H) else
'0';
rI2C_Address <= (kCDCEI2C_Addr(7 downto 1) & '1') when (rState = stReadBackData_H or rState = stReadBackData_L) else kCDCEI2C_Addr;
--MEALY State-Machine
rIncCmdCnt <= '1' when (rState = stCheckConfigDone and rConfigDone = '0') else
'0';
aREFSEL_TriStateCtl <= '1' when (kCDCEI2C_Addr = x"CE") else '0';
aHW_SW_CTRL_TriStateCtl <= '1' when (kCDCEI2C_Addr = x"CE") else '0';
NextStateDecode: process (rState, rI2C_Done, rI2C_Error, rConfigDone, rReadBackDone, rReadBackErr)
begin
--declare default state for next_state to avoid latches
rNState <= rState;
case (rState) is
when stIdle =>
if (rConfigDone = '0') then
rNState <= stRegAddress_H;
elsif (kCDCE_SimulationConfig = false) then
if (rReadBackDone = '0') then
rNState <= stReadBackAddress_H;
end if;
end if;
when stRegAddress_H =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stRegAddress_L;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stRegAddress_L =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stRegData_H;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stRegData_H =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stRegData_L;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stRegData_L =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stCheckCmdCnt;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stCheckCmdCnt =>
rNState <= stCheckConfigDone;
when stCheckConfigDone =>
if (rConfigDone = '1') then
rNState <= stIdle;
else
rNState <= stRegAddress_H;
end if;
when stReadBackAddress_H =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stReadBackAddress_L;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stReadBackAddress_L =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stReadBackData_H;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stReadBackData_H =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stReadBackData_L;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stReadBackData_L =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stCheckReadBackError;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stCheckReadBackError =>
if (rReadBackErr = '1') then
rNState <= stIdle;
else
rNState <= stCheckReadBackDone;
end if;
when stCheckReadBackDone =>
if (rReadBackDone = '1') then
rNState <= stIdle;
else
rNState <= stReadBackAddress_H;
end if;
when others =>
rNState <= stIdle;
end case;
end process NextStateDecode;
end Behavioral;
|
mit
|
ae8b07ea20142e33cc0b1141101bcfdc
| 0.536239 | 4.293856 | false | true | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
matrix/matrix.vhd
| 1 | 3,107 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity matrix is
Port (
clock : in std_logic;
selector : out std_logic_vector( 2 downto 0 );
display : out std_logic_vector( 7 downto 0 )
);
end matrix;
architecture Behavioral of matrix is
--signal count:std_logic_vector( 15 downto 0 );
signal count:std_logic_vector( 6 downto 0 );
signal number:std_logic_vector( 2 downto 0 );
begin
process( clock )
begin
if clock'event and clock = '1' then
count <= count + 1;
if count = 0 then
if number = 0 then
selector <= "000";
-- display <= "11100000";
elsif number = 1 then
selector <= "001";
-- display <= "11000000";
elsif number = 2 then
selector <= "010";
-- display <= "10110111";
elsif number = 3 then
selector <= "011";
-- display <= "00110111";
elsif number = 4 then
selector <= "100";
-- display <= "00110111";
elsif number = 5 then
selector <= "101";
-- display <= "10110111";
elsif number = 6 then
selector <= "110";
-- display <= "11000000";
else
selector <= "111";
-- display <= "11100000";
end if;
number <= number + 1;
end if;
end if;
-- A
--display <=
-- "11100000" when number = 1 else
-- "11000000" when number = 2 else
-- "10110111" when number = 3 else
-- "00110111" when number = 4 else
-- "00110111" when number = 5 else
-- "10110111" when number = 6 else
-- "11000000" when number = 7 else
-- "11100000" ;
end process;
-- A
display <=
"11100000" when number = 0 else
"11000000" when number = 1 else
"10110111" when number = 2 else
"00110111" when number = 3 else
"00110111" when number = 4 else
"10110111" when number = 5 else
"11000000" when number = 6 else
"11100000" ;
-- runhorse
-- display <=
-- "11111110" when number = 0 else
-- "11111101" when number = 1 else
-- "11111011" when number = 2 else
-- "11110111" when number = 3 else
-- "11101111" when number = 4 else
-- "11011111" when number = 5 else
-- "10111111" when number = 6 else
-- "01111111" ;
-- I
-- display <=
-- "01111110" when number = 1 else
-- "01111110" when number = 2 else
-- "01111110" when number = 3 else
-- "00000000" when number = 4 else
-- "00000000" when number = 5 else
-- "01111110" when number = 6 else
-- "01111110" when number = 7 else
-- "01111110" ;
-- C
-- display <=
-- "11100111" when number = 1 else
-- "11011011" when number = 2 else
-- "10111101" when number = 3 else
-- "01111110" when number = 4 else
-- "01111110" when number = 5 else
-- "01111110" when number = 6 else
-- "10111101" when number = 7 else
-- "11011011" ;
end Behavioral;
|
mit
|
20220ffc9bebc11b5bfb1ba4a451213e
| 0.577406 | 3.135217 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/AXIvideo2Mat.vhd
| 1 | 69,169 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity AXIvideo2Mat is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC;
img_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_out_full_n : IN STD_LOGIC;
img_rows_V_out_write : OUT STD_LOGIC;
img_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_out_full_n : IN STD_LOGIC;
img_cols_V_out_write : OUT STD_LOGIC );
end;
architecture behav of AXIvideo2Mat is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_data_out : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_payload_A : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_payload_B : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_data_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_user_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_last_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal stream_in_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
signal ap_block_pp1_stage0 : BOOLEAN;
signal exitcond_i_reg_442 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_reg_451 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
signal ap_block_pp2_stage0 : BOOLEAN;
signal eol_2_i_reg_270 : STD_LOGIC_VECTOR (0 downto 0);
signal img_rows_V_blk_n : STD_LOGIC;
signal img_cols_V_blk_n : STD_LOGIC;
signal img_data_stream_0_V_blk_n : STD_LOGIC;
signal img_data_stream_1_V_blk_n : STD_LOGIC;
signal img_data_stream_2_V_blk_n : STD_LOGIC;
signal img_rows_V_out_blk_n : STD_LOGIC;
signal img_cols_V_out_blk_n : STD_LOGIC;
signal t_V_2_reg_200 : STD_LOGIC_VECTOR (10 downto 0);
signal eol_i_reg_211 : STD_LOGIC_VECTOR (0 downto 0);
signal eol_reg_223 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_i_reg_234 : STD_LOGIC_VECTOR (23 downto 0);
signal axi_last_V_3_i_reg_281 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_3_i_reg_293 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_fu_315_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_reg_403 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_block_state1 : BOOLEAN;
signal tmp_44_fu_319_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_44_reg_408 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_data_V_reg_413 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_last_V_reg_421 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_i_fu_336_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_V_fu_341_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_437 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_i_fu_351_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state5_pp1_stage0_iter0 : BOOLEAN;
signal ap_predicate_op75_read_state6 : BOOLEAN;
signal ap_block_state6_pp1_stage0_iter1 : BOOLEAN;
signal ap_block_pp1_stage0_11001 : BOOLEAN;
signal j_V_fu_356_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
signal brmerge_i_fu_365_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state8_pp2_stage0_iter0 : BOOLEAN;
signal ap_block_state9_pp2_stage0_iter1 : BOOLEAN;
signal ap_block_pp2_stage0_11001 : BOOLEAN;
signal ap_block_pp1_stage0_subdone : BOOLEAN;
signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_block_pp2_stage0_subdone : BOOLEAN;
signal ap_phi_mux_eol_2_i_phi_fu_273_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V1_i_reg_169 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal axi_data_V1_i_reg_179 : STD_LOGIC_VECTOR (23 downto 0);
signal t_V_reg_189 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_phi_mux_eol_i_phi_fu_215_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_p_Val2_s_phi_fu_262_p4 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp1_iter1_p_Val2_s_reg_258 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_block_pp1_stage0_01001 : BOOLEAN;
signal sof_1_i_fu_98 : STD_LOGIC_VECTOR (0 downto 0);
signal t_V_cast_i_fu_332_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal t_V_3_cast_i_fu_347_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_user_V_fu_323_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_idle_pp1 : STD_LOGIC;
signal ap_enable_pp1 : STD_LOGIC;
signal ap_idle_pp2 : STD_LOGIC;
signal ap_enable_pp2 : STD_LOGIC;
signal ap_condition_529 : BOOLEAN;
begin
AXI_video_strm_V_data_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out))) then
AXI_video_strm_V_data_V_0_sel_rd <= not(AXI_video_strm_V_data_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) then
AXI_video_strm_V_data_V_0_sel_wr <= not(AXI_video_strm_V_data_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_dest_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_out))) then
AXI_video_strm_V_last_V_0_sel_rd <= not(AXI_video_strm_V_last_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) then
AXI_video_strm_V_last_V_0_sel_wr <= not(AXI_video_strm_V_last_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_out))) then
AXI_video_strm_V_user_V_0_sel_rd <= not(AXI_video_strm_V_user_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) then
AXI_video_strm_V_user_V_0_sel_wr <= not(AXI_video_strm_V_user_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
else
if (((exitcond_i_fu_351_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
else
if (((ap_phi_mux_eol_2_i_phi_fu_273_p4 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
axi_data_V1_i_reg_179_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_data_V1_i_reg_179 <= tmp_data_V_reg_413;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_data_V1_i_reg_179 <= axi_data_V_3_i_reg_293;
end if;
end if;
end process;
axi_data_V_1_i_reg_234_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
axi_data_V_1_i_reg_234 <= ap_phi_mux_p_Val2_s_phi_fu_262_p4;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
axi_data_V_1_i_reg_234 <= axi_data_V1_i_reg_179;
end if;
end if;
end process;
axi_data_V_3_i_reg_293_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_data_V_3_i_reg_293 <= axi_data_V_1_i_reg_234;
elsif (((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_data_V_3_i_reg_293 <= AXI_video_strm_V_data_V_0_data_out;
end if;
end if;
end process;
axi_last_V1_i_reg_169_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_last_V1_i_reg_169 <= tmp_last_V_reg_421;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_last_V1_i_reg_169 <= axi_last_V_3_i_reg_281;
end if;
end if;
end process;
axi_last_V_3_i_reg_281_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_last_V_3_i_reg_281 <= eol_reg_223;
elsif (((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_last_V_3_i_reg_281 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_2_i_reg_270_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
eol_2_i_reg_270 <= eol_i_reg_211;
elsif (((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
eol_2_i_reg_270 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_i_reg_211_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_i_reg_211 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_i_reg_211 <= ap_const_lv1_0;
end if;
end if;
end process;
eol_reg_223_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_reg_223 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_reg_223 <= axi_last_V1_i_reg_169;
end if;
end if;
end process;
sof_1_i_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_351_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
sof_1_i_fu_98 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
sof_1_i_fu_98 <= ap_const_lv1_1;
end if;
end if;
end process;
t_V_2_reg_200_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_351_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
t_V_2_reg_200 <= j_V_fu_356_p2;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
t_V_2_reg_200 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_189_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
t_V_reg_189 <= ap_const_lv11_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
t_V_reg_189 <= i_V_reg_437;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_A)) then
AXI_video_strm_V_data_V_0_payload_A <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_B)) then
AXI_video_strm_V_data_V_0_payload_B <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_A)) then
AXI_video_strm_V_last_V_0_payload_A <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_B)) then
AXI_video_strm_V_last_V_0_payload_B <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_A)) then
AXI_video_strm_V_user_V_0_payload_A <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_B)) then
AXI_video_strm_V_user_V_0_payload_B <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_351_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
brmerge_i_reg_451 <= brmerge_i_fu_365_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
exitcond_i_reg_442 <= exitcond_i_fu_351_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
i_V_reg_437 <= i_V_fu_341_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_44_reg_408 <= tmp_44_fu_319_p1;
tmp_reg_403 <= tmp_fu_315_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
tmp_data_V_reg_413 <= AXI_video_strm_V_data_V_0_data_out;
tmp_last_V_reg_421 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, AXI_video_strm_V_data_V_0_vld_out, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, exitcond2_i_fu_336_p2, ap_CS_fsm_state4, ap_enable_reg_pp1_iter0, ap_block_pp1_stage0_subdone, ap_enable_reg_pp2_iter0, ap_block_pp2_stage0_subdone, tmp_user_V_fu_323_p1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((tmp_user_V_fu_323_p1 = ap_const_lv1_0) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state2;
elsif (((tmp_user_V_fu_323_p1 = ap_const_lv1_1) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
if (((exitcond2_i_fu_336_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_pp1_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
when ap_ST_fsm_pp2_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
end if;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
AXI_video_strm_V_data_V_0_ack_in <= AXI_video_strm_V_data_V_0_state(1);
AXI_video_strm_V_data_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_270, ap_predicate_op75_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_data_V_0_data_out_assign_proc : process(AXI_video_strm_V_data_V_0_payload_A, AXI_video_strm_V_data_V_0_payload_B, AXI_video_strm_V_data_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_sel)) then
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_B;
else
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_data_V_0_load_A <= (not(AXI_video_strm_V_data_V_0_sel_wr) and AXI_video_strm_V_data_V_0_state_cmp_full);
AXI_video_strm_V_data_V_0_load_B <= (AXI_video_strm_V_data_V_0_state_cmp_full and AXI_video_strm_V_data_V_0_sel_wr);
AXI_video_strm_V_data_V_0_sel <= AXI_video_strm_V_data_V_0_sel_rd;
AXI_video_strm_V_data_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_data_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_data_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_data_V_0_vld_out <= AXI_video_strm_V_data_V_0_state(0);
AXI_video_strm_V_dest_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_270, ap_predicate_op75_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_dest_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_ack_in <= AXI_video_strm_V_last_V_0_state(1);
AXI_video_strm_V_last_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_270, ap_predicate_op75_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_last_V_0_data_out_assign_proc : process(AXI_video_strm_V_last_V_0_payload_A, AXI_video_strm_V_last_V_0_payload_B, AXI_video_strm_V_last_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_sel)) then
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_B;
else
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_last_V_0_load_A <= (not(AXI_video_strm_V_last_V_0_sel_wr) and AXI_video_strm_V_last_V_0_state_cmp_full);
AXI_video_strm_V_last_V_0_load_B <= (AXI_video_strm_V_last_V_0_state_cmp_full and AXI_video_strm_V_last_V_0_sel_wr);
AXI_video_strm_V_last_V_0_sel <= AXI_video_strm_V_last_V_0_sel_rd;
AXI_video_strm_V_last_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_last_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_last_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_vld_out <= AXI_video_strm_V_last_V_0_state(0);
AXI_video_strm_V_user_V_0_ack_in <= AXI_video_strm_V_user_V_0_state(1);
AXI_video_strm_V_user_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_270, ap_predicate_op75_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_user_V_0_data_out_assign_proc : process(AXI_video_strm_V_user_V_0_payload_A, AXI_video_strm_V_user_V_0_payload_B, AXI_video_strm_V_user_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_sel)) then
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_B;
else
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_user_V_0_load_A <= (not(AXI_video_strm_V_user_V_0_sel_wr) and AXI_video_strm_V_user_V_0_state_cmp_full);
AXI_video_strm_V_user_V_0_load_B <= (AXI_video_strm_V_user_V_0_state_cmp_full and AXI_video_strm_V_user_V_0_sel_wr);
AXI_video_strm_V_user_V_0_sel <= AXI_video_strm_V_user_V_0_sel_rd;
AXI_video_strm_V_user_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_user_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_user_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_user_V_0_vld_out <= AXI_video_strm_V_user_V_0_state(0);
ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(4);
ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(7);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state7 <= ap_CS_fsm(5);
ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_01001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_predicate_op75_read_state6)
begin
ap_block_pp1_stage0_01001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_predicate_op75_read_state6)
begin
ap_block_pp1_stage0_11001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_predicate_op75_read_state6)
begin
ap_block_pp1_stage0_subdone <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp2_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_270)
begin
ap_block_pp2_stage0_11001 <= ((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_pp2_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_270)
begin
ap_block_pp2_stage0_subdone <= ((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_state1_assign_proc : process(real_start, ap_done_reg, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
ap_block_state1 <= ((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state5_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp1_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond_i_reg_442, ap_predicate_op75_read_state6)
begin
ap_block_state6_pp1_stage0_iter1 <= (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_block_state8_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp2_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, eol_2_i_reg_270)
begin
ap_block_state9_pp2_stage0_iter1 <= ((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out));
end process;
ap_condition_529_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442)
begin
ap_condition_529 <= ((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0));
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond2_i_fu_336_p2, ap_CS_fsm_state4)
begin
if (((exitcond2_i_fu_336_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0)
begin
if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0))) then
ap_idle_pp1 <= ap_const_logic_1;
else
ap_idle_pp1 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter0)
begin
if (((ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))) then
ap_idle_pp2 <= ap_const_logic_1;
else
ap_idle_pp2 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, brmerge_i_reg_451, eol_reg_223, ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245, ap_condition_529)
begin
if ((ap_const_boolean_1 = ap_condition_529)) then
if ((brmerge_i_reg_451 = ap_const_lv1_1)) then
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 <= eol_reg_223;
elsif ((brmerge_i_reg_451 = ap_const_lv1_0)) then
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
end if;
else
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
end if;
end process;
ap_phi_mux_eol_2_i_phi_fu_273_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_i_reg_270)
begin
if (((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_phi_mux_eol_2_i_phi_fu_273_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_eol_2_i_phi_fu_273_p4 <= eol_2_i_reg_270;
end if;
end process;
ap_phi_mux_eol_i_phi_fu_215_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442, eol_i_reg_211, ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_phi_mux_eol_i_phi_fu_215_p4 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
else
ap_phi_mux_eol_i_phi_fu_215_p4 <= eol_i_reg_211;
end if;
end process;
ap_phi_mux_p_Val2_s_phi_fu_262_p4_assign_proc : process(AXI_video_strm_V_data_V_0_data_out, brmerge_i_reg_451, axi_data_V_1_i_reg_234, ap_phi_reg_pp1_iter1_p_Val2_s_reg_258, ap_condition_529)
begin
if ((ap_const_boolean_1 = ap_condition_529)) then
if ((brmerge_i_reg_451 = ap_const_lv1_1)) then
ap_phi_mux_p_Val2_s_phi_fu_262_p4 <= axi_data_V_1_i_reg_234;
elsif ((brmerge_i_reg_451 = ap_const_lv1_0)) then
ap_phi_mux_p_Val2_s_phi_fu_262_p4 <= AXI_video_strm_V_data_V_0_data_out;
else
ap_phi_mux_p_Val2_s_phi_fu_262_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
end if;
else
ap_phi_mux_p_Val2_s_phi_fu_262_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
end if;
end process;
ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245 <= "X";
ap_phi_reg_pp1_iter1_p_Val2_s_reg_258 <= "XXXXXXXXXXXXXXXXXXXXXXXX";
ap_predicate_op75_read_state6_assign_proc : process(exitcond_i_reg_442, brmerge_i_reg_451)
begin
ap_predicate_op75_read_state6 <= ((brmerge_i_reg_451 = ap_const_lv1_0) and (exitcond_i_reg_442 = ap_const_lv1_0));
end process;
ap_ready <= internal_ap_ready;
brmerge_i_fu_365_p2 <= (sof_1_i_fu_98 or ap_phi_mux_eol_i_phi_fu_215_p4);
exitcond2_i_fu_336_p2 <= "1" when (t_V_cast_i_fu_332_p1 = tmp_reg_403) else "0";
exitcond_i_fu_351_p2 <= "1" when (t_V_3_cast_i_fu_347_p1 = tmp_44_reg_408) else "0";
i_V_fu_341_p2 <= std_logic_vector(unsigned(t_V_reg_189) + unsigned(ap_const_lv11_1));
img_cols_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_empty_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_blk_n <= img_cols_V_empty_n;
else
img_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_out_blk_n <= img_cols_V_out_full_n;
else
img_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_out_din <= img_cols_V_dout;
img_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_out_write <= ap_const_logic_1;
else
img_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img_cols_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_read <= ap_const_logic_1;
else
img_cols_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_0_V_blk_n_assign_proc : process(img_data_stream_0_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_blk_n <= img_data_stream_0_V_full_n;
else
img_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_0_V_din <= ap_phi_mux_p_Val2_s_phi_fu_262_p4(8 - 1 downto 0);
img_data_stream_0_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_block_pp1_stage0_11001)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_write <= ap_const_logic_1;
else
img_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_blk_n_assign_proc : process(img_data_stream_1_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_blk_n <= img_data_stream_1_V_full_n;
else
img_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_1_V_din <= ap_phi_mux_p_Val2_s_phi_fu_262_p4(15 downto 8);
img_data_stream_1_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_block_pp1_stage0_11001)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_write <= ap_const_logic_1;
else
img_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_blk_n_assign_proc : process(img_data_stream_2_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_blk_n <= img_data_stream_2_V_full_n;
else
img_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_2_V_din <= ap_phi_mux_p_Val2_s_phi_fu_262_p4(23 downto 16);
img_data_stream_2_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_block_pp1_stage0_11001)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_write <= ap_const_logic_1;
else
img_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
img_rows_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_blk_n <= img_rows_V_empty_n;
else
img_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_out_blk_n <= img_rows_V_out_full_n;
else
img_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_out_din <= img_rows_V_dout;
img_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_out_write <= ap_const_logic_1;
else
img_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img_rows_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_read <= ap_const_logic_1;
else
img_rows_V_read <= ap_const_logic_0;
end if;
end process;
internal_ap_ready_assign_proc : process(exitcond2_i_fu_336_p2, ap_CS_fsm_state4)
begin
if (((exitcond2_i_fu_336_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
j_V_fu_356_p2 <= std_logic_vector(unsigned(t_V_2_reg_200) + unsigned(ap_const_lv11_1));
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (start_full_n = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
stream_in_TDATA_blk_n_assign_proc : process(AXI_video_strm_V_data_V_0_state, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442, brmerge_i_reg_451, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_i_reg_270)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((brmerge_i_reg_451 = ap_const_lv1_0) and (exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
stream_in_TDATA_blk_n <= AXI_video_strm_V_data_V_0_state(0);
else
stream_in_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
stream_in_TREADY <= AXI_video_strm_V_dest_V_0_state(1);
t_V_3_cast_i_fu_347_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_2_reg_200),12));
t_V_cast_i_fu_332_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_189),12));
tmp_44_fu_319_p1 <= img_cols_V_dout(12 - 1 downto 0);
tmp_fu_315_p1 <= img_rows_V_dout(12 - 1 downto 0);
tmp_user_V_fu_323_p1 <= AXI_video_strm_V_user_V_0_data_out;
end behav;
|
mit
|
2ddd5fd81e062a3a5ad0ec77016626f1
| 0.600558 | 2.607789 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/HS_Negotiation.vhd
| 2 | 24,545 |
-------------------------------------------------------------------------------
--
-- File: HS_Negotiation.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles the USB speed negociatian, reset and suspend protocols
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity HS_Negotiation is
Port (
u_Reset : in STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
--command signals used to initiate register read/write,
--NOPID frameworks of the ULPI state machine
u_Send_NOPID_CMD : out STD_LOGIC;
u_Send_EXTW_CMD : out STD_LOGIC;
u_Send_REGW_CMD : out STD_LOGIC;
u_Send_EXTR_CMD : out STD_LOGIC;
u_Send_REGR_CMD : out STD_LOGIC;
u_Send_STP_CMD : out STD_LOGIC;
u_Send_Last : out STD_LOGIC;
u_Remote_Wake : in STD_LOGIC;
--NOPID data, register data, register address used for
--attachment signaling and for chirping
u_Tx_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Regw_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Reg_Addr : out STD_LOGIC_VECTOR (7 downto 0);
--inputs from ULPI state machine
u_Rx_Cmd_Received : in STD_LOGIC;
u_Tx_Cmd_Done : in STD_LOGIC;
--UTMI+ signals
u_LineState : in STD_LOGIC_VECTOR (1 downto 0);
u_Vbus : in STD_LOGIC_VECTOR (1 downto 0);
-- Negotiation outputs
u_USB_Mode : out STD_LOGIC;
u_Not_Connected : OUT std_logic;
u_Set_Mode_HS : OUT std_logic;
u_Set_Mode_FS : OUT std_logic;
u_Wake : OUT std_logic;
u_USBCMD_RS : in std_logic;
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0);
u_Negociation_Done : out STD_LOGIC
);
end HS_Negotiation;
architecture Behavioral of HS_Negotiation is
constant Const_10Ms : STD_LOGIC_VECTOR (10 downto 0) := "00001100100"; --100
constant Const_20Ms : STD_LOGIC_VECTOR (10 downto 0) := "00011001000"; --200
constant Const_50Ms : STD_LOGIC_VECTOR (10 downto 0) := "00111110100"; --500
constant Const_1_2Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000001100"; --12
constant Const_2_5Us : STD_LOGIC_VECTOR (12 downto 0) := "0000010010110"; --150 * Ulpi_Clk_period = 2.5Us
constant Const_2_5Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000011001"; --25Const_3Ms
constant Const_3Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000011110"; --30
constant Const_200Us : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; --2
type state_type is (IDLE, REGR, EXTR_W, EXTR_R, DISCONNECTED, WAIT_ATTACH, WRITE_FCR, ATTACH, WAIT_RESET, PULL_UP_ID, NORMAL,RST_RES_SUSP, SUSPEND, HS_SUSPEND, FS_SUSPEND, SUSP_RES, RESET, ERROR, SEND_CHIRP_K, WAIT_CHIRP_J, WAIT_CHIRP_K, SEND_CHIRP_K_LAST, WAIT_CHIRP_SE0, SET_FS, SET_HS, SWITCH_FS, FS_WAIT_SE0, FS_WAIT_J, RESUME_REQ_WAIT, WAIT_HSEOP, CLEAR_SUSPEND, SIGNAL_WAKE); -- CLEAR_SUSPEND_COMPLETE
signal u_Negociation_State, u_Negociation_Next_State : state_type;
signal u_RX_J : STD_LOGIC;
signal u_RX_K : STD_LOGIC;
signal u_RX_SE0 : STD_LOGIC;
signal u_RX_Idle : STD_LOGIC;
signal u_Set_Mode_HS_Loc : STD_LOGIC;
signal u_Mode : STD_LOGIC; --1 when the device is in High Speed mode, 0 otherwise
signal u_Negociation_Done_Rst : STD_LOGIC;
signal u_Negociation_Done_Set : STD_LOGIC;
signal u_LineState_q : STD_LOGIC_VECTOR(1 downto 0);
signal u_LineState_Change : STD_LOGIC;
signal u_Cnt1_Us : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt1_Ms : STD_LOGIC_VECTOR(10 downto 0);
signal u_Cnt2_Us : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt1_Ms_Presc : STD_LOGIC;
signal u_Cnt1_Rst_Ms : STD_LOGIC;-- initial 100ms, chirp_k
signal u_Cnt2_Rst_Ms : STD_LOGIC;
signal u_Cnt_Chirp : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal u_Cnt_Chirp_CE : STD_LOGIC;
signal u_Cnt_Chirp_Rst : STD_LOGIC;
--degug
signal u_Cnt1_Ms_debug : STD_LOGIC_VECTOR(10 downto 0);
attribute mark_debug : string;
attribute keep : string;
--attribute mark_debug of state_ind_hs_r : signal is "true";
--attribute keep of state_ind_hs_r : signal is "true";
--attribute mark_debug of rst : signal is "true";
--attribute keep of rst : signal is "true";
--attribute mark_debug of u_LineState : signal is "true";
--attribute keep of u_LineState : signal is "true";
--attribute mark_debug of u_Cnt1_Us : signal is "true";
--attribute keep of u_Cnt1_Us : signal is "true";
--attribute mark_debug of u_Cnt1_Ms : signal is "true";
--attribute keep of u_Cnt1_Ms : signal is "true";
--attribute mark_debug of u_RX_Idle : signal is "true";
--attribute keep of u_RX_Idle : signal is "true";
--attribute mark_debug of u_Cnt1_Rst_Ms : signal is "true";
--attribute keep of u_Cnt1_Rst_Ms : signal is "true";
--attribute mark_debug of u_Mode : signal is "true";
--attribute keep of u_Mode : signal is "true";
--attribute mark_debug of u_Cnt1_Ms_debug : signal is "true";
--attribute keep of u_Cnt1_Ms_debug : signal is "true";
begin
u_USB_Mode <= u_Mode;
u_Set_Mode_HS <= u_Set_Mode_HS_Loc;
u_RX_SE0 <= '1' when u_LineState = "00"
else '0';
u_RX_K <= '1' when u_LineState = "10"
else '0';
u_RX_J <= '1' when u_LineState = "01"
else '0';
u_RX_Idle <= u_RX_SE0 when u_Mode = '1'
else u_RX_J;
--debug purposes
delay_cnt: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
u_Cnt1_Ms_debug <= u_Cnt1_Ms;
end if;
end process;
--detect state machine changes
STATE_CHANGE: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
u_LineState_q <= u_LineState;
if (u_LineState_q = u_LineState) then
u_LineState_Change <= '0';
else
u_LineState_Change <= '1';
end if;
end if;
end process;
--u_Mode encodes the negotiated speed
MODEHS : process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0') then
u_Mode <= '0';
else
if (u_Set_Mode_HS_Loc = '1') then
u_Mode <= '1';
end if;
end if;
end if;
end process;
NEG_DONE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0' or u_Negociation_Done_Rst = '0') then
u_Negociation_Done <= '0';
else
if (u_Negociation_Done_Set = '1') then
u_Negociation_Done <= '1';
end if;
end if;
end if;
end process;
--Counters/Timers used to monitor Reset, Suspend, Resume, High Speed Negotiation characteristic intervals
US_COUNTER1: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if ((u_Cnt1_Rst_Ms = '1') or (u_Reset = '0')) then
u_Cnt1_Us <= (others => '0');
u_Cnt1_Ms_Presc <= '0';
else
u_Cnt1_Us <= u_Cnt1_Us + '1';
if (u_Cnt1_Us = 6000) then -- u_Cnt1_Ms_Presc = 100us
u_Cnt1_Ms_Presc <= '1';
u_Cnt1_Us <= (others => '0');
else
u_Cnt1_Ms_Presc <= '0';
end if;
end if;
end if;
end process;
MS_COUNTER1: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt1_Rst_Ms = '1' or (u_Reset = '0')) then
u_Cnt1_Ms <= (others => '0');
else
if (u_Cnt1_Ms_Presc = '1') then
u_Cnt1_Ms <= u_Cnt1_Ms + '1';
end if;
end if;
end if;
end process;
US_COUNTER2: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt2_Rst_Ms = '1' or (u_Reset = '0')) then
u_Cnt2_Us <= (others => '0');
else
u_Cnt2_Us <= u_Cnt2_Us + '1';
if (u_Cnt2_Us = 6000) then
u_Cnt2_Us <= (others => '0');
end if;
end if;
end if;
end process;
CHIRP_COUNTER: process (u_Cnt_Chirp_CE, Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt_Chirp_Rst = '1' or (u_Reset = '0')) then
u_Cnt_Chirp <= (others => '0');
elsif (u_Cnt_Chirp_CE = '1') then
u_Cnt_Chirp <= u_Cnt_Chirp + '1';
end if;
end if;
end process;
--High Speed Negotiation State Machine
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0') then
u_Negociation_State <= IDLE;
else
u_Negociation_State <= u_Negociation_Next_State;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (u_Negociation_State, u_Vbus, u_Rx_Cmd_Received, u_USBCMD_RS, u_LineState, u_LineState_Change, u_Tx_Cmd_Done, u_RX_J, u_RX_K, u_RX_Idle, u_RX_SE0, u_Cnt_Chirp, u_Remote_Wake, u_Mode)
begin
u_Negociation_Next_State <= u_Negociation_State;
state_ind_hs <= "00000";
u_Tx_Data <= (others => '0');
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Cnt_Chirp_CE <= '0';
u_Cnt_Chirp_Rst <= '1';
u_Set_Mode_HS_Loc <= '0';
u_Negociation_Done_Rst <= '1';
u_Negociation_Done_Set <= '0';
u_Send_REGW_CMD <= '0';
u_Send_NOPID_CMD <= '0';
u_Send_Last <= '0';
u_Tx_Regw_Data <= (others => '0');
u_Tx_Reg_Addr <= (others => '0');
u_Send_REGR_CMD <= '0';
u_Send_EXTW_CMD <= '0';
u_Send_EXTR_CMD <= '0';
u_Send_STP_CMD <= '0';
u_Not_Connected <= '0';
u_Set_Mode_FS <= '0';
u_Wake <= '0';
case (u_Negociation_State) is
when IDLE =>
if (u_USBCMD_RS = '1') then --Waits for user interaction (USBCMD-> RS bit : Run/Stop) to start negociation
u_Negociation_Next_State <= DISCONNECTED;
end if;
when DISCONNECTED =>
state_ind_hs <= "00001";
u_Negociation_Done_Rst <= '0';
u_Not_Connected <= '1';
if (u_Vbus = "11") then
u_Negociation_Next_State <= WAIT_ATTACH;
end if;
when WAIT_ATTACH =>
state_ind_hs <= "00010";
u_Not_Connected <= '1';
u_Cnt1_Rst_Ms <= '0';
if ( u_Cnt1_Ms = Const_50Ms) then -- Debounce interval. Not required by specifications
if (u_Vbus = "11") then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= PULL_UP_ID;
else
u_Negociation_Next_State <= DISCONNECTED;
end if;
end if;
when PULL_UP_ID =>
state_ind_hs <= "00011";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "001010"; --u_Tx_Data (6 downto 0) = OTG control reg write addr
u_Tx_Regw_Data <= "00000001";
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= WRITE_FCR;
end if;
when WRITE_FCR =>
state_ind_hs <= "00100";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --Select peripheral Full Speed driver: opmode = 00, xcvrselect = 01, termselect = 1; the pull-up resistor on D+ will be attached
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= ATTACH;
end if;
when ATTACH =>
state_ind_hs <= "00101";
if (u_LineState = "01") then
u_Negociation_Next_State <= WAIT_RESET;
end if;
when WAIT_RESET => --the host should detect the pull-up resistor and should place the bus in SE0 state
state_ind_hs <= "00110";
u_Cnt1_Rst_Ms <= '0';
if (u_LineState = "00") then
u_Negociation_Next_State <= NORMAL;
end if;
when NORMAL => -- this is the state corresponding to normal operation. The state machine monitors SUSPEND(IDLE) and RESET conditions
state_ind_hs <= "11111";
if ( u_LineState_Change = '0') then
if (u_RX_Idle = '1') then -- if the device is in high speed mode it can not distinguish between IDLE and SE0 at this point
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_3Ms) then
u_Negociation_Next_State <= RST_RES_SUSP;
end if;
elsif ((u_RX_SE0 = '1') and (u_Mode = '0')) then --If the device is being reset from a non-suspended full-speed state, then the device begins a high-speed
--detection handshake after the detection of SE0 for no less than 2.5 ?s and no more than 3.0 ms
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
else
u_Cnt1_Rst_Ms <= '1';
end if;
else
u_Cnt1_Rst_Ms <= '1';
end if;
when RST_RES_SUSP =>
state_ind_hs <= "00111";
if (u_Mode = '0') then
u_Negociation_Next_State <= SUSPEND;
elsif (u_Mode = '1') then
u_Negociation_Next_State <= SWITCH_FS;
end if;
--RESET sequence
when RESET => --Enter High-speed Detection Handshake. Select peripheral chirp by writing to the PHY FCR
state_ind_hs <= "01000";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01010100"; --opmode = 10, xcvrselect = 00, termselect = 1
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SEND_CHIRP_K;
end if;
when SEND_CHIRP_K =>
state_ind_hs <= "01001";
u_Cnt1_Rst_Ms <= '0';
u_Send_NOPID_CMD <= '1'; --This will instruct the ULPI state machine to send NOPID_CMD with transmit data which is by default 00h (drive current into D-)
if (u_Cnt1_Ms = Const_1_2Ms) then --The device chirp must last no less than 1.0 ms (TUCH) and must end no more than 7.0 ms (TUCHEND) high-speed Reset time T0.
u_Cnt1_Rst_Ms <= '1';
u_Send_Last <= '1';
u_Negociation_Next_State <= SEND_CHIRP_K_LAST;
end if;
when SEND_CHIRP_K_LAST =>
state_ind_hs <= "01010";
--u_Tx_Data <= (others => '0');
u_Cnt1_Rst_Ms <= '1';
if (u_Rx_Cmd_Received = '1') then
if (u_RX_SE0 = '1') then
u_Negociation_Next_State <= WAIT_CHIRP_SE0;
end if;
end if;
--------------------------------------------------------------
when WAIT_CHIRP_SE0 =>
state_ind_hs <= "01011";
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
u_Negociation_Next_State <= WAIT_CHIRP_K;
elsif (u_Cnt1_Ms = Const_2_5Ms) then
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
--------------------------------------------------------------
when WAIT_CHIRP_K =>
state_ind_hs <= "01100";
u_Cnt_Chirp_Rst <= '0';
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
if (u_RX_K = '1') then
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
if (u_Cnt2_Us = Const_2_5Us) then
if(u_Cnt_Chirp > 5) then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Cnt_Chirp_Rst <= '1';
u_Cnt_Chirp_CE <= '0';
u_Negociation_Next_State <= SET_HS;
else
u_Cnt_Chirp_CE <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Negociation_Next_State <= WAIT_CHIRP_J;
end if;
end if;
elsif (u_Cnt1_Ms = Const_2_5Ms or u_RX_SE0 = '1') then
u_Send_REGW_CMD <= '1';
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
when WAIT_CHIRP_J =>
state_ind_hs <= "01101";
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
u_Cnt_Chirp_Rst <= '0';
if (u_RX_J = '1') then
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
if (u_Cnt2_Us = Const_2_5Us) then
if(u_Cnt_Chirp > 5) then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Cnt_Chirp_Rst <= '1';
u_Cnt_Chirp_CE <= '0';
u_Negociation_Next_State <= SET_HS;
else
u_Cnt2_Rst_Ms <= '1';
u_Cnt_Chirp_CE <= '1';
u_Negociation_Next_State <= WAIT_CHIRP_K;
end if;
end if;
elsif (u_Cnt1_Ms = Const_2_5Ms or u_RX_SE0 = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "00000101"; --opmode = 00, xcvrselect = 00, termselect = 1
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
when SET_FS =>
state_ind_hs <= "01110";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --opmode = 00, xcvrselect = 01, termselect = 1
u_Send_REGW_CMD <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Done_Set <= '1';
u_Negociation_Next_State <= NORMAL;
end if;
when SET_HS =>
state_ind_hs <= "01111";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000000"; --opmode = 00, xcvrselect = 00, termselect = 0
u_Set_Mode_HS_Loc <= '1';
u_Send_REGW_CMD <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Done_Set <= '1';
u_Negociation_Next_State <= NORMAL;
end if;
---SUSPEND/RESUME -- Not Tested!
when SWITCH_FS => -- Select peripherla Full Speed by writing to FCR
u_Negociation_Done_Rst <= '0';
state_ind_hs <= "10000";
u_Cnt1_Rst_Ms <= '0';
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --opmode = 00, xcvrselect = 01, termselect = 1
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SUSP_RES;
end if;
when SUSP_RES =>
state_ind_hs <= "10001";
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_200Us) then --The device samples the bus state, and checks for SE0 (reset as opposed to suspend), no less than 100 �s and no more than 875 �s (TWTRSTHS) after starting reversion to full-speed.
if( u_RX_SE0 = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
elsif (u_RX_J = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= SUSPEND;
else
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= DISCONNECTED;
end if;
end if;
when SUSPEND =>
state_ind_hs <= "10010";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg set addr
u_Tx_Regw_Data <= "00010101"; --set suspendM
if (u_Tx_Cmd_Done = '1') then
if (u_Mode = '1') then
u_Negociation_Next_State <= HS_SUSPEND;
else
u_Negociation_Next_State <= FS_SUSPEND;
end if;
end if;
when FS_SUSPEND =>
state_ind_hs <= "10011";
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_20Ms) then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= FS_WAIT_SE0;
end if;
elsif (u_RX_SE0 = '1')then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
elsif (u_Remote_Wake = '1') then -- 3ms to enter suspend + 2ms
u_Send_STP_CMD <= '1';
u_Negociation_Next_State <= CLEAR_SUSPEND;
else
u_Cnt1_Rst_Ms <= '1';
end if;
when HS_SUSPEND =>
state_ind_hs <= "10100";
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
state_ind_hs <= "11110";
if (u_Cnt1_Ms = Const_20Ms) then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= WAIT_HSEOP;
end if;
elsif (u_RX_SE0 = '1')then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
state_ind_hs <= "11101";
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
elsif (u_Remote_Wake = '1') then -- 3ms to enter suspend + 2ms
u_Send_STP_CMD <= '1';
u_Negociation_Next_State <= CLEAR_SUSPEND;
else
state_ind_hs <= "11100";
u_Cnt1_Rst_Ms <= '1';
end if;
when FS_WAIT_SE0 =>
state_ind_hs <= "10101";
if (u_RX_SE0 = '1') then
u_Negociation_Next_State <= FS_WAIT_J;
end if;
when FS_WAIT_J =>
state_ind_hs <= "10110";
if (u_RX_J = '1') then
u_Send_REGW_CMD <= '1';
u_Set_Mode_FS <= '1';
u_Wake <= '1';
u_Negociation_Next_State <= SET_FS;
else
u_Negociation_Next_State <= ERROR;
end if;
when WAIT_HSEOP =>
state_ind_hs <= "10111";
if (u_RX_SE0 = '1') then
u_Send_REGW_CMD <= '1';
u_Wake <= '1';
u_Negociation_Next_State <= SET_HS;
end if;
when CLEAR_SUSPEND =>
state_ind_hs <= "11001";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100";
u_Tx_Regw_Data <= "01010101";
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SIGNAL_WAKE;
end if;
when SIGNAL_WAKE =>
state_ind_hs <= "11010";
u_Send_NOPID_CMD <= '1';
u_Tx_Data <= "11111111";
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_10Ms) then
u_Send_Last <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= RESUME_REQ_WAIT;
end if;
end if;
when RESUME_REQ_WAIT =>
state_ind_hs <= "11011";
u_Cnt1_Rst_Ms <= '0';
if (u_RX_K = '1') then
u_Negociation_Next_State <= WAIT_HSEOP;
end if;
when others =>
u_Negociation_Next_State <= DISCONNECTED;
end case;
end process;
end Behavioral;
|
mit
|
a827252eeb22a7b2ead98d4421580771
| 0.551608 | 3.129431 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/Control_Registers.vhd
| 2 | 38,369 |
-------------------------------------------------------------------------------
--
-- File: Control_Registers.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements the control registers required by USB Device IP.
-- Control Registers data is written/read over an AXI Lite interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Control_Registers is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
--Identification: Configuration Constants
USBSCFG_rd : out std_logic_vector(31 downto 0);
--Operational : Interrupts, Schedule Pointers (Host), and Endpoint Pointers (Device)
USBCMD_rd : out std_logic_vector(31 downto 0);
USBSTS_wr_UI : in std_logic;
USBCMD_SUTW_wr : in std_logic;
USBCMD_SUTW_wr_en : in std_logic;
USBCMD_ATDTW_wr : in std_logic;
USBCMD_ATDTW_wr_en : in std_logic;
USBSTS_rd : out std_logic_vector(31 downto 0);
USBSTS_wr_NAKI : in std_logic;
USBSTS_wr_SLI : in std_logic;
USBSTS_wr_SRI : in std_logic;
USBSTS_wr_URI : in std_logic;
USBSTS_wr_PCI : in std_logic;
USBSTS_wr_en_NAK : in std_logic;
USBSTS_wr_en_SLI : in std_logic;
USBSTS_wr_en_SRI : in std_logic;
USBSTS_wr_en_URI : in std_logic;
USBSTS_wr_en_PCI : in std_logic;
USBSTS_wr_en_UI : in std_logic;
USBINTR_rd : out std_logic_vector(31 downto 0);
FRINDEX_rd : out std_logic_vector(31 downto 0);
FRINDEX_wr : in std_logic_vector(10 downto 0);
FRINDEX_wr_en : in std_logic;
a_DEVICEADDR_rd : out std_logic_vector(31 downto 0);
a_DEVICEADDR_IPush : out std_logic;
ENDPOINTLISTADDR_rd : out std_logic_vector(31 downto 0);
ENDPTNAK_rd : out std_logic_vector(31 downto 0);
ENDPTNAK_wr : in std_logic_vector(31 downto 0);
ENDPTNAK_wr_en : in std_logic;
ENDPTNAKEN_rd : out std_logic_vector(31 downto 0);
CONFIGFLAG_rd : out std_logic_vector(31 downto 0);
PORTSC1_rd : out std_logic_vector(31 downto 0);
PORTSC1_PSPD_wr : in std_logic_vector(1 downto 0);
PORTSC1_PSPD_wr_en : in std_logic;
OTGSC_rd : out std_logic_vector(31 downto 0);
USBMODE_rd : out std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_rd : out std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_wr : in std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_wr_en : in std_logic;
ENDPTPRIME_rd : out std_logic_vector(31 downto 0);
ENDPTPRIME_clear : in std_logic_vector(31 downto 0);
ENDPTPRIME_clear_en : in std_logic;
ENDPTPRIME_set : in std_logic_vector(31 downto 0);
ENDPTPRIME_set_en : in std_logic;
EMDPTFLUSH_rd : out std_logic_vector(31 downto 0);
EMDPTFLUSH_clear : in std_logic_vector(31 downto 0);
EMDPTFLUSH_clear_en : in std_logic;
EMDPTFLUSH_set : in std_logic_vector(31 downto 0);
EMDPTFLUSH_set_en : in std_logic;
ENDPTSTAT_wr : in std_logic_vector(31 downto 0);
ENDPTCOMPLETE_rd : out std_logic_vector(31 downto 0);
ENDPTCOMPLETE_wr : in std_logic_vector(31 downto 0);
ENDPTCOMPLETE_wr_en : in std_logic;
ENDPTCTRL0_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL1_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL2_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL3_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL4_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL5_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL6_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL7_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL8_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL9_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL10_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL11_rd : out std_logic_vector(31 downto 0)
);
end Control_Registers;
architecture arch_imp of Control_Registers is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 6;
signal a_USBSCFG_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_USBCMD_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_USBSTS_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_USBINTR_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_FRINDEX_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_DEVICEADDR_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPOINTLISTADDR_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTNAK_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTNAKEN_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_CONFIGFLAG_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_PORTSC1_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_OTGSC_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_USBMODE_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTSETUPSTAT_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTPRIME_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_EMDPTFLUSH_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTSTAT_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCOMPLETE_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL0_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL1_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL2_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL3_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL4_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL5_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL6_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL7_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL8_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL9_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL10_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_ENDPTCTRL11_Reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
constant ID : std_logic_vector(31 downto 0) := (others => '0');
constant HWGENERAL : std_logic_vector(31 downto 0) := (others => '0');
constant HWDEVICE : std_logic_vector(31 downto 0) := (others => '0');
constant HWTXBUF : std_logic_vector(31 downto 0) := (others => '0');
constant HWRXBUF : std_logic_vector(31 downto 0) := (others => '0');
constant CAPLENGTH_HCIVERSION : std_logic_vector(31 downto 0) := (others => '0');
constant DCIVERSION : std_logic_vector(31 downto 0) := (others => '0');
constant DCCPARAMS : std_logic_vector(31 downto 0) := (others => '0');
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of USBCMD_rd : signal is "true";
-- attribute keep of USBCMD_rd : signal is "true";
-- attribute mark_debug of USBSTS_rd : signal is "true";
-- attribute keep of USBSTS_rd : signal is "true";
-- attribute mark_debug of ENDPTPRIME_rd : signal is "true";
-- attribute keep of ENDPTPRIME_rd : signal is "true";
-- attribute mark_debug of ENDPTCTRL0_rd : signal is "true";
-- attribute keep of ENDPTCTRL0_rd : signal is "true";
-- attribute mark_debug of ENDPOINTLISTADDR_rd : signal is "true";
-- attribute keep of ENDPOINTLISTADDR_rd : signal is "true";
-- attribute mark_debug of ENDPTCOMPLETE_rd : signal is "true";
-- attribute keep of ENDPTCOMPLETE_rd : signal is "true";
-- attribute mark_debug of ENDPTSETUPSTAT_rd : signal is "true";
-- attribute keep of ENDPTSETUPSTAT_rd : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Reg : signal is "true";
-- attribute keep of a_ENDPTSTAT_Reg : signal is "true";
begin
USBSCFG_rd <= a_USBSCFG_Reg;
USBCMD_rd <= a_USBCMD_Reg;
USBSTS_rd <= a_USBSTS_Reg;
USBINTR_rd <= a_USBINTR_Reg;
FRINDEX_rd <= a_FRINDEX_Reg;
a_DEVICEADDR_rd <= a_DEVICEADDR_Reg;
ENDPOINTLISTADDR_rd <= a_ENDPOINTLISTADDR_Reg;
ENDPTNAK_rd <= a_ENDPTNAK_Reg;
ENDPTNAKEN_rd <= a_ENDPTNAKEN_Reg;
CONFIGFLAG_rd <= a_CONFIGFLAG_Reg;
PORTSC1_rd <= a_PORTSC1_Reg;
OTGSC_rd <= a_OTGSC_Reg;
USBMODE_rd <= a_USBMODE_Reg;
ENDPTSETUPSTAT_rd <= a_ENDPTSETUPSTAT_Reg;
ENDPTPRIME_rd <= a_ENDPTPRIME_Reg;
EMDPTFLUSH_rd <= a_EMDPTFLUSH_Reg;
a_ENDPTSTAT_Reg <= ENDPTSTAT_wr;
ENDPTCOMPLETE_rd <= a_ENDPTCOMPLETE_Reg;
ENDPTCTRL0_rd <= a_ENDPTCTRL0_Reg;
ENDPTCTRL1_rd <= a_ENDPTCTRL1_Reg;
ENDPTCTRL2_rd <= a_ENDPTCTRL2_Reg;
ENDPTCTRL3_rd <= a_ENDPTCTRL3_Reg;
ENDPTCTRL4_rd <= a_ENDPTCTRL4_Reg;
ENDPTCTRL5_rd <= a_ENDPTCTRL5_Reg;
ENDPTCTRL6_rd <= a_ENDPTCTRL6_Reg;
ENDPTCTRL7_rd <= a_ENDPTCTRL7_Reg;
ENDPTCTRL8_rd <= a_ENDPTCTRL8_Reg;
ENDPTCTRL9_rd <= a_ENDPTCTRL9_Reg;
ENDPTCTRL10_rd <= a_ENDPTCTRL10_Reg;
ENDPTCTRL11_rd <= a_ENDPTCTRL11_Reg;
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
a_USBSCFG_Reg <= (others => '0');
a_USBCMD_Reg <= (others => '0');
a_USBINTR_Reg <= (others => '0');
a_FRINDEX_Reg <= (others => '0');
a_DEVICEADDR_Reg <= (others => '0');
a_DEVICEADDR_IPush <= '0';
a_ENDPOINTLISTADDR_Reg <= (others => '0');
a_ENDPTNAK_Reg <= (others => '0');
a_ENDPTNAKEN_Reg <= (others => '0');
a_CONFIGFLAG_Reg <= (others => '0');
a_PORTSC1_Reg <= (others => '0');
a_OTGSC_Reg <= (others => '0');
a_USBMODE_Reg <= (others => '0');
a_ENDPTPRIME_Reg <= (others => '0');
a_ENDPTCOMPLETE_Reg <= (others => '0');
a_ENDPTCTRL0_Reg <= (others => '0');
a_ENDPTCTRL1_Reg <= (others => '0');
a_ENDPTCTRL2_Reg <= (others => '0');
a_ENDPTCTRL3_Reg <= (others => '0');
a_ENDPTCTRL4_Reg <= (others => '0');
a_ENDPTCTRL5_Reg <= (others => '0');
a_ENDPTCTRL6_Reg <= (others => '0');
a_ENDPTCTRL7_Reg <= (others => '0');
a_ENDPTCTRL8_Reg <= (others => '0');
a_ENDPTCTRL9_Reg <= (others => '0');
a_ENDPTCTRL10_Reg <= (others => '0');
a_ENDPTCTRL11_Reg <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0100100" => --SBUSCFG 0x0090
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_USBSCFG_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010000" => --USBCMD 0x0140
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_USBCMD_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010010" => --USBINTR 0x0148
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_USBINTR_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010011" => --FRINDEX 0x014C
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_FRINDEX_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010101" => --DEVICEADDR 0x0154
a_DEVICEADDR_IPush <= '1';
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_DEVICEADDR_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010110" => --ENDPOINTLISTADDR 0x158
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPOINTLISTADDR_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011110" => --ENDPTNAK 0x0178
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTNAK_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011111" => -- ENDPTNAKEN 0x17c
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTNAKEN_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL7_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL8_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1100001" => --PORTSC1 0x0184
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_PORTSC1_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101001" => --OTGSC 0x01A4
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_OTGSC_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101010" => --USBMODE 0x1A8
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_USBMODE_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101100" => --ENDPTPRIME 0x01B0
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTPRIME_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101111" => --ENDPTCOMPLETE 0x01BC
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCOMPLETE_Reg(byte_index*8+7 downto byte_index*8) <= a_ENDPTCOMPLETE_Reg(byte_index*8+7 downto byte_index*8) and ( not (S_AXI_WDATA(byte_index*8+7 downto byte_index*8)));
end if;
end loop;
when b"1110000" => --ENDPTCTRL0 0x01C0
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL0_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110001" => --ENDPTCTRL1 0x01C4
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL1_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110010" => --ENDPTCTRL2 0x01C8
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL2_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110011" => --ENDPTCTRL3 0x01CC
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL3_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110100" => --ENDPTCTRL4 0x01D0
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL4_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110101" => --ENDPTCTRL5 0x01D4
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL5_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110110" => --ENDPTCTRL6 0x01D8
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL6_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110111" => --ENDPTCTRL7 0x01DC
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL7_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111000" => --ENDPTCTRL8 0x01E0
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL8_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111001" => --ENDPTCTRL9 0x01E4
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL9_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111010" => --ENDPTCTRL10 0x01E8
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL10_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111011" => --D 0x01EC
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTCTRL11_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
a_USBSCFG_Reg <= a_USBSCFG_Reg;
a_USBCMD_Reg <= a_USBCMD_Reg;
a_USBINTR_Reg <= a_USBINTR_Reg;
a_FRINDEX_Reg <= a_FRINDEX_Reg;
a_DEVICEADDR_Reg <= a_DEVICEADDR_Reg;
a_DEVICEADDR_IPush <= '0';
a_ENDPOINTLISTADDR_Reg <= a_ENDPOINTLISTADDR_Reg;
a_ENDPTNAK_Reg <= a_ENDPTNAK_Reg;
a_ENDPTNAKEN_Reg <= a_ENDPTNAKEN_Reg;
a_CONFIGFLAG_Reg <= a_CONFIGFLAG_Reg;
a_PORTSC1_Reg <= a_PORTSC1_Reg;
a_OTGSC_Reg <= a_OTGSC_Reg;
a_USBMODE_Reg <= a_USBMODE_Reg;
a_ENDPTPRIME_Reg <= a_ENDPTPRIME_Reg;
a_ENDPTCOMPLETE_Reg <= a_ENDPTCOMPLETE_Reg;
a_ENDPTCTRL0_Reg <= a_ENDPTCTRL0_Reg;
a_ENDPTCTRL1_Reg <= a_ENDPTCTRL1_Reg;
a_ENDPTCTRL2_Reg <= a_ENDPTCTRL2_Reg;
a_ENDPTCTRL3_Reg <= a_ENDPTCTRL3_Reg;
a_ENDPTCTRL4_Reg <= a_ENDPTCTRL4_Reg;
a_ENDPTCTRL5_Reg <= a_ENDPTCTRL5_Reg;
a_ENDPTCTRL6_Reg <= a_ENDPTCTRL6_Reg;
a_ENDPTCTRL7_Reg <= a_ENDPTCTRL7_Reg;
a_ENDPTCTRL8_Reg <= a_ENDPTCTRL8_Reg;
a_ENDPTCTRL9_Reg <= a_ENDPTCTRL9_Reg;
a_ENDPTCTRL10_Reg <= a_ENDPTCTRL10_Reg;
a_ENDPTCTRL11_Reg <= a_ENDPTCTRL11_Reg;
end case;
elsif (USBCMD_SUTW_wr_en = '1') then
a_USBCMD_Reg(13) <= USBCMD_SUTW_wr;
elsif (USBCMD_ATDTW_wr_en = '1') then
a_USBCMD_Reg(14) <= USBCMD_ATDTW_wr;
elsif (a_USBCMD_Reg(1) = '1') then
a_USBCMD_Reg(1) <= '0';
elsif (FRINDEX_wr_en = '1') then
a_FRINDEX_Reg(10 downto 0) <= FRINDEX_wr;
elsif (ENDPTNAK_wr_en = '1') then
a_ENDPTNAK_Reg <= ENDPTNAK_wr;
elsif (PORTSC1_PSPD_wr_en = '1') then
a_PORTSC1_Reg(27 downto 26) <= PORTSC1_PSPD_wr;
elsif (ENDPTPRIME_clear_en = '1') then
a_ENDPTPRIME_Reg <= a_ENDPTPRIME_Reg and ENDPTPRIME_clear;
elsif (ENDPTPRIME_set_en = '1') then
a_ENDPTPRIME_Reg <= a_ENDPTPRIME_Reg or ENDPTPRIME_set;
elsif (ENDPTCOMPLETE_wr_en = '1') then
a_ENDPTCOMPLETE_Reg <= a_ENDPTCOMPLETE_Reg or ENDPTCOMPLETE_wr;
end if;
end if;
end if;
end process;
ENDPTSETUPSTAT_PROC : process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
a_ENDPTSETUPSTAT_Reg <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1' and loc_addr = "1101011") then
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_ENDPTSETUPSTAT_Reg(byte_index*8+7 downto byte_index*8) <= a_ENDPTSETUPSTAT_Reg(byte_index*8+7 downto byte_index*8) and ( not (S_AXI_WDATA(byte_index*8+7 downto byte_index*8)));
end if;
end loop;
elsif (ENDPTSETUPSTAT_wr_en = '1') then
a_ENDPTSETUPSTAT_Reg <= a_ENDPTSETUPSTAT_Reg or ENDPTSETUPSTAT_wr;
end if;
end if;
end if;
end process;
ENDPTFLUSH_PROC : process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
a_EMDPTFLUSH_Reg <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1' and loc_addr = "1101101") then --EMDPTFLUSH 0x01B4
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_EMDPTFLUSH_Reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
elsif (EMDPTFLUSH_clear_en = '1') then
a_EMDPTFLUSH_Reg <= a_EMDPTFLUSH_Reg and EMDPTFLUSH_clear;
elsif (EMDPTFLUSH_set_en = '1') then
a_EMDPTFLUSH_Reg <= a_EMDPTFLUSH_Reg or EMDPTFLUSH_set;
end if;
end if;
end if;
end process;
USBSTS_PROC : process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
a_USBSTS_Reg <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1' and loc_addr = "1010001") then
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
a_USBSTS_Reg(byte_index*8+7 downto byte_index*8) <= (a_USBSTS_Reg(byte_index*8+7 downto byte_index*8)) and (not (S_AXI_WDATA(byte_index*8+7 downto byte_index*8)));
end if;
end loop;
elsif (USBSTS_wr_en_UI = '1' or USBSTS_wr_en_NAK = '1' or USBSTS_wr_en_SLI = '1' or USBSTS_wr_en_SRI = '1' or USBSTS_wr_en_URI = '1' or USBSTS_wr_en_PCI = '1') then
a_USBSTS_Reg(0) <= a_USBSTS_Reg(0) or USBSTS_wr_en_UI;
a_USBSTS_Reg(16) <= a_USBSTS_Reg(16) or USBSTS_wr_en_NAK;
a_USBSTS_Reg(8) <= a_USBSTS_Reg(8) or USBSTS_wr_en_SLI;
a_USBSTS_Reg(7) <= a_USBSTS_Reg(7) or USBSTS_wr_en_SRI;
a_USBSTS_Reg(6) <= a_USBSTS_Reg(6) or USBSTS_wr_en_URI;
a_USBSTS_Reg(2) <= a_USBSTS_Reg(2) or USBSTS_wr_en_PCI;
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
axi_arready <= '1';
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (a_USBSCFG_Reg, a_USBCMD_Reg, a_USBSTS_Reg, a_USBINTR_Reg, a_FRINDEX_Reg, a_DEVICEADDR_Reg, a_ENDPOINTLISTADDR_Reg, a_ENDPTNAK_Reg, a_ENDPTNAKEN_Reg, a_CONFIGFLAG_Reg, a_PORTSC1_Reg, a_OTGSC_Reg, a_USBMODE_Reg, a_ENDPTSETUPSTAT_Reg, a_ENDPTPRIME_Reg, a_EMDPTFLUSH_Reg, a_ENDPTSTAT_Reg, a_ENDPTCOMPLETE_Reg, a_ENDPTCTRL0_Reg, a_ENDPTCTRL1_Reg, a_ENDPTCTRL2_Reg, a_ENDPTCTRL3_Reg, a_ENDPTCTRL4_Reg, a_ENDPTCTRL5_Reg, a_ENDPTCTRL6_Reg, a_ENDPTCTRL7_Reg, a_ENDPTCTRL8_Reg, a_ENDPTCTRL9_Reg, a_ENDPTCTRL10_Reg, a_ENDPTCTRL11_Reg, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000000" =>
reg_data_out <= ID;
when b"0000001" =>
reg_data_out <= HWGENERAL;
when b"0000011" =>
reg_data_out <= HWDEVICE;
when b"000100" =>
reg_data_out <= HWTXBUF;
when b"000101" =>
reg_data_out <= HWRXBUF;
when b"0100100" => --SBUSCFG
reg_data_out <= a_USBSCFG_Reg;
when b"1000000" => --CAPLENGTH_HCIVERSION
reg_data_out <= CAPLENGTH_HCIVERSION;
when b"1001000" => --DCIVERSION
reg_data_out <= DCIVERSION;
when b"1001001" => --DCCPARAMS
reg_data_out <= DCCPARAMS;
when b"1010000" => --USBCMD
reg_data_out <= a_USBCMD_Reg;
when b"1010001" => --USBSTS
reg_data_out <= a_USBSTS_Reg;
when b"1010010" => --USBINTR
reg_data_out <= a_USBINTR_Reg;
when b"1010011" => --FRINDEX
reg_data_out <= a_FRINDEX_Reg;
when b"1010101" => --DEVICEADDR
reg_data_out <= a_DEVICEADDR_Reg;
when b"1010110" => --ENDPOINTLISTADDR
reg_data_out <= a_ENDPOINTLISTADDR_Reg;
when b"1011110" => --ENDPTNAK
reg_data_out <= a_ENDPTNAK_Reg;
when b"1011111" => --ENDPTNAKEN
reg_data_out <= a_ENDPTNAKEN_Reg;
when b"1100000" => --CONFIGFLAG
reg_data_out <= a_CONFIGFLAG_Reg;
when b"1100001" => --PORTSC1
reg_data_out <= a_PORTSC1_Reg;
when b"1101001" => --OTGSC
reg_data_out <= a_OTGSC_Reg;
when b"1101010" => --USBMODE
reg_data_out <= a_USBMODE_Reg;
when b"1101011" => --ENDPTSETUPSTAT
reg_data_out <= a_ENDPTSETUPSTAT_Reg;
when b"1101100" => --ENDPTPRIME
reg_data_out <= a_ENDPTPRIME_Reg;
when b"1101101" => --EMDPTFLUSH
reg_data_out <= a_EMDPTFLUSH_Reg;
when b"1101110" => --ENDPTSTAT
reg_data_out <= a_ENDPTSTAT_Reg;
when b"1101111" => --ENDPTCOMPLETE
reg_data_out <= a_ENDPTCOMPLETE_Reg;
when b"1110000" => --ENDPTCTRL0
reg_data_out <= a_ENDPTCTRL0_Reg;
when b"1110001" => --ENDPTCTRL1
reg_data_out <= a_ENDPTCTRL1_Reg;
when b"1110010" => --ENDPTCTRL2
reg_data_out <= a_ENDPTCTRL1_Reg;
when b"1110011" => --ENDPTCTRL3
reg_data_out <= a_ENDPTCTRL3_Reg;
when b"1110100" => --ENDPTCTRL4
reg_data_out <= a_ENDPTCTRL4_Reg;
when b"1110101" => --ENDPTCTRL5
reg_data_out <= a_ENDPTCTRL5_Reg;
when b"1110110" => --ENDPTCTRL6
reg_data_out <= a_ENDPTCTRL6_Reg;
when b"1110111" => --ENDPTCTRL7
reg_data_out <= a_ENDPTCTRL7_Reg;
when b"1111000" => --ENDPTCTRL8
reg_data_out <= a_ENDPTCTRL8_Reg;
when b"1111001" => --ENDPTCTRL9
reg_data_out <= a_ENDPTCTRL9_Reg;
when b"1111010" => --ENDPTCTRL10
reg_data_out <= a_ENDPTCTRL10_Reg;
when b"1111011" => --ENDPTCTRL11
reg_data_out <= a_ENDPTCTRL11_Reg;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
end arch_imp;
|
mit
|
af70e2da1f971f136f9367cfc17821cb
| 0.562329 | 3.309384 | false | false | false | false |
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