repo_name
stringlengths
6
79
path
stringlengths
6
236
copies
int64
1
472
size
int64
137
1.04M
content
stringlengths
137
1.04M
license
stringclasses
15 values
hash
stringlengths
32
32
alpha_frac
float64
0.25
0.96
ratio
float64
1.51
17.5
autogenerated
bool
1 class
config_or_test
bool
2 classes
has_no_keywords
bool
1 class
has_few_assignments
bool
1 class
Darkin47/Zynq-TX-UTT
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sg_if.vhd
3
81,371
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sg_if.vhd -- Description: This entity is the S2MM Scatter Gather Interface for Descriptor -- Fetches and Updates. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_9; use axi_dma_v7_1_9.axi_dma_pkg.all; library lib_cdc_v1_0_2; library lib_srl_fifo_v1_0_2; use lib_srl_fifo_v1_0_2.srl_fifo_f; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sg_if is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Any one of the 4 clock inputs is not -- synchronous to the other ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ; -- AXI Master Stream in for descriptor fetch C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ; -- 1 IOC bit + 32 Update Status Bits C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ; -- Master AXI Memory Map Address Width for S2MM Write Port C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ; -- Slave AXI Status Stream Data Width C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ; C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- s2mm_desc_info_in : in std_logic_vector (13 downto 0) ; -- -- SG S2MM Descriptor Fetch AXI Stream In -- m_axis_s2mm_ftch_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_s2mm_ftch_tvalid : in std_logic ; -- m_axis_s2mm_ftch_tready : out std_logic ; -- m_axis_s2mm_ftch_tlast : in std_logic ; -- m_axis_s2mm_ftch_tdata_new : in std_logic_vector -- (96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); -- m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector -- (63 downto 0); -- m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- m_axis_s2mm_ftch_tvalid_new : in std_logic ; -- m_axis_ftch2_desc_available : in std_logic; -- -- -- SG S2MM Descriptor Update AXI Stream Out -- s_axis_s2mm_updtptr_tdata : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- s_axis_s2mm_updtptr_tvalid : out std_logic ; -- s_axis_s2mm_updtptr_tready : in std_logic ; -- s_axis_s2mm_updtptr_tlast : out std_logic ; -- -- s_axis_s2mm_updtsts_tdata : out std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_updtsts_tvalid : out std_logic ; -- s_axis_s2mm_updtsts_tready : in std_logic ; -- s_axis_s2mm_updtsts_tlast : out std_logic ; -- -- -- S2MM Descriptor Fetch Request (from s2mm_sm) -- desc_available : out std_logic ; -- desc_fetch_req : in std_logic ; -- updt_pending : out std_logic ; desc_fetch_done : out std_logic ; -- -- -- S2MM Descriptor Update Request (from s2mm_sm) -- desc_update_done : out std_logic ; -- s2mm_sts_received_clr : out std_logic ; -- s2mm_sts_received : in std_logic ; -- -- -- Scatter Gather Update Status -- s2mm_done : in std_logic ; -- s2mm_interr : in std_logic ; -- s2mm_slverr : in std_logic ; -- s2mm_decerr : in std_logic ; -- s2mm_tag : in std_logic_vector(3 downto 0) ; -- s2mm_brcvd : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- s2mm_eof_set : in std_logic ; -- s2mm_packet_eof : in std_logic ; -- s2mm_halt : in std_logic ; -- -- -- S2MM Status Stream Interface -- stsstrm_fifo_rden : out std_logic ; -- stsstrm_fifo_empty : in std_logic ; -- stsstrm_fifo_dout : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); -- -- -- DataMover Command -- s2mm_cmnd_wr : in std_logic ; -- s2mm_cmnd_data : in std_logic_vector -- (((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- S2MM Descriptor Field Output -- s2mm_new_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- s2mm_new_curdesc_wren : out std_logic ; -- -- s2mm_desc_info : out std_logic_vector -- (31 downto 0); -- s2mm_desc_baddress : out std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_desc_blength : out std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- s2mm_desc_blength_v : out std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- s2mm_desc_blength_s : out std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- s2mm_desc_cmplt : out std_logic ; -- s2mm_eof_micro : out std_logic ; s2mm_sof_micro : out std_logic ; s2mm_desc_app0 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- s2mm_desc_app1 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- s2mm_desc_app2 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- s2mm_desc_app3 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- s2mm_desc_app4 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) -- ); end axi_dma_s2mm_sg_if; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sg_if is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ATTRIBUTE async_reg : STRING; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Status reserved bits constant RESERVED_STS : std_logic_vector(2 downto 0) := (others => '0'); -- Zero value constant constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0'); -- Zero length constant constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal ftch_shftenbl : std_logic := '0'; -- fetch descriptor holding registers signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_pending_update : std_logic := '0'; signal s2mm_new_curdesc_wren_i : std_logic := '0'; signal s2mm_ioc : std_logic := '0'; signal s2mm_pending_pntr_updt : std_logic := '0'; -- Descriptor Update Signals signal s2mm_complete : std_logic := '0'; signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0'); -- Signals for pointer support -- Make 1 bit wider to allow tagging of LAST for use in generating tlast signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0'); signal updt_shftenbl : std_logic := '0'; signal updtptr_tvalid : std_logic := '0'; signal updtptr_tlast : std_logic := '0'; signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); -- Signals for Status Stream Support signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal writing_app_fields : std_logic := '0'; signal stsstrm_fifo_rden_i : std_logic := '0'; signal sts_shftenbl : std_logic := '0'; signal sts_received : std_logic := '0'; signal sts_received_d1 : std_logic := '0'; signal sts_received_re : std_logic := '0'; -- Queued Update signals signal updt_data_clr : std_logic := '0'; signal updt_sts_clr : std_logic := '0'; signal updt_data : std_logic := '0'; signal updt_sts : std_logic := '0'; signal ioc_tag : std_logic := '0'; signal s2mm_sof_set : std_logic := '0'; signal s2mm_in_progress : std_logic := '0'; signal eof_received : std_logic := '0'; signal sof_received : std_logic := '0'; signal updtsts_tvalid : std_logic := '0'; signal updtsts_tlast : std_logic := '0'; signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_halt_d1_cdc_tig : std_logic := '0'; signal s2mm_halt_cdc_d2 : std_logic := '0'; signal s2mm_halt_d2 : std_logic := '0'; --ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true"; signal desc_fetch_done_i : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Drive buffer length out s2mm_desc_blength <= s2mm_desc_blength_i; s2mm_desc_blength_v <= s2mm_desc_blength_v_i; s2mm_desc_blength_s <= s2mm_desc_blength_s_i; updt_pending <= s2mm_pending_update; -- Drive ready if descriptor fetch request is being made m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch and not s2mm_pending_update; -- No pending pointer updates desc_fetch_done <= desc_fetch_done_i; -- Shift in data from SG engine if tvalid and fetch request ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new and desc_fetch_req and not s2mm_pending_update; -- Passed curdes write out to register module s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i; -- tvalid asserted means descriptor availble desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new; --***************************************************************************-- --** Register DataMover Halt to secondary if needed --***************************************************************************-- GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate begin -- Double register to secondary clock domain. This is sufficient -- because halt will remain asserted until halt_cmplt detected in -- reset module in secondary clock domain. REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_halt, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => s2mm_halt_cdc_d2, scndry_vect_out => open ); -- REG_TO_SECONDARY : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- -- if(m_axi_sg_aresetn = '0')then -- -- s2mm_halt_d1_cdc_tig <= '0'; -- -- s2mm_halt_d2 <= '0'; -- -- else -- s2mm_halt_d1_cdc_tig <= s2mm_halt; -- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig; -- -- end if; -- end if; -- end process REG_TO_SECONDARY; s2mm_halt_d2 <= s2mm_halt_cdc_d2; end generate GEN_FOR_ASYNC; GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate begin -- No clock crossing required therefore simple pass through s2mm_halt_d2 <= s2mm_halt; end generate GEN_FOR_SYNC; --***************************************************************************-- --** Descriptor Fetch Logic **-- --***************************************************************************-- s2mm_desc_curdesc_lsb <= desc_reg0; --s2mm_desc_curdesc_lsb_nxt <= desc_reg2; --s2mm_desc_curdesc_msb_nxt <= desc_reg3; s2mm_desc_baddr_lsb <= desc_reg4; GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0); desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32); desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); desc_reg9(30 downto 0) <= (others => '0'); s2mm_desc_curdesc_lsb_nxt <= desc_reg0; -- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1; s2mm_desc_info <= (others => '0'); -- desc 4 and desc 5 are reserved and thus don't care s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT); s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT); s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT); s2mm_desc_blength_v_i <= (others => '0'); s2mm_desc_blength_s_i <= (others => '0') ; ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate begin s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97); s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129); end generate ADDR_64BIT; ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin s2mm_desc_curdesc_msb <= (others => '0'); s2mm_desc_baddr_msb <= (others => '0'); end generate ADDR_32BIT; ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate begin s2mm_desc_curdesc_lsb_nxt <= desc_reg0; s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129); end generate ADDR_64BIT_DMA; ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin s2mm_desc_curdesc_lsb_nxt <= desc_reg0; s2mm_desc_curdesc_msb_nxt <= (others => '0'); end generate ADDR_32BIT_DMA; end generate GEN_NO_MCDMA; GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl; desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96); desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0); desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32); desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64); desc_reg9(30 downto 0) <= (others => '0'); desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0); desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0); desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32); s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0); -- desc 4 and desc 5 are reserved and thus don't care s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0); s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19); s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0); ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate begin s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97); s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129); end generate ADDR_64BIT_1; ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin s2mm_desc_curdesc_msb <= (others => '0'); s2mm_desc_baddr_msb <= (others => '0'); end generate ADDR_32BIT_1; ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate begin s2mm_desc_curdesc_lsb_nxt <= desc_reg2; s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32); end generate ADDR_64BIT_MCDMA; ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin s2mm_desc_curdesc_lsb_nxt <= desc_reg2; s2mm_desc_curdesc_msb_nxt <= (others => '0'); end generate ADDR_32BIT_MCDMA; end generate GEN_MCDMA; s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT); s2mm_desc_app0 <= (others => '0'); s2mm_desc_app1 <= (others => '0'); s2mm_desc_app2 <= (others => '0'); s2mm_desc_app3 <= (others => '0'); s2mm_desc_app4 <= (others => '0'); ------------------------------------------------------------------------------- -- BUFFER ADDRESS ------------------------------------------------------------------------------- -- If 64 bit addressing then concatinate msb to lsb GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb; -- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97); end generate GEN_NEW_64BIT_BUFADDR; -- If 32 bit addressing then simply pass lsb out GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate s2mm_desc_baddress <= s2mm_desc_baddr_lsb; end generate GEN_NEW_32BIT_BUFADDR; ------------------------------------------------------------------------------- -- NEW CURRENT DESCRIPTOR ------------------------------------------------------------------------------- -- If 64 bit addressing then concatinate msb to lsb GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt; end generate GEN_NEW_64BIT_CURDESC; -- If 32 bit addressing then simply pass lsb out GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt; end generate GEN_NEW_32BIT_CURDESC; s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl; --***************************************************************************-- --** Descriptor Update Logic **-- --***************************************************************************-- -- SOF Flagging logic for when descriptor queues are enabled in SG Engine GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate -- SOF Queued one count value constant ONE_COUNT : std_logic_vector(2 downto 0) := "001"; signal incr_sof_count : std_logic := '0'; signal decr_sof_count : std_logic := '0'; signal sof_count : std_logic_vector(2 downto 0) := (others => '0'); signal sof_received_set : std_logic := '0'; signal sof_received_clr : std_logic := '0'; signal cmd_wr_mask : std_logic := '0'; begin -- Keep track of number of commands queued up in data mover to -- allow proper setting of SOF's and EOF's when associated -- descriptor is updated. REG_SOF_COUNT : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sof_count <= (others => '0'); elsif(incr_sof_count = '1')then sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1); elsif(decr_sof_count = '1')then sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1); end if; end if; end process REG_SOF_COUNT; -- Increment count on each command write that does NOT occur -- coincident with a status received incr_sof_count <= s2mm_cmnd_wr and not sts_received_re; -- Decrement count on each status received that does NOT -- occur coincident with a command write decr_sof_count <= sts_received_re and not s2mm_cmnd_wr; -- Drive sof and eof setting to interrupt module for delay interrupt --s2mm_packet_sof <= s2mm_sof_set; REG_SOF_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sof_received <= '0'; elsif(sof_received_set = '1')then sof_received <= '1'; elsif(sof_received_clr = '1')then sof_received <= '0'; end if; end if; end process REG_SOF_STATUS; -- SOF Received -- Case 1 (i.e. already running): EOF received therefore next has to be SOF -- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover and eof_received = '1') -- End of packet received -- OR... or (s2mm_cmnd_wr = '1' -- Command written to datamover and cmd_wr_mask = '0' -- Not inner-packet command and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds else '0'; -- Done with SOF's -- Status received and EOF received flag not set -- Or status received and EOF received flag set and last SOF sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0') or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT) else '0'; -- Mask command writes if inner-packet command written. An inner packet -- command is one where status if received and eof_received is not asserted. -- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning -- no commands happen to be queued in datamover. WR_MASK : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then cmd_wr_mask <= '0'; -- received data mover status, mask if EOF not set -- clear mask if EOF set. elsif(sts_received_re = '1')then cmd_wr_mask <= not eof_received; end if; end if; end process WR_MASK; end generate GEN_SOF_QUEUE_MODE; -- SOF Flagging logic for when descriptor queues are disabled in SG Engine GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin ----------------------------------------------------------------------- -- Assert window around receive packet in order to properly set -- SOF and EOF bits in descriptor -- -- SOF for S2MM determined by new command write to datamover, i.e. -- command write receive packet not already in progress. ----------------------------------------------------------------------- RX_IN_PROG_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then s2mm_in_progress <= '0'; s2mm_sof_set <= '0'; elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then s2mm_in_progress <= '1'; s2mm_sof_set <= '1'; else s2mm_in_progress <= s2mm_in_progress; s2mm_sof_set <= '0'; end if; end if; end process RX_IN_PROG_PROCESS; -- Drive sof and eof setting to interrupt module for delay interrupt --s2mm_packet_sof <= s2mm_sof_set; REG_SOF_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then sof_received <= '0'; elsif(s2mm_sof_set = '1')then sof_received <= '1'; end if; end if; end process REG_SOF_STATUS; end generate GEN_SOF_NO_QUEUE_MODE; -- IOC and EOF bits in desc update both set via packet eof flag from -- command/status interface. eof_received <= s2mm_packet_eof; s2mm_ioc <= s2mm_packet_eof; --***************************************************************************-- --** Descriptor Update Logic **-- --***************************************************************************-- --***************************************************************************** --** Pointer Update Logic --***************************************************************************** ----------------------------------------------------------------------- -- Capture LSB cur descriptor on write for use on descriptor update. -- This will be the address the descriptor is updated to ----------------------------------------------------------------------- UPDT_DESC_WRD0: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_reg0 (31 downto 0) <= (others => '0'); elsif(s2mm_new_curdesc_wren_i = '1')then updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb; end if; end if; end process UPDT_DESC_WRD0; --------------------------------------------------------------------------- -- Capture MSB cur descriptor on write for use on descriptor update. -- This will be the address the descriptor is updated to --------------------------------------------------------------------------- PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin UPDT_DESC_WRD1: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0'); elsif(s2mm_new_curdesc_wren_i = '1')then updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb; end if; end if; end process UPDT_DESC_WRD1; end generate PTR_64BIT_CURDESC; -- Shift in pointer to SG engine if tvalid, tready, and not on last word updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready; -- Update data done when updating data and tlast received and target -- (i.e. SG Engine) is ready updt_data_clr <= '1' when updtptr_tvalid = '1' and updtptr_tlast = '1' and s_axis_s2mm_updtptr_tready = '1' else '0'; --------------------------------------------------------------------------- -- When desc data ready for update set and hold flag until -- data can be updated to queue. Note it may -- be held off due to update of status --------------------------------------------------------------------------- UPDT_DATA_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then updt_data <= '0'; -- clear flag when data update complete -- elsif(updt_data_clr = '1')then -- updt_data <= '0'; -- -- set flag when desc fetched as indicated -- -- by curdesc wren elsif(s2mm_new_curdesc_wren_i = '1')then updt_data <= '1'; end if; end if; end process UPDT_DATA_PROCESS; updtptr_tvalid <= updt_data; updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH); updtptr_tdata <= updt_desc_reg0; -- Pass out to sg engine s_axis_s2mm_updtptr_tdata <= updtptr_tdata; s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid; s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid; --***************************************************************************** --** Status Update Logic - DESCRIPTOR QUEUES INCLUDED ** --***************************************************************************** GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate signal xb_fifo_reset : std_logic := '0'; signal xb_fifo_full : std_logic := '0'; begin s2mm_complete <= '1'; -- Fixed at '1' ----------------------------------------------------------------------- -- Need to flag a pending point update to prevent subsequent fetch of -- descriptor from stepping on the stored pointer, and buffer length ----------------------------------------------------------------------- REG_PENDING_UPDT : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then s2mm_pending_pntr_updt <= '0'; elsif(s2mm_new_curdesc_wren_i = '1')then s2mm_pending_pntr_updt <= '1'; end if; end if; end process REG_PENDING_UPDT; -- Pending update on pointer not updated yet or xfer'ed bytes fifo full s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full; -- Clear status received flag in cmdsts_if to -- allow more status to be received from datamover s2mm_sts_received_clr <= updt_sts_clr; -- Generate a rising edge off status received in order to -- flag status update REG_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sts_received_d1 <= '0'; else sts_received_d1 <= s2mm_sts_received; end if; end if; end process REG_STATUS; -- CR 566306 Status invalid during halt -- sts_received_re <= s2mm_sts_received and not sts_received_d1; sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2; --------------------------------------------------------------------------- -- When status received set and hold flag until -- status can be updated to queue. Note it may -- be held off due to update of data --------------------------------------------------------------------------- UPDT_STS_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then updt_sts <= '0'; -- clear flag when status update done or -- datamover halted -- elsif(updt_sts_clr = '1')then -- updt_sts <= '0'; -- set flag when status received elsif(sts_received_re = '1')then updt_sts <= '1'; end if; end if; end process UPDT_STS_PROCESS; updt_sts_clr <= '1' when updt_sts = '1' and updtsts_tvalid = '1' and updtsts_tlast = '1' and s_axis_s2mm_updtsts_tready = '1' else '0'; -- for queue case used to keep track of number of datamover queued cmnds UPDT_DONE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_update_done <= '0'; else desc_update_done <= updt_sts_clr; end if; end if; end process UPDT_DONE_PROCESS; --***********************************************************************-- --** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **-- --***********************************************************************-- --------------------------------------------------------------------------- -- Generate Descriptor Update Signaling for NO Status App Stream --------------------------------------------------------------------------- GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate begin stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode -- Transferred byte length from status is equal to bytes transferred field -- in descriptor status GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate begin s2mm_xferd_bytes <= s2mm_brcvd; end generate GEN_EQ_23BIT_BYTE_XFERED; -- Transferred byte length from status is less than bytes transferred field -- in descriptor status therefore need to pad value. GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd; end generate GEN_LESSTHN_23BIT_BYTE_XFERED; ----------------------------------------------------------------------- -- Catpure Status. Status is built from status word from DataMover -- and from transferred bytes value. ----------------------------------------------------------------------- UPDT_DESC_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_sts <= (others => '0'); elsif(sts_received_re = '1')then updt_desc_sts <= DESC_LAST & s2mm_ioc & s2mm_complete & s2mm_decerr & s2mm_slverr & s2mm_interr & sof_received -- If asserted also set SOF & eof_received -- If asserted also set EOF & RESERVED_STS & s2mm_xferd_bytes; end if; end if; end process UPDT_DESC_STATUS; -- Drive TVALID updtsts_tvalid <= updt_sts; -- Drive TLast updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH); -- Drive TData GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) & s2mm_desc_info_in (13 downto 10) & "000" & s2mm_desc_info_in (9 downto 5) & "000" & s2mm_desc_info_in (4 downto 0); end generate GEN_DESC_UPDT_MCDMA; GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); end generate GEN_DESC_UPDT_DMA; end generate GEN_DESC_UPDT_NO_STSAPP; --***********************************************************************-- --** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **-- --***********************************************************************-- --------------------------------------------------------------------------- -- Generate Descriptor Update Signaling for Status App Stream --------------------------------------------------------------------------- GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate begin -- Get rx length is identical to command written, therefor store -- the BTT value from the command written to be used as the xferd bytes. GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin ----------------------------------------------------------------------- -- On S2MM transferred bytes equals buffer length. Capture length -- on curdesc write. ----------------------------------------------------------------------- XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f generic map( C_DWIDTH => BUFFER_LENGTH_WIDTH , C_DEPTH => 16 , C_FAMILY => C_FAMILY ) port map( Clk => m_axi_sg_aclk , Reset => xb_fifo_reset , FIFO_Write => s2mm_cmnd_wr , Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) , FIFO_Read => sts_received_re , Data_Out => s2mm_xferd_bytes , FIFO_Empty => open , FIFO_Full => xb_fifo_full , Addr => open ); xb_fifo_reset <= not m_axi_sg_aresetn; end generate GEN_USING_STSAPP_LENGTH; -- Not using status app length field therefore primary S2MM DataMover is -- configured as a store and forward channel (i.e. indeterminate BTT mode) -- Receive length will be reported in datamover status. GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode -- Transferred byte length from status is equal to bytes transferred field -- in descriptor status GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate begin s2mm_xferd_bytes <= s2mm_brcvd; end generate GEN_EQ_23BIT_BYTE_XFERED; -- Transferred byte length from status is less than bytes transferred field -- in descriptor status therefore need to pad value. GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd; end generate GEN_LESSTHN_23BIT_BYTE_XFERED; end generate GEN_NOT_USING_STSAPP_LENGTH; ----------------------------------------------------------------------- -- For EOF Descriptor then need to update APP fields from Status -- Stream FIFO ----------------------------------------------------------------------- WRITE_APP_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then writing_app_fields <= '0'; -- If writing app fields and reach LAST then stop writing -- app fields elsif(writing_app_fields = '1' -- Writing app fields and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1) and stsstrm_fifo_rden_i = '1')then -- Fifo read writing_app_fields <= '0'; -- ON EOF Descriptor, then need to write application fields on desc -- update elsif(s2mm_packet_eof = '1' and s2mm_xferd_bytes /= ZERO_LENGTH) then writing_app_fields <= '1'; end if; end if; end process WRITE_APP_PROCESS; -- Shift in apps to SG engine if tvalid, tready, and not on last word sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready; ----------------------------------------------------------------------- -- Catpure Status. Status is built from status word from DataMover -- and from transferred bytes value. ----------------------------------------------------------------------- UPDT_DESC_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_sts <= (others => '0'); elsif(sts_received_re = '1')then updt_desc_sts <= DESC_NOT_LAST & s2mm_ioc & s2mm_complete & s2mm_decerr & s2mm_slverr & s2mm_interr & sof_received -- If asserted also set SOF & eof_received -- If asserted also set EOF & RESERVED_STS & s2mm_xferd_bytes; elsif(sts_shftenbl='1')then updt_desc_sts <= updt_desc_reg3; end if; end if; end process UPDT_DESC_STATUS; ----------------------------------------------------------------------- -- If EOF Descriptor (writing_app_fields=1) then pass data from -- status stream FIFO into descriptor update shift registers -- Else pass zeros ----------------------------------------------------------------------- UPDT_REG3_MUX : process(writing_app_fields, stsstrm_fifo_dout, updt_zero_reg3, sts_shftenbl) begin if(writing_app_fields = '1')then updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting & '0' & stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word stsstrm_fifo_rden_i <= sts_shftenbl; else updt_desc_reg3 <= updt_zero_reg3; stsstrm_fifo_rden_i <= '0'; end if; end process UPDT_REG3_MUX; stsstrm_fifo_rden <= stsstrm_fifo_rden_i; ----------------------------------------------------------------------- -- APP 0 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD3 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream & '0' -- Don't set IOC & ZERO_VALUE; -- Remainder is zero -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg3 <= updt_zero_reg4; end if; end if; end process UPDT_ZERO_WRD3; ----------------------------------------------------------------------- -- APP 1 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD4 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream & '0' -- Don't set IOC & ZERO_VALUE; -- Remainder is zero -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg4 <= updt_zero_reg5; end if; end if; end process UPDT_ZERO_WRD4; ----------------------------------------------------------------------- -- APP 2 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD5 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream & '0' -- Don't set IOC & ZERO_VALUE; -- Remainder is zero -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg5 <= updt_zero_reg6; end if; end if; end process UPDT_ZERO_WRD5; ----------------------------------------------------------------------- -- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD6 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream & '0' -- Don't set IOC & ZERO_VALUE; -- Remainder is zero -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg6 <= DESC_LAST -- Last word of stream & s2mm_ioc & ZERO_VALUE; -- Remainder is zero end if; end if; end process UPDT_ZERO_WRD6; ----------------------------------------------------------------------- -- Drive TVALID -- If writing app then base on stsstrm fifo empty flag -- If writing datamover status then base simply assert on updt_sts ----------------------------------------------------------------------- TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty) begin if(updt_sts = '1' and writing_app_fields = '1')then updtsts_tvalid <= not stsstrm_fifo_empty; else updtsts_tvalid <= updt_sts; end if; end process TVALID_MUX; -- Drive TLAST updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH); -- Drive TDATA updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); end generate GEN_DESC_UPDT_STSAPP; -- Pass out to sg engine s_axis_s2mm_updtsts_tdata <= updtsts_tdata; s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid; s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid; end generate GEN_DESC_UPDT_QUEUE; --***************************************************************************-- --** Status Update Logic - NO DESCRIPTOR QUEUES **-- --***************************************************************************-- GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration -- Status received based on a DONE or an ERROR from DataMover sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr; -- Generate a rising edge off done for use in triggering an -- update to the SG engine REG_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sts_received_d1 <= '0'; else sts_received_d1 <= sts_received; end if; end if; end process REG_STATUS; -- CR 566306 Status invalid during halt -- sts_received_re <= sts_received and not sts_received_d1; sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2; --------------------------------------------------------------------------- -- When status received set and hold flag until -- status can be updated to queue. Note it may -- be held off due to update of data --------------------------------------------------------------------------- UPDT_STS_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_sts <= '0'; -- clear flag when status update done elsif(updt_sts_clr = '1')then updt_sts <= '0'; -- set flag when status received elsif(sts_received_re = '1')then updt_sts <= '1'; end if; end if; end process UPDT_STS_PROCESS; -- Clear status update on acceptance of tlast by sg engine updt_sts_clr <= '1' when updt_sts = '1' and updtsts_tvalid = '1' and updtsts_tlast = '1' and s_axis_s2mm_updtsts_tready = '1' else '0'; -- for queue case used to keep track of number of datamover queued cmnds UPDT_DONE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_update_done <= '0'; else desc_update_done <= updt_sts_clr; end if; end if; end process UPDT_DONE_PROCESS; --***********************************************************************-- --** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **-- --***********************************************************************-- --------------------------------------------------------------------------- -- Generate Descriptor Update Signaling for NO Status App Stream --------------------------------------------------------------------------- GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate begin stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate begin -- Transferred byte length from status is equal to bytes transferred field -- in descriptor status GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate begin s2mm_xferd_bytes <= s2mm_brcvd; end generate GEN_EQ_23BIT_BYTE_XFERED; -- Transferred byte length from status is less than bytes transferred field -- in descriptor status therefore need to pad value. GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd; end generate GEN_LESSTHN_23BIT_BYTE_XFERED; end generate GEN_NO_MICRO_DMA; GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate begin s2mm_xferd_bytes <= (others => '0'); end generate GEN_MICRO_DMA; ----------------------------------------------------------------------- -- Catpure Status. Status is built from status word from DataMover -- and from transferred bytes value. ----------------------------------------------------------------------- UPDT_DESC_WRD2 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_sts <= (others => '0'); -- Register Status on status received rising edge elsif(sts_received_re = '1')then updt_desc_sts <= DESC_LAST & s2mm_ioc & s2mm_complete & s2mm_decerr & s2mm_slverr & s2mm_interr & sof_received -- If asserted also set SOF & eof_received -- If asserted also set EOF & RESERVED_STS & s2mm_xferd_bytes; end if; end if; end process UPDT_DESC_WRD2; GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) & s2mm_desc_info_in (13 downto 10) & "000" & s2mm_desc_info_in (9 downto 5) & "000" & s2mm_desc_info_in (4 downto 0); end generate GEN_DESC_UPDT_MCDMA_NOQUEUE; GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); end generate GEN_DESC_UPDT_DMA_NOQUEUE; -- Drive TVALID updtsts_tvalid <= updt_sts; -- Drive TLAST updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH); -- Drive TData -- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0); end generate GEN_DESC_UPDT_NO_STSAPP; --***********************************************************************-- --** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **-- --***********************************************************************-- --------------------------------------------------------------------------- -- Generate Descriptor Update Signaling for NO Status App Stream --------------------------------------------------------------------------- GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate begin -- Rx length is identical to command written, therefore store -- the BTT value from the command written to be used as the xferd bytes. GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin ----------------------------------------------------------------------- -- On S2MM transferred bytes equals buffer length. Capture length -- on curdesc write. ----------------------------------------------------------------------- REG_XFERRED_BYTES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_xferd_bytes <= (others => '0'); elsif(s2mm_cmnd_wr = '1')then s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0); end if; end if; end process REG_XFERRED_BYTES; end generate GEN_USING_STSAPP_LENGTH; -- Configured as a store and forward channel (i.e. indeterminate BTT mode) -- Receive length will be reported in datamover status. GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin -- Transferred byte length from status is equal to bytes transferred field -- in descriptor status GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate begin s2mm_xferd_bytes <= s2mm_brcvd; end generate GEN_EQ_23BIT_BYTE_XFERED; -- Transferred byte length from status is less than bytes transferred field -- in descriptor status therefore need to pad value. GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd; end generate GEN_LESSTHN_23BIT_BYTE_XFERED; end generate GEN_NOT_USING_STSAPP_LENGTH; ----------------------------------------------------------------------- -- For EOF Descriptor then need to update APP fields from Status -- Stream FIFO ----------------------------------------------------------------------- WRITE_APP_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_app_fields <= '0'; -- If writing app fields and reach LAST then stop writing -- app fields elsif(writing_app_fields = '1' -- Writing app fields and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1) and stsstrm_fifo_rden_i = '1')then -- Fifo read writing_app_fields <= '0'; -- ON EOF Descriptor, then need to write application fields on desc -- update elsif(eof_received = '1' and s2mm_xferd_bytes /= ZERO_LENGTH) then writing_app_fields <= '1'; end if; end if; end process WRITE_APP_PROCESS; -- Shift in apps to SG engine if tvalid, tready, and not on last word sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready; ----------------------------------------------------------------------- -- Catpure Status. Status is built from status word from DataMover -- and from transferred bytes value. ----------------------------------------------------------------------- UPDT_DESC_WRD2 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_sts <= (others => '0'); -- Status from Prmry Datamover received elsif(sts_received_re = '1')then updt_desc_sts <= DESC_NOT_LAST & s2mm_ioc & s2mm_complete & s2mm_decerr & s2mm_slverr & s2mm_interr & sof_received -- If asserted also set SOF & eof_received -- If asserted also set EOF & RESERVED_STS & s2mm_xferd_bytes; -- Shift on descriptor update elsif(sts_shftenbl = '1')then updt_desc_sts <= updt_desc_reg3; end if; end if; end process UPDT_DESC_WRD2; ----------------------------------------------------------------------- -- If EOF Descriptor (writing_app_fields=1) then pass data from -- status stream FIFO into descriptor update shift registers -- Else pass zeros ----------------------------------------------------------------------- UPDT_REG3_MUX : process(writing_app_fields, stsstrm_fifo_dout, updt_zero_reg3, sts_shftenbl) begin if(writing_app_fields = '1')then updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting & '0' & stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word stsstrm_fifo_rden_i <= sts_shftenbl; else updt_desc_reg3 <= updt_zero_reg3; stsstrm_fifo_rden_i <= '0'; end if; end process UPDT_REG3_MUX; stsstrm_fifo_rden <= stsstrm_fifo_rden_i; ----------------------------------------------------------------------- -- APP 0 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD3 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg3 <= (others => '0'); -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg3 <= updt_zero_reg4; end if; end if; end process UPDT_ZERO_WRD3; ----------------------------------------------------------------------- -- APP 1 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD4 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg4 <= (others => '0'); -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg4 <= updt_zero_reg5; end if; end if; end process UPDT_ZERO_WRD4; ----------------------------------------------------------------------- -- APP 2 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD5 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg5 <= (others => '0'); -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg5 <= updt_zero_reg6; end if; end if; end process UPDT_ZERO_WRD5; ----------------------------------------------------------------------- -- APP 3 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD6 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg6 <= (others => '0'); -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg6 <= updt_zero_reg7; end if; end if; end process UPDT_ZERO_WRD6; ----------------------------------------------------------------------- -- APP 4 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD7 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_zero_reg7 <= (others => '0'); elsif(sts_received_re = '1')then updt_zero_reg7 <= DESC_LAST & '0' & ZERO_VALUE; end if; end if; end process UPDT_ZERO_WRD7; ----------------------------------------------------------------------- -- Drive TVALID -- If writing app then base on stsstrm fifo empty flag -- If writing datamover status then base simply assert on updt_sts ----------------------------------------------------------------------- TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty) begin if(updt_sts = '1' and writing_app_fields = '1')then updtsts_tvalid <= not stsstrm_fifo_empty; else updtsts_tvalid <= updt_sts; end if; end process TVALID_MUX; -- Drive TDATA updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- DRIVE TLAST updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH); end generate GEN_DESC_UPDT_STSAPP; -- Pass out to sg engine s_axis_s2mm_updtsts_tdata <= updtsts_tdata; s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid; s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid; end generate GEN_DESC_UPDT_NO_QUEUE; end implementation;
gpl-3.0
76b7f069caf0a58794326572492685ac
0.438178
4.443589
false
false
false
false
stanford-ppl/spatial-lang
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_bdg/ghrd_10as066n2_rst_bdg_inst.vhd
1
460
component ghrd_10as066n2_rst_bdg is port ( clk : in std_logic := 'X'; -- clk in_reset : in std_logic := 'X'; -- reset out_reset : out std_logic -- reset ); end component ghrd_10as066n2_rst_bdg; u0 : component ghrd_10as066n2_rst_bdg port map ( clk => CONNECTED_TO_clk, -- clk.clk in_reset => CONNECTED_TO_in_reset, -- in_reset.reset out_reset => CONNECTED_TO_out_reset -- out_reset.reset );
mit
09fbdbececcc9c92d5148cac03dc0696
0.578261
2.705882
false
false
false
false
makestuff/comm-fpga
ss/vhdl/sync-send/tb_unit/sync_send_tb.vhdl
1
3,973
-- -- Copyright (C) 2009-2012 Chris McClelland -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; entity sync_send_tb is end entity; architecture behavioural of sync_send_tb is signal sysClk : std_logic; -- main system clock signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns -- Serial out signal serClk : std_logic; signal serData : std_logic; -- Parallel in signal sendData : std_logic_vector(7 downto 0); signal sendValid : std_logic; signal sendReady : std_logic; -- Detect rising serClk edges signal serClk_prev : std_logic; signal serClkRE : std_logic; begin -- Instantiate sync_send module for testing uut: entity work.sync_send port map( clk_in => sysClk, -- Serial I/O serClkRE_in => serClkRE, serData_out => serData, -- Parallel out sendData_in => sendData, sendValid_in => sendValid, sendReady_out => sendReady ); -- Infer registers process(sysClk) begin if ( rising_edge(sysClk) ) then serClk_prev <= serClk; end if; end process; -- Detect rising edges on serClk serClkRE <= '1' when serClk = '1' and serClk_prev = '0' else '0'; -- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time -- for signals in GTKWave. process begin sysClk <= '0'; dispClk <= '1'; wait for 10 ns; dispClk <= '0'; wait for 10 ns; loop dispClk <= '1'; wait for 4 ns; sysClk <= '1'; wait for 6 ns; dispClk <= '0'; wait for 4 ns; sysClk <= '0'; wait for 6 ns; end loop; end process; -- Drive serClk process begin serClk <= '0'; loop wait until rising_edge(sysClk); wait until rising_edge(sysClk); wait until rising_edge(sysClk); wait until rising_edge(sysClk); serClk <= not(serClk); end loop; end process; -- Drive the sync serial signals process --procedure sendByte(constant b : in std_logic_vector(7 downto 0)) is --begin -- serData <= '0'; -- start bit -- wait until rising_edge(serClk); serData <= b(0); -- bit 0 -- wait until rising_edge(serClk); serData <= b(1); -- bit 1 -- wait until rising_edge(serClk); serData <= b(2); -- bit 2 -- wait until rising_edge(serClk); serData <= b(3); -- bit 3 -- wait until rising_edge(serClk); serData <= b(4); -- bit 4 -- wait until rising_edge(serClk); serData <= b(5); -- bit 5 -- wait until rising_edge(serClk); serData <= b(6); -- bit 6 -- wait until rising_edge(serClk); serData <= b(7); -- bit 7 -- wait until rising_edge(serClk); serData <= '1'; -- stop bit -- wait until rising_edge(serClk); --end procedure; procedure pause(constant n : in integer) is variable i : integer; begin for i in 1 to n loop wait until rising_edge(serClk); end loop; end procedure; begin sendData <= (others => 'X'); sendValid <= '0'; pause(4); wait until rising_edge(sysClk); sendData <= x"55"; sendValid <= '1'; wait until falling_edge(sendReady); sendData <= (others => 'X'); sendValid <= '0'; pause(4); sendData <= x"55"; sendValid <= '1'; wait until falling_edge(sendReady); sendData <= (others => 'X'); sendValid <= '0'; wait; end process; end architecture;
gpl-3.0
50abaeecc1f89f0d5ce4119d13150943
0.652152
3.243265
false
false
false
false
tgingold/ghdl
testsuite/synth/dispvhdl01/tb_vhd01.vhdl
1
441
entity tb_vhd01 is end tb_vhd01; library ieee; use ieee.std_logic_1164.all; use work.pkg.all; architecture behav of tb_vhd01 is signal i1, o1 : std_logic_vector(1 to 1); begin dut: entity work.vhd01 port map (i1 => i1, o1 => o1); process begin i1 <= "1"; wait for 1 ns; assert o1 = "1" severity failure; i1 <= "0"; wait for 1 ns; assert o1 = "0" severity failure; wait; end process; end behav;
gpl-2.0
9cd63e69f9276d8d43587b9cea7b0486
0.619048
2.826923
false
false
false
false
tgingold/ghdl
testsuite/synth/issue1122/mult.vhd
1
5,939
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mult_pkg.all; entity mult is port ( clk : in std_logic; rst : in std_logic; slot : in std_logic; a : in mult_i_t; y : out mult_o_t); end mult; architecture stru of mult is signal this_c : mult_reg_t; signal this_r : mult_reg_t := MULT_RESET; begin mult : process(this_r, slot, a) variable this : mult_reg_t; variable aa : std_logic_vector(31 downto 0); variable ah : std_logic_vector(30 downto 0); variable bh : std_logic_vector(15 downto 0); variable abh2 : std_logic_vector(32 downto 0); variable p2 : std_logic_vector(31 downto 0); variable p3 : std_logic_vector(31 downto 0); variable sgn : std_logic_vector(31 downto 0); variable pm : std_logic_vector(47 downto 0); variable c : std_logic_vector(63 downto 0); variable acc : std_logic_vector(63 downto 0); variable region: std_logic_vector(2 downto 0); variable sat : std_logic; variable code : mult_codeline_t; begin this := this_r; code := MULT_CODE(this.state); y.busy <= code.busy; -- FIXME: warning : combinatorial output -- operand intermediates, multiplier and input mux, lower 31bits of A and upper/lower 16bits of B aa := this.m1; if code.sela = MB then aa := this.mb; end if; ah := aa(30 downto 0); if code.size = B16 then ah(30 downto 15) := (others => '0'); end if; bh := this.m2(15 downto 0); if code.size = B16 then bh(15) := '0'; elsif code.shift = '1' then bh := '0' & this.m2(30 downto 16); end if; -- partial product adder input mux if code.size = B16 then abh2 := '0' & x"0000" & (aa(15) and this.m2(15)) & this.abh(29 downto 15); elsif this.shift = '0' then abh2 := '0' & this.abh(46 downto 15); else abh2 := '0' & (aa(31) and this.m2(31)) & this.abh(45 downto 15); end if; -- partial products adders p2 := (others => '0'); if aa(31) = '1' and code.shift = '1' then p2 := '0' & this.m2(30 downto 0); end if; if aa(15) = '1' and code.size = B16 then p2 := x"0000" & '0' & this.m2(14 downto 0); end if; p3 := (others => '0'); if this.m2(31) = '1' and code.shift = '1' then p3 := '0' & aa(30 downto 0); end if; if this.m2(15) = '1' and code.size = B16 then p3 := x"0000" & '0' & aa(14 downto 0); end if; if code.sign = 1 then sgn := (others => '1'); else sgn := (others => '0'); end if; pm := std_logic_vector(unsigned(abh2) + unsigned(sgn(0) & (this.p23 xor sgn)) + code.sign) & this.abh(14 downto 0); this.p23 := std_logic_vector(unsigned(p2) + unsigned(p3)); if this.shift = '0' then if pm(47) = '1' and code.size = B16 then c := x"ffff" & pm; else c := x"0000" & pm; end if; else c := pm & x"0000"; end if; -- accumulator acc := std_logic_vector(unsigned(c) + unsigned((this.mach and to_slv(code.use_h, 32)) & this.macl)); -- saturate sat := '1'; region := (others => '0'); case this.result_op is when IDENTITY => sat := '0'; when SATURATE64 => if acc(63) = '0' and acc(62 downto 47) /= x"0000" then region(0) := '1'; elsif acc(63) = '1' and acc(62 downto 47) /= x"ffff" then region(0) := '1'; end if; region(2 downto 1) := this.mach(31) & acc(63); if c(63) = '0' then case region is when "001" | "010" | "011" | "101" => acc := P48MAX; when "111" => acc := N48MAX; when others => sat := '0'; end case; else case region is when "001" => acc := P48MAX; when "011" | "100" | "101" | "111" => acc := N48MAX; when others => sat := '0'; end case; end if; when SATURATE32 => region := this.macl(31) & acc(31) & '0'; if c(31) = '0' then case (region) is when "010" => acc := P32MAX; when others => sat := '0'; end case; else case (region) is when "100" => acc := N32MAX; when others => sat := '0'; end case; end if; end case; -- multiplier this.abh := std_logic_vector(unsigned(ah) * unsigned(bh)); -- load the internal registers from the CPU if slot = '1' then if a.command /= NOP then this.m2 := a.in2; if a.command = MACL or a.command = MACW then this.mb := this.m1; end if; end if; if a.wr_m1 = '1' then this.m1 := a.in1; end if; end if; if slot = '1' and a.wr_mach = '1' then this.mach := a.in1; elsif slot = '1' and (a.command = DMULSL or a.command = DMULUL) then this.mach := x"00000000"; elsif this.state = MACWS1 and sat = '1' then this.mach := this.mach or x"00000001"; elsif code.mach_en = '1' then this.mach := acc(63 downto 32); end if; if slot = '1' and a.wr_macl = '1' then this.macl := a.in2; elsif slot = '1' and a.command /= NOP and a.command /= MACL and a.command /= MACW then this.macl := x"00000000"; elsif code.macl_en = '1' then this.macl := acc(31 downto 0); end if; -- delayed versions of the control signals to delay for p23 pipeline register this.state := code.state; this.shift := code.shift; -- load the command from the CPU if code.busy = '0' and slot = '1' then this.result_op := IDENTITY; this.state := a.command; if a.command = MACL then if a.s = '1' then this.result_op := SATURATE64; end if; elsif a.command = MACW then -- override start state, MACWS and MACW set different busy and mach_en values if a.s = '1' then this.result_op := SATURATE32; this.state := MACWS; end if; end if; end if; this_c <= this; end process; mult_r0 : process(clk, rst) begin if rst='1' then this_r <= MULT_RESET; elsif clk='1' and clk'event then this_r <= this_c; end if; end process; -- drive the outputs y.mach <= this_r.mach; y.macl <= this_r.macl; end stru;
gpl-2.0
f74cadf7baa1d179679c99c226897c70
0.568446
3.051901
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_50M_0/synth/design_1_rst_processing_system7_0_50M_0.vhd
1
6,745
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 9 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY design_1_rst_processing_system7_0_50M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END design_1_rst_processing_system7_0_50M_0; ARCHITECTURE design_1_rst_processing_system7_0_50M_0_arch OF design_1_rst_processing_system7_0_50M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_1_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_processing_system7_0_50M_0_arch : ARCHITECTURE IS "design_1_rst_processing_system7_0_50M_0,proc_sys_reset,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "design_1_rst_processing_system7_0_50M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END design_1_rst_processing_system7_0_50M_0_arch;
gpl-3.0
2edb93900c82e9dc429cba2939e20703
0.716679
3.451894
false
false
false
false
tgingold/ghdl
testsuite/synth/synth109/tb_ram9.vhdl
1
1,806
entity tb_ram3 is end tb_ram3; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_ram3 is signal clkA : std_logic; signal enA : std_logic; signal weA : std_logic; signal addrA : std_logic_vector(7 downto 0); signal rdatA : std_logic_vector(7 downto 0); signal wdatA : std_logic_vector(7 downto 0); signal clkB : std_logic; signal enB : std_logic; signal weB : std_logic; signal addrB : std_logic_vector(5 downto 0); signal rdatB : std_logic_vector(31 downto 0); signal wdatB : std_logic_vector(31 downto 0); begin dut: entity work.ram3 port map (clkA => clkA, clkB => clkB, enA => enA, enB => enB, weA => weA, weB => weB, addrA => addrA, addrB => addrB, diA => wdatA, diB => wdatB, doA => rdatA, doB => rdatB); process procedure pulseB is begin clkB <= '0'; wait for 1 ns; clkB <= '1'; wait for 1 ns; end pulseB; begin clkA <= '0'; enA <= '0'; enB <= '1'; weB <= '1'; addrB <= b"00_0000"; wdatB <= x"11_22_33_f0"; pulseB; pulseB; assert rdatB = x"11_22_33_f0" severity failure; addrB <= b"00_0001"; wdatB <= x"11_22_33_f1"; pulseB; pulseB; assert rdatB = x"11_22_33_f1" severity failure; -- Read. weB <= '0'; addrB <= b"00_0000"; wdatB <= x"ff_22_33_f1"; pulseB; pulseB; assert rdatB = x"11_22_33_f0" severity failure; addrB <= b"00_0001"; wdatB <= x"ff_22_33_f1"; pulseB; pulseB; assert rdatB = x"11_22_33_f1" severity failure; -- Disable. enB <= '0'; weB <= '1'; addrB <= b"00_0000"; wdatB <= x"11_22_33_f0"; pulseB; assert rdatB = x"11_22_33_f1" severity failure; wait; end process; end behav;
gpl-2.0
54295456ce3a66f4af2b51efb8a79b80
0.554817
3.129983
false
false
false
false
tgingold/ghdl
testsuite/gna/issue42/bugreport_attribute.vhdl
1
3,011
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Reproducer: Experiments on custom attributes ended in a crash. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= -- -- Issue: -- I'm not sure if my experimental code is allowed in VHDL, but it let GHDL -- crash. So I'm reporting just an unhandled exception. -- -- GHDL's output is: -- .\attribute.vhdl:64:58: can't match 'image attribute with type character -- .\attribute.vhdl:64:53: (location of 'image attribute) -- finish_sem_name: cannot handle IIR_KIND_OVERLOAD_LIST (??:??:??) -- -- ******************** GHDL Bug occurred **************************** -- Please report this bug on https://github.com/tgingold/ghdl/issues -- GHDL release: GHDL 0.34dev (commit: 2016-02-11; git branch: paebbels/master'; hash: f24fdfb) [Dunoon edition] -- Compiled with GNAT Version: GPL 2015 (20150428-49) -- In directory: H:\Austausch\PoC\temp\ghdl\ -- Command line: -- C:\Tools\GHDL.new\bin\ghdl.exe -a --std=08 .\attribute.vhdl -- Exception TYPES.INTERNAL_ERROR raised -- Exception information: -- Exception name: TYPES.INTERNAL_ERROR -- Message: errorout.adb:66 -- ****************************************************************** -- -- GHDL calls: -- PS> ghdl.exe -a --std=93c .\attribute.vhdl -- PS> ghdl.exe -a --std=08 .\attribute.vhdl -- library IEEE; use IEEE.std_logic_1164.all; entity test is end entity; architecture tb of test is function to_string(slv : STD_LOGIC_VECTOR) return STRING is variable Result : STRING(slv'length - 1 downto 0); begin for i in slv'range loop Result(i + 1) := STD_LOGIC'image(slv(i)); end loop; return Result; end function; attribute serialize : to_string; signal mySignal : STD_LOGIC_VECTOR(7 downto 0); attribute serialize of mySignal : signal is to_string[STD_LOGIC_VECTOR return STRING]; begin mySignal <= x"24"; process begin report "mySignal=" & mySignal'serialize severity NOTE; wait; end process; end architecture;
gpl-2.0
0299ca5eee39252a003208b831bec405
0.622717
3.610312
false
false
false
false
tgingold/ghdl
testsuite/synth/issue1122/mult_pkg.vhd
1
4,520
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package mult_pkg is type mult_state_t is (NOP, DMULSL, DMULSL1, DMULSL2, DMULUL, DMULUL1, DMULUL2, MACL, MACL1, MACL2, MACW, MACW1, MACWS, MACWS1, MULL, MULL1, MULL2, MULSW, MULSW1, MULUW, MULUW1); type mult_result_op_t is (IDENTITY, SATURATE32, SATURATE64); type mult_sela_t is ( M1, MB ); type mult_size_t is ( B16, B32 ); constant P48MAX : std_logic_vector(63 downto 0) := x"00007fffffffffff"; constant N48MAX : std_logic_vector(63 downto 0) := x"ffff800000000000"; constant P32MAX : std_logic_vector(63 downto 0) := x"000000007fffffff"; constant N32MAX : std_logic_vector(63 downto 0) := x"ffffffff80000000"; type mult_codeline_t is record state : mult_state_t; busy : std_logic; sela : mult_sela_t; shift : std_logic; sign : integer range 0 to 1; size : mult_size_t; mach_en : std_logic; macl_en : std_logic; use_h : std_logic; end record; type mult_microcode_t is array (mult_state_t) of mult_codeline_t; constant MULT_CODE : mult_microcode_t := ( -- state busy sela shft sign size h_en l_en use_h ( NOP, '0', M1, '0', 0, B16, '0', '0', '1' ), -- NOP ( DMULSL1, '1', M1, '0', 1, B32, '0', '0', '1' ), -- DMULSL ( DMULSL2, '1', M1, '1', 1, B32, '1', '1', '1' ), -- DMULSL1 ( NOP, '0', M1, '1', 1, B32, '1', '1', '1' ), -- DMULSL2 ( DMULUL1, '1', M1, '0', 0, B32, '0', '0', '1' ), -- DMULUL ( DMULUL2, '1', M1, '1', 0, B32, '1', '1', '1' ), -- DMULUL1 ( NOP, '0', M1, '1', 0, B32, '1', '1', '1' ), -- DMULUL2 ( MACL1, '1', MB, '0', 1, B32, '0', '0', '1' ), -- MACL ( MACL2, '1', MB, '1', 1, B32, '1', '1', '1' ), -- MACL1 ( NOP, '0', MB, '1', 1, B32, '1', '1', '1' ), -- MACL2 ( MACW1, '1', M1, '0', 1, B16, '0', '0', '1' ), -- MACW ( NOP, '0', M1, '0', 1, B16, '1', '1', '1' ), -- MACW1 ( MACWS1, '1', M1, '0', 1, B16, '0', '0', '0' ), -- MACWS ( NOP, '0', M1, '0', 1, B16, '0', '1', '0' ), -- MACWS1 ( MULL1, '1', M1, '0', 1, B32, '0', '0', '0' ), -- MULL ( MULL2, '1', M1, '1', 1, B32, '0', '1', '0' ), -- MULL1 ( NOP, '0', M1, '1', 1, B32, '0', '1', '0' ), -- MULL2 ( MULSW1, '1', M1, '0', 1, B16, '0', '0', '0' ), -- MULSW ( NOP, '0', M1, '0', 1, B16, '0', '1', '0' ), -- MULSW1 ( MULUW1, '1', M1, '0', 0, B16, '0', '0', '0' ), -- MULUW ( NOP, '0', M1, '0', 0, B16, '0', '1', '0' ) -- MULUW1 ); type mult_i_t is record wr_m1 : std_logic; command : mult_state_t; s : std_logic; wr_mach : std_logic; wr_macl : std_logic; in1 : std_logic_vector(31 downto 0); in2 : std_logic_vector(31 downto 0); end record; type mult_o_t is record mach : std_logic_vector(31 downto 0); macl : std_logic_vector(31 downto 0); busy : std_logic; end record; type mult_reg_t is record state : mult_state_t; result_op : mult_result_op_t; m1, m2, mb : std_logic_vector(31 downto 0); p23 : std_logic_vector(31 downto 0); mach, macl : std_logic_vector(31 downto 0); shift : std_logic; abh : std_logic_vector(46 downto 0); end record; constant MULT_RESET : mult_reg_t := (state => NOP, result_op => IDENTITY, m1 => (others => '0'), m2 => (others => '0'), mb => (others => '0'), p23 => (others => '0'), mach => (others => '0'), macl => (others => '0'), shift => '0', abh => (others => '0') ); component mult is port ( clk : in std_logic; rst : in std_logic; slot : in std_logic; a : in mult_i_t; y : out mult_o_t); end component mult; function to_slv(b : std_logic; s : integer) return std_logic_vector; end package; package body mult_pkg is function to_slv(b : std_logic; s : integer) return std_logic_vector is variable r : std_logic_vector(s-1 downto 0); begin r := (others => b); return r; end function to_slv; end package body;
gpl-2.0
06e0989721c998c182c1cb0537eef5ed
0.459735
2.734422
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_04.vhd
4
2,297
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_07_fg_07_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity fg_07_04 is end entity fg_07_04; architecture test of fg_07_04 is signal phase1, phase2, reg_file_write_en, A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0'; begin -- code from book control_sequencer : process is procedure control_write_back is begin wait until phase1 = '1'; reg_file_write_en <= '1'; wait until phase2 = '0'; reg_file_write_en <= '0'; end procedure control_write_back; procedure control_arith_op is begin wait until phase1 = '1'; A_reg_out_en <= '1'; B_reg_out_en <= '1'; wait until phase1 = '0'; A_reg_out_en <= '0'; B_reg_out_en <= '0'; wait until phase2 = '1'; C_reg_load_en <= '1'; wait until phase2 = '0'; C_reg_load_en <= '0'; control_write_back; -- call procedure end procedure control_arith_op; -- . . . begin -- . . . control_arith_op; -- call procedure -- . . . -- not in book wait; -- end not in book end process control_sequencer; -- end code from book clock_gen : process is begin phase1 <= '1' after 10 ns, '0' after 20 ns; phase2 <= '1' after 30 ns, '0' after 40 ns; wait for 40 ns; end process clock_gen; end architecture test;
gpl-2.0
8db1ec706b3486d9bd5e88ccdc4c7893
0.589029
3.550232
false
false
false
false
nickg/nvc
test/regress/issue38.vhd
1
756
package p is function f (i : bit) return integer; end package p; package body p is function f (i : bit) return integer is begin report f'instance_name; assert f'instance_name = ":work:p:f:"; assert f'path_name = ":work:p:f:"; return 0; end function f; end package body p; ------------------------------------------------------------------------------- entity issue38 is begin end entity issue38; use work.p.all; architecture a of issue38 is function g (i : bit) return integer is begin assert g'instance_name = ":issue38(a):g:"; assert g'path_name = ":issue38:g:"; return 0; end function g; begin assert (f('1') = 0); assert (g('1') = 0); end architecture a;
gpl-3.0
9d8f0b3696639a34113beb28cbd1931f
0.537037
3.687805
false
false
false
false
DE5Amigos/SylvesterTheDE2Bot
DE2Botv3Fall16Main/TIMER.vhd
1
1,301
-- TIMER.VHD (a peripheral module for SCOMP) -- 2003.04.24 -- -- Timer returns a 16 bit counter value with a resolution of the CLOCK period. -- Writing any value to timer resets to 0x0000, but the timer continues to run. -- The counter value rolls over to 0x0000 after a clock tick at 0xFFFF. LIBRARY IEEE; LIBRARY LPM; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE LPM.LPM_COMPONENTS.ALL; ENTITY TIMER IS PORT(CLOCK, RESETN, CS, IO_WRITE : IN STD_LOGIC; IO_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END TIMER; ARCHITECTURE a OF TIMER IS SIGNAL COUNT : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL IO_OUT : STD_LOGIC; BEGIN -- Use LPM function to create bidirection I/O data bus IO_BUS: lpm_bustri GENERIC MAP ( lpm_width => 16 ) PORT MAP ( data => COUNT, enabledt => IO_OUT, tridata => IO_DATA ); IO_OUT <= (CS AND NOT(IO_WRITE)); PROCESS (CLOCK, RESETN, CS, IO_WRITE) BEGIN IF (RESETN = '0' OR (CS AND IO_WRITE) = '1') THEN COUNT <= x"0000"; ELSIF (FALLING_EDGE(CLOCK)) THEN COUNT <= COUNT + 1; END IF; END PROCESS; END a;
mit
cede11a92103736537af2df6679415f1
0.587241
3.497312
false
false
false
false
tgingold/ghdl
testsuite/gna/bug019/PoC/src/io/uart/uart_fifo.vhdl
3
10,178
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Martin Zabel -- Patrick Lehmann -- -- Module: UART Wrapper with Embedded FIFOs and Optional Flow Control -- -- Description: -- ------------------------------------ -- Small FIFOs are included in this module, if larger or asynchronous -- transmit / receive FIFOs are required, then they must be connected -- externally. -- -- old comments: -- UART BAUD rate generator -- bclk = bit clock is rising -- bclk_x8 = bit clock times 8 is rising -- -- -- License: -- ============================================================================ -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.vectors.all; use PoC.physical.all; use PoC.components.all; use PoC.uart.all; entity uart_fifo is generic ( CLOCK_FREQ : FREQ := 100 MHz; BAUDRATE : BAUD := 115200 Bd; FLOWCONTROL : T_IO_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE; TX_MIN_DEPTH : POSITIVE := 16; TX_ESTATE_BITS : NATURAL := 1; RX_MIN_DEPTH : POSITIVE := 16; RX_FSTATE_BITS : NATURAL := 1; RX_OUT_REGS : BOOLEAN := FALSE; ADD_INPUT_SYNCHRONIZERS : BOOLEAN := TRUE; SWFC_XON_CHAR : std_logic_vector(7 downto 0) := x"11"; -- ^Q SWFC_XON_TRIGGER : real := 0.0625; SWFC_XOFF_CHAR : std_logic_vector(7 downto 0) := x"13"; -- ^S SWFC_XOFF_TRIGGER : real := 0.75 ); port ( Clock : in std_logic; Reset : in std_logic; -- FIFO interface TX_put : in STD_LOGIC; TX_Data : in STD_LOGIC_VECTOR(7 downto 0); TX_Full : out STD_LOGIC; TX_EmptyState : out STD_LOGIC_VECTOR(TX_ESTATE_BITS - 1 downto 0); RX_Valid : out STD_LOGIC; RX_Data : out STD_LOGIC_VECTOR(7 downto 0); RX_got : in STD_LOGIC; RX_FullState : out STD_LOGIC_VECTOR(RX_FSTATE_BITS - 1 downto 0); RX_Overflow : out std_logic; -- External pins UART_TX : out std_logic; UART_RX : in std_logic ); end entity; architecture rtl of uart_fifo is signal FC_TX_Strobe : STD_LOGIC; signal FC_TX_Data : T_SLV_8; signal FC_TX_got : STD_LOGIC; signal FC_RX_put : STD_LOGIC; signal FC_RX_Data : T_SLV_8; signal TXFIFO_Valid : STD_LOGIC; signal TXFIFO_Data : T_SLV_8; signal RXFIFO_Full : STD_LOGIC; signal TXUART_Ready : STD_LOGIC; signal RXUART_Strobe : STD_LOGIC; signal RXUART_Data : T_SLV_8; signal BitClock : STD_LOGIC; signal BitClock_x8 : STD_LOGIC; signal UART_RX_sync : STD_LOGIC; begin assert FALSE report "uart_fifo: BAUDRATE=: " & to_string(BAUDRATE, 3) severity NOTE; -- =========================================================================== -- Transmit and Receive FIFOs -- =========================================================================== TXFIFO : entity PoC.fifo_cc_got generic map ( D_BITS => 8, -- Data Width MIN_DEPTH => TX_MIN_DEPTH, -- Minimum FIFO Depth DATA_REG => TRUE, -- Store Data Content in Registers STATE_REG => FALSE, -- Registered Full/Empty Indicators OUTPUT_REG => FALSE, -- Registered FIFO Output ESTATE_WR_BITS => TX_ESTATE_BITS, -- Empty State Bits FSTATE_RD_BITS => 0 -- Full State Bits ) port map ( rst => Reset, clk => Clock, put => TX_put, din => TX_Data, full => TX_Full, estate_wr => TX_EmptyState, valid => TXFIFO_Valid, dout => TXFIFO_Data, got => FC_TX_got, fstate_rd => open ); RXFIFO : entity PoC.fifo_cc_got generic map ( D_BITS => 8, -- Data Width MIN_DEPTH => RX_MIN_DEPTH, -- Minimum FIFO Depth DATA_REG => TRUE, -- Store Data Content in Registers STATE_REG => FALSE, -- Registered Full/Empty Indicators OUTPUT_REG => FALSE, -- Registered FIFO Output ESTATE_WR_BITS => 0, -- Empty State Bits FSTATE_RD_BITS => RX_FSTATE_BITS -- Full State Bits ) port map ( rst => Reset, clk => Clock, put => FC_RX_put, din => FC_RX_Data, full => RXFIFO_Full, estate_wr => open, valid => RX_Valid, dout => RX_Data, got => RX_got, fstate_rd => RX_FullState ); genNOFC : if (FLOWCONTROL = UART_FLOWCONTROL_NONE) generate signal Overflow_r : std_logic := '0'; begin FC_TX_Strobe <= TXFIFO_Valid and TXUART_Ready; FC_TX_Data <= TXFIFO_Data; FC_TX_got <= TXFIFO_Valid and TXUART_Ready; FC_RX_put <= RXUART_Strobe; FC_RX_Data <= RXUART_Data; Overflow_r <= ffrs(q => Overflow_r, rst => Reset, set => (RXUART_Strobe and RXFIFO_Full)) when rising_edge(Clock); RX_Overflow <= Overflow_r; end generate; -- =========================================================================== -- Software Flow Control -- =========================================================================== genSWFC : if (FLOWCONTROL = UART_FLOWCONTROL_XON_XOFF) generate constant XON : std_logic_vector(7 downto 0) := x"11"; -- ^Q constant XOFF : std_logic_vector(7 downto 0) := x"13"; -- ^S constant XON_TRIG : integer := integer(SWFC_XON_TRIGGER * real(2**RX_FSTATE_BITS)); constant XOFF_TRIG : integer := integer(SWFC_XOFF_TRIGGER * real(2**RX_FSTATE_BITS)); signal send_xoff : std_logic; signal send_xon : std_logic; signal set_xoff_transmitted : std_logic; signal clr_xoff_transmitted : std_logic; signal discard_user : std_logic; signal set_overflow : std_logic; -- registers signal xoff_transmitted : std_logic; begin -- -- send XOFF only once when fill state goes above trigger level -- send_xoff <= (not xoff_transmitted) when (rf_fs >= XOFF_TRIG) else '0'; -- set_xoff_transmitted <= tx_rdy when (rf_fs >= XOFF_TRIG) else '0'; -- -- -- send XON only once when receive FIFO is almost empty -- send_xon <= xoff_transmitted when (rf_fs = XON_TRIG) else '0'; -- clr_xoff_transmitted <= tx_rdy when (rf_fs = XON_TRIG) else '0'; -- -- -- discard any user supplied XON/XOFF -- discard_user <= '1' when (tf_dout = SWFC_XON_CHAR) or (tf_dout = SWFC_XOFF_CHAR) else '0'; -- -- -- tx / tf control -- tx_din <= SWFC_XOFF_CHAR when (send_xoff = '1') else -- SWFC_XON_CHAR when (send_xon = '1') else -- tf_dout; -- -- tx_stb <= send_xoff or send_xon or (tf_valid and (not discard_user)); -- tf_got <= (send_xoff nor send_xon) and -- tf_valid and tx_rdy; -- always check tf_valid -- -- -- rx / rf control -- rf_put <= (not rf_full) and rx_dos; -- always check rf_full -- rf_din <= rx_dout; -- -- set_overflow <= rf_full and rx_dos; -- -- -- registers -- process (Clock) -- begin -- process -- if rising_edge(Clock) then -- if (rst or set_xoff_transmitted) = '1' then -- -- send a XON after reset -- xoff_transmitted <= '1'; -- elsif clr_xoff_transmitted = '1' then -- xoff_transmitted <= '0'; -- end if; -- -- if rst = '1' then -- overflow <= '0'; -- elsif set_overflow = '1' then -- overflow <= '1'; -- end if; -- end if; -- end process; end generate; -- =========================================================================== -- Hardware Flow Control -- =========================================================================== genHWFC1 : if (FLOWCONTROL = UART_FLOWCONTROL_RTS_CTS) generate begin end generate; -- =========================================================================== -- Hardware Flow Control -- =========================================================================== genHWFC2 : if (FLOWCONTROL = UART_FLOWCONTROL_RTR_CTS) generate begin end generate; -- =========================================================================== -- BitClock, Transmitter, Receiver -- =========================================================================== genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate UART_RX_sync <= UART_RX; end generate; genSync: if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate sync_i : entity PoC.sync_Bits port map ( Clock => Clock, -- Clock to be synchronized to Input(0) => UART_RX, -- Data to be synchronized Output(0) => UART_RX_sync -- synchronised data ); end generate; -- =========================================================================== -- BitClock, Transmitter, Receiver -- =========================================================================== bclk : entity PoC.uart_bclk generic map ( CLOCK_FREQ => CLOCK_FREQ, BAUDRATE => BAUDRATE ) port map ( clk => Clock, rst => Reset, bclk => BitClock, bclk_x8 => BitClock_x8 ); TX : entity PoC.uart_tx port map ( clk => Clock, rst => Reset, bclk => BitClock, stb => FC_TX_Strobe, din => FC_TX_Data, rdy => TXUART_Ready, txd => UART_TX ); RX : entity PoC.uart_rx generic map ( OUT_REGS => RX_OUT_REGS ) port map ( clk => Clock, rst => Reset, bclk_x8 => BitClock_x8, dos => RXUART_Strobe, dout => RXUART_Data, rxd => UART_RX_sync ); end;
gpl-2.0
dec832393aa6002c2751575ab0fed764
0.531244
3.248643
false
false
false
false
tgingold/ghdl
testsuite/gna/bug040/outdata_comp_vpos.vhd
2
1,476
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity outdata_comp_vpos is port ( wa0_data : in std_logic_vector(31 downto 0); wa0_addr : in std_logic_vector(1 downto 0); clk : in std_logic; ra0_addr : in std_logic_vector(1 downto 0); ra0_data : out std_logic_vector(31 downto 0); wa0_en : in std_logic ); end outdata_comp_vpos; architecture augh of outdata_comp_vpos is -- Embedded RAM type ram_type is array (0 to 2) of std_logic_vector(31 downto 0); signal ram : ram_type := (others => (others => '0')); -- Little utility functions to make VHDL syntactically correct -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. -- This happens when accessing arrays with <= 2 cells, for example. function to_integer(B: std_logic) return integer is variable V: std_logic_vector(0 to 0); begin V(0) := B; return to_integer(unsigned(V)); end; function to_integer(V: std_logic_vector) return integer is begin return to_integer(unsigned(V)); end; begin -- Sequential process -- It handles the Writes process (clk) begin if rising_edge(clk) then -- Write to the RAM -- Note: there should be only one port. if wa0_en = '1' then ram( to_integer(wa0_addr) ) <= wa0_data; end if; end if; end process; -- The Read side (the outputs) ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-'); end architecture;
gpl-2.0
6a41ab2fc26aac2ad44a2a4dad76318d
0.672764
2.911243
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi-b.vhd
4
13,461
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_15_dlxi-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- library bv_utilities; package body dlx_instr is use bv_utilities.bv_arithmetic.all; constant opcode_names : opcode_name_array := ( "SPECIAL ", "FPARITH ", "J ", "JAL ", "BEQZ ", "BNEZ ", "BFPT ", "BFPF ", "ADDI ", "ADDUI ", "SUBI ", "SUBUI ", "ANDI ", "ORI ", "XORI ", "LHI ", "RFE ", "TRAP ", "JR ", "JALR ", "SLLI ", "UNDEF_15", "SRLI ", "SRAI ", "SEQI ", "SNEI ", "SLTI ", "SGTI ", "SLEI ", "SGEI ", "UNDEF_1E", "UNDEF_1F", "LB ", "LH ", "UNDEF_22", "LW ", "LBU ", "LHU ", "LF ", "LD ", "SB ", "SH ", "UNDEF_2A", "SW ", "UNDEF_2C", "UNDEF_2D", "SF ", "SD ", "SEQUI ", "SNEUI ", "SLTUI ", "SGTUI ", "SLEUI ", "SGEUI ", "UNDEF_36", "UNDEF_37", "UNDEF_38", "UNDEF_39", "UNDEF_3A", "UNDEF_3B", "UNDEF_3C", "UNDEF_3D", "UNDEF_3E", "UNDEF_3F" ); constant sp_func_names : sp_func_name_array := ( "NOP ", "UNDEF_01", "UNDEF_02", "UNDEF_03", "SLL ", "UNDEF_05", "SRL ", "SRA ", "UNDEF_08", "UNDEF_09", "UNDEF_0A", "UNDEF_0B", "UNDEF_0C", "UNDEF_0D", "UNDEF_0E", "UNDEF_0F", "SEQU ", "SNEU ", "SLTU ", "SGTU ", "SLEU ", "SGEU ", "UNDEF_16", "UNDEF_17", "UNDEF_18", "UNDEF_19", "UNDEF_1A", "UNDEF_1B", "UNDEF_1C", "UNDEF_1D", "UNDEF_1E", "UNDEF_1F", "ADD ", "ADDU ", "SUB ", "SUBU ", "AND ", "OR ", "XOR ", "UNDEF_27", "SEQ ", "SNE ", "SLT ", "SGT ", "SLE ", "SGE ", "UNDEF_2E", "UNDEF_2F", "MOVI2S ", "MOVS2I ", "MOVF ", "MOVD ", "MOVFP2I ", "MOVI2FP ", "UNDEF_36", "UNDEF_37", "UNDEF_38", "UNDEF_39", "UNDEF_3A", "UNDEF_3B", "UNDEF_3C", "UNDEF_3D", "UNDEF_3E", "UNDEF_3F" ); constant fp_func_names : fp_func_name_array := ( "ADDF ", "SUBF ", "MULTF ", "DIVF ", "ADDD ", "SUBD ", "MULTD ", "DIVD ", "CVTF2D ", "CVTF2I ", "CVTD2F ", "CVTD2I ", "CVTI2F ", "CVTI2D ", "MULT ", "DIV ", "EQF ", "NEF ", "LTF ", "GTF ", "LEF ", "GEF ", "MULTU ", "DIVU ", "EQD ", "NED ", "LTD ", "GTD ", "LED ", "GED ", "UNDEF_1E", "UNDEF_1F" ); procedure disassemble ( instr : dlx_bv_word; disassembled_instr : out string; len : out positive ) is alias norm_disassembled_instr : string(1 to disassembled_instr'length) is disassembled_instr; alias instr_opcode : dlx_opcode is instr(0 to 5); alias instr_sp_func : dlx_sp_func is instr(26 to 31); alias instr_fp_func : dlx_fp_func is instr(27 to 31); alias instr_rs1 : dlx_reg_addr is instr(6 to 10); alias instr_rs2 : dlx_reg_addr is instr(11 to 15); alias instr_Itype_rd : dlx_reg_addr is instr(11 to 15); alias instr_Rtype_rd : dlx_reg_addr is instr(16 to 20); alias instr_immed16 : dlx_immed16 is instr(16 to 31); alias instr_immed26 : dlx_immed26 is instr(6 to 31); variable instr_opcode_num : dlx_opcode_num; variable instr_sp_func_num : dlx_sp_func_num; variable instr_fp_func_num : dlx_fp_func_num; variable rs1 : reg_index; variable rs2 : reg_index; variable Itype_rd : reg_index; variable Rtype_rd : reg_index; variable result : string(1 to 40) -- long enough for longest instruction := (others => ' '); variable index : positive range 1 to 41 := 1; -- position for next char in result procedure disassemble_reg ( reg : reg_index; reg_prefix : character ) is begin result(index) := reg_prefix; index := index + 1; if reg < 10 then result(index to index) := integer'image(reg); index := index + 1; else result(index to index + 1) := integer'image(reg); index := index + 2; end if; end procedure disassemble_reg; procedure disassemble_special_reg ( reg : reg_index ) is begin case reg is when 0 => result(index to index + 2) := "IAR"; index := index + 3; when 1 => result(index to index + 2) := "FSR"; index := index + 3; when others => disassemble_reg(reg, 'S'); end case; end procedure disassemble_special_reg; procedure disassemble_integer ( int : integer ) is constant int_image_length : natural := integer'image(int)'length; begin result(index to index + int_image_length - 1) := integer'image(int); index := index + int_image_length; end procedure disassemble_integer; begin instr_opcode_num := bv_to_natural(instr_opcode); instr_sp_func_num := bv_to_natural(instr_sp_func); instr_fp_func_num := bv_to_natural(instr_fp_func); rs1 := bv_to_natural(instr_rs1); rs2 := bv_to_natural(instr_rs2); Itype_rd := bv_to_natural(instr_Itype_rd); Rtype_rd := bv_to_natural(instr_Rtype_rd); if (instr_opcode /= op_special) and (instr_opcode /= op_fparith) then result(index to index + instr_name'length - 1) := opcode_names(instr_opcode_num); index := index + instr_name'length + 1; -- include space after opcode name end if; case instr_opcode is when op_special => result(index to index + instr_name'length - 1) := sp_func_names(instr_sp_func_num); index := index + instr_name'length + 1; -- include space after function name case instr_sp_func is when sp_func_nop => null; when sp_func_sll | sp_func_srl | sp_func_sra | sp_func_sequ | sp_func_sneu | sp_func_sltu | sp_func_sgtu | sp_func_sleu | sp_func_sgeu | sp_func_add | sp_func_addu | sp_func_sub | sp_func_subu | sp_func_and | sp_func_or | sp_func_xor | sp_func_seq | sp_func_sne | sp_func_slt | sp_func_sgt | sp_func_sle | sp_func_sge => disassemble_reg(Rtype_rd, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs2, 'R'); when sp_func_movi2s => disassemble_special_reg(Rtype_rd); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'R'); when sp_func_movs2i => disassemble_reg(Rtype_rd, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_special_reg(rs1); when sp_func_movf | sp_func_movd => disassemble_reg(Rtype_rd, 'F'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'F'); when sp_func_movfp2i => disassemble_reg(Rtype_rd, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'F'); when sp_func_movi2fp => disassemble_reg(Rtype_rd, 'F'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'R'); when others => null; end case; when op_fparith => result(index to index + instr_name'length - 1) := fp_func_names(instr_fp_func_num); index := index + instr_name'length + 1; -- include space after function name case instr_fp_func is when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf | fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd | fp_func_mult | fp_func_div | fp_func_multu | fp_func_divu => disassemble_reg(Rtype_rd, 'F'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'F'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs2, 'F'); when fp_func_cvtf2d | fp_func_cvtd2f => disassemble_reg(Rtype_rd, 'F'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'F'); when fp_func_cvtf2i | fp_func_cvtd2i => disassemble_reg(Rtype_rd, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'F'); when fp_func_cvti2f | fp_func_cvti2d => disassemble_reg(Rtype_rd, 'F'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'R'); when fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf | fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned | fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged => disassemble_reg(rs1, 'F'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs2, 'F'); when others => null; end case; when op_j | op_jal => disassemble_integer(bv_to_integer(instr_immed26)); when op_beqz | op_bnez => disassemble_reg(rs1, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_integer(bv_to_integer(instr_immed16)); when op_bfpt | op_bfpf => disassemble_integer(bv_to_integer(instr_immed16)); when op_slli | op_srli | op_srai => disassemble_reg(Itype_rd, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_integer(bv_to_natural(instr_immed16(11 to 15))); when op_addi | op_subi | op_seqi | op_snei | op_slti | op_sgti | op_slei | op_sgei => disassemble_reg(Itype_rd, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_integer(bv_to_integer(instr_immed16)); when op_addui | op_subui | op_andi | op_ori | op_xori | op_sequi | op_sneui | op_sltui | op_sgtui | op_sleui | op_sgeui => disassemble_reg(Itype_rd, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(rs1, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_integer(bv_to_natural(instr_immed16)); when op_lhi => disassemble_reg(Itype_rd, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_integer(bv_to_natural(instr_immed16)); when op_rfe => null; when op_trap => disassemble_integer(bv_to_natural(instr_immed26)); when op_jr | op_jalr => disassemble_reg(rs1, 'R'); when op_lb | op_lh | op_lw | op_lbu | op_lhu | op_lf | op_ld => disassemble_reg(Itype_rd, 'R'); result(index) := ','; index := index + 2; -- include space after comma disassemble_integer(bv_to_integer(instr_immed16)); result(index) := '('; index := index + 1; disassemble_reg(rs1, 'R'); result(index) := ')'; index := index + 1; when op_sb | op_sh | op_sw | op_sf | op_sd => disassemble_integer(bv_to_integer(instr_immed16)); result(index) := '('; index := index + 1; disassemble_reg(rs1, 'R'); result(index) := ')'; index := index + 1; result(index) := ','; index := index + 2; -- include space after comma disassemble_reg(Itype_rd, 'R'); when others => null; -- remaining opcodes have no operands to disassemble end case; if index > norm_disassembled_instr'length then index := norm_disassembled_instr'length; -- limit to out parameter length else index := index - 1; -- index points to last result character end if; norm_disassembled_instr(1 to index) := result(1 to index); len := index; end procedure disassemble; end package body dlx_instr;
gpl-2.0
1c69c6e606c391c530b88764fbb8a146
0.538222
3.245178
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
1
98,844
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity sum2_e is generic (k1, k2: real := 1.0); -- Gain multipliers port ( terminal in1, in2: electrical; terminal output: electrical); end entity sum2_e; architecture simple of sum2_e is QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF; QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; begin vout == k1*vin1 + k2*vin2; end architecture simple; -- library IEEE; use IEEE.MATH_REAL.all; -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.ELECTRICAL_SYSTEMS.all; entity gain_e is generic ( k: REAL := 1.0); -- Gain multiplier port ( terminal input : electrical; terminal output: electrical); end entity gain_e; architecture simple of gain_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; begin vout == k*vin; end architecture simple; -- ------------------------------------------------------------------------------- -- S-Domain Limiter Model -- ------------------------------------------------------------------------------- library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity limiter_2_e is generic ( limit_high : real := 4.8; -- upper limit limit_low : real := -4.8); -- lower limit port ( terminal input: electrical; terminal output: electrical); end entity limiter_2_e; architecture simple of limiter_2_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; constant slope : real := 1.0e-4; begin if vin > limit_high use -- Upper limit exceeded, so limit input signal vout == limit_high + slope*(vin - limit_high); elsif vin < limit_low use -- Lower limit exceeded, so limit input signal vout == limit_low + slope*(vin - limit_low); else -- No limit exceeded, so pass input signal as is vout == vin; end use; break on vin'above(limit_high), vin'above(limit_low); end architecture simple; -- ------------------------------------------------------------------------------- -- Lead-Lag Filter -- -- Transfer Function: -- -- (s + w1) -- H(s) = k * ---------- -- (s + w2) -- -- DC Gain = k*w1/w2 ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE_proposed; use IEEE_proposed.electrical_systems.all; library IEEE; use ieee.math_real.all; entity lead_lag_e is generic ( k: real := 1.0; -- Gain multiplier f1: real := 10.0; -- First break frequency (zero) f2: real := 100.0); -- Second break frequency (pole) port ( terminal input: electrical; terminal output: electrical); end entity lead_lag_e; architecture simple of lead_lag_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; quantity vin_temp : real; constant w1 : real := f1*math_2_pi; constant w2 : real := f2*math_2_pi; constant num : real_vector := (w1, 1.0); constant den : real_vector := (w2, 1.0); begin vin_temp == vin; vout == k*vin_temp'ltf(num, den); end architecture simple; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity rudder_servo is port( terminal servo_in : electrical; terminal pos_fb : electrical; terminal servo_out : electrical ); end rudder_servo; architecture rudder_servo of rudder_servo is -- Component declarations -- Signal declarations terminal error : electrical; terminal ll_in : electrical; terminal ll_out : electrical; terminal summer_fb : electrical; begin -- Signal assignments -- Component instances summer : entity work.sum2_e(simple) port map( in1 => servo_in, in2 => summer_fb, output => error ); forward_gain : entity work.gain_e(simple) generic map( k => 100.0 ) port map( input => error, output => ll_in ); fb_gain : entity work.gain_e(simple) generic map( k => -4.57 ) port map( input => pos_fb, output => summer_fb ); servo_limiter : entity work.limiter_2_e(simple) generic map( limit_high => 4.8, limit_low => -4.8 ) port map( input => ll_out, output => servo_out ); lead_lag : entity work.lead_lag_e(simple) generic map( k => 400.0, f1 => 5.0, f2 => 2000.0 ) port map( input => ll_in, output => ll_out ); end rudder_servo; -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : gear_rv_r.vhd -- Author : Mentor Graphics -- Created : 2001/10/10 -- Last update: 2019-12-30 ------------------------------------------------------------------------------- -- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains) ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/10/10 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity gear_rv_r is generic( ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1) -- Note: can be negative, if shaft polarity changes port ( terminal rotv1 : rotational_v; terminal rot2 : rotational); end entity gear_rv_r; ------------------------------------------------------------------------------- -- Ideal Architecture ------------------------------------------------------------------------------- architecture ideal of gear_rv_r is quantity w1 across torq_vel through rotv1 to rotational_v_ref; -- quantity w2 across torq2 through rotv2 to rotational_v_ref; quantity theta across torq_ang through rot2 to rotational_ref; begin -- w2 == w1*ratio; theta == ratio*w1'integ; torq_vel == -1.0*torq_ang*ratio; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------- -- Rotational to Electrical Converter -- ------------------------------------------------------------------------------- library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; use IEEE_proposed.electrical_systems.all; entity rot2v is generic ( k : real := 1.0); -- optional gain port ( terminal input : rotational; -- input terminal terminal output : electrical); -- output terminal end entity rot2v ; architecture bhv of rot2v is quantity rot_in across input to rotational_ref; -- Converter's input branch quantity v_out across out_i through output to electrical_ref;-- Converter's output branch begin -- bhv v_out == k*rot_in; end bhv; -- ------------------------------------------------------------------------------- -- Control Horn for Rudder Control (mechanical implementation) -- -- Transfer Function: -- -- tran = R*sin(rot) -- -- Where pos = output translational position, -- R = horn radius, -- theta = input rotational angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity horn_r2t is generic ( R : real := 1.0); -- horn radius port ( terminal theta : ROTATIONAL; -- input angular position port terminal pos : TRANSLATIONAL); -- output translational position port end entity horn_r2t; architecture bhv of horn_r2t is QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF; QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF; begin -- bhv tran == R*sin(rot); -- Convert angle in to translational out tran_frc == -rot_tq/R; -- Convert torque in to force out end bhv; -- ------------------------------------------------------------------------------- -- Control Horn for Rudder Control (mechanical implementation) -- -- Transfer Function: -- -- theta = arcsin(pos/R) -- -- Where pos = input translational position, -- R = horn radius, -- theta = output rotational angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity horn_t2r is generic ( R : real := 1.0); -- Rudder horn radius port ( terminal pos : translational; -- input translational position port terminal theta : rotational); -- output angular position port end entity horn_t2r ; architecture bhv of horn_t2r is QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF; QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF; begin -- bhv rot == arcsin(tran/R); -- Convert translational to angle rot_tq == -tran_frc*R; -- Convert force to torque end bhv; -- library IEEE; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity tran_linkage is port ( terminal p1, p2 : translational ); begin end tran_linkage; architecture a1 of tran_linkage is QUANTITY pos_1 across frc_1 through p1 TO translational_ref; QUANTITY pos_2 across frc_2 through p2 TO translational_ref; begin pos_2 == pos_1; -- Pass position frc_2 == -frc_1; -- Pass force end; -- ------------------------------------------------------------------------------- -- Rudder Model (Rotational Spring) -- -- Transfer Function: -- -- torq = -k*(theta - theta_0) -- -- Where theta = input rotational angle, -- torq = output rotational angle, -- theta_0 = reference angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity rudder is generic ( k : real := 1.0; -- Spring constant theta_0 : real := 0.0); port ( terminal rot : rotational); -- input rotational angle end entity rudder; architecture bhv of rudder is QUANTITY theta across torq through rot TO ROTATIONAL_REF; begin -- bhv torq == k*(theta - theta_0); -- Convert force to torque end bhv; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Constant Voltage Source (Includes Frequency Domain settings) LIBRARY IEEE; USE IEEE.MATH_REAL.ALL; -- Use proposed IEEE natures and packages LIBRARY IEEE_proposed; USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL; ENTITY v_constant IS -- Initialize parameters GENERIC ( level : VOLTAGE; -- Constant voltage value (V) ac_mag : VOLTAGE := 1.0; -- AC magnitude (V) ac_phase : real := 0.0); -- AC phase (degrees) -- Define ports as electrical terminals PORT ( TERMINAL pos, neg : ELECTRICAL); END ENTITY v_constant; -- Ideal Architecture (I = constant) ARCHITECTURE ideal OF v_constant IS -- Declare Branch Quantities QUANTITY v ACROSS i THROUGH pos TO neg; -- Declare quantity in frequency domain for AC analysis QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0; BEGIN IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE v == level; ELSE v == ac_spec; -- used for Frequency (AC) analysis END USE; END ARCHITECTURE ideal; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Electrical sinusoidal voltage source (stick.vhd) LIBRARY IEEE; USE IEEE.MATH_REAL.ALL; -- Use proposed IEEE natures and packages LIBRARY IEEE_proposed; USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL; ENTITY stick IS -- Initialize parameters GENERIC ( freq : real; -- frequency, [Hertz] amplitude : real; -- amplitude, [Volt] phase : real := 0.0; -- initial phase, [Degree] offset : real := 0.0; -- DC value, [Volt] df : real := 0.0; -- damping factor, [1/second] ac_mag : real := 1.0; -- AC magnitude, [Volt] ac_phase : real := 0.0); -- AC phase, [Degree] -- Define ports as electrical terminals PORT ( TERMINAL v_out : ELECTRICAL); END ENTITY stick; -- Ideal Architecture ARCHITECTURE ideal OF stick IS -- Declare Branch Quantities QUANTITY v ACROSS i THROUGH v_out TO electrical_ref; -- Declare Quantity for Phase in radians (calculated below) QUANTITY phase_rad : real; -- Declare Quantity in frequency domain for AC analysis QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0; BEGIN -- Convert phase to radians phase_rad == math_2_pi *(freq * NOW + phase / 360.0); IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df); ELSE v == ac_spec; -- used for Frequency (AC) analysis END USE; END ARCHITECTURE ideal; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity RF_xmtr_rcvr is generic (td : time := 0 ns); port ( tdm_in : in std_logic ; tdm_out : out std_logic ); end RF_xmtr_rcvr; architecture behavioral of RF_xmtr_rcvr is begin tdm_out <= tdm_in after td; end; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Simple Digital-Controlled Two-position Switch Model -- Switch position 1 ('0') or switch position 2 ('1') LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.math_real.all; -- Use proposed IEEE natures and packages LIBRARY IEEE_proposed; USE IEEE_proposed.electrical_systems.ALL; ENTITY switch_dig_2in is GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance r_closed : RESISTANCE := 0.001; -- Closed switch resistance trans_time : real := 0.00001); -- Transition time to each position PORT (sw_state : in std_logic; -- Digital control input TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output END ENTITY switch_dig_2in; ARCHITECTURE ideal OF switch_dig_2in IS -- CONSTANT log_r_open : real := log10(r_open); -- CONSTANT log_r_closed : real := log10(r_closed); -- SIGNAL r_sig1 : RESISTANCE := log_r_closed; -- Variable to accept switch resistance -- SIGNAL r_sig2 : RESISTANCE := log_r_open; -- Variable to accept switch resistance SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out BEGIN PROCESS (sw_state) -- Sensitivity to digital control input BEGIN IF (sw_state'event AND sw_state = '0') THEN -- Close sig1, open sig2 r_sig1 <= r_closed; r_sig2 <= r_open; ELSIF (sw_state'event AND sw_state = '1') THEN -- Open sig1, close sig2 r_sig1 <= r_open; r_sig2 <= r_closed; END IF; END PROCESS; r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity v1 == r1*i1; -- Apply Ohm's law to in1 v2 == r2*i2; -- Apply Ohm's law to in2 END ARCHITECTURE ideal; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Digital clock with 50% duty cycle LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY clock IS GENERIC ( period : time); -- Clock period PORT ( clk_out : OUT std_logic); END ENTITY clock; ARCHITECTURE ideal OF clock IS BEGIN -- clock process process begin clk_out <= '0'; wait for period/2; clk_out <= '1'; wait for period/2; end process; END ARCHITECTURE ideal; -- -- This digital clock allows user to specify the duty cycle using -- the parameters "on_time" and "off_time" library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; ENTITY clock_duty IS GENERIC ( on_time : time := 20 us; off_time : time := 19.98 ms ); PORT ( clock_out : OUT std_logic := '0'); END ENTITY clock_duty; ARCHITECTURE ideal OF clock_duty IS BEGIN -- clock process process begin clock_out <= '1'; wait for on_time; clock_out <= '0'; wait for off_time; end process; END ARCHITECTURE ideal; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity rc_clk is port( clk_100k : out std_logic; clk_6K : out std_logic; clk_50 : out std_logic ); end rc_clk; architecture rc_clk of rc_clk is -- Component declarations -- Signal declarations begin -- Signal assignments -- Component instances XCMP1 : entity work.clock(ideal) generic map( period => 10 us ) port map( CLK_OUT => clk_100k ); XCMP2 : entity work.clock(ideal) generic map( period => 150 us ) port map( CLK_OUT => clk_6K ); clk_50Hz : entity work.clock_duty(ideal) generic map( on_time => 20 us, off_time => 19.98 ms ) port map( CLOCK_OUT => clk_50 ); end rc_clk; -- -- This model counts the number of input clock transitions and outputs -- a '1' when this number equals the value of the user-defined constant 'count' library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity bit_cnt is generic ( count : integer -- User-defined value to count up to ); port ( bit_in : in std_logic ; clk : in std_logic ; dly_out : out std_logic ); end bit_cnt; architecture behavioral of bit_cnt is begin serial_clock : process is begin wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H'); FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions wait until clk'event AND (clk = '1' OR clk = 'H'); END LOOP ; dly_out <= '1'; -- After count is reached, set output high wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L'); dly_out <= '0'; -- Reset output to '0' on next clock input end process serial_clock; end; -- --////////////////////////////////////////////////////////////////// -- NOTE: This is an intermediate file for HDL inspection only. -- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach1.sdg. -- Generated by sde2hdl version 16.1.0.2 --////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; LIBRARY IEEE_proposed; USE IEEE_proposed.electrical_systems.all; USE IEEE_proposed.mechanical_systems.all; ENTITY state_mach1 IS PORT ( a2d_eoc : IN std_logic; clk_50 : IN std_logic; clk_100k : IN std_logic; clk_6k : IN std_logic; ser_done : IN std_logic; ch_sel : OUT std_logic; frm_gen : OUT std_logic; a2d_oe : OUT std_logic; a2d_start : OUT std_logic; p2s_oe : OUT std_logic; p2s_load : OUT std_logic; parity_oe : OUT std_logic; ser_cnt : OUT std_logic; p2s_clr : OUT std_logic); END state_mach1; ARCHITECTURE state_diagram OF state_mach1 IS ATTRIBUTE ENUM_TYPE_ENCODING: STRING; TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2 , load, ad_ch2, delay); SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1; SIGNAL FB_frm_gen : std_logic; SIGNAL FB_p2s_load : std_logic; SIGNAL FB_ch_sel : std_logic; BEGIN frm_gen <= FB_frm_gen ; p2s_load <= FB_p2s_load ; ch_sel <= FB_ch_sel ; sm1: PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel) BEGIN CASE CS_state_mach1_sm1 IS WHEN V_begin => FB_frm_gen <= ('1'); a2d_start <= ('0'); a2d_oe <= ('0'); FB_p2s_load <= ('0'); p2s_clr <= ('0'); p2s_oe <= ('0'); FB_ch_sel <= ('0'); parity_oe <= ('0'); ser_cnt <= ('0'); IF ((FB_frm_gen = '1')) THEN NS_state_mach1_sm1 <= frm_rd; ELSE NS_state_mach1_sm1 <= V_begin; END IF; WHEN frm_rd => FB_p2s_load <= ('1'); IF ((FB_p2s_load = '1')) THEN NS_state_mach1_sm1 <= ser_oe; ELSE NS_state_mach1_sm1 <= frm_rd; END IF; WHEN ser_oe => p2s_oe <= ('1'); FB_frm_gen <= ('0'); FB_p2s_load <= ('0'); ser_cnt <= ('1'); IF ((ser_done = '1')) THEN NS_state_mach1_sm1 <= ch1; ELSE NS_state_mach1_sm1 <= ser_oe; END IF; WHEN ch1 => p2s_oe <= ('0'); FB_ch_sel <= ('0'); a2d_start <= ('1'); ser_cnt <= ('0'); IF ((a2d_eoc = '1')) THEN NS_state_mach1_sm1 <= data_en; ELSE NS_state_mach1_sm1 <= ch1; END IF; WHEN data_en => a2d_start <= ('0'); a2d_oe <= ('1'); parity_oe <= ('1'); NS_state_mach1_sm1 <= load; WHEN tdm_oe => a2d_oe <= ('0'); parity_oe <= ('0'); p2s_oe <= ('1'); FB_p2s_load <= ('0'); ser_cnt <= ('1'); IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN NS_state_mach1_sm1 <= ch2; ELSE NS_state_mach1_sm1 <= tdm_oe; END IF; WHEN ch2 => p2s_oe <= ('0'); ser_cnt <= ('0'); FB_ch_sel <= ('1'); NS_state_mach1_sm1 <= delay; WHEN load => FB_p2s_load <= ('1'); NS_state_mach1_sm1 <= tdm_oe; WHEN ad_ch2 => a2d_start <= ('1'); IF ((a2d_eoc = '1')) THEN NS_state_mach1_sm1 <= data_en; ELSE NS_state_mach1_sm1 <= ad_ch2; END IF; WHEN delay => NS_state_mach1_sm1 <= ad_ch2; END CASE; END PROCESS; sm1_CTL: PROCESS (clk_100k, clk_50) BEGIN IF (clk_100k'event AND clk_100k='1') THEN IF (clk_50= '1' ) THEN CS_state_mach1_sm1 <= V_begin; ELSE CS_state_mach1_sm1 <= NS_state_mach1_sm1; END IF; END IF; END PROCESS; END state_diagram; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity sm_cnt is port( a2d_eoc : in std_logic; clk_50 : in std_logic; clk_100k : in std_logic; clk_6k : in std_logic; p2s_load : out std_logic; p2s_oe : out std_logic; parity_oe : out std_logic; a2d_start : out std_logic; a2d_oe : out std_logic; frm_gen : out std_logic; ch_sel : out std_logic; p2s_clr : out std_logic ); end sm_cnt; architecture sm_cnt of sm_cnt is -- Component declarations -- Signal declarations signal ser_done : std_logic; signal serial_cnt : std_logic; begin -- Signal assignments -- Component instances bit_cnt1 : entity work.bit_cnt(behavioral) generic map( count => 15 ) port map( bit_in => serial_cnt, clk => clk_6k, dly_out => ser_done ); state_mach16 : entity work.state_mach1 port map( ser_cnt => serial_cnt, ch_sel => ch_sel, frm_gen => frm_gen, a2d_oe => a2d_oe, a2d_start => a2d_start, parity_oe => parity_oe, p2s_oe => p2s_oe, p2s_load => p2s_load, p2s_clr => p2s_clr, clk_6k => clk_6k, clk_100k => clk_100k, clk_50 => clk_50, a2d_eoc => a2d_eoc, ser_done => ser_done ); end sm_cnt; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Analog to Digital Converter (Successive Aproximation Register) model with sar architecture (a2d_nbit.vhd) --DESCRIPTION: -- --This is a VHDL-AMS model of a simple analog to digital converter. The model --describes the general behavior of A/D converters for system level design and --verification. --The format of the digital output is binary coding. -- --N.B, dout(n-1) is the MSB while dout(0) is the LSB. -- -- Use IEEE natures and packages library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity a2d_nbit is generic ( Vmax: REAL := 5.0 ; -- ADC's maximum range Nbits: INTEGER := 10 ; -- number bits in ADC's output delay: TIME := 10 us -- ADC's conversion time ); port ( signal start: in std_logic ; -- Start signal signal clk: in std_logic ; -- Strobe clock signal oe: in std_logic ; -- Output enable terminal ain: ELECTRICAL ; -- ADC's analog input terminal signal eoc: out std_logic := '0' ; -- End Of Conversion pin signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal end entity a2d_nbit; architecture sar of a2d_nbit is type states is (input, convert, output) ; -- Three states of A2D Conversion constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch begin sa_adc: process variable thresh: REAL := Vmax ; -- Threshold to test input voltage against variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data variable status: states := input ; -- Begin with "input" CASE variable bit_cnt: integer := Nbits -1 ; begin CASE status is when input => -- Read input voltages when start goes high wait on start until start = '1' or start = 'H' ; thresh := Vmax ; Vtmp := Vin ; eoc <= '0' ; status := convert ; -- Go to convert state when convert => -- Begin successive approximation conversion thresh := thresh / 2.0 ; -- Get value of MSB wait on clk until clk = '1' OR clk = 'H'; if Vtmp > thresh then dtmp(bit_cnt) := '1' ; Vtmp := Vtmp - thresh ; else dtmp(bit_cnt) := '0' ; end if ; bit_cnt := bit_cnt - 1 ; if (bit_cnt + 1) < 1 then status := output ; -- Go to output state end if; when output => -- Wait for output enable, then put data on output pins eoc <= '1' after delay ; wait on oe until oe = '1' OR oe = 'H' ; FOR i in bit_range DOWNTO 0 LOOP dout(i) <= dtmp(i) ; END LOOP ; wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low FOR i in bit_range DOWNTO 0 LOOP dout <= "ZZZZZZZZZZ" ; END LOOP ; bit_cnt := bit_range ; status := input ; -- Set up for next conversion END CASE ; end process sa_adc ; Iin == 0.0 ; -- Ideal input draws no current end architecture sar ; -- -- Parallel input/serial output shift register -- With 4 trailing zeros library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity shift_reg is generic ( td : time := 0 ns); port ( bus_in : in std_logic_vector ; -- Input bus clk : in std_logic ; -- Shift clock oe : in std_logic ; -- Output enable ser_out : out std_logic := '0'; -- Output port load : in std_logic ; -- Parallel input load clr : in std_logic -- Clear register ); end entity shift_reg; architecture behavioral of shift_reg is begin control_proc : process VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input begin IF (clr = '1' OR clr = 'H') then bit_val := "000000000000"; -- Set all input bits to zero ELSE wait until load'event AND (load = '1' OR load = 'H'); FOR i IN bus_in'high DOWNTO bus_in'low LOOP bit_val(i) := bus_in(i) ; -- Transfer input data to variable END LOOP ; END IF; wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled FOR i IN bit_val'high DOWNTO bit_val'low LOOP wait until clk'event AND (clk = '1' OR clk = 'H'); ser_out <= bit_val(i) ; END LOOP ; FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros wait until clk'event AND (clk = '1' OR clk = 'H'); ser_out <= '0'; END LOOP; END process; end architecture behavioral; -- -- This model generates a 12-bit data frame synchronization code library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity frame_gen is port ( oe : in std_logic := '0'; sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ"); end entity frame_gen; architecture simple of frame_gen is begin enbl: PROCESS BEGIN WAIT ON OE; IF OE = '1' THEN sync_out <= "010101010101"; -- Sync code ELSE sync_out <= "ZZZZZZZZZZZZ"; END IF; END PROCESS; end architecture simple; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Two input XOR gate LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY xor2 IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( in1, in2 : IN std_logic; output : OUT std_logic); END ENTITY xor2; ARCHITECTURE ideal OF xor2 IS BEGIN output <= in1 XOR in2 AFTER delay; END ARCHITECTURE ideal; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- level_set_tri.vhd -- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z') -- If OE = '0' set output to high impedance LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY level_set_tri IS GENERIC ( logic_val : std_logic := 'Z'); PORT ( OE : IN std_logic; level : OUT std_logic := 'Z'); END ENTITY level_set_tri; -- Simple architecture ARCHITECTURE ideal OF level_set_tri IS BEGIN oe_ctl: PROCESS BEGIN WAIT ON OE; IF OE = '1' THEN level <= logic_val; ELSE level <= 'Z'; END IF; END PROCESS; END ARCHITECTURE ideal; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Simple Tri-state Buffer with delay time -- If OE = 1, output = input after delay -- If OE /= 1, output = Z after delay LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY buffer_tri IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( input : IN std_logic; OE : IN std_logic; output : OUT std_logic); END ENTITY buffer_tri; ARCHITECTURE ideal OF buffer_tri IS BEGIN oe_ctl: PROCESS BEGIN WAIT ON OE, input; IF OE = '1' THEN output <= input AFTER delay; ELSE output <= 'Z' AFTER delay; END IF; END PROCESS; END ARCHITECTURE ideal; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- ideal one bit D/A converter LIBRARY IEEE_proposed; USE IEEE_proposed.electrical_systems.ALL; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY d2a_bit IS GENERIC (vlow : real :=0.0; -- output high voltage vhigh : real :=5.0); -- output low voltage PORT (D : IN std_logic; -- digital (std_logic) intout TERMINAL A : electrical); -- analog (electrical) output END ENTITY d2a_bit; ARCHITECTURE ideal OF d2a_bit IS QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF; SIGNAL vin : real := 0.0; BEGIN vin <= vhigh WHEN D = '1' ELSE vlow; -- Use 'RAMP for discontinuous signal vout == vin'RAMP(1.0e-9); END ARCHITECTURE ideal; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity parity_gen is port( parity : in std_logic_vector(1 to 10); oe : in std_logic; parity_out : out std_logic_vector(0 to 11) ); end parity_gen; architecture parity_gen of parity_gen is -- Component declarations -- Signal declarations terminal par_bit_gen_a : electrical; signal XSIG010002 : std_logic; signal XSIG010003 : std_logic; signal XSIG010004 : std_logic; signal XSIG010005 : std_logic; signal XSIG010006 : std_logic; signal XSIG010007 : std_logic; signal XSIG010008 : std_logic; signal XSIG010009 : std_logic; signal XSIG010098 : std_logic; begin -- Signal assignments -- Component instances XCMP1 : entity work.xor2(ideal) port map( in1 => parity(1), in2 => parity(2), output => XSIG010002 ); XCMP2 : entity work.xor2(ideal) port map( in1 => parity(3), in2 => parity(4), output => XSIG010003 ); XCMP3 : entity work.xor2(ideal) port map( in1 => parity(5), in2 => parity(6), output => XSIG010004 ); XCMP4 : entity work.xor2(ideal) port map( in1 => parity(7), in2 => parity(8), output => XSIG010005 ); XCMP5 : entity work.xor2(ideal) port map( in1 => parity(9), in2 => parity(10), output => XSIG010008 ); XCMP6 : entity work.xor2(ideal) port map( in1 => XSIG010002, in2 => XSIG010003, output => XSIG010006 ); XCMP7 : entity work.xor2(ideal) port map( in1 => XSIG010004, in2 => XSIG010005, output => XSIG010007 ); XCMP8 : entity work.xor2(ideal) port map( in1 => XSIG010006, in2 => XSIG010007, output => XSIG010009 ); XCMP9 : entity work.xor2(ideal) port map( in1 => XSIG010009, in2 => XSIG010008, output => XSIG010098 ); XCMP18 : entity work.level_set_tri(ideal) generic map( logic_val => '1' ) port map( level => parity_out(11), oe => oe ); XCMP19 : entity work.buffer_tri(ideal) port map( input => parity(1), output => parity_out(1), oe => oe ); XCMP20 : entity work.buffer_tri(ideal) port map( input => parity(2), output => parity_out(2), oe => oe ); XCMP21 : entity work.buffer_tri(ideal) port map( input => parity(3), output => parity_out(3), oe => oe ); XCMP22 : entity work.buffer_tri(ideal) port map( input => parity(4), output => parity_out(4), oe => oe ); XCMP23 : entity work.buffer_tri(ideal) port map( input => parity(5), output => parity_out(5), oe => oe ); XCMP24 : entity work.buffer_tri(ideal) port map( input => parity(6), output => parity_out(6), oe => oe ); XCMP25 : entity work.buffer_tri(ideal) port map( input => parity(7), output => parity_out(7), oe => oe ); XCMP26 : entity work.buffer_tri(ideal) port map( input => parity(8), output => parity_out(8), oe => oe ); XCMP27 : entity work.buffer_tri(ideal) port map( input => parity(9), output => parity_out(9), oe => oe ); XCMP28 : entity work.buffer_tri(ideal) port map( input => parity(10), output => parity_out(10), oe => oe ); XCMP29 : entity work.buffer_tri(ideal) port map( input => XSIG010098, output => parity_out(0), oe => oe ); XCMP30 : entity work.d2a_bit(ideal) port map( D => XSIG010098, A => par_bit_gen_a ); end parity_gen; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity tdm_encoder is port( clk : in std_logic; p2s_oe : in std_logic; p2s_load : in std_logic; frm_gen : in std_logic; parity_oe : in std_logic; tdm_out : out std_logic; p2s_clr : in std_logic; a2d_data : in std_logic_vector(1 to 10) ); end tdm_encoder; architecture tdm_encoder of tdm_encoder is -- Component declarations -- Signal declarations signal sync_par : std_logic_vector(0 to 11); begin -- Signal assignments -- Component instances p2s1 : entity work.shift_reg(behavioral) port map( bus_in => sync_par, clk => clk, oe => p2s_oe, ser_out => tdm_out, load => p2s_load, clr => p2s_clr ); sync_gen1 : entity work.frame_gen(simple) port map( oe => frm_gen, sync_out => sync_par ); par_gen1 : entity work.parity_gen port map( parity => a2d_data, parity_out => sync_par, oe => parity_oe ); end tdm_encoder; -- -- Manchester Encoder LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY menc_rsc IS port ( dig_in : in STD_LOGIC; -- digital input clk : in STD_LOGIC; -- TX internal clock reset: in STD_LOGIC; -- not reset -- bit_out : inout real); -- real output bit_out : out std_logic); -- real output END ENTITY menc_rsc; ARCHITECTURE bhv OF menc_rsc IS -- signal bhigh:real:= 1.0; -- bit encoding -- signal blow:real:= -1.0; -- bit encoding -- signal bnormal:real:=0.0; -- bit encoding signal bit1:STD_LOGIC; signal bhigh:std_logic:= '1'; -- bit encoding signal blow:std_logic:= '0'; -- bit encoding begin -- proc1: process (dig_in, clk, bit1,bhigh,blow,bnormal) proc1: process (dig_in, clk, bit1,bhigh,blow) begin if (reset = '1') then bit1 <= '0'; else bit1 <= dig_in XOR clk; -- manchester encoding end if; if (bit1 = '1') then bit_out <= bhigh; else bit_out <= blow; -- elsif bit1 = '0' then -- bit_out <= blow; -- else -- bit_out <= bnormal; end if; end process; end architecture bhv; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity Digitize_Encode_Man is port( tdm_out : out std_logic; terminal ch1_in : electrical; terminal ch2_in : electrical ); end Digitize_Encode_Man; architecture Digitize_Encode_Man of Digitize_Encode_Man is -- Component declarations -- Signal declarations terminal a2d_ana_in : electrical; signal ch_bus : std_logic_vector(1 to 10); signal clk_6K : std_logic; signal dig_in : std_logic; signal frm_gen_ctl : std_logic; signal p2s_clr : std_logic; signal p2s_load : std_logic; signal p2s_oe : std_logic; signal par_oe : std_logic; signal reset : std_logic; signal reset_m : std_logic; signal start_a2d1 : std_logic; signal sw_ctl : std_logic; signal XSIG010091 : std_logic; signal XSIG010190 : std_logic; signal XSIG010196 : std_logic; begin -- Signal assignments -- Component instances A_SWITCH1 : entity work.switch_dig_2in(ideal) port map( p_in1 => ch1_in, p_out => a2d_ana_in, sw_state => sw_ctl, p_in2 => ch2_in ); rc_clk2 : entity work.rc_clk port map( clk_50 => reset, clk_6K => clk_6K, clk_100k => XSIG010190 ); sm_xmtr1 : entity work.sm_cnt port map( clk_100k => XSIG010190, a2d_start => start_a2d1, a2d_eoc => XSIG010091, p2s_oe => p2s_oe, p2s_load => p2s_load, ch_sel => sw_ctl, frm_gen => frm_gen_ctl, parity_oe => par_oe, a2d_oe => XSIG010196, clk_50 => reset, clk_6k => clk_6K, p2s_clr => p2s_clr ); a2d1 : entity work.a2d_nbit(sar) generic map( Vmax => 4.8 ) port map( dout => ch_bus, ain => a2d_ana_in, clk => XSIG010190, start => start_a2d1, eoc => XSIG010091, oe => XSIG010196 ); tdm_enc1 : entity work.tdm_encoder port map( clk => clk_6K, p2s_oe => p2s_oe, tdm_out => dig_in, p2s_load => p2s_load, a2d_data => ch_bus, frm_gen => frm_gen_ctl, parity_oe => par_oe, p2s_clr => p2s_clr ); menc_rsc3 : entity work.menc_rsc(bhv) port map( dig_in => dig_in, clk => clk_6K, reset => reset_m, bit_out => tdm_out ); XCMP90 : entity work.clock_duty(ideal) generic map( off_time => 19.98 sec ) port map( CLOCK_OUT => reset_m ); end Digitize_Encode_Man; -- ------------------------------------------------------------------------------- -- Second Order Lowpass filter -- -- Transfer Function: -- -- w1*w2 -- H(s) = k * ---------------- -- (s + w1)(s + w2) -- -- DC Gain = k ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE_proposed; use IEEE_proposed.electrical_systems.all; library IEEE; use ieee.math_real.all; entity lpf_2_e is generic ( k: real := 1.0; -- Gain multiplier f1: real := 10.0; -- First break frequency (pole) f2: real := 100.0); -- Second break frequency (pole) port ( terminal input: electrical; terminal output: electrical); end entity lpf_2_e; architecture simple of lpf_2_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; quantity vin_temp : real; constant w1 : real := f1*math_2_pi; constant w2 : real := f2*math_2_pi; -- constant num : real := k; constant num : real_vector := (0 => w1*w2*k); -- 0=> is needed to give -- index when only a single -- element is used. constant den : real_vector := (w1*w2, w1+w2, 1.0); begin vin_temp == vin; -- intermediate variable (vin) req'd for now vout == vin_temp'ltf(num, den); end architecture simple; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Two input AND gate LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY and2 IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( in1, in2 : IN std_logic; output : OUT std_logic); END ENTITY and2; ARCHITECTURE ideal OF and2 IS BEGIN output <= in1 AND in2 AFTER delay; END ARCHITECTURE ideal; -- -- D Flip Flop with reset (negative edge triggered) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY d_latch_n_edge_rst IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( data, clk : IN std_logic; q : OUT std_logic := '0'; qn : OUT std_logic := '1'; rst : IN std_logic := '0'); -- reset END ENTITY d_latch_n_edge_rst ; ARCHITECTURE behav OF d_latch_n_edge_rst IS BEGIN data_in : PROCESS(clk, rst) IS BEGIN IF clk = '0' AND clk'event AND rst /= '1' THEN q <= data AFTER delay; qn <= NOT data AFTER delay; ELSIF rst = '1' THEN q <= '0'; qn <= '1'; END IF; END PROCESS data_in; -- End of process data_in END ARCHITECTURE behav; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity counter_12 is port( cnt : out std_logic_vector(0 to 11); reset : in std_logic; enable : in std_logic; clk : in std_logic ); end counter_12; architecture counter_12 of counter_12 is -- Component declarations -- Signal declarations signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11); signal XSIG010078 : std_logic; signal XSIG010081 : std_logic; signal XSIG010083 : std_logic; signal XSIG010085 : std_logic; signal XSIG010087 : std_logic; signal XSIG010101 : std_logic; signal XSIG010102 : std_logic; signal XSIG010103 : std_logic; signal XSIG010104 : std_logic; signal XSIG010115 : std_logic; signal XSIG010116 : std_logic; signal XSIG010117 : std_logic; signal XSIG010132 : std_logic; begin -- Signal assignments cnt(0) <= cdb2vhdl_tmp_1(0); cnt(1) <= cdb2vhdl_tmp_1(1); cnt(2) <= cdb2vhdl_tmp_1(2); cnt(3) <= cdb2vhdl_tmp_1(3); cnt(4) <= cdb2vhdl_tmp_1(4); cnt(5) <= cdb2vhdl_tmp_1(5); cnt(6) <= cdb2vhdl_tmp_1(6); cnt(7) <= cdb2vhdl_tmp_1(7); cnt(8) <= cdb2vhdl_tmp_1(8); cnt(9) <= cdb2vhdl_tmp_1(9); cnt(10) <= cdb2vhdl_tmp_1(10); cnt(11) <= cdb2vhdl_tmp_1(11); -- Component instances XCMP92 : entity work.and2(ideal) port map( in1 => clk, in2 => enable, output => XSIG010132 ); XCMP93 : entity work.d_latch_n_edge_rst(behav) port map( CLK => XSIG010132, DATA => XSIG010078, QN => XSIG010078, Q => cdb2vhdl_tmp_1(0), RST => reset ); XCMP94 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(0), DATA => XSIG010081, QN => XSIG010081, Q => cdb2vhdl_tmp_1(1), RST => reset ); XCMP95 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(1), DATA => XSIG010083, QN => XSIG010083, Q => cdb2vhdl_tmp_1(2), RST => reset ); XCMP96 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(2), DATA => XSIG010085, QN => XSIG010085, Q => cdb2vhdl_tmp_1(3), RST => reset ); XCMP97 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(3), DATA => XSIG010087, QN => XSIG010087, Q => cdb2vhdl_tmp_1(4), RST => reset ); XCMP98 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(4), DATA => XSIG010101, QN => XSIG010101, Q => cdb2vhdl_tmp_1(5), RST => reset ); XCMP99 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(5), DATA => XSIG010102, QN => XSIG010102, Q => cdb2vhdl_tmp_1(6), RST => reset ); XCMP100 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(6), DATA => XSIG010103, QN => XSIG010103, Q => cdb2vhdl_tmp_1(7), RST => reset ); XCMP101 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(7), DATA => XSIG010104, QN => XSIG010104, Q => cdb2vhdl_tmp_1(8), RST => reset ); XCMP102 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(8), DATA => XSIG010115, QN => XSIG010115, Q => cdb2vhdl_tmp_1(9), RST => reset ); XCMP103 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(9), DATA => XSIG010116, QN => XSIG010116, Q => cdb2vhdl_tmp_1(10), RST => reset ); XCMP104 : entity work.d_latch_n_edge_rst(behav) port map( CLK => cdb2vhdl_tmp_1(10), DATA => XSIG010117, QN => XSIG010117, Q => cdb2vhdl_tmp_1(11), RST => reset ); end counter_12; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- ideal one bit A/D converter LIBRARY IEEE; USE IEEE.math_real.ALL; USE IEEE.std_logic_1164.ALL; LIBRARY IEEE_proposed; USE IEEE_proposed.electrical_systems.ALL; ENTITY a2d_bit IS GENERIC ( thres : real := 2.5); -- Threshold to determine logic output PORT ( TERMINAL a : electrical; -- analog input SIGNAL d : OUT std_logic); -- digital (std_logic) output END ENTITY a2d_bit; ARCHITECTURE ideal OF a2d_bit IS QUANTITY vin ACROSS a; BEGIN -- threshold -- Process needed to detect threshold crossing and assign output (d) PROCESS (vin'ABOVE(thres)) IS BEGIN -- PROCESS IF vin'ABOVE(thres) THEN d <= '1'; ELSE d <= '0'; END IF; END PROCESS; END ideal; -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Digital clock with 50% duty cycle and enable pin LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY clock_en IS GENERIC ( pw : time); -- Clock pulse width PORT ( enable : IN std_logic ; clock_out : INOUT std_logic := '0'); END ENTITY clock_en; ARCHITECTURE ideal OF clock_en IS BEGIN -- clock process process (clock_out, enable) is begin if clock_out = '0' AND enable = '1' THEN clock_out <= '1' after pw, '0' after 2*pw; end if; end process; END ARCHITECTURE ideal; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Inverter LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY inverter IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( input : IN std_logic; output : OUT std_logic); END ENTITY inverter; ARCHITECTURE ideal OF inverter IS BEGIN output <= NOT input AFTER delay; END ARCHITECTURE ideal; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Two input OR gate LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY or2 IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( in1, in2 : IN std_logic; output : OUT std_logic); END ENTITY or2; ARCHITECTURE ideal OF or2 IS BEGIN output <= in1 OR in2 AFTER delay; END ARCHITECTURE ideal; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; ENTITY d2a_nbit IS GENERIC ( vmax : real := 5.0; -- High output vmin : real := 0.0; -- Low output high_bit : integer := 9; -- High end of bit range for D/A low_bit : integer := 0); -- Low end of bit range for D/A PORT ( SIGNAL bus_in : IN STD_LOGIC_VECTOR; -- variable width vector input SIGNAL latch : IN STD_LOGIC; TERMINAL ana_out : electrical); -- analog output END ENTITY d2a_nbit ; ARCHITECTURE behavioral OF d2a_nbit IS SIGNAL sout : real := 0.0; QUANTITY vout across iout through ana_out TO electrical_ref; BEGIN -- ARCHITECTURE behavioral proc : PROCESS VARIABLE v_sum : real; -- Sum of voltage contribution from each bit VARIABLE delt_v : real; -- Represents the voltage value of each bit BEGIN WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high v_sum := vmin; delt_v := vmax - vmin; FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions delt_v := delt_v / 2.0; IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN v_sum := v_sum + delt_v; END IF; END LOOP; sout <= v_sum; END PROCESS; vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels END ARCHITECTURE behavioral; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity pw2ana is port( terminal ana_out : electrical; terminal pw_in : electrical ); end pw2ana; architecture pw2ana of pw2ana is -- Component declarations -- Signal declarations signal bus_servo : std_logic_vector(0 to 11); signal XSIG010008 : std_logic; signal XSIG010013 : std_logic; signal XSIG010019 : std_logic; signal XSIG010020 : std_logic; signal XSIG010021 : std_logic; signal XSIG010022 : std_logic; begin -- Signal assignments -- Component instances counter_rudder : entity work.counter_12 port map( enable => XSIG010022, cnt => bus_servo, reset => XSIG010021, clk => XSIG010008 ); XCMP3 : entity work.a2d_bit(ideal) port map( D => XSIG010022, A => pw_in ); clk_en_rudder : entity work.clock_en(ideal) generic map( pw => 500 ns ) port map( CLOCK_OUT => XSIG010008, enable => XSIG010022 ); XCMP5 : entity work.inverter(ideal) generic map( delay => 2 us ) port map( input => XSIG010022, output => XSIG010013 ); XCMP8 : entity work.inverter(ideal) generic map( delay => 2 us ) port map( input => XSIG010020, output => XSIG010021 ); XCMP9 : entity work.inverter(ideal) generic map( delay => 2 us ) port map( input => XSIG010022, output => XSIG010019 ); or_rudder : entity work.or2(ideal) port map( in1 => XSIG010022, in2 => XSIG010019, output => XSIG010020 ); XCMP11 : entity work.d2a_nbit(behavioral) generic map( vmax => 4.8, high_bit => 9, low_bit => 0 ) port map( bus_in => bus_servo, ana_out => ana_out, latch => XSIG010013 ); end pw2ana; -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : DC_Motor.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2001/06/16 ------------------------------------------------------------------------------- -- Description: Basic DC Motor ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; use IEEE_proposed.electrical_systems.all; entity DC_Motor is generic ( r_wind : resistance; -- Motor winding resistance [Ohm] kt : real; -- Torque coefficient [N*m/Amp] l : inductance; -- Winding inductance [Henrys] d : real; -- Damping coefficient [N*m/(rad/sec)] j : mmoment_i); -- Moment of inertia [kg*meter**2] port (terminal p1, p2 : electrical; terminal shaft_rotv : rotational_v); end entity DC_Motor; ------------------------------------------------------------------------------- -- Basic Architecture -- Motor equations: V = Kt*W + I*Rwind + L*dI/dt -- T = -Kt*I + D*W + J*dW/dt ------------------------------------------------------------------------------- architecture basic of DC_Motor is quantity v across i through p1 to p2; quantity w across torq through shaft_rotv to rotational_v_ref; begin torq == -1.0*kt*i + d*w + j*w'dot; v == kt*w + i*r_wind + l*i'dot; end architecture basic; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : stop_r.vhd -- Author : Mentor Graphics -- Created : 2001/10/10 -- Last update: 2001/10/10 ------------------------------------------------------------------------------- -- Description: Mechanical Hard Stop (ROTATIONAL domain) ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.MECHANICAL_SYSTEMS.all; entity stop_r is generic ( k_stop : real; -- ang_max : angle; -- ang_min : angle := 0.0; ang_max : real; ang_min : real := 0.0; damp_stop : real := 0.000000001 ); port ( terminal ang1, ang2 : rotational); end entity stop_r; architecture ideal of stop_r is quantity velocity : velocity; quantity ang across trq through ang1 to ang2; begin velocity == ang'dot; if ang'above(ang_max) use trq == k_stop * (ang - ang_max) + (damp_stop * velocity); elsif ang'above(ang_min) use trq == 0.0; else trq == k_stop * (ang - ang_min) + (damp_stop * velocity); end use; break on ang'above(ang_min), ang'above(ang_max); end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- 12-bit digital comparator model library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity dig_cmp is port ( eq : out std_logic := '0'; in1 : in std_logic_vector (0 to 11); in2 : in std_logic_vector (0 to 11); latch_in1 : in std_logic := '0'; -- Currently unused latch_in2 : in std_logic := '0'; cmp : in std_logic := '0'; clk : in std_logic ); end entity dig_cmp ; architecture simple of dig_cmp is begin compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list variable in2_hold : std_logic_vector (0 to 11) := "000000000000"; BEGIN if latch_in2 = '1' then -- in2 data is latched and stored in2_hold := in2; end if; if cmp = '1' then if in1 = in2_hold then -- latched in2 checked against current in1 eq <= '0'; else eq <= '1'; end if; end if; END PROCESS; end architecture simple; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Electrical Resistor Model -- Use proposed IEEE natures and packages LIBRARY IEEE_proposed; USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL; ENTITY resistor IS -- Initialize parameters GENERIC ( res : RESISTANCE); -- resistance (no initial value) -- Define ports as electrical terminals PORT ( TERMINAL p1, p2 : ELECTRICAL); END ENTITY resistor; -- Ideal Architecture (V = I*R) ARCHITECTURE ideal OF resistor IS -- Declare Branch Quantities QUANTITY v ACROSS i THROUGH p1 TO p2; BEGIN -- Characteristic equations v == i*res; END ARCHITECTURE ideal; -- -- Set/reset flip flop -- When S goes high, Q is set high until reset -- When R goes high, Q is set low until set library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity sr_ff is port ( S : in std_logic ; R : in std_logic ; Q : out std_logic ); end sr_ff ; architecture simple of sr_ff is begin set_reset: PROCESS(S, R) IS BEGIN -- assert S='1' nand R='1' -- Warning if both inputs are high -- report "S and R are both active. Use with caution" -- severity warning; if S'event AND S = '1' then Q <= '1'; end if; if R'event AND R = '1' then Q <= '0'; end if; END PROCESS set_reset; end; -- --////////////////////////////////////////////////////////////////// -- NOTE: This is an intermediate file for HDL inspection only. -- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach_rcvr.sdg. -- Generated by sde2hdl version 16.1.0.2 --////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; LIBRARY IEEE_proposed; USE IEEE_proposed.electrical_systems.all; USE IEEE_proposed.mechanical_systems.all; USE IEEE_proposed.fluidic_systems.all; USE IEEE_proposed.thermal_systems.all; USE IEEE_proposed.radiant_systems.all; ENTITY state_mach_rcvr IS PORT ( clk_50 : IN std_logic; clk_100k : IN std_logic; ser_done : IN std_logic; par_det : IN std_logic; frm_det : IN std_logic; clk_6k : IN std_logic; start_pulse : IN std_logic; dly_done : IN std_logic; s2p_rst : OUT std_logic; s2p_en : OUT std_logic; cnt1_en : OUT std_logic; cnt1_rst : OUT std_logic; cmp1_ltch1 : OUT std_logic; cmp1_ltch2 : OUT std_logic; cnt2_en : OUT std_logic; cnt2_rst : OUT std_logic; cmp2_ltch1 : OUT std_logic; cmp2_ltch2 : OUT std_logic; da_latch : OUT std_logic; ser_cnt : OUT std_logic; dly_cnt : OUT std_logic; par_oe : OUT std_logic); END state_mach_rcvr; ARCHITECTURE state_diagram OF state_mach_rcvr IS ATTRIBUTE ENUM_TYPE_ENCODING: STRING; TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt , s_bit, par1, par2); SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1; BEGIN sm1: PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det) BEGIN CASE CS_state_mach_rcvr_sm1 IS WHEN V_begin => cnt1_en <= ('0'); cnt1_rst <= ('1'); cmp1_ltch1 <= ('0'); cmp1_ltch2 <= ('0'); cnt2_en <= ('0'); cnt2_rst <= ('1'); cmp2_ltch1 <= ('0'); cmp2_ltch2 <= ('0'); s2p_en <= ('1'); s2p_rst <= ('0'); da_latch <= ('0'); ser_cnt <= ('0'); dly_cnt <= ('0'); par_oe <= ('0'); IF ((frm_det = '1')) THEN NS_state_mach_rcvr_sm1 <= s_bit; ELSE NS_state_mach_rcvr_sm1 <= V_begin; END IF; WHEN cnt => ser_cnt <= ('1'); cnt1_rst <= ('0'); cnt2_rst <= ('0'); IF ((ser_done = '1')) THEN NS_state_mach_rcvr_sm1 <= par1; ELSE NS_state_mach_rcvr_sm1 <= cnt; END IF; WHEN ch1 => cmp1_ltch2 <= ('1'); ser_cnt <= ('0'); dly_cnt <= ('1'); IF (((start_pulse = '1') AND (dly_done = '1'))) THEN NS_state_mach_rcvr_sm1 <= rst1; ELSE NS_state_mach_rcvr_sm1 <= ch1; END IF; WHEN rst1 => cmp1_ltch2 <= ('0'); ser_cnt <= ('1'); dly_cnt <= ('0'); par_oe <= ('0'); IF ((ser_done = '1')) THEN NS_state_mach_rcvr_sm1 <= par2; ELSE NS_state_mach_rcvr_sm1 <= rst1; END IF; WHEN ch2 => cmp2_ltch2 <= ('1'); ser_cnt <= ('0'); da_latch <= ('1'); NS_state_mach_rcvr_sm1 <= rst2; WHEN rst2 => cmp2_ltch2 <= ('0'); s2p_en <= ('0'); par_oe <= ('0'); da_latch <= ('0'); NS_state_mach_rcvr_sm1 <= cnt_cmp; WHEN cnt_cmp => cnt1_en <= ('1'); cmp1_ltch1 <= ('1'); cnt2_en <= ('1'); cmp2_ltch1 <= ('1'); NS_state_mach_rcvr_sm1 <= rst_cnt; WHEN rst_cnt => cnt1_en <= ('0'); cmp1_ltch1 <= ('0'); cnt2_en <= ('0'); cmp2_ltch1 <= ('0'); NS_state_mach_rcvr_sm1 <= rst_cnt; WHEN s_bit => IF ((start_pulse = '1')) THEN NS_state_mach_rcvr_sm1 <= cnt; ELSE NS_state_mach_rcvr_sm1 <= s_bit; END IF; WHEN par1 => par_oe <= ('1'); IF ((par_det = '0')) THEN NS_state_mach_rcvr_sm1 <= ch1; ELSIF ((par_det = '1')) THEN NS_state_mach_rcvr_sm1 <= rst1; ELSE NS_state_mach_rcvr_sm1 <= par1; END IF; WHEN par2 => par_oe <= ('1'); IF ((par_det = '0')) THEN NS_state_mach_rcvr_sm1 <= ch2; ELSIF ((par_det = '1')) THEN NS_state_mach_rcvr_sm1 <= rst2; ELSE NS_state_mach_rcvr_sm1 <= par2; END IF; END CASE; END PROCESS; sm1_CTL: PROCESS (clk_100k, clk_50) BEGIN IF (clk_100k'event AND clk_100k='1') THEN IF (clk_50= '1' ) THEN CS_state_mach_rcvr_sm1 <= V_begin; ELSE CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1; END IF; END IF; END PROCESS; END state_diagram; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity sm_cnt_rcvr is port( cmp1_ltch1 : out std_logic; cmp2_ltch1 : out std_logic; s2p_en : out std_logic; s2p_rst : out std_logic; frm_det : in std_logic; par_det : in std_logic; clk_100k : in std_logic; clk_6k : in std_logic; clk_50 : in std_logic; start_pulse : in std_logic; cnt1_en : out std_logic; cnt1_rst : out std_logic; cmp1_ltch2 : out std_logic; cnt2_en : out std_logic; cnt2_rst : out std_logic; cmp2_ltch2 : out std_logic; da_latch : out std_logic; par_oe : out std_logic ); end sm_cnt_rcvr; architecture sm_cnt_rcvr of sm_cnt_rcvr is -- Component declarations -- Signal declarations terminal dly_cnt_a : electrical; terminal dly_done_a : electrical; terminal ser_cnt_a : electrical; terminal ser_done_a : electrical; signal XSIG010001 : std_logic; signal XSIG010002 : std_logic; signal XSIG010145 : std_logic; signal XSIG010146 : std_logic; begin -- Signal assignments -- Component instances XCMP1 : entity work.d2a_bit(ideal) port map( D => XSIG010001, A => ser_cnt_a ); XCMP2 : entity work.d2a_bit(ideal) port map( D => XSIG010002, A => ser_done_a ); bit_cnt3 : entity work.bit_cnt(behavioral) generic map( count => 2 ) port map( bit_in => XSIG010145, clk => clk_6k, dly_out => XSIG010146 ); bit_cnt4 : entity work.bit_cnt(behavioral) generic map( count => 10 ) port map( bit_in => XSIG010001, clk => clk_6k, dly_out => XSIG010002 ); XCMP8 : entity work.d2a_bit(ideal) port map( D => XSIG010145, A => dly_cnt_a ); XCMP9 : entity work.d2a_bit(ideal) port map( D => XSIG010146, A => dly_done_a ); state_mach_rcvr8 : entity work.state_mach_rcvr port map( clk_100k => clk_100k, clk_50 => clk_50, s2p_rst => s2p_rst, s2p_en => s2p_en, cnt1_en => cnt1_en, cnt1_rst => cnt1_rst, cmp1_ltch1 => cmp1_ltch1, cmp1_ltch2 => cmp1_ltch2, cnt2_en => cnt2_en, cnt2_rst => cnt2_rst, cmp2_ltch1 => cmp2_ltch1, cmp2_ltch2 => cmp2_ltch2, da_latch => da_latch, ser_cnt => XSIG010001, ser_done => XSIG010002, par_det => par_det, frm_det => frm_det, clk_6k => clk_6k, start_pulse => start_pulse, dly_done => XSIG010146, dly_cnt => XSIG010145, par_oe => par_oe ); end sm_cnt_rcvr; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- level_set.vhd -- Set digital output "level" with parameter "logic_val" (default is '1') LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY level_set IS GENERIC ( logic_val : std_logic := '1'); PORT ( level : OUT std_logic); END ENTITY level_set; -- Simple architecture ARCHITECTURE ideal OF level_set IS BEGIN level <= logic_val; END ARCHITECTURE ideal; -- -- Serial to parallel data converter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity ser2par is port ( par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ"; clk : in std_logic ; load_en : in std_logic ; ser_in : in std_logic ; reset : in std_logic ); begin end ser2par; architecture a1 of ser2par is BEGIN sr_sm: PROCESS (load_en, clk, reset, ser_in) BEGIN if (reset = '1' and load_en = '1') then par_out <= "000000000000"; -- Reset the parallel data out elsif (clk'event and clk = '1') then if (load_en ='1') then -- The register will shift when load is enabled -- and will shift at rising edge of clock par_out(0) <= ser_in; -- Input data shifts into bit 0 par_out(1) <= par_out(0); par_out(2) <= par_out(1); par_out(3) <= par_out(2); par_out(4) <= par_out(3); par_out(5) <= par_out(4); par_out(6) <= par_out(5); par_out(7) <= par_out(6); par_out(8) <= par_out(7); par_out(9) <= par_out(8); par_out(10) <= par_out(9); par_out(11) <= par_out(10); else -- The otput data will not change -- if load_en is not enabled par_out <= "ZZZZZZZZZZZZ"; end if; end if; END PROCESS; end; -- -- This model ouputs a '1' when a specific bit pattern is encountered -- Otherwise, it outputs a zero library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity frame_det is port ( bus_in : in std_logic_vector (0 to 11); clk : in std_logic; frm_bit : out std_logic := '0' -- Initialize output to zero ); end entity frame_det; architecture simple of frame_det is begin enbl: PROCESS (bus_in, clk) -- Sensitivity list BEGIN if bus_in = "010101010101" then -- This is the pre-defined bit pattern if clk'event AND clk = '0' then -- Output updated synchronously frm_bit <= '1'; end if; else frm_bit <= '0'; end if; END PROCESS; end architecture simple; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity parity_det is port( bus_in : in std_logic_vector(0 to 11); par_bit : out std_logic; oe : in std_logic ); end parity_det; architecture parity_det of parity_det is -- Component declarations -- Signal declarations signal cdb2vhdl_tmp_1 : std_logic; terminal par_bit_a : electrical; signal XSIG010010 : std_logic; signal XSIG010011 : std_logic; signal XSIG010012 : std_logic; signal XSIG010013 : std_logic; signal XSIG010014 : std_logic; signal XSIG010015 : std_logic; signal XSIG010016 : std_logic; signal XSIG010017 : std_logic; signal XSIG010019 : std_logic; signal XSIG010057 : std_logic; begin -- Signal assignments par_bit <= cdb2vhdl_tmp_1; -- Component instances XCMP1 : entity work.xor2(ideal) port map( in1 => bus_in(1), in2 => bus_in(2), output => XSIG010010 ); XCMP2 : entity work.xor2(ideal) port map( in1 => bus_in(3), in2 => bus_in(4), output => XSIG010011 ); XCMP3 : entity work.xor2(ideal) port map( in1 => bus_in(5), in2 => bus_in(6), output => XSIG010012 ); XCMP4 : entity work.xor2(ideal) port map( in1 => bus_in(7), in2 => bus_in(8), output => XSIG010013 ); XCMP5 : entity work.xor2(ideal) port map( in1 => bus_in(9), in2 => bus_in(10), output => XSIG010016 ); XCMP6 : entity work.xor2(ideal) port map( in1 => XSIG010010, in2 => XSIG010011, output => XSIG010014 ); XCMP7 : entity work.xor2(ideal) port map( in1 => XSIG010012, in2 => XSIG010013, output => XSIG010015 ); XCMP8 : entity work.xor2(ideal) port map( in1 => XSIG010014, in2 => XSIG010015, output => XSIG010017 ); XCMP9 : entity work.xor2(ideal) port map( in1 => XSIG010017, in2 => XSIG010016, output => XSIG010019 ); XCMP10 : entity work.xor2(ideal) port map( in1 => XSIG010019, in2 => bus_in(0), output => XSIG010057 ); XCMP11 : entity work.d2a_bit(ideal) port map( D => cdb2vhdl_tmp_1, A => par_bit_a ); XCMP12 : entity work.and2(ideal) port map( in1 => oe, in2 => XSIG010057, output => cdb2vhdl_tmp_1 ); end parity_det; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity TDM_Demux_dbg is port( s2p_en : in std_logic; tdm_in : in std_logic; clk_6k : in std_logic; s2p_rst : in std_logic; par_det : out std_logic; frm_det : out std_logic; da_latch : in std_logic; par_oe : in std_logic; data_bus : out std_logic_vector(1 to 10); start_bit : out std_logic ); end TDM_Demux_dbg; architecture TDM_Demux_dbg of TDM_Demux_dbg is -- Component declarations -- Signal declarations terminal d2a_out : electrical; signal rcvr_bus : std_logic_vector(0 to 11); begin -- Signal assignments data_bus(1) <= rcvr_bus(1); data_bus(2) <= rcvr_bus(2); data_bus(3) <= rcvr_bus(3); data_bus(4) <= rcvr_bus(4); data_bus(5) <= rcvr_bus(5); data_bus(6) <= rcvr_bus(6); data_bus(7) <= rcvr_bus(7); data_bus(8) <= rcvr_bus(8); data_bus(9) <= rcvr_bus(9); data_bus(10) <= rcvr_bus(10); start_bit <= rcvr_bus(0); -- Component instances s2p1 : entity work.ser2par(a1) port map( par_out => rcvr_bus, clk => clk_6k, load_en => s2p_en, ser_in => tdm_in, reset => s2p_rst ); frm_det1 : entity work.frame_det(simple) port map( bus_in => rcvr_bus, frm_bit => frm_det, clk => clk_6k ); par_det1 : entity work.parity_det port map( bus_in => rcvr_bus, par_bit => par_det, oe => par_oe ); XCMP113 : entity work.d2a_nbit(behavioral) generic map( low_bit => 1, high_bit => 10, vmax => 4.8 ) port map( bus_in => rcvr_bus(1 to 10), ana_out => d2a_out, latch => da_latch ); end TDM_Demux_dbg; -- -- Manchester Decoder with clock recovery using 8x referenced clock LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mdec_rsc is -- port ( din: in real; -- real input port ( din: in std_logic; -- real input clk16x: in std_logic; -- 16x referenced clock reset: in std_logic; -- not reset bout: out std_logic := '0'; -- digital output clk_out: inout std_logic := '0'); -- recovered clock end entity mdec_rsc; architecture bhv of mdec_rsc is -- signal bhigh:real:= 1.0; -- bit decoding -- signal blow:real:= -1.0; -- bit decoding -- signal bnormal:real:=0.0; -- bit decoding signal bhigh:std_logic:= '1'; -- bit decoding signal blow:std_logic:= '0'; -- bit decoding signal bout1:std_logic; signal clk_div:std_logic_vector(3 downto 0):="0000"; -- clock counter signal trans:std_logic; -- transisition trigger begin -- bit decoding proc1: process (reset,din,clk16x) begin if (reset = '1') then bout1 <= 'X'; elsif (clk16x'event and clk16x = '1') then if (din = bhigh) then bout1 <= '1'; elsif (din = blow) then bout1 <= '0'; else bout1 <= 'X'; end if; end if; end process; -- clock counter proc2: process (reset, clk16x, clk_div) begin if (reset = '1') then clk_div <= "0000"; elsif (clk16x'event and clk16x = '1') then clk_div <= clk_div + "0001"; end if; end process; -- recovered clock -- clk_out <= not clk_div(3); clk_out <= clk_div(3); -- transition trigger trans <= ((not clk_div(3)) and (not clk_div(2)) and clk_div(1) and clk_div(0)) or (clk_div(3) and clk_div(2) and (not clk_div(1)) and (not clk_div(0))); -- Manchester decoder proc3: process (reset, trans, bout1, clk_out, clk16x) begin if (reset = '1') then bout <= '0'; elsif (clk16x'event and clk16x = '1') then if (trans = '1') then bout <= bout1 XOR clk_out; end if; end if; end process; end architecture bhv; architecture bhv_8 of mdec_rsc is -- signal bhigh:real:= 1.0; -- bit decoding -- signal blow:real:= -1.0; -- bit decoding -- signal bnormal:real:=0.0; -- bit decoding signal bhigh:std_logic:= '1'; -- bit decoding signal blow:std_logic:= '0'; -- bit decoding signal bout1:std_logic; signal clk_div:std_logic_vector(2 downto 0):="000"; -- clock counter signal trans:std_logic; -- transisition trigger begin -- bit decoding proc1: process (reset,din,clk16x) begin if (reset = '1') then bout1 <= 'X'; elsif (clk16x'event and clk16x = '1') then if (din = bhigh) then bout1 <= '1'; elsif (din = blow) then bout1 <= '0'; else bout1 <= 'X'; end if; end if; end process; -- clock counter proc2: process (reset, clk16x, clk_div) begin if (reset = '1') then clk_div <= "000"; elsif (clk16x'event and clk16x = '1') then clk_div <= clk_div + "001"; end if; end process; -- recovered clock clk_out <= not clk_div(2); -- transition trigger trans <= ((not clk_div(1)) and clk_div(0)) or (clk_div(1) and (not clk_div(0))); -- Manchester decoder proc3: process (reset, trans, bout1, clk_out, clk16x) begin if (reset = '1') then bout <= '0'; elsif (clk16x'event and clk16x = '1') then if (trans = '1') then bout <= bout1 XOR clk_out; end if; end if; end process; end architecture bhv_8; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity Decode_PW_Man is port( terminal power : electrical; terminal ch1_pw : electrical; terminal ch2_pw : electrical; bit_stream_in : in std_logic ); end Decode_PW_Man; architecture Decode_PW_Man of Decode_PW_Man is -- Component declarations -- Signal declarations signal bit_stream_in_mdec : std_logic; signal clk16x : std_logic; signal clk6k : std_logic; signal clk_100k : std_logic; signal cmp_bus : std_logic_vector(0 to 11); signal cnt1 : std_logic_vector(0 to 11); signal cnt2 : std_logic_vector(0 to 11); signal mdec_clk : std_logic; signal mdec_out : std_logic; signal reset : std_logic; signal reset_m : std_logic; signal XSIG010228 : std_logic; signal XSIG010229 : std_logic; signal XSIG010256 : std_logic; signal XSIG010263 : std_logic; signal XSIG010264 : std_logic; signal XSIG010266 : std_logic; signal XSIG010267 : std_logic; signal XSIG010268 : std_logic; signal XSIG010320 : std_logic; signal XSIG010330 : std_logic; signal XSIG010334 : std_logic; signal XSIG010339 : std_logic; signal XSIG010349 : std_logic; signal XSIG010357 : std_logic; signal XSIG010371 : std_logic; signal XSIG010372 : std_logic; signal XSIG010373 : std_logic; signal XSIG010383 : std_logic; signal XSIG010384 : std_logic; signal XSIG010385 : std_logic; signal XSIG010386 : std_logic; signal XSIG010390 : std_logic; signal XSIG010433 : std_logic; begin -- Signal assignments bit_stream_in_mdec <= bit_stream_in; -- Component instances cntr1 : entity work.counter_12 port map( enable => XSIG010384, cnt => cnt1, reset => XSIG010357, clk => XSIG010433 ); cntr2 : entity work.counter_12 port map( enable => XSIG010349, cnt => cnt2, reset => XSIG010385, clk => XSIG010320 ); cmp1 : entity work.dig_cmp(simple) port map( in1 => cnt1, eq => XSIG010371, clk => XSIG010433, in2 => cmp_bus, cmp => XSIG010384, latch_in1 => XSIG010256, latch_in2 => XSIG010383 ); cmp2 : entity work.dig_cmp(simple) port map( in1 => cnt2, eq => XSIG010372, clk => XSIG010320, in2 => cmp_bus, cmp => XSIG010349, latch_in1 => XSIG010263, latch_in2 => XSIG010264 ); XCMP109 : entity work.resistor(ideal) generic map( res => 1000000.0 ) port map( p1 => power, p2 => ELECTRICAL_REF ); clk_1M2 : entity work.clock_en(ideal) generic map( pw => 500 ns ) port map( CLOCK_OUT => XSIG010320, enable => XSIG010349 ); clk_1M1 : entity work.clock_en(ideal) generic map( pw => 500 ns ) port map( CLOCK_OUT => XSIG010433, enable => XSIG010384 ); XCMP134 : entity work.d2a_bit(ideal) port map( D => XSIG010371, A => ch1_pw ); XCMP135 : entity work.d2a_bit(ideal) port map( D => XSIG010372, A => ch2_pw ); XCMP137 : entity work.SR_FF(simple) port map( S => XSIG010330, R => XSIG010334, Q => XSIG010349 ); XCMP138 : entity work.inverter(ideal) port map( input => XSIG010372, output => XSIG010334 ); XCMP139 : entity work.SR_FF(simple) port map( S => XSIG010373, R => XSIG010339, Q => XSIG010384 ); XCMP140 : entity work.inverter(ideal) port map( input => XSIG010371, output => XSIG010339 ); rc_clk2 : entity work.rc_clk port map( clk_50 => reset, clk_6K => clk6k, clk_100k => clk_100k ); sm_rcvr1 : entity work.sm_cnt_rcvr port map( cnt1_en => XSIG010373, cmp1_ltch1 => XSIG010256, cnt2_rst => XSIG010385, clk_100k => clk_100k, cnt1_rst => XSIG010357, cnt2_en => XSIG010330, cmp2_ltch1 => XSIG010263, frm_det => XSIG010229, par_det => XSIG010228, s2p_en => XSIG010266, s2p_rst => XSIG010267, clk_6k => mdec_clk, clk_50 => reset, da_latch => XSIG010268, cmp1_ltch2 => XSIG010383, cmp2_ltch2 => XSIG010264, start_pulse => XSIG010390, par_oe => XSIG010386 ); XCMP155 : entity work.level_set(ideal) generic map( logic_val => '0' ) port map( level => cmp_bus(11) ); XCMP157 : entity work.TDM_Demux_dbg port map( data_bus => cmp_bus(0 to 9), tdm_in => mdec_out, clk_6k => mdec_clk, s2p_en => XSIG010266, s2p_rst => XSIG010267, da_latch => XSIG010268, frm_det => XSIG010229, par_det => XSIG010228, par_oe => XSIG010386, start_bit => XSIG010390 ); XCMP172 : entity work.level_set(ideal) generic map( logic_val => '1' ) port map( level => cmp_bus(10) ); clock1 : entity work.clock(ideal) generic map( period => 9.375 us ) port map( CLK_OUT => clk16x ); mdec_rsc7 : entity work.mdec_rsc(bhv) port map( din => bit_stream_in_mdec, clk16x => clk16x, reset => reset_m, bout => mdec_out, clk_out => mdec_clk ); XCMP181 : entity work.clock_duty(ideal) generic map( off_time => 19.98 sec ) port map( CLOCK_OUT => reset_m ); end Decode_PW_Man; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity tb_CS5_CC_Rudder is end tb_CS5_CC_Rudder; architecture TB_CS5_CC_Rudder of tb_CS5_CC_Rudder is -- Component declarations -- Signal declarations terminal gear_out : rotational; terminal link_in : translational; terminal link_out : translational; terminal pot_fb : electrical; signal rf_in : std_logic; signal rf_out : std_logic; terminal rudder : rotational; terminal rudder_ana : electrical; terminal rudder_cmd : electrical; terminal rudder_mtr_in : electrical; terminal rudder_mtr_out : rotational_v; terminal rudder_pw : electrical; terminal rudder_servo_in : electrical; terminal throttle_ana : electrical; terminal throttle_cmd : electrical; terminal throttle_pw : electrical; terminal XSIG010013 : electrical; begin -- Signal assignments -- Component instances rudder_servo1 : entity work.rudder_servo port map( servo_out => rudder_mtr_in, servo_in => rudder_servo_in, pos_fb => pot_fb ); gear1 : entity work.gear_rv_r(ideal) generic map( ratio => 0.01 ) port map( rotv1 => rudder_mtr_out, rot2 => gear_out ); potentiometer : entity work.rot2v(bhv) generic map( k => 1.0 ) port map( output => pot_fb, input => gear_out ); g_horn : entity work.horn_r2t(bhv) port map( theta => gear_out, pos => link_in ); r_horn : entity work.horn_t2r(bhv) port map( theta => rudder, pos => link_out ); \linkage\ : entity work.tran_linkage(a1) port map( p2 => link_out, p1 => link_in ); rudder_1 : entity work.rudder(bhv) generic map( k => 0.2 ) port map( rot => rudder ); XCMP6 : entity work.v_constant(ideal) generic map( level => 5.0 ) port map( pos => XSIG010013, neg => ELECTRICAL_REF ); t_stick : entity work.stick(ideal) generic map( offset => 2.397, phase => 0.0, amplitude => 2.397, freq => 1.0 ) port map( v_out => throttle_cmd ); r_stick : entity work.stick(ideal) generic map( freq => 1.0, amplitude => 2.397, phase => 270.0, offset => 2.397 ) port map( v_out => rudder_cmd ); RF : entity work.rf_xmtr_rcvr(behavioral) port map( tdm_in => rf_in, tdm_out => rf_out ); Digitize_Encode1 : entity work.Digitize_Encode_Man port map( ch2_in => rudder_cmd, ch1_in => throttle_cmd, tdm_out => rf_in ); filter : entity work.lpf_2_e(simple) generic map( f2 => 10.0, f1 => 10.0 ) port map( input => rudder_ana, output => rudder_servo_in ); t_pw2ana : entity work.pw2ana port map( ana_out => throttle_ana, pw_in => throttle_pw ); r_pw2ana : entity work.pw2ana port map( ana_out => rudder_ana, pw_in => rudder_pw ); motor2 : entity work.DC_Motor(basic) generic map( r_wind => 2.2, kt => 3.43e-3, l => 2.03e-3, d => 5.63e-6, j => 168.0e-9 ) port map( p1 => rudder_mtr_in, p2 => ELECTRICAL_REF, shaft_rotv => rudder_mtr_out ); stop3 : entity work.stop_r(ideal) generic map( k_stop => 1.0e6, ang_max => 1.05, ang_min => -1.05, damp_stop => 1.0e2 ) port map( ang1 => gear_out, ang2 => ROTATIONAL_REF ); Decode_PW_Man2 : entity work.Decode_PW_Man port map( bit_stream_in => rf_out, ch2_pw => rudder_pw, ch1_pw => throttle_pw, power => XSIG010013 ); end TB_CS5_CC_Rudder; --
gpl-2.0
3dd0e54a0cdd4d122d5bd54cdd49307e
0.564131
3.605208
false
false
false
false
tgingold/ghdl
testsuite/synth/mem01/tb_srom01.vhdl
1
729
entity tb_srom01 is end tb_srom01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_srom01 is signal addr : std_logic_vector(3 downto 0); signal rdat : std_logic_vector(7 downto 0); signal clk : std_logic; begin dut: entity work.srom01 port map (clk_i => clk, addr_i => addr, data_o => rdat); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin addr <= "0000"; pulse; assert rdat = x"f0" severity failure; addr <= "0001"; pulse; assert rdat = x"e1" severity failure; addr <= "0100"; pulse; assert rdat = x"b4" severity failure; wait; end process; end behav;
gpl-2.0
e15a14a91746f7b3cb01bad5e9add9f5
0.603567
3.24
false
false
false
false
nickg/nvc
test/regress/attr14.vhd
1
801
entity attr14 is end entity; architecture test of attr14 is type rec is record x : bit_vector(7 downto 0); end record; signal s : rec; signal t : bit_vector(3 downto 0); begin p1: process is begin wait for 1 ns; s.x(4) <= '1'; wait for 1 ns; s.x(4) <= '1'; wait; end process; p2: process is begin wait on s.x; assert now = 1 ns; assert s.x'event; assert s.x'last_event = 0 ns; assert s.x'last_active = 0 ns; assert s.x(4) = '1'; wait on s.x; assert s.x'active; assert not s.x'event; assert s.x'last_event = 1 ns; assert s.x'last_active = 0 ns; assert s.x(4) = '1'; wait; end process; end architecture;
gpl-3.0
ae81e6ae7d40136cd1042acd9f852d4b
0.506866
3.229839
false
false
false
false
nickg/nvc
test/regress/wait20.vhd
1
463
entity wait20 is end entity; architecture test of wait20 is signal x : bit_vector(1 to 3); begin main: process is begin x <= "010" after 2 ns, "101" after 4 ns, "111" after 6 ns; wait on x(2) for 10 ns; -- Splits the nexus assert now = 2 ns; assert x = "010"; wait for 3 ns; assert x = "101"; wait for 2 ns; assert x = "111"; wait; end process; end architecture;
gpl-3.0
f046f6d143fb098d26bccbb03bc80d53
0.531317
3.481203
false
false
false
false
tgingold/ghdl
testsuite/gna/issue708/ent.vhdl
1
510
library IEEE; use IEEE.std_logic_1164.all; entity ent is end entity; architecture a of ent is constant CHECK : natural := 4; signal last : std_logic; signal clk: std_logic; begin process(clk) variable i : natural range 0 to 127 := 0; begin if rising_edge(clk) then if (((i+1) mod CHECK = 0) xor (last = '1')) then report "Above line crashes"; end if; i := i + 1; end if; end process; end architecture;
gpl-2.0
84b3f0b165df48f3f1b2cf5f71277bcb
0.55098
3.669065
false
false
false
false
tgingold/ghdl
testsuite/synth/func02/tb_func01.vhdl
1
494
entity tb_func01 is end tb_func01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_func01 is signal a, b : std_logic_vector(7 downto 0); begin dut: entity work.func01 port map (a, b); process begin a <= x"5d"; wait for 1 ns; assert b = x"1d" severity failure; a <= x"ff"; wait for 1 ns; assert b = x"3f" severity failure; a <= x"c0"; wait for 1 ns; assert b = x"00" severity failure; wait; end process; end behav;
gpl-2.0
173648603d60d13b41fff0160c0cdab7
0.61336
2.975904
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_50M_0/sim/design_1_rst_processing_system7_0_50M_0.vhd
2
5,932
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 9 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0_9; USE proc_sys_reset_v5_0_9.proc_sys_reset; ENTITY design_1_rst_processing_system7_0_50M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END design_1_rst_processing_system7_0_50M_0; ARCHITECTURE design_1_rst_processing_system7_0_50M_0_arch OF design_1_rst_processing_system7_0_50M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END design_1_rst_processing_system7_0_50M_0_arch;
gpl-3.0
4c959fabb8425f25f4b442480fab3808
0.708699
3.564904
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_02.vhd
4
2,402
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_tb_05_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity tb_05_02 is end entity tb_05_02; architecture test of tb_05_02 is signal a1, a2, b1, b2, y : bit; begin dut : entity work.and_or_inv(primitive) port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2, y => y ); stimulus : process is subtype stim_vector_type is bit_vector(0 to 3); type stim_vector_array is array ( natural range <> ) of stim_vector_type; constant stim_vector : stim_vector_array := ( "0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111", "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111" ); begin for i in stim_vector'range loop (a1, a2, b1, b2) <= stim_vector(i); wait for 10 ns; assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1)) or (stim_vector(i)(2) and stim_vector(i)(3)) ); end loop; wait; end process stimulus; end architecture test;
gpl-2.0
af890da56753cb79469d30d35b7db1e9
0.478768
4.304659
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_timer_v2_0/hdl/src/vhdl/axi_timer.vhd
3
17,245
------------------------------------------------------------------------------- -- xps_timer - entity/architecture pair ------------------------------------------------------------------------------- -- -- *************************************************************************** -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename :axi_timer.vhd -- Company :Xilinx -- Version :v2.0 -- Description :Timer/Counter for AXI -- Standard :VHDL-93 ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_timer. -- -- axi_timer.vhd -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd -- --tc_types.vhd -- --tc_core.vhd -- --mux_onehot_f.vhd -- --family_support.vhd -- --timer_control.vhd -- --count_module.vhd -- --counter_f.vhd -- --family_support.vhd -- -- ------------------------------------------------------------------------------- -- ^^^^^^ -- Author: BSB -- History: -- BSB 03/18/2010 -- Ceated the version v1.00.a -- ^^^^^^ -- Author: BSB -- History: -- BSB 09/18/2010 -- Ceated the version v1.01.a -- -- axi lite ipif v1.01.a used -- ^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_S_AXI_DATA_WIDTH -- AXI data bus width -- C_S_AXI_ADDR_WIDTH -- AXI address bus width -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- C_COUNT_WIDTH -- Width in the bits of the counter -- C_ONE_TIMER_ONLY -- Number of the Timer -- C_TRIG0_ASSERT -- Assertion Level of captureTrig0 -- C_TRIG1_ASSERT -- Assertion Level of captureTrig1 -- C_GEN0_ASSERT -- Assertion Level for GenerateOut0 -- C_GEN1_ASSERT -- Assertion Level for GenerateOut1 ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready ------------------------------------------------------------------------------- -- timer/counter signals ------------------------------------------------------------------------------- -- capturetrig0 -- Capture Trigger 0 -- capturetrig1 -- Capture Trigger 1 -- generateout0 -- Generate Output 0 -- generateout1 -- Generate Output 1 -- pwm0 -- Pulse Width Modulation Ouput 0 -- interrupt -- Interrupt -- freeze -- Freeze count value ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library axi_timer_v2_0_10; library axi_lite_ipif_v3_0_3; library axi_lite_ipif_v3_0_3; use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce; use axi_lite_ipif_v3_0_3.ipif_pkg.SLV64_ARRAY_TYPE; use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE; ------------------------------------------------------------------------------- -- Entity declarations ------------------------------------------------------------------------------- entity axi_timer is generic ( C_FAMILY : string := "virtex7"; C_COUNT_WIDTH : integer := 32; C_ONE_TIMER_ONLY : integer := 0; C_TRIG0_ASSERT : std_logic := '1'; C_TRIG1_ASSERT : std_logic := '1'; C_GEN0_ASSERT : std_logic := '1'; C_GEN1_ASSERT : std_logic := '1'; -- axi lite ipif block generics C_S_AXI_DATA_WIDTH: integer := 32; C_S_AXI_ADDR_WIDTH: integer := 5 --5 ); port ( --Timer/Counter signals capturetrig0 : in std_logic; capturetrig1 : in std_logic; generateout0 : out std_logic; generateout1 : out std_logic; pwm0 : out std_logic; interrupt : out std_logic; freeze : in std_logic; --system signals s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic := '1'; s_axi_awaddr : in std_logic_vector(4 downto 0); --(c_s_axi_addr_width-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(31 downto 0); -- (c_s_axi_data_width-1 downto 0); s_axi_wstrb : in std_logic_vector(3 downto 0); -- ((c_s_axi_data_width/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(4 downto 0); --(c_s_axi_addr_width-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(31 downto 0); --(c_s_axi_data_width-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic ); -- Fan-out attributes for XST attribute MAX_FANOUT : string; attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; attribute MAX_FANOUT of S_AXI_ARESETN: signal is "10000"; end entity axi_timer; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture imp of axi_timer is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- constant added for webtalk information ------------------------------------------------------------------------------- --function chr(sl: std_logic) return character is -- variable c: character; -- begin -- case sl is -- when '0' => c:= '0'; -- when '1' => c:= '1'; -- when 'Z' => c:= 'Z'; -- when 'U' => c:= 'U'; -- when 'X' => c:= 'X'; -- when 'W' => c:= 'W'; -- when 'L' => c:= 'L'; -- when 'H' => c:= 'H'; -- when '-' => c:= '-'; -- end case; -- return c; -- end chr; -- --function str(slv: std_logic_vector) return string is -- variable result : string (1 to slv'length); -- variable r : integer; -- begin -- r := 1; -- for i in slv'range loop -- result(r) := chr(slv(i)); -- r := r + 1; -- end loop; -- return result; -- end str; constant ZEROES : std_logic_vector(0 to 31) := X"00000000"; constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( -- Timer registers Base Address ZEROES & X"00000000", ZEROES & X"0000001F" ); constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => 8 ); constant C_S_AXI_MIN_SIZE :std_logic_vector(31 downto 0):= X"0000001F"; constant C_USE_WSTRB :integer := 0; constant C_DPHASE_TIMEOUT :integer range 0 to 256 := 32; --Signal declaration -------------------------------- signal bus2ip_clk : std_logic; signal bus2ip_resetn : std_logic; signal bus2ip_reset : std_logic; signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) :=(others => '0'); signal ip2bus_error : std_logic := '0'; signal ip2bus_wrack : std_logic := '0'; signal ip2bus_rdack : std_logic := '0'; ----------------------------------------------------------------------- signal bus2ip_data : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); signal bus2ip_be : std_logic_vector (0 to C_S_AXI_DATA_WIDTH/8-1 ); signal bus2ip_rdce : std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1); signal bus2ip_wrce : std_logic_vector (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1); ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin -- architecture imp TC_CORE_I: entity axi_timer_v2_0_10.tc_core generic map ( C_FAMILY => C_FAMILY, C_COUNT_WIDTH => C_COUNT_WIDTH, C_ONE_TIMER_ONLY => C_ONE_TIMER_ONLY, C_DWIDTH => C_S_AXI_DATA_WIDTH, C_AWIDTH => C_S_AXI_ADDR_WIDTH, C_TRIG0_ASSERT => C_TRIG0_ASSERT, C_TRIG1_ASSERT => C_TRIG1_ASSERT, C_GEN0_ASSERT => C_GEN0_ASSERT, C_GEN1_ASSERT => C_GEN1_ASSERT, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ) port map ( -- IPIF signals Clk => bus2ip_clk, --[in] Rst => bus2ip_reset, --[in] Bus2ip_addr => bus2ip_addr, --[in] Bus2ip_be => bus2ip_be, --[in] Bus2ip_data => bus2ip_data, --[in] TC_DBus => ip2bus_data, --[out] bus2ip_rdce => bus2ip_rdce, --[in] bus2ip_wrce => bus2ip_wrce, --[in] ip2bus_rdack => ip2bus_rdack, --[out] ip2bus_wrack => ip2bus_wrack, --[out] TC_errAck => ip2bus_error, --[out] -- Timer/Counter signals CaptureTrig0 => capturetrig0, --[in] CaptureTrig1 => capturetrig1, --[in] GenerateOut0 => generateout0, --[out] GenerateOut1 => generateout1, --[out] PWM0 => pwm0, --[out] Interrupt => interrupt, --[out] Freeze => freeze --[in] ); --------------------------------------------------------------------------- -- INSTANTIATE AXI Lite IPIF --------------------------------------------------------------------------- AXI4_LITE_I : entity axi_lite_ipif_v3_0_3.axi_lite_ipif generic map ( C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IP Interconnect (IPIC) port signals ------------------------------- Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, IP2Bus_Data => ip2bus_data, IP2Bus_WrAck => ip2bus_wrack, IP2Bus_RdAck => ip2bus_rdack, IP2Bus_Error => ip2bus_error, Bus2IP_Addr => bus2ip_addr, Bus2IP_Data => bus2ip_data, Bus2IP_RNW => open, Bus2IP_BE => bus2ip_be, Bus2IP_CS => open, Bus2IP_RdCE => bus2ip_rdce, Bus2IP_WrCE => bus2ip_wrce ); bus2ip_reset <= not bus2ip_resetn; end architecture imp;
gpl-3.0
b35f9be88001b53a321896db2f74a369
0.441925
4.212262
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd
4
2,765
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- Pendulum example. Look at velocity quantity, phi_dot, to see effects of -- discontinuity. Run simulation for about 20 sec. library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; library ieee; use ieee.math_real.all; entity pendulum_wa is end entity pendulum_wa; -- ====================================================================================== -- constrained architecture -- ====================================================================================== architecture constrained of pendulum_wa is constant mass : real := 10.0; constant arm_length : real := 5.0; constant pin_angle : real := 0.25*math_pi; constant pin_distance : real := 2.5; constant damping : real := 1.0; constant gravity : real := 9.81; constant short_length : real := arm_length-pin_distance; quantity phi : real := -0.5*math_pi; signal current_length : real := arm_length; quantity acceleration, velocity : real; quantity phi_dot : real; signal pin_thresh : boolean; signal phi_dot_at_pin_thresh : real := 0.0; signal transition : boolean := false; begin if domain = quiescent_domain use phi == -0.5*math_pi; phi'dot == 0.0; elsif transition and pin_thresh use phi == pin_angle; phi'dot == phi_dot_at_pin_thresh*arm_length/short_length; elsif transition and not pin_thresh use phi == pin_angle; phi'dot == phi_dot_at_pin_thresh*short_length/arm_length; else mass*acceleration == -mass*gravity*sin(phi)-damping*velocity; velocity == current_length*phi'dot; end use; acceleration == velocity'dot; phi_dot == phi'dot; pin_thresh <= phi'above(pin_angle); process begin wait on pin_thresh; phi_dot_at_pin_thresh <= phi_dot; if pin_thresh = true then current_length <= short_length; transition <= true; else current_length <= arm_length; transition <= true; end if; wait for 1 us; transition <= false; end process; break on pin_thresh; break on transition; end architecture constrained;
gpl-2.0
a0018248f72cbf147b9f2640def28fa9
0.667269
3.558559
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd
1
1,736
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library ieee_proposed; use ieee_proposed.mechanical_systems.all; entity stop_r is generic ( k_stop : real := 1.0e6; ang_max : real := 1.05; ang_min : real := -1.05; damp_stop : real := 1.0e2 ); port ( terminal ang1, ang2 : rotational ); end entity stop_r; ---------------------------------------------------------------- architecture ideal of stop_r is quantity qvelocity : velocity; quantity ang across trq through ang1 to ang2; begin qvelocity == ang'dot; if ang > ang_max use -- Hit upper stop, generate opposing torque trq == k_stop * (ang - ang_max) + (damp_stop * qvelocity); elsif ang > ang_min use -- Between stops, no opposing torque trq == 0.0; else -- Hit lower stop, generate opposing torque trq == k_stop * (ang - ang_min) + (damp_stop * qvelocity); end use; break on ang'above(ang_min), ang'above(ang_max); end architecture ideal;
gpl-2.0
437d3e61c0a48bd5bd0db94bd66e5dc7
0.654954
3.840708
false
false
false
false
DE5Amigos/SylvesterTheDE2Bot
DE2Botv3Fall16Main/lpm_bustri_uart0.vhd
1
3,547
-- megafunction wizard: %LPM_BUSTRI% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_bustri -- ============================================================ -- File Name: lpm_bustri_uart0.vhd -- Megafunction Name(s): -- lpm_bustri -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_bustri_uart0 IS PORT ( data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); enabledt : IN STD_LOGIC ; tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END lpm_bustri_uart0; ARCHITECTURE SYN OF lpm_bustri_uart0 IS COMPONENT lpm_bustri GENERIC ( lpm_type : STRING; lpm_width : NATURAL ); PORT ( enabledt : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; BEGIN lpm_bustri_component : lpm_bustri GENERIC MAP ( lpm_type => "LPM_BUSTRI", lpm_width => 16 ) PORT MAP ( enabledt => enabledt, data => data, tridata => tridata ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: BiDir NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: nBit NUMERIC "16" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt -- Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0] -- Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0 -- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_uart0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_uart0.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_uart0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_uart0.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_uart0_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
mit
81ae757cff25bc1f3790a124aeeddccc
0.623344
3.753439
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_14.vhd
4
2,319
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_16_fg_16_14.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- -- not in book entity example_entity is end entity example_entity; -- end not in book architecture contrived of example_entity is constant sig_width : positive := 16; signal s1, s2, s3 : bit_vector (0 to sig_width - 1); signal sel : bit; -- . . . begin mux : block is generic ( width : positive ); generic map ( width => sig_width ); port ( d0, d1 : in bit_vector(0 to width - 1); y : out bit_vector(0 to width - 1); sel : in bit); port map ( d0 => s1, d1=> s2, y => s3, sel => sel ); constant zero : bit_vector(0 to width - 1) := ( others => '0' ); signal gated_d0, gated_d1 : bit_vector(0 to width - 1); begin gated_d0 <= d0 when sel = '0' else zero; gated_d1 <= d1 when sel = '1' else zero; y <= gated_d0 or gated_d1; end block mux; -- . . . -- not in book stimulus : process is begin s1 <= X"1111"; s2 <= X"2222"; sel <= '0'; wait for 10 ns; s1 <= X"0101"; wait for 10 ns; s2 <= X"0202"; wait for 10 ns; sel <= '1'; wait for 10 ns; s1 <= X"0001"; wait for 10 ns; s2 <= X"0002"; wait for 10 ns; wait; end process stimulus; -- end not in book end architecture contrived;
gpl-2.0
feac76505da3391250bb40d50088364d
0.567055
3.61215
false
false
false
false
nickg/nvc
test/parse/uvvm1.vhd
1
1,488
-- From UVVM ti_vvc_framework_support_pkg.vhd -- License: Apache 2.0 -- package uvvm1 is type unsigned is array (natural range <>) of bit; type t_direction is (TRANSMIT, RECEIVE); type t_dut_if_field_config is record dut_address : unsigned; -- Address of the DUT IF field dut_address_increment : integer; -- Incrementation of the address on each access data_width : positive; -- Width of the data per transfer use_field : boolean; -- Used by the HVVC to send/request fields to/from the bridge or ignore them when not applicable field_description : string; -- Description of the DUT IF field end record; constant C_DUT_IF_FIELD_CONFIG_DEFAULT : t_dut_if_field_config(dut_address(0 downto 0)) := ( dut_address => (others => '0'), dut_address_increment => 0, data_width => 8, use_field => true, field_description => "default"); type t_dut_if_field_config_array is array (natural range <>) of t_dut_if_field_config; type t_dut_if_field_config_direction_array is array (t_direction range <>) of t_dut_if_field_config_array; constant C_DUT_IF_FIELD_CONFIG_DIRECTION_ARRAY_DEFAULT : t_dut_if_field_config_direction_array(t_direction'low to t_direction'high)(0 to 0)(dut_address(0 downto 0), field_description(1 to 7)) -- OK := (others => (others => C_DUT_IF_FIELD_CONFIG_DEFAULT)); end package;
gpl-3.0
c63c14265351fa76b7a6ca72bd6008ef
0.634409
3.647059
false
true
false
false
tgingold/ghdl
testsuite/synth/synth87/tb_repro01.vhdl
1
677
entity tb_repro01 is end tb_repro01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_repro01 is signal a : std_logic; signal b : std_logic; signal c : std_logic; signal z : std_logic; begin dut: entity work.repro01 port map (a, b, c, z); process constant av : std_logic_vector := b"1101"; constant bv : std_logic_vector := b"0111"; constant cv : std_logic_vector := b"0011"; constant zv : std_logic_vector := b"0111"; begin for i in av'range loop a <= av (i); b <= bv (i); c <= cv (i); wait for 1 ns; assert z = zv(i) severity failure; end loop; wait; end process; end behav;
gpl-2.0
4c79f79a208d4233dd82275c41b877f4
0.604136
3.134259
false
false
false
false
nickg/nvc
test/regress/genpack1.vhd
1
1,296
package myfixed is generic ( whole : natural; frac : natural ); constant width : natural := whole + frac; type fixed_t is array (1 to width) of bit; function "+"(x, y : fixed_t) return fixed_t; function total_bits return natural; end package; package body myfixed is function total_bits return natural is begin return whole + frac; end function; function "+"(x, y : fixed_t) return fixed_t is variable result : fixed_t; begin for i in 1 to width loop result(i) := x(i) or y(i); end loop; return result; end function; end package body; ------------------------------------------------------------------------------- entity genpack1 is end entity; architecture test of genpack1 is package myfixed_2_4 is new work.myfixed generic map (2, 4); use myfixed_2_4.all; constant c : natural := myfixed_2_4.width; constant d : myfixed_2_4.fixed_t := (others => '0'); begin p1: process is variable v : myfixed_2_4.fixed_t; begin assert c = 6; assert myfixed_2_4.total_bits = 6; v := "110000"; v := v + d; assert v = "110000"; assert whole = 2; assert frac = 4; wait; end process; end architecture;
gpl-3.0
8b90f3026c4afe2010a441bb7ba6c86e
0.549383
3.868657
false
false
false
false
nickg/nvc
test/sem/ambiguous.vhd
1
5,411
entity e is end entity; architecture a of e is type foo is (a, b, c); type bar is (a, b, c); signal x : foo := a; signal y : bar := b; begin process is begin x <= c; y <= a; end process; process is begin x <= foo'(a); y <= bar'(a); end process; p3: process is type baz is (a, b, c, d); variable z : baz := b; begin z := d; -- OK z := a; -- OK x <= a; -- OK end process; process is begin x <= bar'(c); -- Error! end process; process is type small is range 10 downto -5; variable z : small := -5; variable a : boolean; begin a := z = -5; -- OK a := -5 = z; -- OK end process; process is variable a : bit_vector(3 downto 0); variable x : character; variable b : boolean; begin b := x = '1'; -- OK b := '1' = x; -- OK b := a = ('0', '1', '0', '1'); -- OK b := ('0', '1', '0', '1') = a; -- OK b := ('0', '1') = ('0', '1'); -- Error end process; process is subtype some_foo is foo range a to b; -- OK subtype less_foo is some_foo range a to a; subtype all_foo is foo; variable f : some_foo; variable g : all_foo; variable h : less_foo; begin f := a; -- OK f := c; -- OK at semantic check g := f; -- OK g := h; -- OK end process; process is type weird is ( '¢', '¦' ); variable x : weird; variable y : character; begin x := '¢'; -- OK y := '¢'; -- OK report "foo¥bar"; -- OK end process; process is type t is (false, true); begin for i in false to false loop -- Error end loop; end process; process is function now return integer; begin for i in now to now loop -- Error end loop; end process; process is function false return integer is begin return 1; end function; begin for i in false to false loop -- Error end loop; end process; process is function "="(a, b : foo) return boolean is begin return false; end function; variable x, y : foo; begin assert x = y; -- OK end process; end architecture; package pack is type my_int is range 1 to 10; end package; use work.pack.all; package pack2 is function "<"(a, b: my_int) return boolean; end package; use work.pack2.all; use work.pack.all; architecture a2 of e is function ">"(a, b: my_int) return boolean; begin process is variable x, y : my_int; begin assert x > y; -- OK assert x < y; -- Error end process; process is function uniform (a, b : real) return real; type disttype is (none, uniform, other); variable v : disttype; variable r : real; begin case v is when none | uniform => r := uniform(1.0, 2.0); -- OK when others => r := 0.0; end case; end process; end architecture; architecture a3 of e is type unsigned is array (natural range <>) of bit; function "*"(a, b : unsigned) return bit_vector; function "*"(a, b : bit_vector) return bit_vector; function "*"(a, b : unsigned) return unsigned; function "+"(a, b : unsigned) return bit_vector; function "+"(a, b : bit_vector) return bit_vector; function "+"(a, b : unsigned) return unsigned; signal x, y, z : bit_vector(7 downto 0); begin x <= unsigned(y) * unsigned(z) + unsigned(z); end architecture; -- Test case reduced from Altera model architecture a4 of e is function resolved (x : bit_vector) return bit; subtype rbit is resolved bit; type rbit_vector is array (natural range <>) of rbit; function "and" (x, y : rbit_vector) return rbit_vector; signal mdio_wr : rbit; signal reg_addr : rbit_vector(15 downto 0); begin process is begin assert ((X"0000" & mdio_wr) and reg_addr) /= X"0000"; end process; end architecture; architecture issue61 of e is type ubit_vector is array (natural range <>) of bit; begin process is variable x: bit_vector(4 downto 0); variable y: ubit_vector(6 downto 0); begin y := ubit_vector(x & ('0' & '1')); y := ubit_vector((x & '0') & '1'); y := ubit_vector(x & '0' & '1'); wait; end process; end architecture; architecture cassign of e is function "="(x, y : bit) return bit; signal x, y, z : bit; begin x <= '1' when y = z else '0'; -- OK end architecture; architecture expect_fail of e is type t is (C, B, A); type t_vec is array (1 to 2) of t; -- Type of aggregate must be determinable from the context constant x : boolean := (A, A) < (C, C); -- Error begin end architecture; -- -*- coding: latin-1; -*-
gpl-3.0
09ee2d74f2340ca9e23d17ff51462d49
0.48808
3.829441
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
1
35,277
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity sum2_e is generic (k1, k2: real := 1.0); -- Gain multipliers port ( terminal in1, in2: electrical; terminal output: electrical); end entity sum2_e; architecture simple of sum2_e is QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF; QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; begin vout == k1*vin1 + k2*vin2; end architecture simple; -- library IEEE; use IEEE.MATH_REAL.all; -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.ELECTRICAL_SYSTEMS.all; entity gain_e is generic ( k: REAL := 1.0); -- Gain multiplier port ( terminal input : electrical; terminal output: electrical); end entity gain_e; architecture simple of gain_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; begin vout == k*vin; end architecture simple; -- ------------------------------------------------------------------------------- -- S-Domain Limiter Model -- ------------------------------------------------------------------------------- library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity limiter_2_e is generic ( limit_high : real := 4.8; -- upper limit limit_low : real := -4.8); -- lower limit port ( terminal input: electrical; terminal output: electrical); end entity limiter_2_e; architecture simple of limiter_2_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; constant slope : real := 1.0e-4; begin if vin > limit_high use -- Upper limit exceeded, so limit input signal vout == limit_high + slope*(vin - limit_high); elsif vin < limit_low use -- Lower limit exceeded, so limit input signal vout == limit_low + slope*(vin - limit_low); else -- No limit exceeded, so pass input signal as is vout == vin; end use; break on vin'above(limit_high), vin'above(limit_low); end architecture simple; -- ------------------------------------------------------------------------------- -- Lead-Lag Filter -- -- Transfer Function: -- -- (s + w1) -- H(s) = k * ---------- -- (s + w2) -- -- DC Gain = k*w1/w2 ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE_proposed; use IEEE_proposed.electrical_systems.all; library IEEE; use ieee.math_real.all; entity lead_lag_e is generic ( k: real := 1.0; -- Gain multiplier f1: real := 10.0; -- First break frequency (zero) f2: real := 100.0); -- Second break frequency (pole) port ( terminal input: electrical; terminal output: electrical); end entity lead_lag_e; architecture simple of lead_lag_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; quantity vin_temp : real; constant w1 : real := f1*math_2_pi; constant w2 : real := f2*math_2_pi; constant num : real_vector := (w1, 1.0); constant den : real_vector := (w2, 1.0); begin vin_temp == vin; vout == k*vin_temp'ltf(num, den); end architecture simple; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity rudder_servo is port( terminal servo_in : electrical; terminal pos_fb : electrical; terminal servo_out : electrical ); end rudder_servo; architecture rudder_servo of rudder_servo is -- Component declarations -- Signal declarations terminal error : electrical; terminal ll_in : electrical; terminal ll_out : electrical; terminal summer_fb : electrical; begin -- Signal assignments -- Component instances summer : entity work.sum2_e(simple) port map( in1 => servo_in, in2 => summer_fb, output => error ); forward_gain : entity work.gain_e(simple) generic map( k => 100.0 ) port map( input => error, output => ll_in ); fb_gain : entity work.gain_e(simple) generic map( k => -4.57 ) port map( input => pos_fb, output => summer_fb ); XCMP21 : entity work.limiter_2_e(simple) generic map( limit_high => 4.8, limit_low => -4.8 ) port map( input => ll_out, output => servo_out ); XCMP22 : entity work.lead_lag_e(simple) generic map( f2 => 2000.0, f1 => 5.0, k => 400.0 ) port map( input => ll_in, output => ll_out ); end rudder_servo; -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : gear_rv_r.vhd -- Author : Mentor Graphics -- Created : 2001/10/10 -- Last update: 2019-12-30 ------------------------------------------------------------------------------- -- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains) ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/10/10 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity gear_rv_r is generic( ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1) -- Note: can be negative, if shaft polarity changes port ( terminal rotv1 : rotational_v; terminal rot2 : rotational); end entity gear_rv_r; ------------------------------------------------------------------------------- -- Ideal Architecture ------------------------------------------------------------------------------- architecture ideal of gear_rv_r is quantity w1 across torq_vel through rotv1 to rotational_v_ref; -- quantity w2 across torq2 through rotv2 to rotational_v_ref; quantity theta across torq_ang through rot2 to rotational_ref; begin -- w2 == w1*ratio; theta == ratio*w1'integ; torq_vel == -1.0*torq_ang*ratio; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------- -- Rotational to Electrical Converter -- ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; use IEEE_proposed.electrical_systems.all; entity rot2v is generic ( k : real := 1.0); -- optional gain port ( terminal input : rotational; -- input terminal terminal output : electrical); -- output terminal end entity rot2v ; architecture bhv of rot2v is quantity rot_in across input to rotational_ref; -- Converter's input branch quantity v_out across out_i through output to electrical_ref;-- Converter's output branch begin -- bhv v_out == k*rot_in; end bhv; -- ------------------------------------------------------------------------------- -- Control Horn for Rudder Control (mechanical implementation) -- -- Transfer Function: -- -- tran = R*sin(rot) -- -- Where pos = output translational position, -- R = horn radius, -- theta = input rotational angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity horn_r2t is generic ( R : real := 1.0); -- horn radius port ( terminal theta : ROTATIONAL; -- input angular position port terminal pos : TRANSLATIONAL); -- output translational position port end entity horn_r2t; architecture bhv of horn_r2t is QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF; QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF; begin -- bhv tran == R*sin(rot); -- Convert angle in to translational out tran_frc == -rot_tq/R; -- Convert torque in to force out end bhv; -- ------------------------------------------------------------------------------- -- Control Horn for Rudder Control (mechanical implementation) -- -- Transfer Function: -- -- theta = arcsin(pos/R) -- -- Where pos = input translational position, -- R = horn radius, -- theta = output rotational angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity horn_t2r is generic ( R : real := 1.0); -- Rudder horn radius port ( terminal pos : translational; -- input translational position port terminal theta : rotational); -- output angular position port end entity horn_t2r ; architecture bhv of horn_t2r is QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF; QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF; begin -- bhv rot == arcsin(tran/R); -- Convert translational to angle rot_tq == -tran_frc*R; -- Convert force to torque end bhv; -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : DC_Motor.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2001/06/16 ------------------------------------------------------------------------------- -- Description: Basic DC Motor ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; use IEEE_proposed.electrical_systems.all; entity DC_Motor is generic ( r_wind : resistance; -- Motor winding resistance [Ohm] kt : real; -- Torque coefficient [N*m/Amp] l : inductance; -- Winding inductance [Henrys] d : real; -- Damping coefficient [N*m/(rad/sec)] j : mmoment_i); -- Moment of inertia [kg*meter**2] port (terminal p1, p2 : electrical; terminal shaft_rotv : rotational_v); end entity DC_Motor; ------------------------------------------------------------------------------- -- Basic Architecture -- Motor equations: V = Kt*W + I*Rwind + L*dI/dt -- T = -Kt*I + D*W + J*dW/dt ------------------------------------------------------------------------------- architecture basic of DC_Motor is quantity v across i through p1 to p2; quantity w across torq through shaft_rotv to rotational_v_ref; begin torq == -1.0*kt*i + d*w + j*w'dot; v == kt*w + i*r_wind + l*i'dot; end architecture basic; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : stop_r.vhd -- Author : Mentor Graphics -- Created : 2001/10/10 -- Last update: 2001/10/10 ------------------------------------------------------------------------------- -- Description: Mechanical Hard Stop (ROTATIONAL domain) ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.MECHANICAL_SYSTEMS.all; entity stop_r is generic ( k_stop : real; -- ang_max : angle; -- ang_min : angle := 0.0; ang_max : real; ang_min : real := 0.0; damp_stop : real := 0.000000001 ); port ( terminal ang1, ang2 : rotational); end entity stop_r; architecture ideal of stop_r is quantity velocity : velocity; quantity ang across trq through ang1 to ang2; begin velocity == ang'dot; if ang'above(ang_max) use trq == k_stop * (ang - ang_max) + (damp_stop * velocity); elsif ang'above(ang_min) use trq == 0.0; else trq == k_stop * (ang - ang_min) + (damp_stop * velocity); end use; break on ang'above(ang_min), ang'above(ang_max); end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- library IEEE; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity tran_linkage is port ( terminal p1, p2 : translational ); begin end tran_linkage; architecture a1 of tran_linkage is QUANTITY pos_1 across frc_1 through p1 TO translational_ref; QUANTITY pos_2 across frc_2 through p2 TO translational_ref; begin pos_2 == pos_1; -- Pass position frc_2 == -frc_1; -- Pass force end; -- ------------------------------------------------------------------------------- -- Rudder Model (Rotational Spring) -- -- Transfer Function: -- -- torq = -k*(theta - theta_0) -- -- Where theta = input rotational angle, -- torq = output rotational angle, -- theta_0 = reference angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity rudder is generic ( k : real := 1.0; -- Spring constant theta_0 : real := 0.0); port ( terminal rot : rotational); -- input rotational angle end entity rudder; architecture bhv of rudder is QUANTITY theta across torq through rot TO ROTATIONAL_REF; begin -- bhv torq == k*(theta - theta_0); -- Convert force to torque end bhv; -- -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Electrical Resistor Model -- Use proposed IEEE natures and packages LIBRARY IEEE_proposed; USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL; ENTITY resistor IS -- Initialize parameters GENERIC ( res : RESISTANCE); -- resistance (no initial value) -- Define ports as electrical terminals PORT ( TERMINAL p1, p2 : ELECTRICAL); END ENTITY resistor; -- Ideal Architecture (V = I*R) ARCHITECTURE ideal OF resistor IS -- Declare Branch Quantities QUANTITY v ACROSS i THROUGH p1 TO p2; BEGIN -- Characteristic equations v == i*res; END ARCHITECTURE ideal; -- library ieee_proposed; use ieee_proposed.electrical_systems.all; entity amp_lim is port (terminal ps : electrical; -- positive supply terminal terminal input, output : electrical); end entity amp_lim; architecture simple of amp_lim is quantity v_pwr across i_pwr through ps to electrical_ref; quantity vin across iin through input to electrical_ref; quantity vout across iout through output to electrical_ref; quantity v_amplified : voltage ; constant gain : real := 1.0; begin v_amplified == gain*vin; if v_amplified > v_pwr use vout == v_pwr; else vout == v_amplified; end use; -- ignore loading effects i_pwr == 0.0; iin == 0.0; end architecture simple; -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : v_pulse.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2001/07/09 ------------------------------------------------------------------------------- -- Description: Voltage Pulse Source -- Includes Frequency Domain settings ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created -- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type -- time. Uses time2real function. -- Pulsewidth no longer includes -- rise and fall times. ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity v_pulse is generic ( initial : voltage := 0.0; -- initial value [Volts] pulse : voltage; -- pulsed value [Volts] ti2p : time := 1 ns; -- initial to pulse [Sec] tp2i : time := 1 ns; -- pulse to initial [Sec] delay : time := 0 ms; -- delay time [Sec] width : time; -- duration of pulse [Sec] period : time; -- period [Sec] ac_mag : voltage := 1.0; -- AC magnitude [Volts] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical); end entity v_pulse; ------------------------------------------------------------------------------- -- Ideal Architecture ------------------------------------------------------------------------------- architecture ideal of v_pulse is -- Declare Through and Across Branch Quantities quantity v across i through pos to neg; -- Declare quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; -- Signal used in CreateEvent process below signal pulse_signal : voltage := initial; -- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute) -- Note: these lines gave an error during simulation. Had to use a -- function call instead. -- constant ri2p : real := time'pos(ti2p) * 1.0e-15; -- constant rp2i : real := time'pos(tp2i) * 1.0e-15; -- Function to convert numbers of type TIME to type REAL function time2real(tt : time) return real is begin return time'pos(tt) * 1.0e-15; end time2real; -- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute) constant ri2p : real := time2real(ti2p); constant rp2i : real := time2real(tp2i); begin if domain = quiescent_domain or domain = time_domain use v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions else v == ac_spec; -- used for Frequency (AC) analysis end use; -- purpose: Create events to define pulse shape -- type : combinational -- inputs : -- outputs: pulse_signal CreateEvent : process begin wait for delay; loop pulse_signal <= pulse; wait for (width + ti2p); pulse_signal <= initial; wait for (period - width - ti2p); end loop; end process CreateEvent; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- library ieee; use ieee.math_real.all; package pwl_full_functions is function next_increment(x : in real; xdata : in real_vector ) return real; function interpolate (x,y2,y1,x2,x1 : in real) return real; function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector ) return real; end package pwl_full_functions; package body pwl_full_functions is function next_increment(x : in real; xdata : in real_vector) return real is variable i : integer; begin i := 0; while i <= xdata'right loop if x >= xdata(i) - 6.0e-15 then -- The value 6.0e-15 envelopes round-off error -- of real-to-time conversion in calling model i := i + 1; else return xdata(i) - xdata(i - 1); end if; end loop; return 1.0; -- Returns a "large number" relative to expected High-Speed time scale end function next_increment; function interpolate (x,y2,y1,x2,x1 : in real) return real is variable m, yvalue : real; begin assert (x1 /= x2) report "interpolate: x1 cannot be equal to x2" severity error; assert (x >= x1) and (x <= x2) report "interpolate: x must be between x1 and x2, inclusively " severity error; m := (y2 - y1)/(x2 - x1); yvalue := y1 + m*(x - x1); return yvalue; end function interpolate; -- Created a new pwl_dim1_flat function that returns a constant -- value of ydata(0) if x < xdata(0), or ydata(ydata'right) if x > xdata(xdata'right) function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector ) return real is variable xvalue, yvalue, m : real; variable start, fin, mid: integer; begin if x >= xdata(xdata'right) then yvalue := ydata(ydata'right); return yvalue; end if; if x <= xdata(0) then yvalue := ydata(0); return yvalue; end if; start:=0; fin:=xdata'right; -- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive. -- so fin==n-1 in C terms (where n is the size of the array). while start <=fin loop mid:=(start+fin)/2; if xdata(mid) < x then start:=mid+1; else fin:=mid-1; end if; end loop; if xdata(mid) > x then mid:=mid-1; end if; yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid)); return yvalue; end function pwl_dim1_flat; end package body pwl_full_functions; -- Not sure the sync_tdata process is necessary. Requires the tdata set contain -- a larger value than the actual simulation time. -- Piece-wise linear voltage source model library IEEE; use IEEE.std_logic_1164.all; Library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use work.pwl_full_functions.all; entity v_pwl_full is generic ( vdata : real_vector; -- v-pulse data tdata : real_vector -- time-data for v-pulse ); port ( terminal pos, neg : electrical ); end entity v_pwl_full; architecture ideal of v_pwl_full is QUANTITY v across i through pos TO neg; signal tick : std_logic := '0'; -- Sync signal for tdata "tracking" begin sync_tdata: process is variable next_tick_delay : real := 0.0; -- Time increment to the next time-point in tdata begin wait until domain = time_domain; loop next_tick_delay := next_increment(NOW,tdata); tick <= (not tick) after (integer(next_tick_delay * 1.0e15) * 1 fs); wait on tick; end loop; end process sync_tdata; break on tick; -- Forces analog solution point at all tdata time-points v == pwl_dim1_flat(NOW, tdata, vdata); end architecture ideal; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; use IEEE_proposed.fluidic_systems.all; use IEEE_proposed.thermal_systems.all; use IEEE_proposed.radiant_systems.all; entity tb_CS5_Amp_Lim is end tb_CS5_Amp_Lim; architecture TB_CS5_Amp_Lim of tb_CS5_Amp_Lim is -- Component declarations -- Signal declarations terminal amp_in : electrical; terminal gear_out : rotational; terminal link_in : translational; terminal link_out : translational; terminal mot_in : electrical; terminal mot_out : rotational_v; terminal pos_fb_v : electrical; terminal power : electrical; terminal rudder_in : rotational; terminal src_in : electrical; terminal XSIG010068 : electrical; begin -- Signal assignments -- Component instances rudder_servo1 : entity work.rudder_servo port map( servo_out => amp_in, servo_in => src_in, pos_fb => pos_fb_v ); gear3 : entity work.gear_rv_r(ideal) generic map( ratio => 0.01 ) port map( rotv1 => mot_out, rot2 => gear_out ); r2v : entity work.rot2v(bhv) generic map( k => 1.0 ) port map( output => pos_fb_v, input => gear_out ); r2t : entity work.horn_r2t(bhv) port map( theta => gear_out, pos => link_in ); t2r : entity work.horn_t2r(bhv) port map( theta => rudder_in, pos => link_out ); motor1 : entity work.DC_Motor(basic) generic map( j => 168.0e-9, d => 5.63e-6, l => 2.03e-3, kt => 3.43e-3, r_wind => 2.2 ) port map( p1 => mot_in, p2 => ELECTRICAL_REF, shaft_rotv => mot_out ); stop1 : entity work.stop_r(ideal) generic map( ang_min => -1.05, ang_max => 1.05, k_stop => 1.0e6, damp_stop => 1.0e2 ) port map( ang1 => gear_out, ang2 => ROTATIONAL_REF ); XCMP35 : entity work.tran_linkage(a1) port map( p2 => link_out, p1 => link_in ); XCMP36 : entity work.rudder(bhv) generic map( k => 0.2 ) port map( rot => rudder_in ); R2w : entity work.resistor(ideal) generic map( res => 1000.0 ) port map( p1 => XSIG010068, p2 => ELECTRICAL_REF ); XCMP55 : entity work.amp_lim(simple) port map( input => amp_in, output => mot_in, ps => power ); v9 : entity work.v_pulse(ideal) generic map( initial => 0.0, pulse => 4.8, ti2p => 300 ms, tp2i => 300 ms, delay => 100 ms, width => 5 ms, period => 605 ms ) port map( pos => src_in, neg => ELECTRICAL_REF ); XCMP57 : entity work.v_pwl_full(ideal) generic map( tdata => (0.0,100.0e-3,400.0e-3,900.0e-3,1300.0e-3,1800.0e-3,2300.0e-3,2600.0e-3, 2900.0e-3), vdata => (0.0,0.0,2.4,2.4,4.7,4.7,1.0,1.0,0.0) ) port map( pos => XSIG010068, neg => ELECTRICAL_REF ); XCMP60 : entity work.v_pwl_full(ideal) generic map( vdata => (4.8,4.8,4.4,4.4,4.0,4.0,3.6,3.6,3.2,3.2), tdata => (0.0,705.0e-3,706.0e-3,1310.0e-3,1320.0e-3,1915.0e-3,1925.0e-3,2520.0e-3,2530.0e-3,3125.0e-3) ) port map( pos => power, neg => ELECTRICAL_REF ); end TB_CS5_Amp_Lim; --
gpl-2.0
a6ac06be0b93709f7e2891bf3d6750d9
0.576693
4.113936
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd
4
3,287
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity bus_monitor is end entity bus_monitor; architecture test of bus_monitor is subtype byte is bit_vector(7 downto 0); type byte_array is array (natural range <>) of byte; function resolve_bytes ( drivers : in byte_array ) return byte is begin return drivers(drivers'left); end function resolve_bytes; function resolve_bits ( drivers : in bit_vector ) return bit is begin return drivers(drivers'left); end function resolve_bits; -- code from book (in text) signal address : bit_vector(15 downto 0); signal data : resolve_bytes byte; signal rd, wr, io : bit; -- read, write, io/mem select signal ready : resolve_bits bit; -- end code from book begin -- code from book bus_monitor : process is constant header : string(1 to 44) := FF & " Time R/W I/M Address Data"; use std.textio.all; file log : text open write_mode is "buslog"; variable trace_line : line; variable line_count : natural := 0; begin if line_count mod 60 = 0 then write ( trace_line, header ); writeline ( log, trace_line ); writeline ( log, trace_line ); -- empty line end if; wait until (rd = '1' or wr = '1') and ready = '1'; write ( trace_line, now, justified => right, field => 10, unit => us ); write ( trace_line, string'(" ") ); if rd = '1' then write ( trace_line, 'R' ); else write ( trace_line, 'W' ); end if; write ( trace_line, string'(" ") ); if io = '1' then write ( trace_line, 'I' ); else write ( trace_line, 'M' ); end if; write ( trace_line, string'(" ") ); write ( trace_line, address ); write ( trace_line, ' '); write ( trace_line, data ); writeline ( log, trace_line ); line_count := line_count + 1; end process bus_monitor; -- end code from book stimulus : process is begin wait for 0.4 us - now; rd <= '1', '0' after 10 ns; address <= X"0000"; data <= B"10011110"; ready <= '1', '0' after 10 ns; wait for 0.9 us - now; rd <= '1', '0' after 10 ns; address <= X"0001"; data <= B"00010010"; ready <= '1', '0' after 10 ns; wait for 2.0 us - now; rd <= '1', '0' after 10 ns; address <= X"0014"; data <= B"11100111"; ready <= '1', '0' after 10 ns; wait for 2.7 us - now; wr <= '1', '0' after 10 ns; io <= '1', '0' after 10 ns; address <= X"0007"; data <= X"00"; ready <= '1', '0' after 10 ns; wait; end process stimulus; end architecture test;
gpl-2.0
ff3d74d13a2bc71e6e6f7a4fda058d01
0.623669
3.478307
false
false
false
false
tgingold/ghdl
testsuite/gna/bug035/my_project.vhdl
4
1,786
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- This is a template file. -- -- TODO -- -- USAGE: -- 1) Copy this file into your project's source directory and rename it to -- "my_project.vhdl". -- 2) Add file to library "poc" in your synthesis tool. -- 3) Change setup appropriately. -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library PoC; package my_project is -- Change these lines to setup configuration. constant MY_PROJECT_DIR : string := "."; constant MY_OPERATING_SYSTEM : string := "LINUX"; -- e.g. "WINDOWS", "LINUX" end package; package body my_project is end package body;
gpl-2.0
b974bf7086266e60121f8c23150e1434
0.584546
4.16317
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_doHistStretch_0_0/sim/design_1_doHistStretch_0_0.vhd
2
12,920
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: utt.fr:hls:doHistStretch:1.0 -- IP Revision: 1606210026 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY design_1_doHistStretch_0_0 IS PORT ( s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC; s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC; s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_CTRL_BUS_WVALID : IN STD_LOGIC; s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC; s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC; s_axi_CTRL_BUS_BREADY : IN STD_LOGIC; s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC; s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC; s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC; s_axi_CTRL_BUS_RREADY : IN STD_LOGIC; ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; interrupt : OUT STD_LOGIC; inStream_TVALID : IN STD_LOGIC; inStream_TREADY : OUT STD_LOGIC; inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0); inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0); inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0); inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0); inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0); outStream_TVALID : OUT STD_LOGIC; outStream_TREADY : IN STD_LOGIC; outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END design_1_doHistStretch_0_0; ARCHITECTURE design_1_doHistStretch_0_0_arch OF design_1_doHistStretch_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHistStretch_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT doHistStretch IS GENERIC ( C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER ); PORT ( s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC; s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC; s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_CTRL_BUS_WVALID : IN STD_LOGIC; s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC; s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC; s_axi_CTRL_BUS_BREADY : IN STD_LOGIC; s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC; s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC; s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC; s_axi_CTRL_BUS_RREADY : IN STD_LOGIC; ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; interrupt : OUT STD_LOGIC; inStream_TVALID : IN STD_LOGIC; inStream_TREADY : OUT STD_LOGIC; inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0); inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0); inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0); inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0); inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0); outStream_TVALID : OUT STD_LOGIC; outStream_TREADY : IN STD_LOGIC; outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT doHistStretch; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RREADY"; ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST"; ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID"; ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY"; ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA"; ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST"; ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP"; ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB"; ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER"; ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST"; ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID"; ATTRIBUTE X_INTERFACE_INFO OF outStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TVALID"; ATTRIBUTE X_INTERFACE_INFO OF outStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TREADY"; ATTRIBUTE X_INTERFACE_INFO OF outStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDATA"; ATTRIBUTE X_INTERFACE_INFO OF outStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDEST"; ATTRIBUTE X_INTERFACE_INFO OF outStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TKEEP"; ATTRIBUTE X_INTERFACE_INFO OF outStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TSTRB"; ATTRIBUTE X_INTERFACE_INFO OF outStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TUSER"; ATTRIBUTE X_INTERFACE_INFO OF outStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TLAST"; ATTRIBUTE X_INTERFACE_INFO OF outStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TID"; BEGIN U0 : doHistStretch GENERIC MAP ( C_S_AXI_CTRL_BUS_ADDR_WIDTH => 5, C_S_AXI_CTRL_BUS_DATA_WIDTH => 32 ) PORT MAP ( s_axi_CTRL_BUS_AWADDR => s_axi_CTRL_BUS_AWADDR, s_axi_CTRL_BUS_AWVALID => s_axi_CTRL_BUS_AWVALID, s_axi_CTRL_BUS_AWREADY => s_axi_CTRL_BUS_AWREADY, s_axi_CTRL_BUS_WDATA => s_axi_CTRL_BUS_WDATA, s_axi_CTRL_BUS_WSTRB => s_axi_CTRL_BUS_WSTRB, s_axi_CTRL_BUS_WVALID => s_axi_CTRL_BUS_WVALID, s_axi_CTRL_BUS_WREADY => s_axi_CTRL_BUS_WREADY, s_axi_CTRL_BUS_BRESP => s_axi_CTRL_BUS_BRESP, s_axi_CTRL_BUS_BVALID => s_axi_CTRL_BUS_BVALID, s_axi_CTRL_BUS_BREADY => s_axi_CTRL_BUS_BREADY, s_axi_CTRL_BUS_ARADDR => s_axi_CTRL_BUS_ARADDR, s_axi_CTRL_BUS_ARVALID => s_axi_CTRL_BUS_ARVALID, s_axi_CTRL_BUS_ARREADY => s_axi_CTRL_BUS_ARREADY, s_axi_CTRL_BUS_RDATA => s_axi_CTRL_BUS_RDATA, s_axi_CTRL_BUS_RRESP => s_axi_CTRL_BUS_RRESP, s_axi_CTRL_BUS_RVALID => s_axi_CTRL_BUS_RVALID, s_axi_CTRL_BUS_RREADY => s_axi_CTRL_BUS_RREADY, ap_clk => ap_clk, ap_rst_n => ap_rst_n, interrupt => interrupt, inStream_TVALID => inStream_TVALID, inStream_TREADY => inStream_TREADY, inStream_TDATA => inStream_TDATA, inStream_TDEST => inStream_TDEST, inStream_TKEEP => inStream_TKEEP, inStream_TSTRB => inStream_TSTRB, inStream_TUSER => inStream_TUSER, inStream_TLAST => inStream_TLAST, inStream_TID => inStream_TID, outStream_TVALID => outStream_TVALID, outStream_TREADY => outStream_TREADY, outStream_TDATA => outStream_TDATA, outStream_TDEST => outStream_TDEST, outStream_TKEEP => outStream_TKEEP, outStream_TSTRB => outStream_TSTRB, outStream_TUSER => outStream_TUSER, outStream_TLAST => outStream_TLAST, outStream_TID => outStream_TID ); END design_1_doHistStretch_0_0_arch;
gpl-3.0
5be7f6560ec84d4c6aaeb90da5967321
0.712771
3.375131
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd
4
3,400
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- code from book (in text) entity computer_system is generic ( instrumented : boolean := false ); port ( -- . . . ); -- not in book other_port : in bit := '0' ); -- end not in book end entity computer_system; -- end code from book -- code from book architecture block_level of computer_system is -- . . . -- type and component declarations for cpu and memory, etc signal clock : bit; -- the system clock signal mem_req : bit; -- cpu access request to memory signal ifetch : bit; -- indicates access is to fetch an instruction signal write : bit; -- indicates access is a write -- . . . -- other signal declarations begin -- . . . -- component instances for cpu and memory, etc instrumentation : if instrumented generate signal ifetch_freq, write_freq, read_freq : real := 0.0; begin access_monitor : process is variable access_count, ifetch_count, write_count, read_count : natural := 0; begin wait until mem_req = '1'; if ifetch = '1' then ifetch_count := ifetch_count + 1; elsif write = '1' then write_count := write_count + 1; else read_count := read_count + 1; end if; access_count := access_count + 1; ifetch_freq <= real(ifetch_count) / real(access_count); write_freq <= real(write_count) / real(access_count); read_freq <= real(read_count) / real(access_count); end process access_monitor; end generate instrumentation; -- not in book stimulus : process is begin ifetch <= '1'; write <= '0'; mem_req <= '1', '0' after 10 ns; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '1'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '1'; write <= '0'; wait for 20 ns; mem_req <= '1', '0' after 10 ns; ifetch <= '0'; write <= '0'; wait for 20 ns; wait; end process stimulus; -- end not in book end architecture block_level; -- end code from book
gpl-2.0
312543ca1f0d33927c453686c1e79cca
0.6
3.590285
false
false
false
false
nickg/nvc
test/regress/elab27.vhd
1
934
entity sub is port ( c : out integer := 0; a, b : in integer ); end entity; architecture impl of sub is begin c <= a + b; end architecture; ------------------------------------------------------------------------------- entity elab27 is end entity; architecture test of elab27 is component comp is port ( b : in integer; c : out integer; a : in integer ); end component; signal x, y1, y2, z : integer := 0; for all : comp use entity work.sub; function negate (x : in integer) return integer is begin return -x; end function; begin uut1: component comp port map (x, y1, z); uut2: component comp port map (x, negate(c) => y2, a => z); p1: process is begin x <= 1; z <= 2; wait for 1 ns; assert y1 = 3; assert y2 = -3; wait; end process; end architecture;
gpl-3.0
7c7a9fd95e5cc47e5b50be08cd935d08
0.490364
3.92437
false
false
false
false
nickg/nvc
test/regress/predef2.vhd
1
858
entity predef2 is end entity; architecture test of predef2 is type int_vector is array (natural range <>) of integer; type bit_vector is array (natural range <>) of bit; begin main: process is variable p, q : int_vector(1 to 3); variable bv1 : bit_vector(3 downto 0); variable iv1 : int_vector(3 downto 0); variable b1 : bit; variable int1 : integer; begin p := (1, 2, 3); q := (4, 5, 6); wait for 1 ns; assert p < q; assert minimum(p, q) = (1, 2, 3); assert maximum(p, q) = (4, 5, 6); bv1 := "0100"; b1 := maximum (bv1); assert b1 = '1' report to_string(b1); iv1 := (5, 4, 30, 2); int1 := minimum(iv1); assert int1 = 2 report to_string(int1); wait; end process; end architecture;
gpl-3.0
740c50791e39debfb1e3fef1dd19cdfd
0.52331
3.338521
false
false
false
false
nickg/nvc
test/simp/genpack1.vhd
1
809
package pack is generic ( x : string := "foo" ) ; constant s : string := x ; constant t : string := "hello" ; constant k : integer; end package ; package body pack is constant k : integer := 42; end package body; ------------------------------------------------------------------------------- package pack2 is new work.pack generic map (x => "bar") ; ------------------------------------------------------------------------------- entity genpack1 is end entity; use work.pack2.all; architecture test of genpack1 is function get_length (s : string) return integer is begin return s'length; end function; begin p1: process is begin assert k = 42; assert s = "bar"; assert t = "hello"; wait; end process; end architecture;
gpl-3.0
47f2d2b7633c497e8ad5d2028246ef22
0.490729
4.445055
false
false
false
false
stanford-ppl/spatial-lang
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/ghrd_10as066n2_f2sdram2_m_inst.vhd
1
2,111
component ghrd_10as066n2_f2sdram2_m is port ( clk_clk : in std_logic := 'X'; -- clk clk_reset_reset : in std_logic := 'X'; -- reset master_address : out std_logic_vector(31 downto 0); -- address master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata master_read : out std_logic; -- read master_write : out std_logic; -- write master_writedata : out std_logic_vector(31 downto 0); -- writedata master_waitrequest : in std_logic := 'X'; -- waitrequest master_readdatavalid : in std_logic := 'X'; -- readdatavalid master_byteenable : out std_logic_vector(3 downto 0); -- byteenable master_reset_reset : out std_logic -- reset ); end component ghrd_10as066n2_f2sdram2_m; u0 : component ghrd_10as066n2_f2sdram2_m port map ( clk_clk => CONNECTED_TO_clk_clk, -- clk.clk clk_reset_reset => CONNECTED_TO_clk_reset_reset, -- clk_reset.reset master_address => CONNECTED_TO_master_address, -- master.address master_readdata => CONNECTED_TO_master_readdata, -- .readdata master_read => CONNECTED_TO_master_read, -- .read master_write => CONNECTED_TO_master_write, -- .write master_writedata => CONNECTED_TO_master_writedata, -- .writedata master_waitrequest => CONNECTED_TO_master_waitrequest, -- .waitrequest master_readdatavalid => CONNECTED_TO_master_readdatavalid, -- .readdatavalid master_byteenable => CONNECTED_TO_master_byteenable, -- .byteenable master_reset_reset => CONNECTED_TO_master_reset_reset -- master_reset.reset );
mit
72564500b2c2874131c8565d000446fa
0.500237
4.044061
false
false
false
false
tgingold/ghdl
testsuite/synth/issue1122/repro.vhdl
1
1,658
entity repro is port (clk : bit; rst : bit; d : bit_vector (7 downto 0); q : out bit_vector (7 downto 0)); end repro; architecture behav of repro is constant c : bit_vector (7 downto 0) := x"7e"; signal s : bit_vector (7 downto 0) := c; begin process (clk) begin if rst = '1' then s <= c; elsif clk = '1' and clk'event then s <= d; end if; end process; q <= s; end behav; -- For this design: -- %3:$o[8]{n7w8} := 8'uh7e -- \s:$o[8]{n8w8} := $isignal{i7} ( -- .$i: %8:$o[8]{n12w8} := $mux2{i11} ( -- .$s: \rst{n2w1}, -- .$i0: %7:$o[8]{n11w8} := $mux2{i10} ( -- .$s: %6:$o{n10w1} := $edge{i9} ( -- .$i: \clk{n1w1}), -- .$i0: \s:$o{n8w8}, -- .$i1: \d{n3w8}), -- .$i1: %3:$o{n7w8}), -- .$init: %3:$o{n7w8}) -- \q := \s:$o{n8w8} -- For repro2: -- \s:$o{n8w1} := $isignal{i7} ( -- .$i: %9:$o{n13w1} := $mux2{i12} ( -- .$s: \rst{n2w1}, -- .$i0: %8:$o{n12w1} := $mux2{i11} ( -- .$s: %7:$o{n11w1} := $edge{i10} ( -- .$i: \clk{n1w1}), -- .$i0: \s:$o{n8w1}, -- .$i1: \d{n3w1}), -- .$i1: %6:$o{n10w1} := 1'uh1), -- .$init: %3:$o{n7w1} := 1'uh1) -- \q := \s:$o{n8w1} --> -- %3:$o{n7w1} := 1'uh1 -- \s:$o{n8w1} := $isignal{i7} ( -- .$i: %10:$q{n14w1} := $iadff{i13} ( -- .$clk: \clk{n1w1}, -- .$d: \d{n3w1}, -- .$rst: \rst{n2w1}, -- .$rst_val: %6:$o{n10w1} := 1'uh1, -- .$init: %3:$o{n7w1}), -- .$init: %3:$o{n7w1}) -- \q := \s:$o{n8w1}
gpl-2.0
4faae78c8047436c032859ba409aaa3d
0.379976
2.090794
false
false
false
false
nickg/nvc
test/regress/synopsys1.vhd
5
550
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity synopsys1 is end entity; architecture test of synopsys1 is begin process is variable x, y, z : std_logic_vector(7 downto 0); begin x := conv_std_logic_vector(5, 8); y := conv_std_logic_vector(3, 8); z := x + y; assert conv_integer(z) = 8; z := x - y; assert conv_integer(z) = 2; assert conv_integer(x * y) = 15; wait; end process; end architecture;
gpl-3.0
b5ea13e8d12838c4bc73516c203ccbdd
0.590909
3.16092
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_13.vhd
4
1,650
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_01_fg_01_13.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- entity test_bench is end entity test_bench; architecture test_reg4 of test_bench is signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit; begin dut : entity work.reg4(behav) port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 ); stimulus : process is begin d0 <= '1'; d1 <= '1'; d2 <= '1'; d3 <= '1'; en <= '0'; clk <= '0'; wait for 20 ns; en <= '1'; wait for 20 ns; clk <= '1'; wait for 20 ns; d0 <= '0'; d1 <= '0'; d2 <= '0'; d3 <= '0'; wait for 20 ns; en <= '0'; wait for 20 ns; -- . . . wait; end process stimulus; end architecture test_reg4;
gpl-2.0
7a3238a5d7b81ca3f01e0ec780506364
0.581212
3.326613
false
true
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd
4
1,595
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA architecture functional of S_R_flipflop is begin q <= '1' when s = '1' else '0' when r = '1'; q_n <= '0' when s = '1' else '1' when r = '1'; end architecture functional; entity tb_S_R_flipflop is end entity tb_S_R_flipflop; architecture test of tb_S_R_flipflop is signal s, r : bit := '0'; signal q, q_n : bit; begin dut : entity work.S_R_flipflop(functional) port map ( s => s, r => r, q => q, q_n => q_n ); stimulus : process is begin wait for 10 ns; s <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '1'; wait for 10 ns; r <= '0'; wait for 10 ns; s <= '1'; wait for 10 ns; r <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '0'; wait for 10 ns; wait; end process stimulus; end architecture test;
gpl-2.0
c91bba0727ab545300db0d2cb04df37d
0.64326
3.372093
false
false
false
false
tgingold/ghdl
testsuite/synth/issue1162/counter.vhdl
1
500
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity counter is generic( LEN : positive := 1 ); port( clk : in std_ulogic; reset_n : in std_ulogic ); end counter; architecture behav of counter is signal c : integer range 0 to LEN-1; begin process(clk, reset_n) begin if reset_n = '0' then c <= 0; elsif rising_edge(clk) then if c = LEN-1 then c <= 0; else c <= c + 1; end if; end if; end process; end architecture;
gpl-2.0
bb37dd6a0a0004da2fb574301ea6aa57
0.608
2.688172
false
false
false
false
tgingold/ghdl
testsuite/synth/dff01/tb_dff11.vhdl
1
776
entity tb_dff11 is end tb_dff11; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_dff11 is signal clk : std_logic; signal din : std_logic_vector (7 downto 0); signal dout : std_logic_vector (7 downto 0); begin dut: entity work.dff11 port map ( q => dout, d => din, clk => clk); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin din <= x"00"; pulse; assert dout = x"00" severity failure; din <= x"ab"; pulse; assert dout = x"ab" severity failure; pulse; assert dout = x"ab" severity failure; din <= x"12"; pulse; assert dout = x"12" severity failure; wait; end process; end behav;
gpl-2.0
34eac79ed3d8abe01a26204a14a01b9c
0.582474
3.344828
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_02.vhd
4
2,938
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_16_fg_16_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity processor is end entity processor; -- code from book architecture rtl of processor is subtype word is bit_vector(0 to 31); type word_vector is array (natural range <>) of word; function resolve_unique ( drivers : word_vector ) return word is begin return drivers(drivers'left); end function resolve_unique; signal source1, source2 : resolve_unique word register; -- . . . -- not in book type alu_op_type is (pass1, pass2, add, subtract); procedure perform_alu_op ( signal alu_opcode : in alu_op_type; signal source1, source2 : in word; signal destination : out word; constant ignored : in integer := 0 ) is begin null; end procedure perform_alu_op; signal phase1, source1_reg_out_en,other_signal : bit; signal alu_opcode : alu_op_type; signal destination : word; -- end not in book begin source1_reg : process (phase1, source1_reg_out_en, -- . . .) is -- not in book other_signal) is -- end not in book variable stored_value : word; begin -- . . . if source1_reg_out_en = '1' and phase1 = '1' then source1 <= stored_value; -- not in book stored_value := not stored_value; -- end not in book else source1 <= null; end if; end process source1_reg; alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . ); -- not in book open ); -- end not in book -- . . . -- not in book process is begin wait for 10 ns; source1_reg_out_en <= '1'; phase1 <= '1', '0' after 10 ns; wait for 20 ns; source1_reg_out_en <= '1'; phase1 <= '1', '0' after 10 ns; wait; end process; -- end not in book end architecture rtl; -- end code from book
gpl-2.0
21b3c9b04a38113672d6957a7cb52a9b
0.58373
3.927807
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xbip_bram18k_v3_0_2/xbip_bram18k_v3_0_vh_rfs.vhd
9
96,728
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block obXXhxRlTaHjCpJV4uPTkRwgR3GpcvDfot0y8VTPyFxY1NMmmd9nxF2yYzxY4op4aE47wJsPh3ch Ifk4Z8Oulg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hmzRe/Qr+6nIcxuhkGdjIkYxpmHpO2VQJwayWf2lxaeB8TRqxhanf79tJphTIT7qZJNlaejd5WBb CQ1aMumla5wg4w9VFCJ3RfIX218tcMJOolbR14I3sidO+tsZwyzxKpPgnD/kd4T877IMOTrRvnIx 6PdsYAvnCf3xQFi7I2w= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block x0fTehxzghnOkOVVaF5ZPRso1LEjaAT4Ij9Za1bH3Oj/tMEqkw6sMVwuBHCx+9OVt2006A4ekCrO o6bGNZkP9ZTi3rPDQxJqDp8sg5+LnJfN79zDXHa15RdmKwVkjgf3nwhk4ny+EFYVb0Y54aV8MR9O zAXbiBIex84Cf/eo0y4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Ic1yv1cEiezEPDPgDJrMxh9C2VwWquV93tLinJarxYj+AmqpzKzI5K1H2OQZe7dbFN/MWnbwXkU3 VZ4HTFO2LNY6CAQ7agHefFUAhNGwX0QRTr7VGuTBYmzhsAHdeMqszybd5GeRvJKr6TK24gNATQrN nT2+HjrdVmQVjknT/su1Hfhm/cYUP3DwaHb/YUh3OhjGRMtE/ZGv2ChKMu2k7R9vmk5m/gNYJ2nE 08anLKgzUjVJXgO49+Y0G/wzgXuirkniHC7vyzJoNICrYz2RxJ622p1143uKw66xJyQQhrd2qIBT Jl/KhVnIuyuaJXAkrqwFPiigy+IHyR/snmCbug== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LFux42eTG7g9Qxp237PDkKB2zzr08ZwHBtwQiK5Ci6HPYEcDQC5ARtEmy5K+FX4t3iGvCUCf7B7w WkQZxeuQq5Pu6G1UdqUYoZkYnIGvv/FBS58O80A7wz1hDYmIuCFtceYj9Pc2fMtYY1GsiMPo8DHK SwPJ/nBgoPhAul+T5S2sYyEyPKDBAHo2NS+ueZipFxaUmHpYSWv2JHPg5npmpprgScJtWI7t52dF UBV3yLc4chOAUHmW60pHDB60diNc3yRD3AWRAYuPmEcz797OhGqtq/0Gf/sQq2aaRuUjcjmv7RjV F0UQ0AGzw4qc2pK/6BN6qq92U2093f2LWTUUxA== `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mLsPIi/Ovuty+EZo5FSaXGTuskBHoX/S7M5BlV63QV6xgpHFSsvDZ9Xz7MoE307jvEG7GvmYbswJ 7MgGzFiYjlGDXcPhjku9wDs+Lmtnt1wDk3JEvFz7Qw/y4xrtBAKwKEzSCJWoN1fsuG/a1bHGMBW9 QIANQXT/XtWTLwK/eGYczVjN8LvuNEgutpT0ch7ABudM0jLaNAh74dH36yQSfhAmYUPLYgwDG1YG +aO/K3xh2vVQGtq+ZMzL4D6TG82lwyl33sG5zqpY5BEVhRG0s6EN4POou3ixu/Cj3dzQaQQh4MGA wnkI7caqlqGiTD7K0fMqU6D6LxVakb07jRj56Q== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 69472) `protect data_block ZSNt4Iv9z7W52E4HVDUrJeMgb+XldKDqCetylmR3xDloDszn1RI4cli6QJboyTTugHpb35VwVP8w RYH0rPbdXvR5vxC4rNO5zZPVkhSMLR36lXUKymwLB/c5AfSmRUe+7c4MSOF2YA8rP3Xp4bJWdpUy Y8ZsjGHEm26eq+jL4Mj1m3odQxKbjxAt6UsiGwM+BdcW8rPVh2W5Pht/178zi0/V26wdF7NcFcN4 MWR4ahjRRFEPt8GrppqTPLdK0B6VuIZA6djURspniDLn9NK36m7PtNlBNGnlMOe+R/qs6OwJi81V 2Bk1mH5nCyrJjr0Ia94pJIkgtL+Qc9Ch2PUwYGtOP3mJMQ41AIGMiwMz2FfK11stDvGssgdvUdlf bFuRKf0Hu+rsTESXC5hqBCTo2Xh1uUq1JJURTZbvC1B8xvou5sClL3gqLuKE1938HQ1F6+i/8csS rzr0CPYIWKr+ojSTtmmtf7sjUVVdacVHkvxtBV3tWU57+B/4ejSSO/p7BCSV5HccE1R0cBKhyvy/ 4zna4YQyR31Rw4viAxBzyhd2lQt3DmYlpOZl+a0ZeoZJfT3yZEqt9m+7tVNJvEUV77GIgpX9PHIv 4Im/VixH/P8Y/FrJDPR8xZ4SQouOSX+YX44GuPMpuz7Ll2cgyFSdY6WqqKJy2ra7UB5CIKzeqBI+ ZR0anenXY0nbw8v2RxShKwsIsFIQKC41z6mQnIPjs0a0cJ2B3ILK+JzablJIZKbi29p16uhzqEYj 3sIQ2Fz+L2/e5px8n2LMfrdOtky3q4EgYUivnOCG6MJ+idK9ko//YidDumPmrMUZtPVclY+Iiov9 5um5Qjz3TnR1Vae8pj465wiQtxdjfvj9ZlUm0GtOVFApNdF8oZKABjK1FmGsSNJh08PGdU8j04Cc ruMvej0DKg2Lj2cFUA10fq/VEUJ8eAkvCbZdqw8PXTZjYGjYATbHfZggIjKXOJyXPePr3L7QIpYC 4ZSz0VFsw8HmZ8E3nCL8obzC+JfOlc7Pqa5Az/hsfWvUYWMfJIGcpu8PCvY1mWJmU3djk4vF403z bwVjSfg2Ul3YQZ7IcUKeDCHxVqv8+XGOVbPadtvUnkA8YECw8KXfrN47VwIbGoYDlaSsHpSqr9q1 va5vqeghDrmLjDKd1EJ5M7KuuceQwj0JYg7JhN5DJCuWQaNHNSqkKlax9phQobgu8SBPigAWTzh4 TzXEef/ZjnuVpPADvYzKyYvGLmMoqeb/da3sqaoq0Rhld7mkvVxv3rIVn2F4p/MliH4lk1+MCtib DVs1ZcGpQOxdNubltkMhCqDqWi+h5Ln4r04Y/hd0ApGGAWVb0Cw26IeRD/dkYR9l2J8/zzK0MTkp OnISles/JqwMLW8kKOGbO6IJZR7aCV6tP/dLGSLHgpXiKoO29vpB+3+voGNKPzcw0CPBW+m+n2dX /oAQiU5ZDrBkAVZLS7JEAjbVJDsR3BhJwN5buW9ddF3zZ7bN5Q66NBNcF5MPjR5G+e4qLYTAkch6 ER+cpWBRVCs8p4F9eRZoNeDkCK5/pYhTERONOsqzwCZLr+cvZs85vY0mbAmtR0vyQCb/rP7KjM/D 8VWWt/Vk+Dr7VCVKsBpNxaUX/xQbH3V7CSD0Aeb4BDdfsy1FJKaQY6ghksum32N8ZV9u9sOpynlW dTJLHr16JfZr4F7mr2s568L8I/2/L2kkWODKIPOYc56ai8RVxbkU7kbbRhDkgdQpcz2HLTB0dQCP QOfLKL0co2os0Rp/r4q8NDTinbscSqp8UD9eWBEgeFrat9mkD08i12pdXrWV1F8sb3gk1//9IaPa gBwE42bpONlvRgPwpPZfsRepBBdgGtC9lMYOBTbXREEWAUwALrZKeOv4BwQRrBKFaUQyleMjsgjm hP6c1Hsh3siGohLB7sp6BVKh2nxrGKTIlJhDZCKIJITEA69uXarTanbxobbO/FgqPFXFaqQegnGJ Wq9CmXqsMEp3njkuKnWMoiMQENTmkUb5kAgquEgZWUEEb7qnS0h0z5ME/2zjIRPoKZrVwCM2vhbe 0FYcwUQQHzka5bcj5Ka579xCFs1S5AJVlWTddWIFcYrF0lyqGBE+svAHmNG7RN0m8UYy4NroHMID fMfj9pWN/KcGg4kSpKiogyxNdyJWtEppKxhqt1ia658HCiaZTIVlGjF7DRd/RejHLwDjeVGGDv2Y lv8hW96VpvpLmLLvByOGh2iyLSEF/0iibWroxDGEom5LiBV124sgIF2tA+pOwdSMEqJ7TpqwBF/C ihz8LZKSiRZKWw8dmyybCHV8yir2vZp3f5nbwbuFCTeXNe9FzHR4WZjdEuRW1OS/Ek3A1NYgSvZ9 ZWqTVtX9lnvwHZgsEtxWsazzssCGgt+GyMvVPr64JuEFdaF0dySRAomgXYRwRre3fGiKpdldzvFb AbaA+9YIk6TfL2A3q1QddEOkh/oOOm9iqRYERECBq6G/8pFM8VBOllIEK7RrkdIqx2zIPvLRNkB+ xdArUos1rwTexj09QZSF53OuTAkNXAlQf36ys1L7/vTGkzwW40tUOOUNBSq3TYmq/5KnIRuj7V+t sktCZ1oJsHrrtzV4mDa7tXBpUKqV6V532DL5UjiZePxrS5qWd265ri2zvFQIbQxhUXHK1Yo6DBuK z+Gdx/w+eoPur6k2XGDZs0jej6y6gLwwYvjsIbQ+1VHs37nbd8e3ZWwad/4qaaD9x/use/86FmSu J+KhzHeqCudgtRdPAOSUtrACR7Y0YHOYrZ364fthJzwQJhu3//ejevnPEuDyE91GAOLxH+S9i9dG RYNx1YI7npnBZqM1vrMknHDx3JSOiT0UojvmksZL7DnbLH4wQCeXTxkmPBfw/2xVfPCnZTOsYhmg pwnZNYHkEM2JonDamCqbVO+l3IWIg0JhJutR2tjN2xmDX5e5Oy/x53Mtm2rHj5Jdd1ib+zTqdUsE R24W84xZszr0YlB2wZSt/P2XZcGXNEk5D6dubM6YPW1O56jdPqhk0E3VuP0yx3YlaZKpLnm5+ihL bu9p6h7uBSKZVp5OWxS99DTAsPqv8ct/4VfNFX5aUB/VuecAyWyQO9t2WSB9Qlo/v6OUG5URVX6d 1rjQnLF9BAVWdAhb4IRHQ5InZkm0I86swTY95Bil7y3KOuS65FHlTrJknwYR/qBjrOuq73SiVNfS NFVYkgZDFIsCzAgk4BB813x0Qso7rV8iLNFKYajj5X8xYET5zCoqoHy0VfLx+ZtLVzfuKXr+EAEk EulCtVfyaGot71k+O0jslSGOj3nmXGTDB8WNt2iHy+g4/EjQduygK+nxfFIijDm6Eg6hax/ubnM3 nFJHxsB4+35Sce+S5gYx8+BEvYRbNtdFbmNtnxBZinsIAeC3Q2e5LiiZWSCFOn78Sa3KCxIKS9mr Rsjvm8CIWzRUcdkZLyDcAA6e6k1AzOa4m3pdEheJ+PCbspUVd0egRDAHCPIPV72XTvK+TsolpFYP LMeFeCix0P4aN+02w89FW/gJT7TPFDo3q+nDKpR25680pQgV1CLtV1zmoGIFRdP1eJz+FQ6lS1W+ tjaAMeU1AmKUPLdKqDEb2Zxpz8MqJaq3jgHB6XNbQE543QSFlQQLLj7pltLhxM2nXYaPaVgGeTpt oH6MbJFODuLDbM5qrhlYsBlI2hyVLKsmsLeD1K8v0oEX3B6lWksYTMvAr9RALEhN46QSQB1EBZIA Zl/7Fyuci80VfAbc49iBdytbrIc4x8SkNu50bH1UN+vFcBUC/ruImU4YMuJ9PEPdbUqQsqUIPrUI 8gcIFDK1pb3bc0m+bVe9RwVQpKprJhyZh0dTTRdTh5xKZYfSwvQmWcR6w2AJdrudrgZsfypE1SG/ 9SScm/e8XN2Bnepw7r6NXZnDhyPX+3Atom2ShTXVL8Khf1FwVjJQwc5DvjOhOqPS+fMi6ktKmRl9 oAy1gKzuwsNBwMthmJN0OZgnxW+jnKHa61ZPU7H7RJQiKJbaBZmdS+ZUNg0nhTTCjGOpHOKDAmKa DXxnOf3/7M2X4HI+oDtnOFz5hiRVii4Cotf3icVdvLal/un4phnZfrn2+cGRKXZuJu2XbTTd5a51 bKFXIgCA0zhpNauUX0+FRaDUg0RepSuWgymSJnshOZ4SJG6RoLwpE59CKVXyO3cDdTUga0fraLy6 uvDMcniHXyz1xj9QRpyMrJ+x65vopVLXv+DdFa43m+mTwEZJzAjHCfIfxDSYxxCN9Cz8D9JJAB3l RLMvlztK2g5kpzhsmDa/YUFOayDSvIz2im2k4lpWpCQESUv40QHZN3JMknL1Y+3YWzcJrMPEIcaV UhUnD5lTNgti4tmT9YhoWhJvZ5O3uFGE38qFTzpFcAv0QL9bLwlUXAzXVOQRGGz9HyZRiHVrbFXo dBJ41LSf/yIPx4nwzyETTo+KAmvLx1ruyguIARL/hGaW51emm53lEStA9oI8pbGa4nWq+Q7AyG9k VYwcLZ6J1bL/fsWcVpju+nvkXVl+zjXmr0AqDOpOcdwp0whXi7jqh/tsEywiS+O3Nhrd4siExfVl oGvV6jRNUrIWiFwldV5Fs/WyK02p6346nsJgzEpF7JBgOeHdmY3TSzS4SyCqg4PZ/PYhk6Fo3V4l WENsWL73fh7UMd1aNFg3yPkhBecydkZUGgXHZl+zIRn/jVPkH5ytFoFlTJB7Mj2G3R1dhmmpY9gc B1Lzgjc8U4dIDug8u0kklx8kdN/Y2FFlrxGLhgIlTqq28tRJyeJKoral50T0Ld77Tk6GnM4oNZiF 19IX5Ga4P8BzeTEhE0E+uagvUf1b4Lci21QEnEMltkaMQDYv49Hra8kWVFQq4frXvnP3/efY6adR CMspH4qkdvBE+22+vwQVMGYgjesxvCGWSALXKqUtZnLBz4wqx4usm6DbquH4d2Z1uCDhqmbQHBts 0k4mMqllxG0+FmPOJt/DhXmrHMhfeN7KKEkGqi+zptBPIOLSA3bip22dRJUvBWR9vKS4bYK/85KF nkC/n3iA3Z8hPV3BguvW2/QSug7KXm1GNzi3+dpGRFIQfzm61Ih23Tq2uVfQ3NIiuac/iK7QOpWM RbnXqi7uCIfUxiN4J4SjpNlkWicvM5MUNY2bCQVwJxD5XNLyeo1dZw8mFSWBkr26MKKEA9OCdR6Y RrTDAfJdbXNfAPO9dCvbTjYWz7av8eWHfcG4iIgF8qwYdtBDz7/gvJuzDKDo8siZ98bPwjzubjlR T++JHrypCLScGZCkIjJxJlHO029LvWhduungMqIltpDqkyzX3u0ypdeFVhzdtFplEa8iiijNRUov aHTIWdxLy3DtfYXIGZNLFuQLu6mNrwv+wypWLAKNDQAF7Yrqv9V418cp1WXW9UCF4VUofwYVA7SH n5nGP5NDag7EwzcST1k6fp679gAqR7i0myy1wBP9FD93bAFupjifZzlwxAG80svTpIP9ej45NfRK RWnqkXjhUO3AH3yMmIdK4uGJY80r2VVMyF/5jfbko8Nse+/uOExd8wIvBk8zkry3S1zNRx8r5w8V JBYPoxgIf2wwh1qkIZT3ITOVOZEuyTJNvlTgHWeZIfoMKhK7bArk2qpPM1a2WpowCc+gV+Ste6iN 5lxu1GUZCsyUzzijESnVeQfMFtGDMcj5WfYKTcfvaqnHrke6N4EIzharfeeHzoazIAssfn+1XUio Pf2ref5QThqaqJBWCjFnXhX8Cd2nu9Fs3akYT0nhvq1e4m9Qouy1DRXQNnncP2XMiRSSQSHKh+Vq ca7GtrozpafnD1m4y9auRgtF6LEOQq/amOoUD836VFcPMHBZrEHoZ+nR2kqJJpERdHhZYQN3toCD ACSA+qfqLCY9kz4H4IXGAt759ndLlJzJ8cbz7w3MAulscDotge2NVXAlRct1Z26YlyKqeTWu7Byw RktIlt7Yrd8JbB11+T+H6Tqw83aZx37KqoJJsuOZKfDMZD6vca7VLmgYlGb5xEvi1RG6w7NX/00A P2QQ0w54j5WjbMDyyLFTcqFoT77BUytmZV5PhU5UUl2m61V6hYr1U4GlcxE7tGHs+m6GyblHLUbO U/1kiJXtVQSQWjY1Qx96gM6+gCdj5pqMtEtinUMEcomwO7Tw+KVGkXulLKOmnb4MaNlnJLGpcQK8 uBHBMh9Dvb2EwIHyJZkYskSN+3823N0Re3YtxIuRI9wmSS8FQaEHkDXbCvnEpGJpeVNjgAGIYTlb s68TqlKpCBlfcSKwAnnRSO09jK0Eku5gnQ/+QnTKajblljD686zTAk5/RegIJ4qJ+VoLm10bxPX3 dokvlhV9ViH+5Iaq+9/C3GAlPNy0sUGY7gRNRTk2IDUIR68hUvh9pr4ueyTGR/jwBUSipZrZ8qFe C3CydNiduH1r9P2zaUkTlIViwtURCCe9pNmr81bjDn6KXC5aMaO9j0kKBrE7MEEU6vCihKpUzy/T lxgQzhGE+rzAdIWihhrObyfQWeUNGSLQK5Aaugds3l8xPJdY/Yrld3DIrezuRGN6DdbOmX/Zz4Ju NDfxB6WMy+SZy0O8T1Q3SSfJu/RGlKdlMGR2Jl+PDiFCMIxLZw2HQhQwm07OC5IbOPyWD9Z1yB63 RDPqT/m5DGTGIImhko0qqNCfLcl92RQscBO9LS6QnQXe16RdOU0nULP3VStOrtq/3p7oJRoE0h1A v18kbUup1UKPQp9nrpKJfZNVqK4kPKsliqu1J/2oXNHAOOoD+lrlcbW6pwLNw4yUA++zZ1GyuZRw DT0lcSv3qjUraWcU4BEI0KuvCA6ma9rDhS7Em930ZAtHjN3J9RVvGEeLJ323nK4Yb8L1mtMFEvrH wz3oP9mugqxQbC0uBXLiOSxc0WJLwzywux3Nz8u4CZAxLLaa9hcw/UyzORTHAmCGXkCRomDG/Zq/ e0+ziEnmN4DoVpMeCHUu4OLcq3J1injLHBaB51Nza8M+XGZSReF2ffT+3XKvR0H2k0iOaB1uJ8VI k5As7h8zfTnQfrz7ivTOURj5p5KFHHLjg9eWEvZUOs2MWOtR6HZKGyunwD1IxvmSQSpQqwPPIgKs /LJcLpHRBWXlQrEr4vwwkZZ2FGFjU5KTnZoHdxVlGj/Ixq/CnjE2HhbfpxfON8TQ5WeRJ37a6n9O rCCNPqRaEt0RsRloLyjf81HRZW5RB244cEYVKHpcdrfzFP6HuKUHdvmL91zAP1rKIQ4uHFw71DKK Nvxr30sHfJnYsyhJG4BizJElAh0z9Ubfp+uxrEST1q+CzvREwXqgycut4ck6z8kImVIWZWghCQXs RDap+vo2tmPoqnK4Hqezti2vARLJ0LJQhywN5Bp8slzydIqxu2z8C+2UIPEnmkAzYjlB820ha75M KiMX8aMEJ0iGKrzarOF2l4h4+4K6FkKgd/u9ojasHba3KwwJAJ0xMDyIr9slf6P2PD0BXZ1Xa6f2 NcL7/s4FcqflJw0Pg3jBky6gzQQZEIY04G5L7g1VgtMtVPaArdf4qCMDppqge1Bav/jt93y5zJqM wMwf1PyUrf0s9lrVi3d1o5JThomn3LIjHOsBMxXNhlM89jT+p+RNA1Ytsar6gminu41HtX0/wsG6 Pv8DXuPCLAk/4p/kxmpRwEM9+lUm1hPeoCSIpJaKUQKxQEMNEw1qjwBTR4D0Dc4muj1+R7nWcG26 Q6WO1D3U20EjUMyXTp9Io5qjI9ZfIJU2cblZxTmj/TDpmxZaIwBqdtUvbBU7s2APvdoj87NOLJEO Iiae9CpQEoHIF56q0btozbua28S5HO/0W7xJ1mG5G8YXgCjwfAvlDOdJB4Q0t4G3+W14YhLa58li xNO6uJ/FeqiTCy0agEQ0u2iQI1Y2N3lKdqchGuF4diK+etZiL0dH0hOBKLY0d2n4yoC3ZE5l3atN P8OZ9xL17Su5JiwqIHNov0d2/p0vZpCHaNNRXdQh5jFU6eG8L24sHhYTLizTR99Bc88Q2DFvR1tx 7xd3ysIZSoHjJQ5bGFzkMVKpq5f7zua6MZNCmoeXOMFUQxzdhalv7ltP2OCL4duOjXJtrmPSWOBh OpZm9NNJK8f/UU/dirdkdwMe0Hx3RVVRZ7flswpJAsVHlTDYVjATjn4cfQB5hXjwKwL4fJSJCqhF Y+KA/ER2izgIDHRPC4E1GZZPsxsECwt3y/va7uZ6Enc4LPm6p/VspGhIyAW9OZofNyfuNYVt6E2B SG6F3F2oTqUZl8i4e+E/m64PVLKs9IFtLBPbbEVteyAhmLVM2kc/9+KcmzDzsX0cYM/SM748Gc5X 3Vp/712B2oazTlCIgBOqFTps43HsqLbTmsBXWCHQ5VBOWJl9zK1LwIAW64rbb9c4opyDtQcQ8Nk/ yxHTD8KhBDaum53FPj76fvFGMOdQ84oFlSFxM3cQ14BhfypkXDaad4YrKc1N2iDTZrhCrJxCk3Uo c3q8RMZffuO4moMR2jrqgNVdwHoUNc/GSzV2LH3DoVYmATYVV0n4UZSfCIFkjPzAcyUr1T3PdI7s 7oOmnOhJEC5EuL0lkg3NsO9xP/GlIDt7T8ihCgOnYWME3beAO4RyBqtiZUDg8e0sWN8Ke9Ln7lFp O8He1nujAkTvAUxucyRFIkxylEF4OM05fXFlckcbN4buwDb1OKl++QRrqT+ks8ePi8CVZL/XgyCM XhPrbkCUfwpzoFFYhXiLX6NRJmRgS2DH8vuhXW3vGJdEZhUx+s3JkPGP1LFwCPdR9EjXeVfq+0mr Sz4zIQHfgkLQLPs9YPAcT0ywfsPgZHnbSjRDovkRDMAEfJ4+2wsLidjg3cKwGhj2Wu5uD6Ll7HxO fZ5KJwGa9Xng5+33xZn+1Cd4gdAh19K3EkWTWCcccI/VdRa+SKfK0lwB89CjISoDKvxzqiFZSPqD tYd8aWX7YIGfTQhevWgSQpR083Ba52VFaIEGc9avM0QJhqgbwf5qzLmnX1PbJsY4kl3FejEuux1b unDIOINyIIaiETt3pZ8zHUHzpDpJ+p0yXKp49fkpoO0D2+oioI+TGNtmta7+CXhkqCm3mKrC+GC+ eFNOj4ZTQQiv+n7ZByFpXS6wcsnxC6qeS2g0KyWZDWTJPZsVNl7puK5m86FqxsueTUF6h1KHY/yi s4XHe/qpleJrS8Ef5aT5qTgiB+GmYPympXd0C99/8o+5x99d032LR7kp/aIvRbTQrcEnAib/28qP 4Gjv7HexbUvWgtwEPRv/r4hAG1ZQmOSFGPQ6ZIFfYt6OrUkthsz0d0xtOSy3iaBbmqGnU7lEvc3j ADawzy2Tj4QH1LZl3jAxCykE1kWvlGao3FVjGqFM8p8zY4jb9brHyRw8HM03mqZiFifgZRa+Va88 AxIttY4c5WYIUSjEcwvGl6OL3ZmBB2HJTPxIZ2W/mA5dTzGx3adK1d8B1Qy5NqRPrdRLSxg2ENS6 JwzKAjcQzN0ACns3OcK+1SqkeKwKXnsU/LWEF9BXGEiR8gmXzPbv6T/L97OnYRE6UQWKs64hZl4c 5waBycek7tMZIEEeSzfz28DUUKGmOt2ZBSA9MNQCaw9zFfiGTWs++SNmVjOesll/cFUezP2TSPd/ 7t0kdAXP3Uz5ohZn2N1rAoIX5ClNEkn0zLs88N1TaKsNp5jIXxQEtF7zYfJI2gps4AnMf6IKDUGN V6ODC3mxWoFSo36GenmgOO//Z40nfeSyD/oi8v/vEnYntnUHdU18vImPUmSwO85W+GJzxznGmw6u jE5KgnEh3+dZ87xN7uRrRd/8bsh9oyYJ8KLauQ9x93mxBl6e+7kFZcHka1IOtyKWui/we1DcEU2C Bd2ch2+LO8cJFGUD7zMKys2Bzkb8VAqW7iIVi/aS+ceVzsLXFY1nlSqJ4qoSAqW+qeTcq8V4mRhV ZtH4UvwD9PLkPsC1CTrUfF+y2frx/duh9jVt4EZQWjoxbeSOhzKZctTg/mwel09Z2b1VRN0aP+Cd WNBf/0X705AkiLFidDjHUhRPMsyslT7ndEix2S5SwpAoUAhA7ww45JiM659yMfiHhpbbV1kPJn9w L65ZbRtMoA/6/61gGed3ZMCk65zoMdL8muMbco4bM6f0d6iKpfbhjnm+RIXOIxV7s9rhN5JUery/ uwUXMwqK9W1GRwkehd5a6f9XeZ5lK/wVt+VNNcc/Nee133jrghpz2vaUdkwHI7Pac/aR36islOYL GsomKPqIRrBuenKh2jOMmdHmue6Ux/PWNeV9mbPqDeUp6dcyRJ22/Lci8gAMfEIUrIMyw4iDIAb4 t2cxtoCzR7LcjfEoD8a5+Il6SRTp1FuYFmEIpEfO4uhH3HFf7qpkg4J1xAU16pbkvYdgS4C3BreB QIndFBqrns/+BvzskJSIwamPK6rKKEWChyd/6EEXWGvPMferMTnC4lPSDZRxOgWN6e5Qmn0Pzn9N JFiooz2QhD4qHiPxNDbF5uEDdd6z4FNGtcWd/i2p1l1vYeqab1p9mth0PFs4HTcHohgZGn9JOEfY +tD7RO9TpqCxwE1zQpBlmkHtwdI0KtX0DUWIVaT40TjXS0RX3SuY7lp8kPrrgjLMi5hci1GZr/fT MtWYQUo7VNHfL0NUVBc+Bm5h6pnaKsSt4RZ3txje7UoUeNW/Oo1pKjsPG4pLoB1iVtwU9Tf97q9E RQ5XuCjCbifZC9k/4NdFYQMhg3RUXns/FkUMXHQOe+QFqEcpHmUIl121bfRefn87SLUV/i++ZX+8 QJcWLKEW1bKxJu8W5jnrsuSC4BKCCLHThWcInuiLjOaY9dJAxTwPwvSQlOwQSHF2xBzfwvJ08dVm PmcS0tqUOrLGnIkiviNI6k8/Jrl6otlJHRpEqNjX6JiE4GhvtxJUCn0BezYywpKf7nMWgJBNK9/R TO8LybMiqiYw4t/iDeDGCyI35q427eMKyu5+LzyGuUDLFXPKOoKgI+HJPHkqiV02bx6NHKEe7BW5 SF41966Oxx0kXWINJj47/JRuRhZfhlnaMX+QxA8pRBMubQNJD9wSMSpdkTJdn42H1FMP7yt6iiOm qvU3ItgnsOePVVw09i6iXOnuX9vK+Qe74Fgbr/eZerv5LbB5mDDuPmhbOTjS7Pmyj1yiHkUi6PMg TTlRg39klqKpr+Pp4kkQHuYxcitF5KGX+R7U45OKeo620Dv62s0qQ2MvcRuaqOaPTlsu2PvH3Qf9 rKpYFKyP6FJ4p0O9uJSWbNTpcPgZb2jfzOMMtabbuUBOSramQu4RQwqNwoncItcBs6n9/hMmizhG iXA4UmAv2Vqb/Wh3wewzL1x7K1Kqyge/9WpISRoap9CVUSVJpLsLOCDECOCwi31842gyMf+81hJk hlxNgeOi6JiKkipFNYDcZgBhiWkW34ZPSXTl2YBJ6wTMNrRtqjEL3rJ3u3v9e4+7X4Tp12rB+ogw JFHY8PXkkAtjF5mSxhMosVN/F6STsGAYzu7kyrzZpY5JPpGo3Lzc2W/7t4uoJPlOmybr6zZYmOHb ywlABbhOoTN2OU0X0j/8UAJSilTs6kTpD2EjVUYl2HZXcZXCW+gUJYJYtAE5dM8VK7KYJtnrkvIj 06jZ/8tDdBjfEY2cOtlw9XNrrezVqUFjD+YQ4sL+g+hdqdcPF8s9GqcsEoUd1ThB6Ig/3GwlFRBD dBumTZ+E2FeNDo6LW2Ps4iGhQEaKtw+kCF7qroQZZxdbQUgWydkVz+5HJJNkuzJk8gXf8Tt3/ckF FtF7lS8E0gvQ4FxyLptjx/BvQknv/VjDq2kKHDhFeVjQu20wWjJq6hk2Ii2qngZFNKKsOsjTiX5h OtC8WnQL+0OPqNFejmVKeGZUpbu8rVipWx3V+mZcZ9FYerRJmqtv5GMn0h5xQmexkA+q0/QG3dUA ceSkMym+w/dJuL8FVMwdR12W6EGteR6LJSf5+RmOipOb6U+IGhFZYKup1weBkNMF/hgmo3aYx7Ua Ml7qFNdp2EXWJ9mq8XPWmrWOb37q7VbhY1jm2S4WvilqO14t2GZ0/9+0f6kAKuHmTC7SMkKMfunz Oev8hywSMYdfBfutPsh7LfU2ahzgklAkJXeVk/PHn08KBSETnGHPQUEo6XUEbHzxLMZ5XAPo02kd OyMYd2s2AoD8nbzIfr+lqoItsgNut4Z23OsEVEE2MasKzccj6Q2X/7ugPtDvPytjLmScxwiObhL7 uoyVUxYX+rikIvLenvYTvmuLDqYr/U+m6j2TbHllZ0hYmCBvFVofWq50mdleTB0wAYXLBLNmV7An 63DZGt+m9pExz3c3EbenTsDSzxSaospKujWaIiJDc47SQ+8VG3knZLZ8BzOgIO5xYWQT8r0axrM7 3RE1omlZrjLcm0pcHDkTZEx0baLoeKYzcqzAno1VwH/QPQloMkODKlHUvl+Iwz4tfkIJxrjOlXVb S/rKAidvTbG2yi9lHtRz5PeeaT202qZIIRnjI7DkuQUQmtan9lwmN41qmGIN0hU4qqaHMoEEpGPu aNLoqxC8E5xIEK3qTTW361/jNIpJv/iL044sjWAFfjhjHxSNlVD03R/pU9j0AezNQGo+Ra9ZxKXc f5nEP9ed2TEm4BnZZQy5/pNbpBT4Y69ZMcT5DZqbhETAcKArRzMRyOF3vTCanwbnCVo/vzHvTvjQ zcWdHxGr0LZYaBblIKYDXhQZan4z+kFNmB6WYrP8Pl/ydm8ZDrZW3GRXFGVoef73nkMqbt2jCc3e okd0Y5fBiBpz78dTMRRrpVTNYetciAMpZvmJ+PqQpEjKyds4bsZgtNkaOGkS+71GxVYgwXnUZHEW o5+QFaNzxtbmEUTaZ3bRxkrQE1xgXvUeEnF6d0k3XoOgSmqD/GE7JjmgXtpnbK5BPEe/WgmO7Dkf 53taI6sC8CScTKo1jJKFFpplPK2MU2Evv7lbZJ8AYDPTu6X28NjO3IviLgJwC2FBqTcVYc4Oju+2 clv8gRSYJEK5BjC1OWRMWxX2SbV5tp9AIlDHtmptUvA58y12wFTrZdiQEG6h9dCAaWh/1Iw3g7Bg rKZXkxThkBIwdFBcZK/9B1bpQXG4fEMOZx49k6j2ZbaoUYLfe/HVCv5cVdSrNnvny91Sh41v24aG HWpFFwJbYXbug5CHwoOt8RM1AJtnfXYxmOaLVMmARWTjFiEjzvHMDrPsaqYgn4SoDSjGR4JxGc7D gjoUQO4PDjLn+/u7V3yQKi5vpNnlV2Nr3wZ7zITFAbxV2V1P+sL9H1orlbP1hJXsV3RVA+afPhH8 E3O8v9od8lCZJCMCvIzUiobUbmBCtwIUvhygPxX8vl0woPaAv6tNANImmlK1wktulM1owxf+d2ho +nvUcfuVQHwXX4hB5tzYC1jN0yOtI5VEgvUs9irsKcvxPQcypg1QgFqBdHnPqTunRX5sfcOhHQks qOsp34TM2saFyfOk9naitnDkOn7aHdT7ypTPc8f8mKRzqo+aAtEA+TH59KbZpRKvYv7m0FxQsd1K bhcQw5I+200jXYsddGJfsHABXkN2pO965O8t12PwSAbQWLTT9lIjUCmA7EoxhHqO4TRG/mqSyRnY IJJm26Erp+6AEaUOWlNBo7fDCjtVL6VSwD2SGF2F4pCyDjAhp9O4JX7XFl0ygw2yQCivzbzNEeD3 +z6r968vVRpR2IeWr54rx/Oq/9CEuWRMzArgO5kbw/SHaHEgcIjhNANz5zmf0j5ZAjaQRqgFAu1F z4KS0yh56LkqL4n31TjspZ25gIcQf6ehGgLlbAyKKiPoGUu7WdQViT8o5qKp/ow5aDY8aiSXVqY3 LmN5At726U7XPwKzOqkUlYyhgGImItE9mQDl7mCOTzoSBATuoQo6KSN3uU5p+pEx2JM8AIMKj930 XKmMOvXL4N5q5ZZl4Qc2Qm+hE1+4nxtJIxuVSDxdE+r2EEbVA4hD03D4DYjGrwZvLBmOEBOUHLaC fWpbsPnwLbyI0Xw84ofZFMpRW3hLB3ziOgY7euVdqKWPIM7yHp4sbzzsQdgz6VlYrQCUhK9adLZt laSMxeSaMZ3rJqjN+vi89qW4uUGEcpjI8gKEK6OMXWx8ZxBjyt9mbSOCCLXoLL7weN4DLFOYYoI5 jZigVNaa7hf43cJStfub7k0pdQeJpBg5cSrdLu6OSquR/1s+nhARXLbiY3XvDgJzdBB3XZy4LcMM 0bQAOUVEyM/mcT0HeRYc+D6M2/wmMte3adERkMu3eKJxVywXURuySYtozPC/vQ2EaJQkdGkileal 6FRWrJ5g9rcFSsYciZRmAsL3KCFhFFuRttayl92TQ3iPBk/EgMRkjFcWn2wukA2JhyU9y4pJd98K GO7VT08EixnOO7uu8dWlUfZkVnaiE6eP+ommM47sCUs7V7I2Kn+5GlnCZ039GMHzlKzYaGeOOfcA W0sGCCldGwRye7snIcA6AfdgtBLknSh7pzeSDwRJpGhv++Bzx/PPLLhXf+ms4YRqe85fooLdUhvz pNHeNWJXY1Kup795+ji8qVisjwVe3rMHejIdTciLXBYkzdSYN4/uRpa3djzek9Uxcs6Ht8l8UQ63 Cb1PVCyf9Ue3OgQDK9wPNLAkeDtSb5yAXoU5zlRFtseJOR7O5JF8LGU1fE8hAvOFqkCb7Tw4CObv twwfk4uOJbtGpVq4mrt/KdtHkl3wGOAXhMiUWxOhqIysaGKmVwWgJ2q6RB/78jPAWZ+GPcJGlouJ K+RDAJUuUKC5TT3Dx9gMUng02M9RMRel4+h/XhmnCsNdJnWS5vmwb0wBXPHuMY0B7kwINGvopYLK 0cspI8bw5JG+L78SQxU68Fogln7GZeIfiK3+2+TTZ5NfoMyNpF9rAjUe6icOj00WJScHC6pvu6Yj 5BysbHDPS/SQ+LE2c2XCXhC/MC0Vp7L8L5yJSwrQGlSls59AIVs+yDsgx9gCD+N3LQTKxsnney5J bU4DiAb+6jDlx6cpkR8RdkvG7/w/ICBczB5l+UT0TyT3tAZhgDYqfm0NfCILjPa0zq8qoMfQZ7HD MTTBCOgqJMR0lvrzvyUs+hlLYPrJ9cAC9P1C1xHA9faWOVUqda5Kw+WP2tL8begKg/u5qZHEqd3V 6WRMGrgnzGYC8VOT2DLPAckgwa+5+1uavMQtbLP1iZzgw4/krjk+Pma1Zu5AC98SGm5LbNetHJNq 7kLpOrb5JbOFeBNNdggpMUrNCuM6pzfXIqW1Ww2E2R+25upl6QWI3ciE9PEF1hoC/QVfS/FFAYZp DF8c0XOHAWQRQrGEMFdMo3eY0+7YdXYkMpf/ivcMncLMNa/U93zRFWPLPs86sZw+wlvy7NqQn3e+ ADznteRwEgJl6oz15Rr+P3EibTE8o8eQUOmj4iUyaEEjBAXOcQt3nvSOyHI+AtQs0YWVoxovdHg7 /AZZsvDGRZeOzCcjuU1MJNqOGayxqC8OCT4XOkrs/GEUHmq0mZQ90X7hUtmFvQNC4toGqRaNJghb HTbjOPzQ0buoohtTPDothjNVUpQPocsIkSklmiEpza49GsCMEsYHPrXlvHuY0vdshgzgVR2KCQcw 1c+1vLywSYByXdsqy+Hd5zJAC7Ua7Du+sflYAo1Ntnst6OQt1B63RFcbnWG6j4y5+LrtCaXW1GsP FXmTWIHtEX9iGbwBCHosAzgecOxAsWmxxOp7isWAkHXBhNWcZh0Cw0MLpxvT3JUhHC8SIIoZSob0 v9G3Uuu9WsjgwfHyNHhiyhSizFarOcNUsDjAXUzjYU7X6R9wbK6u/qVYu7Oh0hNHSwpX1G2E2VkL p0tJFcXZkvKnx4RmIxkUDhGrhDVETDm9r/M3WoWzpbvwA9A652APephp/SbhNT6eRlDUNKLCeGdN 1wUEAwGdX9ERqvB543KHwLktkTHy7douykgyUYg5r2uvaxB9/8GoLYAyNyoJShtBXwRKXYqG6qgH 4gVd7+eYHcDHUvhlh5xQL3Th6rtsTHHtNKPbMuQGzoA3hBkU8SQB562iz9zKHkurfyRBvsSKO2XX DM9odLmBEz7hwRA3cJRKwT1P4Ifl9e4b2MT8dbqsdUc1FSzXcx9u5jrpVvcZL3f7ptSFS0Yd3sPc l8bsyB7dcbTpSzcJkQ/ZLRXxNg6/Kr7PMwr7QDiIZA/K6RoES6gvkpsOb58BRxBqJWoGkEVcQa9V sdLLc/YLoWNr/VzAMzNiU+CRMV47J3ebx9k3ZrYDeP30KawuMtWGlRpDY9rFvfZ/LRoYHo/d5fgO 2yMKhXuJNBgDqJXXVP42Se463Dse8RD8VozUQCg23lwBoZTlEdl8nAb45X5xD2clqFlciUC6Jc4K CNKqi7xmPo1kmdyWSfutzXmKMcJHbD87wiJPMpsM3aMTM/5UMWnxsBKTenqCXeZvAQzyw6LPyQz8 Vx2X5VaxoILT8ZOQHTyonUBx3pyVFNZneho6PJkKr7fageWHpVmnNRl9tEqVfe3DpJ+SRYt6XF4s TKKv/FF1Tobv1Z27FuFBQyS4LBC9kIpM9Icb3kGexjw0xdz2d6m0QiYy7dRgfHbIeedIBcmGyi0S PCnvrls2/GtOUHUa/nlVsQcHWE/bYKkq3wy1VL7shNEIBkvyyNs7eZLvVvJRx07lz1+UadDQf3OU gde8v/28hQPKKoTb72hI/LyzJrGUMQnCJmJK1x36GZTjI0eFN4i+cH+3mKjAFLyScS2GanpnvRG8 R8gkqnEBM4GE4qDlwPyJKjv8/J5a7Ky+HHKlcOVoImxAFNDEYDb2YecXNP3XvwOqU0eHRFDid8Xr 4/MG5spRKJeDUEk8d0+oGVGygGvvDpZV4bliT7Vh2hZVOZQCsnPcO57G2hCGLHatH1TCd5W2wmdy QRKbW6LI5oC27P+X/QQWG7ekJmPI+Fvv1TVECqR2s3YZlSd3IgN7MkF01LtvaHA6KG+GmkRRbFdM bYQBX1AXOvZeV+GiIHUKwCKP0sdCD61FMczx7aJbzYx59SHhXnMfjGHwhLbmmxUmonxBuhb9NgXx 1VI/OawwlFNbcO2yElinmmVlrzK9zmzqQ3hhLztPKYz8OVlBEmEbCc7jdGwoaN9PL46agzwiL2xE QA6rf7e0z1Dztc0s2zyWdqEFndduPR/FV/npK1Phq5XDzwbYRittxRWfMO9blpFUeIUJEZla/HU1 V3OcQ302G6IzGdima8h3yjO9NmHuC79ULbQ2/TCmsu6Oz6lirOXlbM6OICI9eN4qAyoZunBfZY5C r35Oj64crZeqrF8Fw85OhR0/MbNnMwNeiGm71HSMIS2tXWDliP56oGSJ7rW5oZKw2eyd9olec4LI ODT0CTg9I3XlftCX/BwlnjT9hq0J9XA1mbzx+TYNJSP1Sb0pXO1y33zMRwU0ds85jOlWAIgtCJVE qQrhBWcz7R8seHMDHGepeInsYdT7FkuWOGb09MYZ1/b1WYW1SLcQMZ/JpD0QXNLbKz9jDGChCz4s LEJeCNNIgoljLGnZsaz2aNZXhmQTo0nTkXj5o2nlzf+a/9//EaOM4O5q649BjxjIqjxePRTt9HSx cdJ2qR79XDp5xp3S3yB3BoPAne5o6vCH+iyYhsJpFTVacAiWVOYV++OQU/I2hL7hiUVVtgvu99Ke 2Wz8vLGXYXqmj0Uh9EmQ52yS2HhRwN6LGMZ3AEqbn+pfFRSU4PD8jRLnjJOM2XwOm/Lvq9v/bqqd aq0oWvwkYcITZV2+fotS/Z5U3WvrOJyb+Z4SKB5XJPT9qEYKGTbkVZYEhqPY5XRiFItdbRemkfcC t8DYFDtyHLS0GB8Qa478wmwumwNxYFz8REJawayKEYi+DbjC+/kvu8YKQLjj6jUXR+7pzES+xoqd 1mWH/YThpnl0kbaPH7bQG/jXKG7u7m23s2wFQrramh6MqZu21r/V5ED8IgcGnS7vRESEgEsEZXR/ Kf+scenaKAJJ0+UogaCcMDsP2mkV1k7fF0iFDZLh2YAiWOGTNFrsRPbqxCp1vGaMwVsTHAoyyLvQ d0TgVfPdC5SrTC81ASPb7UxnN2LsQ3dOM/YxQDzpz/zkXYrQ7OtAZbwKXNrlM5P1ZVduuRx3jppI mrKTLoLkopkcBIvMa6skNzpbycHK2nv6YbzzTccOCx3jXdFr9zHm16ec05VSUIi0OzVgBNjmxuo1 GlRa5Ulf9nb/I6PRvHLxMyRARydo9DuGyQHzAt8Yt2gumTAghZWHNcKJ6zgtQECbikieu+iVpHHd CokOgHLO+B3dEaPE42lBrVhHA5bETyNszIdXQlbVGeob6qqC7XDJTRKc8VyhVnulPwevGitgsBv3 qOqSy3t8Rq/HQu3oUBNsDEHCDoapExOpx2Qukg1i+twsTsdZqtHNu0w/SWrYMUROZvM1K4qhRMk3 oQybKzgElmjk/LG+H5jhbI+D7HWkmlvRltZooM7mQpoVRLS5RGY/cHD3PMrP2xp60jZVEk05i4F+ sATlKAAdU1jtQuSZgx/gcw/VKiC7wHUz7af5cJqTqRG2X0EQaQyMRKhxEeV6+QA3x0GyTwHD3HHt EFrp2sOoAz/oFJs031cknZC31jNmFmkjxEzVStJKWFKEwFW9H41BWLvJRa3lgmo7nPrxXNoa4wF3 L6QeNtF8E53e7+QOxsCdS23bD9k3Lpfl0n+gemiJoiOaP7BPpivCWZs0/Hk44uKBkK7v/bVYcm31 EmxxM+T1aKzDHA9iVFT4DI0xyEz/fiZYj+tNDWHaqsbyyKDD4Ibi0Pic7SEhd3Dx+P/bMr+YFJrz S434AmZ8DMLL1/GBv3FmbHo1SdTU9Kc2YKl0HXoSaQV7ANQDKWyfyNkD2dPm3mGpfZ6HXTMiQBiO PmFAHSXS5W9aoAJ439zDXEzRvtTBneO9Ko+cUZhyXB63EhErAr58yrMhLpSspeyJGU/2V57dF1Z1 b1TVBzi8gP2GhXNKjR20e5h3/Dl34G0c+9mE51YWcPn857Blefld+76RAFUc0Or48mwniI/2fBCN N5lVVWR2c1IjzVw5Ypxo9vKViimmPTfBd0MXiCazEY9rC7dFjXE7RFosJAWTpgBLYt7zlz1KOzKO zc6jihnClazOk5uyCny2nkdCQmgrKJmnFsnqByrVFwHCWB4oZOZkaJ6jdnta1IRppfQVsdTX/txl eLDm56nAJIeRFSvzYeGNZ0+7VECDGiLOtalJj9HndngfC8y2NBn9yHi1hhhjCOzdhFOckKmCq7fg EShOnMWsmLG/Ry7fhqvaKqBatLdtvpJj3/BFJs36xqdKmPv049aRBvrDEozI50CakdFUl4Y9Ry3l YIKlIokYJt4SLixC5I/Z4SA+eDyJcSWT8S4iBNnkWJR/ET6MvS19I04sAXJAwMkO4+Gja9dWjuJm PR1WfvGSyvpMNCDRt01vOwBggrwdrgQrOnoCD3m3jNqYrtYZ4tAQmRjwWfY98ccW5hliCskblNma puP14uL2heH2SUAm1PcKe2rRDx5huIe4H1hLUuza49Li1dxHS+k4zJK4bpOJyGMXZiVlL4MSTimF GxX74o70lZwPHALrApWGD6xYPiCnDnrhHKuk1NrCzTStw1HU/ZxiuZY9ULNtUAscxbYR3EQ2msag vvD1xAJt2sFEgVF96FVZf3ZtIxlTWq7T4VKTru1GiS+k//l5vqzQznOdfIB90egKAMxsBkYBG1NQ IeHYpukN6wSZLEJxYd4eCngWiX4RFQw0+ZjNpfH34G4mbOS9DiNTjl2wplbZtCuSKAp/YPQ/jjdy DQJAkv8u7gN8ivM+GSaK90fHE5CImRLW7mhsXa6xEnMAHhsOU8/XmApbpVyrpo9AOZXq7MpIRHvB I9+6Nn8ikB/THaHSj+nGMjPzqlnTGP96NLYhc8Ufx6EI+weTd2JLD9RC6BEMTCqtfjzQSzM58zJU DpeXy1FCKRom2iSRZbrLlmu8csRrpLjWgXqh3CPIRNLNQALPPETG26Aza3XugC2xiABHp6JNPyLE SscvsBhwdjbpjRYoZQ87sByzqH30hjlB3Y30dKgVal/OSQ3iiKokDYdv9Bof0vWBf/7Zy6z0gEdA QG+21k6YnL69r+Kitdqt6eRKhq/m8E7seyQOWvSLMcjocVnjfhgWcJRD49cxU3scVIkpLKAR0LRi jPONf20svajBdf/e3YloFJHvo9H0ofrFoC/JTepJqBw9p3aWaKDiX4YBK9pszxHHjxBkv6/YmToV akJM7UAn2221zRwlVRuVxQua/lZMUEdrRg4tgn/ZDL56pfFWO1ecyzpvO1AKpRs2lD0LtGq+Pam/ s5hqWOfCll8xqavmqf5f2zrLiZs4xit8REDcdr47VCSP1nTWxthxuPH84Dnzlm9FTOYRdmC1HqkM /EIYCY+vsl9ms9g6lVoi4V7OgZUcZNnqChDyzxVh7O3AmTVQ/PJY0PlbrPVwFtA8r1zNLg7N/oF9 NrY3O25+U7006Fqfw6DJB3J5ZRWL6zJdabF0FMbZsQ8Q5Ti//fHcgdc1owTqHczRrmamBs+FNMUg xgDirOBOchkFLDINpdNypPS8Fi6BraXgtLUJIjI/z4V1sGOhYqO4iNpauWpMnPPbmM62yJkJeB1a aA9Qp2DRK7JNkdSaj4TH8rqLZvFg+Din1/mrvNeLI5iuyMVOunwlXXUilt/rIhHyAECiMJxsgRf5 aDVXG+959C4nT5Hxg/gmT1gpGvmsHFo8o6ENujMo9Ab8KhpTXrfrlRfHIujoSR3NO7aLlinE3xdb dA2yf0l4ty4NwaSVjDjcc+OUj500JJJ57gBzHFPScENmzD4s1KdYj3Gfgn4cXP1ut8giYgTKVz8u rWZgUAURfM3EeDxYDQ3XrVk4Bb8P3YSAWwK3DbGaW0AEduj87qxyocSxiS9CBCzGsPftgNHmHhlw tSaSatN1SOIGP/DTG09Eii2fU8ymYWmiv3zCTAyx91H1mqxFdthRcq2Zp1z+xzAP42iL7YWLvx5C b4wwZZnd2+srdlMzm6X9G9NmRnN+MrYMUn2lo7jo0rHlQ+rl53nNQm6C3hSyyxr3NVTwPE+80chD 3Jp/29VS6G1omBqJaYY9FBMUxfbwKkumwHjTlM8l7Y2wR+d/2uzuUgkMAMVM9s1spKU1IaBI/gDR bMkoDw5UE0TSLfGNOvfevgMNgywXwAGlDN3EoIBAJgbqn7+1Erul0LkC+T41SSeSpnmVg/A21Xql kir3X+Ht+3lA/959Uk7YD71D6Wm2aUCXRFK9ZRzcpb5/6OgIZnui4O2qnhBxWTTBKBtEg6CrAYHe 1Vpq1BOKYoUH6Z1Tq208KDGoHD21pHMyS6wgJMu4qAZkWBzLJtaFr3M81UYQkc4ZDvCmadUi6p7B Dp1aRIPVTSazv+lmudEMS73je3p3rkwijKmnM7ehnA82lV4GJ72oEi7hRfVF1v/ZVuQM5ROOJ3sQ VjyRKHctsGZyyX6CXALe9e1GM82Zsc+Pio+AQNz2CLW01/28HQmiW+fAea0pHXblDhho3J2BGOUJ 4KprGRDro9hZMOECGz/LhqxJgaqGDLHT7FiycLyUQlslizNums0gkdkK8VheJ4SeMBcIK59SKqpG 9nqfqZ4eNA5FL3s9zbmmuhCgsVijbulGc5tqKxYdC/HIoLhMrQJSnRyXMGsswwdGtOUi1//GGRLy 9GJ9N9hgEbQwPx18ncsimy9XZsx1Tw4gwb212aN4fll5VmKbMX8CQULJt6ZAzaOi0Gbf61lvi1zJ 9i47CFdjfhtcPwG/WjfZ8KvStM5QmchJGImb6gZ657v0ZsBMVfOIKfoy6Wnoae6s+ZTxwCbxMSpg W8C3ujzQmTzjxi6V2JXE9CVf8ycinvKscnWdUi8wm5oi74lAD9qN7WdI6NfYS7/IwOwc46etUGFV oYdz28QndIriptVP5WVflU8WcLlRdQUERoTu5ed+PycSEYvBifeqkfQnw9XRdKFeI6+M1GWQ2kQ2 zsrJqofRSUa9mlLGXJJYer7N8V/VBSGVhgbaQOwU+zHP5Z4MMRGEAVoC3lWcFvbjcKsdx4MCCH5Y QKyLXJw/tbRIvf0zBpSwwIMOhwQeOr4cBG2EJUo+eoKx2wm9ylCe+o3QkjRGAi/RJj4ggPZga0zb +1w0apeoGH6z03pbhBh/E1Bgyweahm2ktTNICC0fZqfEbDREwaRV2uSToEHiyRMJgRl6X0xfHMSC yBIGpF6i2jKyb8kW4IM5+F8lRoE3LSUUc9rqP4B7hW2+vJQpmFhmKWL/i7eiqqgQnKz2tyHO/Xwt skpwXYGf/yuz3pxvjyjYPkL6YiIJEKXO3lt3eedGsWVq07chqgrntkV/YKlRWRa854NyUdtmBNAW ca5Jz1RkQmSXcgku2RhSgqqAtDKpvkimn9B7f8+pu2Cfyqz3j2l6lyFTPBBLWamg+QEMfeBeFySA GT9ojNpYHXMub+JLEyZ5WtRxra7AoKaanFiZol/E7B/GvkbYpn2bBIJBSwP/eyZP7HgRlcL015wY xYJ04cXS3sy6VYKAxKSMKw+WzZEsQkO93Oedq105ccAeGqccPq27CQ0mtQMGJqJWZy59G5G7ONYw Q/2DTmQ0Iovs7j45eLex5P+rJXyJ6HNzhjhqXNfgF6RVBLQ7zeYgQ7kus+K9PnmwWPzCNNCCm3mN 0y2WEBHbyiqpRL83WyrFDMp4I+sKm8mlox5y6+mUtYrTomut96WhzYsMu/MDwvLF+AN+4GbA9VNL HJwAN3cLLbYjnFaYzJ7TBI6Oa9p7rQabi24cWxipVFhp0hjnPe5UD/MKuaeX/8+O9zJH1jES8InF +N+LxxfjIO+d4B4ee+osL48jT8zZVQgv2Jo44t2Gf5Na2dEUe3Bz2OIyVIjQCbo6g7lADObBz+8I HftZi3fkJubWRzLBiMa4PWmS9VAnxZ+ZfZoDFBfP4OOSmbB5j6IfVz0yElMRidJUAoqmv0mt7nkz n3X8G5G3HvjzRiQ/O/5R7ZrdwbR22vsE3WKKyrXPxzatlLd90tplogfdHRKoR9iJ1K56QCK0Jz6K PNG8ArX2f2LFQAvVDE2NgSnAllnG+1WApaOnaco7LfQsXNVbgA3CmfkAsuq2fKbWLNcupNK/GM/V 9JvTRidpxFSMbTLda48qdJGyHn1f0AUnHrjZmeiIRs43+J7y9FSoLtJtnnZR+KJZb4Y4hRMwxJGQ nDwqNHXCaDT0mPr3G5lCNxROe/0Um66c6nG/4DlhEHI6cV1rZnS1NkdS+P5oMK+cbCnFhfXI2ftz 5i9Qghd08AQS1Bw1cYRBjFIc8YXKVrLojeX9zh/JOYKHj6RgtE3kuNwHK8a05rdD15+uEBqxeCmg gUzC1rAK5gnTs4l3T4wgFmLMO5l/Aye04idC6w9oQUXI1jbUvRXV92rTEhRieXH0P6Qf9142sX0R 8/o2S0Tzy0ppht3jMyV7Xmpa3PVauXYHiXb8gQ5NSHC4+lw+xvjzUthZyoat1hvZge6xJUMYPVkB 0q9SMQz5GTmkSoi9MDZf132Y8UdR6KTwm03+x5tppULA/JBchXwDHD9BLBDmhP97vW50eg/Ndmlh Cm5YQHPj6r4Rv/QP6YqkawPsINEqSmhUvpWM4sM7RNzABoZIubBbGaUX4oG//pcdKlW/2UspIAPB sVOt0ChwE9IBYX+ePGoyQJMZS3o3bhUvixG14hU/bQ8q4FTOiOYHjYYzUPokNDLgHCEfnDq1nDD1 eTEKU6RGyGYZp/+M+angIgKWJ7GeD98AKxD99+4rG+O00gIkiCDu9GRExbCXVUUKr2dg2JC+Jy5K /gz3MdTEhX19ol/9SRaCbuMf7p7IE+AMLfMLeeLRKiNF7vB9q2kcpHdIUltNTTyrovmgAsOkIbUG mGHp4vAjEgFlpAZmmDaEd/Bgl1dN6UidfWs337YJrq5kG9G23h/Ny08kKvvzm6MteeYPqS2hBVHY zbLJ5NGpjZLeWsqX+20tIZQ0WACPiCPeTho6sfarLIEvrWKqh0AH/CmqEDrhEn7DJZuotDVa+4cq VflmFCt9klgAcp7g2YmJSUKyTJRxCP2IwVd08ZOEwhYgv5NX1QsVhYDWwD0VuIf7midOAuOsok4m Hau1mF6ck3SsiksLlEFnn50VNv76rCLc5pDxiJObDQ9bR1epgX7zxRDlXe9vPcHrLS5mkBc0yOXM 8POHr5GZE/8NoujeDbqdnFpi6NyUZGRe6bQJ6WPI3LxsTALX7OllpYNaLHTi97hIaEaVGZ0mxMPo dJminj93MgssUJOwOSGphu2jXAsZ/E3l4uRrahh8OM+9x25+3HO/tEwDBbadei4r94psF3vu2FPX Rb5PMVWc4sUExpeuK7z+ABRNLjhhExXZEmCs2qYH6SrVIUMA2lVwnFaMLOxV62T3o4eLFAwlAl8i n1A0mYMI1UfEwlnxwFUyxktl8gHPl9/S82DaK64DAiMTvwahLq3HAfVz4FkHRPaP/eMS75b2TNaQ yf8G0vN1nH7G6wGcHUlWPHPfLusgjkvdrQLUcwJnGUM7lxCuuPGG5lPLevoX6n+XP6Pp0r9ykK+s 8rN22As+z2xBOV1TYYax/HKMfaySmFlSCBnguc0czqB1SrlzDXrQJcTgpD4U03d1mfVWE1Sgda2E kgKdorUfg96R0+dUKTl2jVtZojlj7MctlcX1R/SX0k4f9ex/sDnIglOfgffjIFzv52AtWoV+gUr2 1bW1D8oRu2v1GZF0ScCj8O+YUpIg8/lRjK6fB3+lNocmtVyHN4Kg+e7jtniDdud1M0vL0tISJKj8 l3/nMA/d0GGQwm8fN/OG+vKBmKLHCLzdlJnfAxUOHUDgm5O2dBfOE7Go3+Y686JJ0UlZlhohu3IK 92T5CWd5x52Bp4w9AseSAe5Iy3xnGKfPIbcXrroAnf7M9QU2g3r97/B/UgUqKLYGcS8qdZfaWjYg t2hG9Ua1y9+wyg2g0tTxdJ3G0X6p38oDzOShXFHjKV+EXEGQpb3U314OJ+gT3+8KdY/Ie7SlYa+f 4H3GdmdlXu0wdfKm0l1spb1zI8vWyLG1DReVX4DtjQ1+9aXpyFsubKwqPk99//j/Xfu/vQgSFfIZ tEdBSusJhH6fNIenUiItT6XcDv1vPAwdmOU9Vp1J1ZYEY0SdmHxg/S2+7jZcUod24AA54EVFAp5H KPExKp7ti9nGf8wT8KXWh/Fy5HDQYz3M5QGCL2IJCM/5zpnGxYFYsIC+aJ9dYgb4BYv6Z6Ai6o4D dImHnIcKq2V1NRAzb6L8lOsvQlXYy79B1T0YtlcAtGs6Orxb1Lor4UjLdbyEHA3TyH3kxOM15VCu TwBo+stL2Z/4qy/OSQto8HQfTh7Q2xnzwXNHO6he+TNEy2Wc6nOQUBCJ+P3mmA8JZyLtpN13osRh HVNIiYPTzfZ6G7Jv8ZCfYpO5lKbQPeFYohoXgq+lYU8/KN+LUeymCH6LE/ZMqIRoCBKrIj85Kdvx Tlxbt1crDLfGJpjgBACCb2osSnaZMRlD1Glqp27SzY8rsUvFpab/6DQS3SNc4nd3a4LT9/J14tIE zWJ3kCgVR6W+1E8gNSkaoxR7JVvBVPPgy+QdY3fYSLvzUTmlhPUypPysLG8uuaoGFKa5iiH8bn0q rzLmdi0P51zx65vW15Ys7ukvInLT9wSFosSU+JykXKYwO9PvSenlrbpEg4z6dREQhgbCDToxPsya QNkwwnH/xpjBpWMwA8PMSMiG00si3/B+IOWX13S9ENeYBQglL3AJWIuN05BBetMUM78pSJQznSMs AsE1Lp+MS71x4VxpjcHLDMUV5aGFZ+QQiG4VA1VHKcqvTs94UStECuUY+na8viFGK+oHUkWF93q6 saSVno7qfBSKRzRlkLfVklRWzqPC5hELfxLKO9ksEZpqcm95h7zek29vib+eten/6dwpRGCf4G3c +MMXTwv68eIMeEXf6lgkARHKZH/ls0q7t3yEnNQaU6nJw61rHkwYbCZsXDC57zDrUzgVQQINlq6f CmLOvM1phQY/mAsMqAz7SSNwBTsVp/VZ3AE5yGlMfEquB2kaPIyH1FXHzDx/3xz+hBJrq5+6eqqj k93thEdKSby8hxSa0AZ02tY1CyP/EpIaKlvKTpemkIMoSLbteKtWOQOlJfqDAvNSoA+n8AJQRIkn DLYnzB2LASIexCQRF2eHWCZTAMj51zDHHz1GaQ+dnYkAdyJJj9lYmtExrOm5ul7sB5FGhVYG8zqn 4RExv3vokWK5lRQL71UfPCSMcQMy3xvl1dfuYx+6GVr7nj9qo+fKTP5G7C6EWTlM48aXad8Or/aW yhc1g/+8wEmgIxM6e0tQXRVX4QqBibVGHSdkDGMJHKI1tWvbBUqy+ZZRG8yHflSIfIl+Lvi5EaRM fMrB44fu0sLVyg95iNfcc5hHjjfmRtwfLpdLgmIBZnSPzl3EVhePBQXNzCwNDEGx6NPwpr8UIiv9 +xy/4LRhqvUgRc6wnCMmH3NQdatoVR9UmqoCXDfa36mIGcIUz7CbE1mVhqzjQgCDpc9It8MXwigj YvCg+jcLVRffpat/+KpXEzAIV9uXm8uVYQ9YB45iPvNoiBw8fodhSk9RHwKMFigdEgu7q4HRgYvS pE8rDaNGB2nPMXqWf/xmdEt1G/BujBDt6rBVdzJpsq3P9DfsOEl6/6h+8LX/re+aZVXPNqYM4iUN IGLFzg7oGbOPKVzkBDd38H3u8i8vM8EB7uSCLwB4JNA/rtqEQ41MiIkYfQToHScxiK2eGelLYLna tkSUmdTshY00nzIlCNwAW2vtuuICRpw8I8+y4Nu21iMTjPvAD7pK+ukAXf+UUejS/4MIXs2t2WWK FDsIMinSO3MMUnjp+xLuJrAkzZczVE/DCloqPK2TsNWj3ckhMWfVBr12TBXSqPf+UD+m+nFBXzaN 7JGnvQGzIOaj32L22ELyP4AuOMMD8WfOSzkqgQJIn9PROBLkDrYdlWqDaoGufDbUuxEzbzNdCuY7 CFRPMMR8y2Z8v8DMzC3o9mF7Ee9+P3gZ4B8fHUlsnhr4vEiA0ZsHZPGD4OD5bVUIsxJFAS5yBWJJ OOPyyIeWFYShxQuwjVCom/UuHDGBHCgSzxPd9LyhXq3ztDk9CPsOVu55eF3yCznpqsY4GDbS/AEI fq+Jm5EPP0nrJd5vVqpi5nMHXJrrQ0LN1xUM5YwUx6W0oJ7DFAyhcFEMhlDdL+bSYDQA8RPUt5dk JkMcBtRCpxF5UIbjwEaJWjoiQ/1+IETjDjntUwRixFkF3lyeIgHN4gP7RDdkgsOFHRHjQC+Lr0Lw VQZ/d563wSXKPyhzJG4Qi7YyvvfIjJr5oF+Q/2Ryl74WU8m5NFgejpt+lPph48i0BfFt7YqUjrfz jcvpYUrm894MjBajArLmmoXqEYJrch8VbaeZZz4nvkYNOa3ufquOxvSpwZasJq9OJC91m37553ms 5gua5OVFFN7fFOvMLaxsv7AJ6YAHvAWKtc8T+U2qEu/4W6lh4GywPRZMrVxnLt3uY4OzAIDYufjt nE8vKVAoecJBAO4X23wvduoxH+5a3X+BPX7T/JIA+jlInr55UeYwc8pmHTFn3ApJJlFfLDys9ikp kgBM5AlpMtgscnPRRFdRw6PfTsGrcRwvaLrAr6h7lFdEwDRnSNSFysuJ3bqyhV6zjaemcRSs8kD8 Zs0r6zxSsLILGWuT1xuVxW5NWtPCg0sdHg4ERnX3hXtBSBMUi/IVMoJubyyXasVnVKXdgfjK434u bRT9Kh4RVQqNlAXmx0MJabATUvAYpEO6Mdx1nU5LdCP0sw2JmY7xLjuxg3xyKF//WQlBz6YYDm8E BWAicyQPDv/wRF3XkhSPKD/EzWLmvHdYvoK9tSDYwU5O5StWFBFgfFCwiXRKMEs9SzmcTLZJIMoK 3d0dRm+FGHEqAwENkLs51OrKPhQmdcOigPU9vx7sw3wQLoc/aO/cHvbhOwwAsTfYw/A2W0j2r2rf r+voKZOmXy2kn+lJ9HtIOlcMNxZc563RFMshjbrJGTN4E2OyZfCkELelsapXXd5lpus1jTPTi+FQ d4tnQf2eevkWJ3w40w/TNEOuboev5fCn5hAbVK3+BKEZz+F0qAqwL4/NKtRupAKGXJhKDvMjyhzF EHSDMEPwFUuzkV5yWT+GF6PrcE5mwFRoJnxwOYih4e/CryJMJGa4zKfXl4aPHoyjfivznJhEiV/A bREGhLaRrH5XoYmrUPjoQ6QOm+SM385dtq0tYUk7xmDRZLdRxQsx9e9anR2Tfv7dl++wjAqz2yMn xhQQxdEC0aP1WNtIAOR2PVToj/TzG8GQUXWBqDmhR/MwVhjXu1QYc1kzKzgHq+Os9MW8WCIPTFSw e4D6sN57ziuU8JukFt/BvrQDw+mTO47DwRej82P7ZbUtMXSittwT8S6oFl4xJ/sIW6MWG+Bz0RIf FAcDNBxHzrov0SxGDHY+KSCkDFNElqsEu+dT026mw3jUwMiC+cNl8ZUNXIZouvWtWlGAHFepGtHZ LrNg/MosfphA8PFGIGk2Pasl+lQj8b5RTou8BYl5SPPvAGL7g5xp4zPKLoYxvZuHaOStZN0/vFcq yT5sIfB3hURRwrCjDgMI2ALmPjEGEcoLcVAIN240C2AYIKHd/oN4RsoM+y5BHmHzK8oGW3jdMwnW vWAOe/bB7NN2XXLFiL/U4N0YLMBAR0zbWSIIkROr4yBl9PUHKQhm0pxzvGlHFDd54dyO5y7qhruz 8ztLjpS/C7r4wHJwk/npHlD14xweBTWAYgtifEXtzSilKHZMu7RIwFwIhYf6Z7aTXBud7DbTuQru mrPAkHS7J8GJaN4ySCdGN3uPbeeyqyvRXNJPpeWUiv4fct6q6rXI95ftuAX3/MFiQm4qGh11p72E IpoSPcIxT6gBHfCPqN8e+Fq8fLSZw7v/zy7rVmNsQ2eCbJzFpfnWez8iTqJWJyZw+y3G2UplvOwn J6N1ajMEfHiLvV8s8OSKVFCmgy82WJbL0TY/kP5SrAYkefW/Dm4Oht0WNspYwHzKHs5V0LmUHYbU d6dv72So8UCeRBjP1A8pl3KNHlKvaw8idWhYSCuj0dsXCl7Q72avxLacENs99ysYk64aoJ9YH0cL pYyjgMEjPbuZIK7t30A3qCx3Bx2WqdpsWNznBvEght/6Y+tonQbbZG6hH82xmz+5ZdDX/FI7AOig IE6SNFbRpfZKh71w21xA2pzAUTMcR0JaC8y6MbU6hqlhh2I8xKSWM/x+yjlcxc7NQreqIGs6iBC6 gzdU6jlvxYl43BJGtlv4Pc39EpSgiRY1sXLPAit8b5KlUb7/EsTG+snMaEjTt5l0m6bmm5ice/n8 jEYM2gaKdUW+lm0dGWXlq8+TRuhLIVR00vCvrDE2kw8FE1wqEV7KvORUKYkooFFf0cU5MMuIKlSk W7MOinp6p5Gd3e+BEGzzMMNUjzzxhta0esbLQOfxKljKaYmI5M7/qqRmMyBV8H8pcRDH9KKKjTmp 6ayOXwNoZQU9iV5Jb2Ps9vfE4Iv+q1ldZOCwRE3M1IFm2y39aAXt/j22R7IvjdFRImBxQTWtpHhN 4M36HKHEoXkIAxEJnuKSAvRmQX2WtpoXG9WJ6S+lvgbSy4HQwD7my2EzSXFpqOxeO7eO4/p2TH1G POL0aVdOAXpe7njfTb8yjIJytRm0VIwAgYigZBqWtMTsYgapN3ioZ+L4/FNxV7gjoJbL+c88mIg1 mtjWZk2HssO/YvVlAykUPQfjYLNOZsN5WJjZDWKL9i+vUHmcWTYhnKqvcy1YMqUN10JiDeaNkiBt 7/0Jj6vyL93azVi9ywm3shbz5daAorX+fg+U8DSWU/JPeWBDVIm5rKss4y+KG9B/Hadnt5cKgd0L bBjBR9FBR65IGoZUVD+0OSnQ5p0bblhbbwk7r9hH0on7jyQP15L8Cz1/Tv/QWWsUTsQ1pF4kJJNs x0Kmzdp/0DTxadICxKFuINGg8PDeX4fC35p7yZ4e4zt9F4eMlx0OWDLvhZkqRyWMvVazfX9w1lSz yYPceQjxXA4KbD2ie8xtVidfv2ZabBLY3b3POKgGOVGdBvviMVAluXf/gTHOzWvMECKrNFuOFzZF 12x+CrpHC2uxPoHv+8qvMrusV5zGN43YOXRzW87aPq+mG0D+hKBPFLEKY5CFS2w0owQ1+H4+tu3R yduflUY09N6xiTnr/V2J4uFPH+RlbB0gX8KfXcudRQSTsCGFgDry62ApyQu26fKA6kFNgZT82+KL w2Dy5xtqrYHAYPZSz4kK5XW7id4RywoPbnAHNM4r/NJaQX2c/twzGfcWH6AWrTmUmP7TPkK2Lz/I ppJAaCJ4l+VbkGYbIqsYPe8wD+HP+ZwDHiM3SQKl2RzXO/8ITwXuOAQ+mhLO87R2Rtn4duP2fBOd iL20pOlFQ0ilRuJDXXROaYwt5daLGDe+P/L3KRiGQVTBEhOf/espHpF/Cs0H/KAk1/FhdOcEj/bQ A3wOeKZPP5IF6ptQ3ytBv3hBajwCy3mrjyVMxlD7BzubQry36FRn56wAD88ZSZo7VdGsG8ib6lLy 4VyJEpOnJcZlMNRA9/qTEme+OBqmRBRCAKDCDEweCByKwmBnsk6XK/JapYxbG5xvCdNWhJo9JT13 NB/DGHxiyNZzY5TS0ErZWAYzirIg2YatpmHdE1sny/fX39c56JVCvpZbt3FIexv6o9hJv1oujQQl vk23alLjVIBBsqHOSBy3NAUA0nPpzgWm/GngOjTfx7CvMuCtO8m2lYYc2s3p2nmmlpjH7zsJ5zRj N2WeRKqbMrFnzqncr3XLMe/xzP4Jhe3Bk0fgS+UI+w3q8cdu9aIVOtAKLHOnkr36Rvd1dfJW24Wm Izchz0usmJCeNCHrNbuhUz+/i4V+j+eM4PciAjcSPsEygyLsMa9pl5pECWcauo1V9yQTooSlVo8H VfAtYOmEUuyostDUsBJ7vOV+BE7Finzd0Xw5P6yLTo0zjaj40NhT6darCVt+lLF3ODCATwpiqpbA nexCaXxnkN0VtUjZuQUFmFrVMELcVJorIiQC4825Y5XcDteKq3ZrYea5JW1dEPTer4f4C3sDassy Gd+bhXu1nQlSIeFtfXY0xiSpZXLuIkRYmG5yt3l1Z8UtcpKqRTPGgnBeeRLw+kTQ9B0Ewd33x4J9 zxemquBtkugfN3B5atF+p5s7/ThVvbXqIxz01ELFtxeCpMy5cnC6TnqmlaUrHCb7NX/htdeC5pDN R8DLGijdP2ET+2xmkm0DNeBl6KB+Xc8FMBKRKSbliVrzflMSrs/jK0G6Jl9IYmQR98eqieqzWKmv oudqmxDL7HZzBaNPxrIK/bGsjSwlLHdtQKjfi9opOco0X5TV2HHH1LvrWvK6DuNaqqJ+QzS+D5Tg eUul+HFq2OfyUVgzp+eTPapJAhO6AW6tfy51alr6FJ10aDsE952qcs/vJqgJhR/G/9SAKLH/gnca oEk1poeTZV2SAdpGN71ujTzet18QdHmUz0Uen/+68xPO2GUtow05MpZ9OBdDxlL4cBtKJHjM0vr1 tczqLx4JPlwM5ZJqzzmikAY7u8n7K3q8MUJl1e/q+pkVcdiRRq7FHBvBkl/3+JizEddqVi9cCx35 fQVzr96qgNMGbTqCi/oPx2KJYVbKunZeJKyuWdLIJvd0vl53FhhSKaqyTubmn30wv23zBe8njBLM GM1A+9ZU8upA2v0ki6mFx/DNQFyLvBBQl2CRpM4VzgcQKaafLhVA01XxUDIPacAxzneBmmZSa0/J Y8wP/siuOk0TqHv86+0V9bN2mYPqnuedzB1I0KiXYsIJDj6igumIS730oZA8U+u/4hSVtmmXOtNR aCzvB+JKZi8o0KMj3xc7D8XjkRCo0iyY7DtBFbJaKQCVIgNyO57Iqqv6oZmQuaANs2Xn9IK9KtXN y1WcoC4DHSv+cqHfRPULcrPxA3BYUDDhb1g6HqUkYKGPabtn++55hG3DV+UiF5oUfhCnU53iRgoo B52RqQ0DjJGGAN84ujEefyAkTng703MaFywpWJ72WySSfcgrs2Aki7CtZatdqq7hV5mLb4gOnNJt BV1r2byucjPk4uLCKkArMyB3D88WkJs1GT+yQLMWoigK5iWvogno6HlfLYjRx2/jHgXUpeXaFrtT caGAmSnACrIORntDjYCerZNkW0brIKNfDU+BIfFG6nbWFPJSOSS91Me/vgJM+REZDLlsono3hC/0 16FT2ghxOQxdwT9FBKivvaNcqLXWvSRLxOc3ONE2Uiw1DvLY7PhtT7WzXatqKXHRzfYvg9C812pl N87l1ZOkmLNKSH58l2BTic0b/TJjeigebCcbKtN53gxh6B6J76KwW6adWJJupaoez+8Vb4zHZu8W Gft3EJOV4bjwZAdxVKKexpZkx04AMfDlA+rJpx1k/vd9h96Y/pVtdRcVVFCB5RFs5l3P8rBEyVYj zxeVzHaDfd7MFpRKFkG66XIDnWvMpKCOr3T6OffT9aVE07uCExFjYS/t3Kf0MFFOwTC5x++E1Qx+ Zd63XWrHfr5ZQPtC/Vk0oqjMXekgr69K2Gkkp9Yv8da33+S5noJ7rv8A5k+awB+bdJBq/mPX0BDF /XDgBHNmS48ItAGOjYKu+GfXfLYwaj9zqf3p0hb6BJhjZUcu3FMtJz5KCa9hxs7SRZNaYghE5g39 Cwp0xMrhFC2OXOKKIDaBQ4UxtrZ+7t1OhZkIwRE7e+giHH8fdDrfW6NpVRqjagFf4eHK5stuIniA fbDB0XmLjux5tDbz1H5MleCI4KOJ6mDv/e1H36iYflhVna/gG17QtLINUV4qNgpyS+OrBbZjnvhl uqI5Rfz2XAjN4HsWQ5KIOOkWdnltd3n/RQc0cKw/AEuaIE/I6+PbuB3eJXopENGH1MLmGU7FbP5s RTPAQmU3hku36YIlxMZNL5N11dM6gg7uI9Le8sCnb0Y9EkyrzjWjiMpJhGTR4aJzv1FiL2Xtd1b/ PLiC2sBFRM3cKR6OSFo5gdMBfJBuDtz62OTlfDDeeo+vk9J6ekVL8z3kxUkS47/wDk7rtvHVThZJ oXjmi9X0abUF1bhljayG5zNmHg4VLTCUi1SK4iK3P+oIlLEXbDIrbyCcuGBlqp8hTD9RSM2VQpM5 ZjduTHcBsIHdbLfDiF/A5sgTDig0q2woJc73VBGKD7b4zYZ//6xSiti7RoByP4hPhl8Y3v3OpRyO +3w3YXMEQCuElxnOCh+A+iFyvkxtzO/xcPw10Yi/AmlUpxo6JWCGc3xIHeoqqL4m/FIPBK9H/rwO ZEfY8i7HwuNRaHpeCtBWjetAvU+7weKlA/qQZgq7V9EV7KPpVZ/PQqlW/TPRwVWVK7l88qYtaSq9 nHzi1QWOZ4dffFWykN3uT4+83kqYoFGvsXk/gaAXO+GzruK3x7GEOAsjoMDF62ECr9qMyfQrTQoQ OozKUeJAXnkn9nVCmJSj5cy3pc59EjZuckoVMjszH0mtjRxKNpTDdq5Rm7p+Ii6O4ow7Ba51bVEU 3KscFYmSMUao2aMeqPT5CNUuSiYSWqmND/TKH4T+MjzzrYQAHHF5iHjn1xLjQXvMXHMMqUT2eHrX EkvuYC1cEEQaAXLiSJi3KLk5Xje0voWM4j1RBKFfoRlRy3HQ2IM5DxouW1ZKkoHQCTILwCiztKJf yItawJ7Y8mZMBSWU6gKBXdwRAp4UC891GP0/9B8K16PnV9ejEasoGc2Z8HW4YRe6ammwnatPC0zW WHBokMQnG0SvTzbP+JBmWoc6hU8IpmuOC+BzO1aeQ8OaV0Ui66D72AV861OSqPJ2DIeusy4vg6m5 X33QZLQxQDbZrs/tcoN3mZkLJGIz/y9/OkSoXKnlYZLcmEfM7BCgTLreFjlsry6kLzATWoL6jNf6 PBIOk6zZsOY4E2KNyuM3BYCOaubbG981Q2RPQlxQZWjyYpkpNnInmzxJS2iLPXHKKUCFxOFSdx9E m7+ldH2jZeXok5jBo3E1e0ldrk0uwj3CLMuGMZFrOWiDTculuZ0eTKwmd9QM2jVXK7pyReLOHiTR GwlR91olCwqu5BLIjiz+a6/n9yDlIsJn4NV6dKOolqhp8n7uBsw+ovwJj7H4xmACJdVuZF3T+x21 /Bq+NAHBzj554gpzpwb6Ehl85LcAOHu1mjvNlZ8z1KoOMT2bYAAlEDCVG2AMjxvLVvWyn23NbDfA lHnr886Uuh/mSgTP3L4RB67LlOs734dTNadnf4FQhPTPjw4QllP0yd8vu7rZgmmvzpWTVMSb+q5A bdDNWBYTY2XOZFX82CXEY9EP1dfUJ/oHRPn7SlvUP8IQYixT32pJEjXQmxlU5LLj/GCX71DXaPJH gP9HaTktUXBKXnLm+vlKoJffxWK7QZqNK81QY+WO4ABPCxQoEIF9X4+tKD8O+IGeCOSciINlfWay hDbzJ6QA+JklTc9odwQ5NitbrgjGOzjxIW8cIhYdplxF1l5ChuEQdE53nZvNWNpSaZUXAShC8fWO 4ESsKHQBQtijT7GWMEHo8V3A15fLdbLSgQGGbBK6HNFjRVte2knQT+f+7JZ9PZnmY7YXVkM0QiL9 1652TvBvBZqc9F3S5H1JtMOgNdo6veh11nWV0cpJ2PbuON83G6vYI+UAUUaV78/Y5pelc1TTuIbk 77hk5HF2WOJehtv2XS1wea6sd+WRXDdT5srxrCb4foBo1Tq5IdiWSTw5jG/wckwueqwQe3/vkEZ7 VZd2KBfsBj3bZcofrGA51rRXB7pEuqXrl6gyFszmL90f1UP4rFwj25Cye60H0lbhcgM9NalINicc 5a/74SImwCaduDi627hxoIxj9e8C2jI1gdBzw3kb7D/fZ7liBtpX4UQSZD06uPQCW7nX0PDC7o8/ pYNqRDpTRP9ZW4CRyMv0fv0ct+QiOL1PeitSRjGNzOpOE/3mJjmq3hun2TeK+9pASZDL/8HJgDrp rFV/lsHU7wl1YfKgq85PT2/QVYFVhn1GLok74FG7FaZ+toMkAeKMZiwHPxePm/qVjipfQt8pagp6 OIEz7R6Toex///FhmaleYcjoBqIqnh1hPocmUURZn6Ds2zgxzcnRmfZZnGYRflcccOhAvzRw2c0m zreMbw+aRYOa89ydDJ15OwS4Ycign7DNiDxQZe1/UXLBtTIbvOPp3bUh/vIeM84I0BMG6WXkNhjc +HUjZuPsfQgB/4Wu7WsDp61CzYTQtXyA2suerewzZ0clk0MT5KZAR/El++v+58H1RMQQ8BjQ4xZy VYagp7/0VFf113e1OiqQVk+taiFUfs3WHx/PmR3dSadj1N4xmmo437joVVfG3GEkpO0ChB9ITpTH W/HYDpiIWMowQD41dsixovdXZu7wsNivdTTHW6d5k4Rq9IGW43KnHWeO2qswoXKcc15Dummd6qch 9sAwhS3W+1JNGJj3nQcpB4pTzqZSzBXlYIobUg+yxV32JPsozIeUgtbKMKgeNNfZmxZvqNPmSnAK KSo2FIPy1nx5FElvGvaryLsygiWVIYzshuJuDQSak/wkA7hNIl3QIqTqMkoitPNp0uw7eqZDxk+p DACrBsmL3eOFL5oKuOIH8SKkdZ2q24X6a4J9AjwR1m3aQFi3n67zDw3bwYypVbCheLGsKnZZfpFe EfsXT7iPsxPwB2U3W6PE8qxdMb87ypAfb0cksRpl8K64iVmMtmDu/abb1mH3tZ7rZwNKcMvag8Bb oBfjLo50ZyA9iJ1w+qz2qprhMDlqXip2mUqrMGs9OZJBZPSFJ6ijYfzAabUTgviAZeMebPBXBErV 8ao4WJuXAp8xCGVY3A6yHWXGlurt+ixoDK5H5yx2W2QWKyqk6Z/GZVh7iVJJLzT2f2pZd8Zwwxh8 ZIzuLjl5ZzMstg1j+izMLkEwffApNqEwlEXqSS4JZE+I6G+wREe8CwcmbiBwcPXb7L5WF5lSMKjv mD6Ow4+UGptK9GL7QmjyQ79j7uR3d8GB9uuag3KOK+Pux1VmaQ3jFyOVHYDOhkUde+Fd233SaTBW 8W3DvTqQen6fDeimvPEiS1n/hAM7fqVdvOoRNUHdAxDo6MKNJI5foK+Q7KtKK6y925kxrADwC5BM 2B6vZIAtvrN+oS6Yx/k7ao9Z5ax6wZXmJSHNquTDD4FNUdZNsWTy6ptPLWJCYDb/yQw8+Gso5O7e 5VzuDQHKtMfqe0RHtErhtIX0g5GpqhIEYY4x0v788HTOuWcxtz7coZr0kg/elF7V1z5RzgKSQdUm L46R/ZUV/jwN1fYFGZrPs7UqiYRe7JwN3Eonlls8npG33DdFKoJETmjsua9QbSlwSztc6HDIdks8 Jc2PwtgBim0Ufj53OYeOMqWSkzlqlKg/7z0sfua1/kdo8KSTu9RJHW4FUNXY30sefhK3CbXSiee5 QJmiz88oyISeCjBB3JuN+jPY+OPnMtYW+1IzHzVT5ont1fI0/lJJFsTY/YZx6SNxRG8HM+h39dpx +HjNxoccCOOhqd88rIhIDjrZw0KsjlAgcVpxwoY54WDdrS56RKP/XidxLo429W0+CkEismb/aiTM vPR+CBEiX0ygdjQoyN98nhEa4kK0FVUUbdT415xMGX6CDxTVM0ztdcLz7xVdF/naFqudo5rn+T7j utTePPd3VYUujy0lmMh1PAy7ac/Yh+2WQbpWHqC1jWR2rlV6YYnF1mnL3GFuiQhKm6OBAW+XuDII C6q92YZJefSYBlJQHVNoQMK8kCEQ3O7uSKP2pb1smXXD7VYaMAzo6ugDLxf+pzxmxQZMNky4hokU tGR+YxVVM8YmnRs0Dt+4AQMcxpEzXgnujczOhZCEMjdWn6dTku/tgCUJBUIFhZmmAnZ/fhfznrjg IyU2D5h7poHuItmSLxk3PGLCQAjbYVLJvCuNS7NoeUGHgYUeQZ+7Bz1lzZ+w/+s8fhaYOJjSpjk9 G4fTEidbfueMxoKwi8ZwyWOf2ZtSNzWMs6IehSleAwyFWGYBDPzdOhGQRP4kpJzXaceKHj0VGQPu J4k+fyp5D7AXLkn9Ip/zufJlO/p4pG5h/kSlHAOrO7DIlXTtUh7RSzHJhZ4isPNS89fUf/Mtj6LF FnR2o+9KfF8oVcLcQoJTP+OemMu2tOAMa5SDpQNNg4Ss/l1MEK68IaJM/gwav9vxmZUXzcWDx/WP FO8bXyAiW7x50AZEuAJHKv2rJYxGt+E7Yn6eOlWMFzKusAByE+GPJfyG+AgtmqY+gnfqIEDepkKd DEXrMWYTdUEoqXPH2cXag8JL4wiVlzvKDbnDFAO8nBy1NfpSNishP++t+7UBOEU/xCKdjQ93xefE W1JYga1itq08fSk3hZ/gjxgn5Ah8VPIT0YPfD9hfQ47Gh3zZviIJ+BSC4apRUwyMTXQdy6aIt07/ zCCe16CidOh/KS/W9V8vdPdFLUTHFBhVEXHIKjtEjw6551LfRINYuX0NNMS/vEIWTFk7LpcnQMfP Iav4kA40UE+zrtpwei4V+FzFkVmHma2z+tXba+7ZmAJblNwW52xzAsxQRU82VPu9NwLtm4ht1v/Z kIe5Bn26fP15DX0Q6JYLTksfdSTUOoA0eyj/aHdSaInnyChovF5jCBEQrOX6+L+MQlBGfjVUufer B0DXg8VHisjnKEWs+ZwqCu/FjdfvGF8A8zcOFP5G6fbemDJUaZ9/xLXi1aHSOlJrTDhqYs2mQ6Tq I/ZspyPs0vmh3eD0FkLO7/f4EEPzidDbB/xDt7+W9wQWoXyKIerC3BKYXUmOZ4osiL27hxYLJbpJ worS4r9tqlas2En0/xL6DVHcKZC8hhmmnCI8T8my2T8odGewRMcEN+aNaqeuoZgjZTHDdqoSsygM AfEMUmpregl9shDVx+1Q2w6Qn8K43szzrVyzyXUQOwNqPHbYI9US/RlzktwVh2gj+RsCsMGfdxnL LRdYfjClLOmmgTey2GVKw7VH/k1h6Z1y7iMygUQJR8y35L8rZ8vYuibTOgokAwPpTuDQUFIfCZg5 fRSHZjH69UCQr6/TVuJCdypz4F6fhL6pWP18xWN1rq4OS7dLuGD/A1klFlK772/aDq2D5vtbERbF 1lnT3Cd7MclscPyH8pl26DgFJAql3Yeknu16kyYH4wNbx0fMNf1BIKZuAgHpAZyQnODl+li3C6Ku E9cub5KKO+7YHCYIFX3rhZ4PYu+nJwsbSARRbT05pDEU2PRKI1XCbl7CSvAnmzZHlQ9RgQoR+01I oy82ozXlRgp9xu7K1Ow+1sIxs6x1h5DIU9ZJG7RrI3ocGjxr6Y2tZS2rMGJauEYtYuuAtFGonZDB qh1uoQbG0axR3igvMIfAax7tJ8MjwdjAMrBrtyM++OMARYuzUm1CnTqKGnRrFcb304APof3sa0DA 64/f4l/2ko4C3D49aH+pIbKZKzZuo3bFTbWSKQr7xkzveILHztsVOPgLh6sJcL66SNrMrJKOkVOQ +71d7O+aUIZK1nTw4ErBL3njqwKmpAkYCTJS04Cb3OiP6p1SLuDjptgG+3xQLJF1wniq1zBH3isa jklODyXMqPMAJmS7+hlud3IEFxaEswRvZRmC17HgpUIm82P7GBOkN2DVRBwB7v8/fUGa1mEtnsUG 2uxqBAtRY6h/G8AVo+qxYEXIqI/u3GgxgLVnjX/ydUNXlLxdoB1aRXvDx5dCzUL/flDSo9dx9KP3 MFiIOnruYlEeVpcyjOHAUoQGOnK5+VLSS/bcffa7g2jXhQ2Q0hTKvlx+wwoFn6HsUlIISVhe0A4s Pf2jloeyQzt6I0GXQo3OMtUg3DAalE/ZrgNjEYhPym3+aC33f9ajX30tZJP4hPoMxz3Z3PXAOUPI T4PsTq7gjEx/YRJSZ1vOTN9X+IyjvE1I/nAPrAAb+rbLEMrPSRxQUPKlWPJCBNZ/OI4gIIMOvVlQ 6lq9eiiUg66roM/ec+OcVtLdSx60lPFZkQx6uImYefRWy/XqpgCe+KiEaex+/xH9LNckX2w+Q9nF t1sK8TYIZn3TGFfz2ZLZQuT5D3LGwcBYnzgv97+JgxtOXjo7N23ePXzgQ/udNG7eBG+lPLh7nJc0 o87JXuMlmArLESzyPjvT/eLJbhAtuB+bbjhHSPRT2wkDrNKdq17A0LXfbcoxvDk3dF6NADZR0HUf qpjcITLWNxZ9voduJFuI//XqTb0YcnE12M/qrdBUtCE37+ZF+HlE+bMLDJUzycN+xWdZFpG+LYvB 8eI1tEBAgFLrbYinWqZfwLFLPRU/EymjvWaUGKW4y72S3cZNa2Xpzj1FZeT24+TcewME5m4V23+B 4K1ZF2xHlMVSGS8a5Xn/g0qDrAcRpc3bRnjJvVMFgv3V4ZpmmEOIxH9kzrbsrp7FHm6pK4MyzGcT lfscuvmybvh1jdmEmP5YPkZb1TBqd1B5725RyAyteKeKwugpwwS1ufhAt8KZLwrbzIvlxvf2GJEq TAV+IofwTYsnK0AbWYCTcVMv28sAPsDoSZvX5mfjn6cWjaZhZovpRbNs8eSzGXGBErlD+mYF1oqa zV9WrTYbDcW/NvmEfnNPMKUUYpo7KFYCw/Rb6zoPmjOUMeQBKa6g9UMC9cIjTTy+7Wv8HKkJZSpN 1HWfGWE4meg+oMzHDkFDerTQZlusP2tjxtfUoN3Ga6FpQrKtiazFJrWmTwdTO4LNztIKjG9hEN8D 5VPIglGJ41202z8NCwjCKspH5W50BKQLHoUAf7fGrxv0Q6Yr+RzJhilS5bX6MTYy3zL5dYlKZ9+z YnKbRtB/uB3HsFHU44NOVbLMzrNGWKt22vBx3UEaiTQkAl+XkEvEWKJ1GGo6JofjVHzbRRZHGZNd qD+b2JStDfvAT4FsvRp+1x5Mk3VnrKQgbmo+V4GwLfYf984MSCxlKMfpEF4fad+7VXTP0GyIepYD k+rxI4SzvFIILxvgFFVGAbZRSnaZsG2ba4xzXeAJ79uPFE0ZQ3HtNAXQiS4goge9IR8Qt0or23cU TMiABtvZ/f473VnjNnsBdYaUGpYraOSH3jBJ/gmU/Z6AJh0RxS6fKVUqOR8L325ih+SOxjRTOX7L As4f7vuaxRf6HTyKhhSATzWyAXw+f4Bh0w/BiFcJO2nwjmGQWF88Olhnf5RIRAfVdXr/YgAsrmU9 8dRnzTeCCRzPuSVFoHG6Z3YSz7FUlrez5C5Hz0vD9rqA2k1WQfXZoOUXJ8eUt9Kj/hYwc+cnlOrr 8Q/L3ywvw/BnqxyVzyDAGGhljXHE/vtZ3cajAfLCNk3QaK3pIEYRFtVQSejV+jaM11C7ZDNPLssf Z/tqXzB76zEiA/nNsJkt3X6pk7esh806vfpIukB81+w4JB3A0I74L4Gc7k2p0lIU5qif4ex5dR1G Q3AT+/A0GidLITMKJeoPnKW5NDOc6j1ulD9TebS+NLIbZDGDwNDeTVm4kX6LgAjXRYpzkeiswDk3 ICOjmEvPk55L1Ni9iVin0kHbVbkqVL0LBLmfZRPooC7tE7denAo/Zm0MXG4E/3uMhoZEqNO8GVR2 FKsIM275qE1F8QOoLDnVrmJpGlqF0qJ5UTE6aqKfDhgPi43Tfs50jQ5xNjO0WyJ3auxyF9tkaH07 zFU7TDsy7RG4ocDhmync7ZQCWw/+apL2DqA2eGdzt5TbhJFH0EvDwFCchZPWrQtXC98g2LUK6z9f QjwRF6tSuWom+p91Gtp638c4+t5MInn9weYuLFol8Xjclqp5I5ATopfBMikiQ+qMwbO5qXVuTNPd NHvf8HsEM9ycw8gmMXiY3Dq4jQJM5oVH+Zt0mZRNMwc3pZTWTyoXt24cmzKFtv+SfXSlCfQ3caS6 u43KhMxCScWBJqqB+apv00nYj79X0qLuSW0t6IFBnrRcpWqhSvYKMbrSxCo864PmtIPrXRQbgQao 9QmE8F9WyHCMTsPBWp1r2LwNDtDMGX4GpeK5EdkMq8zWVFoF6XworPA0tQMzYm5V53lC83cxc7rS yVhBUlj1SFtlWyyG1SUqaeJ8fZiX7EDaicBhXWHlbX7qpx8AWWAyWqkc4syQvCq0yka7y9RE2+cS LkG199G3GieR/BK0yu+YGRUBwBntuK0R6WLRmXTSF7EeOGsuWj1EUGW//k6DhEn94sOeoMilrAOc shbMJh0cGuhLq4o7LrU6MvnEF7lQtClZzw18Pd3pOn4ioo1syZ2PC7SID1TJ5ejL5/SxDOqOblt5 2sV3mVleg4SxIDykffCppFUVhVYmLRTUsxlALfn0pLI4ungogFINN0ne0UhVwUuTTDCWI5mNboM2 YLyZAYReEkPNN1g7H/Gm5Uy9Efd5yLZ2XJtqLLsTspUECn8+eFI3h1OfK8YXKuPJBwp1lJhz60uY iEzAqE6TxohSBx01k/26Sozds4+nm9Skl798E1sH3ITv/Xs+rRKJNFy5HGA1hQyJXBhOv66zhnY4 8rVHgOOY0nIrScVi7Rv0bDdH3iMaGZwvvqDVyb9U8MqfthPzIZL8Y9o2JlLDNAErW2Ev6mdV64J6 1zwgrMs+9lrzMAuyed/C86K9J0YlzWbyzpS8DAI2MYK2oO1JTrMGzoVxKBHEy0vUcKLUffxZWDKg klZaUk8F405n1Vfcv9sia0SaZae7LO7PYTptczaUkAyrtJxocV/DFC+FP+h27NCmdm+jw3B1/n+K EuFqb5feBgYdFoJV60wgjEitcdCIzbcrX7UUhSvPPiOG1xZHGfmJyhs5t29TXrV+jn+i6fB5SgSe eD29tTLcyAOGob8dy2uPeKF8gPp2uvQvPN0N6X5t1NurmQ3tPZu5kTEzoxyXEpTnbEbwqffRMW2R l4vyGv0XmvkVCEsO/nAEgT+RonfukuQsjK8m2oyQ8rdtisX/qYlJRYP+J4zcmapLHNXBXX6Jqnpj wshqsbTKKv/NyCp1Jtwr6QtJBkCkP1duGBkDPktdy9PMNFkU/liZ3dtn3w1HPVQbQcf46iYmPvQz T7ukM3LTclCguu3XmZCD2WSjLYqEFrwCBGeg5E9eWRqKNAKLTUTMPOARhMAKMwk+WQ1zHl9tD+pI pqxAH1Qcmja/LtQrJMTSklokKikRLyxoHxilY4EOqlaBiLb1bpjLZjGIRQO6b0aDFs6YG1tlQjgg M4jkpj9gTgBNBzBIWBJa1WFELZXqzVwZQ5ZnOAALXbxuD3NpepqkCPQqtCpDwZJx7HETYfQkbIFN 6VP8PpWS3KknWbJJ5tvM3fMmKvKMCUceOlpCQdlaemmFGfnBt99RGrZ89v1qVwHDV+h2fxH5aaQE mJul82GMqDIH3Qx29OIbRiJMDCvk/pqsbEeSc3IlGCzbHu/B4flXcxvT+YfXliJG3QPaY+OU/jDp PpXvWuDMgVzNfLoT6oyHtm58xu1Dvb41rztsRoDb4oK4WsyafxF2Acv+tGLBxC4+RKWj3eHmHVNx Xw6dAen3M7lbBrVPtG3bNU+S9o8CCO4EDn4UzDpSC9JDveBt4JarpyMITVW9Q6TK/ZpTkdv9kbO9 XAYRJVAi2BgY6Okg2rLvVw9DQ+KmE3HxFr3AXKOMjaw9iJoPJMNj4FpfoHzRtcJF4L1TYxPGBR1g d0Ivg/G7m2RGxtdf2NUtWxRlPEuezvWT40IdVgAHQNYzi1535dE2AVSAbE2mSUn8FXhL8CidDbXz on7NUC0YVaMPd/HXDiThJUyIiF+a/Lp6b+wca6et+onpdL6U2NqXP65EnORDQ4IMmsEl4RmiCZqD ADo9ZyVRMuQUR+KchLGx3qiJDEtm2tgmYQ5QUASyCgSjMu79FXZTdyGMDmkYo73+PKS9JPcFUn6Y qqLlt8it/KKkW3VWMYDc/ECZQzSWyPxdumXo+E3xvZ9urP9etmTJxnW+dh0f9esvfv+nHmpOhQSO eKzDssjeDJl8d6UjjpuP+PZ27fbJkYiEnpLTo8iONAYL0PSoqtRR2NUSjSeJLYOtSn/9mkxO4a73 s/5le4xhJr7tWiInjvF38NP6kdm34G7Fl1wa0KrvshO8sS8G3uIjAjR51xXHrb1gVS5TmD3AFkrb KeHltQpPx7KbG4T/ev1L5Ei86iN4vAxd2Fgce3gkSgqjBlH8O3BWVQ8VYXIBqeFqgH75LhZjcd+e D3d2+E9bXWpDMLmwrzzJs19z4+cFk5SrbUYi0C/lDrt93CdhF2GVLKjyJ+Y7UL/2nUBk10SMePkB Xh83TU/3cnLRV6Qx7dLlkJ0Z+UYvkHxG2X9wXXwH08dHrJkyOWpXFgOR/B4bzE+zNXSushuA3dxa 1P+KE2WtpfqmUiQoK2JoTLzbNgS2MgwoNqxb9XwZLOEnxBiUsZa0X5O8eAXVJWMuFKSEEvY2iFWe 2G/FVtstRNmSVZaGgx1uvviwQky87kWJrKZo+KtxG6JtZ67GpTWOvjS5oIV2eS0P9jlIkziqFvRp MWPStafN8OeyJKO8k8C7BpY9uxcezwkpdvF7rAk4TUvaMDcGwPdFUKgv5oPfDnSVPK0v0RYpxFii bLa4lu2k16bcMv8931VuFfzrmFPQC5YlS0uGB6bPqacB0O9bXdQNaj2L6JzxlH8Chx/I8q3znRYO CtF6dVhiktO8M5alIFUtsKO2eA+LTwKVNF+jZRtkJBMDATogdwFuhQefKEpLm1poAv41AoBA6G2C I4A/9EvUz67YSd3RRcl0/vuArvkC0sw7XrmFEK4XXjz11tRPH3/6eebfDpwkqCxFFCaYCigoVl0v Tfgdvne+GpEDyHyqcixh4DkznibZi/j6l2B+YTROxtueknVeD3C8Qt23t0dnsU/GG+MH6cKtKOe8 VDUhglCee+uVlDyCjrJOJg875EbfcPajQ7z/oRvpCW/ccs451L9wtumkmYC1apwR3qF/KlDJwwws we3EUFANYsTSZBx64ur9REF1md1ez/EoT+jEVOM226Sw4QZ+j1/+ofxJiU7pRCa/ybDSrXKfLYot mUkvqiDxMHJlIKnpPvrZ1wqXgKPNKVHo4c75zR0oRkHJA6Wf0heKniZ0eUNtkmuT91pBzp63NDok HO/nFfLGA8hu6+aL8hl2GYfMS+iDZH3KFc6r3hj+iPEeVm8iBLazGV9xfMeR0uKBAV7U1JnC4Ieu 5qf4OuebytyNr15KpYL/sRWHibSXxedDKjPCxmvFdnUWGv07SpJ25BMl63hLihMOe9AK7qJac3oW wvq+4T4WA7AtQyE3IWGOADTcjWHuUQHLLmAqSBtSV/EzvGdRBRBb0VkHO9MIsUK/SnZ1TAeRG5PA 7gDTbGzEGI+/PcKfIa38b4DJ6JnAZo2HMv5M6UeYfUkKY8miKA+meH/zLXhpz+ekVdonznQ7TG3g t8B1/pic+WxJB2xeaptafs3GHWTWZPy4tLtpzGcJ0ig4y/J2tUds+ktdKpucpEpyOUyiXz8GWw7X g2SD/Zmi5yltV/R2KyWmHqzqaqLeguzdlQAsuFSzo0tYJPkpsaJavQVwStrqDzIVNaiouKzpcZxk JRFw6lUY3rGHN6iOKScfcPbq2vrcetkySTqrmvYeqNhSMHuGz+ksyu4OZpHkWUnW5jHcbanqqS4F jq01+j15bqhH4W/KdgVMJx77NJYNmR/+fdzualN5/LKApJCI4Usqaitw2O/klfg8DM3+EH4kPCQP OkkMxT0BruiBtVqbceCdcgtAuaI/iJ2E3lQx21Nh4KT2iH6lm9HNdkfWWO6uZTweuEv4B/y766Hk 472WGW1baG0XU6/yoxPyzdohkumYQmxhBsc1H6aFqGO2KvpztSUpOeB08qCFgRNHtHrqxwGe64bE shMeqpvOq5t1JOi85NiYfkgs4y64nrstduj/ab1ajWHRsSBlMUOZfSSfnZhm/GW+nxS1b0Ss0E3n v4fW5czZ1AXZ+LkBRQ1waIYagYpRmQ4AJKQfRzOsqbSg7mpwOqY0FwwBhrSlgaespR/unK9ZCpIe QRDEo6TOO1eOxcQNSu7vN3W1+P2xGde3c0G5swHM0/Kr0IYtFKuNB3ZRcxP+6VCnqG2TmrMb90Xp JdyKUOLVG781PfnbMXn9N3sP4K7uDWuvxynFa1dqrx7zt8RL9yfqRHspvuNySrtBMzpxGmQ06wJT OwvePVW0FdO94InWSxU7ciu9O7FgyV5HrnfkG0XvsV01mSSkd4QHuwnpT1REbKTcJmjeyawGft3G F+hoGMXegKKXnzPBNn8RyyTpwOCIgGlGIaMinv6zYs0cwrWA5vJwat+KKmnR7pie2Vj2CexQm7OE YDCl9jG7CLDjjMXUU56mzaFuMcM9/r9vqO75w30VsBfM4wOA+HEqWN+P/jfeMm7kwwbOx+Xsb1G3 fEXAM8yKM3pdRvMROOsbX0CDfFIM+GxYpNHq0+UQlUpsv4jjKxMF2VdKJIuHq3G6Yq6sbKLufwSZ aTPtkFPGpnUqVypPr04tFmB/Rwlu6dh+MwFjsjkbuuQ0pHp3gNLk5Yl0bK8yL9j4aHj2G8YlBhRH s2Dgp6oHX5C+3ELg/gtAe3B8f4i4gV7RvdS+qkE+fKth1OfVted7caCUSINVbfeyb6PMMiLvHg1J UOVncexjRfIrDu9B9S3MOL4dLN9wNkmI4oEhbRI+PoXSsT3FLpMAkOkvmL+hVF49Xe+OpX/w0Ho6 joVZg+QnupoleEDQL1UjhyDRPNDpgxcYhsttfBxv6Skn86td6j8M5/tQtoM2dzRa2PJwEqjtnRwu TiAUZ9U7Kw+ztkjg3dsWKk94h3P2xskzGgINO/83EoQ5Cx12xKSgp324lLtUzHFP21ekQLDOlsD0 QsKfwC9/+g0nhIdpgJVCjasegyeodR+NX25Z58swOWh+fQyzCC0WGXF6S6qsGjWKGnp6tYcHiCm9 RRBYcnGB5TlsUs31scnCfLdja6yFFLS+fYTDNSKgLCE59FGu1NCvPHB0FT3xhhR72SuNocq86+fz KoCPDdQVD1fm9YqzK1VJ8d+hhuJ+ZsRz2jZXTtokYbfNJUjId5OEPLp18rD1cxP/t4FkNQNlW8hi XOTK0S40zrhAmbxTtHAwbQXllQIsMOmCRg/rfe1UkVQ87oU+3QfhGO2Z94bcz/JvgAdFx0JT0q8h XuNgVHlElQbfBsKsNX5EC96KamFeeB/sYAawAYkQNI0+YH3c85uHlmlZDgyj7SrR2UKtXi33CgAZ 3dm7bVuBTW3KHa8efP4o/1cRWtpOFwSg2dbfn4QR9vfWCBTQWWj00X29m6wrrhkNP8PxWPBvhKH1 Vgab6keWxg0DC5uppwkPLqLVeFj5fhuS9liJKnA5jCi3kp+pMGNR88EfjJW9eKgHwTA2Etp5t75J Ccd+w03/8zCUAxJih7+HTjUBCn7uJtPBXhxE2C4xJ0PNrvhrqoTYWc2XTbNn0gS0J7hwCDL58Iu2 HB5C3yTOuGFgU5wLXHztfx4kDNYjle5+ZuACQiI28ThJ2PmuA5Yo5wROslmu+Jv4JP1tCcOiFUbA b3JgnDGzxOR44bTZtLJrx6kBrDbHjnZkqbpTb77i3/U7Hh3tVyjHDqyXuMFplUWMsfiAABeX3aes juaCC4ulgooLC8PPn2HTc+4gkERQle7x6Gt3KHYceMH42QsMVmuoYNlra66d6mA5gG4GSaIMWwDl oW0ThKIS7JeTM4jwltGgEOZpDANUbKvifzDi+sI9JaLK0e78BVwzyVLEvLuH3swJTpgtq2MFzI2X yjih+uVbTTw5XfkK196aRDkIgC/FVkY2tfzyEAH2zo+0JtRuO3GGmJSAvG6TbzJpvbLfrCGYyPqe Vd8zdyjcstDH/QbbmLOcFZfEBt7my34EdnJ5BmRQu0sz9dKj3IoHihngRGZDHaThc03XNDO/T7cZ xdR6joBWWEzCqmyvUERFngm7/zGL8SJw+bmh+fkl+uk/x7gDmbVLypVZzkiO0ia+FUWKnlxB9btS rBEf219E2GLgIxRgZdVUa1aLjXuMQabdLHXMos7c7HoOXCuiTCT49r/gehnP6oLlB98TIsoEypmB FhW8lVaMeZhY0VYS+QTbXOZs76jJbao9DCnAOOZIVcJjDJDEQzqwQ/8RLQRRtl1jvOp9iN1yQ3NE /q7UOo90eHNWvjmwXaaThTVEnVMJTrzCUjM5m2VAOl1cdxROLSRdL3hkv2F398QIlRdMsP3L73Ay LELYTyqsiuYXLemtqlQuvQbSVCInL6CWHPh+CrL7Uw5XSzW4VHC+X+JQDEonSagNN5lAgN9JUWY8 JPRKRhioNJyeJEEXnYmRCOPmQZeLdSXAtxn37uUUBGbN4R2MborhVr5ssYt0oWh1odENKsakYfTN PgjPNxpvg4o/ADPet6xuo7xjwRd86F/5IknDoUSQTgT5GcMq1hZBenW2v7ez/QL3eVTGZet31uyk gfnGJJf4Zx7MaMstNDGQtDfQqWPu9a8pFkdX5XClHH58CbYKGrqvy1lcRi59jL06YdV6YpCPla3U UBPs9EHL4N+7Xjr3/LgYvqA/rCLJhuEbiOuCdlVljDCokAzxBa5jstAYcq+ah8dYsJp48OMfOHEX dsmm5srIHhdKezOY7I6srqoCxKvEnDRdiB0ufdr0UJIB37nOl23RW3J/NP8FItfe0QQ4q6h1Qet0 fW98HTSOMdX6XV2VoAUUAIC8t/ASgsOZXqqXgaGadnV+Q0Tag2wyYSKhhQgjZ684dTRsOJLfpngP dspN1DnHuFXtjbELRuH4Z/zD74MM4QqCeElnDjqcxnaiuI7d43vhi682xI/uPgp7LZ32ys1YLH3L 9pWSvMn+hxPzzxW/dTIs17HJ1WAhI/fiXPB2entE2O2NFpUbBZJubqmWUHQfC8j5xG5tKhPE8nM/ zQ2fe/tAxvUfFCDV/vNE6NL4Hz8q1jw4YzBacj2J610FbdHcJh1RgngyUVVCf221LYs7XJMYV+MO 70HYX+As5M+bfrflG3dcTU4Xrwgwxo2yoOcKtHD65b3d3IGShd/bQbABWqazX+R975JbG8CQfxR1 rH8xAIp6Ok9DsRXUsDCZaQZvBtYQ8Fd1hg1rmQalbU/CdQ90+39YiDiGuQePgv2VB2ITFmDuRV/C uN/O/wjvZkBQB/FzG2kMm00glcnlp5LEhKVKCkEfUeNATZq3lJpdcHdb3FNl+bFfcV2V8bBqzBUM f0QV1deMBeoPiVxfPBqEVrS9s6PKimVKnCKLubtlIRPZL15EDETlkWytJC1+ZpQ03SEFyj2D/DNM qb5DWhzlLFSD/6FkAU5SHdv/arPhDAAVbDdZccUDEhLAjjIWN9W9GUQYtXcqfgPaUNSFhQcWIbzW ISTjF0fwv3EVADvj5MsNFuEoTNAJgX7yIkJ5gBpgEV4hgbj9vMabgQjAV3jWhW1X3oaQWIoOy7Kv Q+HVBJVvupyAhHg+L39TI+03S9jSA2Y3/vgxxd83qqljPpBdev4gVNdh6//gdorr9ii+Wy+vaAjL 0myaY8/6yA3AcX6194cdrlyzwttOALf3gv0/vkSWCh0rfHhM8m4u8FmITH8MC9ZR0/OrJ4OtBiep d2qJOkFfQpAovkz3+gnNX/W15z4ZCxdgrly2keVW9OgSqKrsVfThqO4CduC0mT3S7tYGwJfgtISS f3YWB0FnfRtR+ARJ3aHghmJ+kWIw1AQ4NJQ7ZbwxxOcn+Vd/5YlqJOTRTqfjUTSnQNXbITUseIyD ox/piRPzJnGrFKc4OfQ35oNo3fjVDgySw0WFM62056sW0IK87lYf33sdv/W8tOCGj49JsPMlCYvj i16KG1Hw8r6zui5V//Zu4T71y22tzF+jyLybQBaW7k9BUV4boJ+5S7tnUi+FfSHhv/toDomX6yyG 07Gi7KdRAYkGIb9vEMOs2bkwkXRNfAAqbRyGn6ejAnT3IHyunA3VG1S7T6zWQ9cRnz1C7pM8R+OA /+a+ddRhHkTAk3Uuq07BodmnpQxxpTVL5DOxT5aQN/1EeGBMAANFUkbJveOurddfgy7eYYxIevgp m62P3Fe9LheDgOEFJxf+LYo8TOAbHDle5oPSp7m8TGPXqFpASzi2tNhHzy+0HIAXEvqJY1rJoa6D sYGh+TdYcS9VClnuaHfZQ5ykHOsLHkh8GrXPBpKZIfgN4mWR8HmO0sGyOEyFAVkbd1bH+DqNnQWe uS+qEuoslwKtwPMHDeL4reM4AOn2EPm9R784Q36lcu4nckjeLOn/okry6VV4FCmd4l4U4Z1wJIpK i41nfgSWsTQe1xMGlJuLjdA/xjLD0SS5l9uFyjxOMXEWIJJDRY+j/p7yFbqevvVPVtndBhzoyLHj bsHMJVgk/7ylRmtV6Wgg42hv74LrA+ZSO9gAuSBb+7g7OAoqHtsP+9lhVAGkVv3l/A67bNckck7b qNw/xcPKCxJFTCuLpjKsA7yqqK0V8B76KSfm0TiVjeBnsA5BCp1LovFopBBDVvi0A3B4iDC2WpXI EYznaxCoDCemevgN2qBaXWYsRh+Qznq6P2DQc3ylJ4aFsnTlmwnucVKNG9b0gamIzsNaYWuoBCyh adVDj5I9ZecvH0Bj9JVk53FG6S98pj8wnHdIhfaQ1KW2abr7CI1ukD/jWVBGf1KNQ4SJO+ocu+50 YD7TW2/LE2T/gs+VhTnJ+wc1f8rkGgvSgxKioERGMIs/Tlz9XhkTCpErHQngaFxsRsfv6uFoN3ZW dySgiQ+MtJc2HgypZvzl7bCwdZaFbNubWGV34bi8WFf77WSfgNv5yUu7lt9GAMHjuewr6cYoIyG7 GqoaQ4N3aJCDVL4OhYhpvkNAjF0dDmVuwoZowGsV1KMSpOIEnCODx84vSlN2RC+7MlxOB7Nttnz+ 8Vp5VtI6F8bsQmK2RYTxawyXUVDj826Lj/FrtohICeinB0CkZCqZuK9m/tRgFPB2fbhNhaxj0Dy1 sQEUSiL+eeZ+w4jb8TIAqvD4w0FWMr59uUEjFeYJCziSUA84iFezebRcVeHcJ8C18n/rtaPQMBX/ 6W1q9vrwU/Y96Dy4GuZJiKe6NBa0ljmLC2aEAaMulQaqKS9+Td6cIcvym4DeM2tf827B2qYSqL6L CEearOv9j1d2KVqEGIoICbg4HfouiDc5syalkuLIALQPiJX24Fk3+53Wu6hFibgfFUoozzWXzL9z gfOkr4Zo8wHg4tmVDFV9XhSuO/LP0/DpiliEuABID9tya/bLysiCMJy/+kDSC0hELXHO7Bjn9XrG 38gDIIUU7vNyvHv5Aa3ZCZ4Gqwrj9SLOqTkMAwU+NQfpRHcdih2jht9ffZk+i08/ODLPXBeTaTc5 OMjLKIfFFBqUpAnpud5UFJYxuNX12CagUCjipMBtkh9BcP41jDlKp8GJgrMm1vJ5e5Zv/ZL3oEKz +2rOYJ9ha1ijW3Ng27XpOnRI/8EOLSNwZt9LehT5dYcH0L9d7Jv3d+TMBMzHgzWs8d9EMHLU6PN4 ryi3sltxQ6EtBgeJX5QUjb8RmUwPSWI2rfc6/AkfTUaDkQLq7C3EGDZaxyGh0RVq/OhIgcXp96Kh 65bkWMCqkTHdkGe8ss3l4oDnn9N2YoOQOUQumybwiSogKv9cu68fm/Jneq0YqeKKOB4KhXhDPHty crgRosCZod6JpYrqS3VUw+BYgAjuAtBwdqgzm1zRXMeZGk7p9MU+/EdsYavobGRVdCtEBwXhl9mw DmXJVBsjniz3CGc91WrkBDYBHL/Rm2Q9qAliLyWfnhsXMF6wN5DV8rGGO9Wb5Eb/h6ddyoCR/9zR wNqZlqhsG1VSMucy2xMlWYpN0fnXLRatBUXbktQjPyMKeQ7UsFYD+AoKt8YvkdXki9BLHU04PonB qMM8p5D5YR4P0M38nzt6jszLlS6BdpmnivLEGgZbQrmtNEkLaMsvWlYBN2zTsZKPaUC+UZTB1p7Z ebafJ3v2wPZbrhDMUeHYrcIZfn5xZ1zqayPOP1DpdXRhNxcDfnAOi445DgGED3dw5L7L7V7Z+RQk Py1AnJP/NBDLWAruLrc84qKHhzdJFm5tEXdS09wq/2ZAINNDvaJt8F+W+Vi66KI3t3juT9FWhJ10 BKKB4mP1A6v4mjPObA+2Ib+kuB/HSkyAMGQTeOB9CEQf+5ENL4V2+s20ioX06w7t+qcci4/P5R4e RNF8v6KkLCnxJMHb495FmA0++pKJjzQBJrKusw/ot6MKlEac3cOjHiy58RVojvwG2ST9Uj/AkXmh KldwKzc4oTN4QqXPWc6Fp1pG1CNztWA8uW2nW10tseW5KxXiNvq3LQNvBO8mls+RtgzjXZwwl66U XTMVJNrsJXYm1apItoYu96iXdSrbCNzLysxwUXB4MUUihLLIhyBvQ3KPBX7aPx7/YmcF5MfsgPTm sahRMnivcXbbBNyenb+j59kU2uYk/jBS6LCb/Kghtvz0O19hDKxWHgcAWI4nxEQkvn4991jBlUEv Y9eD9VZpn7UhniwrY7dC9Bmpuh97A92RVDsn+vp+wiy68dpj1UEGaVBwpmJ4pat9TMlfRoVp/olL gunbgqpkW28n300U6WDmQQvTZ//iK8a1gnawJfplM4bNLb3G7l0wlM978kTqzV8l0f81eWAZyMHl YDBiPK1iIWwmqHhhg8fxH7IB0cNwYuOSJA6Ps+Idbceska+PS/5/XvnGalWkuPYfsNHk9017Q97w NdX5jVuucdVk3+K23rWZPgK8AG/OrxX51ZTdLWik4OTQi3TRf6qC82UJpdY9sbLgRpW0/h3DNez7 SLmCy8rEduf06pAnqAbyzma0blWxAbYPtkUeCUS2D9FcZ69THvumncXlpD2lmwtsEX7800E7hKhR 2VtfU/VaEKD4ZfU2kbtpvkIepXrGqnbwya2auWZi1a7TVZw3lst1ad5n9q2vvcjm+Gw4562Yt06N EG+EVsqHJQM9TbYQ+aSOYHbOh2/btBrxEo7EpYjXj6Fii2UuG8oY+yAfmtt46GME23XBpe9ZQIz+ rJp4q8p+ltq/8PY6Fe86wHruUIwO7iqZqUCG1iGuIFxXmh/wB0N06/kQuWqEdlaoWKSlbw/CrtKO 7XctCI+kCVvoYb2AqbQ4CZeANKmahyNUTOSRgR1Y4p+nGfiFvaCTcPt4d1TO+XO48JQKhGShsm9P HPzMgrHJ0aDZEuSwZ57axRJN3xy7iWtIfcYJE4l5KBMGh7nzm0KDMw5EJctcm2BGb8ad3arzGP1k g9Xk/aNHe4KuzkBtnGWo+j71YlAma8Xk/h4IY3t36oxF5eEN2cwL0ZUNwF+s/wN8ShKS8PvP/VS7 SVTvTcfSUrU9CXhEpwqOaooktl9P18xZ4pCVvOuQPTRGuOxg0AByGwOJbQma05fP3nVeLHeD/Bp5 GlDHlZ/XUav0zA8Wc+HnjrCYstTFSi8ANKmitV2iz9j71nr430cSWk/ToGbSWn0qeuXIILZTmvzD yGe3uTKjMbSqb0xC6yx1IkUpnWadQQYw0LFKnAEtAdnJojHq3584WmNrXfDPvsrn2SZfknIi4Wb/ bX0r1fM/UvEMbCREjerE2nF40QpqymcvRInXIwoUkKmluFtl3rxdRQP95SMHlqH5Lqol/UgNsQW3 7fV6ES/P4eKaN0crtJBwd7/ylPHFAB9zRrrz9CpfWx6w0rTF61a2XULDQlisTTf3GmvBrVxd4cL/ dbFJA86pMzRHmAUSAZvWJSc6W4RFUI1DjZB9ZuuixEVONKHYcna09GGUOMorOJF2f0gAYQvJBaq9 luz3rerWMRTv+MQXMXPAk5h9DWm1JTaraOUwk5GdTRlLZRTFdGHeJDnRPiYYRSJlltByn4bhk5VR LbweQkNhvuP9ajZe7BXhVU+CIVkpaZh0j11/7JY8CeDCBL+KPhHIYGXrFyXqOefXZY2EW+Uv6lxh mkotEf/xE7195+Z/x9v5Yq6Yg9fj6m2eKF9k6M1zub4aS4GTYn+MBgFbWB7lBifESJI06vh2vps2 SSXlz8YDYbkSMxjuthSP7HbyfcKchQwLbekyhuXg1Ko9YIozzSRBIhToZ9HSbJ3m4ofNirSV/Wl0 II16b94eLt804H+fd7MQZbVGvdhMu1A7Plded1cUC/57uP0zen4qHe20z7R8mywWEJCnFy9nNnYF GTRkpIxZpsW/+ZM4vrhxJmE9dlCQqZn4LMFGWVfeAYNmK+SCpzggM2p5ik0M9BAxIebi1p+p6fil zQKIpNEo4d0Ix8zcvVbvwkend09H0w16wlXufv1XU9u5g1A8K0TbQ01f5qX3X7uV/PJg8RX3JjXz wEEn8RDi+j2HcRbj8jnv7qJAH3n0hJK3ZSzXiS9O88zIyqGC+da5PiXxSOGBD1RYiC8lrc7+SqCK 6FnyDZ9lon4BGZ2P/egWwoQ2zYE3be1LfTmR2XaBMDAn1Jv8zXE3eCug3c5WItGRUHypZ8Bt6ouC 4ORUEH3O5g8lQ93M0MoE7SrD1wiEH/LpVJVzYkCjsvHEHn55YxZeTS1leCH0O/fo1BJijOnbA244 t9xYHo45XX5i9XhuYrVcX/gD7/g7Nb+11oSN1wxa1K3JU7LGOgDQ5pU/I5ljlsBwLJXAndpc6zjT MPHr1yC3wnSOd9Y0AUV5HrEyvSllHD07fzeBTDrgQQgAJcyN7n47w6qYZWbPp7xUPO9DQ7aUsUgg 7TDj9I4CPIocs2d3vgj/7oybEFlsLlp1mtCaoiU8UWm/6CMwdJGWC1Z54d6P7f+MKHl8+WLGC6g2 XOZZxcmJXS/zgRMWxYm5q1SqF0+4HpxDhocySkMHZ9zUYB7e7saNEXpDVXd4TQiGOQEtPYf2g71P VHzcSrooRIVOuPWr2YUDrOmfqml7XSqEWMITx4ry8ZtRsr75/w1YSG7EPCK9gLBQqWi15ONd5yT+ NMr0PHaWOSoobuybYeRH2G3GKqaLmaJ3QPn2YnNR8E1djL64b76pBLL1NMvi/ljRdTEehG4kr0xC mYKocizrP3i0jPV8ukL4QdT6JRYWOG2X7hh2rOnIGKPuGaKJhMIiTKcVVNL+/szRUqe6vXWvv3FA D2Oc+rJFcFTSq+oZIzx/Ujko0ldNpuKEcl0+xnf+SI8si0G5psG56DB1GkGsRrhJOOVdw6gt9RAS 2B7iWg2WGVI51ilBKbytYzPMbrP2VAWF0AqvMMNruzSxdnAMNY8wdZqG7YJ3j47Ccqk0ntLbsTUf K95cP+DGHvdJDJP6wRcbriAANW0+J+WhwdMfC/vXPaflMg7DbqjDhnqlpJMZGfFAVdYsJ4R0b13y vyfUlQLcMcGSmRs2JmWm/Jfmg3EEnYg7w1TXjPy8bwg9cf+b7j+C3ZFZy5kUupPa3otj1A5pUOFs Gf0+k23mmlrEA/sDUO0hZ1FAKGH93xe/WoYMu9NaWvarqtcA6ys07Z7Z0mXY2ZSnqLcN7gIG1+uR 9ddATTrycupZXZSkiv/mgoyWA0PJGJx4K4x6uEyzPhfSS4EUz2OSsn3052BkPZOgUkUmDDo3pY+B cw9sZm6hWuLkMs7Wa8Y28F+jYzWVGPPk6tY+4+oX9I997OYq5Rp7Wzc9h6LjJUoD4me5rbSvDy3J sxLWLG1NKMhYKd/EJJs8YDiJ2F32DpUmEvwB1RLtgLRFDgfnu196g9dHsw47TCBEWO+yMe/GmNSL AZ3j3iL7SvuC+0ytB3MPNvdN72VuX1wxbiY5YtM6IPmXmSMVSZy6WZ1WpuviYJOyIiA2VkrCNFL8 vHjwjK9BePD/eVTumGmPdLJvpkZuWfZA24J2iEdPphnDXmugdGFGwOf13Y1cv0A+N0rYHjbX+a6F EAHejSoBlxK54exoOvpDXx9NxnffT3/8aBj43quKrp/ZiOqidWGgjz4dKX4IvZI8DdV5LFxHK6kp X9w3pBP4SVusFXW1HeTrgwCCwfORZVwjSTD9iWxVPkhrOlksckMpcDS1bR8bvqdikuO7iKQw5crJ PKnCQw9dOjm9CK6+3YpCRxFwqhlt8eoE4ITAZYNGVnfuaPR0kah1s5YbfCxXBkKS3fTwg/feN2um kDCSXva9JDb2FMnukg3OQZWKr8WzEEt1+alkbaHq01CD/5pTzXtetqj99BOufJlNLX4dyEI0bmJT F/srzs1dRN40w4d4zn51RuwlVvEqlgScZVyaa1SJ3XOFGCKfBFhEwzInrB80UoGvvqk2kqoejHzz 3cfu9rK+iNMTM+8jSSRHk1VFr0T33I7Z2DvRnjc07QB/xIaBABt7I2Po0+cQAWKxTiPHGNRMzQBL HSPSrSXXzWxWpREjGnPSQkTWr9fiuUgp6+2JSyR7P+8NAn9aklRKt5tWLvWNJYy7thRDwCtBuvAs RJNcX1hRvINtfNZiPED5d1bt4mdmbxAlI4eRuoN3gGtlpnVWkhb3lQv8EvndMlz3sXib5RatRNaA n9R4LuF16P3eHP/T4gNNPMMRjsxG/pfRTAXJlB+rYGYa29i6kb4Ny/H2OyddqcCtIFjzPHdjcyWU 6Eyx9+3fSap43knpEUgtAXmrTrHH07zpFHZxKirJI6nTKDe59REKTVZWtvMRrrHojxelECwkWUjz 20XiMjIwruy/r0WwezNjZGe9rhKo4yFe9xGsALAqBe3Oilx34I3bqVsLrsa8Z+eztPOYg62UTqTb J+mfW8i3hp7R5f7exOcy8R+fVQrk2DPf3nXcAYJdgQKvXGa41FJZhb/qaJxu/2TzV1thjOhkZpub EaxE2oxNUCV28BC8e/CGk/wgw3Z8xEHLrADNFxOxjiUOYVi11NU5/UkAbnbxFkMJG6vl2r48DeKI QSF1Pm2GIe2L2xTRG6s78qgQWvst5iatlpo2C/vDKrFi+1417ckwWE68iHw7w7RsuVknhVk2tOo1 zL4PkBTHJns9V1MJJLHZcUEMCvrA+77FSLQrrUiflk8xRurcFb7Kee0+n9AWRKcMeVfpbGvEUrmd r86bbp3cJm0Md0kEjaNvVoE0pUNAN6gbGAJG2/0FDJyhqePaQhVNEGB6U9DZBARSLsGkFLWu1bcC BPelIPj9nyrPAe120fSIeNRxHH0gBA6ZaV33HpMVEemzabgjYlXqWEBtD3Bp81ovhZIHWq5Rq7PT cTjLEz2ldaNOTExITcb5naqKWQW5YNHcGbE0ivikiJWlVQsGcnAeXlWXgzKO/37CzuGcX9/4GprJ VjQ+5GECQkmPd2LB3CcqVXcSHemJ5DhWADPbFPKZKp27ilwstVfNaDqKt2UB6A6IQopj1MASP0Wt hzZ2FiJzaD9W62REbYseVtUEaCvgNYzE+rUp8NKcfuqdq9jqoGavH3uI6EP1pfLFLHVxtwsRYBib BkzWVb9/Pr0E7+tlABLjHFkHsgkUxOD+ivyTs5GBTzG4ICPTSLViqKtypmHdZt+Hn4SHoilLlJ0m Y8cxpcSKDHlpfMbFUBC1T+wOrvDuinq6JRcgreq0yCDWG9CUtjP9PFCo245AOWFqiM7e4KWhND7u Vi9Y2GEUdDmEJA+LRP9JV4Xp7LVcHlnwLKvoEH77bAkT0pXOfxR/PidF32av9NVPg5/fwUwmTvDB s/ZWTPTFYf+MFRmeBx712MckVxcU9++Gk6hEZXjTDK3jxJ76lozFKhhz5pcKReVeSLPzftTkOSpQ cJyS03yclT6qUViuMtmF9kRk9dhnpWmW0fC/gNXm6kf4XkRTN3mJrjLEWJAUDKfELY1C8iCrC8Nd XxzAcpBdVWIPDdHDD6Ol2VxIKf+MufMgNghLQDhenGqGdS1vg3JNP2cG6AwjGbMX02yULEEChjIr /a6cFoNdC9FrkzCFmjrWj7+Vq9AWg/mQTxE5HWaQtM9eFmMwg6X/1r18Ekc2h97gFHqmSQcFu4BG CpIf5JlTZufBgoj31qrBK3+L2c0/j1HQio6ccnzvuzz8x6IbziuUK8JsmMU4v92SR73qEWG8XQDS /qCBdBGBHP9QsPZvKcy3AND42RQGnQTn6i7O/pWMpTYDVK+lsldiX5p166ZdYd+Ibr9ygifvrajm VFnu6mPOnapO6xni15J9O9eqOCFOCOxTk4RA7mS182cKY57n7C4DiN2JQoaMy39mQ+MvfKdfyScE FYgGoPwIHLsvlRffm3jhcZ+QPuH05s9ZiN49JAxR7ph/+o9kL78lLffUoMM2Van9kcvgYtW1AyDO zpkCIiAiaewhgYaihcN5yfUWxxq580tIJvZ1CWcZl0k1h/REVhv13WHcTH+IyjZ6XBfJQ4YrHtvp YfdXrEyEUgpKrt3EbDsVQS2eMzDiZSiMqQisSSJ1Bt5SQWIPz2w88L0l9g5msPZ22zsdQ1UaB7zs mKornMQzUmoBrzByJdS/9UMgmMK8e6+4OaZpHPGMc8CjbI5lDICSI041S6ra8VT3MLDnQJFDGUaX iJv9HxTaFpD2nGvo9d5Zanlx0f43e2IAMkssFrSSEju4vzGLkOP5/8pvLWC3ntu3nN44HGJlY7AB C+pzPM2K2a/1K0SFomoqCJp02Y1YkGPlYELoSpR5FkQlW8DmIbHk6dBqHSmxM1/zMFMpN7pKXyFT tjntOAWSWAwOsEVX531q9yu2zSkLevXgPSlEMW2T6igWcpjNEhnqAY1n0h0S1KfIUC/bNVz6/2MZ U6sfYYoBRPwkgIaH9DczSSV5pdpViB1LYZuyPI8ZU37B9epfXS0WMEXAN6TsAl0KT1VMUguUebKd jkkHutenHTkQt84jh/Uh+gikjlDPSF7oXmADjvAYqx0EFdk6Wl/+xQcJf5zDRItxQ0JHBOcyGJXu cnBia7YEUbZIUTyIO6FfyvWg7SNTHAaMRnyzuniezGbojUcjHRa4ekFADGr8WxH3Aswk4ZkgZYAs YBZqZdYa/QaieWOxxwaq9hjLMm2wUZwtFrlOtwYpKc0iGoVK6EVk/nDxrbY3fCLlFotclugKkpgI +1IqohxPl7akya5BD48ZahYBBXA0cLaTU0zkHvJ2ALP8NlSeJlBnl4VdXnZ6ei7znuD4YSHu70HZ MqHHWfLtGpQzTTdKcWsRsrCWkkszZqBhKh3nXGIfuvZ0nFWMqPZOqyRtsqMbKvuLjLhRCpC+yAn7 nOEVyOAT0qPPH7Kiw1/zbvsFfEsJSG3BNb8cVYLtQZFx8U6iGeYq3HHlhGvSQWrO22VyVEUCsdZV 3MG7yzv/JjPEMdV2or9sezk56I53SD+PFfm9GjfX3SZULXA+XcCCahshgm/WlqVCR1rfBuIQaYWR jAfqy8bzg/cIpoeGoStq/X6Olw7N0dDpgZ/n0gspooj0csE8X7iPjdX7I7JKGkxqehaOeDRgyj7t Z5TDnUH/TRJnMdrsULeqYQG9OQPBtZViJkd5+9A1DTOtAfrdhKEHfmpXhSW38klzRfRx4yLznmvW NfmprLwGpKwhQWjweI3Iz9M/62TptSPGIwvxgrCeVqpRy9DMUwHLz7W7SO3emx+FBfyi0TW1/vDi t61UlEJUPIbWK1QoUPzADgGGfsm8IfZbCJIjFDT4Q/rSEECr79g16XVHi3Bnt2Lh+lAbwUsKSKlZ QwBVnPXufwN+dSshpNYlmFB5zbc6cOLKS/Y+A5UR6c8icUYFWoytqBloGkol+O8DLCuHQtW6kyCx RdtpXNSrehULrueLGAbllQ4LWIO0rHoIyohgbnt9Kx+e/wpfG26TeBOMuPZaUGMvFA0VzYwTCCav cU/tSUBjF67FMHPz3U6ISqxKT8L7qu0EDn8ur76EHJZd73ZPeGzUpg0YCOoi9Nytxff+G4jd0pKN vetZm2017czyDC5HvSCYfcFAxn4DC8naVFn++43dx5yzGlBfc3paDP3zYs3JoUmLtQ/pB8LNFBOl Cdyn2wz9d4TwSalSYNFwrGZjo7I5bJkEqROu0VsHfsbO2EVoLZ1m9lXy5DSsTbeLc8e3fjyQTn9r cy8qqGt6++UW4AvAwg7Bhm4S4xgttoUmin8dFFem0nkug8CPOLVmDb9IEvYeZC/uxZK8ogTmofZJ z6yh4ua9yx1TBDA+J9d/BNwkUf3H5lhBhiY9fWPwr1FvfZpT0nLg2nGtQix4zZ9gnYaqD8XwQrqm AsPaQG+kRJbtutdAi/HtWQe1MO23CFVg7n2wiaIUUTqAjaHGomb9epPGdDyx/2x6lEQ1r6Iv1uI3 sLolQnKIknZp5uxzcqXaE9XT2nWNlRedHk6eTsL+xuVi/90uTnegDSreMVyVKvl0JnUYE2LaDJC8 mhEf0I8ByMylQUvMc6TSpxEqrH9XTkz/TZR6Zo7TflfmtKKMZZgwlCOtOPhcaBOtNQZk3qsYgkGm 1H+S0H18kmT4MAAD12h1HgfJ4d/8tI3TShRsfT6JI29nvzWVW6bqXLz9C3oK0Sw/fxujlLBpSyaY q60bAY1GsGgrXD4F/ZAGX3MiZ6cR/4yCOmer82QMmNmNUORRixqEE/N6Ktzz1YZdJM1F6dLe4BD7 Y1N2WkyLJ0qost4f/yDzp6W5mPyEofLHhIaqjp9R3HQtV1sniO6yFkWDcTNN/er1n49UJ4VqwXIK XjR8K7JRMb/ULqJXVXhHTuTsuPQRLbMTcgJ6ZkMFv6/Pfq0G/YC2C/6XCjcvXV9rvkKgdJhOqCnh 9aziugSNh1JsvmIj7azIzS0LDQx7Uy6SZ0eKQKyaiapF+UOXBXzFHGfRwx0p1GMeuEotwX9IZ62+ UvlmAErUWOwvMLqubtrV28j8lZJPLsv2JTGaY3BWEan/iQHkA+JKiRDjR5hJ+BzmpQiZJcR1VLd5 fbg66FxLUJCPzvIU1g1pCHJs2YgkWPjSetm61TahKHl1iz6ZSrHyUlYvJI/sspjf/l9M4f2xJIud ko4PP63KGhnaYjyfdSg5OeKlbBPi1V/Yed/e7+dVqKOGHpDrQuIG2dG04q5DR+6yFso9Lc0HbZXp 169Qfa6QAbjyaLVALq2NGTid8n0WzDgCIAtjizWrBEXeNfK0YQgKFSVfaRUAlBbFp64UdZcdTKWn NtLCNIO7wHJmyIFaAHDxY8am7j/+qeLCRpTt8F/rpnkl+T8mJMp5zN6cPlZ+TYJgV0Nw4s1gXHfC IXj8lFpUKFZTp6hx8BX6/0oIUDg2uIy5pOdYiThwUnKScoVi992kGzSMFVMumstNh2ORaRI5ndxs cNjub8UogePcWA9bMIbptKtKi0stfmejwi+HQjBxkzClsG81xnc64MDWQbsxHVl35UuHiDdZb2tq jkCoSFcykY/m3jiJwwGYzI6Ew2LrDx0KXuWjJ0MftslQy+m571YrkOf86zxNlZWuZnjXa4Pie50X rXm7OP7KJeRVKLMb0Sqtl5WE1xupPGwoi68fS//UdDvU+IUFLsvw7fqNf6EWXEtDovlE8lD4SI4p 5UN/vCGqkrmOT/+95QvZRCjJtl7lhs8n1NGYhunJnG8DmuaETawjgDR4rhZu2VWILroz5i0p8mv8 qQIE+xjL5S4iihHpmLkhxj7PqGieK5xMJhETuJsDJGhttsQK6qbOEw9WXiU142bcXTAtBQ6A7dUF ZSCVEys9g4a+GbbVwK+O2h8viobiulpdzqFcJz7CFeX5vWmjqrc7OqZKM4FAK5F9s6YjktD+xEd1 f8CuAKC1DzvMTKuGEo3tfwQKFo53zuV1Cr+8an7fh23lFY0FOIeL+V6kCOa+fE5YvI6wLaMEaCIs BAyDvSDomxBW/IVMjLv+gMK2rVHb/YYHTZ/pKP5NvP5DsNNk2ciSyjyrELMhXW0rDAcQjo9XJfC1 EqM5y8yzbo77Xs3k5VdMC52s+HeQIm2HZQmmpkSlCck+eFlZe+zQT8Q6vVUL6ShEyQpUzrqQfKHc /SVVqcWRwNwyC025VJR6OSCH7VjnU7X4WBdWPnVdkpT1gd2Zrlm5ekvJwd32BkFI7RIfOAzc8a6J 2xpFK5xhm7EEYIYWqSYJ2Itjsfkaw9x5e/I00/aYvFxEFShuYiQWBvVEu0dn0GgGXPt2M43bfCtd uw3lznwbzDxcHw4YNbBATVzslEgnkM9ddoiowY43hAYqOuj9Hihzk7Wet9LmjndRmpqoO7NEZHKw i6YlHz7sXj9gKZzEzd4NtX4o33pXzkx4swV2uBrZzvspirPhhnOZcsDasoJo1DItz4+A2UbCl9g6 dUwb0M+RWAmpuSdZHkAY4LlO1Wv+J/6pngWIrxupkcxktDnNhAwexWSTAXddOsI0rClZ9EMoDNyT 1WRCM+PPpHI/2RLAHtS7kdTGAzaAWMYITeChvsiRTUMc5xvTKN12f2yiGXMFf3gcgVXVrtRL4ADx Ovhztsft/y7advaKo67Gcs3lYFngu1Iflz39xR5a8DBBAjQ5jRS5iCZ0o7hjvyEMhIxUpietKrak vd4obaFWN2jiJilraezjUeGf39/ryyFG3qVfBavNlSmGAb/ejZ6DsjpDbY95xM+JQHLkjeBCn5zZ CFaqBSRR6XvjBpXREQsSzOFXj3W8TAIcTFqZCmaB8d6O/d9Y47xkt5jq7LyQFabXiyp0dJOkFUh/ 7RvfH4/BEfPQLOoFQKolbsigd/pKgA6LSJuzuZrZ553xe8suR2YYApS4waWaZZ4iIi/vl37Vjx8b QgTTtFSnA+C+THKn28T7pyYwzaMlYlCvEUAmm+o7VqBKGbc4jRjxck8FZhYaa6XJhvcoQKd9Q1Gb 8H3oiGLdRzjibOjpUoiaTJK0zoIBQiG74XoIqUcti2MeuwUJj6mLbrIKeV2BK9fmIGVqPBSTPF7n 5VbTJSCsPJZv8JK30SCUlXSFdU7wDZ4ShfFbaiBMmifDQXG6tvFHV4nvJFCYzkl0HSaRS3vPTrnR GhWD/kRd8kgqZsmZROxolDQRp033c3PKVtauZV+XyVPVCADljeKobNVPZGwkQKP6izXfI5tH2v+2 8N/aY9PpfIFdOqbtTfu9n6zg/TP3s2GtQx0syLtwL0k5DpZQuy/A6MBKnJU06cUMA5asJPOIqX/L BPB0FWhFJYHsmZ0f7QPmnsB/sF97kyi4Za7ztad6wajV1nPRlH1xLDKPrGDwaRsxgsgjoGB4n8xr cAjfIrTEvJ9bplTuwy5jcUCAbBLTxWs7BoAJ/AulBSXFXhmjc8RMw8WO4Iv1OC/ZmkbNp/xKH/YV 2T2ux/6lVNOtKwautSJWgtjbNPJY5979KwoztP8g1BE2z7SPJZQ4ov6C4Ldz8XMBRSihdA56ZdB0 CAHq1Ykx6iHAQqzKfMp7kBW6SSGinCK63pmTw8TCnDWvup6Yu9we1Bns+sx7BblkQUki5MMW1T77 upY2n+bJkYLEVebA7LVfyJY7aej4yKKIx68/TDHH43kQP7GMcEIX2PnEG798bNmJnBGpwUXnk+Iv mV2zYJyiQL/QN6p6T0jIM0s070WtCrjt/KglEWSfCt52vooUQ/tLo55FL9OUD4GMF+5qqvgRU4gu nzjjpx0BwM4WJ2PuiGPxW4mwCR2YMj4ORE/44G3ukTzOPg62Yo07r+ikQs+v5XobZS7mV2Fux42d mwNTlJ/eWEjsv9ZzwNmiEUZgtQdbBFImUhRY8FgJMvk1rMV+z/Gs8L/AQf/YBaVLnpDCIGDhLEo+ 1ZX0NW4d8HZQG42itOHy5kaJ06HSDnLsD1sj/agiiMzua9ZHB1qg7plL07Kq8u7DasiopANivI3y pf5nKy/5F6XX9JbV9hTWvCccy6rpBkr8e8xLVb+UgPawWLQXHUj4WGBg4WpLVtEI1MTLn/08FCao hejT9CgI4mcPqCpVUcevFfYdVNyBxZq8cDP3Til4/f3k0s6gbML7jkxTmxFBQli3CMDHsfxziOWM TiNNG1pUgH18QpaAIaD/608k4yt+vQgqbQ7T0uYN39XUrZqrwvSosonZyCop/K+RqtyBhLLF7Rab ElLnqJ+krpdNP1znr7+diy7Uxl4wUWS2gRzfmM5QCUCFEfwdPhKkpimcKIAlfUAYzgvV/K+2YVi0 CzVawwzWtuhp4FJxvMrd9mIO+ihGHB9opUFqFgbPOXPK8F/Zc8mZwgg664qkkPflDB9zAtYAw0Ru RQupl1YkN7Mhs4wFR3n1fKbR59Mq7ztX4T2V39cHICJpEolQnlxtgYj8Tl2LJqhpKdoAWNxxtl7K aef9HP95AQDV7560BdPOPQt2UfpsjngXB5GhVl+TbG4T0dp3bgm6FP2Tol6cb0RGkU8o16bD224t lqJBth/x8z0fHEr9NC56fEksEm58GYVKyd7XEXFuGh/zciZJukNRLMwkknAXZQo74IQLRRXotpjY ZsKPyneCp9pDxwiTsXE9AOnZzwNpD5yWNGJzYkAOWyCVRyWP8xwSvLmI++0lkhjqriGaJ/kazROB pakvmYgBG1Li+f59OVTcEn9bObru6S8AXlW4AGaC8I5sC4bneO6i6KNBlvivYsm72RSLg8M+r1bO Lc/OqHrd6Ffgguyczwh2yJh9t8n1rg2KGWf0lxUYs4laoG0dQRgS1jMzCWWreh4govj7o6ZIX8kd XGonVw+zEUwRBncZAte4+YRZIm/K4D/zn0LO411o0Prci2lVPS9ZB8DIILNUgueZJq21tt8HGnNG 16dAJLuPSx3eWIrkfad9GFI2r6XOeAfgbTq3Tld4eumYiWrdCQJC31VG/S5eGY3jHufmr8HIcsrg XGg7O4YjCeas0fgKgQ/j/D5ZsNZaLn7zB89gIdnezmLvl9vX0qlSGezuqi8+ugdEiZLtN8bpQ09w ZxThpxuhYDj+g76F92xw5Z9edKVnEU9zDqgJ2fnLpxbS/FnN/1K66WDUTRCUYvj/GrHou71g3Uee EDmBl0/gxspac+Icb+HhPN3XxuNCTI4rM3FyweTjPVk23U0zYTXGTMVbFx2FHfSShFTlv5mpwWtC kysdLOnUlbXNV9S4JprY1/rw2EP33/ienzCw2xb60y3iUiQFQ8YmPx519GHWTRg4pI1bqrFSBP/C 74pEClcju7D6GJ6k7TRMIgRMPWxLg5PKcb4LE/nuO12EuBDC5oIMvCT9Vl0oQ+lWjsl2+HSlKLIe qbqkUTO8DL5QYvZ+/3yFUwiAF6rIGAoyt5TjQ9RaN2W11cLOz+krTLzvWz1mmah2VoMmIr/oxWi4 7dwmwhBvlTE9hU2FL3Nt3EP/lLioJUZf5eIjjmTtIvvJHekkZoW7cboANQA/ai/ZQPdjyIwuWKnI 4MljkF0qX7RWL+ILR8RLsqckI075AKaqDa6fzWqeTwIzXz8Sy/G/H4V2z+bI8sIiH8L+D/3dzf8k n+LhttMpm1g1IbPjKDSLc6n5IMG6jTLs85/WluvmGgAoOBv/SBnvx7iTpTdeyrXqta60QXbqZd7I 6wgJ7S2OE1qjsWNJIPRry9FWpSmvKd87PWNTeCmlrP+whm3k4dM6QoVaaMt6gNAXQK49qja0AHEs RJn9lubxFhC1jokxS+Yua7GT3L2i/5w4xZ7iBXwZngRJwKNl7A1ZK1oRLY4AXmYUUYkaSJBDUGFr aYUmuke7bDiurfC5ltBS7oa4A0GsS7n7A57wYE+xbWozDfoL7t0lqVc2JSjhauWVM8GfsafMrMJa gjYr4RMMWM4z7NeZoLNjBMHZi5sdrN8FMZKwXBWA4P/rMujU+P5yzH4/yBYCFLPpLem4IXZQYKrZ /Xe0qJ3omBIUwroAM/9AQWRfCG1CXXOoWZWf79fo2LL4UCjEnbnGMzZtyuGog+4UwJcc+n1Vsh2/ dW3stjh4CKrMDpnxhNtyDbXVdA0tZBsIpeGls8QEfCiG3FWSfdoeY1B+vWFVMVv3vObm4AN30Oba 6aHQ+GsJ6XdEnmV73/om4Hv8HWMhOr1M424cKKMBv7DV20U4XOKoh4ITsWUONPjXlUYe1myfKwXS szBoce8vMZpwD4Zy+XCm1URuM40p/qGyef/JeMfk8suTkX8xmcBkgvikF255xQ1ydJ0G0aVwI9Z5 7+xV5OKpsSY6JaVsg15QBqjF5o+VFQPKUQGrmoj4nCuuu3fnrfe8FrB3AP/UDRUg0jECsXub7dSl 6UmL5KPnrGsGkECZt3xsMhUn9/ytYMX3cRLi+38LSjvBKLqO8WYCKUFjQS2eEaHDyd3JIej8nCbN QrPC6wLdor1po16/XidU8riMoLu0P0b56fY9nprw0XDV5m2cbMNv2fL2fHyfsnh3LgkbFzHC7X/w ZLs2vKm8ezFKyLX78jxd+oX0ResKn9pWYRgvf3P4ALEDFTLrzyRdUyk3F70ToBQf6e+Gqhrh2Ith sAn7+Fuy3KnlHxNNKL8BBbOiCc10c692EMop+/hO60sldJRr7SNmUFlW1bKvRVKvW/hUHLpx16Fz wZHbwZWjDssTwp7a4N96PQ4EI92214lrO5k4kxxH9UkM0mQkiK3zla5nQE1xbmXsSVnYDkggBniw dPqJmq3gz0RP56+/zHoyhZQoeUww+84rC/qmmWjEuNwzGXUsimrg2ZQn8sQxB3Xhfb0F+tlydlw5 VfRPDjR+u2vAEZ40UzlYx0jQJUayU6qBm180ECigZ61Ozl1fd5vgqkNC+Qd8U/zA/QpgzPebhJtD EyeyFwlwnSU2vuyQ+jXnQKxg1nqeTpDqjSg4pZhyypQIkhhsDg/C/mgf21XinKmJXBBuEYsmoqTi efGK1nFXvOh1y0p4GTpdXG3rdvp1ZZHfSl5lkDneSsx+zbopqGkDGIkBtHVBHb+YrV0UpFL/F2fF +uSUeW6GENi3OkkKZ8nC10VjEv5ey6mJnP2vyKf1+KRDybkIfVVS4/AsL6VDJ300Wi23nSh76dY1 OvYPUL/kPy4WnBv/g7B6d+YDNZc4nCGXCFLcp5gqRBEhyVdOQOUHQQZSMATDJYpzMqaZebx8DaT/ +hmJ8mn0WpDKO2J+M6nppVHGfpus91l0oM8SuSY4UN+dWstcPTNzJTnGoURqro51CKdJlDLF7gIo OKMxHyb7+j0FaozT0DYBSdPcvuuS+U8wzxFJo9eP4OoaPDaGNZCLMzUduKj0qHaUbXVbdt+4fIDw O0Ne9vgfTjHXhegQGfDjWG9gEw6PMa8LLszf/HWHQRMNm/eKsxQEJqz+yYqjsedLlL41HB6hGHY2 e2Jiv5JklxXe874vXjlrmtsW6ZPVLPKvFLTmyvG2+rH0ZSA+3XXjPeA27fVoYok3kFjePsjgCbd/ wwGejM5u6amOWJgTlVbgFXmsMJE48q1uDRT0pCbQaRzevf6FrAUkkG3gmNeM3e/Z5ELqNAUGR432 BIGZngusBHcfiLQEkMj9+ZkEt2r/mbK0ZM8frM6MX8DRnWJ9bI5bf16E0aZHwWYWe8tvTcIAJSSY A62cHpjxfCnA0mnpAxe8VDqdbXNbfbfNh485IhUerl9ROmNyd/pHurQV1zstopcD1KCCt4UQHfYF q2jHVS96RwqliDC0lv3g2QcZhQiHNHWMK4Rb1QPOIagMHrAYPlC3mwiOZqSMcdl4nbhgyrUaJA/9 8I78yYSmTCToeA2srPt9Xucmkpp0rhqNZB9xrnqMviXMz5DqIp6cvMXQZN1Q53Dc6OC23SlV4ycZ D2ZlXjweEbaYfGE0A18TCs1fuQGFWvLTUG6ZAoLtMRR11aDJULd+IlcOFJhaM1wvcgWWIyEobXpZ hL4icKaaHq5+j7868cjzjWa26LF2yg376kgGPdz8rGMDku377N6zglg2rJZxJyt2AFBDk9QL/QMM zUx03fnpNhtBZvGrumMD5HToX05vA6CctNa+eH4OMlNN7mM6WPh/vcVOZ7AqrWbL7oCKxF6yQkUM KRtvAsNffbydkEJqL5eNVblPKKG2P7F+IfLhg5wNvXaCqkoj3Y50qKq82+1jGS+cjCnExchTvbn2 ZjK6yO4T90rpRxulOPbLFCM1vMLJp2jReUyUoJ9ENApmGv69A8D4PEM7CVpUUKj/oIGYxJlZhuPB g6r4nECutDYElGHl+uDK4gactw2b+yFxDwuMYbFV4BYiW1rvXEm+DPepoXO6qb2JqkrOkRoIOnD7 iE0Am4jOvYQXTuVVMFd50nmSxetsaqC9844O8JFRMDc05gKhcwL8UEbdeSISTzQyqItGFSDsNigb 1Fs4naYMgN0oh6rVAl6D5eQRoyTsTY5J6IHnycLw/lzrg2H0r9gcgiO7noXqHIC0Z4/2glX9zzmO R5bQFWOYh118s3vZ08VwfiGurUooln+ilQgAXG07Vh97ZRSn7jToW9UsvcVO3mQqiKY81/bBChO6 tIgzBJ0mbnt/VcCw0A8P2TSsqrw2z9cazHCv1oMgh/ezfAlvHb6wh/d7mxwmiSZHMuTTSLhHviHt /9k5pk0pLFptST7ZlVl5XqvLzxi9z3xsNSIp4DX4bdxZohbc081Da6Ra8lzWxChU5fwMbYGWvc/0 Hiq7UT030pxPKoo8JkY4cWnbZoUGCwK1MVaXNWGzcg9Av+onJx+G09W8tLdVMSAJ8uxbaNaOia+L 5kNtYUzgpO9ZjBNBx3TyroSt0oJZsu8wTEhf/wcUzX5KhP7rbiYE5Ea8p7XH0K1tobIpqMZEsubB 9D8P6kpg6802WAnFRo9m5RmJSOqE6oGKn1mQUgm8vblWh4ewoPfB/2muCYysYh/boNFjQ8xweWvW p3YZMAYY3hIl+0Ypq0KzXZ1l8/YgSXcJ/OSx7T3/a58NHBehexblMVWE/Z17BCgMa0co3z+67/Hw K2hCB8E+RJmVxx68VuftycWS/d57nDUBJnB8GY4m05L1a50OwQ1tdxMu2VfE0CktkUgP7ja1LYbO Gry40d/KfZ7etcfmAb2XlgTBRaGfbWU2HqFI9Pu7aRgfO/HRKtbHuWHPSuAr/dV2hgYOSvG0QcWi 0yDyUGHitusfCW082aP5H0+6f858TUGcfKHbHvA78lL0eizfhySF2g2UyIwBVY1T3HTr4tWy5ek4 GjfO4tPV76HmL6PKMtbfrQsqrrG4uvhWdDWh2YdyQq5XTkkfclslKvooSAZGJdepUdFLuiVpRTxe s/TJebGh17nFdv4kug+ukuRul+MbO6uQF2UF4f/A5icZmO5WNPjq7oK7oAFwrSytq/ZJs4ioCGNA dupGsjcRvUaFpK833GEmxMna+EpsmUHZitxtJK4XkT58nciXET/V+MX+3BgsND30jP4bxU/8RXb+ LSWvjsyHPKy5WVteCyS4llwnWNFztz/KJTPv3ffVJ8WyF5P8+d1qAnzYWXR5iT84NVZmaCuMmwav dgCsqxhBoXl3tE0g8LznGuJXL99ztjIlmsR3rk/1CBuF5bpellURcMA4yIgs2UJxebSvLcE/lvll cTIa2sfXKISsNVEYMjwxRS5HgTyTDCIBR4G7OYwp5YyCfw0epkCCr1ujXHxBlAjgFpT2RrKGaGJL mzTg3CqRdEpIjCJvbChDVwIWXQVlfjAykiWq3kwdFxd9D+Gb6UWCLuOfEh8EjvL+g9hLi2wgnVHQ +wfhHYtpZEPj7nxz5DhtnHhXVNGGo2pXZJPHsSb5RHvd5yFeml9WkEiapV51RKmv3tgvuSGOJacp jlbzm+pExSEuTm185Zjtbo8PMlrUautmwUiIxs923kdNqaNsq9CEjE8zH9KRWAb7q0SnwDPBQhzi CHzwyDlyGHOTCPmMIvQPXwuNBBJyGxSsot7XO1iGj2IRDr7NIq6D11LATHHZxAK6E4jAj5R6Rfmo LPdnafENWGrELU71FZ521RRSR0nky+nUx24b9w07X5Z2Uuo6zYLHgILrWDrm37QCUQy2nDFD4Vj+ V76zj/8Q1tPjA7V/d2+k3pFgvjXYOMVvqyQmnsZUiOq8N6BpWicEXp7qWkeKhlIBCS+xJVQcj78C i0OpZqKkXTmimpP2uV6jGZbgKAlAtlfYt7Y1VBrMlUaZWLwjOP5XJKuo4DDVG7NU+yErMsQgXMfv ydGPP1R3qIpih59gW43DgAJWE8QABDI2bk2RWCXfcM3+JJ2iMKk/kz9deh9SRt3BbsnIQcoxo4C+ 5Vgno0A8Gx17bbFWt2bbSVJ9SCRU91DcsMgaRmrAPb4G5CYAwN5xt3x0sMx+lpOxjSgqeMIsyC5u veE0zYORX9Uounf8Vn8McM3ftd0iYIM8NIQxK8VVRiBy0Au3qEncfGrPTujCfgbo61N1E/T7eE+C JfN51rWNOk+IBygy41OsKgirWx73KUrdKGMZ5AkFPXtFquzQ3KGt9mn+ji0NSKeqI9kbgl0cGyWw qJFiyEmlDfSguV4S1km0nCB5wmufXYQLyV7uO+dZKlSIK9tsM+hTv1BUQ/8FkfNS54vEDN6//lsF ZUDwobdQpk3wCushbQzwwCjdBnNwr69pOPLRNkdFb8IHZJT3v8M5D24Dmhk/jacjp4gol6OsD+E8 BPANbPCDZ0/pSL9b+cxBvMVBd2QELAdRZ1Oy7LupJJVDDRwmyf5Tx83S12V5PhyXyq598+rW6gbo e0aDkMVvrV5hqe24GajTeEGBn5eaz3aAz6nRlqO1D7lj3XVQSgcEgSLde6grM5VF8UL600Y7pFkV ETeLDjueZRV/MOAO+jP02pwg50U8EaHnhX7vwtH5adbbyhhpT8OgspfmJABAPHOxRPW4aZ0kfqwA Yn/ozQHV+Cc7UHC9YWYR5SnOz7FLPNJTbpwWxnFCDXYzBdAdiAE28734vMjt0X32qBSTGPUc3dJM GoxbaBdUYJ0KWCEBiLjKjpTPg3WeNkKfmVzbMpOV3NZp/hgx1OEj+8xfRlWObN67HwwqUe2AJisk B2H902ZXm3upVgUOKGnLu8tm8y12xJuYUF5daB0tBpXE0R32sob185TCJHJ80VEOVC1wwZphf3b/ 7o0ftKdQREgnyw54dQ49RuEVdDos+apmLUPTY4Wzx0hrOa34XMPy/ygw1bfBkxtMMy8ac1UXTYFP ZBmwo5sWGCMolS/1Pdo8XqPN5eJE5db1MaIVQDM5ata8PKN2mnExiFzwr1A3Hm867Ik4Q4d6+sHh V6oG/qNFFPmgBbrQXHaUVsvnow6tL54CYJSP04SDvYIcL3LSl7OketkeO0V58KBju99cdNFM+adh lqHiI09Y46R/U9u3UOC9S6AFNKOaTPG4/HNB25JEN3BQYTOEo+kw/beEzkaHDYzDf8JMCaQukvUR yujgvRBrBxFpDtz/K7QWhWR7B+zpaLW/DnMp7RQi5eYC+ec6mR4B0vrSBO1UXt7N3zujaLrwYw1c +ugKUii3zqh47gqf7Aopw6TwCEK+dIS5Y9ra2zcIE5rJhilHIr7Sa7Kp/+nROrl2I76nCXvmI58k oBT545d7o5R8rq3QrkXZnH3F1ne5YUFHthBtFseXZVTmdKSOQ+K1qNijvxC6zDwmDqDmYLqn1n0m /NkEGKPftG0y6Mk7qJiKye5J6bRMz0aAYrK0if/zJs/rkEb7jfD+khfVNxHPSD1cO/t7FVE5EI5A b4u7xFj86Xr+iykWBRjvs0acd0zzT9XihRcbQEiFcsHilE9rksAfsT3zoRFmxtwmRJotQAkvqmNj MK+gGsSK+qFzTXlAzkYRp58icXP0MIvwzYR9EVbLxUfBhRY9FpFIMik1JQqHwFX7tna0BPApubeL owTQpfHK3HCiuzfDHE1Q0C9j1lklCt0ly7TTEmWTcJ2amuNOCIe7NTJ0eC45hRyM6xHnNT6XdbUJ WsJterOZhJRKpvnraP/PLEKvf+VsNRCm/imiIkPPptlY/bAZBOFe5GP+J1nRPOz3Lazv3avSOZCO R2vUgghiw/JW8LgTDChtJ6dgoIJ0JI7EmnWgy0TKLUsBfwx3DkUwyGOOSwDQz4P1yZZuCn/Krd1W H9Rv5uOiO9588KXjz3LdI3iw7wxNFLxBwmP2+I9b12WOFR8i5M96o25x6lIe8Po4BxcDSzwmc6+W Y2nbefif8S9DRV4pPh3tMzN5SsxgKbADLFxEYwOi/swQpDfo2mYLafzn1Ob79DqyJOzoeDb0ZlD6 CnpqZ2p5+hzcr2aZHbEQUvfjQUlXeCtj8y0DNkcOZzflTMUDQDRsVKySGN1yqedjGbSMxQVgjTLV ju8I9r9vLSmIg4SP52Vre9Jjk29AOhHp4iHuOAcw8vkpviKXYKB8u5GmvxZi1C3Imhb2VZtbPAa3 WAgr4/qiJEeVRw6B9oUxVmrF2DkJgnzdPwHFqG2hTsNOqiM/ECCSsuMUuvpeWcWJr63bSqCu9ojx VT8D0jyklatX4u+39NSVjWyJSWspX842JfwSIrEipDDFy4Xmhjc/tVGqp1cb90JvivT33TDAm688 MRfA12XwSpFSrRsle7qDuk2fuvVwo7Egj9UE7JGntio0qT0ABv/HiqpJPYuenWYfw7whITrONB3/ uW7M7ndXUb5CaCGA9So3H2zJHE0KgUdGe/Vfytld6Tja4SntH5ywji88yXwqnaZyyunpidQ2j13M btRGxkrCGStxmZU/dYUsiGR+riv+js7+0ctmZz2qN0SPm1dK6OjuV3mx4COEy5XHV20aFOK0ilfg baC0ok7nSBE97gkqmGJdTtKwehqzw6My+M7yzZbdKMUNPtQC4fAMuaBPNpcvGBWVNi24q/AOQDvV OUo4qA42/hit3v3rABbbiNO3fqhM94QueTrLyrh3JzRZH/kekPlZcCZ2/SUgQLcIXQ3uXTSDx+j3 BSh1s+64guBHzZ/9IX/VNExGhm5LnSXppCTZe9gI6E9MTRTbC3QPK85r5U71OMNiVKIA1TVnmucH fYKbrVgKvGAkrGDtgHC2PMYgUL51k5PKh1xmZFT0paXXon3wN3j4jiBsHzst2LlYm8Be2KxlC9Wc 313xyoB5wDKHoB+3kVXs8D4eOSMh9sQGEkM0N2Kap3fS+VpphIhJJslLKRhB1utnLg6AvR8L+Pf8 iOnCZkgstVgf6NOQXH9UuQTRelFKnGNcNPCbE+Kx+PiXPTAKMR/tXjX3vgasrmMv+4qxiaJPqK2p fxar6sIN3mejMs24UvbX4Mh+BfGmHO8Hc9Kjov/+nebT1Urbt16WcZGseqLv/wYpxtbz++qOb3As I9jYnoA0afOL3wQ71LYguFjHSc2Dz32x8IQERRQSVtFi+ArgJ01jh8JhJFZJu96wlEv9wyxJUPQ6 SnEtugVMONBwaHSxo7tp1GE4H+pkYz+izNu7h9g8QdpU7WgkPDBj8YcoJ/x8/N2hYnX+ThLjGNeV TzEAwbgCOgL1u4V3i/fCm9BjtjEWFIeM3XWx/SvznZMmzWH/Jbhgb98Uu+RZmS720UB3Djk0d0h8 fMmmLd1YbtH5BrQrXGQXJ2rOe1AUbOPxOJiN07m94snjST8sNVUUGqrT8mZyemeenbU93JkrV3V9 TO1Qirba+Gx9K1b0o67fQSdGYh5ttVEzg+iv3XAJeE4hKD1JsOZnvNAJ3tdPE5kaV6v/IySHu8MD LA5OonICqOYpQu546FVGW2KYjXvuHEy5Nj7/g5ZtTQv5DIqGN4JCdG0QPl4YG5IcKjJ8egSqXzDh X3gBPprKcM/IslArcw5db2pBSKbbZRlBiPyANVdsibuPK22elQvL/4GU3Cvob8UTYVCyjWdmAaK9 eoJzWRRx6wqVguSEnQ1Y9TvgRcPARZRV4S4N6KUnoZLXGLouvLV3EsBaTrtjpqQi0V8xGGHt/eR5 X8gXuC6gl+v0Q1XzLDeJWYlPt4xEyzIg7hOKS6xJGANF7Kj0Oh8pUPG0P8owQZ2oDxExAh1UFSfk xhxFfZTW7MnhYdiTeSPNTH3UdiVmISuv9qIA00lPi/k70lPsxUrRSXs+FNABaLPsL8mTX0qqM532 T/cYteDXtRXf1uRmggYk55bOs1v5yYsMqqm1e/QH43INig6um8gc65NQz4cJ0KDla/PHxCx8HVMJ smeZDKU9au8a5V3Ro6uFxu6aS675p751efxh7EEcPySjkiJ74w8Q0xuYiLdqSTW/6LNrZM7O9Dzy HLL6ndrlDzuSTumRCoUwevM/YQFjhK34n1qIh0fE9SSVc2BbXp2ln6MZBUGLzniAFfGNPQ0+A8+/ P2XpKwfnHo9dRZmcJHayT4EB+y9nMWBjiRkIDEXSPVmHr6Ggf/YsBoACnu6HKN6zqjCUqOmzDA2t iwXJdWTllt+bY6Aq3krlr9vx6hTjnFX+oyoC/ekU+K/jBZdil2O1hJQeT21WBQa2x5XRncKu+jLD yDYVK0EFDXg/6FehOqzARrhyvRa+7yYb1bia4gjAtNaFqKFIf+TcBVDFAEkmoXoJywHd1ChH4AQi t9WbUff3gFcQXf4wi+XvQIhu6NFWCE8e4d5v/90Aa7cXME+N5RRNOenVeH2+oA0TqyQ/qztBaqZN Fj8EfJhb/OB7TrUTOvzbPNY2Iw65MSvrrlVLcs/75liauW751RCk5v5IBfEoqFuayL7+S1h+sbnG LjzMQXhxsYIEALSoUeAVDlfXxFJZ5Q/3S6eIsoCJy48eZIR4WeFKd5LD9b6OxRdTIcUrbrlb/lz1 lYbiVtpMBNLYpZoFgtnlshMvFFaJSDGwKuxKFb1CJAciSMI7zs3DGIYBzCS8+Za6cGS6cyOdXLqj imbiey+uGEpwVDFf5KdUaoz9SQsYrNnsoqY0KwWeK/XQ5HflVrVpdcesnos62/+de/s7lzlwCQoE oWmhrHDQnIpIRQAQcNxLUXMe42zgwQT5sMpjzBG6L8xG48QgTTy2xey5ISTUEGsNaxz91iheh8zz DxSqmGgIyVsZ5Ne5ns4+efWbcwXnAuxS+PkUvx6U0+PsW4LoCc4INVcuF/bZdaeUsHW8w4akVTii YbDhQsbmyLxDSUocL73nXy5Q4c3iL3LSILMHqtryYEuzeyXaaz+2OD1ECDe14eZPD5YfE0TyZ85n hIX90MGxywkksGGnJf5YWzka3lVd4ESYKhZiHN3zOSEgwm5zQ7Rr971U6FfQ27LceqVCTFzW2Fk+ U9LPWQHKHRJ0p7rsPnWjz9sd87zHjXm0dax+9Z9AdvbKUjBnBiZ9Ge/kD6wxFuveAgTuJXrL3TLT ZJJ/5LZxgk/lR2g3/lsFMXoKuTZvIqYBP9lxYArJthVciRwSGUObDgrk6pB3/O0hgzIUnNtSTXQv LSXVkYsGbGAF6YCcQlGbBy+huz8mQc+BFDVGu0Vmy7C2zW3k/v7BmA4OTHgP4PLKT1bwOa07cj6Q Ni5ikhSSdb2HKeG8wVjXKDc6uzLLSfh0JvHhtndjbnyVHMqkShSBa4ubzkIXULbHTwuD/Ry2kCWp fmTzgmC3/gtzEcMNCy+6TySGVy4i1XdO7hiAdAG6hq6RMbAoKX/5TixVguI+ms0Bth5EDyHn2kle WpZgo8b+5tA6epai1rL7mGPjjFPCHrcgjB1UL7qmAi7aIcmYGs3Mk33jwOf8qo2j0bnITcZpWeN4 aUwPtZTN1LNFXY5AwhhgfBppkXpBn13Y9tWZAs3vPdEY15nhNNsSm2H06Py9ExMUt4l3u173F9am bz8LL20SJ52ORO3k3c+vt5AbD99B5xDGSJ+ku8hlT2damI4b1b7266PQbLacsCmFnitB6akp7oH3 n2IxHxiAQIvtkkJ49A876n7LMt+DxxRP8HuxkvoldVTwwhisSIBq2bBgJYQPVE6X88cwpzge6PUl fV47tnKjuaVEpSRE0q513tlBNZE6/NmeEO3KcI37MvDANJbENnrmxr1pBAmNUaZfSX7iWgkQmXvB fOkWXz7EVqRZZfs+TrjpffcKhIs5AcwgDsFNRaip8dOOHcto+qREaJfY9N8v/sSGpL6gop6BDKXV //uLx10bn4aciDMFaY+ORpBnTXqEFlG509de7UKMY3uSbA4WpWR8s6hetDJ9zR87eo0LGb2QfJhW th655CTp3y9v1oLX11Q6kTiiLp8/SLBbT05rAIJZUu/NjMq3ulRTM91N6oXmFvT3drIjeDU3GwBB UnJDt2tvk8GpHeRVCPgmNnYJwbotl+oWJk3LmWhb6Qmin+W0W6YrgwsQOtlQluYqPfUNICxrNzau AiUdHD7qCs4Cm5M5Bx9Ruf85VKEMj88ow5dB12U+u7JqMtyPjX3glse72pkXj/7fzqSjmqChFcVw CZXy3obpRnj+7Knw5/ljaK4qXulfzZXtWK8R3XUasq1rEzBBtDqcwYvJz1DspmC+S4wZSqLvvnAO 9ZOthx6YY4uN52ce0OBN5IyVG/7whW0guGiZjsD+ai759yp1vZyTl7MLt7MoHJVimdiUxMz07eld GgFDdXZTTNaBeJXa8lww3met7FTmzSRM2bi797CpWORJhH5wZWruSpiRV0mn3kpUrfWff4Loi6FY oLc/giGhBFUNNPPuVEuyiIO2FD8pFkyUnWOLCx2CF9i8/3qeipfyQVvBsWZmjkcPEEJYqSQoA+6q c+F6nn31PUuZq8PwMhuQedn50xZsBt7OVEu/iUCe+C78agv+jlv8wdHqIRbLot8fkipJKFyP/rnH 1qOHBY+oPEUKZVOA0Bg9u/krQWOLzD2EcPiNQsb8W4x9EqA97hejHlrW6/BUaRg2SpocmIiyhgB9 gYUNhdQMadXnweupJ6iBlSeJz65lCCm6zYBAzHruY2GJGDh6R4T93RNUlOdE5eJNU11jeqlTHMZd +ZEGlRjUHFOBa+o50wYzfLxM++G6rdcrZ3qPs26SNi4GKOu1n1ew9IScrftoqP/AYsU4cZa1q2I9 nl9o8amhX1jQx+Z0iU2BrdhBsWFXKFlFMxE7rGVyHRls+2boiofO/FpmaK48vgKDJGKEbnvTGIOt /YLyj/Iq3d6RNDiiMJ+ObjBkoRSli+0cW/5pMpgaSyYjIGtCPbcPcBM0AiExpD1WPS8ftpo22rLV ZuQr1KQlO5ddU0hkr0vgxhMTzdh/xFoIPuvicKVtzIONurhpMx+sAWjYVNlw28u1MKDGsK3cYurT K/xvv/QFeKUNgptr2XZhW02sfsd5LHzSwJRNSO8BR2YtTX5HO65EAKThN05uvfSSCrPbZn7DC1rF Mkv2AJwHNu+yqCaEBGm35DpDOXqUQ5+gG/wNu2bItRKVnFQeIXubV03XUoEgZm03kys+/GZplKSY sgmADE4QZzMYcu25BJaeGwxQi6QJU23kCMl7U5r3pRLetKeFiutUOH0e0NDujm+nFlSh4/vqg13f vjuAPVHOuP1AvireMFr2qjh/nEJHcS2JT2vPMFjT2fSgIQmLwVveYfBj/dUZFg4ATPn26hVQDJuU Mz/a6VPCtDJVTT6WRT0l5Tn6GP4doDbo1gnl2sJ69i7L3ssMeIgoZ9OpxoSRJNBEQX4zFk9E2T6e T60fWCwm4RbGAx7MpueceB3CRkfgXeCzgJt3zXWQR4vtBxctUSyAHj3FO5GYN7Lln013IfFYtlWi nPzE7f8EV8B3ahnSRSUj7G+06mZj1Q5MQmDWP6ndYGYU+HsfJyIrC9DPRBj6nY24Y4WurlV7xJfy MwLNnku5S/d1wUkwC3qSL+EX4UnHPlohDH/LjBFnCvAalUHgaELzHwkF2zpWnhZtzeDjaAVUARdO J3lhwp812QfNmuadfWxQhYzT/TWfeP/N+QEjk8aGdjfHXcnww8IgXbHj7YmkJChFO5gCfY29eSBX VhWsAAcCyOObwY/lU9HBQXm5Hg62NVFB5UWxLjcmv0etSHu7dBTNP6MxgNr2KdFzICSm9aFIvNvg niy2tF7jAmgrpTHsg0p1r7HQiNlxJWrq5wtIwFxQgaB5zhAJGQI7dR5karASd3gAkD6nmMnAphBe FAKrNOAahbgE4jyxzuDzInkBKOzRxP/i4X/EQazIr3HoxW6YHwXqKBzZPJBt2Oh4ZYk7AiZfLxdo Vr/XgdCHAmwvq7+859L64WlS7pcUr1iLoV0Xtx4iMCVxvA1mIJxX4xYSt1DLRhwWU0BeV+UeECep eTIAJElF+MHs3dSbOGoHZNJ+FeP1Ef1JuSI3a+Vg7WdVTHxr1J0StEqOzMzvl4dEMkIBParjz14n c4d5yVLPyjLKWt6u11vwmKYxGvsvVRbIIvq5oVyQmwcexPeV2Alom5RLtwGV5+1L6l91uuLX2q2Y u9vu/GuWbURdQatgz+m7Dm4T0X1sKMqlZz15KuE0HS75NJYOuxhPsfo/yAUBTTBKtDaGU2nhVTkx EQh7a324abwcV5ms3i7gbPEpUKlNip5H3+zDnr5GBiG7ykBvz54jdWO5kCvSENjUVY3XFNWCCVze 2Lx69RsiNp4ZfgrArGzL+5clPMArp0zLgonHlj67WvcpHkdfgDlfykwYkraH1u8lnhNvS6VrZd14 vBfyc0Mo8SnZKUOqC72dFf5HlZv1g3luUUpwfweyYBNQlCueMDy/nzJNxkwq7p91kqbapNWQ+x8v 7rP6yn9IndmJs+gAAz8VNxHxFbiiaO9oxRelLKlNlIIAEY28DMbCeXleStEhozMMLUvk9tOVE2VB zi3e0TpfFqepuIt+IPP0XiBjphvwOsE4uSaj5D0iU0T4KXmHhJ5/JrDR6wYVGcli+9yJ9WN+d7OM QSBQ+fhNa/MsZWgWwgCD04mTxZwssFdqX9YpK5iIPx3/qVZk+hdSyM+VjJfAhMYBUpdKRf6vy34z ngsNHrdsQ0LNij/KbZZ7Qh4tbPTSlnQFH24VtACiCQF466Wu+tHNMyRQhr+ShwDPILJgI5Bk62ub njPf3jceoCw9x6YGHgEscOab1wv8+9ZJ8mfDX9p9OPbGJufkkn9T6ogH+q8zWM0jYm3L8QTG8ywL Sww+DePbSZ0mwSOXquXSvk+w32TB0LVeAjdIyUcXDF1XaBicNt0t/TXg2BAKYX2JBvlXcjPyz/5a mmZLt7Z3LR1k5tdiXU7M1X9W5vdMemDJ51nBik+kQevOiN3B9qUljT4OLeVnZbDQ/8ouF5YlYWaz 4PO3EnxfVgii+gPfg9P30UkYVWrTiRZsDVa8taOQ7KykbZc0Nuqnfp5RAAPek85LLx7yallYHYbO L1Q8RAFRpmBs/1x1lp6Zj5nIZurAUJIW5yNu3Fu1vadWjbEMNEwiEywDC+rRu53O424twEqbNvHC 7C3pEwHrWQjCF2kH7qIqyLkmCK7C071mjwMtw2bDI0er6Xns6MbTQXestyEOzBc5jj/O1hCWkYDs PaKle66EwBAOmUrGv+MYmG6rhUkBAeE3koeyxCA29MNjlmraTaXbHPn4D7CF9Eyu3uTEDie+YS7w mc3NExHNCkoP7DNChLwNRutHG80PIIsRajuoxT9n1CwY2Aad7i8yEqD9usvqYXsHL0xs9Bv2gHjg QsMjMIBAAmJuRbKqi9s+GQ/GgLuRloP5fEeoSAzyYxVVuaS7fNZL3JOGpLEU31HILKscbvfgnUfT AiAGMWp+sAJLO+Aj6i08c5oTGCNSWvt/IXJ2cMbmK0ASKdHhMgJqnm6gtE1L+txD7Ryuo3/4Aovb outVcu85cu5F/zpykkQKVYAKLs43n8+3TaLg1emNDd79CEdODOQsPSm8HWd7zGCgztRG8OOiV/F9 WDoLasa734lDM63+8JoTWMF/scyn2DWjv1BOPMy76koR7RfQ6QQtnj4QA+OR1Cw0Ur7qDjvxpJYD cFMvicJyhdqjbHUpCgmaudUuZt6A98EEFnGAHUxYzKOTxkR61e2MjuEaIN26YSqo9oQYIrSs9e+1 TxeM80SBHG2sJ3ZPDgWBF5z64WR3rSOEcux3dtgENXKK9D3o3zR3KE79Wu8P9nTEeiweo+net5dI M+nXgLmG63Sl2nmp0NfeApTZszDmlcjt9x38tPRj/p2ZITxvLYi4A+heWFcesi6fQ8xGBwnGwU1j NvjALvbDlESUkCbjxhRC1qC0gJ2ASK05QiGxmXm/Hyph9x5OO0ZbmRKJDcnsHcYtrJtiPC4kQr0O 6WqVEph3UdMFLqtFZzh/CxNrJ0Xv7FqnQxGJvnxW2g+tCA2TSBcmDVssSNrAQkrW+1IF+V6/rHYC F3EZFwc6xzXJu5wKLaucQzieNHSNjzmZodT+6wSK1t+xLeMKRq5GBDeG3qRTC4KKNDU+zl77AKo/ UmE11bHzua64/eGFlpC0L7zqXZZsG4wtWXwygP+cnGaw/rbHCAYDixMWa0do2+WadQc3tN/Z8LP2 BozY98F2Dbwzxwlq0rzFVaM1yaoNt1hYoMOAZrrxAc6n08SdTZvnxiDq16sFgW0otEY21Ozptp9I bnmm9hemlELQ4Dp+gs8zhrSvmvFN3VJBor2j/v5LgcIEtp7eCxSsrhNg765834DRkCZ94OzJoSD0 wCjuZJg6X+OviB4kkUElUrNhJEqJesiMN4DXDR+mgAIonlCMYT0kyG3U+yEcUyASW37ErkQ9iqIu EV0kE5WTbYXXViJ7R+n7QpJYeVyqmAteDHENhO13mWUGknirVgTVoK4LRIwUbljjF4XjuGc0CG0S MskFfACWeiOyjCRJ8LiUamIeY99EcXbQGnLBvB9NPM5jq84vEba6rhM60EF29hojzvARcIhTafAZ dT5haGaKw9q2rQ1xCYPXv56ieMpmat9tiN1fJZfoLXQYxLHwhSj+wJX6Gl/vHvV58xemt5mIE32B 5Y+vSDzS6IsM76yDFqM9SfdW5VhOdZmTWzXsfVaWXlgvs45W8BJdMmv1wToJSkrGbP8smgK+qKvf 8o3B5GXx7CylJ45JhzYw/DPq6IN1cE5gfnPBcER87jHwWHYVq4tsd8zU/C0M87JjDJcl6TaRQfrf zGKLT+PVvkx7bTsi1chMKAzKOadYtgTEcKU9X6RFUFy0XkvsNCtVJW6z/QkSOpFf/4atYU3dfKeL 74cB4Nl/rY4fJeXgV8h8TDDLCpDVvL1xzL/e5ihtmSxz4Na8lSMpfpFAmQz5Fjf1S+8K/9G+hQCA SHtyk8d1myOKOHowL2vH1hDKJm9EcP1lCb+6KVpDJZzXB7JgjjWo2dbaklyrCYED/8E1aUxMxrgF lINobBCJIwMwDNNhdyj/nby9CeS7yVxGjE9Bt3GtHlP00R5f7SWbPf6iPkcOP2D0cFRcSgk/zerJ 4BxUFI7xPAgD/MKndl1GImWIHtvuBLVpbwneG3hq2Sck/Bx5vvVYwjLsFSwFsp4vNi2yISNpVtQA W85uAnBK44K0eOmrXhb9zyRQyg30OJIEVj3OdQf4ccA4DrFZcVHnocsk6tBBzn2q3XSZTfV+qOnJ LW3eVm8ow71eD5TAk98bQp3aDoDSTdlWSA7Yx5ct5xZfrYZt43B4NniQGnf1CH0zGtehgvJa4Qjr FfHNHxiMx8NMlF3wzzqZHVj7kGhym1Yes9xN0MI0VCWaYUgmRT4NOpyRaNTNJbq+iKnRZFTzffem ONSFhHLXoICswEKBlpDCIiPOSmJ3UATikiU8IUt/vF8J9e2P143yV2nHwWlr3Y9MUHpeh7mx90Jg I4Fo+W8Kr0YCnXmsArKsQw9wseUWT+PUKRMa8haxUkbjktZjVNuDNFm6SehSSQyIBWO2sFwYY4UZ 2YNVj4xQ2/7VPY87354k4E9M4nYF5L2tK/+V4XmP4rNomlsRjsG6VOO6C/NbEhFzUESo0CUqy0PC 1OZI6GIE7VRof9Ww69i6oUYSz05AggpBpjZVViHSop/f4RyOqQ7XRQDoscI7KIvhLwA8nwF5tFKj 9fR9iyuNvI5BAu+44i4qbv6W8z/MtcqEpGO56Ul3xFceOaCzbxzJIbWItzBu6bnE5QTkTtbPT+nv /DJwEevE3Y8Y0JFRznIeihrQUcEa2rcnCQGrzuTSwL0lVLmpm8c0CfzzJp3CsDI3Ira1lhbZPZ59 fp/jwoBW/AOEXR7ru1SuKdzKf/95XvteI1Mwzg79MJkCjIxgujdhpx48K7yEAjTjPUVHZj/xHEfk yFOxoJsfc4Qs/bN3ArqNN6E3oJeAQhThdn3KDe0ejCHlh0d3Sbf3sbj5S7kZpFVtBUA3S7FQ2rXz nLYTkcSUB9IH+7IAZksIQ9eNUPzAmgAETzIcflAdcht1KTMm3SZFpbEOzYDhiZ2AK1dSMHeTkfWz s9/wRxcNmuEZFodYPeFE7OLfpm9ElSZ93EBIyBE70Y114XpWPG6TXrOA3YGxF/tJQEff/atxyZpG OEoMHX4DKKN8MsTq6IDvocPo0SyRvNwy3LLfqpOq/w0cyAcAqESUWRMrYZXJTMqcIoarlHHkvPjg RHvRczhBBLobTGjPE+1pICq29awg2sJCE+seGu5Yutzg6+iaKh3p+wvgIbDNBekymIG2YE7bzZIi y28P34IYP0ZkJN59fNXvSU780Q5o6D5btLVyoF8vDiagOvb5TElJPWBtfdpHrlj22uyCNnjiwIja sbqoKDKoYbzWOXQduh8DW44QaqJK+/6E3dFT/Xlz3tCYQrHmYFZcvBymfpGilMIMXroWvNDyskTG I3RvRVc0IH/KDnFP1m1MxufRhKEDMZdROkf3KZ8nbfy0OZxRD47pke3hgrD0yEdtiB59IPIKgaVJ LrFJZ2wNQ57ZDWrOXuYduxJ4WjI43Zbsr2jQIT/3qash0wgmOQW6t11v9r3Ge9FqYLqCPfG3cKT1 AbfWMtrY8zvNhNdiZO11sd6qhR8cOveTnzYD94p4V/ACTgID6h/p9MoSYBmSbjh26Voyvit7QQCJ +++sHOUrAlch3OhMwo5pwkV9yhJCyrpXNT9QM0BMp7pYuD1j3TrsgvdWwgZBWtS7gC6l0siJip3n koDAJxSFOaaFoPuTiXA/ZHduflFiwLjxTrhz5rmDJARsPuAOO3I2MJkuh9DADem7vYBRYWPv4LcW pM77yqxfVntQYheK54RXH5I58iJ3qUpqJBK6XGSunAxDU41ancOWwdSIG4AUlaIRhAMatz4lV7sI CJSn4wvyoDbhKqgBLu9bxDRuOyG14IkcczHz4uPeZbFpSOX4ajxqQFdI/HTC93SLAIwSSnfJFmGK /MBoTc9OQe3DgkaFAXOeOHtbTZSQ1KakoweB8EY7xHehhQbD7YRCzmU9bFMEbtCo+3ikZeecb/VW 6mgGpJ+U288KxkuYK8e5DnXf3IuFjAMUZpyVpKvlHWMhKwIxvFS8fy2RWFbTIIRvs/HCfAD36g0l Zpd4f7MFO9+dR3hTGWcl94rmQDDluwbPAijtHInpfYT+zt2HradkAT2n+5CC2GBKfty4+yhCNVaf B9eMbt8KSki1MG6Tda/QQJRU7xgugd2Okbmgp0GsBSxdgVkXCUBFWbVnNPOc6xSd+cI0aKZBM4xG Fl/xJEH5pCWoGiTv8ZmP4PKS5wiEi8f4C9N9Y1C46qKN5oe5VVHIeaXq2eqxRgzHn6Jr5zyTgmEV iD6ZyNDL4Tg8m5UCAYG6WyWe+YbxRTx5TiwcPwN+uJeH+au5qhNrpPIE41C/zIPiImgnGCEAz3/+ 9xKYuvIx5JWQ7vmXIKV5Wtx4tKL8DO9rULIcC9abI4dOFoW4BKZkP6gYtjwnd5+cuKnVPwwaS33x lYUttUdTqs0u2raFtF7Gu9PM7jOUxFcqNr9GnEInC17DvuVH3T9A8ZBXurj4ODJGka+N06QbN2Gy RLrjil++64e9bT3YoQ8ngOYTm6yhKR/z3+7JJ/Ged0BZ8F6+zNgJZwUeJ2/qeEA/obBcCUFkicl7 /p2cokUrSdI3nb5zppyLahfSQk3OxM7zZ4dYQBj1FDjcfiLm/wa/N+6pIfnzr3ZG1q+PSjhWZttp K5ZTBehrWWYwwIBhZzznmZJjzJbtcly0QruAjKF7V9t8/TpzjIPy1bRvp1dtYnSxovX8wlw/4Xa2 efwq9dIhWz/9TV2HvEBWQxQXoIf9yvmeHl6tcU0iQkpDAnOujfp2gvz4SFQOjs89X/W7iubHVnHF ao/po0p5tio70jBfy/6+LXfa5x/T6q75aOmOO7nEPXI2tBPLhz/R9nKvUTGnZO2S9m7MJd8ZYR1u oZ7BtM3q0g17G4xV6sK86cBL1BSWqu2yR7EZA5Q+xgAJ8rWuhAWE8lvl2NnLby1BWzq+T3wySKtE gqiibGiUZ6NSBkcByo2YE65M5xazOuRoI5QkPqnCHSBE0+C4vXkUr5KIUmGF6bvMqOJHfY3hGbBQ t/QJHQ0JS3zRfV59aScmrmxSHmw9hP3D7AFsLDe7+g6KYa2ekDeIEDrWJkEI2zNb6dSs+lllhnqS 7O/sPvnjEoFEDLIOPX1GmAD/1SZj6EgGW/uH0/LlIR9QaZLG6D9jLTQ15LVad7Mw7co1ix1sxvhz uz2cngEnF9UrewuZ6VApkUh6lu1m6qIJCjEimgVNw6Qi62y9KaQZeJnpIrHOL2W4NQe9gPtbLZ9N EliceEsg3N5je+85rz/NtnvoaMi1UAWg1K/kH1GVu1GLrj14rG81NStCzNS8dBTKskuVMkqgMDTQ EzX/bFjVDUIL/25wdqN8wRxVEIBBbCfMWVPwdcTWt/D1np4TFdShPXen0DuS193uJcpJdE4ebU9K 4hevuvUU0rdtVOun9RoDuq5bgamwE4ahobZVZhtygw8MCsF7AjBSLDA2o+TA/RX19Jy4HAj3oSSE ZfNZ6i0JOBD+PTORXJdiUnMskWQAEIS396COCgPI03WNr7Bz5qQCfhPCZNX7FSEBRMGy21e7iMx+ kiEiThymcEHC5B2iBDeFOM9kkKnR9o6mJAIqzsxyMRYL5GIx6hgb8Kbscp6Dd3xl0LKjTFUY+DVB NvRSFh1HyUslf86e4MeZ3C3/HLhAI4IGeIdHVqWyV4fr+E3Fu3qInyZF1rMSMnWYT8XSIe/dfS1m bJdvvL1mrt5fszsjJM1k+Pv1I53q1bCscdkcFUaoRkP0xQteJ9Qf4NG7H6qOgx+bqi/USdJT1NGi lyTHPa2a79B+njcCy3N3W5F9DWl31pm5Qqrf7o0FPxa2BrIpa8dyoS7Am2ja0y2hHzyVeG0/r7mD eO04VOCFFRgE9p098FvNSLVM18SbQKg3/Q3GS4XOjrSSBnmyzTaIt/OJufzsw0shh9lkrGqPCpbi azAphgiOp311lzAaS1Od4OWs+TlhBwdakf39z2D4qgVoGSFlcpX29nQAjN910r6N9aqoGcRnP+tL eJyj9SKMLY9gFCDHbdnguNVdDAigurcsXGdWTGRl0mZtFrobqlPJ5pSPdOIb5QDxvjps2vVem+Sb wyw2cX68oBE93iNWwFsuqtyAwvxvp15325XkZXMqNOFxUaiaCy5eox8bSHADvXU61By5yKl4+9vi 2zcKw/zLBugU5a41I9i0FqsBsnaGNrzSNzwj0Fr3FYoD+KGzMtdBSD7jIzKKqSHdwDCtNAAL7pth R2yl8b0QeIugC7blF3/VFdyAecWvFNv75+4dAnC3BbTcbBRAYYyOhSMgAjCmuAVJymG57Qo0JIE0 ULRbCuEh+gPw9m269jRc2wGV13tpmVc+jtXpAjNzvGWyLC3I60G/bMeemsyaXq5AihbhkIOuJgVh Fx+sd6286mC9FKhRhblpiqkqAGXVIk9tEIC4pUZZck/Ilmwp9BjmYooiZMQwdK7eed0w95zr5b8I U+icyxrjBnb3Z9TeKg4hxbrP6IkeDVVLVfdHKixTTlR7hd42kZ/nP5HwUqRIKZeUPFYONbfvu5jL oG7H017z6Rg7NBrnk6X7IlOejvRDrwx91LSETY+30FZojR3ATK7dcGXjUCt2RI4Q9vt2ZppnUKYD 1+KUXm3bwpVv2qF2sucOEYMz3prxK8vexXQLnRWD6oma29H6+rqeZrPlzki1SCetx6zM7zm4M5YY U2h3jYMxLpOx3GyM+ebTG7apR094cLFFwb9aFHSuyPK7fKEX0Hk4B4qViAOFIh4kJwuNgeiliFqg QRXDvRfk3KAL8C0gp5vrwXgIuFrNkjb/2XZVPPvOFEpS+46XXygeLHYBMedEcodv9+2x6U4pIfqO 9jN3C4SArf1zL+sFn9qvtsYAX9SsDNJMdg4VkUoF+Lo9MuNFI25QmEfwvqEbWb0PppXwFFGnDqSe l/IaZj9HSabIhj7r8ek2+RabPt2ZlOwXFiujPlY1VzCvDTpQRfe/hNvITeoCkHzS/XdGfjbxKaJ4 +OJPFzwE7Zf12GeJcN6yqb3rDPYH3CIVA7hlz09BDXHdtBqwZfNil5XtuuBRBKw5JcTN7RfLJZQ/ usnKxMRS0Tq2Z4HUrSfPxfJzIsoRWi4KTXF33hJ77pVIdDK2a8r2I5RLMxqXwzqUpMocvb7ybK/m 5MRl3kVgCls5+CLiqEnBxMXhZN9W6Ft8+ClcQupgVqjyHFlVCbCIXOSci8pWXEPpPqj1YQS8V8tN uFXFL6aAQv9m4qPbBAjIXr2i6acQhGuncEwYV+F5gwXzRzQCmV6B2ccNAlk9FX+M3a0BdjTQSNqo dMf80byqiIHVxrbu0W/0c3fjyc2quQ2jin6fenM4qFo36ZfAi5Lt2Y3F0X8ABLjbl1tqwI/eSgLe I+JI/TuXZPskMOAN7EaLf7zPKMRNMFKJ8R29CEl+NC4FZgnT3v9wrYhkhn1jwtsyvQTg0/kI1HA9 L60oWZgClFVqMQl65/3NRI9j2H2UYlFaHdhRYYOMkK+/wRap/TtdmE4Vwiyjw0IIdQZPMbV+x6Ch TIVw9t/h/CZJ30n9I9K5scUVZq+pgZguEYjD1tsAqawYuSgLg1v0f4HxpXkHerYFQ7QVztxKHUd8 9bmsMvvnvGdDAF46wYHuux5QkimXBtJToLeQiyt/LMuI7FBfSWWUgV/ozwojUVAbPjpkb3dlbdJr EzXypbSgR/Uc/Kms+OEjzqSGogAPydpJPQTLeW9x9bLC+UfdCCZHgJMTUBYcGt6fxekLQiGyxAWi bl5krkGJDBjk7zgg/pvgoEMelk72j61JYvpayJdSbvQm28KjaFconTSGo6mxFXFZzOjFC4h2dHY5 m0OQAV35F6e2PpJlT/woFS/EZ+Z+ulCIce3s0r7IVniiO/mj/be+iYTZjjkiTqoigJu9lHNwlgNq 87jhjIu60CMAyX54Ht8TN6fgm8fLNMdd0WSQoAMac1mE4Je7/+RlvlzU1qSdQpcWdmFRK0lbPZc9 PYMCTQMByCS59P9eCapOtEebP+stSjcvhmIFemdKPAqfccjlolV1j5sM3qeVzzOeilVznTwl96tH UcS58RppzRbYTovn4zc9wyZpcC321AzOnpNnxkDqX37CfHe+gWGwviOT5OoRBeWS0iCLbeOCe9X2 O4R0dirT0rzh/uoCT40LAXyhUw3jDdqJl7owV9TgueOeV/6SPbSPJ5llEGbYS/J1MUAe1+vu491q ZNMiFJOpy+a0HvruMGfY7PEn9idPDIeWd7kAijcEir6+TQJGNCveKd6p0jINMWoXyIM+fTxs7FwE zB7056sXk57y+hutofuVoraaES3kpU5gkt7OGDUJZA7Fw3Detq8tD6Yy6F2g2QV/uQNQ8hcZnPZi DR5JbXtka4vzZOdnXeUpBcM/sY04UB/VCvo2qjIySNrUz6VK2sN8fWaVPc6QdGib2y2UK8RvyoD9 yQjpjn87kdNr6KLzZ7OIdIhIzRfsOTz9dOcrwpvFKOtEzcg555YPFw87gmSrmU0H8nbqOhaVmT0F Ie7ad92A1KLpxNMRlqtTUulYaejNBlbh5bgaEdzgsUCb1eCOYZK+8mfS3ywYAN7ES13JmWyy7k1P 5z6BR8yLjgcefUi3QE745HAzopOu9T/VxZN9gCXTHdzK8nA9cODuF27OFFaV7JwdExvOcwE1vGRM /LHweWvgmzMkMrHpJfFrPWnOBdjRlNBjXBfhqqx2yeMy5OA54c7EwF1ibchtE17B1JkaFZHDwkoM VbUCiWJp26Pyo6W04J/FctyJ0UuTRW4QFKXd6v/afLOjsBDR/f9G1nOkMv1HB1auEigeBmSB3MdB aoC4njBo246axqf4ZYy4hdaGJgXoPCW24gkAMTGPhPOSwdir5C1E2aV7VmWghSkPaFvURA6RSHQV XkTALlZPb2FnUw4qk6PyVO4K9mWLA1wo/Ciriv71hTNTZB1Vyxvet/zeFHxOP7j9d45R27S5+Xq2 3mNbXLclhN/Fy5/yIIoYc40tkClhTHI0CbVJxLNytYBxQkLMQvbpiluz0JV3xb4n6eHfrK6pl5po tCjgeeizyGQqAtoQKLQEhrP4cg0Fv1BGC0I+lcYkT/Ds+w2dAVeHhLppauZ9x4xmy0derjhGr2HM vWaiq9jh4FJlwb+qiN1O2tLN2+JzsZ8ufxA2qdWF/cI36wcHhtqgYo2w5azpmhdzoKCIkUNnFtIQ K5HZiJAZgqDPmbUnPD1yYj4yE7800+XR6hgfsYX46ZCD/4gzMuWTL+Uu/CPw16XBrBjaCwH1H8dF Rv51HAxSuDcSHW6QHcuwcghLXWU544pTXcZweNc9FdFrpZUHHpzINwjK/7MM+NyAnpf+ZiXoUE70 cS7gxPi668vP65a7axlzt23Ds2UqBb9GuX1c4P/8b2LDoanDNA+87vyC6y9bKNvWOztiv6fKmxtl W57xQ18fKt/3Dun2l5ojNMbUPMS6BDLArXRGtC7Aa6VwWS4MvFFgxmmgjqIHMQFJnO5pjx89Z6JE rN19LWgRng5ibb8Ue07ixxpWmNRNf5QBcccD1GL3Bqb5+gSonM84X21PkdQYLxI8+bMuVabZfoth Sl41wQ3knuY9Uq0Ues6yDXlQDgQaVI/bmm/6xsKfttThmbpUKiU5RdWelGbbiY5PNN+91VfWBtaz yExMCK8XT2LPxr0kdWlhsWPwTD0/S2jGFj9rT3Kdh7gk1V6DNsgkQPSb9tfx23WAwph4puaLi9tv j3Ux+mRVcysxMceH9RvfJ8kHesMvktg/BvtlV/SG15wIJEUQNCBaCdB+yI97c5GNMgB/4oDqfddM N89nVFCihMsF8f78Wkd0CTWowEBhOQsg2jPnwoJbCjwkh+QLcJ3YE2hD06VxcTzbFk/oZ62+IZQz Kd13FLRWArazBSAwkAoJqJWmKFsNMCN+MO7H6wNGf8U1GqT4IURhp/9hHhssODt2CtFdMMS3GCD3 zbFfoy88XOZ0TMngZ2FuhN7Ihs6fI/huMutWp4BQ2d+USWPxNmIpT3MkbG3xqOll2WrNGsPHc23i /63IViXC7yp8aSR7INPI5pra6OLyqaAZJFZ7HcZ1riQPZmrmF3LVSDCLlBWSwJg3Ih+LJF3QqyX4 lEBsMbMDsrDd00eB6BEHHLnaqq7qOmDEcyfIdf+BonlJ5Y8nLYPLWa2lVntCFDy3LUcYStILpOoz wGFbVtz8SJr6fqdc48BToL6qZStDQ32lUAIOJi5/LQ08FnHsVsA8HYNApMnzMiLcdo96YMiZY32O gTjl4myaYBRI+HU6LrCf4l4A1ekX50WKpPcNynVNemto/xwnRKacySmMCPXOx9yaNBOshOyedWsl RRWSn7BfPQUlZQxCy+kfCZbW2es0mwet8yymi+opompB/xbkY4OJYEdCo00nIgayj4798iP/b5iN zUuTdaOYw6ZyC/VWLAanJzJGtjK41+DL8kLzDyiqR3E2LAyvOe7FY2Q9TOpShPpLvhsoI+rWa3kY JfdnC+L0dzD1CtolbBLqJPZrH3noALGI3Vwic+OPlRuajw9UIUdwd7xS2EDWvDFy8k+i+gH12XJ4 k7H9CO11Z5ZrG58iDC8PAZ9H2KIEWAuZ/eB51ft+GrHcDGSu5ZXlK+YMsEksiNLAlW6T+5tizm+a +fxGmakoN9rSuiG9H14+HxdYB6YtytHLPzUUMyzPr3htQ7oadT6jV2qoej+1ZBAyEDXS0+m9zneV volFi6l/5hL0b7i35hMBcsRoRMqbzrGqhivxOGPUzzixR1/+DhDhszm/yFY6U0dqGvU27D7dVdX7 MWeGkl7zaP7jnjjcJPIudxsnvDmY9CGdglrLFhanp1s1Bo7uVCyRhXYjTEGlCCwKdYQT3pnseBEX lW3jQl8tQ++Y8Vf6lvaglyrOn/0bQ+2qFqO4gcExfdLEv6MDG28rlVGEaqb8nS7Zzrg9Jny2I6/j UDLypTVaZ0oschrdXzfphEIhnhfGh3FBKyBVh6j2AXhdgc1w/klzWIKktZWLzJ+eDvN03bFkoJAh xjBbDMsvm34z5AaMjz05cSkgpcX2+d0ZpcMxeMHrfBYtzifj/2qMDmvYvsvQtdWBRQ0qoYRjOSLa LogAeAe4+HzfMQqBwwiE6wIm5epFVD6OZ8siH+ewCbWXcv3HBCFfSM/x1aFESO0pCM9S4Cq3xCI3 usPwjDnQtj9Vu+anfzc7G/rGV53SVQvx10DELc18s+RL9rpnFSWBqcod8FH8QRKV9hy7woXuKC6l SBA5+xVPx9ebcSETLWLKxi/Xpy3EZmapIe2l2VRD5fJtjwl3BEMLUVmJYIZSD/i2+MN7Kft0IkSl btO8W/4Q2YTd3rMD65G0JBpcIUbhXXRoZCiCGjXK9f4KgyvmdX+/EKuHDqrFvbYAMr1qP9hqY9nh AXoKPwYZcwJmXP1x4Q4BQD/6hFrwjnsrmWqXiFaVdzROwS2YgAMJXhAAETN2SZbnmqIQfkbLCY2f vl71Hol/g/5L9A6aK8LbAk8PrSWx1rdwV7VTtUImhFmqQDNdlB9caGmqH7L7XzE9N0gnDX1KH37V XdL+If6iLT5V5aCodNlR7bxgX8+B/rKgvntWMUUvvXo1fivK+Md+4hbrw7HF8BAGnIzWD+zsmyKA fTxQ4DBYcW0QMUQW4sWPtVbFqw5PNUhKT6QVzPR72j9Qc1Eiut/vWM5l2Os2IACDws55daIIFFRp j0QuT9M9/3vd4QwBRDGS9iNNX1ZH9pZHKBjGpilsBAhQRVYIjeV5/C9y8VjVU7kvgSFJy5qnZMGE lnELcksUruO/1HvLpp1rya78j2bypfIIhSTtEnp5o+IKwCKClRYC8S0tijYaAHb8dpy2zK1bNoGG cD/tGYos2iJOQJK4KmBTtIDjUMZEzBltOAdtlCAFJRG15uclqNCAqb2ReZiw7jqnFAdsLclH7vEv 2H3PdCT9PY+mp8TdU1xpcr9aknvmJd7KSXwehLB7ObZnFZgNG3JqN/p9VL1nCoO8F1heXKbuOTh4 1oQaEgGv7tGug62QYNOqj9gAA3whNJC6Dyj9egqERP4pEExiguMyl8ZIFbzB1dwYzUd5MuMW+qLX t6OlLBFTrbhaaK8wfaz4HsgnmQ5t6Kv5WkV4AslIs5acwF16vtM7UHA3KTPcXScXotBLpPCAPf1W mK/fRv2S+yW/2If0wVGmb2LcqpFEsxeRQR4+RwJMZ3ciFtNqVYHHrQaOhqwwb5ua5szyNAi/pDIT fVUV7R6YMnQyBaz025AXQ6+mcSaLROf17xzBt7DLwHePulSSryG13tAbChvGMMjQT37f/qpvFqYj +sLYxREVrSJgk7epx7OfKVk33xebzmiW4cYiwdm4cuaYchx6rIJvjpKIKUuVySz5OIdL+NcQAHD4 5SB4+1toE5kA3BDQBGe8AZJ2l376E0wtcBmlVO7slI4W5NcGwBBl5Q8NLngPhafFR5QPeUYsUrxj yn9U/NfjdDRiLh6Vg4j1yR2NE+vllVss73SRsI2FTaUhcPPFu+awVCkpGqId9DSLaU9OHhqIwoS1 B2KHJEi2jSqCZDF9C0T3tCwTG4u3MUu+C9Cb7n1wev1CG6s6yq4Ahw1mcgjlu5LmaLkgvFXD53Si I3VXwZADDhZ4KgQSZFNMAokioVF2A93lWBvLjNQmx6P9+vZvGaaYagUUwwz/yY2fhEr9nxcMq1dR OSFSuYWpQCL/nMOU7Cx1SCbQLMENa4XhUjQdQE/3FVFUrqg/VM5D6n8dHXqezw22WUZI90AmIB6A tdgwnCTm69uOlFaWGYY4hhnSnxWGZgs+tj83ADcKM4Z2WuvnZryDjzE1F04Q5zY9WCgpb4uCPmWH kSmHEZWgSr6YnObY/xTlvupP/jgmwpiKfEgTFSdAILvQBjrBwtQ88GEZZCXxuf36nZOT7y9WmF4R aYc79l73ST5o2ilYOkp4po761dU6II4Raua3qZaLDyxarHEEwvnGNxhyVhwbwwVaUFsEfh+XplhV bwzRxJo9GryJVIk8x9llsfR3XmnOI47BnKazr6sirdSsNIlItOk3tgsNmTCerIpo4vIA5Sf2tDJm stOizopkpmDamJb3KhSOAyhhJlFs4v9O15VexOX18PGNDOjpncKNmClIOP4F3ulViswO6E6sM3b/ LJyNcY/kjZ3d4ebI6WhAfUCuqyOJJiZsyephmPa9rZCMb3Tk5xkdaHUirIBQL14KMmAQVQK5qtHm zDHG0YfqpfK/3aow9SwCGCU9mcl+upXh36MKFIeUSfR9Jtlx3JtR8/rlmu7qVoxcDiosL+AAn7Cb JSToUZW/jdQC/abX49ig1Omwe7fHSPK9I7J2EdiM8/7wT0MYcKBZY15Ca6vGig0aP1EkIojhUCd8 wuvXLb8mLyXbFCOe2c6IdCw/XtFdw45tnSJ8ecfctPkUuJGXVK+cWfLN6F4V1djsU/vPuFrewsOS mEYq4rO/kFEFBRfOIf7j6PN8T3zbS+q+W8awd5oAET74dr7lQ672UHki7uGaKXTBW/h8niEOU+Nq nfa3KvUtGQhuC/2phKvzcXHv9wVl5uVhk6VCksiUZkZ3OnJBkpGoSDM3u6rZ2Z64EwCRGNVAnmaR Ay5qpHNIyUYEjC/MZKTdbHrWiUZ7VDbRnE/iIow9OOMCN1V3CH9ql5QmbLDR3dwFcp83RZ7QPqqR HMFN2rO8T//VKHZl3Je3GapmIEK10ogDgL1A/aVIZyXZ87Axm6j4FlzbmLGZyH0in5CyNwxXf0WO W7AAbF/Nl9FgPVgEPzlztMGuMcvddsdM2voOOIlXdhETznmyVMog+MgS/vdu1H4CWJgJIAKAZnPX 0fcgiwVSq53qIfQQV1MZGhmIT6AzCLXoAbDZ2JHK0EBfuLiJfebX1DC4SdFrByPEOACD/rqH/nSO eSIMCtpT7sURFQ4fVuCxTUo5IKNtfUVAMtZOT+nIdlwAOyPhe07QJS9jaSKFJbFLeAHD1wkrUMkB GWxQJfpbhPXhFQICj//hBuZZcpEN59WS6ugFO4x8c2IgpKEKh4DL3PA3XiZ1ErEnvqayJ88Byxn7 7Ms49Pk/7wiROawF3zJEtmhs1WkshkhMDaEb4uXnzQcXrRhjAOHhdr+PJlxf7PVj3rNplkdC89hI hAA8EhaTXxIZ4SwBhOZ/gnMaad66rpsZ6QGUTaBi499PkX1+zfRIa47WXD3y1ernADUOwOwxj3h2 L6pU1V79T4fmg8wvh4VFtLPofvflfKtCZu2JxRvh0MPcP63Q0K2hf9YS3yPlL0TqYeLyS6Q30fcY JVayNG6IfUruaK/oiuqJ/0xmixAWKn7pLLBConiBfmm9qTYC7Y4LtETJ4ZRLLBZsJFTAK6uDbXx9 SxYEFJZVNceosv3IAuCHGOF0qIukJ6yLipfAKwqkWy8FCrvHQLiv1Wry+p6fizfWoRRynjcga41X 4G08k9frHSHwWmEK0K6ybO2Uaq0wXPiGotgmgUxiDCq4JBDdGjOZVh1+4Yer9ivojzv7U5IzqIFV JqZUE/Lw+RMYJxMG2zOfrs5LCgvCBJvVREonaSpIvD07NCmPz3fWlCacgaeXSU3U3NheM9QsTiXT VbutBhKY5p1o37sByvmDV/9iJp0vCw4/ggygs2M11WZmw4pMJPI/pWj0Vee867wluCmGp+9YUQba Hr5qElTJcAqzv4UEa3PIxeSP4QWBBtbwBV8osrMbG99cqWuBQoVlR73Qp0KaSdIHJIl8VnAKR6ay e8cr5WOov6yv/TP5Xe6DA74lZcYd5h9eztuZDUOA4cTFA1jJVcjuSHWEs2M2SQ== `protect end_protected
gpl-3.0
0a0a5015d16c0d198cf2ade742c534a6
0.952227
1.829752
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/hdl/design_1.vhd
1
376,192
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016 --Date : Thu Jun 23 01:53:37 2016 --Host : darkin-UX303LN running 64-bit elementary OS Freya --Command : generate_target design_1.bd --Design : design_1 --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity m00_couplers_imp_1R706YB is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awvalid : out STD_LOGIC; M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 ); M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 ); M_AXI_rlast : in STD_LOGIC; M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_wlast : out STD_LOGIC; M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end m00_couplers_imp_1R706YB; architecture STRUCTURE of m00_couplers_imp_1R706YB is component design_1_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component design_1_auto_pc_0; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 ); signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 ); signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC; signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC; signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC; signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC; signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC; begin M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0); M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0); M_AXI_arid(0) <= auto_pc_to_m00_couplers_ARID(0); M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0); M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0); M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0); M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0); M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0); M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0); M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0); M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0); M_AXI_awid(0) <= auto_pc_to_m00_couplers_AWID(0); M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0); M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0); M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0); M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0); M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0); M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID; M_AXI_bready <= auto_pc_to_m00_couplers_BREADY; M_AXI_rready <= auto_pc_to_m00_couplers_RREADY; M_AXI_wdata(63 downto 0) <= auto_pc_to_m00_couplers_WDATA(63 downto 0); M_AXI_wid(0) <= auto_pc_to_m00_couplers_WID(0); M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST; M_AXI_wstrb(7 downto 0) <= auto_pc_to_m00_couplers_WSTRB(7 downto 0); M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY; S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY; S_AXI_bid(0) <= m00_couplers_to_auto_pc_BID(0); S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID; S_AXI_rdata(63 downto 0) <= m00_couplers_to_auto_pc_RDATA(63 downto 0); S_AXI_rid(0) <= m00_couplers_to_auto_pc_RID(0); S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID; S_AXI_wready <= m00_couplers_to_auto_pc_WREADY; auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready; auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready; auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0); auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_m00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0); auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast; auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_m00_couplers_WREADY <= M_AXI_wready; m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); m00_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0); m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0); m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0); m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); m00_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0); m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0); m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0); m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; m00_couplers_to_auto_pc_BREADY <= S_AXI_bready; m00_couplers_to_auto_pc_RREADY <= S_AXI_rready; m00_couplers_to_auto_pc_WDATA(63 downto 0) <= S_AXI_wdata(63 downto 0); m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; m00_couplers_to_auto_pc_WSTRB(7 downto 0) <= S_AXI_wstrb(7 downto 0); m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component design_1_auto_pc_0 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1(0), m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0), m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0), m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0), m_axi_arid(0) => auto_pc_to_m00_couplers_ARID(0), m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0), m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0), m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0), m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0), m_axi_arready => auto_pc_to_m00_couplers_ARREADY, m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0), m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0), m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0), m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0), m_axi_awid(0) => auto_pc_to_m00_couplers_AWID(0), m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0), m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0), m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0), m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0), m_axi_awready => auto_pc_to_m00_couplers_AWREADY, m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0), m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID, m_axi_bid(0) => auto_pc_to_m00_couplers_BID(0), m_axi_bready => auto_pc_to_m00_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_m00_couplers_BVALID, m_axi_rdata(63 downto 0) => auto_pc_to_m00_couplers_RDATA(63 downto 0), m_axi_rid(0) => auto_pc_to_m00_couplers_RID(0), m_axi_rlast => auto_pc_to_m00_couplers_RLAST, m_axi_rready => auto_pc_to_m00_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_m00_couplers_RVALID, m_axi_wdata(63 downto 0) => auto_pc_to_m00_couplers_WDATA(63 downto 0), m_axi_wid(0) => auto_pc_to_m00_couplers_WID(0), m_axi_wlast => auto_pc_to_m00_couplers_WLAST, m_axi_wready => auto_pc_to_m00_couplers_WREADY, m_axi_wstrb(7 downto 0) => auto_pc_to_m00_couplers_WSTRB(7 downto 0), m_axi_wvalid => auto_pc_to_m00_couplers_WVALID, s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(0) => m00_couplers_to_auto_pc_ARID(0), s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0), s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0), s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => m00_couplers_to_auto_pc_ARREADY, s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0), s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(0) => m00_couplers_to_auto_pc_AWID(0), s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0), s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0), s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => m00_couplers_to_auto_pc_AWREADY, s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0), s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID, s_axi_bid(0) => m00_couplers_to_auto_pc_BID(0), s_axi_bready => m00_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => m00_couplers_to_auto_pc_BVALID, s_axi_rdata(63 downto 0) => m00_couplers_to_auto_pc_RDATA(63 downto 0), s_axi_rid(0) => m00_couplers_to_auto_pc_RID(0), s_axi_rlast => m00_couplers_to_auto_pc_RLAST, s_axi_rready => m00_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => m00_couplers_to_auto_pc_RVALID, s_axi_wdata(63 downto 0) => m00_couplers_to_auto_pc_WDATA(63 downto 0), s_axi_wlast => m00_couplers_to_auto_pc_WLAST, s_axi_wready => m00_couplers_to_auto_pc_WREADY, s_axi_wstrb(7 downto 0) => m00_couplers_to_auto_pc_WSTRB(7 downto 0), s_axi_wvalid => m00_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity m00_couplers_imp_OBU1DD is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_wready : in STD_LOGIC; M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end m00_couplers_imp_OBU1DD; architecture STRUCTURE of m00_couplers_imp_OBU1DD is component design_1_auto_pc_1 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component design_1_auto_pc_1; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC; signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC; signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC; signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_auto_pc_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); begin M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0); M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0); M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID; M_AXI_bready <= auto_pc_to_m00_couplers_BREADY; M_AXI_rready <= auto_pc_to_m00_couplers_RREADY; M_AXI_wdata(31 downto 0) <= auto_pc_to_m00_couplers_WDATA(31 downto 0); M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY; S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY; S_AXI_bid(11 downto 0) <= m00_couplers_to_auto_pc_BID(11 downto 0); S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID; S_AXI_rdata(31 downto 0) <= m00_couplers_to_auto_pc_RDATA(31 downto 0); S_AXI_rid(11 downto 0) <= m00_couplers_to_auto_pc_RID(11 downto 0); S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID; S_AXI_wready <= m00_couplers_to_auto_pc_WREADY; auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready; auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready; auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_m00_couplers_WREADY <= M_AXI_wready; m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); m00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0); m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0); m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); m00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0); m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0); m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; m00_couplers_to_auto_pc_BREADY <= S_AXI_bready; m00_couplers_to_auto_pc_RREADY <= S_AXI_rready; m00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; m00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component design_1_auto_pc_1 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1(0), m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0), m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0), m_axi_arready => auto_pc_to_m00_couplers_ARREADY, m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0), m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0), m_axi_awready => auto_pc_to_m00_couplers_AWREADY, m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID, m_axi_bready => auto_pc_to_m00_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_m00_couplers_BVALID, m_axi_rdata(31 downto 0) => auto_pc_to_m00_couplers_RDATA(31 downto 0), m_axi_rready => auto_pc_to_m00_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_m00_couplers_RVALID, m_axi_wdata(31 downto 0) => auto_pc_to_m00_couplers_WDATA(31 downto 0), m_axi_wready => auto_pc_to_m00_couplers_WREADY, m_axi_wstrb(3 downto 0) => NLW_auto_pc_m_axi_wstrb_UNCONNECTED(3 downto 0), m_axi_wvalid => auto_pc_to_m00_couplers_WVALID, s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(11 downto 0) => m00_couplers_to_auto_pc_ARID(11 downto 0), s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0), s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0), s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => m00_couplers_to_auto_pc_ARREADY, s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0), s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => m00_couplers_to_auto_pc_AWID(11 downto 0), s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0), s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0), s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => m00_couplers_to_auto_pc_AWREADY, s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0), s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID, s_axi_bid(11 downto 0) => m00_couplers_to_auto_pc_BID(11 downto 0), s_axi_bready => m00_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => m00_couplers_to_auto_pc_BVALID, s_axi_rdata(31 downto 0) => m00_couplers_to_auto_pc_RDATA(31 downto 0), s_axi_rid(11 downto 0) => m00_couplers_to_auto_pc_RID(11 downto 0), s_axi_rlast => m00_couplers_to_auto_pc_RLAST, s_axi_rready => m00_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => m00_couplers_to_auto_pc_RVALID, s_axi_wdata(31 downto 0) => m00_couplers_to_auto_pc_WDATA(31 downto 0), s_axi_wlast => m00_couplers_to_auto_pc_WLAST, s_axi_wready => m00_couplers_to_auto_pc_WREADY, s_axi_wstrb(3 downto 0) => m00_couplers_to_auto_pc_WSTRB(3 downto 0), s_axi_wvalid => m00_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity m01_couplers_imp_1FBREZ4 is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end m01_couplers_imp_1FBREZ4; architecture STRUCTURE of m01_couplers_imp_1FBREZ4 is component design_1_auto_pc_2 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component design_1_auto_pc_2; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m01_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_m01_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m01_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_m01_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_m01_couplers_BREADY : STD_LOGIC; signal auto_pc_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m01_couplers_BVALID : STD_LOGIC; signal auto_pc_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m01_couplers_RREADY : STD_LOGIC; signal auto_pc_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m01_couplers_RVALID : STD_LOGIC; signal auto_pc_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m01_couplers_WREADY : STD_LOGIC; signal auto_pc_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m01_couplers_WVALID : STD_LOGIC; signal m01_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m01_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m01_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m01_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m01_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m01_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m01_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m01_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m01_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal m01_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m01_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m01_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal m01_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m01_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m01_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m01_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m01_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m01_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m01_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m01_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m01_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal m01_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m01_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m01_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal m01_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m01_couplers_to_auto_pc_BREADY : STD_LOGIC; signal m01_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m01_couplers_to_auto_pc_BVALID : STD_LOGIC; signal m01_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m01_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m01_couplers_to_auto_pc_RLAST : STD_LOGIC; signal m01_couplers_to_auto_pc_RREADY : STD_LOGIC; signal m01_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m01_couplers_to_auto_pc_RVALID : STD_LOGIC; signal m01_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m01_couplers_to_auto_pc_WLAST : STD_LOGIC; signal m01_couplers_to_auto_pc_WREADY : STD_LOGIC; signal m01_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m01_couplers_to_auto_pc_WVALID : STD_LOGIC; signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); begin M_AXI_araddr(31 downto 0) <= auto_pc_to_m01_couplers_ARADDR(31 downto 0); M_AXI_arvalid <= auto_pc_to_m01_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= auto_pc_to_m01_couplers_AWADDR(31 downto 0); M_AXI_awvalid <= auto_pc_to_m01_couplers_AWVALID; M_AXI_bready <= auto_pc_to_m01_couplers_BREADY; M_AXI_rready <= auto_pc_to_m01_couplers_RREADY; M_AXI_wdata(31 downto 0) <= auto_pc_to_m01_couplers_WDATA(31 downto 0); M_AXI_wstrb(3 downto 0) <= auto_pc_to_m01_couplers_WSTRB(3 downto 0); M_AXI_wvalid <= auto_pc_to_m01_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= m01_couplers_to_auto_pc_ARREADY; S_AXI_awready <= m01_couplers_to_auto_pc_AWREADY; S_AXI_bid(11 downto 0) <= m01_couplers_to_auto_pc_BID(11 downto 0); S_AXI_bresp(1 downto 0) <= m01_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= m01_couplers_to_auto_pc_BVALID; S_AXI_rdata(31 downto 0) <= m01_couplers_to_auto_pc_RDATA(31 downto 0); S_AXI_rid(11 downto 0) <= m01_couplers_to_auto_pc_RID(11 downto 0); S_AXI_rlast <= m01_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= m01_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= m01_couplers_to_auto_pc_RVALID; S_AXI_wready <= m01_couplers_to_auto_pc_WREADY; auto_pc_to_m01_couplers_ARREADY <= M_AXI_arready; auto_pc_to_m01_couplers_AWREADY <= M_AXI_awready; auto_pc_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_m01_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); auto_pc_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_m01_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_m01_couplers_WREADY <= M_AXI_wready; m01_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); m01_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); m01_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); m01_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); m01_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); m01_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0); m01_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); m01_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); m01_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0); m01_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); m01_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; m01_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); m01_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); m01_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); m01_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); m01_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); m01_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0); m01_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); m01_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); m01_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0); m01_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); m01_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; m01_couplers_to_auto_pc_BREADY <= S_AXI_bready; m01_couplers_to_auto_pc_RREADY <= S_AXI_rready; m01_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); m01_couplers_to_auto_pc_WLAST <= S_AXI_wlast; m01_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); m01_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component design_1_auto_pc_2 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1(0), m_axi_araddr(31 downto 0) => auto_pc_to_m01_couplers_ARADDR(31 downto 0), m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0), m_axi_arready => auto_pc_to_m01_couplers_ARREADY, m_axi_arvalid => auto_pc_to_m01_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_m01_couplers_AWADDR(31 downto 0), m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0), m_axi_awready => auto_pc_to_m01_couplers_AWREADY, m_axi_awvalid => auto_pc_to_m01_couplers_AWVALID, m_axi_bready => auto_pc_to_m01_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_m01_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_m01_couplers_BVALID, m_axi_rdata(31 downto 0) => auto_pc_to_m01_couplers_RDATA(31 downto 0), m_axi_rready => auto_pc_to_m01_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_m01_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_m01_couplers_RVALID, m_axi_wdata(31 downto 0) => auto_pc_to_m01_couplers_WDATA(31 downto 0), m_axi_wready => auto_pc_to_m01_couplers_WREADY, m_axi_wstrb(3 downto 0) => auto_pc_to_m01_couplers_WSTRB(3 downto 0), m_axi_wvalid => auto_pc_to_m01_couplers_WVALID, s_axi_araddr(31 downto 0) => m01_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => m01_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => m01_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(11 downto 0) => m01_couplers_to_auto_pc_ARID(11 downto 0), s_axi_arlen(7 downto 0) => m01_couplers_to_auto_pc_ARLEN(7 downto 0), s_axi_arlock(0) => m01_couplers_to_auto_pc_ARLOCK(0), s_axi_arprot(2 downto 0) => m01_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => m01_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => m01_couplers_to_auto_pc_ARREADY, s_axi_arregion(3 downto 0) => m01_couplers_to_auto_pc_ARREGION(3 downto 0), s_axi_arsize(2 downto 0) => m01_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => m01_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => m01_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => m01_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => m01_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => m01_couplers_to_auto_pc_AWID(11 downto 0), s_axi_awlen(7 downto 0) => m01_couplers_to_auto_pc_AWLEN(7 downto 0), s_axi_awlock(0) => m01_couplers_to_auto_pc_AWLOCK(0), s_axi_awprot(2 downto 0) => m01_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => m01_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => m01_couplers_to_auto_pc_AWREADY, s_axi_awregion(3 downto 0) => m01_couplers_to_auto_pc_AWREGION(3 downto 0), s_axi_awsize(2 downto 0) => m01_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => m01_couplers_to_auto_pc_AWVALID, s_axi_bid(11 downto 0) => m01_couplers_to_auto_pc_BID(11 downto 0), s_axi_bready => m01_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => m01_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => m01_couplers_to_auto_pc_BVALID, s_axi_rdata(31 downto 0) => m01_couplers_to_auto_pc_RDATA(31 downto 0), s_axi_rid(11 downto 0) => m01_couplers_to_auto_pc_RID(11 downto 0), s_axi_rlast => m01_couplers_to_auto_pc_RLAST, s_axi_rready => m01_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => m01_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => m01_couplers_to_auto_pc_RVALID, s_axi_wdata(31 downto 0) => m01_couplers_to_auto_pc_WDATA(31 downto 0), s_axi_wlast => m01_couplers_to_auto_pc_WLAST, s_axi_wready => m01_couplers_to_auto_pc_WREADY, s_axi_wstrb(3 downto 0) => m01_couplers_to_auto_pc_WSTRB(3 downto 0), s_axi_wvalid => m01_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity m02_couplers_imp_MVV5YQ is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end m02_couplers_imp_MVV5YQ; architecture STRUCTURE of m02_couplers_imp_MVV5YQ is component design_1_auto_pc_3 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component design_1_auto_pc_3; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m02_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_m02_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m02_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_m02_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_m02_couplers_BREADY : STD_LOGIC; signal auto_pc_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m02_couplers_BVALID : STD_LOGIC; signal auto_pc_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m02_couplers_RREADY : STD_LOGIC; signal auto_pc_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m02_couplers_RVALID : STD_LOGIC; signal auto_pc_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m02_couplers_WREADY : STD_LOGIC; signal auto_pc_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m02_couplers_WVALID : STD_LOGIC; signal m02_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m02_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m02_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m02_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m02_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m02_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m02_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m02_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m02_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal m02_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m02_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m02_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal m02_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m02_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m02_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m02_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m02_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m02_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m02_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m02_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m02_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal m02_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m02_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m02_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal m02_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m02_couplers_to_auto_pc_BREADY : STD_LOGIC; signal m02_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m02_couplers_to_auto_pc_BVALID : STD_LOGIC; signal m02_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m02_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m02_couplers_to_auto_pc_RLAST : STD_LOGIC; signal m02_couplers_to_auto_pc_RREADY : STD_LOGIC; signal m02_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m02_couplers_to_auto_pc_RVALID : STD_LOGIC; signal m02_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m02_couplers_to_auto_pc_WLAST : STD_LOGIC; signal m02_couplers_to_auto_pc_WREADY : STD_LOGIC; signal m02_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m02_couplers_to_auto_pc_WVALID : STD_LOGIC; signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); begin M_AXI_araddr(31 downto 0) <= auto_pc_to_m02_couplers_ARADDR(31 downto 0); M_AXI_arvalid <= auto_pc_to_m02_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= auto_pc_to_m02_couplers_AWADDR(31 downto 0); M_AXI_awvalid <= auto_pc_to_m02_couplers_AWVALID; M_AXI_bready <= auto_pc_to_m02_couplers_BREADY; M_AXI_rready <= auto_pc_to_m02_couplers_RREADY; M_AXI_wdata(31 downto 0) <= auto_pc_to_m02_couplers_WDATA(31 downto 0); M_AXI_wstrb(3 downto 0) <= auto_pc_to_m02_couplers_WSTRB(3 downto 0); M_AXI_wvalid <= auto_pc_to_m02_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= m02_couplers_to_auto_pc_ARREADY; S_AXI_awready <= m02_couplers_to_auto_pc_AWREADY; S_AXI_bid(11 downto 0) <= m02_couplers_to_auto_pc_BID(11 downto 0); S_AXI_bresp(1 downto 0) <= m02_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= m02_couplers_to_auto_pc_BVALID; S_AXI_rdata(31 downto 0) <= m02_couplers_to_auto_pc_RDATA(31 downto 0); S_AXI_rid(11 downto 0) <= m02_couplers_to_auto_pc_RID(11 downto 0); S_AXI_rlast <= m02_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= m02_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= m02_couplers_to_auto_pc_RVALID; S_AXI_wready <= m02_couplers_to_auto_pc_WREADY; auto_pc_to_m02_couplers_ARREADY <= M_AXI_arready; auto_pc_to_m02_couplers_AWREADY <= M_AXI_awready; auto_pc_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_m02_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); auto_pc_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_m02_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_m02_couplers_WREADY <= M_AXI_wready; m02_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); m02_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); m02_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); m02_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); m02_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); m02_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0); m02_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); m02_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); m02_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0); m02_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); m02_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; m02_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); m02_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); m02_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); m02_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); m02_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); m02_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0); m02_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); m02_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); m02_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0); m02_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); m02_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; m02_couplers_to_auto_pc_BREADY <= S_AXI_bready; m02_couplers_to_auto_pc_RREADY <= S_AXI_rready; m02_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); m02_couplers_to_auto_pc_WLAST <= S_AXI_wlast; m02_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); m02_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component design_1_auto_pc_3 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1(0), m_axi_araddr(31 downto 0) => auto_pc_to_m02_couplers_ARADDR(31 downto 0), m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0), m_axi_arready => auto_pc_to_m02_couplers_ARREADY, m_axi_arvalid => auto_pc_to_m02_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_m02_couplers_AWADDR(31 downto 0), m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0), m_axi_awready => auto_pc_to_m02_couplers_AWREADY, m_axi_awvalid => auto_pc_to_m02_couplers_AWVALID, m_axi_bready => auto_pc_to_m02_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_m02_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_m02_couplers_BVALID, m_axi_rdata(31 downto 0) => auto_pc_to_m02_couplers_RDATA(31 downto 0), m_axi_rready => auto_pc_to_m02_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_m02_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_m02_couplers_RVALID, m_axi_wdata(31 downto 0) => auto_pc_to_m02_couplers_WDATA(31 downto 0), m_axi_wready => auto_pc_to_m02_couplers_WREADY, m_axi_wstrb(3 downto 0) => auto_pc_to_m02_couplers_WSTRB(3 downto 0), m_axi_wvalid => auto_pc_to_m02_couplers_WVALID, s_axi_araddr(31 downto 0) => m02_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => m02_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => m02_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(11 downto 0) => m02_couplers_to_auto_pc_ARID(11 downto 0), s_axi_arlen(7 downto 0) => m02_couplers_to_auto_pc_ARLEN(7 downto 0), s_axi_arlock(0) => m02_couplers_to_auto_pc_ARLOCK(0), s_axi_arprot(2 downto 0) => m02_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => m02_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => m02_couplers_to_auto_pc_ARREADY, s_axi_arregion(3 downto 0) => m02_couplers_to_auto_pc_ARREGION(3 downto 0), s_axi_arsize(2 downto 0) => m02_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => m02_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => m02_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => m02_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => m02_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => m02_couplers_to_auto_pc_AWID(11 downto 0), s_axi_awlen(7 downto 0) => m02_couplers_to_auto_pc_AWLEN(7 downto 0), s_axi_awlock(0) => m02_couplers_to_auto_pc_AWLOCK(0), s_axi_awprot(2 downto 0) => m02_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => m02_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => m02_couplers_to_auto_pc_AWREADY, s_axi_awregion(3 downto 0) => m02_couplers_to_auto_pc_AWREGION(3 downto 0), s_axi_awsize(2 downto 0) => m02_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => m02_couplers_to_auto_pc_AWVALID, s_axi_bid(11 downto 0) => m02_couplers_to_auto_pc_BID(11 downto 0), s_axi_bready => m02_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => m02_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => m02_couplers_to_auto_pc_BVALID, s_axi_rdata(31 downto 0) => m02_couplers_to_auto_pc_RDATA(31 downto 0), s_axi_rid(11 downto 0) => m02_couplers_to_auto_pc_RID(11 downto 0), s_axi_rlast => m02_couplers_to_auto_pc_RLAST, s_axi_rready => m02_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => m02_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => m02_couplers_to_auto_pc_RVALID, s_axi_wdata(31 downto 0) => m02_couplers_to_auto_pc_WDATA(31 downto 0), s_axi_wlast => m02_couplers_to_auto_pc_WLAST, s_axi_wready => m02_couplers_to_auto_pc_WREADY, s_axi_wstrb(3 downto 0) => m02_couplers_to_auto_pc_WSTRB(3 downto 0), s_axi_wvalid => m02_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity m03_couplers_imp_1GHG26R is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_arlock : out STD_LOGIC; M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_awlock : out STD_LOGIC; M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awvalid : out STD_LOGIC; M_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_rlast : in STD_LOGIC; M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_wlast : out STD_LOGIC; M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arlock : in STD_LOGIC; S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awlock : in STD_LOGIC; S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end m03_couplers_imp_1GHG26R; architecture STRUCTURE of m03_couplers_imp_1GHG26R is signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m03_couplers_to_m03_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m03_couplers_to_m03_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m03_couplers_to_m03_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m03_couplers_to_m03_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m03_couplers_to_m03_couplers_ARLOCK : STD_LOGIC; signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC; signal m03_couplers_to_m03_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC; signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m03_couplers_to_m03_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m03_couplers_to_m03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m03_couplers_to_m03_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m03_couplers_to_m03_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m03_couplers_to_m03_couplers_AWLOCK : STD_LOGIC; signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC; signal m03_couplers_to_m03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC; signal m03_couplers_to_m03_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC; signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC; signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m03_couplers_to_m03_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m03_couplers_to_m03_couplers_RLAST : STD_LOGIC; signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC; signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC; signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m03_couplers_to_m03_couplers_WLAST : STD_LOGIC; signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC; signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC; begin M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= m03_couplers_to_m03_couplers_ARBURST(1 downto 0); M_AXI_arcache(3 downto 0) <= m03_couplers_to_m03_couplers_ARCACHE(3 downto 0); M_AXI_arid(11 downto 0) <= m03_couplers_to_m03_couplers_ARID(11 downto 0); M_AXI_arlen(7 downto 0) <= m03_couplers_to_m03_couplers_ARLEN(7 downto 0); M_AXI_arlock <= m03_couplers_to_m03_couplers_ARLOCK; M_AXI_arprot(2 downto 0) <= m03_couplers_to_m03_couplers_ARPROT(2 downto 0); M_AXI_arsize(2 downto 0) <= m03_couplers_to_m03_couplers_ARSIZE(2 downto 0); M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0); M_AXI_awburst(1 downto 0) <= m03_couplers_to_m03_couplers_AWBURST(1 downto 0); M_AXI_awcache(3 downto 0) <= m03_couplers_to_m03_couplers_AWCACHE(3 downto 0); M_AXI_awid(11 downto 0) <= m03_couplers_to_m03_couplers_AWID(11 downto 0); M_AXI_awlen(7 downto 0) <= m03_couplers_to_m03_couplers_AWLEN(7 downto 0); M_AXI_awlock <= m03_couplers_to_m03_couplers_AWLOCK; M_AXI_awprot(2 downto 0) <= m03_couplers_to_m03_couplers_AWPROT(2 downto 0); M_AXI_awsize(2 downto 0) <= m03_couplers_to_m03_couplers_AWSIZE(2 downto 0); M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID; M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY; M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY; M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0); M_AXI_wlast <= m03_couplers_to_m03_couplers_WLAST; M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0); M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID; S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY; S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY; S_AXI_bid(11 downto 0) <= m03_couplers_to_m03_couplers_BID(11 downto 0); S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0); S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID; S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0); S_AXI_rid(11 downto 0) <= m03_couplers_to_m03_couplers_RID(11 downto 0); S_AXI_rlast <= m03_couplers_to_m03_couplers_RLAST; S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0); S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID; S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY; m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); m03_couplers_to_m03_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); m03_couplers_to_m03_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); m03_couplers_to_m03_couplers_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); m03_couplers_to_m03_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); m03_couplers_to_m03_couplers_ARLOCK <= S_AXI_arlock; m03_couplers_to_m03_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready; m03_couplers_to_m03_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid; m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); m03_couplers_to_m03_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); m03_couplers_to_m03_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); m03_couplers_to_m03_couplers_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); m03_couplers_to_m03_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); m03_couplers_to_m03_couplers_AWLOCK <= S_AXI_awlock; m03_couplers_to_m03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready; m03_couplers_to_m03_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid; m03_couplers_to_m03_couplers_BID(11 downto 0) <= M_AXI_bid(11 downto 0); m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready; m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid; m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); m03_couplers_to_m03_couplers_RID(11 downto 0) <= M_AXI_rid(11 downto 0); m03_couplers_to_m03_couplers_RLAST <= M_AXI_rlast; m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready; m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid; m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); m03_couplers_to_m03_couplers_WLAST <= S_AXI_wlast; m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready; m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid; end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity m04_couplers_imp_PJ7QT3 is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end m04_couplers_imp_PJ7QT3; architecture STRUCTURE of m04_couplers_imp_PJ7QT3 is component design_1_auto_pc_4 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component design_1_auto_pc_4; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m04_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_m04_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m04_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_m04_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_m04_couplers_BREADY : STD_LOGIC; signal auto_pc_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m04_couplers_BVALID : STD_LOGIC; signal auto_pc_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m04_couplers_RREADY : STD_LOGIC; signal auto_pc_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m04_couplers_RVALID : STD_LOGIC; signal auto_pc_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m04_couplers_WREADY : STD_LOGIC; signal auto_pc_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m04_couplers_WVALID : STD_LOGIC; signal m04_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m04_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m04_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m04_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m04_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m04_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m04_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m04_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m04_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal m04_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m04_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m04_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal m04_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m04_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m04_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m04_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m04_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m04_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m04_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m04_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m04_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal m04_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m04_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m04_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal m04_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m04_couplers_to_auto_pc_BREADY : STD_LOGIC; signal m04_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m04_couplers_to_auto_pc_BVALID : STD_LOGIC; signal m04_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m04_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m04_couplers_to_auto_pc_RLAST : STD_LOGIC; signal m04_couplers_to_auto_pc_RREADY : STD_LOGIC; signal m04_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m04_couplers_to_auto_pc_RVALID : STD_LOGIC; signal m04_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m04_couplers_to_auto_pc_WLAST : STD_LOGIC; signal m04_couplers_to_auto_pc_WREADY : STD_LOGIC; signal m04_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m04_couplers_to_auto_pc_WVALID : STD_LOGIC; signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); begin M_AXI_araddr(31 downto 0) <= auto_pc_to_m04_couplers_ARADDR(31 downto 0); M_AXI_arvalid <= auto_pc_to_m04_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= auto_pc_to_m04_couplers_AWADDR(31 downto 0); M_AXI_awvalid <= auto_pc_to_m04_couplers_AWVALID; M_AXI_bready <= auto_pc_to_m04_couplers_BREADY; M_AXI_rready <= auto_pc_to_m04_couplers_RREADY; M_AXI_wdata(31 downto 0) <= auto_pc_to_m04_couplers_WDATA(31 downto 0); M_AXI_wstrb(3 downto 0) <= auto_pc_to_m04_couplers_WSTRB(3 downto 0); M_AXI_wvalid <= auto_pc_to_m04_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= m04_couplers_to_auto_pc_ARREADY; S_AXI_awready <= m04_couplers_to_auto_pc_AWREADY; S_AXI_bid(11 downto 0) <= m04_couplers_to_auto_pc_BID(11 downto 0); S_AXI_bresp(1 downto 0) <= m04_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= m04_couplers_to_auto_pc_BVALID; S_AXI_rdata(31 downto 0) <= m04_couplers_to_auto_pc_RDATA(31 downto 0); S_AXI_rid(11 downto 0) <= m04_couplers_to_auto_pc_RID(11 downto 0); S_AXI_rlast <= m04_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= m04_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= m04_couplers_to_auto_pc_RVALID; S_AXI_wready <= m04_couplers_to_auto_pc_WREADY; auto_pc_to_m04_couplers_ARREADY <= M_AXI_arready; auto_pc_to_m04_couplers_AWREADY <= M_AXI_awready; auto_pc_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_m04_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); auto_pc_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_m04_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_m04_couplers_WREADY <= M_AXI_wready; m04_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); m04_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); m04_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); m04_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); m04_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); m04_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0); m04_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); m04_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); m04_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0); m04_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); m04_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; m04_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); m04_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); m04_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); m04_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); m04_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); m04_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0); m04_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); m04_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); m04_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0); m04_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); m04_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; m04_couplers_to_auto_pc_BREADY <= S_AXI_bready; m04_couplers_to_auto_pc_RREADY <= S_AXI_rready; m04_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); m04_couplers_to_auto_pc_WLAST <= S_AXI_wlast; m04_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); m04_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component design_1_auto_pc_4 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1(0), m_axi_araddr(31 downto 0) => auto_pc_to_m04_couplers_ARADDR(31 downto 0), m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0), m_axi_arready => auto_pc_to_m04_couplers_ARREADY, m_axi_arvalid => auto_pc_to_m04_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_m04_couplers_AWADDR(31 downto 0), m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0), m_axi_awready => auto_pc_to_m04_couplers_AWREADY, m_axi_awvalid => auto_pc_to_m04_couplers_AWVALID, m_axi_bready => auto_pc_to_m04_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_m04_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_m04_couplers_BVALID, m_axi_rdata(31 downto 0) => auto_pc_to_m04_couplers_RDATA(31 downto 0), m_axi_rready => auto_pc_to_m04_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_m04_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_m04_couplers_RVALID, m_axi_wdata(31 downto 0) => auto_pc_to_m04_couplers_WDATA(31 downto 0), m_axi_wready => auto_pc_to_m04_couplers_WREADY, m_axi_wstrb(3 downto 0) => auto_pc_to_m04_couplers_WSTRB(3 downto 0), m_axi_wvalid => auto_pc_to_m04_couplers_WVALID, s_axi_araddr(31 downto 0) => m04_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => m04_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => m04_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(11 downto 0) => m04_couplers_to_auto_pc_ARID(11 downto 0), s_axi_arlen(7 downto 0) => m04_couplers_to_auto_pc_ARLEN(7 downto 0), s_axi_arlock(0) => m04_couplers_to_auto_pc_ARLOCK(0), s_axi_arprot(2 downto 0) => m04_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => m04_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => m04_couplers_to_auto_pc_ARREADY, s_axi_arregion(3 downto 0) => m04_couplers_to_auto_pc_ARREGION(3 downto 0), s_axi_arsize(2 downto 0) => m04_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => m04_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => m04_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => m04_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => m04_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => m04_couplers_to_auto_pc_AWID(11 downto 0), s_axi_awlen(7 downto 0) => m04_couplers_to_auto_pc_AWLEN(7 downto 0), s_axi_awlock(0) => m04_couplers_to_auto_pc_AWLOCK(0), s_axi_awprot(2 downto 0) => m04_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => m04_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => m04_couplers_to_auto_pc_AWREADY, s_axi_awregion(3 downto 0) => m04_couplers_to_auto_pc_AWREGION(3 downto 0), s_axi_awsize(2 downto 0) => m04_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => m04_couplers_to_auto_pc_AWVALID, s_axi_bid(11 downto 0) => m04_couplers_to_auto_pc_BID(11 downto 0), s_axi_bready => m04_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => m04_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => m04_couplers_to_auto_pc_BVALID, s_axi_rdata(31 downto 0) => m04_couplers_to_auto_pc_RDATA(31 downto 0), s_axi_rid(11 downto 0) => m04_couplers_to_auto_pc_RID(11 downto 0), s_axi_rlast => m04_couplers_to_auto_pc_RLAST, s_axi_rready => m04_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => m04_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => m04_couplers_to_auto_pc_RVALID, s_axi_wdata(31 downto 0) => m04_couplers_to_auto_pc_WDATA(31 downto 0), s_axi_wlast => m04_couplers_to_auto_pc_WLAST, s_axi_wready => m04_couplers_to_auto_pc_WREADY, s_axi_wstrb(3 downto 0) => m04_couplers_to_auto_pc_WSTRB(3 downto 0), s_axi_wvalid => m04_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity s00_couplers_imp_1CFO1MB is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awvalid : out STD_LOGIC; M_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_rlast : in STD_LOGIC; M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_wlast : out STD_LOGIC; M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end s00_couplers_imp_1CFO1MB; architecture STRUCTURE of s00_couplers_imp_1CFO1MB is component design_1_auto_pc_5 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component design_1_auto_pc_5; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal auto_pc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_pc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal auto_pc_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_pc_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal auto_pc_to_s00_couplers_RLAST : STD_LOGIC; signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_WLAST : STD_LOGIC; signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC; signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC; signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC; signal NLW_auto_pc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_auto_pc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); begin M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= auto_pc_to_s00_couplers_ARBURST(1 downto 0); M_AXI_arcache(3 downto 0) <= auto_pc_to_s00_couplers_ARCACHE(3 downto 0); M_AXI_arid(11 downto 0) <= auto_pc_to_s00_couplers_ARID(11 downto 0); M_AXI_arlen(7 downto 0) <= auto_pc_to_s00_couplers_ARLEN(7 downto 0); M_AXI_arlock(0) <= auto_pc_to_s00_couplers_ARLOCK(0); M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0); M_AXI_arqos(3 downto 0) <= auto_pc_to_s00_couplers_ARQOS(3 downto 0); M_AXI_arsize(2 downto 0) <= auto_pc_to_s00_couplers_ARSIZE(2 downto 0); M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0); M_AXI_awburst(1 downto 0) <= auto_pc_to_s00_couplers_AWBURST(1 downto 0); M_AXI_awcache(3 downto 0) <= auto_pc_to_s00_couplers_AWCACHE(3 downto 0); M_AXI_awid(11 downto 0) <= auto_pc_to_s00_couplers_AWID(11 downto 0); M_AXI_awlen(7 downto 0) <= auto_pc_to_s00_couplers_AWLEN(7 downto 0); M_AXI_awlock(0) <= auto_pc_to_s00_couplers_AWLOCK(0); M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0); M_AXI_awqos(3 downto 0) <= auto_pc_to_s00_couplers_AWQOS(3 downto 0); M_AXI_awsize(2 downto 0) <= auto_pc_to_s00_couplers_AWSIZE(2 downto 0); M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID; M_AXI_bready <= auto_pc_to_s00_couplers_BREADY; M_AXI_rready <= auto_pc_to_s00_couplers_RREADY; M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0); M_AXI_wlast <= auto_pc_to_s00_couplers_WLAST; M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0); M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY; S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY; S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0); S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID; S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0); S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0); S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID; S_AXI_wready <= s00_couplers_to_auto_pc_WREADY; auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready; auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready; auto_pc_to_s00_couplers_BID(11 downto 0) <= M_AXI_bid(11 downto 0); auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); auto_pc_to_s00_couplers_RID(11 downto 0) <= M_AXI_rid(11 downto 0); auto_pc_to_s00_couplers_RLAST <= M_AXI_rlast; auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_s00_couplers_WREADY <= M_AXI_wready; s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0); s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0); s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; s00_couplers_to_auto_pc_BREADY <= S_AXI_bready; s00_couplers_to_auto_pc_RREADY <= S_AXI_rready; s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0); s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component design_1_auto_pc_5 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1(0), m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0), m_axi_arburst(1 downto 0) => auto_pc_to_s00_couplers_ARBURST(1 downto 0), m_axi_arcache(3 downto 0) => auto_pc_to_s00_couplers_ARCACHE(3 downto 0), m_axi_arid(11 downto 0) => auto_pc_to_s00_couplers_ARID(11 downto 0), m_axi_arlen(7 downto 0) => auto_pc_to_s00_couplers_ARLEN(7 downto 0), m_axi_arlock(0) => auto_pc_to_s00_couplers_ARLOCK(0), m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0), m_axi_arqos(3 downto 0) => auto_pc_to_s00_couplers_ARQOS(3 downto 0), m_axi_arready => auto_pc_to_s00_couplers_ARREADY, m_axi_arregion(3 downto 0) => NLW_auto_pc_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => auto_pc_to_s00_couplers_ARSIZE(2 downto 0), m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0), m_axi_awburst(1 downto 0) => auto_pc_to_s00_couplers_AWBURST(1 downto 0), m_axi_awcache(3 downto 0) => auto_pc_to_s00_couplers_AWCACHE(3 downto 0), m_axi_awid(11 downto 0) => auto_pc_to_s00_couplers_AWID(11 downto 0), m_axi_awlen(7 downto 0) => auto_pc_to_s00_couplers_AWLEN(7 downto 0), m_axi_awlock(0) => auto_pc_to_s00_couplers_AWLOCK(0), m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0), m_axi_awqos(3 downto 0) => auto_pc_to_s00_couplers_AWQOS(3 downto 0), m_axi_awready => auto_pc_to_s00_couplers_AWREADY, m_axi_awregion(3 downto 0) => NLW_auto_pc_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => auto_pc_to_s00_couplers_AWSIZE(2 downto 0), m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID, m_axi_bid(11 downto 0) => auto_pc_to_s00_couplers_BID(11 downto 0), m_axi_bready => auto_pc_to_s00_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_s00_couplers_BVALID, m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0), m_axi_rid(11 downto 0) => auto_pc_to_s00_couplers_RID(11 downto 0), m_axi_rlast => auto_pc_to_s00_couplers_RLAST, m_axi_rready => auto_pc_to_s00_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_s00_couplers_RVALID, m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0), m_axi_wlast => auto_pc_to_s00_couplers_WLAST, m_axi_wready => auto_pc_to_s00_couplers_WREADY, m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0), m_axi_wvalid => auto_pc_to_s00_couplers_WVALID, s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0), s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0), s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0), s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => s00_couplers_to_auto_pc_ARREADY, s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0), s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0), s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0), s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => s00_couplers_to_auto_pc_AWREADY, s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID, s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0), s_axi_bready => s00_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => s00_couplers_to_auto_pc_BVALID, s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0), s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0), s_axi_rlast => s00_couplers_to_auto_pc_RLAST, s_axi_rready => s00_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => s00_couplers_to_auto_pc_RVALID, s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0), s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0), s_axi_wlast => s00_couplers_to_auto_pc_WLAST, s_axi_wready => s00_couplers_to_auto_pc_WREADY, s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0), s_axi_wvalid => s00_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity s00_couplers_imp_7HNO1D is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arvalid : out STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_rlast : in STD_LOGIC; M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC ); end s00_couplers_imp_7HNO1D; architecture STRUCTURE of s00_couplers_imp_7HNO1D is component design_1_auto_us_0 is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component design_1_auto_us_0; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC; signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC; signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_us_to_s00_couplers_RLAST : STD_LOGIC; signal auto_us_to_s00_couplers_RREADY : STD_LOGIC; signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s00_couplers_RVALID : STD_LOGIC; signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC; signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC; signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_us_RLAST : STD_LOGIC; signal s00_couplers_to_auto_us_RREADY : STD_LOGIC; signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_us_RVALID : STD_LOGIC; signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); begin M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0); M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0); M_AXI_arlen(7 downto 0) <= auto_us_to_s00_couplers_ARLEN(7 downto 0); M_AXI_arlock(0) <= auto_us_to_s00_couplers_ARLOCK(0); M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0); M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0); M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0); M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID; M_AXI_rready <= auto_us_to_s00_couplers_RREADY; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= s00_couplers_to_auto_us_ARREADY; S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0); S_AXI_rlast <= s00_couplers_to_auto_us_RLAST; S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0); S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID; auto_us_to_s00_couplers_ARREADY <= M_AXI_arready; auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); auto_us_to_s00_couplers_RLAST <= M_AXI_rlast; auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid; s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); s00_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid; s00_couplers_to_auto_us_RREADY <= S_AXI_rready; auto_us: component design_1_auto_us_0 port map ( m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0), m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0), m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0), m_axi_arlen(7 downto 0) => auto_us_to_s00_couplers_ARLEN(7 downto 0), m_axi_arlock(0) => auto_us_to_s00_couplers_ARLOCK(0), m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0), m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0), m_axi_arready => auto_us_to_s00_couplers_ARREADY, m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0), m_axi_arvalid => auto_us_to_s00_couplers_ARVALID, m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0), m_axi_rlast => auto_us_to_s00_couplers_RLAST, m_axi_rready => auto_us_to_s00_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_us_to_s00_couplers_RVALID, s_axi_aclk => S_ACLK_1, s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0), s_axi_aresetn => S_ARESETN_1(0), s_axi_arlen(7 downto 0) => s00_couplers_to_auto_us_ARLEN(7 downto 0), s_axi_arlock(0) => '0', s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => B"0000", s_axi_arready => s00_couplers_to_auto_us_ARREADY, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0), s_axi_arvalid => s00_couplers_to_auto_us_ARVALID, s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0), s_axi_rlast => s00_couplers_to_auto_us_RLAST, s_axi_rready => s00_couplers_to_auto_us_RREADY, s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0), s_axi_rvalid => s00_couplers_to_auto_us_RVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity s01_couplers_imp_1W60HW0 is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_wlast : out STD_LOGIC; M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end s01_couplers_imp_1W60HW0; architecture STRUCTURE of s01_couplers_imp_1W60HW0 is component design_1_auto_us_1 is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC ); end component design_1_auto_us_1; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_us_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_us_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s01_couplers_AWREADY : STD_LOGIC; signal auto_us_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s01_couplers_AWVALID : STD_LOGIC; signal auto_us_to_s01_couplers_BREADY : STD_LOGIC; signal auto_us_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s01_couplers_BVALID : STD_LOGIC; signal auto_us_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_us_to_s01_couplers_WLAST : STD_LOGIC; signal auto_us_to_s01_couplers_WREADY : STD_LOGIC; signal auto_us_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_us_to_s01_couplers_WVALID : STD_LOGIC; signal s01_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s01_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s01_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s01_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s01_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s01_couplers_to_auto_us_AWREADY : STD_LOGIC; signal s01_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s01_couplers_to_auto_us_AWVALID : STD_LOGIC; signal s01_couplers_to_auto_us_BREADY : STD_LOGIC; signal s01_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s01_couplers_to_auto_us_BVALID : STD_LOGIC; signal s01_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s01_couplers_to_auto_us_WLAST : STD_LOGIC; signal s01_couplers_to_auto_us_WREADY : STD_LOGIC; signal s01_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s01_couplers_to_auto_us_WVALID : STD_LOGIC; signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); begin M_AXI_awaddr(31 downto 0) <= auto_us_to_s01_couplers_AWADDR(31 downto 0); M_AXI_awburst(1 downto 0) <= auto_us_to_s01_couplers_AWBURST(1 downto 0); M_AXI_awcache(3 downto 0) <= auto_us_to_s01_couplers_AWCACHE(3 downto 0); M_AXI_awlen(7 downto 0) <= auto_us_to_s01_couplers_AWLEN(7 downto 0); M_AXI_awlock(0) <= auto_us_to_s01_couplers_AWLOCK(0); M_AXI_awprot(2 downto 0) <= auto_us_to_s01_couplers_AWPROT(2 downto 0); M_AXI_awqos(3 downto 0) <= auto_us_to_s01_couplers_AWQOS(3 downto 0); M_AXI_awsize(2 downto 0) <= auto_us_to_s01_couplers_AWSIZE(2 downto 0); M_AXI_awvalid <= auto_us_to_s01_couplers_AWVALID; M_AXI_bready <= auto_us_to_s01_couplers_BREADY; M_AXI_wdata(63 downto 0) <= auto_us_to_s01_couplers_WDATA(63 downto 0); M_AXI_wlast <= auto_us_to_s01_couplers_WLAST; M_AXI_wstrb(7 downto 0) <= auto_us_to_s01_couplers_WSTRB(7 downto 0); M_AXI_wvalid <= auto_us_to_s01_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_awready <= s01_couplers_to_auto_us_AWREADY; S_AXI_bresp(1 downto 0) <= s01_couplers_to_auto_us_BRESP(1 downto 0); S_AXI_bvalid <= s01_couplers_to_auto_us_BVALID; S_AXI_wready <= s01_couplers_to_auto_us_WREADY; auto_us_to_s01_couplers_AWREADY <= M_AXI_awready; auto_us_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_us_to_s01_couplers_BVALID <= M_AXI_bvalid; auto_us_to_s01_couplers_WREADY <= M_AXI_wready; s01_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); s01_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); s01_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); s01_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); s01_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); s01_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); s01_couplers_to_auto_us_AWVALID <= S_AXI_awvalid; s01_couplers_to_auto_us_BREADY <= S_AXI_bready; s01_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); s01_couplers_to_auto_us_WLAST <= S_AXI_wlast; s01_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); s01_couplers_to_auto_us_WVALID <= S_AXI_wvalid; auto_us: component design_1_auto_us_1 port map ( m_axi_awaddr(31 downto 0) => auto_us_to_s01_couplers_AWADDR(31 downto 0), m_axi_awburst(1 downto 0) => auto_us_to_s01_couplers_AWBURST(1 downto 0), m_axi_awcache(3 downto 0) => auto_us_to_s01_couplers_AWCACHE(3 downto 0), m_axi_awlen(7 downto 0) => auto_us_to_s01_couplers_AWLEN(7 downto 0), m_axi_awlock(0) => auto_us_to_s01_couplers_AWLOCK(0), m_axi_awprot(2 downto 0) => auto_us_to_s01_couplers_AWPROT(2 downto 0), m_axi_awqos(3 downto 0) => auto_us_to_s01_couplers_AWQOS(3 downto 0), m_axi_awready => auto_us_to_s01_couplers_AWREADY, m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => auto_us_to_s01_couplers_AWSIZE(2 downto 0), m_axi_awvalid => auto_us_to_s01_couplers_AWVALID, m_axi_bready => auto_us_to_s01_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_us_to_s01_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_us_to_s01_couplers_BVALID, m_axi_wdata(63 downto 0) => auto_us_to_s01_couplers_WDATA(63 downto 0), m_axi_wlast => auto_us_to_s01_couplers_WLAST, m_axi_wready => auto_us_to_s01_couplers_WREADY, m_axi_wstrb(7 downto 0) => auto_us_to_s01_couplers_WSTRB(7 downto 0), m_axi_wvalid => auto_us_to_s01_couplers_WVALID, s_axi_aclk => S_ACLK_1, s_axi_aresetn => S_ARESETN_1(0), s_axi_awaddr(31 downto 0) => s01_couplers_to_auto_us_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => s01_couplers_to_auto_us_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => s01_couplers_to_auto_us_AWCACHE(3 downto 0), s_axi_awlen(7 downto 0) => s01_couplers_to_auto_us_AWLEN(7 downto 0), s_axi_awlock(0) => '0', s_axi_awprot(2 downto 0) => s01_couplers_to_auto_us_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => B"0000", s_axi_awready => s01_couplers_to_auto_us_AWREADY, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => s01_couplers_to_auto_us_AWSIZE(2 downto 0), s_axi_awvalid => s01_couplers_to_auto_us_AWVALID, s_axi_bready => s01_couplers_to_auto_us_BREADY, s_axi_bresp(1 downto 0) => s01_couplers_to_auto_us_BRESP(1 downto 0), s_axi_bvalid => s01_couplers_to_auto_us_BVALID, s_axi_wdata(31 downto 0) => s01_couplers_to_auto_us_WDATA(31 downto 0), s_axi_wlast => s01_couplers_to_auto_us_WLAST, s_axi_wready => s01_couplers_to_auto_us_WREADY, s_axi_wstrb(3 downto 0) => s01_couplers_to_auto_us_WSTRB(3 downto 0), s_axi_wvalid => s01_couplers_to_auto_us_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_axi_mem_intercon_0 is port ( ACLK : in STD_LOGIC; ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_ACLK : in STD_LOGIC; M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_arready : in STD_LOGIC; M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_arvalid : out STD_LOGIC; M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_awready : in STD_LOGIC; M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_awvalid : out STD_LOGIC; M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 ); M00_AXI_bready : out STD_LOGIC; M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_bvalid : in STD_LOGIC; M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 ); M00_AXI_rlast : in STD_LOGIC; M00_AXI_rready : out STD_LOGIC; M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_rvalid : in STD_LOGIC; M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); M00_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); M00_AXI_wlast : out STD_LOGIC; M00_AXI_wready : in STD_LOGIC; M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); M00_AXI_wvalid : out STD_LOGIC; S00_ACLK : in STD_LOGIC; S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arready : out STD_LOGIC; S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arvalid : in STD_LOGIC; S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_rlast : out STD_LOGIC; S00_AXI_rready : in STD_LOGIC; S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_rvalid : out STD_LOGIC; S01_ACLK : in STD_LOGIC; S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S01_AXI_awready : out STD_LOGIC; S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S01_AXI_awvalid : in STD_LOGIC; S01_AXI_bready : in STD_LOGIC; S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S01_AXI_bvalid : out STD_LOGIC; S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S01_AXI_wlast : in STD_LOGIC; S01_AXI_wready : out STD_LOGIC; S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S01_AXI_wvalid : in STD_LOGIC ); end design_1_axi_mem_intercon_0; architecture STRUCTURE of design_1_axi_mem_intercon_0 is component design_1_xbar_1 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end component design_1_xbar_1; signal M00_ACLK_1 : STD_LOGIC; signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal S00_ACLK_1 : STD_LOGIC; signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal S01_ACLK_1 : STD_LOGIC; signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_mem_intercon_ACLK_net : STD_LOGIC; signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 ); signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 ); signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC; signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_xbar_ARVALID : STD_LOGIC; signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_RREADY : STD_LOGIC; signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s01_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s01_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 ); signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s01_couplers_to_xbar_AWVALID : STD_LOGIC; signal s01_couplers_to_xbar_BREADY : STD_LOGIC; signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 ); signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 ); signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal s01_couplers_to_xbar_WLAST : STD_LOGIC; signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 ); signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s01_couplers_to_xbar_WVALID : STD_LOGIC; signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_ARREADY : STD_LOGIC; signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_AWREADY : STD_LOGIC; signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_BVALID : STD_LOGIC; signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_RLAST : STD_LOGIC; signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_RVALID : STD_LOGIC; signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_WREADY : STD_LOGIC; signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 64 ); signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); begin M00_ACLK_1 <= M00_ACLK; M00_ARESETN_1(0) <= M00_ARESETN(0); M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0); M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0); M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0); M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0); M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0); M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0); M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0); M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0); M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0); M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID; M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0); M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0); M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0); M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0); M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0); M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0); M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0); M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0); M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0); M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID; M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY; M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY; M00_AXI_wdata(63 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0); M00_AXI_wid(0) <= m00_couplers_to_axi_mem_intercon_WID(0); M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST; M00_AXI_wstrb(7 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0); M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID; S00_ACLK_1 <= S00_ACLK; S00_ARESETN_1(0) <= S00_ARESETN(0); S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY; S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0); S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST; S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0); S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID; S01_ACLK_1 <= S01_ACLK; S01_ARESETN_1(0) <= S01_ARESETN(0); S01_AXI_awready <= axi_mem_intercon_to_s01_couplers_AWREADY; S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0); S01_AXI_bvalid <= axi_mem_intercon_to_s01_couplers_BVALID; S01_AXI_wready <= axi_mem_intercon_to_s01_couplers_WREADY; axi_mem_intercon_ACLK_net <= ACLK; axi_mem_intercon_ARESETN_net(0) <= ARESETN(0); axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0); axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid; axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready; axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0); axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0); axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0); axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0); axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0); axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0); axi_mem_intercon_to_s01_couplers_AWVALID <= S01_AXI_awvalid; axi_mem_intercon_to_s01_couplers_BREADY <= S01_AXI_bready; axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0); axi_mem_intercon_to_s01_couplers_WLAST <= S01_AXI_wlast; axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0); axi_mem_intercon_to_s01_couplers_WVALID <= S01_AXI_wvalid; m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready; m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready; m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0); m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid; m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0); m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0); m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast; m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid; m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready; m00_couplers: entity work.m00_couplers_imp_1R706YB port map ( M_ACLK => M00_ACLK_1, M_ARESETN(0) => M00_ARESETN_1(0), M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0), M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0), M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0), M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0), M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0), M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0), M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0), M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0), M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY, M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0), M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID, M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0), M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0), M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0), M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0), M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0), M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0), M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0), M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0), M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY, M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0), M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID, M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0), M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY, M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0), M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID, M_AXI_rdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0), M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0), M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST, M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY, M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0), M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID, M_AXI_wdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0), M_AXI_wid(0) => m00_couplers_to_axi_mem_intercon_WID(0), M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST, M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY, M_AXI_wstrb(7 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0), M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID, S_ACLK => axi_mem_intercon_ACLK_net, S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0), S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0), S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0), S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0), S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0), S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0), S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0), S_AXI_arready => xbar_to_m00_couplers_ARREADY, S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0), S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0), S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0), S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0), S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0), S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0), S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0), S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0), S_AXI_awready => xbar_to_m00_couplers_AWREADY, S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0), S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0), S_AXI_bid(0) => xbar_to_m00_couplers_BID(0), S_AXI_bready => xbar_to_m00_couplers_BREADY(0), S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), S_AXI_bvalid => xbar_to_m00_couplers_BVALID, S_AXI_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0), S_AXI_rid(0) => xbar_to_m00_couplers_RID(0), S_AXI_rlast => xbar_to_m00_couplers_RLAST, S_AXI_rready => xbar_to_m00_couplers_RREADY(0), S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), S_AXI_rvalid => xbar_to_m00_couplers_RVALID, S_AXI_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0), S_AXI_wlast => xbar_to_m00_couplers_WLAST(0), S_AXI_wready => xbar_to_m00_couplers_WREADY, S_AXI_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0), S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0) ); s00_couplers: entity work.s00_couplers_imp_7HNO1D port map ( M_ACLK => axi_mem_intercon_ACLK_net, M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0), M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0), M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0), M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0), M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0), M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0), M_AXI_arready => s00_couplers_to_xbar_ARREADY(0), M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0), M_AXI_arvalid => s00_couplers_to_xbar_ARVALID, M_AXI_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0), M_AXI_rlast => s00_couplers_to_xbar_RLAST(0), M_AXI_rready => s00_couplers_to_xbar_RREADY, M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0), S_ACLK => S00_ACLK_1, S_ARESETN(0) => S00_ARESETN_1(0), S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0), S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0), S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0), S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY, S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID, S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0), S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST, S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY, S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0), S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID ); s01_couplers: entity work.s01_couplers_imp_1W60HW0 port map ( M_ACLK => axi_mem_intercon_ACLK_net, M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0), M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0), M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0), M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0), M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0), M_AXI_awlock(0) => s01_couplers_to_xbar_AWLOCK(0), M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0), M_AXI_awqos(3 downto 0) => s01_couplers_to_xbar_AWQOS(3 downto 0), M_AXI_awready => s01_couplers_to_xbar_AWREADY(1), M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0), M_AXI_awvalid => s01_couplers_to_xbar_AWVALID, M_AXI_bready => s01_couplers_to_xbar_BREADY, M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2), M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1), M_AXI_wdata(63 downto 0) => s01_couplers_to_xbar_WDATA(63 downto 0), M_AXI_wlast => s01_couplers_to_xbar_WLAST, M_AXI_wready => s01_couplers_to_xbar_WREADY(1), M_AXI_wstrb(7 downto 0) => s01_couplers_to_xbar_WSTRB(7 downto 0), M_AXI_wvalid => s01_couplers_to_xbar_WVALID, S_ACLK => S01_ACLK_1, S_ARESETN(0) => S01_ARESETN_1(0), S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0), S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0), S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0), S_AXI_awready => axi_mem_intercon_to_s01_couplers_AWREADY, S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => axi_mem_intercon_to_s01_couplers_AWVALID, S_AXI_bready => axi_mem_intercon_to_s01_couplers_BREADY, S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0), S_AXI_bvalid => axi_mem_intercon_to_s01_couplers_BVALID, S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0), S_AXI_wlast => axi_mem_intercon_to_s01_couplers_WLAST, S_AXI_wready => axi_mem_intercon_to_s01_couplers_WREADY, S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0), S_AXI_wvalid => axi_mem_intercon_to_s01_couplers_WVALID ); xbar: component design_1_xbar_1 port map ( aclk => axi_mem_intercon_ACLK_net, aresetn => axi_mem_intercon_ARESETN_net(0), m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0), m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0), m_axi_arid(0) => xbar_to_m00_couplers_ARID(0), m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0), m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0), m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0), m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0), m_axi_arready(0) => xbar_to_m00_couplers_ARREADY, m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0), m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0), m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0), m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0), m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0), m_axi_awid(0) => xbar_to_m00_couplers_AWID(0), m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0), m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0), m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0), m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0), m_axi_awready(0) => xbar_to_m00_couplers_AWREADY, m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0), m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0), m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0), m_axi_bid(0) => xbar_to_m00_couplers_BID(0), m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0), m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID, m_axi_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0), m_axi_rid(0) => xbar_to_m00_couplers_RID(0), m_axi_rlast(0) => xbar_to_m00_couplers_RLAST, m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0), m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID, m_axi_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0), m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0), m_axi_wready(0) => xbar_to_m00_couplers_WREADY, m_axi_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0), m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0), s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000", s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), s_axi_arburst(3 downto 2) => B"00", s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0), s_axi_arcache(7 downto 4) => B"0000", s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0), s_axi_arid(1 downto 0) => B"00", s_axi_arlen(15 downto 8) => B"00000000", s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0), s_axi_arlock(1) => '0', s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0), s_axi_arprot(5 downto 3) => B"000", s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), s_axi_arqos(7 downto 4) => B"0000", s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0), s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1), s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0), s_axi_arsize(5 downto 3) => B"000", s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0), s_axi_arvalid(1) => '0', s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID, s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0), s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0), s_axi_awburst(1 downto 0) => B"00", s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0), s_axi_awcache(3 downto 0) => B"0000", s_axi_awid(1 downto 0) => B"00", s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0), s_axi_awlen(7 downto 0) => B"00000000", s_axi_awlock(1) => s01_couplers_to_xbar_AWLOCK(0), s_axi_awlock(0) => '0', s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0), s_axi_awprot(2 downto 0) => B"000", s_axi_awqos(7 downto 4) => s01_couplers_to_xbar_AWQOS(3 downto 0), s_axi_awqos(3 downto 0) => B"0000", s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1), s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0), s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0), s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID, s_axi_awvalid(0) => '0', s_axi_bid(1 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(1 downto 0), s_axi_bready(1) => s01_couplers_to_xbar_BREADY, s_axi_bready(0) => '0', s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2), s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1), s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0), s_axi_rdata(127 downto 64) => NLW_xbar_s_axi_rdata_UNCONNECTED(127 downto 64), s_axi_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0), s_axi_rid(1 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(1 downto 0), s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1), s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0), s_axi_rready(1) => '0', s_axi_rready(0) => s00_couplers_to_xbar_RREADY, s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2), s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1), s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0), s_axi_wdata(127 downto 64) => s01_couplers_to_xbar_WDATA(63 downto 0), s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", s_axi_wlast(1) => s01_couplers_to_xbar_WLAST, s_axi_wlast(0) => '1', s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1), s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0), s_axi_wstrb(15 downto 8) => s01_couplers_to_xbar_WSTRB(7 downto 0), s_axi_wstrb(7 downto 0) => B"11111111", s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID, s_axi_wvalid(0) => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_processing_system7_0_axi_periph_0 is port ( ACLK : in STD_LOGIC; ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_ACLK : in STD_LOGIC; M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_arready : in STD_LOGIC; M00_AXI_arvalid : out STD_LOGIC; M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_awready : in STD_LOGIC; M00_AXI_awvalid : out STD_LOGIC; M00_AXI_bready : out STD_LOGIC; M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_bvalid : in STD_LOGIC; M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_rready : out STD_LOGIC; M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_rvalid : in STD_LOGIC; M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_wready : in STD_LOGIC; M00_AXI_wvalid : out STD_LOGIC; M01_ACLK : in STD_LOGIC; M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M01_AXI_arready : in STD_LOGIC; M01_AXI_arvalid : out STD_LOGIC; M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M01_AXI_awready : in STD_LOGIC; M01_AXI_awvalid : out STD_LOGIC; M01_AXI_bready : out STD_LOGIC; M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M01_AXI_bvalid : in STD_LOGIC; M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M01_AXI_rready : out STD_LOGIC; M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M01_AXI_rvalid : in STD_LOGIC; M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M01_AXI_wready : in STD_LOGIC; M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M01_AXI_wvalid : out STD_LOGIC; M02_ACLK : in STD_LOGIC; M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M02_AXI_arready : in STD_LOGIC; M02_AXI_arvalid : out STD_LOGIC; M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M02_AXI_awready : in STD_LOGIC; M02_AXI_awvalid : out STD_LOGIC; M02_AXI_bready : out STD_LOGIC; M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M02_AXI_bvalid : in STD_LOGIC; M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M02_AXI_rready : out STD_LOGIC; M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M02_AXI_rvalid : in STD_LOGIC; M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M02_AXI_wready : in STD_LOGIC; M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M02_AXI_wvalid : out STD_LOGIC; M03_ACLK : in STD_LOGIC; M03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M03_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M03_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M03_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); M03_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M03_AXI_arlock : out STD_LOGIC; M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M03_AXI_arready : in STD_LOGIC; M03_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M03_AXI_arvalid : out STD_LOGIC; M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M03_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M03_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M03_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); M03_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M03_AXI_awlock : out STD_LOGIC; M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M03_AXI_awready : in STD_LOGIC; M03_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M03_AXI_awvalid : out STD_LOGIC; M03_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); M03_AXI_bready : out STD_LOGIC; M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M03_AXI_bvalid : in STD_LOGIC; M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M03_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); M03_AXI_rlast : in STD_LOGIC; M03_AXI_rready : out STD_LOGIC; M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M03_AXI_rvalid : in STD_LOGIC; M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M03_AXI_wlast : out STD_LOGIC; M03_AXI_wready : in STD_LOGIC; M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M03_AXI_wvalid : out STD_LOGIC; M04_ACLK : in STD_LOGIC; M04_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M04_AXI_arready : in STD_LOGIC; M04_AXI_arvalid : out STD_LOGIC; M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M04_AXI_awready : in STD_LOGIC; M04_AXI_awvalid : out STD_LOGIC; M04_AXI_bready : out STD_LOGIC; M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M04_AXI_bvalid : in STD_LOGIC; M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M04_AXI_rready : out STD_LOGIC; M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M04_AXI_rvalid : in STD_LOGIC; M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M04_AXI_wready : in STD_LOGIC; M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M04_AXI_wvalid : out STD_LOGIC; S00_ACLK : in STD_LOGIC; S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arready : out STD_LOGIC; S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arvalid : in STD_LOGIC; S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awready : out STD_LOGIC; S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awvalid : in STD_LOGIC; S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_bready : in STD_LOGIC; S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_bvalid : out STD_LOGIC; S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_rlast : out STD_LOGIC; S00_AXI_rready : in STD_LOGIC; S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_rvalid : out STD_LOGIC; S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_wlast : in STD_LOGIC; S00_AXI_wready : out STD_LOGIC; S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_wvalid : in STD_LOGIC ); end design_1_processing_system7_0_axi_periph_0; architecture STRUCTURE of design_1_processing_system7_0_axi_periph_0 is component design_1_xbar_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awid : out STD_LOGIC_VECTOR ( 59 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 39 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 14 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 9 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 19 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 19 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 19 downto 0 ); m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 ); m_axi_wlast : out STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_bid : in STD_LOGIC_VECTOR ( 59 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 ); m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_arid : out STD_LOGIC_VECTOR ( 59 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 39 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 14 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 9 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 19 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 19 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 19 downto 0 ); m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 59 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 ) ); end component design_1_xbar_0; signal M00_ACLK_1 : STD_LOGIC; signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal M01_ACLK_1 : STD_LOGIC; signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal M02_ACLK_1 : STD_LOGIC; signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal M03_ACLK_1 : STD_LOGIC; signal M03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal M04_ACLK_1 : STD_LOGIC; signal M04_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal S00_ACLK_1 : STD_LOGIC; signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC; signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC; signal m02_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_ARLOCK : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_AWLOCK : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_RLAST : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_WLAST : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC; signal m03_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m03_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m04_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m04_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m04_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m04_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m04_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m04_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC; signal m04_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m04_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC; signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC; signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC; signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_xbar_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_xbar_ARVALID : STD_LOGIC; signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_xbar_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s00_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_xbar_AWVALID : STD_LOGIC; signal s00_couplers_to_xbar_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_xbar_BREADY : STD_LOGIC; signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_xbar_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_RREADY : STD_LOGIC; signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_xbar_WLAST : STD_LOGIC; signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_xbar_WVALID : STD_LOGIC; signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_ARREADY : STD_LOGIC; signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_AWREADY : STD_LOGIC; signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_BVALID : STD_LOGIC; signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m00_couplers_RLAST : STD_LOGIC; signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_RVALID : STD_LOGIC; signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_WREADY : STD_LOGIC; signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 ); signal xbar_to_m01_couplers_ARBURST : STD_LOGIC_VECTOR ( 3 downto 2 ); signal xbar_to_m01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 7 downto 4 ); signal xbar_to_m01_couplers_ARID : STD_LOGIC_VECTOR ( 23 downto 12 ); signal xbar_to_m01_couplers_ARLEN : STD_LOGIC_VECTOR ( 15 downto 8 ); signal xbar_to_m01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 to 1 ); signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 ); signal xbar_to_m01_couplers_ARQOS : STD_LOGIC_VECTOR ( 7 downto 4 ); signal xbar_to_m01_couplers_ARREADY : STD_LOGIC; signal xbar_to_m01_couplers_ARREGION : STD_LOGIC_VECTOR ( 7 downto 4 ); signal xbar_to_m01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 5 downto 3 ); signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 ); signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 ); signal xbar_to_m01_couplers_AWBURST : STD_LOGIC_VECTOR ( 3 downto 2 ); signal xbar_to_m01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 7 downto 4 ); signal xbar_to_m01_couplers_AWID : STD_LOGIC_VECTOR ( 23 downto 12 ); signal xbar_to_m01_couplers_AWLEN : STD_LOGIC_VECTOR ( 15 downto 8 ); signal xbar_to_m01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 to 1 ); signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 ); signal xbar_to_m01_couplers_AWQOS : STD_LOGIC_VECTOR ( 7 downto 4 ); signal xbar_to_m01_couplers_AWREADY : STD_LOGIC; signal xbar_to_m01_couplers_AWREGION : STD_LOGIC_VECTOR ( 7 downto 4 ); signal xbar_to_m01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 5 downto 3 ); signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 ); signal xbar_to_m01_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 ); signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m01_couplers_BVALID : STD_LOGIC; signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m01_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m01_couplers_RLAST : STD_LOGIC; signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 ); signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m01_couplers_RVALID : STD_LOGIC; signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 ); signal xbar_to_m01_couplers_WLAST : STD_LOGIC_VECTOR ( 1 to 1 ); signal xbar_to_m01_couplers_WREADY : STD_LOGIC; signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 ); signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 ); signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 ); signal xbar_to_m02_couplers_ARBURST : STD_LOGIC_VECTOR ( 5 downto 4 ); signal xbar_to_m02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 11 downto 8 ); signal xbar_to_m02_couplers_ARID : STD_LOGIC_VECTOR ( 35 downto 24 ); signal xbar_to_m02_couplers_ARLEN : STD_LOGIC_VECTOR ( 23 downto 16 ); signal xbar_to_m02_couplers_ARLOCK : STD_LOGIC_VECTOR ( 2 to 2 ); signal xbar_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 8 downto 6 ); signal xbar_to_m02_couplers_ARQOS : STD_LOGIC_VECTOR ( 11 downto 8 ); signal xbar_to_m02_couplers_ARREADY : STD_LOGIC; signal xbar_to_m02_couplers_ARREGION : STD_LOGIC_VECTOR ( 11 downto 8 ); signal xbar_to_m02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 8 downto 6 ); signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 ); signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 ); signal xbar_to_m02_couplers_AWBURST : STD_LOGIC_VECTOR ( 5 downto 4 ); signal xbar_to_m02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 11 downto 8 ); signal xbar_to_m02_couplers_AWID : STD_LOGIC_VECTOR ( 35 downto 24 ); signal xbar_to_m02_couplers_AWLEN : STD_LOGIC_VECTOR ( 23 downto 16 ); signal xbar_to_m02_couplers_AWLOCK : STD_LOGIC_VECTOR ( 2 to 2 ); signal xbar_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 8 downto 6 ); signal xbar_to_m02_couplers_AWQOS : STD_LOGIC_VECTOR ( 11 downto 8 ); signal xbar_to_m02_couplers_AWREADY : STD_LOGIC; signal xbar_to_m02_couplers_AWREGION : STD_LOGIC_VECTOR ( 11 downto 8 ); signal xbar_to_m02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 8 downto 6 ); signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 ); signal xbar_to_m02_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 ); signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m02_couplers_BVALID : STD_LOGIC; signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m02_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m02_couplers_RLAST : STD_LOGIC; signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 ); signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m02_couplers_RVALID : STD_LOGIC; signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 ); signal xbar_to_m02_couplers_WLAST : STD_LOGIC_VECTOR ( 2 to 2 ); signal xbar_to_m02_couplers_WREADY : STD_LOGIC; signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 ); signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 ); signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 ); signal xbar_to_m03_couplers_ARBURST : STD_LOGIC_VECTOR ( 7 downto 6 ); signal xbar_to_m03_couplers_ARCACHE : STD_LOGIC_VECTOR ( 15 downto 12 ); signal xbar_to_m03_couplers_ARID : STD_LOGIC_VECTOR ( 47 downto 36 ); signal xbar_to_m03_couplers_ARLEN : STD_LOGIC_VECTOR ( 31 downto 24 ); signal xbar_to_m03_couplers_ARLOCK : STD_LOGIC_VECTOR ( 3 to 3 ); signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 ); signal xbar_to_m03_couplers_ARREADY : STD_LOGIC; signal xbar_to_m03_couplers_ARSIZE : STD_LOGIC_VECTOR ( 11 downto 9 ); signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 ); signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 ); signal xbar_to_m03_couplers_AWBURST : STD_LOGIC_VECTOR ( 7 downto 6 ); signal xbar_to_m03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 15 downto 12 ); signal xbar_to_m03_couplers_AWID : STD_LOGIC_VECTOR ( 47 downto 36 ); signal xbar_to_m03_couplers_AWLEN : STD_LOGIC_VECTOR ( 31 downto 24 ); signal xbar_to_m03_couplers_AWLOCK : STD_LOGIC_VECTOR ( 3 to 3 ); signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 ); signal xbar_to_m03_couplers_AWREADY : STD_LOGIC; signal xbar_to_m03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 11 downto 9 ); signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 ); signal xbar_to_m03_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 ); signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m03_couplers_BVALID : STD_LOGIC; signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m03_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m03_couplers_RLAST : STD_LOGIC; signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 ); signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m03_couplers_RVALID : STD_LOGIC; signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 ); signal xbar_to_m03_couplers_WLAST : STD_LOGIC_VECTOR ( 3 to 3 ); signal xbar_to_m03_couplers_WREADY : STD_LOGIC; signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 ); signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 ); signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 ); signal xbar_to_m04_couplers_ARBURST : STD_LOGIC_VECTOR ( 9 downto 8 ); signal xbar_to_m04_couplers_ARCACHE : STD_LOGIC_VECTOR ( 19 downto 16 ); signal xbar_to_m04_couplers_ARID : STD_LOGIC_VECTOR ( 59 downto 48 ); signal xbar_to_m04_couplers_ARLEN : STD_LOGIC_VECTOR ( 39 downto 32 ); signal xbar_to_m04_couplers_ARLOCK : STD_LOGIC_VECTOR ( 4 to 4 ); signal xbar_to_m04_couplers_ARPROT : STD_LOGIC_VECTOR ( 14 downto 12 ); signal xbar_to_m04_couplers_ARQOS : STD_LOGIC_VECTOR ( 19 downto 16 ); signal xbar_to_m04_couplers_ARREADY : STD_LOGIC; signal xbar_to_m04_couplers_ARREGION : STD_LOGIC_VECTOR ( 19 downto 16 ); signal xbar_to_m04_couplers_ARSIZE : STD_LOGIC_VECTOR ( 14 downto 12 ); signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 ); signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 ); signal xbar_to_m04_couplers_AWBURST : STD_LOGIC_VECTOR ( 9 downto 8 ); signal xbar_to_m04_couplers_AWCACHE : STD_LOGIC_VECTOR ( 19 downto 16 ); signal xbar_to_m04_couplers_AWID : STD_LOGIC_VECTOR ( 59 downto 48 ); signal xbar_to_m04_couplers_AWLEN : STD_LOGIC_VECTOR ( 39 downto 32 ); signal xbar_to_m04_couplers_AWLOCK : STD_LOGIC_VECTOR ( 4 to 4 ); signal xbar_to_m04_couplers_AWPROT : STD_LOGIC_VECTOR ( 14 downto 12 ); signal xbar_to_m04_couplers_AWQOS : STD_LOGIC_VECTOR ( 19 downto 16 ); signal xbar_to_m04_couplers_AWREADY : STD_LOGIC; signal xbar_to_m04_couplers_AWREGION : STD_LOGIC_VECTOR ( 19 downto 16 ); signal xbar_to_m04_couplers_AWSIZE : STD_LOGIC_VECTOR ( 14 downto 12 ); signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 ); signal xbar_to_m04_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 ); signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m04_couplers_BVALID : STD_LOGIC; signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m04_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal xbar_to_m04_couplers_RLAST : STD_LOGIC; signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 ); signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m04_couplers_RVALID : STD_LOGIC; signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 ); signal xbar_to_m04_couplers_WLAST : STD_LOGIC_VECTOR ( 4 to 4 ); signal xbar_to_m04_couplers_WREADY : STD_LOGIC; signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 ); signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 ); signal NLW_xbar_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 ); signal NLW_xbar_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 ); signal NLW_xbar_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 ); signal NLW_xbar_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 ); begin M00_ACLK_1 <= M00_ACLK; M00_ARESETN_1(0) <= M00_ARESETN(0); M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0); M00_AXI_arvalid <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID; M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0); M00_AXI_awvalid <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID; M00_AXI_bready <= m00_couplers_to_processing_system7_0_axi_periph_BREADY; M00_AXI_rready <= m00_couplers_to_processing_system7_0_axi_periph_RREADY; M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0); M00_AXI_wvalid <= m00_couplers_to_processing_system7_0_axi_periph_WVALID; M01_ACLK_1 <= M01_ACLK; M01_ARESETN_1(0) <= M01_ARESETN(0); M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0); M01_AXI_arvalid <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID; M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0); M01_AXI_awvalid <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID; M01_AXI_bready <= m01_couplers_to_processing_system7_0_axi_periph_BREADY; M01_AXI_rready <= m01_couplers_to_processing_system7_0_axi_periph_RREADY; M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0); M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0); M01_AXI_wvalid <= m01_couplers_to_processing_system7_0_axi_periph_WVALID; M02_ACLK_1 <= M02_ACLK; M02_ARESETN_1(0) <= M02_ARESETN(0); M02_AXI_araddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0); M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID; M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0); M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID; M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY; M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY; M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0); M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0); M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID; M03_ACLK_1 <= M03_ACLK; M03_ARESETN_1(0) <= M03_ARESETN(0); M03_AXI_araddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0); M03_AXI_arburst(1 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARBURST(1 downto 0); M03_AXI_arcache(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARCACHE(3 downto 0); M03_AXI_arid(11 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARID(11 downto 0); M03_AXI_arlen(7 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARLEN(7 downto 0); M03_AXI_arlock <= m03_couplers_to_processing_system7_0_axi_periph_ARLOCK; M03_AXI_arprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0); M03_AXI_arsize(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARSIZE(2 downto 0); M03_AXI_arvalid <= m03_couplers_to_processing_system7_0_axi_periph_ARVALID; M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0); M03_AXI_awburst(1 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWBURST(1 downto 0); M03_AXI_awcache(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWCACHE(3 downto 0); M03_AXI_awid(11 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWID(11 downto 0); M03_AXI_awlen(7 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWLEN(7 downto 0); M03_AXI_awlock <= m03_couplers_to_processing_system7_0_axi_periph_AWLOCK; M03_AXI_awprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0); M03_AXI_awsize(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWSIZE(2 downto 0); M03_AXI_awvalid <= m03_couplers_to_processing_system7_0_axi_periph_AWVALID; M03_AXI_bready <= m03_couplers_to_processing_system7_0_axi_periph_BREADY; M03_AXI_rready <= m03_couplers_to_processing_system7_0_axi_periph_RREADY; M03_AXI_wdata(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0); M03_AXI_wlast <= m03_couplers_to_processing_system7_0_axi_periph_WLAST; M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0); M03_AXI_wvalid <= m03_couplers_to_processing_system7_0_axi_periph_WVALID; M04_ACLK_1 <= M04_ACLK; M04_ARESETN_1(0) <= M04_ARESETN(0); M04_AXI_araddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0); M04_AXI_arvalid <= m04_couplers_to_processing_system7_0_axi_periph_ARVALID; M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0); M04_AXI_awvalid <= m04_couplers_to_processing_system7_0_axi_periph_AWVALID; M04_AXI_bready <= m04_couplers_to_processing_system7_0_axi_periph_BREADY; M04_AXI_rready <= m04_couplers_to_processing_system7_0_axi_periph_RREADY; M04_AXI_wdata(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0); M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0); M04_AXI_wvalid <= m04_couplers_to_processing_system7_0_axi_periph_WVALID; S00_ACLK_1 <= S00_ACLK; S00_ARESETN_1(0) <= S00_ARESETN(0); S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY; S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY; S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0); S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0); S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID; S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0); S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0); S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST; S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0); S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID; S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY; m00_couplers_to_processing_system7_0_axi_periph_ARREADY <= M00_AXI_arready; m00_couplers_to_processing_system7_0_axi_periph_AWREADY <= M00_AXI_awready; m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); m00_couplers_to_processing_system7_0_axi_periph_BVALID <= M00_AXI_bvalid; m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0); m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); m00_couplers_to_processing_system7_0_axi_periph_RVALID <= M00_AXI_rvalid; m00_couplers_to_processing_system7_0_axi_periph_WREADY <= M00_AXI_wready; m01_couplers_to_processing_system7_0_axi_periph_ARREADY <= M01_AXI_arready; m01_couplers_to_processing_system7_0_axi_periph_AWREADY <= M01_AXI_awready; m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0); m01_couplers_to_processing_system7_0_axi_periph_BVALID <= M01_AXI_bvalid; m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0); m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0); m01_couplers_to_processing_system7_0_axi_periph_RVALID <= M01_AXI_rvalid; m01_couplers_to_processing_system7_0_axi_periph_WREADY <= M01_AXI_wready; m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready; m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready; m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0); m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid; m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0); m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0); m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid; m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready; m03_couplers_to_processing_system7_0_axi_periph_ARREADY <= M03_AXI_arready; m03_couplers_to_processing_system7_0_axi_periph_AWREADY <= M03_AXI_awready; m03_couplers_to_processing_system7_0_axi_periph_BID(11 downto 0) <= M03_AXI_bid(11 downto 0); m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0); m03_couplers_to_processing_system7_0_axi_periph_BVALID <= M03_AXI_bvalid; m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0); m03_couplers_to_processing_system7_0_axi_periph_RID(11 downto 0) <= M03_AXI_rid(11 downto 0); m03_couplers_to_processing_system7_0_axi_periph_RLAST <= M03_AXI_rlast; m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0); m03_couplers_to_processing_system7_0_axi_periph_RVALID <= M03_AXI_rvalid; m03_couplers_to_processing_system7_0_axi_periph_WREADY <= M03_AXI_wready; m04_couplers_to_processing_system7_0_axi_periph_ARREADY <= M04_AXI_arready; m04_couplers_to_processing_system7_0_axi_periph_AWREADY <= M04_AXI_awready; m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0); m04_couplers_to_processing_system7_0_axi_periph_BVALID <= M04_AXI_bvalid; m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0); m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0); m04_couplers_to_processing_system7_0_axi_periph_RVALID <= M04_AXI_rvalid; m04_couplers_to_processing_system7_0_axi_periph_WREADY <= M04_AXI_wready; processing_system7_0_axi_periph_ACLK_net <= ACLK; processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0); processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid; processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid; processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready; processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready; processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0); processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast; processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid; m00_couplers: entity work.m00_couplers_imp_OBU1DD port map ( M_ACLK => M00_ACLK_1, M_ARESETN(0) => M00_ARESETN_1(0), M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0), M_AXI_arready => m00_couplers_to_processing_system7_0_axi_periph_ARREADY, M_AXI_arvalid => m00_couplers_to_processing_system7_0_axi_periph_ARVALID, M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0), M_AXI_awready => m00_couplers_to_processing_system7_0_axi_periph_AWREADY, M_AXI_awvalid => m00_couplers_to_processing_system7_0_axi_periph_AWVALID, M_AXI_bready => m00_couplers_to_processing_system7_0_axi_periph_BREADY, M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0), M_AXI_bvalid => m00_couplers_to_processing_system7_0_axi_periph_BVALID, M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0), M_AXI_rready => m00_couplers_to_processing_system7_0_axi_periph_RREADY, M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0), M_AXI_rvalid => m00_couplers_to_processing_system7_0_axi_periph_RVALID, M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0), M_AXI_wready => m00_couplers_to_processing_system7_0_axi_periph_WREADY, M_AXI_wvalid => m00_couplers_to_processing_system7_0_axi_periph_WVALID, S_ACLK => processing_system7_0_axi_periph_ACLK_net, S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0), S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0), S_AXI_arid(11 downto 0) => xbar_to_m00_couplers_ARID(11 downto 0), S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0), S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0), S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0), S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0), S_AXI_arready => xbar_to_m00_couplers_ARREADY, S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0), S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0), S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0), S_AXI_awid(11 downto 0) => xbar_to_m00_couplers_AWID(11 downto 0), S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0), S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0), S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0), S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0), S_AXI_awready => xbar_to_m00_couplers_AWREADY, S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0), S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0), S_AXI_bid(11 downto 0) => xbar_to_m00_couplers_BID(11 downto 0), S_AXI_bready => xbar_to_m00_couplers_BREADY(0), S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), S_AXI_bvalid => xbar_to_m00_couplers_BVALID, S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0), S_AXI_rid(11 downto 0) => xbar_to_m00_couplers_RID(11 downto 0), S_AXI_rlast => xbar_to_m00_couplers_RLAST, S_AXI_rready => xbar_to_m00_couplers_RREADY(0), S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), S_AXI_rvalid => xbar_to_m00_couplers_RVALID, S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0), S_AXI_wlast => xbar_to_m00_couplers_WLAST(0), S_AXI_wready => xbar_to_m00_couplers_WREADY, S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0), S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0) ); m01_couplers: entity work.m01_couplers_imp_1FBREZ4 port map ( M_ACLK => M01_ACLK_1, M_ARESETN(0) => M01_ARESETN_1(0), M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0), M_AXI_arready => m01_couplers_to_processing_system7_0_axi_periph_ARREADY, M_AXI_arvalid => m01_couplers_to_processing_system7_0_axi_periph_ARVALID, M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0), M_AXI_awready => m01_couplers_to_processing_system7_0_axi_periph_AWREADY, M_AXI_awvalid => m01_couplers_to_processing_system7_0_axi_periph_AWVALID, M_AXI_bready => m01_couplers_to_processing_system7_0_axi_periph_BREADY, M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0), M_AXI_bvalid => m01_couplers_to_processing_system7_0_axi_periph_BVALID, M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0), M_AXI_rready => m01_couplers_to_processing_system7_0_axi_periph_RREADY, M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0), M_AXI_rvalid => m01_couplers_to_processing_system7_0_axi_periph_RVALID, M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0), M_AXI_wready => m01_couplers_to_processing_system7_0_axi_periph_WREADY, M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0), M_AXI_wvalid => m01_couplers_to_processing_system7_0_axi_periph_WVALID, S_ACLK => processing_system7_0_axi_periph_ACLK_net, S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0), S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32), S_AXI_arburst(1 downto 0) => xbar_to_m01_couplers_ARBURST(3 downto 2), S_AXI_arcache(3 downto 0) => xbar_to_m01_couplers_ARCACHE(7 downto 4), S_AXI_arid(11 downto 0) => xbar_to_m01_couplers_ARID(23 downto 12), S_AXI_arlen(7 downto 0) => xbar_to_m01_couplers_ARLEN(15 downto 8), S_AXI_arlock(0) => xbar_to_m01_couplers_ARLOCK(1), S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3), S_AXI_arqos(3 downto 0) => xbar_to_m01_couplers_ARQOS(7 downto 4), S_AXI_arready => xbar_to_m01_couplers_ARREADY, S_AXI_arregion(3 downto 0) => xbar_to_m01_couplers_ARREGION(7 downto 4), S_AXI_arsize(2 downto 0) => xbar_to_m01_couplers_ARSIZE(5 downto 3), S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1), S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32), S_AXI_awburst(1 downto 0) => xbar_to_m01_couplers_AWBURST(3 downto 2), S_AXI_awcache(3 downto 0) => xbar_to_m01_couplers_AWCACHE(7 downto 4), S_AXI_awid(11 downto 0) => xbar_to_m01_couplers_AWID(23 downto 12), S_AXI_awlen(7 downto 0) => xbar_to_m01_couplers_AWLEN(15 downto 8), S_AXI_awlock(0) => xbar_to_m01_couplers_AWLOCK(1), S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3), S_AXI_awqos(3 downto 0) => xbar_to_m01_couplers_AWQOS(7 downto 4), S_AXI_awready => xbar_to_m01_couplers_AWREADY, S_AXI_awregion(3 downto 0) => xbar_to_m01_couplers_AWREGION(7 downto 4), S_AXI_awsize(2 downto 0) => xbar_to_m01_couplers_AWSIZE(5 downto 3), S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1), S_AXI_bid(11 downto 0) => xbar_to_m01_couplers_BID(11 downto 0), S_AXI_bready => xbar_to_m01_couplers_BREADY(1), S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0), S_AXI_bvalid => xbar_to_m01_couplers_BVALID, S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0), S_AXI_rid(11 downto 0) => xbar_to_m01_couplers_RID(11 downto 0), S_AXI_rlast => xbar_to_m01_couplers_RLAST, S_AXI_rready => xbar_to_m01_couplers_RREADY(1), S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0), S_AXI_rvalid => xbar_to_m01_couplers_RVALID, S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32), S_AXI_wlast => xbar_to_m01_couplers_WLAST(1), S_AXI_wready => xbar_to_m01_couplers_WREADY, S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4), S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1) ); m02_couplers: entity work.m02_couplers_imp_MVV5YQ port map ( M_ACLK => M02_ACLK_1, M_ARESETN(0) => M02_ARESETN_1(0), M_AXI_araddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0), M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY, M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID, M_AXI_awaddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0), M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY, M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID, M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY, M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0), M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID, M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0), M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY, M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0), M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID, M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0), M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY, M_AXI_wstrb(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0), M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID, S_ACLK => processing_system7_0_axi_periph_ACLK_net, S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0), S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64), S_AXI_arburst(1 downto 0) => xbar_to_m02_couplers_ARBURST(5 downto 4), S_AXI_arcache(3 downto 0) => xbar_to_m02_couplers_ARCACHE(11 downto 8), S_AXI_arid(11 downto 0) => xbar_to_m02_couplers_ARID(35 downto 24), S_AXI_arlen(7 downto 0) => xbar_to_m02_couplers_ARLEN(23 downto 16), S_AXI_arlock(0) => xbar_to_m02_couplers_ARLOCK(2), S_AXI_arprot(2 downto 0) => xbar_to_m02_couplers_ARPROT(8 downto 6), S_AXI_arqos(3 downto 0) => xbar_to_m02_couplers_ARQOS(11 downto 8), S_AXI_arready => xbar_to_m02_couplers_ARREADY, S_AXI_arregion(3 downto 0) => xbar_to_m02_couplers_ARREGION(11 downto 8), S_AXI_arsize(2 downto 0) => xbar_to_m02_couplers_ARSIZE(8 downto 6), S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2), S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64), S_AXI_awburst(1 downto 0) => xbar_to_m02_couplers_AWBURST(5 downto 4), S_AXI_awcache(3 downto 0) => xbar_to_m02_couplers_AWCACHE(11 downto 8), S_AXI_awid(11 downto 0) => xbar_to_m02_couplers_AWID(35 downto 24), S_AXI_awlen(7 downto 0) => xbar_to_m02_couplers_AWLEN(23 downto 16), S_AXI_awlock(0) => xbar_to_m02_couplers_AWLOCK(2), S_AXI_awprot(2 downto 0) => xbar_to_m02_couplers_AWPROT(8 downto 6), S_AXI_awqos(3 downto 0) => xbar_to_m02_couplers_AWQOS(11 downto 8), S_AXI_awready => xbar_to_m02_couplers_AWREADY, S_AXI_awregion(3 downto 0) => xbar_to_m02_couplers_AWREGION(11 downto 8), S_AXI_awsize(2 downto 0) => xbar_to_m02_couplers_AWSIZE(8 downto 6), S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2), S_AXI_bid(11 downto 0) => xbar_to_m02_couplers_BID(11 downto 0), S_AXI_bready => xbar_to_m02_couplers_BREADY(2), S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0), S_AXI_bvalid => xbar_to_m02_couplers_BVALID, S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0), S_AXI_rid(11 downto 0) => xbar_to_m02_couplers_RID(11 downto 0), S_AXI_rlast => xbar_to_m02_couplers_RLAST, S_AXI_rready => xbar_to_m02_couplers_RREADY(2), S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0), S_AXI_rvalid => xbar_to_m02_couplers_RVALID, S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64), S_AXI_wlast => xbar_to_m02_couplers_WLAST(2), S_AXI_wready => xbar_to_m02_couplers_WREADY, S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8), S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2) ); m03_couplers: entity work.m03_couplers_imp_1GHG26R port map ( M_ACLK => M03_ACLK_1, M_ARESETN(0) => M03_ARESETN_1(0), M_AXI_araddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0), M_AXI_arburst(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARBURST(1 downto 0), M_AXI_arcache(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARCACHE(3 downto 0), M_AXI_arid(11 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARID(11 downto 0), M_AXI_arlen(7 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARLEN(7 downto 0), M_AXI_arlock => m03_couplers_to_processing_system7_0_axi_periph_ARLOCK, M_AXI_arprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0), M_AXI_arready => m03_couplers_to_processing_system7_0_axi_periph_ARREADY, M_AXI_arsize(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARSIZE(2 downto 0), M_AXI_arvalid => m03_couplers_to_processing_system7_0_axi_periph_ARVALID, M_AXI_awaddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0), M_AXI_awburst(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWBURST(1 downto 0), M_AXI_awcache(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWCACHE(3 downto 0), M_AXI_awid(11 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWID(11 downto 0), M_AXI_awlen(7 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWLEN(7 downto 0), M_AXI_awlock => m03_couplers_to_processing_system7_0_axi_periph_AWLOCK, M_AXI_awprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0), M_AXI_awready => m03_couplers_to_processing_system7_0_axi_periph_AWREADY, M_AXI_awsize(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWSIZE(2 downto 0), M_AXI_awvalid => m03_couplers_to_processing_system7_0_axi_periph_AWVALID, M_AXI_bid(11 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BID(11 downto 0), M_AXI_bready => m03_couplers_to_processing_system7_0_axi_periph_BREADY, M_AXI_bresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0), M_AXI_bvalid => m03_couplers_to_processing_system7_0_axi_periph_BVALID, M_AXI_rdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0), M_AXI_rid(11 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RID(11 downto 0), M_AXI_rlast => m03_couplers_to_processing_system7_0_axi_periph_RLAST, M_AXI_rready => m03_couplers_to_processing_system7_0_axi_periph_RREADY, M_AXI_rresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0), M_AXI_rvalid => m03_couplers_to_processing_system7_0_axi_periph_RVALID, M_AXI_wdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0), M_AXI_wlast => m03_couplers_to_processing_system7_0_axi_periph_WLAST, M_AXI_wready => m03_couplers_to_processing_system7_0_axi_periph_WREADY, M_AXI_wstrb(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0), M_AXI_wvalid => m03_couplers_to_processing_system7_0_axi_periph_WVALID, S_ACLK => processing_system7_0_axi_periph_ACLK_net, S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0), S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96), S_AXI_arburst(1 downto 0) => xbar_to_m03_couplers_ARBURST(7 downto 6), S_AXI_arcache(3 downto 0) => xbar_to_m03_couplers_ARCACHE(15 downto 12), S_AXI_arid(11 downto 0) => xbar_to_m03_couplers_ARID(47 downto 36), S_AXI_arlen(7 downto 0) => xbar_to_m03_couplers_ARLEN(31 downto 24), S_AXI_arlock => xbar_to_m03_couplers_ARLOCK(3), S_AXI_arprot(2 downto 0) => xbar_to_m03_couplers_ARPROT(11 downto 9), S_AXI_arready => xbar_to_m03_couplers_ARREADY, S_AXI_arsize(2 downto 0) => xbar_to_m03_couplers_ARSIZE(11 downto 9), S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3), S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96), S_AXI_awburst(1 downto 0) => xbar_to_m03_couplers_AWBURST(7 downto 6), S_AXI_awcache(3 downto 0) => xbar_to_m03_couplers_AWCACHE(15 downto 12), S_AXI_awid(11 downto 0) => xbar_to_m03_couplers_AWID(47 downto 36), S_AXI_awlen(7 downto 0) => xbar_to_m03_couplers_AWLEN(31 downto 24), S_AXI_awlock => xbar_to_m03_couplers_AWLOCK(3), S_AXI_awprot(2 downto 0) => xbar_to_m03_couplers_AWPROT(11 downto 9), S_AXI_awready => xbar_to_m03_couplers_AWREADY, S_AXI_awsize(2 downto 0) => xbar_to_m03_couplers_AWSIZE(11 downto 9), S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3), S_AXI_bid(11 downto 0) => xbar_to_m03_couplers_BID(11 downto 0), S_AXI_bready => xbar_to_m03_couplers_BREADY(3), S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0), S_AXI_bvalid => xbar_to_m03_couplers_BVALID, S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0), S_AXI_rid(11 downto 0) => xbar_to_m03_couplers_RID(11 downto 0), S_AXI_rlast => xbar_to_m03_couplers_RLAST, S_AXI_rready => xbar_to_m03_couplers_RREADY(3), S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0), S_AXI_rvalid => xbar_to_m03_couplers_RVALID, S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96), S_AXI_wlast => xbar_to_m03_couplers_WLAST(3), S_AXI_wready => xbar_to_m03_couplers_WREADY, S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12), S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3) ); m04_couplers: entity work.m04_couplers_imp_PJ7QT3 port map ( M_ACLK => M04_ACLK_1, M_ARESETN(0) => M04_ARESETN_1(0), M_AXI_araddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0), M_AXI_arready => m04_couplers_to_processing_system7_0_axi_periph_ARREADY, M_AXI_arvalid => m04_couplers_to_processing_system7_0_axi_periph_ARVALID, M_AXI_awaddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0), M_AXI_awready => m04_couplers_to_processing_system7_0_axi_periph_AWREADY, M_AXI_awvalid => m04_couplers_to_processing_system7_0_axi_periph_AWVALID, M_AXI_bready => m04_couplers_to_processing_system7_0_axi_periph_BREADY, M_AXI_bresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0), M_AXI_bvalid => m04_couplers_to_processing_system7_0_axi_periph_BVALID, M_AXI_rdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0), M_AXI_rready => m04_couplers_to_processing_system7_0_axi_periph_RREADY, M_AXI_rresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0), M_AXI_rvalid => m04_couplers_to_processing_system7_0_axi_periph_RVALID, M_AXI_wdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0), M_AXI_wready => m04_couplers_to_processing_system7_0_axi_periph_WREADY, M_AXI_wstrb(3 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0), M_AXI_wvalid => m04_couplers_to_processing_system7_0_axi_periph_WVALID, S_ACLK => processing_system7_0_axi_periph_ACLK_net, S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0), S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128), S_AXI_arburst(1 downto 0) => xbar_to_m04_couplers_ARBURST(9 downto 8), S_AXI_arcache(3 downto 0) => xbar_to_m04_couplers_ARCACHE(19 downto 16), S_AXI_arid(11 downto 0) => xbar_to_m04_couplers_ARID(59 downto 48), S_AXI_arlen(7 downto 0) => xbar_to_m04_couplers_ARLEN(39 downto 32), S_AXI_arlock(0) => xbar_to_m04_couplers_ARLOCK(4), S_AXI_arprot(2 downto 0) => xbar_to_m04_couplers_ARPROT(14 downto 12), S_AXI_arqos(3 downto 0) => xbar_to_m04_couplers_ARQOS(19 downto 16), S_AXI_arready => xbar_to_m04_couplers_ARREADY, S_AXI_arregion(3 downto 0) => xbar_to_m04_couplers_ARREGION(19 downto 16), S_AXI_arsize(2 downto 0) => xbar_to_m04_couplers_ARSIZE(14 downto 12), S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4), S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128), S_AXI_awburst(1 downto 0) => xbar_to_m04_couplers_AWBURST(9 downto 8), S_AXI_awcache(3 downto 0) => xbar_to_m04_couplers_AWCACHE(19 downto 16), S_AXI_awid(11 downto 0) => xbar_to_m04_couplers_AWID(59 downto 48), S_AXI_awlen(7 downto 0) => xbar_to_m04_couplers_AWLEN(39 downto 32), S_AXI_awlock(0) => xbar_to_m04_couplers_AWLOCK(4), S_AXI_awprot(2 downto 0) => xbar_to_m04_couplers_AWPROT(14 downto 12), S_AXI_awqos(3 downto 0) => xbar_to_m04_couplers_AWQOS(19 downto 16), S_AXI_awready => xbar_to_m04_couplers_AWREADY, S_AXI_awregion(3 downto 0) => xbar_to_m04_couplers_AWREGION(19 downto 16), S_AXI_awsize(2 downto 0) => xbar_to_m04_couplers_AWSIZE(14 downto 12), S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4), S_AXI_bid(11 downto 0) => xbar_to_m04_couplers_BID(11 downto 0), S_AXI_bready => xbar_to_m04_couplers_BREADY(4), S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0), S_AXI_bvalid => xbar_to_m04_couplers_BVALID, S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0), S_AXI_rid(11 downto 0) => xbar_to_m04_couplers_RID(11 downto 0), S_AXI_rlast => xbar_to_m04_couplers_RLAST, S_AXI_rready => xbar_to_m04_couplers_RREADY(4), S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0), S_AXI_rvalid => xbar_to_m04_couplers_RVALID, S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128), S_AXI_wlast => xbar_to_m04_couplers_WLAST(4), S_AXI_wready => xbar_to_m04_couplers_WREADY, S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16), S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4) ); s00_couplers: entity work.s00_couplers_imp_1CFO1MB port map ( M_ACLK => processing_system7_0_axi_periph_ACLK_net, M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0), M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0), M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0), M_AXI_arid(11 downto 0) => s00_couplers_to_xbar_ARID(11 downto 0), M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0), M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0), M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0), M_AXI_arready => s00_couplers_to_xbar_ARREADY(0), M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0), M_AXI_arvalid => s00_couplers_to_xbar_ARVALID, M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0), M_AXI_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0), M_AXI_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0), M_AXI_awid(11 downto 0) => s00_couplers_to_xbar_AWID(11 downto 0), M_AXI_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0), M_AXI_awlock(0) => s00_couplers_to_xbar_AWLOCK(0), M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0), M_AXI_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0), M_AXI_awready => s00_couplers_to_xbar_AWREADY(0), M_AXI_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0), M_AXI_awvalid => s00_couplers_to_xbar_AWVALID, M_AXI_bid(11 downto 0) => s00_couplers_to_xbar_BID(11 downto 0), M_AXI_bready => s00_couplers_to_xbar_BREADY, M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0), M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0), M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0), M_AXI_rid(11 downto 0) => s00_couplers_to_xbar_RID(11 downto 0), M_AXI_rlast => s00_couplers_to_xbar_RLAST(0), M_AXI_rready => s00_couplers_to_xbar_RREADY, M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0), M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0), M_AXI_wlast => s00_couplers_to_xbar_WLAST, M_AXI_wready => s00_couplers_to_xbar_WREADY(0), M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0), M_AXI_wvalid => s00_couplers_to_xbar_WVALID, S_ACLK => S00_ACLK_1, S_ARESETN(0) => S00_ARESETN_1(0), S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0), S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0), S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0), S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0), S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0), S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0), S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY, S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID, S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0), S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0), S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0), S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0), S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0), S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0), S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY, S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID, S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0), S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY, S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0), S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID, S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0), S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0), S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST, S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY, S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0), S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID, S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0), S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0), S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST, S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY, S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0), S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID ); xbar: component design_1_xbar_0 port map ( aclk => processing_system7_0_axi_periph_ACLK_net, aresetn => processing_system7_0_axi_periph_ARESETN_net(0), m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128), m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96), m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64), m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32), m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), m_axi_arburst(9 downto 8) => xbar_to_m04_couplers_ARBURST(9 downto 8), m_axi_arburst(7 downto 6) => xbar_to_m03_couplers_ARBURST(7 downto 6), m_axi_arburst(5 downto 4) => xbar_to_m02_couplers_ARBURST(5 downto 4), m_axi_arburst(3 downto 2) => xbar_to_m01_couplers_ARBURST(3 downto 2), m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0), m_axi_arcache(19 downto 16) => xbar_to_m04_couplers_ARCACHE(19 downto 16), m_axi_arcache(15 downto 12) => xbar_to_m03_couplers_ARCACHE(15 downto 12), m_axi_arcache(11 downto 8) => xbar_to_m02_couplers_ARCACHE(11 downto 8), m_axi_arcache(7 downto 4) => xbar_to_m01_couplers_ARCACHE(7 downto 4), m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0), m_axi_arid(59 downto 48) => xbar_to_m04_couplers_ARID(59 downto 48), m_axi_arid(47 downto 36) => xbar_to_m03_couplers_ARID(47 downto 36), m_axi_arid(35 downto 24) => xbar_to_m02_couplers_ARID(35 downto 24), m_axi_arid(23 downto 12) => xbar_to_m01_couplers_ARID(23 downto 12), m_axi_arid(11 downto 0) => xbar_to_m00_couplers_ARID(11 downto 0), m_axi_arlen(39 downto 32) => xbar_to_m04_couplers_ARLEN(39 downto 32), m_axi_arlen(31 downto 24) => xbar_to_m03_couplers_ARLEN(31 downto 24), m_axi_arlen(23 downto 16) => xbar_to_m02_couplers_ARLEN(23 downto 16), m_axi_arlen(15 downto 8) => xbar_to_m01_couplers_ARLEN(15 downto 8), m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0), m_axi_arlock(4) => xbar_to_m04_couplers_ARLOCK(4), m_axi_arlock(3) => xbar_to_m03_couplers_ARLOCK(3), m_axi_arlock(2) => xbar_to_m02_couplers_ARLOCK(2), m_axi_arlock(1) => xbar_to_m01_couplers_ARLOCK(1), m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0), m_axi_arprot(14 downto 12) => xbar_to_m04_couplers_ARPROT(14 downto 12), m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9), m_axi_arprot(8 downto 6) => xbar_to_m02_couplers_ARPROT(8 downto 6), m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3), m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0), m_axi_arqos(19 downto 16) => xbar_to_m04_couplers_ARQOS(19 downto 16), m_axi_arqos(15 downto 12) => NLW_xbar_m_axi_arqos_UNCONNECTED(15 downto 12), m_axi_arqos(11 downto 8) => xbar_to_m02_couplers_ARQOS(11 downto 8), m_axi_arqos(7 downto 4) => xbar_to_m01_couplers_ARQOS(7 downto 4), m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0), m_axi_arready(4) => xbar_to_m04_couplers_ARREADY, m_axi_arready(3) => xbar_to_m03_couplers_ARREADY, m_axi_arready(2) => xbar_to_m02_couplers_ARREADY, m_axi_arready(1) => xbar_to_m01_couplers_ARREADY, m_axi_arready(0) => xbar_to_m00_couplers_ARREADY, m_axi_arregion(19 downto 16) => xbar_to_m04_couplers_ARREGION(19 downto 16), m_axi_arregion(15 downto 12) => NLW_xbar_m_axi_arregion_UNCONNECTED(15 downto 12), m_axi_arregion(11 downto 8) => xbar_to_m02_couplers_ARREGION(11 downto 8), m_axi_arregion(7 downto 4) => xbar_to_m01_couplers_ARREGION(7 downto 4), m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0), m_axi_arsize(14 downto 12) => xbar_to_m04_couplers_ARSIZE(14 downto 12), m_axi_arsize(11 downto 9) => xbar_to_m03_couplers_ARSIZE(11 downto 9), m_axi_arsize(8 downto 6) => xbar_to_m02_couplers_ARSIZE(8 downto 6), m_axi_arsize(5 downto 3) => xbar_to_m01_couplers_ARSIZE(5 downto 3), m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0), m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4), m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3), m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2), m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1), m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0), m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128), m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96), m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64), m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32), m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), m_axi_awburst(9 downto 8) => xbar_to_m04_couplers_AWBURST(9 downto 8), m_axi_awburst(7 downto 6) => xbar_to_m03_couplers_AWBURST(7 downto 6), m_axi_awburst(5 downto 4) => xbar_to_m02_couplers_AWBURST(5 downto 4), m_axi_awburst(3 downto 2) => xbar_to_m01_couplers_AWBURST(3 downto 2), m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0), m_axi_awcache(19 downto 16) => xbar_to_m04_couplers_AWCACHE(19 downto 16), m_axi_awcache(15 downto 12) => xbar_to_m03_couplers_AWCACHE(15 downto 12), m_axi_awcache(11 downto 8) => xbar_to_m02_couplers_AWCACHE(11 downto 8), m_axi_awcache(7 downto 4) => xbar_to_m01_couplers_AWCACHE(7 downto 4), m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0), m_axi_awid(59 downto 48) => xbar_to_m04_couplers_AWID(59 downto 48), m_axi_awid(47 downto 36) => xbar_to_m03_couplers_AWID(47 downto 36), m_axi_awid(35 downto 24) => xbar_to_m02_couplers_AWID(35 downto 24), m_axi_awid(23 downto 12) => xbar_to_m01_couplers_AWID(23 downto 12), m_axi_awid(11 downto 0) => xbar_to_m00_couplers_AWID(11 downto 0), m_axi_awlen(39 downto 32) => xbar_to_m04_couplers_AWLEN(39 downto 32), m_axi_awlen(31 downto 24) => xbar_to_m03_couplers_AWLEN(31 downto 24), m_axi_awlen(23 downto 16) => xbar_to_m02_couplers_AWLEN(23 downto 16), m_axi_awlen(15 downto 8) => xbar_to_m01_couplers_AWLEN(15 downto 8), m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0), m_axi_awlock(4) => xbar_to_m04_couplers_AWLOCK(4), m_axi_awlock(3) => xbar_to_m03_couplers_AWLOCK(3), m_axi_awlock(2) => xbar_to_m02_couplers_AWLOCK(2), m_axi_awlock(1) => xbar_to_m01_couplers_AWLOCK(1), m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0), m_axi_awprot(14 downto 12) => xbar_to_m04_couplers_AWPROT(14 downto 12), m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9), m_axi_awprot(8 downto 6) => xbar_to_m02_couplers_AWPROT(8 downto 6), m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3), m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0), m_axi_awqos(19 downto 16) => xbar_to_m04_couplers_AWQOS(19 downto 16), m_axi_awqos(15 downto 12) => NLW_xbar_m_axi_awqos_UNCONNECTED(15 downto 12), m_axi_awqos(11 downto 8) => xbar_to_m02_couplers_AWQOS(11 downto 8), m_axi_awqos(7 downto 4) => xbar_to_m01_couplers_AWQOS(7 downto 4), m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0), m_axi_awready(4) => xbar_to_m04_couplers_AWREADY, m_axi_awready(3) => xbar_to_m03_couplers_AWREADY, m_axi_awready(2) => xbar_to_m02_couplers_AWREADY, m_axi_awready(1) => xbar_to_m01_couplers_AWREADY, m_axi_awready(0) => xbar_to_m00_couplers_AWREADY, m_axi_awregion(19 downto 16) => xbar_to_m04_couplers_AWREGION(19 downto 16), m_axi_awregion(15 downto 12) => NLW_xbar_m_axi_awregion_UNCONNECTED(15 downto 12), m_axi_awregion(11 downto 8) => xbar_to_m02_couplers_AWREGION(11 downto 8), m_axi_awregion(7 downto 4) => xbar_to_m01_couplers_AWREGION(7 downto 4), m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0), m_axi_awsize(14 downto 12) => xbar_to_m04_couplers_AWSIZE(14 downto 12), m_axi_awsize(11 downto 9) => xbar_to_m03_couplers_AWSIZE(11 downto 9), m_axi_awsize(8 downto 6) => xbar_to_m02_couplers_AWSIZE(8 downto 6), m_axi_awsize(5 downto 3) => xbar_to_m01_couplers_AWSIZE(5 downto 3), m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0), m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4), m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3), m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2), m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1), m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0), m_axi_bid(59 downto 48) => xbar_to_m04_couplers_BID(11 downto 0), m_axi_bid(47 downto 36) => xbar_to_m03_couplers_BID(11 downto 0), m_axi_bid(35 downto 24) => xbar_to_m02_couplers_BID(11 downto 0), m_axi_bid(23 downto 12) => xbar_to_m01_couplers_BID(11 downto 0), m_axi_bid(11 downto 0) => xbar_to_m00_couplers_BID(11 downto 0), m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4), m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3), m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2), m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1), m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0), m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0), m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0), m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0), m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0), m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID, m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID, m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID, m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID, m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID, m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0), m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0), m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0), m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0), m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0), m_axi_rid(59 downto 48) => xbar_to_m04_couplers_RID(11 downto 0), m_axi_rid(47 downto 36) => xbar_to_m03_couplers_RID(11 downto 0), m_axi_rid(35 downto 24) => xbar_to_m02_couplers_RID(11 downto 0), m_axi_rid(23 downto 12) => xbar_to_m01_couplers_RID(11 downto 0), m_axi_rid(11 downto 0) => xbar_to_m00_couplers_RID(11 downto 0), m_axi_rlast(4) => xbar_to_m04_couplers_RLAST, m_axi_rlast(3) => xbar_to_m03_couplers_RLAST, m_axi_rlast(2) => xbar_to_m02_couplers_RLAST, m_axi_rlast(1) => xbar_to_m01_couplers_RLAST, m_axi_rlast(0) => xbar_to_m00_couplers_RLAST, m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4), m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3), m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2), m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1), m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0), m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0), m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0), m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0), m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0), m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID, m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID, m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID, m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID, m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID, m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128), m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96), m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64), m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32), m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0), m_axi_wlast(4) => xbar_to_m04_couplers_WLAST(4), m_axi_wlast(3) => xbar_to_m03_couplers_WLAST(3), m_axi_wlast(2) => xbar_to_m02_couplers_WLAST(2), m_axi_wlast(1) => xbar_to_m01_couplers_WLAST(1), m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0), m_axi_wready(4) => xbar_to_m04_couplers_WREADY, m_axi_wready(3) => xbar_to_m03_couplers_WREADY, m_axi_wready(2) => xbar_to_m02_couplers_WREADY, m_axi_wready(1) => xbar_to_m01_couplers_WREADY, m_axi_wready(0) => xbar_to_m00_couplers_WREADY, m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16), m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12), m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8), m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4), m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0), m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4), m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3), m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2), m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1), m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0), s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0), s_axi_arid(11 downto 0) => s00_couplers_to_xbar_ARID(11 downto 0), s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0), s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0), s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0), s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0), s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0), s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID, s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => s00_couplers_to_xbar_AWID(11 downto 0), s_axi_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0), s_axi_awlock(0) => s00_couplers_to_xbar_AWLOCK(0), s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0), s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0), s_axi_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0), s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID, s_axi_bid(11 downto 0) => s00_couplers_to_xbar_BID(11 downto 0), s_axi_bready(0) => s00_couplers_to_xbar_BREADY, s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0), s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0), s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0), s_axi_rid(11 downto 0) => s00_couplers_to_xbar_RID(11 downto 0), s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0), s_axi_rready(0) => s00_couplers_to_xbar_RREADY, s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0), s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0), s_axi_wlast(0) => s00_couplers_to_xbar_WLAST, s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0), s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0), s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1 is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC ); attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=30,numReposBlks=19,numNonXlnxBlks=2,numHierBlks=11,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=2,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=7,da_board_cnt=1,da_bram_cntlr_cnt=1,da_ps7_cnt=1,synth_mode=Global}"; attribute HW_HANDOFF : string; attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef"; end design_1; architecture STRUCTURE of design_1 is component design_1_processing_system7_0_0 is port ( TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end component design_1_processing_system7_0_0; component design_1_axi_dma_0_0 is port ( s_axi_lite_aclk : in STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; m_axi_s2mm_aclk : in STD_LOGIC; axi_resetn : in STD_LOGIC; s_axi_lite_awvalid : in STD_LOGIC; s_axi_lite_awready : out STD_LOGIC; s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); s_axi_lite_wvalid : in STD_LOGIC; s_axi_lite_wready : out STD_LOGIC; s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_lite_bvalid : out STD_LOGIC; s_axi_lite_bready : in STD_LOGIC; s_axi_lite_arvalid : in STD_LOGIC; s_axi_lite_arready : out STD_LOGIC; s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); s_axi_lite_rvalid : out STD_LOGIC; s_axi_lite_rready : in STD_LOGIC; s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_mm2s_arvalid : out STD_LOGIC; m_axi_mm2s_arready : in STD_LOGIC; m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_mm2s_rlast : in STD_LOGIC; m_axi_mm2s_rvalid : in STD_LOGIC; m_axi_mm2s_rready : out STD_LOGIC; mm2s_prmry_reset_out_n : out STD_LOGIC; m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_mm2s_tvalid : out STD_LOGIC; m_axis_mm2s_tready : in STD_LOGIC; m_axis_mm2s_tlast : out STD_LOGIC; m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_s2mm_awvalid : out STD_LOGIC; m_axi_s2mm_awready : in STD_LOGIC; m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_s2mm_wlast : out STD_LOGIC; m_axi_s2mm_wvalid : out STD_LOGIC; m_axi_s2mm_wready : in STD_LOGIC; m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_s2mm_bvalid : in STD_LOGIC; m_axi_s2mm_bready : out STD_LOGIC; s2mm_prmry_reset_out_n : out STD_LOGIC; s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_s2mm_tvalid : in STD_LOGIC; s_axis_s2mm_tready : out STD_LOGIC; s_axis_s2mm_tlast : in STD_LOGIC; mm2s_introut : out STD_LOGIC; s2mm_introut : out STD_LOGIC ); end component design_1_axi_dma_0_0; component design_1_rst_processing_system7_0_50M_0 is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end component design_1_rst_processing_system7_0_50M_0; component design_1_doHist_0_1 is port ( s_axi_CTRL_BUS_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_CTRL_BUS_AWVALID : in STD_LOGIC; s_axi_CTRL_BUS_AWREADY : out STD_LOGIC; s_axi_CTRL_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_CTRL_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_CTRL_BUS_WVALID : in STD_LOGIC; s_axi_CTRL_BUS_WREADY : out STD_LOGIC; s_axi_CTRL_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_CTRL_BUS_BVALID : out STD_LOGIC; s_axi_CTRL_BUS_BREADY : in STD_LOGIC; s_axi_CTRL_BUS_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_CTRL_BUS_ARVALID : in STD_LOGIC; s_axi_CTRL_BUS_ARREADY : out STD_LOGIC; s_axi_CTRL_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_CTRL_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_CTRL_BUS_RVALID : out STD_LOGIC; s_axi_CTRL_BUS_RREADY : in STD_LOGIC; ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; interrupt : out STD_LOGIC; inStream_TVALID : in STD_LOGIC; inStream_TREADY : out STD_LOGIC; inStream_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 ); inStream_TDEST : in STD_LOGIC_VECTOR ( 5 downto 0 ); inStream_TKEEP : in STD_LOGIC_VECTOR ( 0 to 0 ); inStream_TSTRB : in STD_LOGIC_VECTOR ( 0 to 0 ); inStream_TUSER : in STD_LOGIC_VECTOR ( 1 downto 0 ); inStream_TLAST : in STD_LOGIC_VECTOR ( 0 to 0 ); inStream_TID : in STD_LOGIC_VECTOR ( 4 downto 0 ); histo_Clk_A : out STD_LOGIC; histo_Rst_A : out STD_LOGIC; histo_EN_A : out STD_LOGIC; histo_WEN_A : out STD_LOGIC_VECTOR ( 3 downto 0 ); histo_Addr_A : out STD_LOGIC_VECTOR ( 31 downto 0 ); histo_Din_A : out STD_LOGIC_VECTOR ( 31 downto 0 ); histo_Dout_A : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); end component design_1_doHist_0_1; component design_1_axis_broadcaster_0_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axis_tvalid : in STD_LOGIC; s_axis_tready : out STD_LOGIC; s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_tlast : in STD_LOGIC; m_axis_tvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axis_tready : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); m_axis_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axis_tlast : out STD_LOGIC_VECTOR ( 1 downto 0 ) ); end component design_1_axis_broadcaster_0_0; component design_1_doHist_0_bram_0 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 3 downto 0 ); addra : in STD_LOGIC_VECTOR ( 31 downto 0 ); dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 3 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 31 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 31 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); end component design_1_doHist_0_bram_0; component design_1_axi_bram_ctrl_0_0 is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC; s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC; s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_clk_a : out STD_LOGIC; bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); end component design_1_axi_bram_ctrl_0_0; component design_1_axi_timer_0_0 is port ( capturetrig0 : in STD_LOGIC; capturetrig1 : in STD_LOGIC; generateout0 : out STD_LOGIC; generateout1 : out STD_LOGIC; pwm0 : out STD_LOGIC; interrupt : out STD_LOGIC; freeze : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC ); end component design_1_axi_timer_0_0; component design_1_doHistStretch_0_0 is port ( s_axi_CTRL_BUS_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_CTRL_BUS_AWVALID : in STD_LOGIC; s_axi_CTRL_BUS_AWREADY : out STD_LOGIC; s_axi_CTRL_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_CTRL_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_CTRL_BUS_WVALID : in STD_LOGIC; s_axi_CTRL_BUS_WREADY : out STD_LOGIC; s_axi_CTRL_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_CTRL_BUS_BVALID : out STD_LOGIC; s_axi_CTRL_BUS_BREADY : in STD_LOGIC; s_axi_CTRL_BUS_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_CTRL_BUS_ARVALID : in STD_LOGIC; s_axi_CTRL_BUS_ARREADY : out STD_LOGIC; s_axi_CTRL_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_CTRL_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_CTRL_BUS_RVALID : out STD_LOGIC; s_axi_CTRL_BUS_RREADY : in STD_LOGIC; ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; interrupt : out STD_LOGIC; inStream_TVALID : in STD_LOGIC; inStream_TREADY : out STD_LOGIC; inStream_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 ); inStream_TDEST : in STD_LOGIC_VECTOR ( 5 downto 0 ); inStream_TKEEP : in STD_LOGIC_VECTOR ( 0 to 0 ); inStream_TSTRB : in STD_LOGIC_VECTOR ( 0 to 0 ); inStream_TUSER : in STD_LOGIC_VECTOR ( 1 downto 0 ); inStream_TLAST : in STD_LOGIC_VECTOR ( 0 to 0 ); inStream_TID : in STD_LOGIC_VECTOR ( 4 downto 0 ); outStream_TVALID : out STD_LOGIC; outStream_TREADY : in STD_LOGIC; outStream_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 ); outStream_TDEST : out STD_LOGIC_VECTOR ( 5 downto 0 ); outStream_TKEEP : out STD_LOGIC_VECTOR ( 0 to 0 ); outStream_TSTRB : out STD_LOGIC_VECTOR ( 0 to 0 ); outStream_TUSER : out STD_LOGIC_VECTOR ( 1 downto 0 ); outStream_TLAST : out STD_LOGIC_VECTOR ( 0 to 0 ); outStream_TID : out STD_LOGIC_VECTOR ( 4 downto 0 ) ); end component design_1_doHistStretch_0_0; signal axi_bram_ctrl_0_BRAM_PORTA_ADDR : STD_LOGIC_VECTOR ( 12 downto 0 ); signal axi_bram_ctrl_0_BRAM_PORTA_CLK : STD_LOGIC; signal axi_bram_ctrl_0_BRAM_PORTA_DIN : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_bram_ctrl_0_BRAM_PORTA_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_bram_ctrl_0_BRAM_PORTA_EN : STD_LOGIC; signal axi_bram_ctrl_0_BRAM_PORTA_RST : STD_LOGIC; signal axi_bram_ctrl_0_BRAM_PORTA_WE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC; signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC; signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWREADY : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWVALID : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_BREADY : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_S2MM_BVALID : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_S2MM_WLAST : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_WREADY : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXI_S2MM_WVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 ); signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 ); signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC; signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC; signal axis_broadcaster_0_M00_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axis_broadcaster_0_M00_AXIS_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 ); signal axis_broadcaster_0_M00_AXIS_TLAST : STD_LOGIC_VECTOR ( 0 to 0 ); signal axis_broadcaster_0_M00_AXIS_TREADY : STD_LOGIC; signal axis_broadcaster_0_M00_AXIS_TVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal axis_broadcaster_0_M01_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 8 ); signal axis_broadcaster_0_M01_AXIS_TKEEP : STD_LOGIC_VECTOR ( 1 to 1 ); signal axis_broadcaster_0_M01_AXIS_TLAST : STD_LOGIC_VECTOR ( 1 to 1 ); signal axis_broadcaster_0_M01_AXIS_TREADY : STD_LOGIC; signal axis_broadcaster_0_M01_AXIS_TVALID : STD_LOGIC_VECTOR ( 1 to 1 ); signal doHistStretch_0_outStream_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); signal doHistStretch_0_outStream_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 ); signal doHistStretch_0_outStream_TLAST : STD_LOGIC_VECTOR ( 0 to 0 ); signal doHistStretch_0_outStream_TREADY : STD_LOGIC; signal doHistStretch_0_outStream_TVALID : STD_LOGIC; signal doHist_0_histo_PORTA_ADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal doHist_0_histo_PORTA_CLK : STD_LOGIC; signal doHist_0_histo_PORTA_DIN : STD_LOGIC_VECTOR ( 31 downto 0 ); signal doHist_0_histo_PORTA_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 ); signal doHist_0_histo_PORTA_EN : STD_LOGIC; signal doHist_0_histo_PORTA_RST : STD_LOGIC; signal doHist_0_histo_PORTA_WE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_DDR_CAS_N : STD_LOGIC; signal processing_system7_0_DDR_CKE : STD_LOGIC; signal processing_system7_0_DDR_CK_N : STD_LOGIC; signal processing_system7_0_DDR_CK_P : STD_LOGIC; signal processing_system7_0_DDR_CS_N : STD_LOGIC; signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_ODT : STD_LOGIC; signal processing_system7_0_DDR_RAS_N : STD_LOGIC; signal processing_system7_0_DDR_RESET_N : STD_LOGIC; signal processing_system7_0_DDR_WE_N : STD_LOGIC; signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC; signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_ARLOCK : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_AWLOCK : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_RLAST : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_WLAST : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_BREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M04_AXI_BVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M04_AXI_RREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M04_AXI_RVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M04_AXI_WREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_M04_AXI_WVALID : STD_LOGIC; signal rst_processing_system7_0_50M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); signal rst_processing_system7_0_50M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_axi_dma_0_mm2s_introut_UNCONNECTED : STD_LOGIC; signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC; signal NLW_axi_dma_0_s2mm_introut_UNCONNECTED : STD_LOGIC; signal NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC; signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC; signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC; signal NLW_axi_timer_0_interrupt_UNCONNECTED : STD_LOGIC; signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC; signal NLW_doHistStretch_0_interrupt_UNCONNECTED : STD_LOGIC; signal NLW_doHistStretch_0_outStream_TDEST_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_doHistStretch_0_outStream_TID_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_doHistStretch_0_outStream_TSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_doHistStretch_0_outStream_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_doHist_0_interrupt_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_rst_processing_system7_0_50M_mb_reset_UNCONNECTED : STD_LOGIC; signal NLW_rst_processing_system7_0_50M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_rst_processing_system7_0_50M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute BMM_INFO_ADDRESS_SPACE : string; attribute BMM_INFO_ADDRESS_SPACE of axi_bram_ctrl_0 : label is "byte 0x40000000 32 > design_1 doHist_0_bram"; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of axi_bram_ctrl_0 : label is "yes"; attribute BMM_INFO_PROCESSOR : string; attribute BMM_INFO_PROCESSOR of processing_system7_0 : label is "arm > design_1 axi_bram_ctrl_0"; attribute KEEP_HIERARCHY of processing_system7_0 : label is "yes"; begin axi_bram_ctrl_0: component design_1_axi_bram_ctrl_0_0 port map ( bram_addr_a(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0), bram_clk_a => axi_bram_ctrl_0_BRAM_PORTA_CLK, bram_en_a => axi_bram_ctrl_0_BRAM_PORTA_EN, bram_rddata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0), bram_rst_a => axi_bram_ctrl_0_BRAM_PORTA_RST, bram_we_a(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0), bram_wrdata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0), s_axi_aclk => processing_system7_0_FCLK_CLK0, s_axi_araddr(12 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(12 downto 0), s_axi_arburst(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARCACHE(3 downto 0), s_axi_aresetn => rst_processing_system7_0_50M_peripheral_aresetn(0), s_axi_arid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARID(11 downto 0), s_axi_arlen(7 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARLEN(7 downto 0), s_axi_arlock => processing_system7_0_axi_periph_M03_AXI_ARLOCK, s_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0), s_axi_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY, s_axi_arsize(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARSIZE(2 downto 0), s_axi_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID, s_axi_awaddr(12 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(12 downto 0), s_axi_awburst(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWID(11 downto 0), s_axi_awlen(7 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWLEN(7 downto 0), s_axi_awlock => processing_system7_0_axi_periph_M03_AXI_AWLOCK, s_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0), s_axi_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY, s_axi_awsize(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWSIZE(2 downto 0), s_axi_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID, s_axi_bid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_BID(11 downto 0), s_axi_bready => processing_system7_0_axi_periph_M03_AXI_BREADY, s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0), s_axi_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID, s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0), s_axi_rid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_RID(11 downto 0), s_axi_rlast => processing_system7_0_axi_periph_M03_AXI_RLAST, s_axi_rready => processing_system7_0_axi_periph_M03_AXI_RREADY, s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0), s_axi_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID, s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0), s_axi_wlast => processing_system7_0_axi_periph_M03_AXI_WLAST, s_axi_wready => processing_system7_0_axi_periph_M03_AXI_WREADY, s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0), s_axi_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID ); axi_dma_0: component design_1_axi_dma_0_0 port map ( axi_resetn => rst_processing_system7_0_50M_peripheral_aresetn(0), m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0, m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0), m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0), m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0), m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0), m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0), m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY, m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0), m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID, m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0), m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST, m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY, m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0), m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID, m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0, m_axi_s2mm_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0), m_axi_s2mm_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0), m_axi_s2mm_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0), m_axi_s2mm_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0), m_axi_s2mm_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0), m_axi_s2mm_awready => axi_dma_0_M_AXI_S2MM_AWREADY, m_axi_s2mm_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0), m_axi_s2mm_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID, m_axi_s2mm_bready => axi_dma_0_M_AXI_S2MM_BREADY, m_axi_s2mm_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0), m_axi_s2mm_bvalid => axi_dma_0_M_AXI_S2MM_BVALID, m_axi_s2mm_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0), m_axi_s2mm_wlast => axi_dma_0_M_AXI_S2MM_WLAST, m_axi_s2mm_wready => axi_dma_0_M_AXI_S2MM_WREADY, m_axi_s2mm_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0), m_axi_s2mm_wvalid => axi_dma_0_M_AXI_S2MM_WVALID, m_axis_mm2s_tdata(7 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(7 downto 0), m_axis_mm2s_tkeep(0) => axi_dma_0_M_AXIS_MM2S_TKEEP(0), m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST, m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY, m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID, mm2s_introut => NLW_axi_dma_0_mm2s_introut_UNCONNECTED, mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED, s2mm_introut => NLW_axi_dma_0_s2mm_introut_UNCONNECTED, s2mm_prmry_reset_out_n => NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED, s_axi_lite_aclk => processing_system7_0_FCLK_CLK0, s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0), s_axi_lite_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY, s_axi_lite_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID, s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0), s_axi_lite_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY, s_axi_lite_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID, s_axi_lite_bready => processing_system7_0_axi_periph_M00_AXI_BREADY, s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0), s_axi_lite_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID, s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0), s_axi_lite_rready => processing_system7_0_axi_periph_M00_AXI_RREADY, s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0), s_axi_lite_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID, s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0), s_axi_lite_wready => processing_system7_0_axi_periph_M00_AXI_WREADY, s_axi_lite_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID, s_axis_s2mm_tdata(7 downto 0) => doHistStretch_0_outStream_TDATA(7 downto 0), s_axis_s2mm_tkeep(0) => doHistStretch_0_outStream_TKEEP(0), s_axis_s2mm_tlast => doHistStretch_0_outStream_TLAST(0), s_axis_s2mm_tready => doHistStretch_0_outStream_TREADY, s_axis_s2mm_tvalid => doHistStretch_0_outStream_TVALID ); axi_mem_intercon: entity work.design_1_axi_mem_intercon_0 port map ( ACLK => processing_system7_0_FCLK_CLK0, ARESETN(0) => rst_processing_system7_0_50M_interconnect_aresetn(0), M00_ACLK => processing_system7_0_FCLK_CLK0, M00_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0), M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY, M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID, M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0), M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY, M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID, M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0), M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY, M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID, M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0), M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST, M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY, M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID, M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), M00_AXI_wid(0) => axi_mem_intercon_M00_AXI_WID(0), M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST, M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY, M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID, S00_ACLK => processing_system7_0_FCLK_CLK0, S00_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0), S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0), S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0), S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0), S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0), S00_AXI_arready => axi_dma_0_M_AXI_MM2S_ARREADY, S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0), S00_AXI_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID, S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0), S00_AXI_rlast => axi_dma_0_M_AXI_MM2S_RLAST, S00_AXI_rready => axi_dma_0_M_AXI_MM2S_RREADY, S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0), S00_AXI_rvalid => axi_dma_0_M_AXI_MM2S_RVALID, S01_ACLK => processing_system7_0_FCLK_CLK0, S01_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), S01_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0), S01_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0), S01_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0), S01_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0), S01_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0), S01_AXI_awready => axi_dma_0_M_AXI_S2MM_AWREADY, S01_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0), S01_AXI_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID, S01_AXI_bready => axi_dma_0_M_AXI_S2MM_BREADY, S01_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0), S01_AXI_bvalid => axi_dma_0_M_AXI_S2MM_BVALID, S01_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0), S01_AXI_wlast => axi_dma_0_M_AXI_S2MM_WLAST, S01_AXI_wready => axi_dma_0_M_AXI_S2MM_WREADY, S01_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0), S01_AXI_wvalid => axi_dma_0_M_AXI_S2MM_WVALID ); axi_timer_0: component design_1_axi_timer_0_0 port map ( capturetrig0 => '0', capturetrig1 => '0', freeze => '0', generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED, generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED, interrupt => NLW_axi_timer_0_interrupt_UNCONNECTED, pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED, s_axi_aclk => processing_system7_0_FCLK_CLK0, s_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(4 downto 0), s_axi_aresetn => rst_processing_system7_0_50M_peripheral_aresetn(0), s_axi_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY, s_axi_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID, s_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(4 downto 0), s_axi_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY, s_axi_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID, s_axi_bready => processing_system7_0_axi_periph_M04_AXI_BREADY, s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0), s_axi_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID, s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0), s_axi_rready => processing_system7_0_axi_periph_M04_AXI_RREADY, s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0), s_axi_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID, s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0), s_axi_wready => processing_system7_0_axi_periph_M04_AXI_WREADY, s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0), s_axi_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID ); axis_broadcaster_0: component design_1_axis_broadcaster_0_0 port map ( aclk => processing_system7_0_FCLK_CLK0, aresetn => rst_processing_system7_0_50M_peripheral_aresetn(0), m_axis_tdata(15 downto 8) => axis_broadcaster_0_M01_AXIS_TDATA(15 downto 8), m_axis_tdata(7 downto 0) => axis_broadcaster_0_M00_AXIS_TDATA(7 downto 0), m_axis_tkeep(1) => axis_broadcaster_0_M01_AXIS_TKEEP(1), m_axis_tkeep(0) => axis_broadcaster_0_M00_AXIS_TKEEP(0), m_axis_tlast(1) => axis_broadcaster_0_M01_AXIS_TLAST(1), m_axis_tlast(0) => axis_broadcaster_0_M00_AXIS_TLAST(0), m_axis_tready(1) => axis_broadcaster_0_M01_AXIS_TREADY, m_axis_tready(0) => axis_broadcaster_0_M00_AXIS_TREADY, m_axis_tvalid(1) => axis_broadcaster_0_M01_AXIS_TVALID(1), m_axis_tvalid(0) => axis_broadcaster_0_M00_AXIS_TVALID(0), s_axis_tdata(7 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(7 downto 0), s_axis_tkeep(0) => axi_dma_0_M_AXIS_MM2S_TKEEP(0), s_axis_tlast => axi_dma_0_M_AXIS_MM2S_TLAST, s_axis_tready => axi_dma_0_M_AXIS_MM2S_TREADY, s_axis_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID ); doHistStretch_0: component design_1_doHistStretch_0_0 port map ( ap_clk => processing_system7_0_FCLK_CLK0, ap_rst_n => rst_processing_system7_0_50M_peripheral_aresetn(0), inStream_TDATA(7 downto 0) => axis_broadcaster_0_M01_AXIS_TDATA(15 downto 8), inStream_TDEST(5 downto 0) => B"000000", inStream_TID(4 downto 0) => B"00000", inStream_TKEEP(0) => axis_broadcaster_0_M01_AXIS_TKEEP(1), inStream_TLAST(0) => axis_broadcaster_0_M01_AXIS_TLAST(1), inStream_TREADY => axis_broadcaster_0_M01_AXIS_TREADY, inStream_TSTRB(0) => '1', inStream_TUSER(1 downto 0) => B"00", inStream_TVALID => axis_broadcaster_0_M01_AXIS_TVALID(1), interrupt => NLW_doHistStretch_0_interrupt_UNCONNECTED, outStream_TDATA(7 downto 0) => doHistStretch_0_outStream_TDATA(7 downto 0), outStream_TDEST(5 downto 0) => NLW_doHistStretch_0_outStream_TDEST_UNCONNECTED(5 downto 0), outStream_TID(4 downto 0) => NLW_doHistStretch_0_outStream_TID_UNCONNECTED(4 downto 0), outStream_TKEEP(0) => doHistStretch_0_outStream_TKEEP(0), outStream_TLAST(0) => doHistStretch_0_outStream_TLAST(0), outStream_TREADY => doHistStretch_0_outStream_TREADY, outStream_TSTRB(0) => NLW_doHistStretch_0_outStream_TSTRB_UNCONNECTED(0), outStream_TUSER(1 downto 0) => NLW_doHistStretch_0_outStream_TUSER_UNCONNECTED(1 downto 0), outStream_TVALID => doHistStretch_0_outStream_TVALID, s_axi_CTRL_BUS_ARADDR(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(4 downto 0), s_axi_CTRL_BUS_ARREADY => processing_system7_0_axi_periph_M01_AXI_ARREADY, s_axi_CTRL_BUS_ARVALID => processing_system7_0_axi_periph_M01_AXI_ARVALID, s_axi_CTRL_BUS_AWADDR(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(4 downto 0), s_axi_CTRL_BUS_AWREADY => processing_system7_0_axi_periph_M01_AXI_AWREADY, s_axi_CTRL_BUS_AWVALID => processing_system7_0_axi_periph_M01_AXI_AWVALID, s_axi_CTRL_BUS_BREADY => processing_system7_0_axi_periph_M01_AXI_BREADY, s_axi_CTRL_BUS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0), s_axi_CTRL_BUS_BVALID => processing_system7_0_axi_periph_M01_AXI_BVALID, s_axi_CTRL_BUS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0), s_axi_CTRL_BUS_RREADY => processing_system7_0_axi_periph_M01_AXI_RREADY, s_axi_CTRL_BUS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0), s_axi_CTRL_BUS_RVALID => processing_system7_0_axi_periph_M01_AXI_RVALID, s_axi_CTRL_BUS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0), s_axi_CTRL_BUS_WREADY => processing_system7_0_axi_periph_M01_AXI_WREADY, s_axi_CTRL_BUS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0), s_axi_CTRL_BUS_WVALID => processing_system7_0_axi_periph_M01_AXI_WVALID ); doHist_0: component design_1_doHist_0_1 port map ( ap_clk => processing_system7_0_FCLK_CLK0, ap_rst_n => rst_processing_system7_0_50M_peripheral_aresetn(0), histo_Addr_A(31 downto 0) => doHist_0_histo_PORTA_ADDR(31 downto 0), histo_Clk_A => doHist_0_histo_PORTA_CLK, histo_Din_A(31 downto 0) => doHist_0_histo_PORTA_DIN(31 downto 0), histo_Dout_A(31 downto 0) => doHist_0_histo_PORTA_DOUT(31 downto 0), histo_EN_A => doHist_0_histo_PORTA_EN, histo_Rst_A => doHist_0_histo_PORTA_RST, histo_WEN_A(3 downto 0) => doHist_0_histo_PORTA_WE(3 downto 0), inStream_TDATA(7 downto 0) => axis_broadcaster_0_M00_AXIS_TDATA(7 downto 0), inStream_TDEST(5 downto 0) => B"000000", inStream_TID(4 downto 0) => B"00000", inStream_TKEEP(0) => axis_broadcaster_0_M00_AXIS_TKEEP(0), inStream_TLAST(0) => axis_broadcaster_0_M00_AXIS_TLAST(0), inStream_TREADY => axis_broadcaster_0_M00_AXIS_TREADY, inStream_TSTRB(0) => '1', inStream_TUSER(1 downto 0) => B"00", inStream_TVALID => axis_broadcaster_0_M00_AXIS_TVALID(0), interrupt => NLW_doHist_0_interrupt_UNCONNECTED, s_axi_CTRL_BUS_ARADDR(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(3 downto 0), s_axi_CTRL_BUS_ARREADY => processing_system7_0_axi_periph_M02_AXI_ARREADY, s_axi_CTRL_BUS_ARVALID => processing_system7_0_axi_periph_M02_AXI_ARVALID, s_axi_CTRL_BUS_AWADDR(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(3 downto 0), s_axi_CTRL_BUS_AWREADY => processing_system7_0_axi_periph_M02_AXI_AWREADY, s_axi_CTRL_BUS_AWVALID => processing_system7_0_axi_periph_M02_AXI_AWVALID, s_axi_CTRL_BUS_BREADY => processing_system7_0_axi_periph_M02_AXI_BREADY, s_axi_CTRL_BUS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0), s_axi_CTRL_BUS_BVALID => processing_system7_0_axi_periph_M02_AXI_BVALID, s_axi_CTRL_BUS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0), s_axi_CTRL_BUS_RREADY => processing_system7_0_axi_periph_M02_AXI_RREADY, s_axi_CTRL_BUS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0), s_axi_CTRL_BUS_RVALID => processing_system7_0_axi_periph_M02_AXI_RVALID, s_axi_CTRL_BUS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0), s_axi_CTRL_BUS_WREADY => processing_system7_0_axi_periph_M02_AXI_WREADY, s_axi_CTRL_BUS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0), s_axi_CTRL_BUS_WVALID => processing_system7_0_axi_periph_M02_AXI_WVALID ); doHist_0_bram: component design_1_doHist_0_bram_0 port map ( addra(31 downto 0) => doHist_0_histo_PORTA_ADDR(31 downto 0), addrb(31 downto 13) => B"0000000000000000000", addrb(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0), clka => doHist_0_histo_PORTA_CLK, clkb => axi_bram_ctrl_0_BRAM_PORTA_CLK, dina(31 downto 0) => doHist_0_histo_PORTA_DIN(31 downto 0), dinb(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0), douta(31 downto 0) => doHist_0_histo_PORTA_DOUT(31 downto 0), doutb(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0), ena => doHist_0_histo_PORTA_EN, enb => axi_bram_ctrl_0_BRAM_PORTA_EN, rsta => doHist_0_histo_PORTA_RST, rstb => axi_bram_ctrl_0_BRAM_PORTA_RST, wea(3 downto 0) => doHist_0_histo_PORTA_WE(3 downto 0), web(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0) ); processing_system7_0: component design_1_processing_system7_0_0 port map ( DDR_Addr(14 downto 0) => DDR_addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0), DDR_CAS_n => DDR_cas_n, DDR_CKE => DDR_cke, DDR_CS_n => DDR_cs_n, DDR_Clk => DDR_ck_p, DDR_Clk_n => DDR_ck_n, DDR_DM(3 downto 0) => DDR_dm(3 downto 0), DDR_DQ(31 downto 0) => DDR_dq(31 downto 0), DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_DRSTB => DDR_reset_n, DDR_ODT => DDR_odt, DDR_RAS_n => DDR_ras_n, DDR_VRN => FIXED_IO_ddr_vrn, DDR_VRP => FIXED_IO_ddr_vrp, DDR_WEB => DDR_we_n, FCLK_CLK0 => processing_system7_0_FCLK_CLK0, FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N, MIO(53 downto 0) => FIXED_IO_mio(53 downto 0), M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0, M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID, PS_CLK => FIXED_IO_ps_clk, PS_PORB => FIXED_IO_ps_porb, PS_SRSTB => FIXED_IO_ps_srstb, S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0, S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), S_AXI_HP0_ARID(5 downto 1) => B"00000", S_AXI_HP0_ARID(0) => axi_mem_intercon_M00_AXI_ARID(0), S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY, S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID, S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), S_AXI_HP0_AWID(5 downto 1) => B"00000", S_AXI_HP0_AWID(0) => axi_mem_intercon_M00_AXI_AWID(0), S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY, S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID, S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0), S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY, S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0), S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST, S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY, S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), S_AXI_HP0_WID(5 downto 1) => B"00000", S_AXI_HP0_WID(0) => axi_mem_intercon_M00_AXI_WID(0), S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST, S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY, S_AXI_HP0_WRISSUECAP1_EN => '0', S_AXI_HP0_WSTRB(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID, TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), USB0_VBUS_PWRFAULT => '0', USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED ); processing_system7_0_axi_periph: entity work.design_1_processing_system7_0_axi_periph_0 port map ( ACLK => processing_system7_0_FCLK_CLK0, ARESETN(0) => rst_processing_system7_0_50M_interconnect_aresetn(0), M00_ACLK => processing_system7_0_FCLK_CLK0, M00_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0), M00_AXI_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY, M00_AXI_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID, M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0), M00_AXI_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY, M00_AXI_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID, M00_AXI_bready => processing_system7_0_axi_periph_M00_AXI_BREADY, M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0), M00_AXI_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID, M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0), M00_AXI_rready => processing_system7_0_axi_periph_M00_AXI_RREADY, M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0), M00_AXI_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID, M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0), M00_AXI_wready => processing_system7_0_axi_periph_M00_AXI_WREADY, M00_AXI_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID, M01_ACLK => processing_system7_0_FCLK_CLK0, M01_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0), M01_AXI_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY, M01_AXI_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID, M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0), M01_AXI_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY, M01_AXI_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID, M01_AXI_bready => processing_system7_0_axi_periph_M01_AXI_BREADY, M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0), M01_AXI_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID, M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0), M01_AXI_rready => processing_system7_0_axi_periph_M01_AXI_RREADY, M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0), M01_AXI_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID, M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0), M01_AXI_wready => processing_system7_0_axi_periph_M01_AXI_WREADY, M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0), M01_AXI_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID, M02_ACLK => processing_system7_0_FCLK_CLK0, M02_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), M02_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(31 downto 0), M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY, M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID, M02_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(31 downto 0), M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY, M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID, M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY, M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0), M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID, M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0), M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY, M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0), M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID, M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0), M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY, M02_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0), M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID, M03_ACLK => processing_system7_0_FCLK_CLK0, M03_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), M03_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(31 downto 0), M03_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARBURST(1 downto 0), M03_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARCACHE(3 downto 0), M03_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARID(11 downto 0), M03_AXI_arlen(7 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARLEN(7 downto 0), M03_AXI_arlock => processing_system7_0_axi_periph_M03_AXI_ARLOCK, M03_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0), M03_AXI_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY, M03_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARSIZE(2 downto 0), M03_AXI_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID, M03_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(31 downto 0), M03_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWBURST(1 downto 0), M03_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWCACHE(3 downto 0), M03_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWID(11 downto 0), M03_AXI_awlen(7 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWLEN(7 downto 0), M03_AXI_awlock => processing_system7_0_axi_periph_M03_AXI_AWLOCK, M03_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0), M03_AXI_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY, M03_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWSIZE(2 downto 0), M03_AXI_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID, M03_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_BID(11 downto 0), M03_AXI_bready => processing_system7_0_axi_periph_M03_AXI_BREADY, M03_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0), M03_AXI_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID, M03_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0), M03_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_RID(11 downto 0), M03_AXI_rlast => processing_system7_0_axi_periph_M03_AXI_RLAST, M03_AXI_rready => processing_system7_0_axi_periph_M03_AXI_RREADY, M03_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0), M03_AXI_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID, M03_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0), M03_AXI_wlast => processing_system7_0_axi_periph_M03_AXI_WLAST, M03_AXI_wready => processing_system7_0_axi_periph_M03_AXI_WREADY, M03_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0), M03_AXI_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID, M04_ACLK => processing_system7_0_FCLK_CLK0, M04_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), M04_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(31 downto 0), M04_AXI_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY, M04_AXI_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID, M04_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(31 downto 0), M04_AXI_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY, M04_AXI_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID, M04_AXI_bready => processing_system7_0_axi_periph_M04_AXI_BREADY, M04_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0), M04_AXI_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID, M04_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0), M04_AXI_rready => processing_system7_0_axi_periph_M04_AXI_RREADY, M04_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0), M04_AXI_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID, M04_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0), M04_AXI_wready => processing_system7_0_axi_periph_M04_AXI_WREADY, M04_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0), M04_AXI_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID, S00_ACLK => processing_system7_0_FCLK_CLK0, S00_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY, S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID, S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY, S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID, S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY, S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID, S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST, S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY, S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID, S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST, S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY, S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID ); rst_processing_system7_0_50M: component design_1_rst_processing_system7_0_50M_0 port map ( aux_reset_in => '1', bus_struct_reset(0) => NLW_rst_processing_system7_0_50M_bus_struct_reset_UNCONNECTED(0), dcm_locked => '1', ext_reset_in => processing_system7_0_FCLK_RESET0_N, interconnect_aresetn(0) => rst_processing_system7_0_50M_interconnect_aresetn(0), mb_debug_sys_rst => '0', mb_reset => NLW_rst_processing_system7_0_50M_mb_reset_UNCONNECTED, peripheral_aresetn(0) => rst_processing_system7_0_50M_peripheral_aresetn(0), peripheral_reset(0) => NLW_rst_processing_system7_0_50M_peripheral_reset_UNCONNECTED(0), slowest_sync_clk => processing_system7_0_FCLK_CLK0 ); end STRUCTURE;
gpl-3.0
b78a17476e349f6347de51841bc69ed7
0.675328
2.816525
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_queue.vhd
7
53,326
-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_queue.vhd -- Description: This entity is the descriptor fetch queue interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1_2; use axi_sg_v4_1_2.axi_sg_pkg.all; library lib_srl_fifo_v1_0_2; use lib_srl_fifo_v1_0_2.srl_fifo_f; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_queue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_SG2_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_INCLUDE_MM2S : integer range 0 to 1 := 0; C_INCLUDE_S2MM : integer range 0 to 1 := 0; C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- s_axis_updt_aclk : in std_logic ; -- -- --********************************-- -- --** Control and Status **-- -- --********************************-- -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- updt2_active : in std_logic ; -- updt2_queue_empty : out std_logic ; -- updt2_ioc : out std_logic ; -- updt2_ioc_irq_set : in std_logic ; -- -- dma2_interr : out std_logic ; -- dma2_slverr : out std_logic ; -- dma2_decerr : out std_logic ; -- dma2_interr_set : in std_logic ; -- dma2_slverr_set : in std_logic ; -- dma2_decerr_set : in std_logic ; -- -- --********************************-- -- --** Update Interfaces In **-- -- --********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- s_axis2_updtptr_tdata : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- s_axis2_updtptr_tvalid : in std_logic ; -- s_axis2_updtptr_tready : out std_logic ; -- s_axis2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis2_updtsts_tvalid : in std_logic ; -- s_axis2_updtsts_tready : out std_logic ; -- s_axis2_updtsts_tlast : in std_logic ; -- -- --********************************-- -- --** Update Interfaces Out **-- -- --********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_queue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_queue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs -- Number of words deep fifo needs to be. Depth required to store 2 word -- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2 --constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2); constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2)); -- Width of fifo rd and wr counts - only used for proper fifo operation constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1); -- Select between BRAM or LOGIC memory type constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16); -- Number of words deep fifo needs to be. Depth required to store all update -- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * C_SG_WORDS_TO_UPDATE)); constant UPDATE_STS2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * C_SG2_WORDS_TO_UPDATE)); -- Select between BRAM or LOGIC memory type constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16); -- Select between BRAM or LOGIC memory type constant STS2_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS2_QUEUE_DEPTH > 16); -- Width of fifo rd and wr counts - only used for proper fifo operation constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_lsb_sm : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal write_curdesc_lsb1 : std_logic := '0'; signal write_curdesc_msb1 : std_logic := '0'; signal rden_del : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_d2 : std_logic := '0'; signal updt_active_re1 : std_logic := '0'; signal updt_active_re2 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; -- State Machine Signal signal writing_status : std_logic := '0'; signal dataq_rden : std_logic := '0'; signal stsq_rden : std_logic := '0'; -- Pointer Queue FIFO Signals signal ptr_queue_rden : std_logic := '0'; signal ptr_queue_wren : std_logic := '0'; signal ptr_queue_empty : std_logic := '0'; signal ptr_queue_full : std_logic := '0'; signal ptr_queue_din : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ptr_queue_dout : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ptr_queue_dout_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); -- Status Queue FIFO Signals signal sts_queue_wren : std_logic := '0'; signal sts_queue_rden : std_logic := '0'; signal sts_queue_din : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts_queue_dout : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts_queue_dout_int : std_logic_vector (3 downto 0) := (others => '0'); signal sts_queue_full : std_logic := '0'; signal sts_queue_empty : std_logic := '0'; signal ptr2_queue_rden : std_logic := '0'; signal ptr2_queue_wren : std_logic := '0'; signal ptr2_queue_empty : std_logic := '0'; signal ptr2_queue_full : std_logic := '0'; signal ptr2_queue_din : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ptr2_queue_dout : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); -- Status Queue FIFO Signals signal sts2_queue_wren : std_logic := '0'; signal sts2_queue_rden : std_logic := '0'; signal sts2_queue_din : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts2_queue_dout : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts2_queue_full : std_logic := '0'; signal sts2_queue_empty : std_logic := '0'; signal sts2_queue_empty_del : std_logic := '0'; signal sts2_dout_valid : std_logic := '0'; signal sts_dout_valid : std_logic := '0'; signal sts2_dout_valid_del : std_logic := '0'; signal valid_new : std_logic := '0'; signal valid_latch : std_logic := '0'; signal valid1_new : std_logic := '0'; signal valid1_latch : std_logic := '0'; signal empty_low : std_logic := '0'; -- Misc Support Signals signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; signal writing_status_re_ch1 : std_logic := '0'; signal writing_status_re_ch2 : std_logic := '0'; signal sinit : std_logic := '0'; signal updt_tvalid : std_logic := '0'; signal updt_tlast : std_logic := '0'; signal updt2_tvalid : std_logic := '0'; signal updt2_tlast : std_logic := '0'; signal status_d1, status_d2 : std_logic := '0'; signal updt_tvalid_int : std_logic := '0'; signal updt_tlast_int : std_logic := '0'; signal ptr_queue_empty_int : std_logic := '0'; signal updt_active_int : std_logic := '0'; signal follower_reg_mm2s : std_logic_vector (33 downto 0) := (others => '0'); signal follower_full_mm2s :std_logic := '0'; signal follower_empty_mm2s : std_logic := '0'; signal follower_reg_s2mm : std_logic_vector (33 downto 0) := (others => '0'); signal follower_full_s2mm :std_logic := '0'; signal follower_empty_s2mm : std_logic := '0'; signal follower_reg, m_axis_updt_tdata_tmp : std_logic_vector (33 downto 0); signal follower_full :std_logic := '0'; signal follower_empty : std_logic := '0'; signal sts_rden : std_logic := '0'; signal sts2_rden : std_logic := '0'; signal follower_tlast : std_logic := '0'; signal follower_reg_image : std_logic := '0'; signal m_axis_updt_tready_mm2s, m_axis_updt_tready_s2mm : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin m_axis_updt_tdata <= follower_reg_mm2s (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) when updt_active = '1' else follower_reg_s2mm (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) ; m_axis_updt_tvalid <= updt_tvalid when updt_active = '1' else updt2_tvalid; m_axis_updt_tlast <= updt_tlast when updt_active = '1' else updt2_tlast; m_axis_updt_tready_mm2s <= m_axis_updt_tready when updt_active = '1' else '0'; m_axis_updt_tready_s2mm <= m_axis_updt_tready when updt2_active = '1' else '0'; -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- channel 1 updt_active_re <= updt_active_re1 or updt_active_re2; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active_re, ptr_queue_empty_int, m_axis_updt_tready, updt_tvalid_int, updt_tlast_int) begin write_curdesc_lsb_sm <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; dataq_rden <= '0'; stsq_rden <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if(updt_active_re = '1')then pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor pointer -- Reads one word from data queue fifo --------------------------------------------------------------- when READ_CURDESC_LSB => -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(ptr_queue_empty_int = '0')then write_curdesc_lsb_sm <= '1'; dataq_rden <= '1'; -- pntr_ns <= READ_CURDESC_MSB; pntr_ns <= WRITE_STATUS; --READ_CURDESC_MSB; else -- coverage off pntr_ns <= READ_CURDESC_LSB; -- coverage on end if; --------------------------------------------------------------- -- Get upper current descriptor -- Reads one word from data queue fifo --------------------------------------------------------------- -- when READ_CURDESC_MSB => -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. -- if(ptr_queue_empty_int = '0')then -- dataq_rden <= '1'; -- write_curdesc_msb <= '1'; -- pntr_ns <= WRITE_STATUS; -- else -- -- coverage off -- pntr_ns <= READ_CURDESC_MSB; -- -- coverage on -- end if; --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => -- De-MUX appropriage tvalid/tlast signals writing_status <= '1'; -- Enable reading of Status Queue if datamover can -- accept data stsq_rden <= m_axis_updt_tready; -- Hold in the status state until tlast is pulled -- from status fifo if(updt_tvalid_int = '1' and m_axis_updt_tready = '1' and updt_tlast_int = '1')then -- if(follower_full = '1' and m_axis_updt_tready = '1' -- and follower_tlast = '1')then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; -- coverage off when others => pntr_ns <= IDLE; -- coverage on end case; end process CURDESC_PNTR_STATE; updt_tvalid_int <= updt_tvalid or updt2_tvalid; updt_tlast_int <= updt_tlast or updt2_tlast; ptr_queue_empty_int <= ptr_queue_empty when updt_active = '1' else ptr2_queue_empty when updt2_active = '1' else '1'; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate begin MM2S_CHANNEL : if C_INCLUDE_MM2S = 1 generate updt_tvalid <= follower_full_mm2s and updt_active; updt_tlast <= follower_reg_mm2s(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt_active; sts_rden <= follower_empty_mm2s and (not sts_queue_empty); -- and updt_active; VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_mm2s = '1' and follower_full_mm2s = '1'))then -- follower_reg_mm2s <= (others => '0'); follower_full_mm2s <= '0'; follower_empty_mm2s <= '1'; else if (sts_rden = '1') then -- follower_reg_mm2s <= sts_queue_dout; follower_full_mm2s <= '1'; follower_empty_mm2s <= '0'; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE; VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then follower_reg_mm2s <= (others => '0'); else if (sts_rden = '1') then follower_reg_mm2s <= sts_queue_dout; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE1; REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active; end if; end if; end process REG_ACTIVE; updt_active_re1 <= updt_active and not updt_active_d1; -- I_UPDT_DATA_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f -- generic map ( -- C_DWIDTH => 32 , -- C_DEPTH => 8 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => ptr_queue_wren , -- Data_In => ptr_queue_din , -- FIFO_Read => ptr_queue_rden , -- Data_Out => ptr_queue_dout , -- FIFO_Empty => ptr_queue_empty , -- FIFO_Full => ptr_queue_full, -- Addr => open -- ); process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then ptr_queue_dout <= (others => '0'); elsif (ptr_queue_wren = '1') then ptr_queue_dout <= ptr_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or ptr_queue_rden = '1') then ptr_queue_empty <= '1'; ptr_queue_full <= '0'; elsif (ptr_queue_wren = '1') then ptr_queue_empty <= '0'; ptr_queue_full <= '1'; end if; end if; end process; -- Channel Pointer Queue (Generate Synchronous FIFO) -- I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f -- generic map ( -- C_DWIDTH => 34 , -- C_DEPTH => 4 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => sts_queue_wren , -- Data_In => sts_queue_din , -- FIFO_Read => sts_rden, --sts_queue_rden , -- Data_Out => sts_queue_dout , -- FIFO_Empty => sts_queue_empty , -- FIFO_Full => sts_queue_full , -- Addr => open -- ); process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then sts_queue_dout <= (others => '0'); elsif (sts_queue_wren = '1') then sts_queue_dout <= sts_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or sts_rden = '1') then sts_queue_empty <= '1'; sts_queue_full <= '0'; elsif (sts_queue_wren = '1') then sts_queue_empty <= '0'; sts_queue_full <= '1'; end if; end if; end process; -- Channel Status Queue (Generate Synchronous FIFO) --***************************************** --** Channel Data Port Side of Queues --***************************************** -- Pointer Queue Update - Descriptor Pointer (32bits) -- i.e. 2 current descriptor pointers and any app fields ptr_queue_din(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- Data Queue Write Enable - based on tvalid and queue not full ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid and not ptr_queue_full; -- Data Queue NOT Full -- Drive channel port with ready if room in data queue s_axis_updtptr_tready <= not ptr_queue_full; --***************************************** --** Channel Status Port Side of Queues --***************************************** -- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits) -- Note: Type field is stripped off sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- Status Queue Write Enable - based on tvalid and queue not full sts_queue_wren <= s_axis_updtsts_tvalid and not sts_queue_full; -- Drive channel port with ready if room in status queue s_axis_updtsts_tready <= not sts_queue_full; --************************************* --** SG Engine Side of Queues --************************************* -- Indicate NOT empty if both status queue and data queue are not empty -- updt_queue_empty <= ptr_queue_empty -- or (sts_queue_empty and follower_empty and updt_active); updt_queue_empty <= ptr_queue_empty or follower_empty_mm2s; -- and updt_active); -- Data queue read enable ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable and ptr_queue_empty = '0' -- Data Queue NOT empty and updt_active = '1' else '0'; -- Status queue read enable sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status and sts_queue_empty = '0' -- Status fifo NOT empty and updt_active = '1' else '0'; ----------------------------------------------------------------------- -- TVALID - status queue not empty and writing status ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- TLAST - status queue not empty, writing status, and last asserted ----------------------------------------------------------------------- -- Drive last as long as tvalid is asserted and last from fifo -- is asserted end generate MM2S_CHANNEL; NO_MM2S_CHANNEL : if C_INCLUDE_MM2S = 0 generate begin updt_active_re1 <= '0'; updt_queue_empty <= '0'; s_axis_updtptr_tready <= '0'; s_axis_updtsts_tready <= '0'; sts_queue_dout <= (others => '0'); sts_queue_full <= '0'; sts_queue_empty <= '0'; ptr_queue_dout <= (others => '0'); ptr_queue_empty <= '0'; ptr_queue_full <= '0'; end generate NO_MM2S_CHANNEL; S2MM_CHANNEL : if C_INCLUDE_S2MM = 1 generate begin updt2_tvalid <= follower_full_s2mm and updt2_active; updt2_tlast <= follower_reg_s2mm(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt2_active; sts2_rden <= follower_empty_s2mm and (not sts2_queue_empty); -- and updt2_active; VALID_REG_S2MM_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_s2mm = '1' and follower_full_s2mm = '1'))then -- follower_reg_s2mm <= (others => '0'); follower_full_s2mm <= '0'; follower_empty_s2mm <= '1'; else if (sts2_rden = '1') then -- follower_reg_s2mm <= sts2_queue_dout; follower_full_s2mm <= '1'; follower_empty_s2mm <= '0'; end if; end if; end if; end process VALID_REG_S2MM_ACTIVE; VALID_REG_S2MM_ACTIVE1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then follower_reg_s2mm <= (others => '0'); else if (sts2_rden = '1') then follower_reg_s2mm <= sts2_queue_dout; end if; end if; end if; end process VALID_REG_S2MM_ACTIVE1; REG2_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_active_d2 <= '0'; else updt_active_d2 <= updt2_active; end if; end if; end process REG2_ACTIVE; updt_active_re2 <= updt2_active and not updt_active_d2; -- I_UPDT2_DATA_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f -- generic map ( -- C_DWIDTH => 32 , -- C_DEPTH => 8 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => ptr2_queue_wren , -- Data_In => ptr2_queue_din , -- FIFO_Read => ptr2_queue_rden , -- Data_Out => ptr2_queue_dout , -- FIFO_Empty => ptr2_queue_empty , -- FIFO_Full => ptr2_queue_full, -- Addr => open -- ); process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then ptr2_queue_dout <= (others => '0'); elsif (ptr2_queue_wren = '1') then ptr2_queue_dout <= ptr2_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or ptr2_queue_rden = '1') then ptr2_queue_empty <= '1'; ptr2_queue_full <= '0'; elsif (ptr2_queue_wren = '1') then ptr2_queue_empty <= '0'; ptr2_queue_full <= '1'; end if; end if; end process; APP_UPDATE: if C_SG2_WORDS_TO_UPDATE /= 1 generate begin I_UPDT2_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f generic map ( C_DWIDTH => 34 , C_DEPTH => 12 , C_FAMILY => C_FAMILY ) port map ( Clk => m_axi_sg_aclk , Reset => sinit , FIFO_Write => sts2_queue_wren , Data_In => sts2_queue_din , FIFO_Read => sts2_rden, Data_Out => sts2_queue_dout , FIFO_Empty => sts2_queue_empty , FIFO_Full => sts2_queue_full , Addr => open ); end generate APP_UPDATE; NO_APP_UPDATE: if C_SG2_WORDS_TO_UPDATE = 1 generate begin process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then sts2_queue_dout <= (others => '0'); elsif (sts2_queue_wren = '1') then sts2_queue_dout <= sts2_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or sts2_rden = '1') then sts2_queue_empty <= '1'; sts2_queue_full <= '0'; elsif (sts2_queue_wren = '1') then sts2_queue_empty <= '0'; sts2_queue_full <= '1'; end if; end if; end process; end generate NO_APP_UPDATE; -- Pointer Queue Update - Descriptor Pointer (32bits) -- i.e. 2 current descriptor pointers and any app fields ptr2_queue_din(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) <= s_axis2_updtptr_tdata( -- DESC DATA C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- Data Queue Write Enable - based on tvalid and queue not full ptr2_queue_wren <= s_axis2_updtptr_tvalid -- TValid and not ptr2_queue_full; -- Data Queue NOT Full -- Drive channel port with ready if room in data queue s_axis2_updtptr_tready <= not ptr2_queue_full; --***************************************** --** Channel Status Port Side of Queues --***************************************** -- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits) -- Note: Type field is stripped off sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis2_updtsts_tlast; -- Store with tlast sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis2_updtsts_tdata( -- IOC & DESC STS C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- Status Queue Write Enable - based on tvalid and queue not full sts2_queue_wren <= s_axis2_updtsts_tvalid and not sts2_queue_full; -- Drive channel port with ready if room in status queue s_axis2_updtsts_tready <= not sts2_queue_full; --************************************* --** SG Engine Side of Queues --************************************* -- Indicate NOT empty if both status queue and data queue are not empty updt2_queue_empty <= ptr2_queue_empty or follower_empty_s2mm; --or (sts2_queue_empty and follower_empty and updt2_active); -- Data queue read enable ptr2_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable and ptr2_queue_empty = '0' -- Data Queue NOT empty and updt2_active = '1' else '0'; -- Status queue read enable sts2_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status and sts2_queue_empty = '0' -- Status fifo NOT empty and updt2_active = '1' else '0'; end generate S2MM_CHANNEL; NO_S2MM_CHANNEL : if C_INCLUDE_S2MM = 0 generate begin updt_active_re2 <= '0'; updt2_queue_empty <= '0'; s_axis2_updtptr_tready <= '0'; s_axis2_updtsts_tready <= '0'; sts2_queue_dout <= (others => '0'); sts2_queue_full <= '0'; sts2_queue_empty <= '0'; ptr2_queue_dout <= (others => '0'); ptr2_queue_empty <= '0'; ptr2_queue_full <= '0'; end generate NO_S2MM_CHANNEL; end generate GEN_Q_FOR_SYNC; -- FIFO Reset is active high sinit <= not m_axi_sg_aresetn; -- LSB_PROC : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' )then -- write_curdesc_lsb <= '0'; -- -- Capture lower pointer from FIFO or channel port -- else -- if(write_curdesc_lsb = '1' and updt_active_int = '1')then write_curdesc_lsb <= write_curdesc_lsb_sm; -- end if; -- end if; -- end process LSB_PROC; --********************************************************************* --** POINTER CAPTURE LOGIC --********************************************************************* ptr_queue_dout_int <= ptr2_queue_dout when (updt2_active = '1') else ptr_queue_dout; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- updt_active_int <= updt_active or updt2_active; REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then updt_curdesc(31 downto 0) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0'); -- updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then updt_curdesc(C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= ptr_queue_dout_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32); -- updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else -- updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then --elsif(write_curdesc_msb = '1' and updt_active_int = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; --********************************************************************* --** ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; writing_status_re_ch1 <= writing_status_re and updt_active; writing_status_re_ch2 <= writing_status_re and updt2_active; ----------------------------------------------------------------------- -- Caputure IOC begin set ----------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re_ch1 = '1')then -- updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT) and updt_active; updt_ioc <= follower_reg_mm2s(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re_ch1 = '1')then --dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT) and updt_active; dma_interr <= follower_reg_mm2s(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re_ch1 = '1')then -- dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT) and updt_active; dma_slverr <= follower_reg_mm2s(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re_ch1 = '1')then -- dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT) and updt_active; dma_decerr <= follower_reg_mm2s(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; ----------------------------------------------------------------------- -- Caputure IOC begin set ----------------------------------------------------------------------- REG_IOC2_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then updt2_ioc <= '0'; elsif(writing_status_re_ch2 = '1')then -- updt2_ioc <= sts2_queue_dout(DESC_IOC_TAG_BIT) and updt2_active; updt2_ioc <= follower_reg_s2mm(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC2_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT2_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then dma2_interr <= '0'; elsif(writing_status_re_ch2 = '1')then -- dma2_interr <= sts2_queue_dout(DESC_STS_INTERR_BIT) and updt2_active; dma2_interr <= follower_reg_s2mm (DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT2_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV2_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then dma2_slverr <= '0'; elsif(writing_status_re_ch2 = '1')then -- dma2_slverr <= sts2_queue_dout(DESC_STS_SLVERR_BIT) and updt2_active; dma2_slverr <= follower_reg_s2mm(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV2_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC2_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then dma2_decerr <= '0'; elsif(writing_status_re_ch2 = '1')then -- dma2_decerr <= sts2_queue_dout(DESC_STS_DECERR_BIT) and updt2_active; dma2_decerr <= follower_reg_s2mm(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC2_ERROR; end implementation;
gpl-3.0
803f26ef2c5242ad7abf97d305483b55
0.430465
4.271548
false
false
false
false
nickg/nvc
test/regress/access11.vhd
1
958
entity access11 is end entity; architecture test of access11 is type list; type list_ptr is access list; type list is record chain : list_ptr; item : integer; end record; impure function make_list(item : integer) return list_ptr is begin return new list'(null, item); end function; shared variable l : list_ptr; begin p1: process is variable tmp : list_ptr; begin for i in 1 to 10 loop tmp := l; l := make_list(i); l.chain := tmp; wait for 1 ns; end loop; wait; end process; p2: process is variable it : list_ptr; variable sum : integer := 0; begin wait for 1 hr; it := l; while it /= null loop sum := sum + it.all.item; it := it.chain; end loop; assert sum = 55; wait; end process; end architecture;
gpl-3.0
57d8560e5fa3c087cc5a455f151b4e8d
0.519833
4.042194
false
false
false
false
nickg/nvc
test/sem/error3.vhd
1
952
entity error3 is end entity; architecture test of error3 is -- Examples from LRM 93 section 7.2.5 type R1 is 0 to 7; -- Error type R2 is 7 downto 0; -- Error type T1 is array (R1 range <>) of Bit; type T2 is array (R2 range <>) of Bit; subtype S1 is T1(R1); subtype S2 is T2(R2); constant K1: S1 := (others => '0'); constant K2: T1 := K1(1 to 3) & K1(3 to 4); -- K2'Left = 0 and K2'Right = 4 constant K3: T1 := K1(5 to 7) & K1(1 to 2); -- K3'Left = 0 and K3'Right = 4 constant K4: T1 := K1(2 to 1) & K1(1 to 2); -- K4'Left = 0 and K4'Right = 1 constant K5: S2 := (others => '0'); constant K6: T2 := K5(3 downto 1) & K5(4 downto 3); -- K6'Left = 7 and K6'Right = 3 constant K7: T2 := K5(7 downto 5) & K5(2 downto 1); -- K7'Left = 7 and K7'Right = 3 constant K8: T2 := K5(1 downto 2) & K5(2 downto 1); -- K8'Left = 7 and K8'Right = 6 begin end architecture;
gpl-3.0
4ea3b4b969b15151a41bea01dd5e8206
0.554622
2.644444
false
false
false
false
nickg/nvc
test/elab/issue514.vhd
1
783
package pack is type params is record x, y : integer; end record; end package; ------------------------------------------------------------------------------- use work.pack.all; entity sub is generic ( p : params ); end entity; architecture test of sub is constant px : integer := p.x; constant py : integer := p.y; begin g: for i in px to py generate end generate; end architecture; ------------------------------------------------------------------------------- use work.pack.all; entity issue514 is end entity; architecture test of issue514 is function get_params return params is begin return (x => 4, y => 6); end function; begin u: entity work.sub generic map (p => get_params); end architecture;
gpl-3.0
62407836751129f61a1decfda9ef88ba
0.508301
4.374302
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd
4
27,142
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : gear_rv_r.vhd -- Author : Mentor Graphics -- Created : 2001/10/10 -- Last update: 2001/10/10 ------------------------------------------------------------------------------- -- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains) ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/10/10 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity gear_rv_r is generic( ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1) -- Note: can be negative, if shaft polarity changes port ( terminal rotv1 : rotational_v; terminal rot2 : rotational); end entity gear_rv_r; ------------------------------------------------------------------------------- -- Ideal Architecture ------------------------------------------------------------------------------- architecture ideal of gear_rv_r is quantity w1 across torq_vel through rotv1 to rotational_v_ref; -- quantity w2 across torq2 through rotv2 to rotational_v_ref; quantity theta across torq_ang through rot2 to rotational_ref; begin -- w2 == w1*ratio; theta == ratio*w1'integ; torq_vel == -1.0*torq_ang*ratio; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------- -- Rotational to Electrical Converter -- ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; use IEEE_proposed.electrical_systems.all; entity rot2v is generic ( k : real := 1.0); -- optional gain port ( terminal input : rotational; -- input terminal terminal output : electrical); -- output terminal end entity rot2v ; architecture bhv of rot2v is quantity rot_in across input to rotational_ref; -- Converter's input branch quantity v_out across out_i through output to electrical_ref;-- Converter's output branch begin -- bhv v_out == k*rot_in; end bhv; -- ------------------------------------------------------------------------------- -- Control Horn for Rudder Control (mechanical implementation) -- -- Transfer Function: -- -- tran = R*sin(rot) -- -- Where pos = output translational position, -- R = horn radius, -- theta = input rotational angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity horn_r2t is generic ( R : real := 1.0); -- horn radius port ( terminal theta : ROTATIONAL; -- input angular position port terminal pos : TRANSLATIONAL); -- output translational position port end entity horn_r2t; architecture bhv of horn_r2t is QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF; QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF; begin -- bhv tran == R*sin(rot); -- Convert angle in to translational out tran_frc == -rot_tq/R; -- Convert torque in to force out end bhv; -- ------------------------------------------------------------------------------- -- Control Horn for Rudder Control (mechanical implementation) -- -- Transfer Function: -- -- theta = arcsin(pos/R) -- -- Where pos = input translational position, -- R = horn radius, -- theta = output rotational angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity horn_t2r is generic ( R : real := 1.0); -- Rudder horn radius port ( terminal pos : translational; -- input translational position port terminal theta : rotational); -- output angular position port end entity horn_t2r ; architecture bhv of horn_t2r is QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF; QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF; begin -- bhv rot == arcsin(tran/R); -- Convert translational to angle rot_tq == -tran_frc*R; -- Convert force to torque end bhv; -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : DC_Motor.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2001/06/16 ------------------------------------------------------------------------------- -- Description: Basic DC Motor ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; use IEEE_proposed.electrical_systems.all; entity DC_Motor is generic ( r_wind : resistance; -- Motor winding resistance [Ohm] kt : real; -- Torque coefficient [N*m/Amp] l : inductance; -- Winding inductance [Henrys] d : real; -- Damping coefficient [N*m/(rad/sec)] j : mmoment_i); -- Moment of inertia [kg*meter**2] port (terminal p1, p2 : electrical; terminal shaft_rotv : rotational_v); end entity DC_Motor; ------------------------------------------------------------------------------- -- Basic Architecture -- Motor equations: V = Kt*W + I*Rwind + L*dI/dt -- T = -Kt*I + D*W + J*dW/dt ------------------------------------------------------------------------------- architecture basic of DC_Motor is quantity v across i through p1 to p2; quantity w across torq through shaft_rotv to rotational_v_ref; begin torq == -1.0*kt*i + d*w + j*w'dot; v == kt*w + i*r_wind + l*i'dot; end architecture basic; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : stop_r.vhd -- Author : Mentor Graphics -- Created : 2001/10/10 -- Last update: 2001/10/10 ------------------------------------------------------------------------------- -- Description: Mechanical Hard Stop (ROTATIONAL domain) ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- library IEEE; -- use IEEE.MATH_REAL.all; -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.MECHANICAL_SYSTEMS.all; entity stop_r is generic ( k_stop : real; -- ang_max : angle; -- ang_min : angle := 0.0; ang_max : real; ang_min : real := 0.0; damp_stop : real := 0.000000001 ); port ( terminal ang1, ang2 : rotational); end entity stop_r; architecture ideal of stop_r is quantity velocity : velocity; quantity ang across trq through ang1 to ang2; begin velocity == ang'dot; if ang > ang_max use trq == k_stop * (ang - ang_max) + (damp_stop * velocity); elsif ang > ang_min use trq == 0.0; else trq == k_stop * (ang - ang_min) + (damp_stop * velocity); end use; break on ang'above(ang_min), ang'above(ang_max); end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- library IEEE; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity tran_linkage is port ( terminal p1, p2 : translational ); begin end tran_linkage; architecture a1 of tran_linkage is QUANTITY pos_1 across frc_1 through p1 TO translational_ref; QUANTITY pos_2 across frc_2 through p2 TO translational_ref; begin pos_2 == pos_1; -- Pass position frc_2 == -frc_1; -- Pass force end; -- ------------------------------------------------------------------------------- -- Rudder Model (Rotational Spring) -- -- Transfer Function: -- -- torq = -k*(theta - theta_0) -- -- Where theta = input rotational angle, -- torq = output rotational angle, -- theta_0 = reference angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity rudder is generic ( k : real := 1.0; -- Spring constant theta_0 : real := 0.0); port ( terminal rot : rotational); -- input rotational angle end entity rudder; architecture bhv of rudder is QUANTITY theta across torq through rot TO ROTATIONAL_REF; begin -- bhv torq == k*(theta - theta_0); -- Convert force to torque end bhv; -- library IEEE; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity sum2_e is generic (k1, k2: real := 1.0); -- Gain multipliers port ( terminal in1, in2: electrical; terminal output: electrical); end entity sum2_e; architecture simple of sum2_e is QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF; QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; begin vout == k1*vin1 + k2*vin2; end architecture simple; -- library IEEE; use IEEE.MATH_REAL.all; -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.ELECTRICAL_SYSTEMS.all; entity gain_e is generic ( k: REAL := 1.0); -- Gain multiplier port ( terminal input : electrical; terminal output: electrical); end entity gain_e; architecture simple of gain_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; begin vout == k*vin; end architecture simple; -- ------------------------------------------------------------------------------- -- S-Domain Limiter Model -- ------------------------------------------------------------------------------- library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity limiter_2_e is generic ( limit_high : real := 4.8; -- upper limit limit_low : real := -4.8); -- lower limit port ( terminal input: electrical; terminal output: electrical); end entity limiter_2_e; architecture simple of limiter_2_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; constant slope : real := 1.0e-4; begin if vin > limit_high use -- Upper limit exceeded, so limit input signal vout == limit_high + slope*(vin - limit_high); elsif vin < limit_low use -- Lower limit exceeded, so limit input signal vout == limit_low + slope*(vin - limit_low); else -- No limit exceeded, so pass input signal as is vout == vin; end use; break on vin'above(limit_high), vin'above(limit_low); end architecture simple; -- LIBRARY ieee; LIBRARY IEEE_proposed; USE IEEE_proposed.electrical_systems.ALL; ENTITY lead_lag_ztf IS GENERIC ( a1, a2 : real; b1, b2 : real; k : real := 1.0; tsampl: real; init_delay: real := 0.0); PORT ( TERMINAL input : electrical; TERMINAL output : electrical); END ENTITY lead_lag_ztf ; ARCHITECTURE simple OF lead_lag_ztf IS QUANTITY vin across input TO electrical_ref; QUANTITY vout across iout through output TO electrical_ref; constant num: real_vector := (a1, a2); constant den: real_vector := (b1, b2); BEGIN -- ARCHITECTURE simple vout == k*vin'ztf(num, den, tsampl, init_delay); END ARCHITECTURE simple; -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; entity rudder_servo_ztf is port( terminal servo_in : electrical; terminal pos_fb : electrical; terminal servo_out : electrical ); end rudder_servo_ztf; architecture rudder_servo_ztf of rudder_servo_ztf is -- Component declarations -- Signal declarations terminal error : electrical; terminal limit_in : electrical; terminal ll_in : electrical; terminal summer_fb : electrical; begin -- Signal assignments -- Component instances summer : entity work.sum2_e(simple) port map( in1 => servo_in, in2 => summer_fb, output => error ); forward_gain : entity work.gain_e(simple) generic map( k => 100.0 ) port map( input => error, output => ll_in ); fb_gain : entity work.gain_e(simple) generic map( k => -4.57 ) port map( input => pos_fb, output => summer_fb ); XCMP21 : entity work.limiter_2_e(simple) generic map( limit_high => 4.8, limit_low => -4.8 ) port map( input => limit_in, output => servo_out ); ll_ztf : entity work.lead_lag_ztf(simple) generic map( a1 => 2.003140, a2 => -1.996860, b1 => 3.25000, b2 => -0.75000, k => 400.0, tsampl => 0.0001 ) port map( input => ll_in, output => limit_in ); end rudder_servo_ztf; -- ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : v_sine.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2001/07/03 ------------------------------------------------------------------------------- -- Description: Electrical sinusoidal voltage source -- Includes frequency domain settings ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created -- 2001/07/03 1.1 Mentor Graphics Changed generics from real to -- voltage. ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- Use proposed IEEE natures and packages library IEEE_proposed; use IEEE_proposed.ELECTRICAL_SYSTEMS.all; entity v_sine is generic ( freq : real; -- frequency [Hertz] amplitude : voltage; -- amplitude [Volts] phase : real := 0.0; -- initial phase [Degrees] offset : voltage := 0.0; -- DC value [Volts] df : real := 0.0; -- damping factor [1/second] ac_mag : voltage := 1.0; -- AC magnitude [Volts] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical); end entity v_sine; ------------------------------------------------------------------------------- -- Ideal Architecture ------------------------------------------------------------------------------- architecture ideal of v_sine is -- Declare Branch Quantities quantity v across i through pos to neg; -- Declare Quantity for Phase in radians (calculated below) quantity phase_rad : real; -- Declare Quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; begin -- Convert phase to radians phase_rad == math_2_pi *(freq * NOW + phase / 360.0); if domain = quiescent_domain or domain = time_domain use v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df); else v == ac_spec; -- used for Frequency (AC) analysis end use; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; use IEEE_proposed.mechanical_systems.all; use IEEE_proposed.fluidic_systems.all; use IEEE_proposed.thermal_systems.all; use IEEE_proposed.radiant_systems.all; entity TB_CS2_Z_Domain_ZTF is end TB_CS2_Z_Domain_ZTF ; architecture TB_CS2_Z_Domain_ZTF of TB_CS2_Z_Domain_ZTF is -- Component declarations -- Signal declarations terminal gear_out : rotational; terminal link_in : translational; terminal link_out : translational; terminal mtr_in : electrical; terminal mtr_out : rotational_v; terminal pot_fb : electrical; terminal rudder : rotational; terminal src_in : electrical; begin -- Signal assignments -- Component instances gear5 : entity work.gear_rv_r(ideal) generic map( ratio => 0.01 ) port map( rotv1 => mtr_out, rot2 => gear_out ); XCMP42 : entity work.rot2v(bhv) generic map( k => 1.0 ) port map( output => pot_fb, input => gear_out ); XCMP43 : entity work.horn_r2t(bhv) port map( theta => gear_out, pos => link_in ); XCMP44 : entity work.horn_t2r(bhv) port map( theta => rudder, pos => link_out ); motor3 : entity work.DC_Motor(basic) generic map( r_wind => 2.2, kt => 3.43e-3, l => 2.03e-3, d => 5.63e-6, j => 168.0e-9 ) port map( p1 => mtr_in, p2 => ELECTRICAL_REF, shaft_rotv => mtr_out ); stop3 : entity work.stop_r(ideal) generic map( damp_stop => 1.0e2, k_stop => 1.0e6, ang_max => 1.05, ang_min => -1.05 ) port map( ang1 => gear_out, ang2 => ROTATIONAL_REF ); \linkage\ : entity work.tran_linkage(a1) port map( p2 => link_out, p1 => link_in ); XCMP46 : entity work.rudder(bhv) generic map( k => 0.2 ) port map( rot => rudder ); rudder_servo_zt1 : entity work.rudder_servo_ztf port map( servo_out => mtr_in, servo_in => src_in, pos_fb => pot_fb ); v8 : entity work.v_sine(ideal) generic map( amplitude => 4.8, freq => 1.0 ) port map( pos => src_in, neg => ELECTRICAL_REF ); end TB_CS2_Z_Domain_ZTF; --
gpl-2.0
0365fe992034fb144a36ff8ea0f6c5a2
0.574313
4.384814
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_mngr.vhd
3
51,651
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_mm2s_mngr.vhd -- Description: This entity is the top level entity for the AXI DMA MM2S -- manager. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_9; use axi_dma_v7_1_9.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_mm2s_mngr is generic( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1; -- Depth of DataMover command FIFO ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_INCLUDE_SG : integer range 0 to 1 := 1; -- Include or Exclude the Scatter Gather Engine -- 0 = Exclude SG Engine - Enables Simple DMA Mode -- 1 = Include SG Engine - Enables Scatter Gather Mode C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- AXI Master Stream in for descriptor fetch C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Control Stream Data Width ----------------------------------------------------------------------- -- Memory Map to Stream (MM2S) Parameters ----------------------------------------------------------------------- C_INCLUDE_MM2S : integer range 0 to 1 := 1; -- Include or exclude MM2S primary data path -- 0 = Exclude MM2S primary data path -- 1 = Include MM2S primary data path C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for MM2S Read Port C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_FAMILY : string := "virtex7" -- Target FPGA Device Family ); port ( -- Secondary Clock and Reset m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Primary Clock and Reset -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- soft_reset : in std_logic ; -- -- -- MM2S Control and Status -- mm2s_run_stop : in std_logic ; -- mm2s_keyhole : in std_logic ; mm2s_halted : in std_logic ; -- mm2s_ftch_idle : in std_logic ; -- mm2s_updt_idle : in std_logic ; -- mm2s_ftch_err_early : in std_logic ; -- mm2s_ftch_stale_desc : in std_logic ; -- mm2s_tailpntr_enble : in std_logic ; -- mm2s_halt : in std_logic ; -- mm2s_halt_cmplt : in std_logic ; -- mm2s_halted_clr : out std_logic ; -- mm2s_halted_set : out std_logic ; -- mm2s_idle_set : out std_logic ; -- mm2s_idle_clr : out std_logic ; -- mm2s_new_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- mm2s_new_curdesc_wren : out std_logic ; -- mm2s_stop : out std_logic ; -- mm2s_desc_flush : out std_logic ; -- cntrl_strm_stop : out std_logic ; mm2s_all_idle : out std_logic ; -- -- mm2s_error : out std_logic ; -- s2mm_error : in std_logic ; -- -- Simple DMA Mode Signals mm2s_sa : in std_logic_vector -- (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- mm2s_length_wren : in std_logic ; -- mm2s_length : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- mm2s_smple_done : out std_logic ; -- mm2s_interr_set : out std_logic ; -- mm2s_slverr_set : out std_logic ; -- mm2s_decerr_set : out std_logic ; -- m_axis_mm2s_aclk : in std_logic; mm2s_strm_tlast : in std_logic; mm2s_strm_tready : in std_logic; mm2s_axis_info : out std_logic_vector (13 downto 0); -- -- SG MM2S Descriptor Fetch AXI Stream In -- m_axis_mm2s_ftch_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_mm2s_ftch_tvalid : in std_logic ; -- m_axis_mm2s_ftch_tready : out std_logic ; -- m_axis_mm2s_ftch_tlast : in std_logic ; -- m_axis_mm2s_ftch_tdata_new : in std_logic_vector -- (96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); -- m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector -- (63 downto 0); -- m_axis_mm2s_ftch_tvalid_new : in std_logic ; -- m_axis_ftch1_desc_available : in std_logic; -- -- SG MM2S Descriptor Update AXI Stream Out -- s_axis_mm2s_updtptr_tdata : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- s_axis_mm2s_updtptr_tvalid : out std_logic ; -- s_axis_mm2s_updtptr_tready : in std_logic ; -- s_axis_mm2s_updtptr_tlast : out std_logic ; -- -- s_axis_mm2s_updtsts_tdata : out std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_mm2s_updtsts_tvalid : out std_logic ; -- s_axis_mm2s_updtsts_tready : in std_logic ; -- s_axis_mm2s_updtsts_tlast : out std_logic ; -- -- -- User Command Interface Ports (AXI Stream) -- s_axis_mm2s_cmd_tvalid : out std_logic ; -- s_axis_mm2s_cmd_tready : in std_logic ; -- s_axis_mm2s_cmd_tdata : out std_logic_vector -- ((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);-- -- -- User Status Interface Ports (AXI Stream) -- m_axis_mm2s_sts_tvalid : in std_logic ; -- m_axis_mm2s_sts_tready : out std_logic ; -- m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; -- m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; -- mm2s_err : in std_logic ; -- -- ftch_error : in std_logic ; -- updt_error : in std_logic ; -- -- -- Memory Map to Stream Control Stream Interface -- m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- ((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); -- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic ; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_dma_mm2s_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_mm2s_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Primary DataMover Command signals signal mm2s_cmnd_wr : std_logic := '0'; signal mm2s_cmnd_data : std_logic_vector ((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0'); signal mm2s_cmnd_pending : std_logic := '0'; -- Primary DataMover Status signals signal mm2s_done : std_logic := '0'; signal mm2s_stop_i : std_logic := '0'; signal mm2s_interr : std_logic := '0'; signal mm2s_slverr : std_logic := '0'; signal mm2s_decerr : std_logic := '0'; signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0'); signal dma_mm2s_error : std_logic := '0'; signal soft_reset_d1 : std_logic := '0'; signal soft_reset_d2 : std_logic := '0'; signal soft_reset_re : std_logic := '0'; signal mm2s_error_i : std_logic := '0'; --signal cntrl_strm_stop : std_logic := '0'; signal mm2s_halted_set_i : std_logic := '0'; signal mm2s_sts_received_clr : std_logic := '0'; signal mm2s_sts_received : std_logic := '0'; signal mm2s_cmnd_idle : std_logic := '0'; signal mm2s_sts_idle : std_logic := '0'; -- Scatter Gather Interface signals signal desc_fetch_req : std_logic := '0'; signal desc_fetch_done : std_logic := '0'; signal desc_fetch_done_del : std_logic := '0'; signal desc_update_req : std_logic := '0'; signal desc_update_done : std_logic := '0'; signal desc_available : std_logic := '0'; signal packet_in_progress : std_logic := '0'; signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_eof : std_logic := '0'; signal mm2s_desc_sof : std_logic := '0'; signal mm2s_desc_cmplt : std_logic := '0'; signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0'); signal mm2s_strm_tlast_int : std_logic; signal rd_en_hold, rd_en_hold_int : std_logic; -- Control Stream Fifo write signals signal cntrlstrm_fifo_wren : std_logic := '0'; signal cntrlstrm_fifo_full : std_logic := '0'; signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0'); signal info_fifo_full : std_logic; signal info_fifo_empty : std_logic; signal updt_pending : std_logic := '0'; signal mm2s_cmnd_wr_1 : std_logic := '0'; signal fifo_rst : std_logic; signal fifo_empty : std_logic; signal fifo_empty_first : std_logic; signal fifo_empty_first1 : std_logic; signal first_read_pulse : std_logic; signal fifo_read : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Include MM2S State Machine and support logic ------------------------------------------------------------------------------- GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate begin -- Pass out to register module mm2s_halted_set <= mm2s_halted_set_i; ------------------------------------------------------------------------------- -- Graceful shut down logic ------------------------------------------------------------------------------- -- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error -- or SG Fetch error, or Stale Descriptor Error mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error or updt_error -- SG Update engine reports error or ftch_error -- SG Fetch engine reports error or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error -- pass out to shut down s2mm mm2s_error <= mm2s_error_i; -- Clear run/stop and stop state machines due to errors or soft reset -- Error based on datamover error report or sg update error or sg fetch error -- SG update error and fetch error included because need to shut down, no way -- to update descriptors on sg update error and on fetch error descriptor -- data is corrupt therefor do not want to issue the xfer command to primary datamover --CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore -- need to stop all processes regardless of the source of the error. -- mm2s_stop_i <= mm2s_error -- Error -- or soft_reset; -- Soft Reset issued mm2s_stop_i <= mm2s_error_i -- Error on MM2S or s2mm_error -- Error on S2MM or soft_reset; -- Soft Reset issued -- Reg stop out REG_STOP_OUT : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_stop <= '0'; else mm2s_stop <= mm2s_stop_i; end if; end if; end process REG_STOP_OUT; -- Generate DMA Controller For Scatter Gather Mode GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate begin -- Not Used in SG Mode (Errors are imbedded in updated descriptor and -- generate error after descriptor update is complete) mm2s_interr_set <= '0'; mm2s_slverr_set <= '0'; mm2s_decerr_set <= '0'; mm2s_smple_done <= '0'; mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new; --------------------------------------------------------------------------- -- MM2S Primary DMA Controller State Machine --------------------------------------------------------------------------- I_MM2S_SM : entity axi_dma_v7_1_9.axi_dma_mm2s_sm generic map( C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH , C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE , C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Channel 1 Control and Status mm2s_run_stop => mm2s_run_stop , mm2s_keyhole => mm2s_keyhole , mm2s_ftch_idle => mm2s_ftch_idle , mm2s_cmnd_idle => mm2s_cmnd_idle , mm2s_sts_idle => mm2s_sts_idle , mm2s_stop => mm2s_stop_i , mm2s_desc_flush => mm2s_desc_flush , -- MM2S Descriptor Fetch Request (from mm2s_sm) desc_available => desc_available , desc_fetch_req => desc_fetch_req , desc_fetch_done => desc_fetch_done , desc_update_done => desc_update_done , updt_pending => updt_pending , packet_in_progress => packet_in_progress , -- DataMover Command mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 , mm2s_cmnd_data => mm2s_cmnd_data , mm2s_cmnd_pending => mm2s_cmnd_pending , -- Descriptor Fields mm2s_cache_info => mm2s_desc_info , mm2s_desc_baddress => mm2s_desc_baddress , mm2s_desc_blength => mm2s_desc_blength , mm2s_desc_blength_v => mm2s_desc_blength_v , mm2s_desc_blength_s => mm2s_desc_blength_s , mm2s_desc_eof => mm2s_desc_eof , mm2s_desc_sof => mm2s_desc_sof ); --------------------------------------------------------------------------- -- MM2S Scatter Gather State Machine --------------------------------------------------------------------------- I_MM2S_SG_IF : entity axi_dma_v7_1_9.axi_dma_mm2s_sg_if generic map( ------------------------------------------------------------------- -- Scatter Gather Parameters ------------------------------------------------------------------- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH, C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_MICRO_DMA => C_MICRO_DMA, C_FAMILY => C_FAMILY ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- SG MM2S Descriptor Fetch AXI Stream In m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata , m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid , m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready , m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast , m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new , m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new , m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new , m_axis_ftch1_desc_available => m_axis_ftch1_desc_available , -- SG MM2S Descriptor Update AXI Stream Out s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata , s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid , s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready , s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast , s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata , s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid , s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready , s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast , -- MM2S Descriptor Fetch Request (from mm2s_sm) desc_available => desc_available , desc_fetch_req => desc_fetch_req , desc_fetch_done => desc_fetch_done , updt_pending => updt_pending , packet_in_progress => packet_in_progress , -- MM2S Descriptor Update Request desc_update_done => desc_update_done , mm2s_ftch_stale_desc => mm2s_ftch_stale_desc , mm2s_sts_received_clr => mm2s_sts_received_clr , mm2s_sts_received => mm2s_sts_received , mm2s_desc_cmplt => mm2s_desc_cmplt , mm2s_done => mm2s_done , mm2s_interr => mm2s_interr , mm2s_slverr => mm2s_slverr , mm2s_decerr => mm2s_decerr , mm2s_tag => mm2s_tag , mm2s_halt => mm2s_halt , -- CR566306 -- Control Stream Output cntrlstrm_fifo_wren => cntrlstrm_fifo_wren , cntrlstrm_fifo_full => cntrlstrm_fifo_full , cntrlstrm_fifo_din => cntrlstrm_fifo_din , -- MM2S Descriptor Field Output mm2s_new_curdesc => mm2s_new_curdesc , mm2s_new_curdesc_wren => mm2s_new_curdesc_wren , mm2s_desc_baddress => mm2s_desc_baddress , mm2s_desc_blength => mm2s_desc_blength , mm2s_desc_blength_v => mm2s_desc_blength_v , mm2s_desc_blength_s => mm2s_desc_blength_s , mm2s_desc_info => mm2s_desc_info , mm2s_desc_eof => mm2s_desc_eof , mm2s_desc_sof => mm2s_desc_sof , mm2s_desc_app0 => mm2s_desc_app0 , mm2s_desc_app1 => mm2s_desc_app1 , mm2s_desc_app2 => mm2s_desc_app2 , mm2s_desc_app3 => mm2s_desc_app3 , mm2s_desc_app4 => mm2s_desc_app4 ); cntrlstrm_fifo_full <= '0'; end generate GEN_SCATTER_GATHER_MODE; -- Generate DMA Controller for Simple DMA Mode GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate begin -- Scatter Gather signals not used in Simple DMA Mode m_axis_mm2s_ftch_tready <= '0'; s_axis_mm2s_updtptr_tdata <= (others => '0'); s_axis_mm2s_updtptr_tvalid <= '0'; s_axis_mm2s_updtptr_tlast <= '0'; s_axis_mm2s_updtsts_tdata <= (others => '0'); s_axis_mm2s_updtsts_tvalid <= '0'; s_axis_mm2s_updtsts_tlast <= '0'; desc_available <= '0'; desc_fetch_done <= '0'; packet_in_progress <= '0'; desc_update_done <= '0'; cntrlstrm_fifo_wren <= '0'; cntrlstrm_fifo_din <= (others => '0'); mm2s_new_curdesc <= (others => '0'); mm2s_new_curdesc_wren <= '0'; mm2s_desc_baddress <= (others => '0'); mm2s_desc_blength <= (others => '0'); mm2s_desc_blength_v <= (others => '0'); mm2s_desc_blength_s <= (others => '0'); mm2s_desc_eof <= '0'; mm2s_desc_sof <= '0'; mm2s_desc_cmplt <= '0'; mm2s_desc_app0 <= (others => '0'); mm2s_desc_app1 <= (others => '0'); mm2s_desc_app2 <= (others => '0'); mm2s_desc_app3 <= (others => '0'); mm2s_desc_app4 <= (others => '0'); desc_fetch_req <= '0'; -- Simple DMA State Machine I_MM2S_SMPL_SM : entity axi_dma_v7_1_9.axi_dma_smple_sm generic map( C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH, C_MICRO_DMA => C_MICRO_DMA ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Channel 1 Control and Status run_stop => mm2s_run_stop , keyhole => mm2s_keyhole , stop => mm2s_stop_i , cmnd_idle => mm2s_cmnd_idle , sts_idle => mm2s_sts_idle , -- DataMover Status sts_received => mm2s_sts_received , sts_received_clr => mm2s_sts_received_clr , -- DataMover Command cmnd_wr => mm2s_cmnd_wr_1 , cmnd_data => mm2s_cmnd_data , cmnd_pending => mm2s_cmnd_pending , -- Trasnfer Qualifiers xfer_length_wren => mm2s_length_wren , xfer_address => mm2s_sa , xfer_length => mm2s_length ); -- Pass Done/Error Status out to DMASR mm2s_interr_set <= mm2s_interr; mm2s_slverr_set <= mm2s_slverr; mm2s_decerr_set <= mm2s_decerr; -- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR. -- Receive clear when not shutting down mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0' -- Else halt set prior to halted being set else mm2s_halted_set_i when mm2s_halted = '0' else '0'; end generate GEN_SIMPLE_DMA_MODE; ------------------------------------------------------------------------------- -- MM2S Primary DataMover command status interface ------------------------------------------------------------------------------- I_MM2S_CMDSTS : entity axi_dma_v7_1_9.axi_dma_mm2s_cmdsts_if generic map( C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH, C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Fetch command write interface from mm2s sm mm2s_cmnd_wr => mm2s_cmnd_wr_1 , mm2s_cmnd_data => mm2s_cmnd_data , mm2s_cmnd_pending => mm2s_cmnd_pending , mm2s_sts_received_clr => mm2s_sts_received_clr , mm2s_sts_received => mm2s_sts_received , mm2s_tailpntr_enble => mm2s_tailpntr_enble , mm2s_desc_cmplt => mm2s_desc_cmplt , -- User Command Interface Ports (AXI Stream) s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid , s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready , s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid , m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready , m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata , m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep , -- MM2S Primary DataMover Status mm2s_err => mm2s_err , mm2s_done => mm2s_done , mm2s_error => dma_mm2s_error , mm2s_interr => mm2s_interr , mm2s_slverr => mm2s_slverr , mm2s_decerr => mm2s_decerr , mm2s_tag => mm2s_tag ); --------------------------------------------------------------------------- -- Halt / Idle Status Manager --------------------------------------------------------------------------- I_MM2S_STS_MNGR : entity axi_dma_v7_1_9.axi_dma_mm2s_sts_mngr generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- dma control and sg engine status signals mm2s_run_stop => mm2s_run_stop , mm2s_ftch_idle => mm2s_ftch_idle , mm2s_updt_idle => mm2s_updt_idle , mm2s_cmnd_idle => mm2s_cmnd_idle , mm2s_sts_idle => mm2s_sts_idle , -- stop and halt control/status mm2s_stop => mm2s_stop_i , mm2s_halt_cmplt => mm2s_halt_cmplt , -- system state and control mm2s_all_idle => mm2s_all_idle , mm2s_halted_clr => mm2s_halted_clr , mm2s_halted_set => mm2s_halted_set_i , mm2s_idle_set => mm2s_idle_set , mm2s_idle_clr => mm2s_idle_clr ); -- MM2S Control Stream Included GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate begin -- Register soft reset to create rising edge pulse to use for shut down. -- soft_reset from DMACR does not clear until after all reset processes -- are done. This causes stop to assert too long causing issue with -- status stream skid buffer. REG_SFT_RST : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then soft_reset_d1 <= '0'; soft_reset_d2 <= '0'; else soft_reset_d1 <= soft_reset; soft_reset_d2 <= soft_reset_d1; end if; end if; end process REG_SFT_RST; -- Rising edge soft reset pulse soft_reset_re <= soft_reset_d1 and not soft_reset_d2; -- Control Stream module stop requires rising edge of soft reset to -- shut down due to DMACR.SoftReset does not deassert on internal hard reset -- It clears after therefore do not want to issue another stop to cntrl strm -- skid buffer. cntrl_strm_stop <= mm2s_error_i -- Error or soft_reset_re; -- Soft Reset issued -- Control stream interface -- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_9.axi_dma_mm2s_cntrl_strm -- generic map( -- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , -- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH , -- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH , -- C_FAMILY => C_FAMILY -- ) -- port map( -- -- Secondary clock / reset -- m_axi_sg_aclk => m_axi_sg_aclk , -- m_axi_sg_aresetn => m_axi_sg_aresetn , -- -- -- Primary clock / reset -- axi_prmry_aclk => axi_prmry_aclk , -- p_reset_n => p_reset_n , -- -- -- MM2S Error -- mm2s_stop => cntrl_strm_stop , -- -- -- Control Stream input ---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren , -- cntrlstrm_fifo_full => cntrlstrm_fifo_full , -- cntrlstrm_fifo_din => cntrlstrm_fifo_din , -- -- -- Memory Map to Stream Control Stream Interface -- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , -- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , -- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , -- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , -- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast -- -- ); end generate GEN_CNTRL_STREAM; -- MM2S Control Stream Excluded GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate begin soft_reset_d1 <= '0'; soft_reset_d2 <= '0'; soft_reset_re <= '0'; cntrl_strm_stop <= '0'; end generate GEN_NO_CNTRL_STREAM; m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= (others => '0'); m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; end generate GEN_MM2S_DMA_CONTROL; ------------------------------------------------------------------------------- -- Exclude MM2S State Machine and support logic ------------------------------------------------------------------------------- GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate begin m_axis_mm2s_ftch_tready <= '0'; s_axis_mm2s_updtptr_tdata <= (others =>'0'); s_axis_mm2s_updtptr_tvalid <= '0'; s_axis_mm2s_updtptr_tlast <= '0'; s_axis_mm2s_updtsts_tdata <= (others =>'0'); s_axis_mm2s_updtsts_tvalid <= '0'; s_axis_mm2s_updtsts_tlast <= '0'; mm2s_new_curdesc <= (others =>'0'); mm2s_new_curdesc_wren <= '0'; s_axis_mm2s_cmd_tvalid <= '0'; s_axis_mm2s_cmd_tdata <= (others =>'0'); m_axis_mm2s_sts_tready <= '0'; mm2s_halted_clr <= '0'; mm2s_halted_set <= '0'; mm2s_idle_set <= '0'; mm2s_idle_clr <= '0'; m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= (others => '0'); m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; mm2s_stop <= '0'; mm2s_desc_flush <= '0'; mm2s_all_idle <= '1'; mm2s_error <= '0'; -- CR#570587 mm2s_interr_set <= '0'; mm2s_slverr_set <= '0'; mm2s_decerr_set <= '0'; mm2s_smple_done <= '0'; cntrl_strm_stop <= '0'; end generate GEN_NO_MM2S_DMA_CONTROL; TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then desc_fetch_done_del <= '0'; else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then desc_fetch_done_del <= desc_fetch_done; end if; end if; end process; process (m_axis_mm2s_aclk) begin if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then if (m_axi_sg_aresetn = '0') then fifo_empty <= '0'; else fifo_empty <= info_fifo_empty; end if; end if; end process; process (m_axis_mm2s_aclk) begin if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then if (m_axi_sg_aresetn = '0') then fifo_empty_first <= '0'; fifo_empty_first1 <= '0'; else if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then fifo_empty_first <= '1'; end if; fifo_empty_first1 <= fifo_empty_first; end if; end if; end process; first_read_pulse <= fifo_empty_first and (not fifo_empty_first1); fifo_read <= first_read_pulse or rd_en_hold; mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0); -- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty); -- process (m_axis_mm2s_aclk) -- begin -- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then -- if (p_reset_n = '0') then -- rd_en_hold <= '0'; -- rd_en_hold_int <= '0'; -- else -- if (rd_en_hold = '1') then -- rd_en_hold <= '0'; -- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then -- rd_en_hold <= '1'; -- rd_en_hold_int <= '0'; -- else -- rd_en_hold <= rd_en_hold; -- rd_en_hold_int <= rd_en_hold_int; -- end if; -- end if; -- end if; -- end process; process (m_axis_mm2s_aclk) begin if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then if (p_reset_n = '0') then rd_en_hold <= '0'; rd_en_hold_int <= '0'; else if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then rd_en_hold <= '1'; rd_en_hold_int <= '0'; elsif (info_fifo_empty = '0') then rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready; rd_en_hold_int <= rd_en_hold; else rd_en_hold <= rd_en_hold; rd_en_hold_int <= rd_en_hold_int; end if; end if; end if; end process; fifo_rst <= not (m_axi_sg_aresetn); -- Following FIFO is used to store the Tuser, Tid and xCache info I_INFO_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord generic map( C_DWIDTH => 14, C_DEPTH => 31 , C_CNT_WIDTH => 5 , C_USE_BLKMEM => 0, C_USE_AUTORD => 1, C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => fifo_rst , AFIFO_Wr_clk => m_axi_sg_aclk , AFIFO_Wr_en => desc_fetch_done_del , AFIFO_Din => mm2s_desc_info_int , AFIFO_Rd_clk => m_axis_mm2s_aclk , AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => open , AFIFO_Dout => mm2s_axis_info , AFIFO_Full => info_fifo_full , AFIFO_Empty => info_fifo_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); end generate TDEST_FIFO; NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate mm2s_axis_info <= (others => '0'); end generate NO_TDEST_FIFO; end implementation;
gpl-3.0
2f61b62ab33f1169661304fbb7c14705
0.406226
4.221577
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc1373.vhd
4
6,563
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1373.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p03n01i01373ent IS END c08s05b00x00p03n01i01373ent; ARCHITECTURE c08s05b00x00p03n01i01373arch OF c08s05b00x00p03n01i01373ent IS BEGIN TESTING: PROCESS -- -- Define constants for package -- constant lowb : integer := 1 ; constant highb : integer := 5 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 ; constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- variable v_st_arr2 : st_arr2 := c_st_arr2_1 ; -- BEGIN v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) := c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ; assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2) report "***PASSED TEST: c08s05b00x00p03n01i01373" severity NOTE; assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2) report "***FAILED TEST: c08s05b00x00p03n01i01373 - The types of the variable and the assigned variable must match." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p03n01i01373arch;
gpl-2.0
4f76a1d9e98b17a46b9412d98ea1f3c9
0.583727
2.932529
false
false
false
false
nickg/nvc
test/sem/gensub.vhd
1
2,814
entity gensub is end entity; architecture test of gensub is begin b1: block is function adder generic (n : integer) (x : integer) return integer is begin return x + n; -- OK end function; function add1 is new adder generic map (1); -- OK constant c1 : integer := add1(2); -- OK begin end block; b2: block is function not_generic return integer; -- OK function error1 is new not_generic generic map (1); -- Error function no_body generic (n : integer) return integer; function error2 is new no_body generic map (1); -- Error begin end block; b3: block is function adder generic (type t; function "+"(l, r : t) return t is <>; n : t) (x : t) return t is -- OK begin return x + n; end function; function add1_int is new adder generic map (t => integer, n => 1); function add1_real is new adder generic map (t => real, n => 1.0); constant c1 : integer := add1_int(integer'(1)); -- OK constant c2 : real := add1_real(real'(1.0)); -- OK function add_error1 is new adder generic map (t => string, n => 1); -- Error constant c3 : integer := adder(4); -- Error procedure do_stuff generic (x : integer) is begin end procedure; begin do_stuff; -- Error end block; b4: block is function outer generic (type t) (x : t) return t is function inner generic (type q; y : q) return q is begin return y + t; -- Error end function; function inner_inst is new inner generic map (q => t, y => x); -- Error begin return inner_inst; end function; begin end block; b5: block is function test1 generic (x : integer) return integer; function test1 generic (x : real) return integer is -- Error begin return 1; end function; function test2 generic (x : integer) return integer; function test2 generic (x, y : real) return integer is -- Error begin return 1; end function; begin end block; b6: block is function test1 generic (type t) (x : t) return integer is begin return 1; end function; function test1 generic (type t) (x : t) return real is begin return 1.0; end function; function test_error is new test1 generic map (t => boolean); -- Error function test_error2 is new test444 generic map (t => boolean); -- Error begin end block; end architecture;
gpl-3.0
4fa9f66dc1cc6afba43bade923e1530e
0.534471
4.250755
false
true
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc1596.vhd
4
1,831
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1596.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s11b00x00p03n01i01596ent IS END c08s11b00x00p03n01i01596ent; ARCHITECTURE c08s11b00x00p03n01i01596arch OF c08s11b00x00p03n01i01596ent IS BEGIN TESTING: PROCESS variable p : integer := 0; BEGIN L : for j in 1 to 10 loop K : for i in 1 to 20 loop exit when j = 5; p := p + 1; end loop K; end loop; assert NOT( p=180 ) report "***PASSED TEST: c08s11b00x00p03n01i01596" severity NOTE; assert ( p=180 ) report "***FAILED TEST: c08s11b00x00p03n01i01596 - Exit applies only to inner loop" severity ERROR; wait; END PROCESS TESTING; END c08s11b00x00p03n01i01596arch;
gpl-2.0
13ac536e988eea7b947511e334068e3f
0.651557
3.625743
false
true
false
false
tgingold/ghdl
testsuite/synth/memmux01/tb_memmux01.vhdl
1
1,353
entity tb_memmux01 is end tb_memmux01; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; architecture behav of tb_memmux01 is signal wen : std_logic; signal addr : std_logic_vector (3 downto 0); signal wdat : std_logic; signal rdat : std_logic_vector (15 downto 0); signal clk : std_logic; signal rst : std_logic; begin dut : entity work.memmux01 port map ( wen => wen, addr => addr, wdat => wdat, rdat => rdat, clk => clk, rst => rst); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; variable v : std_logic_vector(15 downto 0); begin rst <= '1'; wen <= '0'; wdat <= '1'; addr <= x"0"; pulse; rst <= '0'; addr <= x"4"; wen <= '1'; pulse; assert rdat = x"0000" severity failure; addr <= x"f"; pulse; assert rdat = x"0010" severity failure; addr <= x"4"; wdat <= '0'; pulse; assert rdat = x"8010" severity failure; pulse; assert rdat = x"8000" severity failure; v := x"8000"; wdat <= '1'; for i in 0 to 14 loop addr <= std_logic_vector(to_unsigned(i, 4)); pulse; assert rdat = v severity failure; v (i) := '1'; end loop; wait; end process; end behav;
gpl-2.0
d1b1c6dc4ccabf1cf11e79b32d2fb07f
0.546194
3.308068
false
false
false
false
tgingold/ghdl
testsuite/gna/issue207/pack1.vhd
2
2,520
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package pack0 is procedure inc(signal val:inout std_logic_vector); procedure inc(signal val:inout unsigned); procedure inc(signal val:inout signed); procedure inc(signal val:inout integer); procedure dec(signal val:inout std_logic_vector); procedure dec(signal val:inout unsigned); procedure dec(signal val:inout signed); procedure dec(signal val:inout integer); end pack0; package body pack0 is procedure inc(signal val:inout std_logic_vector) is begin val<= std_logic_vector(unsigned(val) + 1); end; procedure inc(signal val:inout signed) is begin val<= val + 1; end; procedure inc(signal val:inout unsigned) is begin val<= val + 1; end; procedure inc(signal val:inout integer) is begin val<= val + 1; end; procedure dec(signal val:inout std_logic_vector) is begin val<= std_logic_vector(unsigned(val) - 1); end; procedure dec(signal val:inout unsigned) is begin val<= val - 1; end; procedure dec(signal val:inout signed) is begin val<= val - 1; end; procedure dec(signal val:inout integer) is begin val<= val - 1; end; end; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package pack1 is procedure inc(variable val:inout unsigned); procedure inc(variable val:inout integer); procedure dec(variable val:inout unsigned); procedure dec(variable val:inout integer); end pack1; package body pack1 is procedure inc(variable val:inout unsigned) is begin val := val + 1; end; procedure inc(variable val:inout integer) is begin val := val + 1; end; procedure dec(variable val:inout unsigned) is begin val := val - 1; end; procedure dec(variable val:inout integer) is begin val := val - 1; end; end; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.pack0.all; use work.pack1.all; entity overload is end entity; architecture foo of overload is signal sig: unsigned ( 7 downto 0) := (others => '0'); signal int: integer range 0 to 255; -- 'LEFT = 0 initial value begin process variable isig: unsigned ( 7 downto 0) := (others => '0'); variable iint: integer range 0 to 255; begin inc(sig); inc(isig); inc(int); inc(iint); wait for 0 ns; dec(sig); dec(isig); dec(int); dec(iint); wait; end process; end architecture;
gpl-2.0
b372649b8949f99d7c2372be148d11ca
0.660317
3.509749
false
false
false
false
tgingold/ghdl
testsuite/gna/bug053/tb3.vhdl
2
546
package pkg2 is package pkg1 is constant c : natural := 5; function f return natural; end pkg1; end pkg2; package body pkg2 is package body pkg1 is function f return natural is begin return 3; end f; end pkg1; end pkg2; entity tb3 is end tb3; use work.pkg2.all; architecture behav of tb3 is begin assert pkg1.c = 5 severity failure; assert pkg1.c /= 5 report "value is correct" severity note; assert pkg1.f = 3 severity failure; assert pkg1.f /= 3 report "value is correct" severity note; end behav;
gpl-2.0
3eeb04f18f92bcb2ae05f5abf7596c31
0.690476
3.329268
false
false
false
false
DE5Amigos/SylvesterTheDE2Bot
DE2Botv3Fall16Main/altpll1.vhd
1
16,366
-- megafunction wizard: %ALTPLL% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altpll -- ============================================================ -- File Name: altpll1.vhd -- Megafunction Name(s): -- altpll -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY altpll1 IS PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ); END altpll1; ARCHITECTURE SYN OF altpll1 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT altpll GENERIC ( clk0_divide_by : NATURAL; clk0_duty_cycle : NATURAL; clk0_multiply_by : NATURAL; clk0_phase_shift : STRING; clk1_divide_by : NATURAL; clk1_duty_cycle : NATURAL; clk1_multiply_by : NATURAL; clk1_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; lpm_type : STRING; operation_mode : STRING; port_activeclock : STRING; port_areset : STRING; port_clkbad0 : STRING; port_clkbad1 : STRING; port_clkloss : STRING; port_clkswitch : STRING; port_configupdate : STRING; port_fbin : STRING; port_inclk0 : STRING; port_inclk1 : STRING; port_locked : STRING; port_pfdena : STRING; port_phasecounterselect : STRING; port_phasedone : STRING; port_phasestep : STRING; port_phaseupdown : STRING; port_pllena : STRING; port_scanaclr : STRING; port_scanclk : STRING; port_scanclkena : STRING; port_scandata : STRING; port_scandataout : STRING; port_scandone : STRING; port_scanread : STRING; port_scanwrite : STRING; port_clk0 : STRING; port_clk1 : STRING; port_clk2 : STRING; port_clk3 : STRING; port_clk4 : STRING; port_clk5 : STRING; port_clkena0 : STRING; port_clkena1 : STRING; port_clkena2 : STRING; port_clkena3 : STRING; port_clkena4 : STRING; port_clkena5 : STRING; port_extclk0 : STRING; port_extclk1 : STRING; port_extclk2 : STRING; port_extclk3 : STRING ); PORT ( inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire5_bv(0 DOWNTO 0) <= "0"; sub_wire5 <= To_stdlogicvector(sub_wire5_bv); sub_wire2 <= sub_wire0(1); sub_wire1 <= sub_wire0(0); c0 <= sub_wire1; c1 <= sub_wire2; sub_wire3 <= inclk0; sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; altpll_component : altpll GENERIC MAP ( clk0_divide_by => 11, clk0_duty_cycle => 50, clk0_multiply_by => 6, clk0_phase_shift => "0", clk1_divide_by => 9, clk1_duty_cycle => 50, clk1_multiply_by => 4, clk1_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 37037, intended_device_family => "Cyclone II", lpm_type => "altpll", operation_mode => "NORMAL", port_activeclock => "PORT_UNUSED", port_areset => "PORT_UNUSED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_configupdate => "PORT_UNUSED", port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_UNUSED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", port_phasestep => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED", port_pllena => "PORT_UNUSED", port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED", port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", port_clk2 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", port_extclk0 => "PORT_UNUSED", port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED" ) PORT MAP ( inclk => sub_wire4, clk => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "11" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.727273" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "324.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "6" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "14.74560000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0" -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" -- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
mit
2a473259f7671ebabe45c84d61010629
0.685384
3.286345
false
false
false
false
tgingold/ghdl
testsuite/gna/issue333/repro.vhdl
1
1,449
entity repro is end repro; architecture Behavioral of repro is constant c_CLOCK_FREQUENCY : natural := 32000000; constant c_SWITCH_ON_TIME_ms : time := 200 ms; constant c_switch_ms : natural := c_SWITCH_ON_TIME_ms / 1 ms; constant c_freq1 : real := real(c_CLOCK_FREQUENCY * (c_SWITCH_ON_TIME_ms / 1 ms)); constant c_SWITCH_COUNT_CYCLES : integer := integer(real(c_CLOCK_FREQUENCY * (c_SWITCH_ON_TIME_ms / 1 ms)) / 1000.0); begin process is begin report " Switch ON time " & time'image(c_SWITCH_ON_TIME_ms) severity NOTE; report " Switch count " & natural'image(c_SWITCH_COUNT_CYCLES) severity NOTE; -- sanity checks on time constraints report "Clock frequency = " & natural'image(c_CLOCK_FREQUENCY) & " Hz" severity NOTE; report "switch_time (ms): " & natural'image (c_switch_ms); report "freq * switch_time (ms): " & real'image (c_freq1); report "Clock period = " & time'image( 1 sec / c_CLOCK_FREQUENCY) severity NOTE; report "Switch period = " & time'image ( 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES) severity NOTE; Assert c_SWITCH_ON_TIME_ms = 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES report "Wrong Switch ON time = " & time'image ( 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES) severity ERROR; wait; end process; end Behavioral;
gpl-2.0
e43bd68781765e214d3aa39176b06c96
0.620428
3.560197
false
false
false
false
tgingold/ghdl
testsuite/gna/issue645/foo.vhdl
1
714
library ieee; use ieee.std_logic_1164.all; package types is type t is array (natural range <>) of std_logic_vector; -- Warning : only compiles with --std=08 end package; library ieee; use ieee.std_logic_1164.all; use work.types.all; entity foo is generic (n: natural; p: natural); port (clk: in std_logic; din: in std_logic_vector(p-1 downto 0); dout: out t); end entity; architecture rtl of foo is signal REG: t(0 to n-1)(p-1 downto 0); -- !!! CRASH HERE begin process (clk) begin if clk'event and clk='1' then for i in 1 to n-1 loop reg(i) <= reg(i-1); end loop; reg(0) <= din; end if; end process; dout <= reg; end architecture;
gpl-2.0
be711bded8e25784327018f07a8c5f79
0.616246
3.077586
false
false
false
false
nickg/nvc
test/regress/wave5.vhd
1
563
entity wave5 is end entity; library ieee; use ieee.std_logic_1164.all; architecture test of wave5 is type pair is record a, b : integer; end record; type rec is record x : integer; y : std_logic_vector(1 to 3); z : pair; end record; signal r : rec; begin main: process is begin wait for 1 ns; r.y <= "101"; wait for 1 ns; r.z.b <= 5; r.z.a <= 6; wait for 1 ns; r.x <= 2; r.z.a <= 1; wait; end process; end architecture;
gpl-3.0
973bdefc1364be21af45c8943e09af6c
0.500888
3.311765
false
false
false
false
tgingold/ghdl
testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_mincode.vhd
2
1,457
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity p_jinfo_ac_dhuff_tbl_mincode is port ( wa0_data : in std_logic_vector(8 downto 0); wa0_addr : in std_logic_vector(6 downto 0); clk : in std_logic; ra0_addr : in std_logic_vector(6 downto 0); ra0_data : out std_logic_vector(8 downto 0); wa0_en : in std_logic ); end p_jinfo_ac_dhuff_tbl_mincode; architecture augh of p_jinfo_ac_dhuff_tbl_mincode is -- Embedded RAM type ram_type is array (0 to 127) of std_logic_vector(8 downto 0); signal ram : ram_type := (others => (others => '0')); -- Little utility functions to make VHDL syntactically correct -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. -- This happens when accessing arrays with <= 2 cells, for example. function to_integer(B: std_logic) return integer is variable V: std_logic_vector(0 to 0); begin V(0) := B; return to_integer(unsigned(V)); end; function to_integer(V: std_logic_vector) return integer is begin return to_integer(unsigned(V)); end; begin -- Sequential process -- It handles the Writes process (clk) begin if rising_edge(clk) then -- Write to the RAM -- Note: there should be only one port. if wa0_en = '1' then ram( to_integer(wa0_addr) ) <= wa0_data; end if; end if; end process; -- The Read side (the outputs) ra0_data <= ram( to_integer(ra0_addr) ); end architecture;
gpl-2.0
2e0a52fcc107a324b2e87a7151692f61
0.676047
2.86811
false
false
false
false
nickg/nvc
test/simp/issue437.vhd
1
1,435
entity SAMPLE is generic ( DATA_BITS : integer := 0 ); port ( DATA : bit_vector(DATA_BITS-1 downto 0) ); end entity; architecture RTL of SAMPLE is begin end RTL; entity issue437 is generic( DATA_BITS : integer := 8 ); end entity; architecture MODEL of issue437 is type VEC_RANGE_TYPE is record VAL_LO : integer; VAL_HI : integer; DATA_LO : integer; DATA_HI : integer; end record; function SET_VEC_RANGE return VEC_RANGE_TYPE is variable v_pos : integer; variable d_pos : integer; variable v : VEC_RANGE_TYPE; procedure SET_DATA_RANGE(DATA_RANGE: inout VEC_RANGE_TYPE; BITS: in integer) is begin v_pos := v_pos + 1; d_pos := d_pos + BITS + 1; end procedure; begin v_pos := 0; d_pos := 0; v.VAL_LO := v_pos; v.DATA_LO := d_pos; SET_DATA_RANGE(v, DATA_BITS); v.VAL_HI := v_pos - 1; v.DATA_HI := d_pos - 1; return v; end function; constant VEC_RANGE : VEC_RANGE_TYPE := SET_VEC_RANGE; signal data : bit_vector(VEC_RANGE.DATA_HI downto VEC_RANGE.DATA_LO); begin U: entity WORK.SAMPLE generic map(DATA_BITS => data'length) port map(DATA => data); end MODEL;
gpl-3.0
503b7af5befe67f4daf3d90d40227c9e
0.513589
3.569652
false
false
false
false
tgingold/ghdl
testsuite/synth/synth60/leds_wrapper_arch_comp_inst.vhdl
1
438
architecture rtl_comp_inst of leds_wrapper is component leds is port (clk : in std_logic; led1, led2, led3, led4, led5, led6, led7, led8 : out std_logic); end component; begin leds_comp_inst : leds port map( clk => clk, led1 => led1, led2 => led2, led3 => led3, led4 => led4, led5 => led5, led6 => led6, led7 => led7, led8 => led8 ); end architecture;
gpl-2.0
8f00e4db3681d444620841401b244fa1
0.543379
3.084507
false
false
false
false
tgingold/ghdl
testsuite/gna/issue828/test.vhdl
1
849
library ieee; use ieee.std_logic_1164.all; entity test is port( tx : out std_logic); end entity; architecture tb of test is begin process procedure transmit(data : std_logic_vector; signal tx : out std_logic) is variable norm : std_logic_vector(data'length - 1 downto 0) := data; procedure send(value : std_logic) is begin tx <= value; wait for 10 ns; end procedure; variable count : natural := 0; begin report natural'image (norm'left); report natural'image (norm'right); for i in norm'reverse_range loop send(norm(i)); report to_string(i); count := count + 1; end loop; assert count = 8 severity failure; end procedure; begin transmit(x"55", tx); wait; end process; end architecture;
gpl-2.0
b9839511ea65d5346b6e0e1e1722b5e3
0.594817
3.894495
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd
4
1,981
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA package inline_20_types is -- code from book: type FIFO_status is record nearly_full, nearly_empty, full, empty : bit; end record FIFO_status; -- end of code from book end package inline_20_types; ---------------------------------------------------------------- use work.inline_20_types.all; entity FIFO is port ( status : out FIFO_status; other_ports : out bit ); end entity FIFO; ---------------------------------------------------------------- entity inline_20 is end entity inline_20; ---------------------------------------------------------------- use work.inline_20_types.all; architecture test of inline_20 is signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit; begin -- code from book: DMA_buffer : entity work.FIFO port map ( -- . . ., status.nearly_full => start_flush, status.nearly_empty => end_flush, status.full => DMA_buffer_full, status.empty => DMA_buffer_empty, -- . . . ); -- not in book other_ports => open ); -- end not in book -- end of code from book end architecture test;
gpl-2.0
b02794b92602b85e4681430fba0d8853
0.596164
4.269397
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd
4
1,922
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity inline_14 is end entity inline_14; ---------------------------------------------------------------- architecture test of inline_14 is signal PC, functional_next_PC, equivalent_next_PC : integer := 0; begin block_3_p : block is port ( next_PC : out integer ); port map ( next_PC => functional_next_PC ); begin -- code from book: PC_incr : next_PC <= PC + 4 after 5 ns; -- end of code from book end block block_3_p; ---------------- block_3_q : block is port ( next_PC : out integer ); port map ( next_PC => equivalent_next_PC ); begin -- code from book: PC_incr : process is begin next_PC <= PC + 4 after 5 ns; wait on PC; end process PC_incr; -- end of code from book end block block_3_q; ---------------- stimulus : process is begin for i in 1 to 10 loop PC <= i after 20 ns; wait for 20 ns; end loop; wait; end process stimulus; verifier : assert functional_next_PC = equivalent_next_PC report "Functional and equivalent models give different results"; end architecture test;
gpl-2.0
29178cd062d4911495c1dafebc5f7201
0.635796
4.037815
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/doHistStretch.autotb.vhd
1
64,442
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; entity apatb_doHistStretch_top is generic ( AUTOTB_CLOCK_PERIOD_DIV2 : TIME := 5.00 ns; AUTOTB_TVIN_inStream_V_data_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_data_V.dat"; AUTOTB_TVIN_inStream_V_keep_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_keep_V.dat"; AUTOTB_TVIN_inStream_V_strb_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_strb_V.dat"; AUTOTB_TVIN_inStream_V_user_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_user_V.dat"; AUTOTB_TVIN_inStream_V_last_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_last_V.dat"; AUTOTB_TVIN_inStream_V_id_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_id_V.dat"; AUTOTB_TVIN_inStream_V_dest_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_dest_V.dat"; AUTOTB_TVIN_outStream_V_data_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_outStream_V_data_V.dat"; AUTOTB_TVIN_outStream_V_keep_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_outStream_V_keep_V.dat"; AUTOTB_TVIN_outStream_V_strb_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_outStream_V_strb_V.dat"; AUTOTB_TVIN_outStream_V_user_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_outStream_V_user_V.dat"; AUTOTB_TVIN_outStream_V_last_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_outStream_V_last_V.dat"; AUTOTB_TVIN_outStream_V_id_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_outStream_V_id_V.dat"; AUTOTB_TVIN_outStream_V_dest_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_outStream_V_dest_V.dat"; AUTOTB_TVIN_xMin : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_xMin.dat"; AUTOTB_TVIN_xMax : STRING := "../tv/cdatafile/c.doHistStretch.autotvin_xMax.dat"; AUTOTB_TVIN_inStream_V_data_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_inStream_V_data_V.dat"; AUTOTB_TVIN_inStream_V_keep_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_inStream_V_keep_V.dat"; AUTOTB_TVIN_inStream_V_strb_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_inStream_V_strb_V.dat"; AUTOTB_TVIN_inStream_V_user_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_inStream_V_user_V.dat"; AUTOTB_TVIN_inStream_V_last_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_inStream_V_last_V.dat"; AUTOTB_TVIN_inStream_V_id_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_inStream_V_id_V.dat"; AUTOTB_TVIN_inStream_V_dest_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_inStream_V_dest_V.dat"; AUTOTB_TVIN_outStream_V_data_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_outStream_V_data_V.dat"; AUTOTB_TVIN_outStream_V_keep_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_outStream_V_keep_V.dat"; AUTOTB_TVIN_outStream_V_strb_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_outStream_V_strb_V.dat"; AUTOTB_TVIN_outStream_V_user_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_outStream_V_user_V.dat"; AUTOTB_TVIN_outStream_V_last_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_outStream_V_last_V.dat"; AUTOTB_TVIN_outStream_V_id_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_outStream_V_id_V.dat"; AUTOTB_TVIN_outStream_V_dest_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_outStream_V_dest_V.dat"; AUTOTB_TVIN_xMin_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_xMin.dat"; AUTOTB_TVIN_xMax_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvin_xMax.dat"; AUTOTB_TVOUT_outStream_V_data_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvout_outStream_V_data_V.dat"; AUTOTB_TVOUT_outStream_V_keep_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvout_outStream_V_keep_V.dat"; AUTOTB_TVOUT_outStream_V_strb_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvout_outStream_V_strb_V.dat"; AUTOTB_TVOUT_outStream_V_user_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvout_outStream_V_user_V.dat"; AUTOTB_TVOUT_outStream_V_last_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvout_outStream_V_last_V.dat"; AUTOTB_TVOUT_outStream_V_id_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvout_outStream_V_id_V.dat"; AUTOTB_TVOUT_outStream_V_dest_V : STRING := "../tv/cdatafile/c.doHistStretch.autotvout_outStream_V_dest_V.dat"; AUTOTB_TVOUT_outStream_V_data_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_data_V.dat"; AUTOTB_TVOUT_outStream_V_keep_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_keep_V.dat"; AUTOTB_TVOUT_outStream_V_strb_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_strb_V.dat"; AUTOTB_TVOUT_outStream_V_user_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_user_V.dat"; AUTOTB_TVOUT_outStream_V_last_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_last_V.dat"; AUTOTB_TVOUT_outStream_V_id_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_id_V.dat"; AUTOTB_TVOUT_outStream_V_dest_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHistStretch.autotvout_outStream_V_dest_V.dat"; AUTOTB_LAT_RESULT_FILE : STRING := "doHistStretch.result.lat.rb"; AUTOTB_PER_RESULT_TRANS_FILE : STRING := "doHistStretch.performance.result.transaction.xml"; LENGTH_inStream_V_data_V : INTEGER := 262144; LENGTH_inStream_V_keep_V : INTEGER := 262144; LENGTH_inStream_V_strb_V : INTEGER := 262144; LENGTH_inStream_V_user_V : INTEGER := 262144; LENGTH_inStream_V_last_V : INTEGER := 262144; LENGTH_inStream_V_id_V : INTEGER := 262144; LENGTH_inStream_V_dest_V : INTEGER := 262144; LENGTH_outStream_V_data_V : INTEGER := 262144; LENGTH_outStream_V_keep_V : INTEGER := 262144; LENGTH_outStream_V_strb_V : INTEGER := 262144; LENGTH_outStream_V_user_V : INTEGER := 262144; LENGTH_outStream_V_last_V : INTEGER := 262144; LENGTH_outStream_V_id_V : INTEGER := 262144; LENGTH_outStream_V_dest_V : INTEGER := 262144; LENGTH_xMin : INTEGER := 1; LENGTH_xMax : INTEGER := 1; AUTOTB_TRANSACTION_NUM : INTEGER := 1 ); end apatb_doHistStretch_top; architecture behav of apatb_doHistStretch_top is signal AESL_clock : STD_LOGIC := '0'; signal rst : STD_LOGIC; signal start : STD_LOGIC := '0'; signal ce : STD_LOGIC; signal continue : STD_LOGIC := '0'; signal AESL_reset : STD_LOGIC := '0'; signal AESL_start : STD_LOGIC := '0'; signal AESL_ce : STD_LOGIC := '0'; signal AESL_continue : STD_LOGIC := '0'; signal AESL_ready : STD_LOGIC := '0'; signal AESL_idle : STD_LOGIC := '0'; signal AESL_done : STD_LOGIC := '0'; signal AESL_done_delay : STD_LOGIC := '0'; signal AESL_done_delay2 : STD_LOGIC := '0'; signal AESL_ready_delay : STD_LOGIC := '0'; signal ready : STD_LOGIC := '0'; signal ready_wire : STD_LOGIC := '0'; signal CTRL_BUS_AWADDR: STD_LOGIC_VECTOR (4 DOWNTO 0); signal CTRL_BUS_AWVALID: STD_LOGIC; signal CTRL_BUS_AWREADY: STD_LOGIC; signal CTRL_BUS_WVALID: STD_LOGIC; signal CTRL_BUS_WREADY: STD_LOGIC; signal CTRL_BUS_WDATA: STD_LOGIC_VECTOR (31 DOWNTO 0); signal CTRL_BUS_WSTRB: STD_LOGIC_VECTOR (3 DOWNTO 0); signal CTRL_BUS_ARADDR: STD_LOGIC_VECTOR (4 DOWNTO 0); signal CTRL_BUS_ARVALID: STD_LOGIC; signal CTRL_BUS_ARREADY: STD_LOGIC; signal CTRL_BUS_RVALID: STD_LOGIC; signal CTRL_BUS_RREADY: STD_LOGIC; signal CTRL_BUS_RDATA: STD_LOGIC_VECTOR (31 DOWNTO 0); signal CTRL_BUS_RRESP: STD_LOGIC_VECTOR (1 DOWNTO 0); signal CTRL_BUS_BVALID: STD_LOGIC; signal CTRL_BUS_BREADY: STD_LOGIC; signal CTRL_BUS_BRESP: STD_LOGIC_VECTOR (1 DOWNTO 0); signal CTRL_BUS_INTERRUPT: STD_LOGIC; signal ap_clk : STD_LOGIC; signal ap_rst_n : STD_LOGIC; signal inStream_TDATA: STD_LOGIC_VECTOR (7 DOWNTO 0); signal inStream_TVALID: STD_LOGIC; signal inStream_TREADY: STD_LOGIC; signal inStream_TKEEP: STD_LOGIC_VECTOR (0 DOWNTO 0); signal inStream_TSTRB: STD_LOGIC_VECTOR (0 DOWNTO 0); signal inStream_TUSER: STD_LOGIC_VECTOR (1 DOWNTO 0); signal inStream_TLAST: STD_LOGIC_VECTOR (0 DOWNTO 0); signal inStream_TID: STD_LOGIC_VECTOR (4 DOWNTO 0); signal inStream_TDEST: STD_LOGIC_VECTOR (5 DOWNTO 0); signal outStream_TDATA: STD_LOGIC_VECTOR (7 DOWNTO 0); signal outStream_TVALID: STD_LOGIC; signal outStream_TREADY: STD_LOGIC; signal outStream_TKEEP: STD_LOGIC_VECTOR (0 DOWNTO 0); signal outStream_TSTRB: STD_LOGIC_VECTOR (0 DOWNTO 0); signal outStream_TUSER: STD_LOGIC_VECTOR (1 DOWNTO 0); signal outStream_TLAST: STD_LOGIC_VECTOR (0 DOWNTO 0); signal outStream_TID: STD_LOGIC_VECTOR (4 DOWNTO 0); signal outStream_TDEST: STD_LOGIC_VECTOR (5 DOWNTO 0); signal ready_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0); signal done_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0); signal ready_initial : STD_LOGIC; signal ready_initial_n : STD_LOGIC; signal ready_last_n : STD_LOGIC; signal ready_delay_last_n : STD_LOGIC; signal done_delay_last_n : STD_LOGIC; signal interface_done : STD_LOGIC := '0'; -- Subtype for random state number, to prevent confusing it with true integers -- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines subtype T_RANDINT is integer range 1 to integer'high; type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER; shared variable AESL_mLatCnterIn : latency_record; shared variable AESL_mLatCnterOut : latency_record; shared variable AESL_mLatCnterIn_addr : INTEGER; shared variable AESL_mLatCnterOut_addr : INTEGER; shared variable AESL_clk_counter : INTEGER; signal reported_stuck : STD_LOGIC := '0'; shared variable reported_stuck_cnt : INTEGER := 0; component doHistStretch is port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; inStream_TDATA : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inStream_TVALID : IN STD_LOGIC; inStream_TREADY : OUT STD_LOGIC; inStream_TKEEP : IN STD_LOGIC_VECTOR (0 DOWNTO 0); inStream_TSTRB : IN STD_LOGIC_VECTOR (0 DOWNTO 0); inStream_TUSER : IN STD_LOGIC_VECTOR (1 DOWNTO 0); inStream_TLAST : IN STD_LOGIC_VECTOR (0 DOWNTO 0); inStream_TID : IN STD_LOGIC_VECTOR (4 DOWNTO 0); inStream_TDEST : IN STD_LOGIC_VECTOR (5 DOWNTO 0); outStream_TDATA : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); outStream_TVALID : OUT STD_LOGIC; outStream_TREADY : IN STD_LOGIC; outStream_TKEEP : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); outStream_TSTRB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); outStream_TUSER : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); outStream_TLAST : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); outStream_TID : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); outStream_TDEST : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC; s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC; s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR (4 DOWNTO 0); s_axi_CTRL_BUS_WVALID : IN STD_LOGIC; s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC; s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR (31 DOWNTO 0); s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR (3 DOWNTO 0); s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC; s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC; s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR (4 DOWNTO 0); s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC; s_axi_CTRL_BUS_RREADY : IN STD_LOGIC; s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC; s_axi_CTRL_BUS_BREADY : IN STD_LOGIC; s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); interrupt : OUT STD_LOGIC); end component; -- The signal of port xMin shared variable AESL_REG_xMin : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); -- The signal of port xMax shared variable AESL_REG_xMax : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal inStream_ready : STD_LOGIC := '0'; signal inStream_done : STD_LOGIC := '0'; signal axi_s_inStream_TVALID : STD_LOGIC := '0'; signal axi_s_inStream_TREADY : STD_LOGIC := '0'; signal reg_inStream_TVALID : STD_LOGIC := '0'; signal reg_inStream_TREADY : STD_LOGIC := '0'; signal ap_c_n_tvin_trans_num_inStream_V_data_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvin_trans_num_inStream_V_keep_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvin_trans_num_inStream_V_strb_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvin_trans_num_inStream_V_user_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvin_trans_num_inStream_V_last_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvin_trans_num_inStream_V_id_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvin_trans_num_inStream_V_dest_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal inStream_ready_reg : STD_LOGIC := '0'; component AESL_axi_s_inStream is port( clk : IN STD_LOGIC; reset : IN STD_LOGIC; TRAN_inStream_TDATA : OUT STD_LOGIC_VECTOR; inStream_TDATA_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_inStream_TKEEP : OUT STD_LOGIC_VECTOR; inStream_TKEEP_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_inStream_TSTRB : OUT STD_LOGIC_VECTOR; inStream_TSTRB_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_inStream_TUSER : OUT STD_LOGIC_VECTOR; inStream_TUSER_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_inStream_TLAST : OUT STD_LOGIC_VECTOR; inStream_TLAST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_inStream_TID : OUT STD_LOGIC_VECTOR; inStream_TID_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_inStream_TDEST : OUT STD_LOGIC_VECTOR; inStream_TDEST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_inStream_TVALID : OUT STD_LOGIC; TRAN_inStream_TREADY : IN STD_LOGIC; ready : IN STD_LOGIC; done : IN STD_LOGIC ); end component; signal outStream_ready : STD_LOGIC := '0'; signal outStream_done : STD_LOGIC := '0'; signal axi_s_outStream_TVALID : STD_LOGIC := '0'; signal axi_s_outStream_TREADY : STD_LOGIC := '0'; signal reg_outStream_TVALID : STD_LOGIC := '0'; signal reg_outStream_TREADY : STD_LOGIC := '0'; signal ap_c_n_tvout_trans_num_outStream_V_data_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvout_trans_num_outStream_V_keep_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvout_trans_num_outStream_V_strb_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvout_trans_num_outStream_V_user_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvout_trans_num_outStream_V_last_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvout_trans_num_outStream_V_id_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal ap_c_n_tvout_trans_num_outStream_V_dest_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32); signal outStream_ready_reg : STD_LOGIC := '0'; component AESL_axi_s_outStream is port( clk : IN STD_LOGIC; reset : IN STD_LOGIC; TRAN_outStream_TDATA : IN STD_LOGIC_VECTOR; outStream_TDATA_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_outStream_TKEEP : IN STD_LOGIC_VECTOR; outStream_TKEEP_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_outStream_TSTRB : IN STD_LOGIC_VECTOR; outStream_TSTRB_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_outStream_TUSER : IN STD_LOGIC_VECTOR; outStream_TUSER_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_outStream_TLAST : IN STD_LOGIC_VECTOR; outStream_TLAST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_outStream_TID : IN STD_LOGIC_VECTOR; outStream_TID_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_outStream_TDEST : IN STD_LOGIC_VECTOR; outStream_TDEST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TRAN_outStream_TVALID : IN STD_LOGIC; TRAN_outStream_TREADY : OUT STD_LOGIC; ready : IN STD_LOGIC; done : IN STD_LOGIC ); end component; signal AESL_slave_output_done : STD_LOGIC; signal AESL_slave_start : STD_LOGIC; signal AESL_slave_write_start_in : STD_LOGIC; signal AESL_slave_write_start_finish : STD_LOGIC; signal AESL_slave_ready : STD_LOGIC; signal slave_start_status : STD_LOGIC := '0'; signal start_rise : STD_LOGIC := '0'; signal ready_rise : STD_LOGIC := '0'; signal slave_done_status : STD_LOGIC := '0'; signal CTRL_BUS_write_data_finish : STD_LOGIC; component AESL_AXI_SLAVE_CTRL_BUS is port( clk : IN STD_LOGIC; reset : IN STD_LOGIC; TRAN_s_axi_CTRL_BUS_AWADDR : OUT STD_LOGIC_VECTOR; TRAN_s_axi_CTRL_BUS_AWVALID : OUT STD_LOGIC; TRAN_s_axi_CTRL_BUS_AWREADY : IN STD_LOGIC; TRAN_s_axi_CTRL_BUS_WVALID : OUT STD_LOGIC; TRAN_s_axi_CTRL_BUS_WREADY : IN STD_LOGIC; TRAN_s_axi_CTRL_BUS_WDATA : OUT STD_LOGIC_VECTOR; TRAN_s_axi_CTRL_BUS_WSTRB : OUT STD_LOGIC_VECTOR; TRAN_s_axi_CTRL_BUS_ARADDR : OUT STD_LOGIC_VECTOR; TRAN_s_axi_CTRL_BUS_ARVALID : OUT STD_LOGIC; TRAN_s_axi_CTRL_BUS_ARREADY : IN STD_LOGIC; TRAN_s_axi_CTRL_BUS_RVALID : IN STD_LOGIC; TRAN_s_axi_CTRL_BUS_RREADY : OUT STD_LOGIC; TRAN_s_axi_CTRL_BUS_RDATA : IN STD_LOGIC_VECTOR; TRAN_s_axi_CTRL_BUS_RRESP : IN STD_LOGIC_VECTOR; TRAN_s_axi_CTRL_BUS_BVALID : IN STD_LOGIC; TRAN_s_axi_CTRL_BUS_BREADY : OUT STD_LOGIC; TRAN_s_axi_CTRL_BUS_BRESP : IN STD_LOGIC_VECTOR; TRAN_CTRL_BUS_interrupt : IN STD_LOGIC; TRAN_CTRL_BUS_write_data_finish : OUT STD_LOGIC; TRAN_CTRL_BUS_ready_out : OUT STD_LOGIC; TRAN_CTRL_BUS_ready_in : IN STD_LOGIC; TRAN_CTRL_BUS_done_out : OUT STD_LOGIC; TRAN_CTRL_BUS_idle_out : OUT STD_LOGIC; TRAN_CTRL_BUS_write_start_in : IN STD_LOGIC; TRAN_CTRL_BUS_write_start_finish : OUT STD_LOGIC; TRAN_CTRL_BUS_transaction_done_in : IN STD_LOGIC; TRAN_CTRL_BUS_start_in : IN STD_LOGIC ); end component; procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is variable whitespace : CHARACTER; variable i : INTEGER; variable ok: BOOLEAN; variable buff: STRING(1 to token'length); begin ok := false; i := 1; loop_main: while not endfile(textfile) loop if textline = null or textline'length = 0 then readline(textfile, textline); end if; loop_remove_whitespace: while textline'length > 0 loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then read(textline, whitespace); else exit loop_remove_whitespace; end if; end loop; loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then exit loop_aesl_read_token; else read(textline, buff(i)); i := i + 1; end if; ok := true; end loop; if ok = true then exit loop_main; end if; end loop; buff(i) := ' '; token := buff; token_len:= i-1; end procedure esl_read_token; procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING) is variable i : INTEGER; begin esl_read_token (textfile, textline, token, i); end procedure esl_read_token; function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0); variable idx : integer := 3; begin ret := (others => '0'); if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then report "Error! The format of hex number is not initialed by 0x"; end if; while true loop if (data_width > 4) then case RHS(idx) is when '0' => ret := ret(data_width - 5 downto 0) & "0000"; when '1' => ret := ret(data_width - 5 downto 0) & "0001"; when '2' => ret := ret(data_width - 5 downto 0) & "0010"; when '3' => ret := ret(data_width - 5 downto 0) & "0011"; when '4' => ret := ret(data_width - 5 downto 0) & "0100"; when '5' => ret := ret(data_width - 5 downto 0) & "0101"; when '6' => ret := ret(data_width - 5 downto 0) & "0110"; when '7' => ret := ret(data_width - 5 downto 0) & "0111"; when '8' => ret := ret(data_width - 5 downto 0) & "1000"; when '9' => ret := ret(data_width - 5 downto 0) & "1001"; when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010"; when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011"; when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100"; when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101"; when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110"; when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111"; when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 4) then case RHS(idx) is when '0' => ret := "0000"; when '1' => ret := "0001"; when '2' => ret := "0010"; when '3' => ret := "0011"; when '4' => ret := "0100"; when '5' => ret := "0101"; when '6' => ret := "0110"; when '7' => ret := "0111"; when '8' => ret := "1000"; when '9' => ret := "1001"; when 'a' | 'A' => ret := "1010"; when 'b' | 'B' => ret := "1011"; when 'c' | 'C' => ret := "1100"; when 'd' | 'D' => ret := "1101"; when 'e' | 'E' => ret := "1110"; when 'f' | 'F' => ret := "1111"; when 'x' | 'X' => ret := "XXXX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 3) then case RHS(idx) is when '0' => ret := "000"; when '1' => ret := "001"; when '2' => ret := "010"; when '3' => ret := "011"; when '4' => ret := "100"; when '5' => ret := "101"; when '6' => ret := "110"; when '7' => ret := "111"; when 'x' | 'X' => ret := "XXX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 2) then case RHS(idx) is when '0' => ret := "00"; when '1' => ret := "01"; when '2' => ret := "10"; when '3' => ret := "11"; when 'x' | 'X' => ret := "XX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 1) then case RHS(idx) is when '0' => ret := "0"; when '1' => ret := "1"; when 'x' | 'X' => ret := "X"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; else report string'("Wrong data_width."); return ret; end if; idx := idx + 1; end loop; return ret; end function; function esl_str_dec2int (RHS : STRING) return INTEGER is variable ret : integer; variable idx : integer := 1; begin ret := 0; while true loop case RHS(idx) is when '0' => ret := ret * 10 + 0; when '1' => ret := ret * 10 + 1; when '2' => ret := ret * 10 + 2; when '3' => ret := ret * 10 + 3; when '4' => ret := ret * 10 + 4; when '5' => ret := ret * 10 + 5; when '6' => ret := ret * 10 + 6; when '7' => ret := ret * 10 + 7; when '8' => ret := ret * 10 + 8; when '9' => ret := ret * 10 + 9; when ' ' => return ret; when others => report "Wrong dec char " & RHS(idx); return ret; end case; idx := idx + 1; end loop; return ret; end esl_str_dec2int; function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is constant str_len : integer := (lv'length + 3)/4; variable ret : STRING (1 to str_len); variable i, tmp: INTEGER; variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0); variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0); begin normal_lv := lv; for i in 1 to str_len loop if(i = 1) then if((lv'length mod 4) = 3) then tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3); case tmp_lv(2 downto 0) is when "000" => ret(i) := '0'; when "001" => ret(i) := '1'; when "010" => ret(i) := '2'; when "011" => ret(i) := '3'; when "100" => ret(i) := '4'; when "101" => ret(i) := '5'; when "110" => ret(i) := '6'; when "111" => ret(i) := '7'; when others => ret(i) := 'X'; end case; elsif((lv'length mod 4) = 2) then tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2); case tmp_lv(1 downto 0) is when "00" => ret(i) := '0'; when "01" => ret(i) := '1'; when "10" => ret(i) := '2'; when "11" => ret(i) := '3'; when others => ret(i) := 'X'; end case; elsif((lv'length mod 4) = 1) then tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1); case tmp_lv(0 downto 0) is when "0" => ret(i) := '0'; when "1" => ret(i) := '1'; when others=> ret(i) := 'X'; end case; elsif((lv'length mod 4) = 0) then tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4); case tmp_lv(3 downto 0) is when "0000" => ret(i) := '0'; when "0001" => ret(i) := '1'; when "0010" => ret(i) := '2'; when "0011" => ret(i) := '3'; when "0100" => ret(i) := '4'; when "0101" => ret(i) := '5'; when "0110" => ret(i) := '6'; when "0111" => ret(i) := '7'; when "1000" => ret(i) := '8'; when "1001" => ret(i) := '9'; when "1010" => ret(i) := 'a'; when "1011" => ret(i) := 'b'; when "1100" => ret(i) := 'c'; when "1101" => ret(i) := 'd'; when "1110" => ret(i) := 'e'; when "1111" => ret(i) := 'f'; when others => ret(i) := 'X'; end case; end if; else tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4); case tmp_lv(3 downto 0) is when "0000" => ret(i) := '0'; when "0001" => ret(i) := '1'; when "0010" => ret(i) := '2'; when "0011" => ret(i) := '3'; when "0100" => ret(i) := '4'; when "0101" => ret(i) := '5'; when "0110" => ret(i) := '6'; when "0111" => ret(i) := '7'; when "1000" => ret(i) := '8'; when "1001" => ret(i) := '9'; when "1010" => ret(i) := 'a'; when "1011" => ret(i) := 'b'; when "1100" => ret(i) := 'c'; when "1101" => ret(i) := 'd'; when "1110" => ret(i) := 'e'; when "1111" => ret(i) := 'f'; when others => ret(i) := 'X'; end case; end if; end loop; return ret; end function; -- purpose: initialise the random state variable based on an integer seed function init_rand(seed : integer) return T_RANDINT is variable result : T_RANDINT; begin -- If the seed is smaller than the minimum value of the random state variable, use the minimum value if seed < T_RANDINT'low then result := T_RANDINT'low; -- If the seed is larger than the maximum value of the random state variable, use the maximum value elsif seed > T_RANDINT'high then result := T_RANDINT'high; -- If the seed is within the range of the random state variable, just use the seed else result := seed; end if; -- Return the result return result; end init_rand; -- purpose: generate a random integer between min and max limits procedure rand_int(variable rand : inout T_RANDINT; constant minval : in integer; constant maxval : in integer; variable result : out integer ) is variable k, q : integer; variable real_rand : real; variable res : integer; begin -- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE -- Based on an example from Numerical Recipes in C, 2nd Edition, page 279 k := rand/127773; q := 16807*(rand-k*127773)-2836*k; if q < 0 then q := q + 2147483647; end if; rand := init_rand(q); -- Convert this integer to a real number in the range 0 to 1 real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low); -- Convert this real number to an integer in the range minval to maxval -- The +1 and -0.5 are to get equal probability of minval and maxval as other values res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval; -- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this if res < minval then res := minval; elsif res > maxval then res := maxval; end if; -- assign output result := res; end rand_int; begin AESL_inst_doHistStretch : doHistStretch port map ( s_axi_CTRL_BUS_AWADDR => CTRL_BUS_AWADDR, s_axi_CTRL_BUS_AWVALID => CTRL_BUS_AWVALID, s_axi_CTRL_BUS_AWREADY => CTRL_BUS_AWREADY, s_axi_CTRL_BUS_WVALID => CTRL_BUS_WVALID, s_axi_CTRL_BUS_WREADY => CTRL_BUS_WREADY, s_axi_CTRL_BUS_WDATA => CTRL_BUS_WDATA, s_axi_CTRL_BUS_WSTRB => CTRL_BUS_WSTRB, s_axi_CTRL_BUS_ARADDR => CTRL_BUS_ARADDR, s_axi_CTRL_BUS_ARVALID => CTRL_BUS_ARVALID, s_axi_CTRL_BUS_ARREADY => CTRL_BUS_ARREADY, s_axi_CTRL_BUS_RVALID => CTRL_BUS_RVALID, s_axi_CTRL_BUS_RREADY => CTRL_BUS_RREADY, s_axi_CTRL_BUS_RDATA => CTRL_BUS_RDATA, s_axi_CTRL_BUS_RRESP => CTRL_BUS_RRESP, s_axi_CTRL_BUS_BVALID => CTRL_BUS_BVALID, s_axi_CTRL_BUS_BREADY => CTRL_BUS_BREADY, s_axi_CTRL_BUS_BRESP => CTRL_BUS_BRESP, interrupt => CTRL_BUS_INTERRUPT, ap_clk => ap_clk, ap_rst_n => ap_rst_n, inStream_TDATA => inStream_TDATA, inStream_TVALID => inStream_TVALID, inStream_TREADY => inStream_TREADY, inStream_TKEEP => inStream_TKEEP, inStream_TSTRB => inStream_TSTRB, inStream_TUSER => inStream_TUSER, inStream_TLAST => inStream_TLAST, inStream_TID => inStream_TID, inStream_TDEST => inStream_TDEST, outStream_TDATA => outStream_TDATA, outStream_TVALID => outStream_TVALID, outStream_TREADY => outStream_TREADY, outStream_TKEEP => outStream_TKEEP, outStream_TSTRB => outStream_TSTRB, outStream_TUSER => outStream_TUSER, outStream_TLAST => outStream_TLAST, outStream_TID => outStream_TID, outStream_TDEST => outStream_TDEST ); -- Assignment for control signal ap_clk <= AESL_clock; ap_rst_n <= AESL_reset; AESL_reset <= rst; AESL_start <= start; AESL_ce <= ce; AESL_continue <= continue; AESL_slave_write_start_in <= slave_start_status and CTRL_BUS_write_data_finish; AESL_slave_start <= AESL_slave_write_start_finish; AESL_done <= slave_done_status ; slave_start_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '0') then slave_start_status <= '1'; else if (AESL_start = '1' ) then start_rise <= '1'; end if; if (start_rise = '1' and AESL_done = '1' ) then slave_start_status <= '1'; end if; if (AESL_slave_write_start_in = '1') then slave_start_status <= '0'; start_rise <= '0'; end if; end if; end if; end process; slave_ready_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '0') then AESL_slave_ready <= '0'; ready_rise <= '0'; else if (AESL_ready = '1' ) then ready_rise <= '1'; end if; if (ready_rise = '1' and AESL_done_delay = '1' ) then AESL_slave_ready <= '1'; end if; if (AESL_slave_ready = '1') then AESL_slave_ready <= '0'; ready_rise <= '0'; end if; end if; end if; end process; slave_done_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if (AESL_done = '1') then slave_done_status <= '0'; elsif (AESL_slave_output_done = '1' ) then slave_done_status <= '1'; end if; end if; end process; AESL_axi_s_inst_inStream : AESL_axi_s_inStream port map ( clk => AESL_clock, reset => AESL_reset, TRAN_inStream_TDATA => inStream_TDATA, inStream_TDATA_trans_num => ap_c_n_tvin_trans_num_inStream_V_data_V, TRAN_inStream_TKEEP => inStream_TKEEP, inStream_TKEEP_trans_num => ap_c_n_tvin_trans_num_inStream_V_keep_V, TRAN_inStream_TSTRB => inStream_TSTRB, inStream_TSTRB_trans_num => ap_c_n_tvin_trans_num_inStream_V_strb_V, TRAN_inStream_TUSER => inStream_TUSER, inStream_TUSER_trans_num => ap_c_n_tvin_trans_num_inStream_V_user_V, TRAN_inStream_TLAST => inStream_TLAST, inStream_TLAST_trans_num => ap_c_n_tvin_trans_num_inStream_V_last_V, TRAN_inStream_TID => inStream_TID, inStream_TID_trans_num => ap_c_n_tvin_trans_num_inStream_V_id_V, TRAN_inStream_TDEST => inStream_TDEST, inStream_TDEST_trans_num => ap_c_n_tvin_trans_num_inStream_V_dest_V, TRAN_inStream_TVALID => axi_s_inStream_TVALID, TRAN_inStream_TREADY => axi_s_inStream_TREADY, ready => inStream_ready, done => inStream_done ); inStream_ready <= inStream_ready_reg or ready_initial; inStream_done <= '0'; gen_reg_inStream_TVALID_proc : process variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin reg_inStream_TVALID <= axi_s_inStream_TVALID; while(true) loop wait until axi_s_inStream_TVALID'event; if(axi_s_inStream_TVALID = '1') then end if; reg_inStream_TVALID <= axi_s_inStream_TVALID; end loop; end process; inStream_TVALID <= reg_inStream_TVALID; axi_s_inStream_TREADY <= inStream_TREADY; AESL_axi_s_inst_outStream : AESL_axi_s_outStream port map ( clk => AESL_clock, reset => AESL_reset, TRAN_outStream_TDATA => outStream_TDATA, outStream_TDATA_trans_num => ap_c_n_tvout_trans_num_outStream_V_data_V, TRAN_outStream_TKEEP => outStream_TKEEP, outStream_TKEEP_trans_num => ap_c_n_tvout_trans_num_outStream_V_keep_V, TRAN_outStream_TSTRB => outStream_TSTRB, outStream_TSTRB_trans_num => ap_c_n_tvout_trans_num_outStream_V_strb_V, TRAN_outStream_TUSER => outStream_TUSER, outStream_TUSER_trans_num => ap_c_n_tvout_trans_num_outStream_V_user_V, TRAN_outStream_TLAST => outStream_TLAST, outStream_TLAST_trans_num => ap_c_n_tvout_trans_num_outStream_V_last_V, TRAN_outStream_TID => outStream_TID, outStream_TID_trans_num => ap_c_n_tvout_trans_num_outStream_V_id_V, TRAN_outStream_TDEST => outStream_TDEST, outStream_TDEST_trans_num => ap_c_n_tvout_trans_num_outStream_V_dest_V, TRAN_outStream_TVALID => axi_s_outStream_TVALID, TRAN_outStream_TREADY => axi_s_outStream_TREADY, ready => outStream_ready, done => outStream_done ); outStream_ready <= '0'; outStream_done <= AESL_done_delay; axi_s_outStream_TVALID <= outStream_TVALID; gen_reg_outStream_TREADY_proc : process variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin reg_outStream_TREADY <= '0'; while(true) loop wait until axi_s_outStream_TREADY'event; reg_outStream_TREADY <= axi_s_outStream_TREADY; end loop; end process; outStream_TREADY <= reg_outStream_TREADY; AESL_axi_slave_inst_CTRL_BUS : AESL_AXI_SLAVE_CTRL_BUS port map ( clk => AESL_clock, reset => AESL_reset, TRAN_s_axi_CTRL_BUS_AWADDR => CTRL_BUS_AWADDR, TRAN_s_axi_CTRL_BUS_AWVALID => CTRL_BUS_AWVALID, TRAN_s_axi_CTRL_BUS_AWREADY => CTRL_BUS_AWREADY, TRAN_s_axi_CTRL_BUS_WVALID => CTRL_BUS_WVALID, TRAN_s_axi_CTRL_BUS_WREADY => CTRL_BUS_WREADY, TRAN_s_axi_CTRL_BUS_WDATA => CTRL_BUS_WDATA, TRAN_s_axi_CTRL_BUS_WSTRB => CTRL_BUS_WSTRB, TRAN_s_axi_CTRL_BUS_ARADDR => CTRL_BUS_ARADDR, TRAN_s_axi_CTRL_BUS_ARVALID => CTRL_BUS_ARVALID, TRAN_s_axi_CTRL_BUS_ARREADY => CTRL_BUS_ARREADY, TRAN_s_axi_CTRL_BUS_RVALID => CTRL_BUS_RVALID, TRAN_s_axi_CTRL_BUS_RREADY => CTRL_BUS_RREADY, TRAN_s_axi_CTRL_BUS_RDATA => CTRL_BUS_RDATA, TRAN_s_axi_CTRL_BUS_RRESP => CTRL_BUS_RRESP, TRAN_s_axi_CTRL_BUS_BVALID => CTRL_BUS_BVALID, TRAN_s_axi_CTRL_BUS_BREADY => CTRL_BUS_BREADY, TRAN_s_axi_CTRL_BUS_BRESP => CTRL_BUS_BRESP, TRAN_CTRL_BUS_interrupt => CTRL_BUS_INTERRUPT, TRAN_CTRL_BUS_write_data_finish => CTRL_BUS_write_data_finish, TRAN_CTRL_BUS_ready_out => AESL_ready, TRAN_CTRL_BUS_ready_in => AESL_slave_ready, TRAN_CTRL_BUS_done_out => AESL_slave_output_done, TRAN_CTRL_BUS_idle_out => AESL_idle, TRAN_CTRL_BUS_write_start_in => AESL_slave_write_start_in, TRAN_CTRL_BUS_write_start_finish => AESL_slave_write_start_finish, TRAN_CTRL_BUS_transaction_done_in => AESL_done_delay, TRAN_CTRL_BUS_start_in => AESL_slave_start ); generate_ready_cnt_proc : process(ready_initial, AESL_clock) begin if(AESL_clock'event and AESL_clock = '0') then if(ready_initial = '1') then ready_cnt <= conv_std_logic_vector(1, 32); end if; elsif(AESL_clock'event and AESL_clock = '1') then if(ready_cnt /= AUTOTB_TRANSACTION_NUM) then if(AESL_ready = '1') then ready_cnt <= ready_cnt + 1; end if; end if; end if; end process; generate_done_cnt_proc : process(AESL_reset, AESL_clock) begin if(AESL_reset = '0') then done_cnt <= (others => '0'); elsif(AESL_clock'event and AESL_clock = '1') then if(done_cnt /= AUTOTB_TRANSACTION_NUM) then if(AESL_done = '1') then done_cnt <= done_cnt + 1; end if; end if; end if; end process; generate_sim_done_proc : process begin while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; assert false report "simulation done!" severity note; assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure; wait; end process; gen_clock_proc : process begin AESL_clock <= '0'; while(true) loop wait for AUTOTB_CLOCK_PERIOD_DIV2; AESL_clock <= not AESL_clock; end loop; wait; end process; gen_reset_proc : process variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin rst <= '0'; wait for 100 ns; for i in 1 to 3 loop wait until AESL_clock'event and AESL_clock = '1'; end loop; rst <= '1'; wait; end process; gen_start_proc : process variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin start <= '0'; ce <= '1'; wait until AESL_reset = '1'; wait until (AESL_clock'event and AESL_clock = '1'); start <= '1'; while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop wait until (AESL_clock'event and AESL_clock = '1'); if(AESL_ready = '1') then start <= '0'; start <= '1'; end if; end loop; start <= '0'; wait; end process; gen_continue_proc : process(AESL_done) begin continue <= AESL_done; end process; gen_AESL_ready_delay_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '0') then AESL_ready_delay <= '0'; else AESL_ready_delay <= AESL_ready; end if; end if; end process; gen_ready_initial_proc : process begin ready_initial <= '0'; wait until AESL_start = '1'; ready_initial <= '1'; wait until AESL_clock'event and AESL_clock = '1'; ready_initial <= '0'; wait; end process; ready_last_n_proc : process begin ready_last_n <= '1'; while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop wait until AESL_clock'event and AESL_clock = '1'; end loop; ready_last_n <= '0'; wait; end process; gen_ready_delay_n_last_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '0') then ready_delay_last_n <= '0'; else ready_delay_last_n <= ready_last_n; end if; end if; end process; ready <= (ready_initial or AESL_ready_delay); ready_wire <= ready_initial or AESL_ready_delay; done_delay_last_n <= '0' when done_cnt = AUTOTB_TRANSACTION_NUM else '1'; gen_done_delay_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '0') then AESL_done_delay <= '0'; AESL_done_delay2 <= '0'; else AESL_done_delay <= AESL_done and done_delay_last_n; AESL_done_delay2 <= AESL_done_delay; end if; end if; end process; gen_interface_done : process(ready, AESL_ready_delay, AESL_done_delay) begin if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then interface_done <= AESL_ready_delay; elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then interface_done <= AESL_done_delay; else interface_done <= '0'; end if; end process; proc_gen_inStream_internal_ready : process variable internal_trans_num : INTEGER; begin wait until AESL_reset = '1'; wait until ready_initial = '1'; inStream_ready_reg <= '0'; wait until AESL_clock'event and AESL_clock = '1'; internal_trans_num := 1; while(internal_trans_num /= AUTOTB_TRANSACTION_NUM + 1) loop if (true and ap_c_n_tvin_trans_num_inStream_V_data_V > internal_trans_num and ap_c_n_tvin_trans_num_inStream_V_keep_V > internal_trans_num and ap_c_n_tvin_trans_num_inStream_V_strb_V > internal_trans_num and ap_c_n_tvin_trans_num_inStream_V_user_V > internal_trans_num and ap_c_n_tvin_trans_num_inStream_V_last_V > internal_trans_num and ap_c_n_tvin_trans_num_inStream_V_id_V > internal_trans_num and ap_c_n_tvin_trans_num_inStream_V_dest_V > internal_trans_num ) then inStream_ready_reg <= '1'; wait until AESL_clock'event and AESL_clock = '1'; inStream_ready_reg <= '0'; internal_trans_num := internal_trans_num + 1; else wait until AESL_clock'event and AESL_clock = '1'; end if; end loop; inStream_ready_reg <= '0'; wait; end process; -- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor write_output_transactor_outStream_V_data_V_runtime_proc : process file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); begin file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_data_V_out_wrapc, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_data_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[runtime]]]")); writeline(fp, token_line); file_close(fp); while done_cnt /= AUTOTB_TRANSACTION_NUM loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_data_V_out_wrapc, APPEND_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_data_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[/runtime]]]")); writeline(fp, token_line); file_close(fp); wait; end process; -- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor write_output_transactor_outStream_V_keep_V_runtime_proc : process file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); begin file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_keep_V_out_wrapc, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_keep_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[runtime]]]")); writeline(fp, token_line); file_close(fp); while done_cnt /= AUTOTB_TRANSACTION_NUM loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_keep_V_out_wrapc, APPEND_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_keep_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[/runtime]]]")); writeline(fp, token_line); file_close(fp); wait; end process; -- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor write_output_transactor_outStream_V_strb_V_runtime_proc : process file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); begin file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_strb_V_out_wrapc, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_strb_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[runtime]]]")); writeline(fp, token_line); file_close(fp); while done_cnt /= AUTOTB_TRANSACTION_NUM loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_strb_V_out_wrapc, APPEND_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_strb_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[/runtime]]]")); writeline(fp, token_line); file_close(fp); wait; end process; -- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor write_output_transactor_outStream_V_user_V_runtime_proc : process file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); begin file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_user_V_out_wrapc, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_user_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[runtime]]]")); writeline(fp, token_line); file_close(fp); while done_cnt /= AUTOTB_TRANSACTION_NUM loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_user_V_out_wrapc, APPEND_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_user_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[/runtime]]]")); writeline(fp, token_line); file_close(fp); wait; end process; -- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor write_output_transactor_outStream_V_last_V_runtime_proc : process file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); begin file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_last_V_out_wrapc, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_last_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[runtime]]]")); writeline(fp, token_line); file_close(fp); while done_cnt /= AUTOTB_TRANSACTION_NUM loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_last_V_out_wrapc, APPEND_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_last_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[/runtime]]]")); writeline(fp, token_line); file_close(fp); wait; end process; -- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor write_output_transactor_outStream_V_id_V_runtime_proc : process file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); begin file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_id_V_out_wrapc, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_id_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[runtime]]]")); writeline(fp, token_line); file_close(fp); while done_cnt /= AUTOTB_TRANSACTION_NUM loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_id_V_out_wrapc, APPEND_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_id_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[/runtime]]]")); writeline(fp, token_line); file_close(fp); wait; end process; -- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor write_output_transactor_outStream_V_dest_V_runtime_proc : process file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); begin file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_dest_V_out_wrapc, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_dest_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[runtime]]]")); writeline(fp, token_line); file_close(fp); while done_cnt /= AUTOTB_TRANSACTION_NUM loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; file_open(fstatus, fp, AUTOTB_TVOUT_outStream_V_dest_V_out_wrapc, APPEND_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_outStream_V_dest_V_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[/runtime]]]")); writeline(fp, token_line); file_close(fp); wait; end process; gen_clock_counter_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '0') then if(AESL_reset = '0') then AESL_clk_counter := 0; else AESL_clk_counter := AESL_clk_counter + 1; end if; end if; end process; gen_mLatcnterout_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '0') then AESL_mLatCnterOut_addr := 0; AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ; reported_stuck_cnt := 0; else if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter; AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1; reported_stuck <= '0'; end if; end if; end if; end process; gen_mLatcnterin_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '0') then AESL_mLatCnterIn_addr := 0; else if (AESL_slave_write_start_finish = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1) then AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter; AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1; end if; end if; end if; end process; gen_performance_check_proc : process variable transaction_counter : INTEGER; variable i : INTEGER; file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); variable latthistime : INTEGER; variable lattotal : INTEGER; variable latmax : INTEGER; variable latmin : INTEGER; variable thrthistime : INTEGER; variable thrtotal : INTEGER; variable thrmax : INTEGER; variable thrmin : INTEGER; variable lataver : INTEGER; variable thraver : INTEGER; type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER; variable lat_array : latency_record; variable thr_array : latency_record; begin i := 0; lattotal := 0; latmax := 0; latmin := 16#7fffffff#; lataver := 0; thrtotal := 0; thrmax := 0; thrmin := 16#7fffffff#; thraver := 0; wait until (AESL_clock'event and AESL_clock = '1'); wait until (AESL_reset = '1'); while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop wait until (AESL_clock'event and AESL_clock = '1'); end loop; wait for 0.001 ns; for i in 0 to AUTOTB_TRANSACTION_NUM - 1 loop latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i); lat_array(i) := latthistime; if (latthistime > latmax) then latmax := latthistime; end if; if (latthistime < latmin) then latmin := latthistime; end if; lattotal := lattotal + latthistime; if (AUTOTB_TRANSACTION_NUM = 1) then thrthistime := latthistime; else thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i); end if; thr_array(i) := thrthistime; if (thrthistime > thrmax) then thrmax := thrthistime; end if; if (thrthistime < thrmin) then thrmin := thrthistime; end if; thrtotal := thrtotal + thrthistime; end loop; lataver := lattotal / AUTOTB_TRANSACTION_NUM; thraver := thrtotal / AUTOTB_TRANSACTION_NUM; file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE); if (fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; if (AUTOTB_TRANSACTION_NUM = 1) then thrmax := 0; thrmin := 0; thraver := 0; write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"'); writeline(fp, token_line); write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"'); writeline(fp, token_line); else write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"'); writeline(fp, token_line); write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(latmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(latmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(lataver) & '"'); writeline(fp, token_line); end if; file_close(fp); file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line,string'(" latency interval")); writeline(fp, token_line); if (AUTOTB_TRANSACTION_NUM = 1) then i := 0; thr_array(i) := 0; write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) ); writeline(fp, token_line); else for i in 0 to AESL_mLatCnterOut_addr - 1 loop write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) ); writeline(fp, token_line); end loop; end if; file_close(fp); wait; end process; end behav;
gpl-3.0
69afbb1f7d23206fdb505d9ec12c178d
0.583346
3.443518
false
false
false
false
tgingold/ghdl
testsuite/gna/issue50/idct.d/pkg_tb.vhd
2
1,771
--test bench written by alban bourge @ tima library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package pkg_tb is --fsm state types type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop); --context descriptor subtype context_t is std_logic_vector(1 downto 0); --argument width and type of fsm instruction constant ARG_WIDTH : integer := 8; subtype argument_t is unsigned(ARG_WIDTH - 1 downto 0); type instruction is record state : state_t; context_uut : context_t; arg : argument_t; end record; --reset instruction constant instr_rst : instruction := (state => Rst, context_uut => (others =>'0'), arg => (others =>'0')); --ram instruction type ram_instruction is record sel : std_logic; we : std_logic; addr_up : std_logic; addr_z : std_logic; end record; constant ram_instr_z : ram_instruction := (sel => '0', we => '0', addr_up => '0', addr_z => '0'); --assert unit instruction type assert_instruction is record en_feed : std_logic; en_check : std_logic; end record; constant assert_instr_z : assert_instruction := (en_feed => '0', en_check => '0'); --size of instruction table defined by PC_SIZE i.e. width of program counter constant PC_SIZE : integer := 5; type table_behavior is array (0 to 2**PC_SIZE - 1) of instruction; --constraint fixed by unit under test (augh dependant) --##CONSTRAINTS_START##-- subtype stdin_vector is std_logic_vector(31 downto 0); subtype stdout_vector is std_logic_vector(7 downto 0); subtype cp_vector is std_logic_vector(63 downto 0); --##CONSTRAINTS_END##-- --assert_uut vector number counter size constant VEC_NO_SIZE : integer := 20; end pkg_tb;
gpl-2.0
d55bf17f4cb6566d7de9e5c983c8c561
0.675889
3.117958
false
false
false
false
tgingold/ghdl
testsuite/gna/issue918/ent.vhdl
1
713
package power is type voltage is range integer'low to integer'high units uV; mV = 1000 uV; V = 1000 mV; kV = 1000 V; end units; end package; use work.power.all; entity LTC is generic ( V_MIN : voltage := 0 V; V_MAX : voltage := voltage'high ); port ( Vin : in voltage range 0 V to 15 V; Vout : out voltage range V_MIN to V_MAX ); end entity; architecture ic of LTC is begin Vout <= Vin * 0.95; end architecture; use work.power.all; entity board is port ( Vin : in voltage; Vout : out voltage ); end entity; architecture ic of board is begin U1: entity work.LTC port map ( Vin => 2.5 V, Vout => open ); end architecture;
gpl-2.0
5cb564509b8e22919bbf48c8ea1cc241
0.607293
3.226244
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd
4
1,617
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity limiter is generic ( limit_high : real := 4.8; -- upper limit limit_low : real := -4.8 ); -- lower limit port ( quantity input : in real; quantity output : out real); end entity limiter; ---------------------------------------------------------------- architecture simple of limiter is constant slope : real := 1.0e-4; begin if input > limit_high use -- upper limit exceeded, so limit input signal output == limit_high + slope*(input - limit_high); elsif input < limit_low use -- lower limit exceeded, so limit input signal output == limit_low + slope*(input - limit_low); else -- no limit exceeded, so pass input signal as is output == input; end use; break on input'above(limit_high), input'above(limit_low); end architecture simple;
gpl-2.0
432fcd81335e520f3a8aaed8b6612ea0
0.666048
4.210938
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_12.vhd
4
2,638
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_07_fg_07_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity fg_07_12 is end entity fg_07_12; architecture test of fg_07_12 is -- code from book procedure find_first_set ( v : in bit_vector; found : out boolean; first_set_index : out natural ) is begin for index in v'range loop if v(index) = '1' then found := true; first_set_index := index; return; end if; end loop; found := false; end procedure find_first_set; -- end code from book begin stimulus : process is -- code from book (in text) variable int_req : bit_vector (7 downto 0); variable top_priority : natural; variable int_pending : boolean; -- . . . -- end code from book constant block_count : natural := 16; -- code from book (in text) variable free_block_map : bit_vector(0 to block_count-1); variable first_free_block : natural; variable free_block_found : boolean; -- . . . -- end code from book begin int_req := "00010000"; -- code from book (in text) find_first_set ( int_req, int_pending, top_priority ); -- end code from book free_block_map := (others => '0'); -- code from book (in text) find_first_set ( free_block_map, free_block_found, first_free_block ); -- end code from book wait; end process stimulus; end architecture test;
gpl-2.0
d4186de7cb40273f5bf1018fe014e3e8
0.547763
4.32459
false
false
false
false
nickg/nvc
test/regress/issue412.vhd
1
1,289
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity issue412 is end issue412; architecture behavioral of issue412 is signal clk : std_logic := '0'; signal running : boolean := true; begin process (clk, running) begin if running then clk <= not clk after 5 ns; end if; end process; process -- Overloading the name is not the issue. procedure wr_data(data : signed) is begin -- A delay here seems to be necessary to cause the issue. wait until clk = '1'; -- wait for 10 ns; end; -- Calling from this function to the next seems -- to be required for the crash. procedure wr_data(data : integer) is begin wr_data(to_signed(data, 32)); end; variable data : signed(31 downto 0); begin -- Loop to 2000 works with line A below. -- for n in 1 to 2000 loop -- Loop to 3000 does not work with line A below. for n in 1 to 3000 loop -- Loop to 3000000 works fine with lines B below. -- for n in 1 to 3000000 loop wr_data(n); -- A -- data := to_signed(n, 32); -- B -- wr_data(data); -- B end loop; assert false report "Test OK" severity note; running <= false; wait; end process; end behavioral;
gpl-3.0
1003c6761542e06690fc8fd451c4c378
0.610551
3.672365
false
false
false
false
nickg/nvc
test/regress/vests17.vhd
1
10,127
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc856.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c01s03b01x00p12n01i00856pkg_b is constant zero : integer ; constant one : integer ; constant two : integer ; constant three: integer ; constant four : integer ; constant five : integer ; constant six : integer ; constant seven: integer ; constant eight: integer ; constant nine : integer ; constant fifteen: integer; end c01s03b01x00p12n01i00856pkg_b; package body c01s03b01x00p12n01i00856pkg_b is constant zero : integer := 0; constant one : integer := 1; constant two : integer := 2; constant three: integer := 3; constant four : integer := 4; constant five : integer := 5; constant six : integer := 6; constant seven: integer := 7; constant eight: integer := 8; constant nine : integer := 9; constant fifteen:integer:= 15; end c01s03b01x00p12n01i00856pkg_b; use work.c01s03b01x00p12n01i00856pkg_b.all; package c01s03b01x00p12n01i00856pkg_a is constant low_number : integer := 0; constant hi_number : integer := 3; subtype hi_to_low_range is integer range low_number to hi_number; type boolean_vector is array (natural range <>) of boolean; type severity_level_vector is array (natural range <>) of severity_level; type integer_vector is array (natural range <>) of integer; type real_vector is array (natural range <>) of real; type time_vector is array (natural range <>) of time; type natural_vector is array (natural range <>) of natural; type positive_vector is array (natural range <>) of positive; type record_std_package is record a: boolean; b: bit; c:character; d:severity_level; e:integer; f:real; g:time; h:natural; i:positive; end record; type array_rec_std is array (natural range <>) of record_std_package; type four_value is ('Z','0','1','X'); --enumerated type constant C1 : boolean := true; constant C2 : bit := '1'; constant C3 : character := 's'; constant C4 : severity_level := note; constant C5 : integer := 3; constant C6 : real := 3.0; constant C7 : time := 3 ns; constant C8 : natural := 1; constant C9 : positive := 1; constant dumy : bit_vector(zero to three) := "1010"; signal Sin1 : bit_vector(zero to five) ; signal Sin2 : boolean_vector(zero to five) ; signal Sin4 : severity_level_vector(zero to five) ; signal Sin5 : integer_vector(zero to five) ; signal Sin6 : real_vector(zero to five) ; signal Sin7 : time_vector(zero to five) ; signal Sin8 : natural_vector(zero to five) ; signal Sin9 : positive_vector(zero to five) ; signal Sin10: array_rec_std(zero to five) ; end c01s03b01x00p12n01i00856pkg_a; use work.c01s03b01x00p12n01i00856pkg_a.all; use work.c01s03b01x00p12n01i00856pkg_b.all; entity test is port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end; architecture test of test is begin sigout1 <= sigin1; sigout2 <= sigin2; sigout4 <= sigin4; sigout5 <= sigin5; sigout6 <= sigin6; sigout7 <= sigin7; sigout8 <= sigin8; sigout9 <= sigin9; sigout10 <= sigin10; end; configuration testbench of test is for test end for; end; use work.c01s03b01x00p12n01i00856pkg_a.all; use work.c01s03b01x00p12n01i00856pkg_b.all; ENTITY c01s03b01x00p12n01i00856ent IS END c01s03b01x00p12n01i00856ent; ARCHITECTURE c01s03b01x00p12n01i00856arch OF c01s03b01x00p12n01i00856ent IS component test port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end component; begin Sin1(zero) <='1'; Sin2(zero) <= true; Sin4(zero) <= note; Sin5(zero) <= 3; Sin6(zero) <= 3.0; Sin7(zero) <= 3 ns; Sin8(zero) <= 1; Sin9(zero) <= 1; Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9); K:block component test port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end component; BEGIN T5 : test port map ( Sin2(4),Sin2(5), Sin1(4),Sin1(5), Sin4(4),Sin4(5), Sin5(4),Sin5(5), Sin6(4),Sin6(5), Sin7(4),Sin7(5), Sin8(4),Sin8(5), Sin9(4),Sin9(5), Sin10(4),Sin10(5) ); G: for i in zero to three generate T1:test port map ( Sin2(i),Sin2(i+1), Sin1(i),Sin1(i+1), Sin4(i),Sin4(i+1), Sin5(i),Sin5(i+1), Sin6(i),Sin6(i+1), Sin7(i),Sin7(i+1), Sin8(i),Sin8(i+1), Sin9(i),Sin9(i+1), Sin10(i),Sin10(i+1) ); end generate; end block; TESTING: PROCESS BEGIN wait for 1 ns; assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure; assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure; assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure; assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure; assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure; assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure; assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure; assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure; assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure; assert NOT( Sin1(0) = sin1(5) and Sin2(0) = Sin2(5) and Sin4(0) = Sin4(5) and Sin5(0) = Sin5(5) and Sin6(0) = Sin6(5) and Sin7(0) = Sin7(5) and Sin8(0) = Sin8(5) and Sin9(0) = Sin9(5) and Sin10(0)= Sin10(0) ) report "***PASSED TEST: c01s03b01x00p12n01i00856" severity NOTE; assert ( Sin1(0) = sin1(5) and Sin2(0) = Sin2(5) and Sin4(0) = Sin4(5) and Sin5(0) = Sin5(5) and Sin6(0) = Sin6(5) and Sin7(0) = Sin7(5) and Sin8(0) = Sin8(5) and Sin9(0) = Sin9(5) and Sin10(0)= Sin10(0) ) report "***FAILED TEST: c01s03b01x00p12n01i00856 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p12n01i00856arch; configuration vests17 of c01s03b01x00p12n01i00856ent is for c01s03b01x00p12n01i00856arch for K for T5:test use configuration work.testbench; end for; for G(hi_to_low_range) for T1:test use configuration work.testbench; end for; end for; end for; end for; end;
gpl-3.0
99ec3e8a417a58cd52ecef20310c673e
0.596228
3.343348
false
true
false
false
tgingold/ghdl
testsuite/synth/const01/const02.vhdl
1
1,460
library ieee; use ieee.std_logic_1164.all; entity const02a is generic (init : std_logic_vector(31 downto 0) := x"10203040"); port (o : out std_logic_vector(0 to 31)); end const02a; architecture behav of const02a is type slv_array is array (natural range <>) of std_logic_vector(7 downto 0); function conv (v : std_logic_vector) return slv_array is variable r : slv_array(0 to v'length / 8 - 1); begin for i in 0 to r'length-1 loop r (i) := v(v'length - (i*8) - 1 downto v'length - (i*8) - 8); end loop; return r; end conv; constant res : slv_array (0 to 3) := conv (init); begin o (0 to 7) <= res (0); o (8 to 15) <= res (1); o (16 to 23) <= res (2); o (24 to 31) <= res (3); end behav; library ieee; use ieee.std_logic_1164.all; entity const02b is generic (init : std_logic_vector(31 downto 0)); port (o : out std_logic_vector(0 to 31)); end const02b; architecture behav of const02b is begin inst: entity work.const02a generic map (init => init) port map (o => o); end behav; library ieee; use ieee.std_logic_1164.all; package cst_pkg is constant init : std_logic_vector(31 downto 0) := x"10203040"; end cst_pkg; library ieee; use ieee.std_logic_1164.all; use work.cst_pkg.all; entity const02 is port (o : out std_logic_vector(0 to 31)); end const02; architecture behav of const02 is begin inst: entity work.const02b generic map (init => init) port map (o => o); end behav;
gpl-2.0
adf25d18421f4fe86fa05b95f2eec25a
0.65137
2.891089
false
false
false
false
tgingold/ghdl
testsuite/gna/bug017/case3.vhdl
2
643
entity case3 is end; architecture behav of case3 is subtype bv4 is bit_vector (1 to 4); type vec2 is array (natural range <>) of bv4; constant vects : vec2 := (x"0", x"4", x"9", x"3", x"a"); begin process variable i : natural := 0; begin for i in vects'range loop case bv4'(vects (i)) is when "0100" => report "value is 4"; wait for 4 ns; when "0011" => report "value is 3"; wait for 3 ns; when others => report "unknown value"; wait for 1 ns; end case; end loop; report "SUCCESS"; wait; end process; end behav;
gpl-2.0
fc924b124832b94afc1adc12d95d669c
0.538103
3.475676
false
false
false
false
tgingold/ghdl
testsuite/gna/issue1051/psi_tb_compare_pkg.vhd
1
8,736
------------------------------------------------------------------------------ -- Copyright (c) 2018 by Paul Scherrer Institute, Switzerland -- All rights reserved. -- Authors: Oliver Bruendler, Benoit Stef ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- Libraries ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.psi_tb_txt_util.all; ------------------------------------------------------------------------------ -- Package Header ------------------------------------------------------------------------------ package psi_tb_compare_pkg is -- returns an index string in the form "[3]" function IndexString( Index : integer) return string; -- std_logic_vector compare to integer procedure StdlvCompareInt ( Expected : in integer; Actual : in std_logic_vector; Msg : in string; IsSigned : in boolean := true; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: "); -- std_logic_vector compare to std_logic_vector procedure StdlvCompareStdlv (Expected : in std_logic_vector; Actual : in std_logic_vector; Msg : in string; Prefix : in string := "###ERROR###: "); -- std_logic compare std_logic procedure StdlCompare( Expected : in integer range 0 to 1; Actual : in std_logic; Msg : in string; Prefix : in string := "###ERROR###: "); -- integer compare to integer procedure IntCompare( Expected : in integer; Actual : in integer; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: "); -- real compare to real procedure RealCompare( Expected : in real; Actual : in real; Msg : in string; Tolerance : in real := 0.0; Prefix : in string := "###ERROR###: "); -- signed compare to signed procedure SignCompare ( Expected : in signed; Actual : in signed; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: "); -- unsigned compare to unsigned procedure UsignCompare (Expected : in unsigned; Actual : in unsigned; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: "); -- signed compare to integer procedure SignCompareInt ( Expected : in integer; Actual : in signed; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: "); -- unsigned compare to integer procedure UsignCompareInt ( Expected : in integer; Actual : in unsigned; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: "); end psi_tb_compare_pkg; ------------------------------------------------------------------------------ -- Package Body ------------------------------------------------------------------------------ package body psi_tb_compare_pkg is -- *** IndexString *** function IndexString( Index : integer) return string is begin return "[" & to_string(Index) & "]"; end function; -- *** StdlvCompareInt *** procedure StdlvCompareInt ( Expected : in integer; Actual : in std_logic_vector; Msg : in string; IsSigned : in boolean := true; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: ") is variable ActualInt_v : integer; variable ExpectedStdlv32_v : std_logic_vector(31 downto 0); variable ActualStdlv32_v : std_logic_vector(31 downto 0); begin -- Convert Input if IsSigned then ActualInt_v := to_integer(signed(Actual)); ExpectedStdlv32_v := std_logic_vector(to_signed(Expected, 32)); ActualStdlv32_v := std_logic_vector(to_signed(ActualInt_v, 32)); else ActualInt_v := to_integer(unsigned(Actual)); ExpectedStdlv32_v := std_logic_vector(to_unsigned(Expected, 32)); ActualStdlv32_v := std_logic_vector(to_unsigned(ActualInt_v, 32)); end if; -- Assertion assert (ActualInt_v >= Expected-Tolerance) and (ActualInt_v <= Expected+Tolerance) report Prefix & Msg & " [Expected " & integer'image(Expected) & "(0x" & hstr(ExpectedStdlv32_v) & ")" & ", Received " & integer'image(ActualInt_v) & "(0x" & hstr(ActualStdlv32_v) & ")" & ", Tolerance " & integer'image(Tolerance) & "]" severity error; end procedure; -- *** StdlvCompareStdlv *** procedure StdlvCompareStdlv ( Expected : in std_logic_vector; Actual : in std_logic_vector; Msg : in string; Prefix : in string := "###ERROR###: ") is constant Expected_c : std_logic_vector(Expected'length-1 downto 0) := Expected; constant Actual_c : std_logic_vector(Actual'length-1 downto 0) := Actual; begin -- Assertion assert Actual_c = Expected_c report Prefix & Msg & " [Expected " & str(Expected_c) & "(0x" & hstr(Expected_c) & ")" & ", Received " & str(Actual_c) & "(0x" & hstr(Actual_c) & ")" & "]" severity error; end procedure; -- *** StdlCompare *** procedure StdlCompare( Expected : in integer range 0 to 1; Actual : in std_logic; Msg : in string; Prefix : in string := "###ERROR###: ") is variable ExStdl_v : std_logic; begin if Expected = 0 then ExStdl_v := '0'; else ExStdl_v := '1'; end if; assert Actual = ExStdl_v report Prefix & Msg & " [Expected " & str(ExStdl_v) & ", Received " & str(Actual) & "]" severity error; end procedure; -- *** IntCompare *** procedure IntCompare( Expected : in integer; Actual : in integer; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: ") is begin assert (Actual >= Expected-Tolerance) and (Actual <= Expected+Tolerance) report Prefix & Msg & " [Expected " & to_string(Expected) & ", Received " & to_string(Actual) & ", Tolerance " & to_string(Tolerance) & "]" severity error; end procedure; -- *** RealCompare *** procedure RealCompare( Expected : in real; Actual : in real; Msg : in string; Tolerance : in real := 0.0; Prefix : in string := "###ERROR###: ") is begin assert (Actual >= Expected-Tolerance) and (Actual <= Expected+Tolerance) report Prefix & Msg & " [Expected " & to_string(Expected) & ", Received " & to_string(Actual) & ", Tolerance " & to_string(Tolerance) & "]" severity error; end procedure; -- *** SignCompare *** procedure SignCompare( Expected : in signed; Actual : in signed; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: ") is begin assert (Actual >= Expected-Tolerance) and (Actual <= Expected+Tolerance) report Prefix & Msg & " [Expected " & to_string(Expected) & ", Received " & to_string(Actual) & ", Tolerance " & to_string(Tolerance) & "]" severity error; end procedure; -- *** UsignCompare *** procedure UsignCompare( Expected : in unsigned; Actual : in unsigned; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: ") is begin assert (Actual >= Expected-Tolerance) and (Actual <= Expected+Tolerance) report Prefix & Msg & " [Expected " & to_string(Expected) & ", Received " & to_string(Actual) & ", Tolerance " & to_string(Tolerance) & "]" severity error; end procedure; -- *** SignCompareInt *** procedure SignCompareInt ( Expected : in integer; Actual : in signed; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: ") is begin StdlvCompareInt ( Expected => Expected, Actual => std_logic_vector(Actual), Msg => Msg, IsSigned => true, Tolerance => Tolerance, Prefix => Prefix); end procedure; -- *** UsignCompareInt *** procedure UsignCompareInt ( Expected : in integer; Actual : in unsigned; Msg : in string; Tolerance : in integer := 0; Prefix : in string := "###ERROR###: ") is begin StdlvCompareInt ( Expected => Expected, Actual => std_logic_vector(Actual), Msg => Msg, IsSigned => false, Tolerance => Tolerance, Prefix => Prefix); end procedure; end psi_tb_compare_pkg;
gpl-2.0
e9698e071ba1de05f2004a5baacc37d5
0.538004
3.56717
false
false
false
false
nickg/nvc
test/regress/guard1.vhd
1
517
entity guard1 is end entity; architecture test of guard1 is signal value : natural := 0; signal output : natural; begin b1: block (value < 10) is begin output <= guarded value * 2; end block; check: process is begin value <= 3; wait for 1 ns; assert output = 6; value <= 4; wait for 1 ns; assert output = 8; value <= 10; wait for 1 ns; assert output = 8; wait; end process; end architecture;
gpl-3.0
b9f4820f2b88b4de4ca1281013011237
0.533849
4.007752
false
false
false
false
nickg/nvc
test/eopt/source1.vhd
1
608
entity sub is port ( i : in bit; o : out bit ); end entity; architecture test of sub is begin o <= i; end architecture; ------------------------------------------------------------------------------- entity source1 is end entity; architecture test of source1 is signal x : bit; signal y : bit_vector(1 to 5); begin x <= '1'; foo: x <= '0'; -- Error y <= "10000"; y(2 to 3) <= "11"; -- Error sub1_i: entity work.sub port map ( x, y(4) ); sub2_i: entity work.sub port map ( x, y(2) ); end architecture;
gpl-3.0
fbe565163286c01792be11f513d63b12
0.442434
3.707317
false
true
false
false
Darkin47/Zynq-TX-UTT
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_skid2mm_buf.vhd
3
17,333
------------------------------------------------------------------------------- -- axi_datamover_skid2mm_buf.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_skid2mm_buf.vhd -- -- Description: -- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_wr_demux; ------------------------------------------------------------------------------- entity axi_datamover_skid2mm_buf is generic ( C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ; -- Width of the MMap Write Data bus (in bits) C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ; -- Width of the Stream Data bus (in bits) C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5 -- Width of the LS address bus needed to Demux the WSTRB ); port ( -- Clock and Reset Inputs ------------------------------------------- -- ACLK : In std_logic ; -- ARST : In std_logic ; -- --------------------------------------------------------------------- -- Slave Side (Wr Data Controller Input Side) ----------------------- -- S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); -- S_VALID : In std_logic ; -- S_READY : Out std_logic ; -- S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); -- S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); -- S_LAST : In std_logic ; -- --------------------------------------------------------------------- -- Master Side (MMap Write Data Output Side) ------------------------ M_VALID : Out std_logic ; -- M_READY : In std_logic ; -- M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); -- M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); -- M_LAST : Out std_logic -- --------------------------------------------------------------------- ); end entity axi_datamover_skid2mm_buf; architecture implementation of axi_datamover_skid2mm_buf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH; Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH; -- Signals decalrations ------------------------- Signal sig_reset_reg : std_logic := '0'; signal sig_spcl_s_ready_set : std_logic := '0'; signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_reg : std_logic := '0'; signal sig_skid_reg_en : std_logic := '0'; signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_mux_out : std_logic := '0'; signal sig_skid_mux_sel : std_logic := '0'; signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_reg_out : std_logic := '0'; signal sig_data_reg_out_en : std_logic := '0'; signal sig_m_valid_out : std_logic := '0'; signal sig_m_valid_dup : std_logic := '0'; signal sig_m_valid_comb : std_logic := '0'; signal sig_s_ready_out : std_logic := '0'; signal sig_s_ready_dup : std_logic := '0'; signal sig_s_ready_comb : std_logic := '0'; signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no"; begin --(architecture implementation) M_VALID <= sig_m_valid_out; S_READY <= sig_s_ready_out; M_STRB <= sig_strb_reg_out; M_LAST <= sig_last_reg_out; M_DATA <= sig_mirror_data_out; -- Assign the special S_READY FLOP set signal sig_spcl_s_ready_set <= sig_reset_reg; -- Generate the ouput register load enable control sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup); -- Generate the skid inpit register load enable control sig_skid_reg_en <= sig_s_ready_dup; -- Generate the skid mux select control sig_skid_mux_sel <= not(sig_s_ready_dup); -- Skid Mux sig_data_skid_mux_out <= sig_data_skid_reg When (sig_skid_mux_sel = '1') Else S_DATA; sig_strb_skid_mux_out <= sig_strb_skid_reg When (sig_skid_mux_sel = '1') --Else S_STRB; Else sig_wstrb_demux_out; sig_last_skid_mux_out <= sig_last_skid_reg When (sig_skid_mux_sel = '1') Else S_LAST; -- m_valid combinational logic sig_m_valid_comb <= S_VALID or (sig_m_valid_dup and (not(sig_s_ready_dup) or not(M_READY))); -- s_ready combinational logic sig_s_ready_comb <= M_READY or (sig_s_ready_dup and (not(sig_m_valid_dup) or not(S_VALID))); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_THE_RST -- -- Process Description: -- Register input reset -- ------------------------------------------------------------- REG_THE_RST : process (ACLK) begin if (ACLK'event and ACLK = '1') then sig_reset_reg <= ARST; end if; end process REG_THE_RST; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_READY_FLOP -- -- Process Description: -- Registers S_READY handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- S_READY_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_s_ready_out <= '0'; sig_s_ready_dup <= '0'; Elsif (sig_spcl_s_ready_set = '1') Then sig_s_ready_out <= '1'; sig_s_ready_dup <= '1'; else sig_s_ready_out <= sig_s_ready_comb; sig_s_ready_dup <= sig_s_ready_comb; end if; end if; end process S_READY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: M_VALID_FLOP -- -- Process Description: -- Registers M_VALID handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- M_VALID_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1' or sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA sig_m_valid_out <= '0'; sig_m_valid_dup <= '0'; else sig_m_valid_out <= sig_m_valid_comb; sig_m_valid_dup <= sig_m_valid_comb; end if; end if; end process M_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_DATA_REG -- -- Process Description: -- This process implements the Skid register for the -- Skid Buffer Data signals. -- ------------------------------------------------------------- SKID_DATA_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (sig_skid_reg_en = '1') then sig_data_skid_reg <= S_DATA; else null; -- hold current state end if; end if; end process SKID_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_CNTL_REG -- -- Process Description: -- This process implements the Output registers for the -- Skid Buffer Control signals -- ------------------------------------------------------------- SKID_CNTL_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_strb_skid_reg <= (others => '0'); sig_last_skid_reg <= '0'; elsif (sig_skid_reg_en = '1') then sig_strb_skid_reg <= sig_wstrb_demux_out; sig_last_skid_reg <= S_LAST; else null; -- hold current state end if; end if; end process SKID_CNTL_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_DATA_REG -- -- Process Description: -- This process implements the Output register for the -- Data signals. -- ------------------------------------------------------------- OUTPUT_DATA_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (sig_data_reg_out_en = '1') then sig_data_reg_out <= sig_data_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_CNTL_REG -- -- Process Description: -- This process implements the Output registers for the -- control signals. -- ------------------------------------------------------------- OUTPUT_CNTL_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_strb_reg_out <= (others => '0'); sig_last_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_strb_reg_out <= sig_strb_skid_mux_out; sig_last_reg_out <= sig_last_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_CNTL_REG; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_WR_DATA_MIRROR -- -- Process Description: -- Implement the Write Data Mirror structure -- -- Note that it is required that the Stream Width be less than -- or equal to the MMap WData width. -- ------------------------------------------------------------- DO_WR_DATA_MIRROR : process (sig_data_reg_out) begin for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1 downto C_SDATA_WIDTH*slice_index) <= sig_data_reg_out; end loop; end process DO_WR_DATA_MIRROR; ------------------------------------------------------------ -- Instance: I_WSTRB_DEMUX -- -- Description: -- Instance for the Write Strobe DeMux. -- ------------------------------------------------------------ I_WSTRB_DEMUX : entity axi_datamover_v5_1_10.axi_datamover_wr_demux generic map ( C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH , C_MMAP_DWIDTH => C_MDATA_WIDTH , C_STREAM_DWIDTH => C_SDATA_WIDTH ) port map ( wstrb_in => S_STRB , demux_wstrb_out => sig_wstrb_demux_out , debeat_saddr_lsb => S_ADDR_LSB ); end implementation;
gpl-3.0
65ab61ffc730a29a25ab06a85e20d421
0.470721
4.488089
false
false
false
false
makestuff/comm-fpga
ss/vhdl/comm_fpga_ss.vhdl
1
9,734
-- -- Copyright (C) 2013 Chris McClelland -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity comm_fpga_ss is generic ( DELAY_COUNT : natural := 3; -- cycles to delay rising edge signal for sender FIFO_DEPTH : natural := 1 -- 2**DEPTH gives number of words in FIFO ); port( clk_in : in std_logic; -- clock input (asynchronous with serial signals) reset_in : in std_logic; -- synchronous active-high reset input -- Serial interface -------------------------------------------------------------------------- serClk_in : in std_logic; -- serial clock (must have Freq < clk_in/2) serData_in : in std_logic; -- connected to Tx of microcontroller serData_out : out std_logic; -- connected to Tx of microcontroller -- Channel read/write interface -------------------------------------------------------------- chanAddr_out : out std_logic_vector(6 downto 0); -- the selected channel (0-127) -- Host >> FPGA pipe: h2fData_out : out std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel h2fValid_out : out std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData_out" h2fReady_in : in std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet" -- Host << FPGA pipe: f2hData_in : in std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel f2hValid_in : in std_logic; -- channel logic can drive this low to say "I don't have data ready for you" f2hReady_out : out std_logic -- '1' means "on the next clock rising edge, put your next byte of data on f2hData_in" ); end entity; architecture rtl of comm_fpga_ss is type StateType is ( S_IDLE, -- wait for requst from host & regster isRead & chanAddr S_GET_COUNT0, -- wait for count high byte S_GET_COUNT1, -- wait for count low byte S_WRITE, -- writing data to FPGA application S_WAIT_STOP, -- wait for the stop bit in preparation for a read S_WAIT_READ, -- wait for microcontroller to assert serData_sync, indicating readiness S_READ, -- send data to microcontroller S_END_READ -- wait for micro to deassert serData_sync, indicating acknowledgement ); signal state : StateType := S_IDLE; signal state_next : StateType; signal count : unsigned(16 downto 0) := (others => '0'); signal count_next : unsigned(16 downto 0); signal isRead : std_logic := '0'; signal isRead_next : std_logic; signal chanAddr : std_logic_vector(6 downto 0) := (others => '0'); signal chanAddr_next : std_logic_vector(6 downto 0); signal delayLine : std_logic_vector(DELAY_COUNT downto 0) := (others => '0'); signal serData_sync : std_logic := '1'; signal serClk_sync : std_logic := '0'; signal serClk_prev : std_logic := '0'; signal serDataIn : std_logic; signal serDataOut : std_logic; signal serClkFE : std_logic; signal recvData : std_logic_vector(7 downto 0); signal recvValid : std_logic; signal sendValid : std_logic; signal sendReady : std_logic; signal fifoInputData : std_logic_vector(7 downto 0); signal fifoInputValid : std_logic; signal fifoOutputValid : std_logic; begin -- Infer registers process(clk_in) begin if ( rising_edge(clk_in) ) then if ( reset_in = '1' ) then state <= S_IDLE; count <= (others => '0'); isRead <= '0'; chanAddr <= (others => '0'); serClk_sync <= '0'; serClk_prev <= '0'; serData_sync <= '1'; delayLine <= (others => '0'); else state <= state_next; count <= count_next; isRead <= isRead_next; chanAddr <= chanAddr_next; serClk_sync <= serClk_in; serClk_prev <= serClk_sync; serData_sync <= serData_in; delayLine <= delayLine(DELAY_COUNT-1 downto 0) & serClkFE; end if; end if; end process; -- Next state logic process( state, count, recvData, recvValid, sendReady, f2hValid_in, serDataOut, serData_sync, isRead, chanAddr, fifoOutputValid) begin state_next <= state; count_next <= count; isRead_next <= isRead; chanAddr_next <= chanAddr; fifoInputData <= (others => 'X'); fifoInputValid <= '0'; serData_out <= '1'; -- default not ready serDataIn <= serData_sync; f2hReady_out <= '0'; sendValid <= '0'; case state is -- Get the count high byte when S_GET_COUNT0 => serData_out <= '0'; -- ready if ( recvValid = '1' ) then count_next(15 downto 8) <= unsigned(recvData); state_next <= S_GET_COUNT1; end if; -- Get the count low byte when S_GET_COUNT1 => serData_out <= '0'; -- ready if ( recvValid = '1' ) then count_next(7 downto 0) <= unsigned(recvData); if ( count(15 downto 8) = x"00" and recvData = x"00" ) then count_next(16) <= '1'; else count_next(16) <= '0'; end if; if ( isRead = '1' ) then state_next <= S_WAIT_STOP; else state_next <= S_WRITE; end if; end if; -- Host is writing when S_WRITE => serData_out <= fifoOutputValid; if ( recvValid = '1' ) then -- We got a data byte from the host fifoInputData <= recvData; fifoInputValid <= '1'; count_next <= count - 1; if ( count = 1 ) then state_next <= S_IDLE; end if; end if; -- Wait for the stop bit in preparation for a read when S_WAIT_STOP => serDataIn <= '1'; -- isolate sync-recv unit from serData_in serData_out <= '1'; -- we'll start writing soon if ( serData_sync = '1' ) then -- Other side has started its stop bit, so proceed state_next <= S_WAIT_READ; end if; -- Wait for microcontroller to assert serData_sync, indicating readiness when S_WAIT_READ => serDataIn <= '1'; -- isolate sync-recv unit from serData_in serData_out <= '1'; -- we'll start writing soon if ( serData_sync = '0' ) then -- Other side is ready to receive, so proceed state_next <= S_READ; end if; -- Send "count" bytes of data, throttling if necessary when S_READ => serDataIn <= '1'; -- isolate sync-recv unit from serData_in serData_out <= serDataOut; if ( serData_sync = '0' ) then sendValid <= f2hValid_in; f2hReady_out <= sendReady; if ( f2hValid_in = '1' and sendReady = '1' ) then count_next <= count - 1; if ( count = 1 ) then state_next <= S_END_READ; end if; end if; end if; -- Wait for microcontroller to deassert serData_sync, indicating acknowledgement when S_END_READ => serDataIn <= '1'; -- isolate sync-recv unit from serData_in serData_out <= serDataOut; if ( serData_sync = '1' ) then -- Other side has finished receiving, so proceed state_next <= S_IDLE; end if; -- S_IDLE and others when others => -- Need to hold off the micro sending us any more commands until the write FIFO is -- completely empty, otherwise we might end up writing the tail end of the previous -- write to the new channel. serData_out <= fifoOutputValid; if ( recvValid = '1' ) then -- We got a byte from the host - it's a message length isRead_next <= recvData(7); chanAddr_next <= recvData(6 downto 0); state_next <= S_GET_COUNT0; end if; end case; end process; -- Clock falling edge flag serClkFE <= '1' when serClk_sync = '0' and serClk_prev = '1' else '0'; -- Tell application which channel we're talking to chanAddr_out <= chanAddr; -- Tell application when there's data for it to read h2fValid_out <= fifoOutputValid; -- Synchronous serial send unit sync_send: entity work.sync_send port map( clk_in => clk_in, -- Serial out serClkRE_in => delayLine(DELAY_COUNT), serData_out => serDataOut, -- Parallel in sendData_in => f2hData_in, sendValid_in => sendValid, sendReady_out => sendReady ); -- Synchronous serial receive unit sync_recv: entity work.sync_recv port map( clk_in => clk_in, -- Serial in serClkFE_in => serClkFE, serData_in => serDataIn, -- Parallel out recvData_out => recvData, recvValid_out => recvValid ); -- TODO: Can this small buffer FIFO be eliminated? write_fifo: entity work.fifo generic map( WIDTH => 8, DEPTH => FIFO_DEPTH ) port map( clk_in => clk_in, reset_in => '0', depth_out => open, -- Input pipe inputData_in => fifoInputData, inputValid_in => fifoInputValid, inputReady_out => open, -- Output pipe outputData_out => h2fData_out, outputValid_out => fifoOutputValid, outputReady_in => h2fReady_in ); end architecture;
gpl-3.0
62634ef8c29cd000e253bf69a39c20e2
0.603863
3.446884
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sm.vhd
3
50,952
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sm.vhd -- Description: This entity contains the S2MM DMA Controller State Machine -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_9; use axi_dma_v7_1_9.axi_dma_pkg.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sm is generic ( C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for S2MM Write Port C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Width of Buffer Length, Transferred Bytes, and BTT fields C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1 -- Depth of DataMover command FIFO ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- -- S2MM Control and Status -- s2mm_run_stop : in std_logic ; -- s2mm_keyhole : in std_logic ; -- s2mm_ftch_idle : in std_logic ; -- s2mm_desc_flush : in std_logic ; -- s2mm_cmnd_idle : out std_logic ; -- s2mm_sts_idle : out std_logic ; -- s2mm_eof_set : out std_logic ; -- s2mm_eof_micro : in std_logic ; -- s2mm_sof_micro : in std_logic ; -- -- -- S2MM Descriptor Fetch Request -- desc_fetch_req : out std_logic ; -- desc_fetch_done : in std_logic ; -- desc_update_done : in std_logic ; -- updt_pending : in std_logic ; desc_available : in std_logic ; -- -- -- S2MM Status Stream RX Length -- s2mm_rxlength_valid : in std_logic ; -- s2mm_rxlength_clr : out std_logic ; -- s2mm_rxlength : in std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- -- DataMover Command -- s2mm_cmnd_wr : out std_logic ; -- s2mm_cmnd_data : out std_logic_vector -- ((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); -- s2mm_cmnd_pending : in std_logic ; -- -- -- Descriptor Fields -- s2mm_desc_info : in std_logic_vector -- (31 downto 0); -- s2mm_desc_baddress : in std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_desc_blength : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_v : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_s : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) -- ); end axi_dma_s2mm_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0'); -- DataMover Command Destination Stream Offset constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant S2MM_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH) := (others => '0'); -- Queued commands counter width constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1); -- Queued commands zero count constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); -- Zero buffer length error - compare value constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- State Machine Signals signal desc_fetch_req_cmb : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal s2mm_rxlength_clr_cmb : std_logic := '0'; signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_rxlength_set : std_logic := '0'; signal blength_grtr_rxlength : std_logic := '0'; signal rxlength_fetched : std_logic := '0'; signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0'); signal count_incr : std_logic := '0'; signal count_decr : std_logic := '0'; signal desc_fetch_done_d1 : std_logic := '0'; signal zero_length_error : std_logic := '0'; signal s2mm_eof_set_i : std_logic := '0'; signal queue_more : std_logic := '0'; signal burst_type : std_logic; signal eof_micro : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin EN_MICRO_DMA : if C_MICRO_DMA = 1 generate begin eof_micro <= s2mm_eof_micro; end generate EN_MICRO_DMA; NO_MICRO_DMA : if C_MICRO_DMA = 0 generate begin eof_micro <= '0'; end generate NO_MICRO_DMA; s2mm_eof_set <= s2mm_eof_set_i; burst_type <= '1' and (not s2mm_keyhole); -- A 0 s2mm_keyhole means incremental burst -- a 1 s2mm_keyhole means fixed burst ------------------------------------------------------------------------------- -- Not using rx length from status stream - (indeterminate length mode) ------------------------------------------------------------------------------- GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, -- EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin -- For no status stream or not using length in status app field then eof set is -- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd) s2mm_eof_set_i <= '0'; ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_fetch_done, desc_update_done, s2mm_cmnd_pending, s2mm_stop, s2mm_desc_flush, updt_pending -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => -- fetch descriptor if desc available, not stopped and running -- if (updt_pending = '1') then -- s2mm_ns <= WAIT_STATUS; if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 1) then s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; else s2mm_ns <= WAIT_STATUS; write_cmnd_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- exit if error or descriptor flushed if(s2mm_desc_flush = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; -- wait until fetch complete then execute -- elsif(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; -- s2mm_ns <= EXECUTE_XFER; elsif (s2mm_cmnd_pending = '0')then desc_fetch_req_cmb <= '0'; if (updt_pending = '0') then if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; write_cmnd_cmb <= '1'; else -- coverage off s2mm_ns <= WAIT_STATUS; -- coverage on end if; end if; else s2mm_ns <= FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- -- when EXECUTE_XFER => -- -- if error exit -- if(s2mm_stop = '1')then -- s2mm_ns <= IDLE; -- -- Write another command if there is not one already pending -- elsif(s2mm_cmnd_pending = '0')then -- if (updt_pending = '0') then -- write_cmnd_cmb <= '1'; -- end if; -- if(C_SG_INCLUDE_DESC_QUEUE = 1)then -- s2mm_ns <= IDLE; -- else -- s2mm_ns <= WAIT_STATUS; -- end if; -- else -- s2mm_ns <= EXECUTE_XFER; -- end if; ------------------------------------------------------------------- when WAIT_STATUS => -- for no Q wait until desc updated if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register State Machine Statues ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register State Machine Signalse ------------------------------------------------------------------------------- -- SM_SIG_REGISTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- desc_fetch_req <= '0' ; -- else -- if (C_SG_INCLUDE_DESC_QUEUE = 0) then -- desc_fetch_req <= '1'; -- else -- desc_fetch_req <= desc_fetch_req_cmb ; -- end if; -- end if; -- end if; -- end process SM_SIG_REGISTER; desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else desc_fetch_req_cmb ; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For Indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & PAD_VALUE -- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro --'0' -- For Indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & s2mm_desc_blength; else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro -- For indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; end generate GEN_CMD_BTT_EQL_23; -- Drive unused output to zero s2mm_rxlength_clr <= '0'; end generate GEN_SM_FOR_NO_LENGTH; ------------------------------------------------------------------------------- -- Generate state machine and support logic for Using RX Length from Status -- Stream ------------------------------------------------------------------------------- -- this would not hold good for MCDMA GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, GET_RXLENGTH, CMPR_LENGTH, EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_update_done, -- desc_fetch_done, updt_pending, s2mm_rxlength_valid, rxlength_fetched, s2mm_cmnd_pending, zero_length_error, s2mm_stop, s2mm_desc_flush -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; s2mm_rxlength_clr_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_rxlength_set <= '0'; --rxlength_fetched_clr <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 0) then if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; else s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; --FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => desc_fetch_req_cmb <= '0'; -- exit if error or descriptor flushed if(s2mm_desc_flush = '1')then s2mm_ns <= IDLE; -- Descriptor fetch complete else --if(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; -- else -- desc_fetch_req_cmb <= '1'; end if; ------------------------------------------------------------------- WHEN GET_RXLENGTH => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- Buffer length zero, do not compare lengths, execute -- command to force datamover to issue interror elsif(zero_length_error = '1')then s2mm_ns <= EXECUTE_XFER; elsif(s2mm_rxlength_valid = '1')then s2mm_rxlength_set <= '1'; s2mm_rxlength_clr_cmb <= '1'; s2mm_ns <= CMPR_LENGTH; else s2mm_ns <= GET_RXLENGTH; end if; ------------------------------------------------------------------- WHEN CMPR_LENGTH => s2mm_ns <= EXECUTE_XFER; ------------------------------------------------------------------- when EXECUTE_XFER => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- write new command if one is not already pending elsif(s2mm_cmnd_pending = '0')then write_cmnd_cmb <= '1'; -- If descriptor queuing enabled then -- do NOT need to wait for status if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; -- No queuing therefore must wait for -- status before issuing next command else s2mm_ns <= WAIT_STATUS; end if; else s2mm_ns <= EXECUTE_XFER; end if; ------------------------------------------------------------------- -- coverage off when WAIT_STATUS => if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; -- coverage on ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register state machine states ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register state machine signals ------------------------------------------------------------------------------- SM_SIG_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_req <= '0' ; s2mm_rxlength_clr <= '0' ; else if (C_SG_INCLUDE_DESC_QUEUE = 0) then desc_fetch_req <= '1'; else desc_fetch_req <= desc_fetch_req_cmb ; end if; s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb; end if; end if; end process SM_SIG_REGISTER; ------------------------------------------------------------------------------- -- Check for a ZERO value in descriptor buffer length. If there is -- then flag an error and skip waiting for valid rxlength. cmnd will -- get written to datamover with BTT=0 and datamover will flag dmaint error -- which will be logged in desc, reset required to clear error ------------------------------------------------------------------------------- REG_ALIGN_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_done_d1 <= '0'; else desc_fetch_done_d1 <= desc_fetch_done; end if; end if; end process REG_ALIGN_DONE; ------------------------------------------------------------------------------- -- Zero length error detection - for determinate mode, detect early to prevent -- rxlength calcuation from first taking place. This will force a 0 BTT -- command to be issued to the datamover causing an internal error. ------------------------------------------------------------------------------- REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then zero_length_error <= '0'; elsif(desc_fetch_done_d1 = '1' and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then zero_length_error <= '1'; end if; end if; end process REG_ZERO_LNGTH_ERR; ------------------------------------------------------------------------------- -- Capture/Hold receive length from status stream. Also decrement length -- based on if received length is greater than descriptor buffer size. (i.e. is -- the case where multiple descriptors/buffers are used to describe one packet) ------------------------------------------------------------------------------- REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then rxlength <= (others => '0'); -- If command register rxlength from status stream fifo elsif(s2mm_rxlength_set = '1')then rxlength <= s2mm_rxlength; -- On command write if current desc buffer size not greater -- than current rxlength then decrement rxlength in preperations -- for subsequent commands elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0)) - unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0))); end if; end if; end process REG_RXLENGTH; ------------------------------------------------------------------------------- -- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To' -- Received Length value ------------------------------------------------------------------------------- REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then blength_grtr_rxlength <= '0'; elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then blength_grtr_rxlength <= '1'; else blength_grtr_rxlength <= '0'; end if; end if; end process REG_BLENGTH_GRTR_RXLNGTH; ------------------------------------------------------------------------------- -- On command assert rxlength fetched flag indicating length grabbed from -- status stream fifo ------------------------------------------------------------------------------- RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then rxlength_fetched <= '0'; elsif(s2mm_rxlength_set = '1')then rxlength_fetched <= '1'; end if; end if; end process RXLENGTH_FTCHED_PROCESS; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '0' -- Cat. EOF=0 to CMD Tag & '0' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '1' -- Cat. EOF=1 to CMD Tag & '1' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- Set EOF=1 & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '0' -- Cat. EOF='0' to CMD Tag & '0' -- Cat. IOC='0' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '1' -- Cat. EOF='1' to CMD Tag & '1' -- Cat. IOC='1' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_EQL_23; end generate GEN_SM_FOR_LENGTH; ------------------------------------------------------------------------------- -- Counter for keepting track of pending commands/status in primary datamover -- Use this to determine if primary datamover for s2mm is Idle. ------------------------------------------------------------------------------- -- Increment queue count for each command written if not occuring at -- same time a status from DM being updated to SG engine count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0' else '0'; -- Decrement queue count for each status update to SG engine if not occuring -- at same time as command being written to DM count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1' else '0'; -- keep track of number queue commands --CMD2STS_COUNTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then -- cmnds_queued <= (others => '0'); -- elsif(count_incr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1); -- elsif(count_decr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1); -- end if; -- end if; -- end process CMD2STS_COUNTER; QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift <= (others => '0'); elsif(count_incr = '1')then cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1'; elsif(count_decr = '1')then cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1); end if; end if; end process CMD2STS_COUNTER1; end generate QUEUE_COUNT; NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift (0) <= '0'; elsif(count_incr = '1')then cmnds_queued_shift (0) <= '1'; elsif(count_decr = '1')then cmnds_queued_shift (0) <= '0'; end if; end if; end process CMD2STS_COUNTER1; end generate NOQUEUE_COUNT; -- indicate idle when no more queued commands --s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000" -- else '0'; s2mm_sts_idle <= not cmnds_queued_shift(0); ------------------------------------------------------------------------------- -- Queue only the amount of commands that can be queued on descriptor update -- else lock up can occur. Note datamover command fifo depth is set to number -- of descriptors to queue. ------------------------------------------------------------------------------- --QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; -- else -- queue_more <= '0'; -- end if; -- end if; -- end process QUEUE_MORE_PROCESS; QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; else queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0'; end if; end if; end process QUEUE_MORE_PROCESS; end implementation;
gpl-3.0
72df04d0cf80ea28859658f003af4b89
0.375903
4.903946
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc366.vhd
4
2,021
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc366.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p03n01i00366ent IS END c03s02b01x01p03n01i00366ent; ARCHITECTURE c03s02b01x01p03n01i00366arch OF c03s02b01x01p03n01i00366ent IS type MVL is ('0', '1', 'Z') ; type tribit is array (natural range <>) of MVL; subtype word is tribit (0 to 16); -- Success_here BEGIN TESTING: PROCESS variable k : word; BEGIN k(0) := '0'; k(16) := 'Z'; assert NOT (k(0)='0' and k(16)='Z') report "***PASSED TEST: c03s02b01x01p03n01i00366" severity NOTE; assert (k(0)='0' and k(16)='Z') report "***FAILED TEST: c03s02b01x01p03n01i00366 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p03n01i00366arch;
gpl-2.0
eed4780bf979896108f594cc001989f4
0.662543
3.596085
false
true
false
false
lfmunoz/vhdl
ip_blocks/sip_check_data/data_align.vhd
1
7,553
------------------------------------------------------------------------------------- -- FILE NAME : data_align.vhd -- AUTHOR : Luis -- COMPANY : -- UNITS : Entity - -- Architecture - Behavioral -- LANGUAGE : VHDL -- DATE : AUG 21, 2014 ------------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------- -- DESCRIPTION -- =========== -- -- -- ------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------- -- LIBRARIES ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- IEEE --use ieee.numeric_std.all; -- non-IEEE use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; Library UNISIM; use UNISIM.vcomponents.all; ------------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------------- entity data_align is port ( clk_in : in std_logic; rst_in : in std_logic; data_in : in std_logic_vector(63 downto 0); val_in : in std_logic; data_out : out std_logic_vector(63 downto 0); val_out : out std_logic ); end data_align; ------------------------------------------------------------------------------------- -- ARCHITECTURE ------------------------------------------------------------------------------------- architecture Behavioral of data_align is ------------------------------------------------------------------------------------- -- CONSTANTS ------------------------------------------------------------------------------------- type alignemnt_state_machine is (WAIT_STATE, CHECK_STATE, DONE_STATE); type bus008 is array(natural range <>) of std_logic_vector( 7 downto 0); type bus064 is array(natural range <>) of std_logic_vector(63 downto 0); ------------------------------------------------------------------------------------- -- SIGNALS ------------------------------------------------------------------------------------- signal sm_rx : alignemnt_state_machine; signal valid_pipe : std_logic_vector(2 downto 0); signal data_pipe : bus064(2 downto 0); signal data_pipe_byte : bus008(23 downto 0); signal val_count : std_logic_vector(3 downto 0); signal alignment_mux_select : std_logic_vector(1 downto 0); --*********************************************************************************** begin --*********************************************************************************** -- buffer 3 cycles process(clk_in) begin if rising_edge(clk_in) then valid_pipe(2) <= val_in; valid_pipe(1) <= valid_pipe(2); valid_pipe(0) <= valid_pipe(1); if val_in = '1' then data_pipe(2) <= data_in; data_pipe(1) <= data_pipe(2); data_pipe(0) <= data_pipe(1); end if; end if; end process; -- Remap data_pipe_byte(23) <= data_pipe(2)(63 downto 56); data_pipe_byte(22) <= data_pipe(2)(55 downto 48); data_pipe_byte(21) <= data_pipe(2)(47 downto 40); data_pipe_byte(20) <= data_pipe(2)(39 downto 32); data_pipe_byte(19) <= data_pipe(2)(31 downto 24); data_pipe_byte(18) <= data_pipe(2)(23 downto 16); data_pipe_byte(17) <= data_pipe(2)(15 downto 8); data_pipe_byte(16) <= data_pipe(2)( 7 downto 0); data_pipe_byte(15) <= data_pipe(1)(63 downto 56); data_pipe_byte(14) <= data_pipe(1)(55 downto 48); data_pipe_byte(13) <= data_pipe(1)(47 downto 40); data_pipe_byte(12) <= data_pipe(1)(39 downto 32); data_pipe_byte(11) <= data_pipe(1)(31 downto 24); data_pipe_byte(10) <= data_pipe(1)(23 downto 16); data_pipe_byte(9) <= data_pipe(1)(15 downto 8); data_pipe_byte(8) <= data_pipe(1)( 7 downto 0); data_pipe_byte(7) <= data_pipe(0)(63 downto 56); data_pipe_byte(6) <= data_pipe(0)(55 downto 48); data_pipe_byte(5) <= data_pipe(0)(47 downto 40); data_pipe_byte(4) <= data_pipe(0)(39 downto 32); data_pipe_byte(3) <= data_pipe(0)(31 downto 24); data_pipe_byte(2) <= data_pipe(0)(23 downto 16); data_pipe_byte(1) <= data_pipe(0)(15 downto 8); data_pipe_byte(0) <= data_pipe(0)( 7 downto 0); process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then sm_rx <= WAIT_STATE; val_count <= (others => '0'); alignment_mux_select <= "00"; data_out <= (others=>'0'); val_out <= '0'; else case sm_rx is -- wait until we get 7 valid data when WAIT_STATE => if val_count = 7 then sm_rx <= CHECK_STATE; elsif val_in = '1' then val_count <= val_count + 1; end if; when CHECK_STATE => if data_pipe_byte(8) = data_pipe_byte(9) and data_pipe_byte(8) = data_pipe_byte(10) and data_pipe_byte(8) = data_pipe_byte(11) then alignment_mux_select <= "00"; sm_rx <= DONE_STATE; elsif data_pipe_byte(8) = data_pipe_byte(9) and data_pipe_byte(8) = data_pipe_byte(10) and data_pipe_byte(8) = data_pipe_byte(7) then alignment_mux_select <= "01"; sm_rx <= DONE_STATE; elsif data_pipe_byte(8) = data_pipe_byte(9) and data_pipe_byte(8) = data_pipe_byte(7) and data_pipe_byte(8) = data_pipe_byte(6) then alignment_mux_select <= "10"; sm_rx <= DONE_STATE; elsif data_pipe_byte(8) = data_pipe_byte(7) and data_pipe_byte(8) = data_pipe_byte(6) and data_pipe_byte(8) = data_pipe_byte(5) then alignment_mux_select <= "11"; sm_rx <= DONE_STATE; end if; when DONE_STATE => sm_rx <= DONE_STATE; when others => sm_rx <= WAIT_STATE; end case; case alignment_mux_select is when "00" => data_out <= data_pipe_byte(15) & data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8); val_out <= valid_pipe(1); when "01" => data_out <= data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7); val_out <= valid_pipe(1); when "10" => data_out <= data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6); val_out <= valid_pipe(1); when "11" => data_out <= data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6) & data_pipe_byte(5); val_out <= valid_pipe(1); when others => end case; end if; end if; end process; --*********************************************************************************** end architecture Behavioral; --***********************************************************************************
mit
d5880e3ece603ba2b921b1da3215faab
0.438236
3.666505
false
false
false
false
tgingold/ghdl
testsuite/synth/issue1099/top.vhdl
1
756
library ieee; use ieee.std_logic_1164.all; entity has_zero_width_port is port( width_one_port: out std_logic_vector(0 downto 0); width_zero_port: out std_logic_vector(-1 downto 0) ); end entity; architecture arch of has_zero_width_port is begin width_one_port <= (others => '0'); width_zero_port <= (others => '0'); end architecture; library ieee; use ieee.std_logic_1164.all; entity top is port( width_one_port: out std_logic_vector(0 downto 0); width_zero_port: out std_logic_vector(-1 downto 0) ); end entity; architecture arch of top is begin wrapped: entity work.has_zero_width_port port map ( width_one_port => width_one_port, width_zero_port => width_zero_port ); end architecture;
gpl-2.0
44c3ba6113ec62cb7f847061a8da960a
0.667989
3.123967
false
false
false
false
tgingold/ghdl
testsuite/synth/synth34/tb_repro_slv.vhdl
1
635
entity tb_repro_slv is end tb_repro_slv; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_repro_slv is signal clk : std_logic; signal a : std_logic_vector(7 downto 0); signal b : std_logic_vector(7 downto 0); begin dut: entity work.repro_slv port map ( clk => clk, a => a, b => b); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin a <= x"ab"; pulse; assert b = x"ab" severity failure; a <= x"12"; pulse; assert b = x"12" severity failure; wait; end process; end behav;
gpl-2.0
7df014928450870397c58a6f95f7f593
0.585827
3.190955
false
false
false
false
tgingold/ghdl
testsuite/synth/asgn01/tb_asgn02.vhdl
1
453
entity tb_asgn02 is end tb_asgn02; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_asgn02 is signal s0 : std_logic; signal r : std_logic_vector (2 downto 0); begin dut: entity work.asgn02 port map (s0 => s0, r => r); process begin s0 <= '1'; wait for 1 ns; assert r = "010" severity failure; s0 <= '0'; wait for 1 ns; assert r = "000" severity failure; wait; end process; end behav;
gpl-2.0
e640d9a0d4f664b5fa9ed784564bbc65
0.620309
3.02
false
false
false
false
nickg/nvc
test/regress/wait14.vhd
1
446
entity wait14 is end entity; architecture test of wait14 is signal v : bit_vector(1 to 3); signal n : integer range v'range := 3; begin stim: process is begin wait for 1 ns; v(2) <= '1'; -- Should not wake up p1 wait for 1 ns; v(3) <= '1'; n <= 1; wait; end process; p1: assert v(1) = '0' and now = 0 ns; p2: assert v(n) = '0'; end architecture;
gpl-3.0
c218c12c6772737bd77ef1ce82110bc5
0.5
3.255474
false
false
false
false
Darkin47/Zynq-TX-UTT
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/synth/design_1_axi_dma_0_0.vhd
1
26,131
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_dma:7.1 -- IP Revision: 9 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_dma_v7_1_9; USE axi_dma_v7_1_9.axi_dma; ENTITY design_1_axi_dma_0_0 IS PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axi_s2mm_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; mm2s_prmry_reset_out_n : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_awvalid : OUT STD_LOGIC; m_axi_s2mm_awready : IN STD_LOGIC; m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_wlast : OUT STD_LOGIC; m_axi_s2mm_wvalid : OUT STD_LOGIC; m_axi_s2mm_wready : IN STD_LOGIC; m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_bvalid : IN STD_LOGIC; m_axi_s2mm_bready : OUT STD_LOGIC; s2mm_prmry_reset_out_n : OUT STD_LOGIC; s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_s2mm_tvalid : IN STD_LOGIC; s_axis_s2mm_tready : OUT STD_LOGIC; s_axis_s2mm_tlast : IN STD_LOGIC; mm2s_introut : OUT STD_LOGIC; s2mm_introut : OUT STD_LOGIC; axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END design_1_axi_dma_0_0; ARCHITECTURE design_1_axi_dma_0_0_arch OF design_1_axi_dma_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_dma IS GENERIC ( C_S_AXI_LITE_ADDR_WIDTH : INTEGER; C_S_AXI_LITE_DATA_WIDTH : INTEGER; C_DLYTMR_RESOLUTION : INTEGER; C_PRMRY_IS_ACLK_ASYNC : INTEGER; C_ENABLE_MULTI_CHANNEL : INTEGER; C_NUM_MM2S_CHANNELS : INTEGER; C_NUM_S2MM_CHANNELS : INTEGER; C_INCLUDE_SG : INTEGER; C_SG_INCLUDE_STSCNTRL_STRM : INTEGER; C_SG_USE_STSAPP_LENGTH : INTEGER; C_SG_LENGTH_WIDTH : INTEGER; C_M_AXI_SG_ADDR_WIDTH : INTEGER; C_M_AXI_SG_DATA_WIDTH : INTEGER; C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER; C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER; C_MICRO_DMA : INTEGER; C_INCLUDE_MM2S : INTEGER; C_INCLUDE_MM2S_SF : INTEGER; C_MM2S_BURST_SIZE : INTEGER; C_M_AXI_MM2S_ADDR_WIDTH : INTEGER; C_M_AXI_MM2S_DATA_WIDTH : INTEGER; C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER; C_INCLUDE_MM2S_DRE : INTEGER; C_INCLUDE_S2MM : INTEGER; C_INCLUDE_S2MM_SF : INTEGER; C_S2MM_BURST_SIZE : INTEGER; C_M_AXI_S2MM_ADDR_WIDTH : INTEGER; C_M_AXI_S2MM_DATA_WIDTH : INTEGER; C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER; C_INCLUDE_S2MM_DRE : INTEGER; C_FAMILY : STRING ); PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_sg_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axi_s2mm_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_awvalid : OUT STD_LOGIC; m_axi_sg_awready : IN STD_LOGIC; m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_wlast : OUT STD_LOGIC; m_axi_sg_wvalid : OUT STD_LOGIC; m_axi_sg_wready : IN STD_LOGIC; m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_bvalid : IN STD_LOGIC; m_axi_sg_bready : OUT STD_LOGIC; m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_arvalid : OUT STD_LOGIC; m_axi_sg_arready : IN STD_LOGIC; m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_rlast : IN STD_LOGIC; m_axi_sg_rvalid : IN STD_LOGIC; m_axi_sg_rready : OUT STD_LOGIC; m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; mm2s_prmry_reset_out_n : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); mm2s_cntrl_reset_out_n : OUT STD_LOGIC; m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC; m_axis_mm2s_cntrl_tready : IN STD_LOGIC; m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC; m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_awvalid : OUT STD_LOGIC; m_axi_s2mm_awready : IN STD_LOGIC; m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_wlast : OUT STD_LOGIC; m_axi_s2mm_wvalid : OUT STD_LOGIC; m_axi_s2mm_wready : IN STD_LOGIC; m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_bvalid : IN STD_LOGIC; m_axi_s2mm_bready : OUT STD_LOGIC; s2mm_prmry_reset_out_n : OUT STD_LOGIC; s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_s2mm_tvalid : IN STD_LOGIC; s_axis_s2mm_tready : OUT STD_LOGIC; s_axis_s2mm_tlast : IN STD_LOGIC; s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s2mm_sts_reset_out_n : OUT STD_LOGIC; s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_s2mm_sts_tvalid : IN STD_LOGIC; s_axis_s2mm_sts_tready : OUT STD_LOGIC; s_axis_s2mm_sts_tlast : IN STD_LOGIC; mm2s_introut : OUT STD_LOGIC; s2mm_introut : OUT STD_LOGIC; axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_dma; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2016.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_dma_0_0_arch : ARCHITECTURE IS "design_1_axi_dma_0_0,axi_dma,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "design_1_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=23,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_A" & "XIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=8,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=8,C_INCLUDE_S2MM_DRE=1,C_FAMILY=zynq}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT"; BEGIN U0 : axi_dma GENERIC MAP ( C_S_AXI_LITE_ADDR_WIDTH => 10, C_S_AXI_LITE_DATA_WIDTH => 32, C_DLYTMR_RESOLUTION => 125, C_PRMRY_IS_ACLK_ASYNC => 0, C_ENABLE_MULTI_CHANNEL => 0, C_NUM_MM2S_CHANNELS => 1, C_NUM_S2MM_CHANNELS => 1, C_INCLUDE_SG => 0, C_SG_INCLUDE_STSCNTRL_STRM => 0, C_SG_USE_STSAPP_LENGTH => 0, C_SG_LENGTH_WIDTH => 23, C_M_AXI_SG_ADDR_WIDTH => 32, C_M_AXI_SG_DATA_WIDTH => 32, C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32, C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32, C_MICRO_DMA => 0, C_INCLUDE_MM2S => 1, C_INCLUDE_MM2S_SF => 1, C_MM2S_BURST_SIZE => 16, C_M_AXI_MM2S_ADDR_WIDTH => 32, C_M_AXI_MM2S_DATA_WIDTH => 32, C_M_AXIS_MM2S_TDATA_WIDTH => 8, C_INCLUDE_MM2S_DRE => 1, C_INCLUDE_S2MM => 1, C_INCLUDE_S2MM_SF => 1, C_S2MM_BURST_SIZE => 16, C_M_AXI_S2MM_ADDR_WIDTH => 32, C_M_AXI_S2MM_DATA_WIDTH => 32, C_S_AXIS_S2MM_TDATA_WIDTH => 8, C_INCLUDE_S2MM_DRE => 1, C_FAMILY => "zynq" ) PORT MAP ( s_axi_lite_aclk => s_axi_lite_aclk, m_axi_sg_aclk => '0', m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_s2mm_aclk => m_axi_s2mm_aclk, axi_resetn => axi_resetn, s_axi_lite_awvalid => s_axi_lite_awvalid, s_axi_lite_awready => s_axi_lite_awready, s_axi_lite_awaddr => s_axi_lite_awaddr, s_axi_lite_wvalid => s_axi_lite_wvalid, s_axi_lite_wready => s_axi_lite_wready, s_axi_lite_wdata => s_axi_lite_wdata, s_axi_lite_bresp => s_axi_lite_bresp, s_axi_lite_bvalid => s_axi_lite_bvalid, s_axi_lite_bready => s_axi_lite_bready, s_axi_lite_arvalid => s_axi_lite_arvalid, s_axi_lite_arready => s_axi_lite_arready, s_axi_lite_araddr => s_axi_lite_araddr, s_axi_lite_rvalid => s_axi_lite_rvalid, s_axi_lite_rready => s_axi_lite_rready, s_axi_lite_rdata => s_axi_lite_rdata, s_axi_lite_rresp => s_axi_lite_rresp, m_axi_sg_awready => '0', m_axi_sg_wready => '0', m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_sg_bvalid => '0', m_axi_sg_arready => '0', m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_sg_rlast => '0', m_axi_sg_rvalid => '0', m_axi_mm2s_araddr => m_axi_mm2s_araddr, m_axi_mm2s_arlen => m_axi_mm2s_arlen, m_axi_mm2s_arsize => m_axi_mm2s_arsize, m_axi_mm2s_arburst => m_axi_mm2s_arburst, m_axi_mm2s_arprot => m_axi_mm2s_arprot, m_axi_mm2s_arcache => m_axi_mm2s_arcache, m_axi_mm2s_arvalid => m_axi_mm2s_arvalid, m_axi_mm2s_arready => m_axi_mm2s_arready, m_axi_mm2s_rdata => m_axi_mm2s_rdata, m_axi_mm2s_rresp => m_axi_mm2s_rresp, m_axi_mm2s_rlast => m_axi_mm2s_rlast, m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, m_axi_mm2s_rready => m_axi_mm2s_rready, mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n, m_axis_mm2s_tdata => m_axis_mm2s_tdata, m_axis_mm2s_tkeep => m_axis_mm2s_tkeep, m_axis_mm2s_tvalid => m_axis_mm2s_tvalid, m_axis_mm2s_tready => m_axis_mm2s_tready, m_axis_mm2s_tlast => m_axis_mm2s_tlast, m_axis_mm2s_cntrl_tready => '0', m_axi_s2mm_awaddr => m_axi_s2mm_awaddr, m_axi_s2mm_awlen => m_axi_s2mm_awlen, m_axi_s2mm_awsize => m_axi_s2mm_awsize, m_axi_s2mm_awburst => m_axi_s2mm_awburst, m_axi_s2mm_awprot => m_axi_s2mm_awprot, m_axi_s2mm_awcache => m_axi_s2mm_awcache, m_axi_s2mm_awvalid => m_axi_s2mm_awvalid, m_axi_s2mm_awready => m_axi_s2mm_awready, m_axi_s2mm_wdata => m_axi_s2mm_wdata, m_axi_s2mm_wstrb => m_axi_s2mm_wstrb, m_axi_s2mm_wlast => m_axi_s2mm_wlast, m_axi_s2mm_wvalid => m_axi_s2mm_wvalid, m_axi_s2mm_wready => m_axi_s2mm_wready, m_axi_s2mm_bresp => m_axi_s2mm_bresp, m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, m_axi_s2mm_bready => m_axi_s2mm_bready, s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n, s_axis_s2mm_tdata => s_axis_s2mm_tdata, s_axis_s2mm_tkeep => s_axis_s2mm_tkeep, s_axis_s2mm_tvalid => s_axis_s2mm_tvalid, s_axis_s2mm_tready => s_axis_s2mm_tready, s_axis_s2mm_tlast => s_axis_s2mm_tlast, s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)), s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)), s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_s2mm_sts_tkeep => X"F", s_axis_s2mm_sts_tvalid => '0', s_axis_s2mm_sts_tlast => '0', mm2s_introut => mm2s_introut, s2mm_introut => s2mm_introut, axi_dma_tstvec => axi_dma_tstvec ); END design_1_axi_dma_0_0_arch;
gpl-3.0
a93801486cd8b42361227ed03581b76c
0.677739
2.743988
false
false
false
false
lfmunoz/vhdl
templates/simulation/testbench_690t.vhd
1
10,194
-------------------------------------------------------------------------------- -- file name : testbench_690t.vhd -- -- author : Luis F. Munoz -- -- company : 4dsp -- -- date : 3/4/2014 -- -- language : vhdl -- -------------------------------------------------------------------------------- -- description -- =========== -- Testbench for the VP780 + FMC160 -- -- notes: -------------------------------------------------------------------------------- -- -- disclaimer: limited warranty and disclaimer. these designs are -- provided to you as is. 4dsp specifically disclaims any -- implied warranties of merchantability, non-infringement, or -- fitness for a particular purpose. 4dsp does not warrant that -- the functions contained in these designs will meet your -- requirements, or that the operation of these designs will be -- uninterrupted or error free, or that defects in the designs -- will be corrected. furthermore, 4dsp does not warrant or -- make any representations regarding use or the results of the -- use of the designs in terms of correctness, accuracy, -- reliability, or otherwise. -- -- limitation of liability. in no event will 4dsp or its -- licensors be liable for any loss of data, lost profits, cost -- or procurement of substitute goods or services, or for any -- special, incidental, consequential, or indirect damages -- arising from the use or operation of the designs or -- accompanying documentation, however caused and on any theory -- of liability. this limitation will apply even if 4dsp -- has been advised of the possibility of such damage. this -- limitation shall apply not-withstanding the failure of the -- essential purpose of any limited remedies herein. -- -- from -- ver pcb mod date changes -- === ======= ======== ======= -- -- 0.0 0 05-12-2006 new version -- ---------------------------------------------- -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Specify libraries -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; library std; use std.textio.all; library work; use work.txt_util.all; use work.std_logic_textio.all; -------------------------------------------------------------------------------- -- Entity declaration -------------------------------------------------------------------------------- entity testbench_690t is end entity testbench_690t; -------------------------------------------------------------------------------- -- Architecture declaration -------------------------------------------------------------------------------- architecture testbench_beh of testbench_690t is -------------------------------------------------------------------------------- -- Constant declarations -------------------------------------------------------------------------------- constant CLK_200_MHZ : time := 5 ns; constant CLK_100_MHZ : time := 10 ns; constant CLK_300_MHZ : time := 3.3333 ns; constant CLK_25_MHZ : time := 40 ns; constant CLK_167_MHZ : time := 6 ns; ----------------------------------------------------------------------------------- -- Signal declarations ----------------------------------------------------------------------------------- signal i2c_scl : std_logic; signal i2c_sda : std_logic; signal ext_trigger_p : std_logic; signal ext_trigger_n : std_logic; signal dac_dco_p : std_logic; signal dac_dco_n : std_logic; signal dac_dci_p : std_logic; signal dac_dci_n : std_logic; signal dac_frm_p : std_logic; signal dac_frm_n : std_logic; signal dac_p0_p : std_logic_vector(13 downto 0); signal dac_p0_n : std_logic_vector(13 downto 0); signal dac_p1_p : std_logic_vector(13 downto 0); signal dac_p1_n : std_logic_vector(13 downto 0); signal adc_i_dclk_p : std_logic; signal adc_i_dclk_n : std_logic; signal adc_i_d_p : std_logic_vector(11 downto 0); signal adc_i_d_n : std_logic_vector(11 downto 0); signal adc_i_dly_p : std_logic_vector(11 downto 0); signal adc_i_dly_n : std_logic_vector(11 downto 0); signal adc_q_dclk_p : std_logic; signal adc_q_dclk_n : std_logic; signal adc_q_d_p : std_logic_vector(11 downto 0); signal adc_q_d_n : std_logic_vector(11 downto 0); signal adc_q_dly_p : std_logic_vector(11 downto 0); signal adc_q_dly_n : std_logic_vector(11 downto 0); signal pg_m2c : std_logic; signal prsnt_m2c_l : std_logic; signal sysclk_p : std_logic := '1'; signal sysclk_n : std_logic := '0'; signal clk25 : std_logic := '1'; signal clk_synth : std_logic := '1'; signal clk200_p : std_logic := '1'; signal clk200_n : std_logic := '0'; signal clk300_p : std_logic := '1'; signal clk300_n : std_logic := '0'; signal cpu_reset : std_logic := '0'; --*********************************************************************************** begin --*********************************************************************************** -------------------------------------------------------------------------------- -- Clock & Reset generation -------------------------------------------------------------------------------- sysclk_p <= not sysclk_p after CLK_100_MHZ/2; sysclk_n <= not sysclk_p; clk25 <= not clk25 after CLK_25_MHZ/2; clk_synth <= not clk_synth after CLK_167_MHZ/2; clk200_p <= not clk200_p after CLK_200_MHZ/2; clk200_n <= not clk200_p; clk300_p <= not clk300_p after CLK_300_MHZ/2; clk300_n <= not clk300_p; cpu_reset <= '1' after CLK_200_MHZ/2 * 10; -------------------------------------------------------------------------------- -- FPGA instantiation -------------------------------------------------------------------------------- inst0_fpga: entity work.vp780_fmc160_690t port map ( --STAR sip_i2c_master, ID=0 (ext_i2c) i2c_scl_0 => i2c_scl, i2c_sda_0 => i2c_sda, --STAR sip_vp780_host_if, ID=8 (ext_vp780_host_if) flash_address_8 => open, flash_ce_n_8 => open, flash_data_8 => open, flash_oe_n_8 => open, flash_we_n_8 => open, fp_cp_8 => open, gpio_led_8 => open, host_if_i2c_scl_8 => open, host_if_i2c_sda_8 => open, pci_exp_rxn_8 => (others => '0'), pci_exp_rxp_8 => (others => '0'), pci_exp_txn_8 => open, pci_exp_txp_8 => open, sys_clk_n_8 => sysclk_p, sys_clk_p_8 => sysclk_n, sys_reset_n_8 => cpu_reset, --STAR sip_clkrst_vp780, ID=0 (ext_vp780_clkin) aux_clk_0 => clk25, clk200_n_0 => clk200_n, clk200_p_0 => clk200_p, clk300_n_0 => clk300_n, clk300_p_0 => clk300_p, clk_synth_0_0 => clk_synth, clk_synth_1_0 => clk_synth, --STAR sip_fmc160, ID=0 (ext_fmc160) adc_i_d_n_0 => adc_i_d_n, adc_i_d_p_0 => adc_i_d_p, adc_i_dclk_n_0 => adc_i_dclk_n, adc_i_dclk_p_0 => adc_i_dclk_p, adc_i_dly_n_0 => adc_i_dly_n, adc_i_dly_p_0 => adc_i_dly_p, adc_q_d_n_0 => adc_q_d_n, adc_q_d_p_0 => adc_q_d_p, adc_q_dclk_n_0 => adc_q_dclk_n, adc_q_dclk_p_0 => adc_q_dclk_p, adc_q_dly_n_0 => adc_q_dly_n, adc_q_dly_p_0 => adc_q_dly_p, dac_dci_n_0 => dac_dci_n, dac_dci_p_0 => dac_dci_p, dac_dco_p_0 => dac_dco_p, dac_dco_n_0 => dac_dco_n, dac_frm_n_0 => dac_frm_n, dac_frm_p_0 => dac_frm_p, dac_p0_n_0 => dac_p0_n, dac_p0_p_0 => dac_p0_p, dac_p1_n_0 => dac_p1_n, dac_p1_p_0 => dac_p1_p, ext_trigger_n_0 => ext_trigger_n, ext_trigger_p_0 => ext_trigger_p, pg_m2c_0 => pg_m2c, prsnt_m2c_l_0 => prsnt_m2c_l ); -------------------------------------------------------------------------------- -- FMC160 model instantiation -------------------------------------------------------------------------------- fmc160_model_inst: entity work.fmc160_model generic map ( CLOCK_PERIOD => 400 ps -- VCO = 2500MHz ) port map ( i2c_scl => i2c_scl, i2c_sda => i2c_sda, i2c_ga0 => '0', i2c_ga1 => '0', ext_trigger_p => ext_trigger_p, ext_trigger_n => ext_trigger_n, dac_dco_p => dac_dco_p, dac_dco_n => dac_dco_n, dac_dci_p => dac_dci_p, dac_dci_n => dac_dci_n, dac_frm_p => dac_frm_p, dac_frm_n => dac_frm_n, dac_p0_p => dac_p0_p, dac_p0_n => dac_p0_n, dac_p1_p => dac_p1_p, dac_p1_n => dac_p1_n, adc_i_dclk_p => adc_i_dclk_p, adc_i_dclk_n => adc_i_dclk_n, adc_i_d_p => adc_i_d_p, adc_i_d_n => adc_i_d_n, adc_i_dly_p => adc_i_dly_p, adc_i_dly_n => adc_i_dly_n, adc_q_dclk_p => adc_q_dclk_p, adc_q_dclk_n => adc_q_dclk_n, adc_q_d_p => adc_q_d_p, adc_q_d_n => adc_q_d_n, adc_q_dly_p => adc_q_dly_p, adc_q_dly_n => adc_q_dly_n, pg_c2m => '1', pg_m2c => pg_m2c, prsnt_m2c_l => prsnt_m2c_l ); --*********************************************************************************** end architecture testbench_beh; --***********************************************************************************
mit
1d5ffb9ec83124e8517ae4e8d5c38405
0.428684
3.518813
false
false
false
false
tgingold/ghdl
testsuite/gna/bug077/repro5.vhdl
1
544
entity repro5 is end repro5; architecture behav of repro5 is type my_rec is record a : bit; w : bit_vector (1 to 2); end record; procedure check (signal v : my_rec) is begin assert v.a = '0' and v.w = "01"; end check; procedure pack (signal a : bit; signal w : bit_vector) is begin check (v.a => a, v.w => w); end pack; signal sa : bit; signal sw : bit_vector (1 to 2); begin process begin sa <= '0'; sw <= "01"; wait for 0 ns; pack (sa, sw); wait; end process; end;
gpl-2.0
8efbc54e45b2f4755aa8eb23d7dacf27
0.5625
3.05618
false
false
false
false
nickg/nvc
test/sem/afunc.vhd
1
1,339
entity afunc is end entity; architecture test of afunc is function get return bit_vector is begin return X"10"; end function; function get2(x : integer := 0) return bit_vector is begin return "01"; end function; begin process is begin assert get(0) = '0'; -- OK assert '0' = get(0); -- OK assert get2(0) = "01"; -- OK assert "01" = get2(0); -- OK assert get2(0) = '0'; -- OK assert '0' = get2(0); -- OK wait; end process; -- Reduced from VESTS case tc1072.vhd b1: block is TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER; SUBTYPE A6 IS A (1 TO 6); SUBTYPE A8 IS A (1 TO 8); FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS BEGIN IF (a=3) AND (b=3) THEN RETURN (1,2,3,4,5,6); ELSE IF (a=3) THEN RETURN (11,22,33,44,55,66); ELSE RETURN (111,222,333,444,555,666); END IF; END IF; END; begin TESTING: PROCESS VARIABLE q : A8; BEGIN q(1) := func1(3)(1); -- OK end process; end block; end architecture;
gpl-3.0
00447e75cb7bf698774933c87c901128
0.444361
3.719444
false
false
false
false
nickg/nvc
lib/ieee/numeric_std.vhdl
1
34,590
-- ----------------------------------------------------------------- -- -- Copyright 2019 IEEE P1076 WG Authors -- -- See the LICENSE file distributed with this work for copyright and -- licensing information and the AUTHORS file. -- -- This file to you under the Apache License, Version 2.0 (the "License"). -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -- implied. See the License for the specific language governing -- permissions and limitations under the License. -- -- Title : Standard VHDL Synthesis Packages -- : (NUMERIC_STD package declaration) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE DASC Synthesis Working Group, -- : Accellera VHDL-TC, and IEEE P1076 Working Group -- : -- Purpose : This package defines numeric types and arithmetic functions -- : for use with synthesis tools. Two numeric types are defined: -- : -- > UNSIGNED: represents an UNSIGNED number -- : in vector form -- : -- > SIGNED: represents a SIGNED number -- : in vector form -- : The base element type is type STD_ULOGIC. -- : The element subtypes are the same subtype as STD_LOGIC. -- : The leftmost bit is treated as the most significant bit. -- : Signed vectors are represented in two's complement form. -- : This package contains overloaded arithmetic operators on -- : the SIGNED and UNSIGNED types. The package also contains -- : useful type conversions functions, clock detection -- : functions, and other utility functions. -- : -- : If any argument to a function is a null array, a null array -- : is returned (exceptions, if any, are noted individually). -- -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; package NUMERIC_STD is constant CopyRightNotice : STRING := "Copyright © 2008 IEEE. All rights reserved."; --============================================================================ -- Numeric Array Type Definitions --============================================================================ type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; --============================================================================ -- Arithmetic Operators: --=========================================================================== -- Id: A.1 function "abs" (ARG : SIGNED) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Returns the absolute value of a SIGNED vector ARG. -- Id: A.2 function "-" (ARG : SIGNED) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Returns the value of the unary minus operation on a -- SIGNED vector ARG. --============================================================================ -- Id: A.3 function "+" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) -- Result: Adds two UNSIGNED vectors that may be of different lengths. -- Id: A.4 function "+" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) -- Result: Adds two SIGNED vectors that may be of different lengths. -- Id: A.5 function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Adds an UNSIGNED vector, L, with a nonnegative INTEGER, R. -- Id: A.6 function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Adds a nonnegative INTEGER, L, with an UNSIGNED vector, R. -- Id: A.7 function "+" (L : INTEGER; R : SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED -- vector, R. -- Id: A.8 function "+" (L : SIGNED; R : INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Adds a SIGNED vector, L, to an INTEGER, R. --============================================================================ -- Id: A.9 function "-" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) -- Result: Subtracts two UNSIGNED vectors that may be of different lengths. -- Id: A.10 function "-" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0) -- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L, -- that may possibly be of different lengths. -- Id: A.11 function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Subtracts a nonnegative INTEGER, R, from an UNSIGNED vector, L. -- Id: A.12 function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Subtracts an UNSIGNED vector, R, from a nonnegative INTEGER, L. -- Id: A.13 function "-" (L : SIGNED; R : INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Subtracts an INTEGER, R, from a SIGNED vector, L. -- Id: A.14 function "-" (L : INTEGER; R : SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Subtracts a SIGNED vector, R, from an INTEGER, L. --============================================================================ -- Id: A.15 function "*" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) -- Result: Performs the multiplication operation on two UNSIGNED vectors -- that may possibly be of different lengths. -- Id: A.16 function "*" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0) -- Result: Multiplies two SIGNED vectors that may possibly be of -- different lengths. -- Id: A.17 function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0) -- Result: Multiplies an UNSIGNED vector, L, with a nonnegative -- INTEGER, R. R is converted to an UNSIGNED vector of -- SIZE L'LENGTH before multiplication. -- Id: A.18 function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0) -- Result: Multiplies an UNSIGNED vector, R, with a nonnegative -- INTEGER, L. L is converted to an UNSIGNED vector of -- SIZE R'LENGTH before multiplication. -- Id: A.19 function "*" (L : SIGNED; R : INTEGER) return SIGNED; -- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0) -- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is -- converted to a SIGNED vector of SIZE L'LENGTH before -- multiplication. -- Id: A.20 function "*" (L : INTEGER; R : SIGNED) return SIGNED; -- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0) -- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is -- converted to a SIGNED vector of SIZE R'LENGTH before -- multiplication. --============================================================================ -- -- NOTE: If second argument is zero for "/" operator, a severity level -- of ERROR is issued. -- Id: A.21 function "/" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R. -- Id: A.22 function "/" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Divides a SIGNED vector, L, by another SIGNED vector, R. -- Id: A.23 function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Divides an UNSIGNED vector, L, by a nonnegative INTEGER, R. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.24 function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Divides a nonnegative INTEGER, L, by an UNSIGNED vector, R. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. -- Id: A.25 function "/" (L : SIGNED; R : INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Divides a SIGNED vector, L, by an INTEGER, R. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.26 function "/" (L : INTEGER; R : SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Divides an INTEGER, L, by a SIGNED vector, R. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. --============================================================================ -- -- NOTE: If second argument is zero for "rem" operator, a severity level -- of ERROR is issued. -- Id: A.27 function "rem" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L and R are UNSIGNED vectors. -- Id: A.28 function "rem" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L and R are SIGNED vectors. -- Id: A.29 function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a -- nonnegative INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.30 function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a -- nonnegative INTEGER. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. -- Id: A.31 function "rem" (L : SIGNED; R : INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.32 function "rem" (L : INTEGER; R : SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. --============================================================================ -- -- NOTE: If second argument is zero for "mod" operator, a severity level -- of ERROR is issued. -- Id: A.33 function "mod" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L and R are UNSIGNED vectors. -- Id: A.34 function "mod" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L and R are SIGNED vectors. -- Id: A.35 function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L is an UNSIGNED vector and R -- is a nonnegative INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.36 function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where R is an UNSIGNED vector and L -- is a nonnegative INTEGER. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. -- Id: A.37 function "mod" (L : SIGNED; R : INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L is a SIGNED vector and -- R is an INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.38 function "mod" (L : INTEGER; R : SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L is an INTEGER and -- R is a SIGNED vector. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. --============================================================================ -- Comparison Operators --============================================================================ -- Id: C.1 function ">" (L, R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.2 function ">" (L, R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.3 function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is a nonnegative INTEGER and -- R is an UNSIGNED vector. -- Id: C.4 function ">" (L : INTEGER; R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is a INTEGER and -- R is a SIGNED vector. -- Id: C.5 function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is an UNSIGNED vector and -- R is a nonnegative INTEGER. -- Id: C.6 function ">" (L : SIGNED; R : INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is a SIGNED vector and -- R is a INTEGER. --============================================================================ -- Id: C.7 function "<" (L, R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.8 function "<" (L, R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.9 function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is a nonnegative INTEGER and -- R is an UNSIGNED vector. -- Id: C.10 function "<" (L : INTEGER; R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.11 function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is an UNSIGNED vector and -- R is a nonnegative INTEGER. -- Id: C.12 function "<" (L : SIGNED; R : INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.13 function "<=" (L, R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.14 function "<=" (L, R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.15 function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is a nonnegative INTEGER and -- R is an UNSIGNED vector. -- Id: C.16 function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.17 function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is an UNSIGNED vector and -- R is a nonnegative INTEGER. -- Id: C.18 function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.19 function ">=" (L, R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.20 function ">=" (L, R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.21 function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is a nonnegative INTEGER and -- R is an UNSIGNED vector. -- Id: C.22 function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.23 function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is an UNSIGNED vector and -- R is a nonnegative INTEGER. -- Id: C.24 function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.25 function "=" (L, R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.26 function "=" (L, R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.27 function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is a nonnegative INTEGER and -- R is an UNSIGNED vector. -- Id: C.28 function "=" (L : INTEGER; R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.29 function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is an UNSIGNED vector and -- R is a nonnegative INTEGER. -- Id: C.30 function "=" (L : SIGNED; R : INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.31 function "/=" (L, R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.32 function "/=" (L, R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.33 function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is a nonnegative INTEGER and -- R is an UNSIGNED vector. -- Id: C.34 function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.35 function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is an UNSIGNED vector and -- R is a nonnegative INTEGER. -- Id: C.36 function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Shift and Rotate Functions --============================================================================ -- Id: S.1 function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on an UNSIGNED vector COUNT times. -- The vacated positions are filled with '0'. -- The COUNT leftmost elements are lost. -- Id: S.2 function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-right on an UNSIGNED vector COUNT times. -- The vacated positions are filled with '0'. -- The COUNT rightmost elements are lost. -- Id: S.3 function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on a SIGNED vector COUNT times. -- The vacated positions are filled with '0'. -- The COUNT leftmost elements are lost. -- Id: S.4 function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-right on a SIGNED vector COUNT times. -- The vacated positions are filled with the leftmost -- element, ARG'LEFT. The COUNT rightmost elements are lost. --============================================================================ -- Id: S.5 function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times. -- Id: S.6 function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times. -- Id: S.7 function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a logical rotate-left of a SIGNED -- vector COUNT times. -- Id: S.8 function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a logical rotate-right of a SIGNED -- vector COUNT times. --============================================================================ ------------------------------------------------------------------------------ -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.9 function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: SHIFT_LEFT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.10 function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: SHIFT_LEFT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE StdL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.11 function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: SHIFT_RIGHT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.12 function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT)) ------------------------------------------------------------------------------ -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.13 function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_LEFT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.14 function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_LEFT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.15 function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_RIGHT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.16 function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_RIGHT(ARG, COUNT) --============================================================================ -- RESIZE Functions --============================================================================ -- Id: R.1 function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED; -- Result subtype: SIGNED(NEW_SIZE-1 downto 0) -- Result: Resizes the SIGNED vector ARG to the specified size. -- To create a larger vector, the new [leftmost] bit positions -- are filled with the sign bit (ARG'LEFT). When truncating, -- the sign bit is retained along with the rightmost part. -- Id: R.2 function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0) -- Result: Resizes the SIGNED vector ARG to the specified size. -- To create a larger vector, the new [leftmost] bit positions -- are filled with '0'. When truncating, the leftmost bits -- are dropped. --============================================================================ -- Conversion Functions --============================================================================ -- Id: D.1 function TO_INTEGER (ARG : UNSIGNED) return NATURAL; -- Result subtype: NATURAL. Value cannot be negative since parameter is an -- UNSIGNED vector. -- Result: Converts the UNSIGNED vector to an INTEGER. -- Id: D.2 function TO_INTEGER (ARG : SIGNED) return INTEGER; -- Result subtype: INTEGER -- Result: Converts a SIGNED vector to an INTEGER. -- Id: D.3 function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(SIZE-1 downto 0) -- Result: Converts a nonnegative INTEGER to an UNSIGNED vector with -- the specified SIZE. -- Id: D.4 function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED; -- Result subtype: SIGNED(SIZE-1 downto 0) -- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE. --============================================================================ -- Logical Operators --============================================================================ -- Id: L.1 function "not" (L : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Termwise inversion -- Id: L.2 function "and" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector AND operation -- Id: L.3 function "or" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector OR operation -- Id: L.4 function "nand" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector NAND operation -- Id: L.5 function "nor" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector NOR operation -- Id: L.6 function "xor" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector XOR operation -- --------------------------------------------------------------------------- -- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. -- --------------------------------------------------------------------------- -- Id: L.7 function "xnor" (L, R : UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector XNOR operation -- Id: L.8 function "not" (L : SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Termwise inversion -- Id: L.9 function "and" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector AND operation -- Id: L.10 function "or" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector OR operation -- Id: L.11 function "nand" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector NAND operation -- Id: L.12 function "nor" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector NOR operation -- Id: L.13 function "xor" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector XOR operation -- --------------------------------------------------------------------------- -- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. -- --------------------------------------------------------------------------- -- Id: L.14 function "xnor" (L, R : SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector XNOR operation --============================================================================ -- Match Functions --============================================================================ -- Id: M.1 function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent -- Id: M.2 function STD_MATCH (L, R : UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent -- Id: M.3 function STD_MATCH (L, R : SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent -- Id: M.4 function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent -- Id: M.5 function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent --============================================================================ -- Translation Functions --============================================================================ -- Id: T.1 function TO_01 (S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED; -- Result subtype: UNSIGNED(S'RANGE) -- Result: Termwise, 'H' is translated to '1', and 'L' is translated -- to '0'. If a value other than '0'|'1'|'H'|'L' is found, -- the array is set to (others => XMAP), and a warning is -- issued. -- Id: T.2 function TO_01 (S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED; -- Result subtype: SIGNED(S'RANGE) -- Result: Termwise, 'H' is translated to '1', and 'L' is translated -- to '0'. If a value other than '0'|'1'|'H'|'L' is found, -- the array is set to (others => XMAP), and a warning is -- issued. end package NUMERIC_STD;
gpl-3.0
545fb34361bdf7de6edf96ab4672c84f
0.560769
4.223959
false
false
false
false
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd
4
1,818
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_tb_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- architecture functional of S_R_flipflop is begin q <= '1' when s = '1' else '0' when r = '1'; q_n <= '0' when s = '1' else '1' when r = '1'; end architecture functional; entity tb_05_07 is end entity tb_05_07; architecture test of tb_05_07 is signal s, r : bit := '0'; signal q, q_n : bit; begin dut : entity work.S_R_flipflop(functional) port map ( s => s, r => r, q => q, q_n => q_n ); stimulus : process is begin wait for 10 ns; s <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '1'; wait for 10 ns; r <= '0'; wait for 10 ns; s <= '1'; wait for 10 ns; r <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '0'; wait for 10 ns; wait; end process stimulus; end architecture test;
gpl-2.0
088122ae24ce3d61bed8d634e0faba03
0.583058
3.436673
false
false
false
false
tgingold/ghdl
testsuite/gna/bug035/simulation.v93.vhdl
6
10,685
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Testbench: Simulation constants, functions and utilities. -- -- Authors: Patrick Lehmann -- Thomas B. Preusser -- -- Description: -- ------------------------------------ -- TODO -- -- License: -- ============================================================================= -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; library PoC; use PoC.vectors.all; use PoC.strings.all; use PoC.physical.all; package simulation is -- predefined constants to ease testvector concatenation constant U8 : T_SLV_8 := (others => 'U'); constant U16 : T_SLV_16 := (others => 'U'); constant U24 : T_SLV_24 := (others => 'U'); constant U32 : T_SLV_32 := (others => 'U'); constant D8 : T_SLV_8 := (others => '-'); constant D16 : T_SLV_16 := (others => '-'); constant D24 : T_SLV_24 := (others => '-'); constant D32 : T_SLV_32 := (others => '-'); -- Testbench Status Management -- =========================================================================== -- The testbench is marked as failed. If a message is provided, it is -- reported as an error. procedure tbFail(msg : in string := ""); -- If the passed condition has evaluated false, the testbench is marked -- as failed. In this case, the optional message will be reported as an -- error if one was provided. procedure tbAssert(cond : in boolean; msg : in string := ""); -- Prints out the overall testbench result as defined by the automated -- testbench process. Unless tbFail() or tbAssert() with a false condition -- have been called before, a successful completion will be reported, a -- failure otherwise. procedure tbPrintResult; -- clock generation -- =========================================================================== subtype T_DutyCycle is REAL range 0.0 to 1.0; procedure simStop; impure function simIsStopped return BOOLEAN; procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5); procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5); -- waveform generation -- =========================================================================== type T_SIM_WAVEFORM_TUPLE_SL is record Delay : TIME; Value : STD_LOGIC; end record; type T_SIM_WAVEFORM_TUPLE_SLV_8 is record Delay : TIME; Value : T_SLV_8; end record; type T_SIM_WAVEFORM_TUPLE_SLV_16 is record Delay : TIME; Value : T_SLV_16; end record; type T_SIM_WAVEFORM_TUPLE_SLV_24 is record Delay : TIME; Value : T_SLV_24; end record; type T_SIM_WAVEFORM_TUPLE_SLV_32 is record Delay : TIME; Value : T_SLV_32; end record; type T_SIM_WAVEFORM_TUPLE_SLV_48 is record Delay : TIME; Value : T_SLV_48; end record; type T_SIM_WAVEFORM_TUPLE_SLV_64 is record Delay : TIME; Value : T_SLV_64; end record; type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL; type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8; type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16; type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24; type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32; type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48; type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64; procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN); procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0'); procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0'); procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8); procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16); procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24); procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32); procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48); procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64); function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC; -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here -- checksum functions -- =========================================================================== -- TODO: move checksum functions here end; use std.TextIO.all; package body simulation is -- Testbench Status Management -- =========================================================================== -- Internal state variable to log a failure condition for final reporting. -- Once de-asserted, this variable will never return to a value of true. shared variable pass : boolean := true; shared variable simStopped : BOOLEAN := FALSE; procedure tbFail(msg : in string := "") is begin if (str_length(msg) > 0) then report str_trim(msg) severity error; end if; pass := false; end; procedure tbAssert(cond : in boolean; msg : in string := "") is begin if not cond then tbFail(msg); end if; end; procedure tbPrintResult is variable l : line; begin write(l, string'("SIMULATION RESULT = ")); if pass then write(l, string'("PASSED")); else write(l, string'("FAILED")); end if; writeline(output, l); end procedure; -- clock generation procedure simStop is begin simStopped := TRUE; end procedure; impure function simIsStopped return BOOLEAN is begin return simStopped; end function; procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is constant Period : TIME := to_time(Frequency); begin simGenerateClock(Clock, Period, DutyCycle); end procedure; procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is constant TIME_HIGH : TIME := Period * DutyCycle; constant TIME_LOW : TIME := Period - TIME_HIGH; begin Clock <= '0'; while (not simStopped) loop wait for TIME_LOW; Clock <= '1'; wait for TIME_HIGH; Clock <= '0'; end loop; end procedure; -- waveform generation procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is variable State : BOOLEAN := InitialValue; begin Wave <= State; for i in Waveform'range loop wait for Waveform(i); State := not State; Wave <= State; end loop; end procedure; procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is variable State : STD_LOGIC := InitialValue; begin Wave <= State; for i in Waveform'range loop wait for Waveform(i); State := not State; Wave <= State; end loop; end procedure; procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is begin Wave <= InitialValue; for i in Waveform'range loop wait for Waveform(i).Delay; Wave <= Waveform(i).Value; end loop; end procedure; procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is begin Wave <= InitialValue; for i in Waveform'range loop wait for Waveform(i).Delay; Wave <= Waveform(i).Value; end loop; end procedure; procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is begin Wave <= InitialValue; for i in Waveform'range loop wait for Waveform(i).Delay; Wave <= Waveform(i).Value; end loop; end procedure; procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is begin Wave <= InitialValue; for i in Waveform'range loop wait for Waveform(i).Delay; Wave <= Waveform(i).Value; end loop; end procedure; procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is begin Wave <= InitialValue; for i in Waveform'range loop wait for Waveform(i).Delay; Wave <= Waveform(i).Value; end loop; end procedure; procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is begin Wave <= InitialValue; for i in Waveform'range loop wait for Waveform(i).Delay; Wave <= Waveform(i).Value; end loop; end procedure; procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is begin Wave <= InitialValue; for i in Waveform'range loop wait for Waveform(i).Delay; Wave <= Waveform(i).Value; end loop; end procedure; function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is begin return (0 => Pause, 1 => ResetPulse); end function; -- checksum functions -- =========================================================================== -- TODO: move checksum functions here end package body;
gpl-2.0
44ddb28ddd6998208bf13174858898d5
0.64745
3.526403
false
false
false
false