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tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd | 4 | 1,502 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_13 is
end entity inline_13;
----------------------------------------------------------------
architecture test of inline_13 is
begin
process_3_b : process is
-- code from book:
type array1 is array (1 to 100) of integer;
type array2 is array (100 downto 1) of integer;
variable a1 : array1;
variable a2 : array2;
-- end of code from book
begin
a1(11 to 20) := a1(11 to 20);
a2(50 downto 41) := a2(50 downto 41);
a1(10 to 1) := a1(10 to 1);
a2(1 downto 10) := a2(1 downto 10);
a1(10 downto 1) := a1(10 downto 1); -- illegal
a2(1 to 10) := a2(1 to 10); -- illegal;
wait;
end process process_3_b;
end architecture test;
| gpl-2.0 | 89751c4f5d89d56cef18bf47ecb2a458 | 0.650466 | 3.727047 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd | 4 | 2,102 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
architecture test of inline_08 is
-- code from book
subtype state_vector is bit_vector(1 to 5);
-- end code from book
signal clk, reset : bit := '0';
signal word_in, word_out : bit_vector(0 to 31);
signal state_in, state_out : state_vector;
begin
-- code from book
word_reg : entity work.reg(behavioral)
generic map ( width => 32 )
port map ( -- . . . );
-- not in book
d => word_in, q => word_out, clk => clk, reset => reset );
-- end not in book
state_reg : entity work.reg(behavioral)
generic map ( width => state_vector'length )
port map ( -- . . . );
-- not in book
d => state_in, q => state_out, clk => clk, reset => reset );
-- end code from book
clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
reset_gen : reset <= '1' after 80 ns, '0' after 105 ns;
stimulus_word : word_in <= X"11111111" after 25 ns,
X"22222222" after 65 ns,
X"33333333" after 85 ns,
X"44444444" after 125 ns;
stimulus_state : state_in <= "00001" after 25 ns,
"00010" after 65 ns,
"00011" after 85 ns,
"00100" after 125 ns;
end architecture test;
| gpl-2.0 | ee965eb20b910a17b17e64aeca92c355 | 0.619886 | 3.842779 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1140/tb_ent.vhdl | 1 | 914 | entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_ent is
-- Interrupt mapping register:
signal iar : unsigned(15 downto 0) := "0000000010010000";
signal ipend : unsigned(3 downto 0) := (others => '0');
signal irq : unsigned(3 downto 0);
signal clk : std_logic := '0';
begin
dut: entity work.ent
generic map (NUM_CHANNELS => 4)
port map (iar => iar, ipend => ipend, irq => irq, clk => clk);
process
begin
clk <= not clk;
wait for 1 ns;
end process;
stim:
process
begin
wait for 10 ns;
ipend(0) <= '1';
wait for 10 ns;
ipend(1) <= '1';
wait for 10 ns;
ipend(2) <= '1';
wait for 10 ns;
ipend <= (others => '0');
wait for 10 ns;
ipend(3) <= '1';
wait for 10 ns;
ipend(2) <= '1';
wait for 10 ns;
ipend(1) <= '1';
wait for 10 ns;
ipend <= (others => '0');
wait;
end process;
end behav;
| gpl-2.0 | 2e6a24dbcfd8a863478d2a3cb76337bc | 0.606127 | 2.696165 | false | false | false | false |
lfmunoz/vhdl | templates/host_interface/generic_host_emu.vhd | 4 | 17,099 | --------------------------------------------------------------------------------
-- file name : sip_vp680_host_if.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library work;
use work.txt_util.all;
use work.std_logic_textio.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end entity generic_host_emu;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture behavioral of generic_host_emu is
--------------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------------
type std2d_32b is array(natural range <>) of std_logic_vector(31 downto 0);
-----------------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------------
signal clk_cmd : std_logic := '0';
signal clk125m : std_logic := '0';
signal out_cmd_val : std_logic := '0';
signal out_cmd : std_logic_vector(63 downto 0) := (others => '0');
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal write_data_val : std_logic := '0';
signal write_data : std_logic_vector(63 downto 0) := (others => '0');
signal read_data_stop : std_logic := '1';
signal read_data_val : std_logic;
signal read_data : std_logic_vector(63 downto 0);
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Clock generation
--------------------------------------------------------------------------------
clk_cmd <= sys_clk;
clk125m <= sys_clk;
--------------------------------------------------------------------------------
-- Perform SIP register read and writes
--------------------------------------------------------------------------------
process
file CMD_SCRIPT : text;
file INPUT_FILE : text;
variable BAR_array :std2d_32b(15 downto 0);
variable BAR_idx :integer range 16 downto 0 :=0;
variable textline : line;
variable sip_command : string(1 to 80);
variable char1 : string(1 to 1);
variable WaitDelay : integer := 0;
variable sip_addr : std_logic_vector(31 downto 0);
variable sip_bar_idx : std_logic_vector(3 downto 0);
variable sip_data : std_logic_vector(31 downto 0);
variable dmapush_size : std_logic_vector(31 downto 0);
variable dmapull_size : std_logic_vector(31 downto 0);
-- Procedure for writing a register
procedure cmd_write(addr : in std_logic_vector(31 downto 0); data : in std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"1" & addr(27 downto 0) & data;
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
REPORT "CMD Write: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_write;
-- Procedure for reading a register
procedure cmd_read(addr : in std_logic_vector(31 downto 0); data : inout std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"2" & addr(27 downto 0) & conv_std_logic_vector(0, 32);
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
wait until in_cmd_val = '1';
data := in_cmd(31 downto 0);
REPORT "CMD Read: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_read;
-- Procedure for pushing DMA to FPGA B
procedure dma_push(dma_size : in std_logic_vector(31 downto 0)) is
variable textline : line;
variable size : integer;
variable dma_data : std_logic_vector(63 downto 0);
begin
size := conv_integer(dma_size);
while (size > 0) loop
wait until clk125m = '0';
--if (in0_stop = '0') then
readline(INPUT_FILE, textline);
hread(textline, dma_data);
write_data_val <= '1';
write_data <= dma_data;
wait until clk125m = '1';
wait until clk125m = '0';
write_data_val <= '0';
size := size - 8;
--end if;
end loop;
REPORT "DMA Push, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_push;
-- Procedure for pulling DMA from FPGA B
procedure dma_pull(dma_size : in std_logic_vector(31 downto 0)) is
variable size : integer;
begin
-- This precedure only pulls down the stop signal for the right amount of time
-- data that comes available is written to file by the "Write data to file"
-- process elsewhere in this file.
size := conv_integer(dma_size);
-- Start reading fast, untill 8 words (64 bytes) left
while (size > 64) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
-- Read the last words slowly
while (size > 0) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
read_data_stop <= '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
read_data_stop <= '1';
REPORT "DMA Pull, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_pull;
variable fstatus: file_open_status; -- declare file
variable sip_mode:std_logic:='0';
begin
--script should start with 16 BAR definitions
for i in 1 to 15 loop
BAR_array(i) := (others=>'0');
end loop;
BAR_idx :=0;
wait for 1 us;
--open advanced sip script which is not compatible with the software sip script parser
file_open(fstatus,CMD_SCRIPT, "sip_cmd.asip", read_mode);
if (fstatus=OPEN_OK) then
sip_mode :='1';
else
file_open(fstatus,CMD_SCRIPT, "sip_cmd.sip", read_mode);
sip_mode := '0';
end if;
file_open(INPUT_FILE, "input.txt", read_mode);
while not endfile(CMD_SCRIPT) loop
readline(CMD_SCRIPT, textline);
next when textline'length = 0; -- Skip empty lines
-- Reset command
for i in 1 to sip_command'length loop
sip_command(i to i) := " ";
end loop;
-- Read command
for i in 1 to sip_command'length loop
-- Exit when exeeding the number of characters on the line
exit when i > textline'length;
read(textline, sip_command(i to i));
-- Comment
if (sip_command(1 to 1) = ";") then
read(textline, sip_command(1 to textline'length));
REPORT(sip_command) SEVERITY warning;
exit;
end if;
if(sip_mode='1') then
--assign to next BAR
if (sip_command(1 to 7) = "BAR_ADR") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, BAR_array(BAR_idx));
BAR_idx := BAR_idx + 1;
exit;
end if;
end if;
-- Write access
if (sip_command(1 to 7) = "REG_SET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
-- Collect data
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_data);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Write
cmd_write(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_write(sip_addr, sip_data);
end if;
exit;
end if;
-- Read access
if (sip_command(1 to 7) = "REG_GET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Read
cmd_read(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_read(sip_addr, sip_data);
end if;
exit;
end if;
-- DMA Push access (from host to card)
if (sip_command(1 to 7) = "DMAPUSH") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapush_size);
-- DMA to FPGA B
dma_push(dmapush_size);
exit;
end if;
-- DMA Pull access (from card to host)
if (sip_command(1 to 7) = "DMAPULL") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapull_size);
-- DMA from FPGA B
dma_pull(dmapull_size);
exit;
end if;
-- Wait
if (sip_command(1 to 4) = "WAIT") then
char1 := " ";
while (char1 /= "=") loop
read(textline, char1);
end loop;
read(textline, WaitDelay);
REPORT("Wait for " & str(WaitDelay) & " us");
for i in 1 to WaitDelay loop
wait for 1 us;
end loop;
exit;
end if;
end loop;
wait for 1 us;
end loop;
file_close(CMD_SCRIPT);
file_close(INPUT_FILE);
REPORT("Ready with reading SIP CMD script!");
wait for 10 us;
REPORT "Testbench ended" severity warning;
wait;
end process;
--------------------------------------------------------------------------------
-- Write data to file
--------------------------------------------------------------------------------
process
file OUTPUT_FILE : text;
variable textline : line;
begin
file_open(OUTPUT_FILE, "output.txt", write_mode);
file_close(OUTPUT_FILE);
while true loop
wait until clk125m = '1';
if (read_data_val = '1') then
file_open(OUTPUT_FILE, "output.txt", append_mode);
hwrite(textline, read_data);
writeline(OUTPUT_FILE, textline);
file_close(OUTPUT_FILE);
end if;
wait until clk125m = '0';
end loop;
wait;
end process;
--------------------------------------------------------------------------------
-- Connect entity
--------------------------------------------------------------------------------
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk <= clk_cmd;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout <= out_cmd;
cmd_out_cmdout_val <= out_cmd_val;
--Wormhole 'cmd_in' of type 'cmd_in':
in_cmd <= cmd_in_cmdin;
in_cmd_val <= cmd_in_cmdin_val;
--Wormhole 'ext_fc6301_host_if' of type 'ext_fc6301_host_if':
ifpga_rst_out_ifpga_rst <= not sys_reset_n;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop <= read_data_stop;
read_data_val <= in_data_in_dval;
read_data <= in_data_in_data;
--Wormhole 'out_data' of type 'wh_out':
out_data_out_dval <= write_data_val;
out_data_out_data <= write_data;
--------------------------------------------------------------------------------
-- End
--------------------------------------------------------------------------------
end architecture behavioral;
| mit | cf551464312f8d315a77b75823b64582 | 0.470378 | 4.106388 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1239/repro2.vhdl | 1 | 448 | library ieee;
use ieee.std_logic_1164.all;
entity repro2 is
generic (
constant DIN_WIDTH : positive := 8;
constant F_SIZE : positive := 2
);
end repro2;
architecture Behav of repro2 is
type SLIDING_WINDOW is array (0 to F_SIZE-1, 0 to F_SIZE-1)
of STD_LOGIC_VECTOR(DIN_WIDTH- 1 downto 0);
signal WINDOW: SLIDING_WINDOW;
begin
WINDOW <=(WINDOW 'range=> (WINDOW 'range=> (WINDOW 'range=>'0')));
end Behav;
| gpl-2.0 | b16fe19dd3119b9560f68d2f9d17d3e5 | 0.645089 | 3.270073 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/fsm_15.vhd | 2 | 12,307 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_15 is
port (
clock : in std_logic;
reset : in std_logic;
out3 : out std_logic;
out157 : out std_logic;
out159 : out std_logic;
out160 : out std_logic;
out171 : out std_logic;
out172 : out std_logic;
out173 : out std_logic;
out175 : out std_logic;
out178 : out std_logic;
in0 : in std_logic;
out0 : out std_logic;
in5 : in std_logic;
in6 : in std_logic;
in7 : in std_logic;
out35 : out std_logic;
out39 : out std_logic;
out40 : out std_logic;
out41 : out std_logic;
out44 : out std_logic;
out46 : out std_logic;
out140 : out std_logic;
in8 : in std_logic;
in9 : in std_logic;
in10 : in std_logic;
in11 : in std_logic;
in12 : in std_logic;
in13 : in std_logic;
in14 : in std_logic;
out65 : out std_logic;
in1 : in std_logic;
in2 : in std_logic;
in3 : in std_logic;
in4 : in std_logic;
out225 : out std_logic;
out227 : out std_logic;
out231 : out std_logic;
out235 : out std_logic;
out236 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out97 : out std_logic;
out98 : out std_logic;
out101 : out std_logic;
out102 : out std_logic;
out124 : out std_logic;
out125 : out std_logic;
out80 : out std_logic;
out81 : out std_logic;
out84 : out std_logic;
out86 : out std_logic;
out88 : out std_logic;
out93 : out std_logic;
out94 : out std_logic
);
end fsm_15;
architecture augh of fsm_15 is
signal state_cur : std_logic_vector(0 to 21) := (19 => '1', others => '0');
signal state_next : std_logic_vector(0 to 21) := (19 => '1', others => '0');
-- Buffers for outputs
signal out0_buf : std_logic := '0';
signal out0_bufn : std_logic;
signal out40_buf : std_logic := '0';
signal out40_bufn : std_logic;
signal out101_buf : std_logic := '0';
signal out101_bufn : std_logic;
signal out172_buf : std_logic := '0';
signal out172_bufn : std_logic;
-- Function calls: return IDs
signal funccall0 : unsigned(0 downto 0) := (others => '0');
signal funccall0_next : unsigned(0 downto 0) := (others => '0');
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out0_buf <= out0_bufn;
out40_buf <= out40_bufn;
out101_buf <= out101_bufn;
out172_buf <= out172_bufn;
-- Function calls: return IDs
funccall0 <= funccall0_next;
end if;
end process;
-- Combinatorial process
-- Compute the next state
-- Compute the outputs
process (
-- Inputs of the FSM
reset, in0, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in1, in2, in3, in4,
-- Function calls: return IDs
funccall0,
-- Current state
state_cur
)
begin
-- Reset the next state value
state_next <= (others => '0');
-- Default value to the outputs or output buffers
out46 <= '0';
out35 <= '0';
out65 <= '0';
out39 <= '0';
out3 <= '0';
out44 <= '0';
out0_bufn <= '0';
out41 <= '0';
out40_bufn <= '0';
out80 <= '0';
out81 <= '0';
out84 <= '0';
out86 <= '0';
out88 <= '0';
out93 <= '0';
out94 <= '0';
out97 <= '0';
out98 <= '0';
out101_bufn <= '0';
out102 <= '0';
out124 <= '0';
out125 <= '0';
out140 <= '0';
out157 <= '0';
out159 <= '0';
out160 <= '0';
out171 <= '0';
out172_bufn <= '0';
out173 <= '0';
out175 <= '0';
out178 <= '0';
out225 <= '0';
out227 <= '0';
out231 <= '0';
out235 <= '0';
out236 <= '0';
out237 <= '0';
out238 <= '0';
-- Function calls: default values (no change)
funccall0_next <= funccall0;
-- For all states, compute the next state bits
-- And the outputs, and the next value for buffered outputs
if state_cur(0) = '1' then
-- Next state
if ((in4) or (in3) or (in2)) = '1' then
state_next(17) <= '1';
-- Next values for buffered outputs
else
if (in1) = '1' then
-- Function call: memextrct_0
-- Save the origin of the call
funccall0_next <= to_unsigned(0, 1);
-- This is where the function call leads
state_next(4) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
else
if (in0) = '1' then
-- Function call: memextrct_1
state_next(2) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
else
state_next(17) <= '1';
-- Next values for buffered outputs
end if;
end if;
end if;
-- Assignment of non-buffered outputs
out3 <= '1';
end if;
if state_cur(1) = '1' then
-- Next state
if (in5) = '1' then
state_next(1) <= '1';
-- Next values for buffered outputs
out40_bufn <= '1';
else
-- Return from function: memextrct_1
-- Function call: memextrct_0
-- Save the origin of the call
funccall0_next <= to_unsigned(1, 1);
-- This is where the function call leads
state_next(4) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
end if;
-- Assignment of non-buffered outputs
out41 <= '1';
out39 <= '1';
out35 <= '1';
end if;
if state_cur(2) = '1' then
-- Next state
state_next(1) <= '1';
-- Next values for buffered outputs
out40_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
end if;
if state_cur(3) = '1' then
-- Next state
if (in6) = '1' then
state_next(3) <= '1';
-- Next values for buffered outputs
out40_bufn <= '1';
else
-- Return from function: memextrct_0
if funccall0 = 1 then
state_next(17) <= '1';
-- Next values for buffered outputs
end if;
-- Return from function: memextrct_0
if funccall0 = 0 then
state_next(17) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out41 <= '1';
out65 <= '1';
out46 <= '1';
end if;
if state_cur(4) = '1' then
-- Next state
state_next(3) <= '1';
-- Next values for buffered outputs
out40_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
end if;
if state_cur(5) = '1' then
-- Next state
if (in8) = '1' then
state_next(20) <= '1';
-- Next values for buffered outputs
else
if (not (in7)) = '1' then
state_next(5) <= '1';
-- Next values for buffered outputs
else
state_next(6) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out84 <= '1';
out81 <= '1';
out80 <= '1';
end if;
if state_cur(6) = '1' then
-- Next state
if (in8) = '1' then
state_next(20) <= '1';
-- Next values for buffered outputs
else
if (not (in9)) = '1' then
state_next(6) <= '1';
-- Next values for buffered outputs
else
state_next(7) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out88 <= '1';
out86 <= '1';
out81 <= '1';
end if;
if state_cur(7) = '1' then
-- Next state
if (in8) = '1' then
state_next(20) <= '1';
-- Next values for buffered outputs
else
if (not (in9)) = '1' then
state_next(7) <= '1';
-- Next values for buffered outputs
else
state_next(16) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out94 <= '1';
out93 <= '1';
out81 <= '1';
end if;
if state_cur(8) = '1' then
-- Next state
state_next(14) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out98 <= '1';
out97 <= '1';
end if;
if state_cur(9) = '1' then
-- Next state
if (in10) = '1' then
state_next(10) <= '1';
-- Next values for buffered outputs
out101_bufn <= '1';
else
state_next(5) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
end if;
if state_cur(10) = '1' then
-- Next state
state_next(11) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out102 <= '1';
end if;
if state_cur(11) = '1' then
-- Next state
state_next(13) <= '1';
-- Next values for buffered outputs
out172_bufn <= '1';
-- Assignment of non-buffered outputs
out125 <= '1';
out124 <= '1';
end if;
if state_cur(12) = '1' then
-- Next state
state_next(9) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out159 <= '1';
out157 <= '1';
out140 <= '1';
end if;
if state_cur(13) = '1' then
-- Next state
if (in8) = '1' then
state_next(20) <= '1';
-- Next values for buffered outputs
else
state_next(9) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out173 <= '1';
out171 <= '1';
out160 <= '1';
out81 <= '1';
end if;
if state_cur(14) = '1' then
-- Next state
if (in11) = '1' then
state_next(15) <= '1';
-- Next values for buffered outputs
out172_bufn <= '1';
out101_bufn <= '1';
else
state_next(12) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
end if;
if state_cur(15) = '1' then
-- Next state
if (in8) = '1' then
state_next(20) <= '1';
-- Next values for buffered outputs
else
state_next(14) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out173 <= '1';
out178 <= '1';
out175 <= '1';
out81 <= '1';
end if;
if state_cur(16) = '1' then
-- Next state
state_next(8) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out159 <= '1';
out227 <= '1';
out225 <= '1';
end if;
if state_cur(17) = '1' then
-- Next state
if (in12) = '1' then
if (in4) = '1' then
state_next(5) <= '1';
-- Next values for buffered outputs
else
if (in3) = '1' then
state_next(6) <= '1';
-- Next values for buffered outputs
else
if (in2) = '1' then
state_next(7) <= '1';
-- Next values for buffered outputs
else
if (in1) = '1' then
state_next(13) <= '1';
-- Next values for buffered outputs
out172_bufn <= '1';
else
state_next(15) <= '1';
-- Next values for buffered outputs
out172_bufn <= '1';
out101_bufn <= '1';
end if;
end if;
end if;
end if;
else
state_next(18) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out231 <= '1';
end if;
if state_cur(18) = '1' then
-- Next state
state_next(18) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
end if;
-- Info: This is the init/reset state
if state_cur(19) = '1' then
-- Next state
if (not (in13)) = '1' then
state_next(19) <= '1';
-- Next values for buffered outputs
else
if (in12) = '1' then
state_next(20) <= '1';
-- Next values for buffered outputs
else
state_next(6) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out236 <= '1';
out235 <= '1';
end if;
if state_cur(20) = '1' then
-- Next state
state_next(21) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out44 <= '1';
end if;
if state_cur(21) = '1' then
-- Next state
if (in14) = '1' then
state_next(21) <= '1';
-- Next values for buffered outputs
else
state_next(0) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
end if;
-- Assignment of non-buffered outputs
out41 <= '1';
out238 <= '1';
out237 <= '1';
end if;
-- Reset input
if reset = '1' then
-- Set the reset state
state_next <= (19 => '1', others => '0');
-- Note: Resetting all buffers for outputs here is not necessary.
-- It would cost hardware. They will be reset at the next clock front.
-- Reset state: set the buffered outputs
end if;
end process;
-- Assignment of buffered outputs
out0 <= out0_buf;
out40 <= out40_buf;
out101 <= out101_buf;
out172 <= out172_buf;
end architecture;
| gpl-2.0 | 29103f84444888258ea34fadb3121a78 | 0.56927 | 2.785019 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1165/bug.vhdl | 1 | 1,276 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
generic(
ADDR_WIDTH : positive := 32;
BUS_WIDTH : positive := 4;
QUEUE_LENGTH : positive := 32
);
port(
clk : in std_ulogic;
reset_n : in std_ulogic
);
end bug;
architecture behav of bug is
signal write_start_addr : unsigned(ADDR_WIDTH-1 downto 0);
signal num_words : integer range 0 to QUEUE_LENGTH-1;
function non_4k_crossing_length(start_addr : unsigned(ADDR_WIDTH-1 downto 0);
max_length : integer range 0 to QUEUE_LENGTH-1) return integer is
constant words_per_page : integer := 4096/BUS_WIDTH;
constant diff : integer range 0 to words_per_page := (words_per_page-(to_integer(start_addr)/BUS_WIDTH mod words_per_page));
begin
return minimum(diff, max_length);
end function;
begin
process(clk, reset_n)
variable aligned_start_addr : unsigned(ADDR_WIDTH-1 downto 0);
variable write_length : integer range 0 to QUEUE_LENGTH-1;
begin
if reset_n = '0' then
elsif rising_edge(clk) then
aligned_start_addr := resize(write_start_addr/BUS_WIDTH*BUS_WIDTH, ADDR_WIDTH);
write_length := non_4k_crossing_length(aligned_start_addr, num_words);
end if;
end process;
end architecture;
| gpl-2.0 | 49f011a5754f12d82b08b31aa8234fca | 0.6779 | 3.135135 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0109/ok.vhdl | 1 | 1,669 | library ieee;
use ieee.std_logic_1164.all;
package foo_pkg is
type unresolved_sfixed is array (integer range <>) of std_ulogic;
subtype sfixed is (resolved) UNRESOLVED_sfixed;
function to_string (inp: unresolved_sfixed) return string;
end package foo_pkg;
package body foo_pkg is
function to_string (inp: unresolved_sfixed) return string is
variable image_str: string (1 to inp'length + 1);
variable j: integer range 1 to image_str'length + 1;
begin
j := 1;
for i in inp'range loop
if i = -1 then
image_str(j) := ',';
j := j + 1;
end if;
image_str(j) := character'VALUE(std_ulogic'IMAGE(inp(i)));
j := j + 1;
end loop;
return image_str;
end function;
end package body foo_pkg;
library ieee;
use ieee.std_logic_1164.all;
use work.foo_pkg.all;
entity foo is
end entity;
architecture fum of foo is
constant sfixed_val: sfixed (3 downto -4):= x"da";
function to_string (inp: sfixed) return string is
variable image_str: string (1 to inp'length + 1);
variable j: integer range 1 to image_str'length + 1;
begin
j := 1;
for i in inp'range loop
if i = -1 then
image_str(j) := '.';
j := j + 1;
end if;
image_str(j) := character'VALUE(std_ulogic'IMAGE(inp(i)));
j := j + 1;
end loop;
return image_str;
end function;
begin
process
begin
report "sfixed_val = " & to_string(sfixed_val);
wait;
end process;
end architecture;
| gpl-2.0 | d51f1a34e52635c8418b14f05f311c3b | 0.55722 | 3.750562 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_timer_v2_0/hdl/src/vhdl/count_module.vhd | 3 | 9,609 | -------------------------------------------------------------------------------
-- count_module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: count_module.vhd
-- Version: v2.0
-- Description: Module with one counter and load register
--
-------------------------------------------------------------------------------
-- Structure:
--
-- count_module.vhd
-- -- counter_f.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_COUNT_WIDTH -- Width of the counter
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- clock
-- Reset -- reset
-- Load_DBus -- Count Load bus
-- Load_Counter_Reg -- Counter load control
-- Load_Load_Reg -- Load register control
-- Write_Load_Reg -- Write Control of TLR reg
-- CaptGen_Mux_Sel -- Mux select for capture and generate data
-- Counter_En -- Counter enable
-- Count_Down -- Count down
-- BE -- Byte enable
-- LoadReg_DBus -- Load reg bus
-- CounterReg_DBus -- Counter reg bus
-- Counter_TC -- counter Carry out signal
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.FDRE;
library axi_timer_v2_0_10;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity count_module is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32
);
port (
Clk : in std_logic;
Reset : in std_logic;
Load_DBus : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Load_Counter_Reg : in std_logic;
Load_Load_Reg : in std_logic;
Write_Load_Reg : in std_logic;
CaptGen_Mux_Sel : in std_logic;
Counter_En : in std_logic;
Count_Down : in std_logic;
BE : in std_Logic_vector(0 to 3);
LoadReg_DBus : out std_logic_vector(0 to C_COUNT_WIDTH-1);
CounterReg_DBus : out std_logic_vector(0 to C_COUNT_WIDTH-1);
Counter_TC : out std_logic
);
end entity count_module;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of count_module is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Signal Declaration
signal iCounterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal loadRegIn : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal load_Reg : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal load_load_reg_be : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal carry_out : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- Architecture imp
-------------------------------------------------------------------------------
--CAPTGEN_MUX_PROCESS : Process to implement mux the Load_DBus and
--iCounterReg_DBus
-------------------------------------------------------------------------------
CAPTGEN_MUX_PROCESS: process (CaptGen_Mux_Sel,Load_DBus,iCounterReg_DBus ) is
begin
if CaptGen_Mux_Sel='1' then
loadRegIn <= Load_DBus;
else
loadRegIn <= iCounterReg_DBus;
end if;
end process CAPTGEN_MUX_PROCESS;
-------------------------------------------------------------------------------
--LOAD_REG_GEN: To generate load register
-------------------------------------------------------------------------------
LOAD_REG_GEN: for i in 0 to C_COUNT_WIDTH-1 generate
load_load_reg_be(i) <= Load_Load_Reg or
(Write_Load_Reg and BE((i-C_COUNT_WIDTH+32)/8));
LOAD_REG_I: component FDRE
port map (
Q => load_Reg(i), -- [out]
C => Clk, -- [in]
CE => load_load_reg_be(i), -- [in]
D => loadRegIn(i), -- [in]
R => Reset -- [in]
);
end generate LOAD_REG_GEN;
-------------------------------------------------------------------------------
--counter_f module is instantiated
-------------------------------------------------------------------------------
COUNTER_I: entity axi_timer_v2_0_10.counter_f
generic map (
C_NUM_BITS => C_COUNT_WIDTH, -- [integer]
C_FAMILY => C_FAMILY -- [string]
)
port map(
Clk => Clk, -- [in std_logic]
Rst => Reset, -- [in std_logic]
Load_In => load_Reg, -- [in std_logic_vector]
Count_Enable => Counter_En, -- [in std_logic]
Count_Load => Load_Counter_Reg, -- [in std_logic]
Count_Down => Count_Down, -- [in std_logic]
Count_Out => iCounterReg_DBus, -- [out std_logic_vector]
Carry_Out => carry_out -- [out std_logic]
);
Counter_TC <= carry_out;
LoadReg_DBus <= load_Reg;
CounterReg_DBus <= iCounterReg_DBus;
end architecture imp;
| gpl-3.0 | 9f448a861d0befc571f1a9a74e68095c | 0.45114 | 4.960764 | false | false | false | false |
mistryalok/FPGA | Xilinx/ISE/Basics/RSFF_viva/RS_viva.vhd | 1 | 1,196 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:04:18 05/22/2013
-- Design Name:
-- Module Name: RS_viva - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RS_viva is
Port ( R : in STD_LOGIC;
S : in STD_LOGIC;
Q : out STD_LOGIC;
Qn : out STD_LOGIC;
clk : in STD_LOGIC);
end RS_viva;
architecture Behavioral of RS_viva is
begin
process(clk)
begin
if(clk='1' and clk'event)then
if(R='1')then
Q<= '0';
Qn <= '1';
elsif (s='1') then
q <= '1';
qn <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | b623a1de687e819956bffceeb7349a94 | 0.505853 | 3.497076 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | BSA/8bits/BSA8bits/BSA8bits.vhd | 1 | 1,587 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY BSA8bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC
);
END BSA8bits;
architecture strc_BSA8bits of BSA8bits is
SIGNAL Cin_temp, Cout_temp, Cout_sig, done: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(7 DOWNTO 0);
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg8Bit
PORT (
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end component;
begin
Reg_A: Reg8Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg8Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cin_temp,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg8Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
process(clk,rst,done)
variable counter: integer range 0 to 8 := 0;
begin
if rst = '1' then
Cin_temp <= '0';
elsif (clk='1' and clk'event) then
Out_sig(counter) <= (A_sig(counter) XOR B_sig(counter)) XOR Cin_temp;
Cin_temp <= (A_sig(counter) AND B_sig(counter)) OR (Cin_temp AND A_sig(counter)) OR (Cin_temp AND B_sig(counter));
counter := counter + 1;
end if;
end process;
end strc_BSA8bits; | mit | 65c7f5ffbf631760bb02b70fc13bc547 | 0.658475 | 2.576299 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_21.vhd | 4 | 2,002 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_21.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
reset_n : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
store : process (clock, reset_n) is
begin
if reset_n = '0' or reset_n = 'L' then
data_out <= (others => '0') after t_pd;
elsif rising_edge(clock) then
data_out <= data_in after t_pd;
end if;
end process store;
end architecture gate_level;
-- end not in book
| gpl-2.0 | 450ac0824a3e9a7843ffeb549c7dcbe7 | 0.527473 | 4.4 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/std_logic_1164-body.vhdl | 1 | 57,019 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body std_logic_1164 is
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
type stdlogic_1d is array (STD_ULOGIC) of STD_ULOGIC;
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
constant resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 |
('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z |
('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W |
('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L |
('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := 'Z'; -- weakest state default
begin
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
if (s'length = 1) then return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
constant and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 1 |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | Z |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | W |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | H |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- | - |
);
-- truth table for "or" function
constant or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U'), -- | U |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | Z |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | H |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X') -- | - |
);
-- truth table for "xor" function
constant xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- truth table for "not" function
constant not_table : stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X');
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (and_table(l, r));
end function "and";
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (and_table(l, r)));
end function "nand";
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (or_table(l, r));
end function "or";
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (or_table(l, r)));
end function "nor";
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (xor_table(l, r));
end function "xor";
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return not_table(xor_table(l, r));
end function "xnor";
function "not" (l : STD_ULOGIC) return UX01 is
begin
return (not_table(l));
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := and_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(and_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := or_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(or_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := xor_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(xor_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "xnor";
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => 'X');
begin
for i in result'range loop
result(i) := not_table(lv(i));
end loop;
return result;
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := and_table (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := and_table (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(and_table (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(and_table (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := or_table (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := or_table (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(or_table (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(or_table (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := xor_table (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := xor_table (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return not_table(result);
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return not_table(result);
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return not_table(result);
end function "xnor";
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
type logic_x01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01;
type logic_x01z_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01Z;
type logic_ux01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT is
begin
case s is
when '0' | 'L' => return ('0');
when '1' | 'H' => return ('1');
when others => return xmap;
end case;
end function To_bit;
--------------------------------------------------------------------
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0')
return BIT_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : BIT_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
case sv(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := xmap;
end case;
end loop;
return result;
end function To_bitvector;
--------------------------------------------------------------------
function To_StdULogic (b : BIT) return STD_ULOGIC is
begin
case b is
when '0' => return '0';
when '1' => return '1';
end case;
end function To_StdULogic;
--------------------------------------------------------------------
function To_StdLogicVector (b : BIT_VECTOR)
return STD_LOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_LOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdLogicVector (s : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_LOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (b : BIT_VECTOR)
return STD_ULOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_ULOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdULogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (s : STD_LOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdULogicVector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := xmap; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01 (sv(i));
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC) return X01 is
begin
return (cvt_to_x01(s));
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT) return X01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01z (sv(i));
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC) return X01Z is
begin
return (cvt_to_x01z(s));
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT) return X01Z is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01Z;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_ux01 (sv(i));
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC) return UX01 is
begin
return (cvt_to_ux01(s));
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT) return UX01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN is
begin
return l = '1' or l = 'H';
end function "??";
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '1') and
(To_X01(s'last_value) = '0'));
end function rising_edge;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '0') and
(To_X01(s'last_value) = '1'));
end function falling_edge;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
for i in s'range loop
case s(i) is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
end loop;
return false;
end function Is_X;
--------------------------------------------------------------------
function Is_X (s : STD_ULOGIC) return BOOLEAN is
begin
case s is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
return false;
end function Is_X;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
function TO_OSTRING (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*3 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*3);
variable result : STRING(1 to result_length);
variable tri : STD_ULOGIC_VECTOR(1 to 3);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
tri := To_X01Z(padded_value(3*i-2 to 3*i));
case tri is
when o"0" => result(i) := '0';
when o"1" => result(i) := '1';
when o"2" => result(i) := '2';
when o"3" => result(i) := '3';
when o"4" => result(i) := '4';
when o"5" => result(i) := '5';
when o"6" => result(i) := '6';
when o"7" => result(i) := '7';
when "ZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function TO_OSTRING;
function TO_HSTRING (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*4 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*4);
variable result : STRING(1 to result_length);
variable quad : STD_ULOGIC_VECTOR(1 to 4);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
quad := To_X01Z(padded_value(4*i-3 to 4*i));
case quad is
when x"0" => result(i) := '0';
when x"1" => result(i) := '1';
when x"2" => result(i) := '2';
when x"3" => result(i) := '3';
when x"4" => result(i) := '4';
when x"5" => result(i) := '5';
when x"6" => result(i) := '6';
when x"7" => result(i) := '7';
when x"8" => result(i) := '8';
when x"9" => result(i) := '9';
when x"A" => result(i) := 'A';
when x"B" => result(i) := 'B';
when x"C" => result(i) := 'C';
when x"D" => result(i) := 'D';
when x"E" => result(i) := 'E';
when x"F" => result(i) := 'F';
when "ZZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function TO_HSTRING;
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable c : CHARACTER;
variable left : positive;
begin
while L /= null and L.all'length /= 0 loop
left := L.all'left;
c := L.all(left);
if (c = ' ' or c = NBSP or c = HT) then
read (L, c);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
skip_whitespace (L);
read (L, c, readOk);
if not readOk then
GOOD := false;
else
if char_to_MVL9plus(c) = error then
GOOD := false;
else
VALUE := char_to_MVL9(c);
GOOD := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, readOk);
i := 0;
GOOD := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
GOOD := false;
return;
elsif c = '_' then
if i = 0 then
GOOD := false; -- Begins with an "_"
return;
elsif lastu then
GOOD := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
GOOD := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
skip_whitespace (L);
read (L, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (L, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(L, MVL9_to_char(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
alias m : STD_ULOGIC_VECTOR(1 to VALUE'length) is VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure Char2TriBits (C : in CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case C is
when '0' => RESULT := o"0"; GOOD := true;
when '1' => RESULT := o"1"; GOOD := true;
when '2' => RESULT := o"2"; GOOD := true;
when '3' => RESULT := o"3"; GOOD := true;
when '4' => RESULT := o"4"; GOOD := true;
when '5' => RESULT := o"5"; GOOD := true;
when '6' => RESULT := o"6"; GOOD := true;
when '7' => RESULT := o"7"; GOOD := true;
when 'Z' => RESULT := "ZZZ"; GOOD := true;
when 'X' => RESULT := "XXX"; GOOD := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & C &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
elsif c = '_' then
if i = 0 then
GOOD := false; -- Begins with an "_"
return;
elsif lastu then
GOOD := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
else
GOOD := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case C is
when '0' => RESULT := x"0"; GOOD := true;
when '1' => RESULT := x"1"; GOOD := true;
when '2' => RESULT := x"2"; GOOD := true;
when '3' => RESULT := x"3"; GOOD := true;
when '4' => RESULT := x"4"; GOOD := true;
when '5' => RESULT := x"5"; GOOD := true;
when '6' => RESULT := x"6"; GOOD := true;
when '7' => RESULT := x"7"; GOOD := true;
when '8' => RESULT := x"8"; GOOD := true;
when '9' => RESULT := x"9"; GOOD := true;
when 'A' | 'a' => RESULT := x"A"; GOOD := true;
when 'B' | 'b' => RESULT := x"B"; GOOD := true;
when 'C' | 'c' => RESULT := x"C"; GOOD := true;
when 'D' | 'd' => RESULT := x"D"; GOOD := true;
when 'E' | 'e' => RESULT := x"E"; GOOD := true;
when 'F' | 'f' => RESULT := x"F"; GOOD := true;
when 'Z' => RESULT := "ZZZZ"; GOOD := true;
when 'X' => RESULT := "XXXX"; GOOD := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Error: Read a '" & C &
"', expected a Hex character (0-F)."
severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
elsif c = '_' then
if i = 0 then
GOOD := false; -- Begins with an "_"
return;
elsif lastu then
GOOD := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
else
GOOD := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, TO_OSTRING(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, TO_HSTRING (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
end package body std_logic_1164;
| gpl-2.0 | 1fb140858a3647de18018c95d645d550 | 0.439117 | 3.954709 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug045/repro.vhdl | 2 | 723 | entity sub is
generic (l : natural);
port (a : out bit;
b : bit_vector (0 to 3);
c : bit_vector (0 to l - 1));
end sub;
architecture behav of sub is
begin
a <= b (0) xor c (0);
end behav;
entity tb is
end tb;
architecture behav of tb is
signal a : bit;
signal b: bit_vector (0 to 3);
signal c: bit_vector (0 to 7);
type state is (S0, S1, S_done);
signal s : state := S0;
begin
my_sub: entity work.sub
generic map (l => c'length)
port map (a => a, b => b, c => c);
process
begin
wait for 1 ns;
assert a = '0';
b <= x"0";
c <= x"80";
s <= s1;
wait for 1 ns;
assert a = '1';
s <= S_done;
wait for 1 ns;
wait;
end process;
end behav;
| gpl-2.0 | d99970170223682de767a6d96e44950c | 0.538036 | 2.857708 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_06.vhd | 4 | 1,918 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 24;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
subtype opcode is bit_vector(5 downto 0);
function extract_opcode ( instr_word : word ) return opcode;
constant op_nop : opcode := "000000";
constant op_breq : opcode := "000001";
constant op_brne : opcode := "000010";
constant op_add : opcode := "000011";
-- . . .
end package cpu_types;
-- not in book
package body cpu_types is
function extract_opcode ( instr_word : word ) return opcode is
begin
return work.cpu_types.op_nop;
end function extract_opcode;
end package body cpu_types;
-- end not in book
| gpl-2.0 | 7d850c48dc18d8a7d52eadd9ba353ccd | 0.638686 | 3.898374 | false | false | false | false |
LaurentCabaret/pyVhdl2Sch | datas/test_files/demo.vhd | 1 | 4,216 | -- Module Name: InputGate - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entIty InputGate is
Generic (
wSize :integer := 9;
hSize :integer := 9;
imgWidth : integer := 512; -- Largeur de l'image
imgHeight : integer := 512); -- Hauteur de l'image
Port ( Clk : in STD_LOGIC;
PxClk : in STD_LOGIC;
PxVal : in STD_LOGIC;
a: in std_logic_vector (5 downto 0);
b : in std_logic_vector(5 downto 0);
c: in std_logic_vector(5 downto 0);
d : in std_logic_vector (5 downto 0);
PxValOut : out STD_LOGIC;
Lig : out std_logic_vector (wSize-1 downto 0);
Lig32 : out std_logic_vector (3 to long_wSize-1);
Col : out std_logic_vector (1 to 8);
StatusInner : out std_logic;
daInOut!@g : inout std_logic_vector (134 downto 7);
FirstPass : out std_logic := '0');
end InputGate;
architecture Behavioral of InputGate is
CONSTANT LargeurBits : integer :=wSize;
CONSTANT HauteurBits : integer :=hSize;
COMPONENT AccessManager IS
generic (
hBusSize : integer range 0 to 11;
vBusSize : integer range 0 to 11;
imgWidth : integer range 0 to 1920;
imgHeight : integer range 0 to 1080
);
port (
C_Add : in std_logic_vector (hBusSize-1 downto 0);
L_Add : in std_logic_vector (0 to vBusSize-1);
StatusInner : out std_logic;
UpLeftCorner : out std_logic;
FirstLine : out std_logic;
FirstRow : out std_logic;
LastRow : out std_logic;
LastPixel : out std_logic
);
END COMPONENT;
signal CleanPxClk : std_logic :='0';
SIGNAL C_Add : std_logic_vector (LargeurBits-1 downto 0) := (others=>'0');
SIGNAL L_Add : std_logic_vector (HauteurBits-1 downto 0) := (others=>'0');
SIGNAL SigLastRow : std_logic := '0';
SIGNAL SigLastPixel : std_logic := '0';
SIGNAL fPass : std_logic := '1';
begin
AM1: AccessManager GENERIC MAP(
hBusSize => LargeurBits,
vBusSize => HauteurBits,
imgWidth => imgWidth,
imgHeight => imgHeight
)
PORT MAP(
C_Add => C_Add,
L_Add => L_Add,
StatusInner => StatusInner,
UpLeftCorner => UpLeftCorner,
FirstLine => FirstLine,
FirstRow => FirstRow,
LastRow => SigLastRow ,
LastPixel => SigLastPixel
);
PxClkEventManager: process(Clk)
variable flag : std_logic := '1';
begin
if Clk'Event and Clk='1' then
if (PxClk = '1' and flag = '0') then CleanPxClk <='1';
flag:='1';
elsif PxClk = '0' then flag:='0';
CleanPxClk <='0';
elsif PxClk = '1' and flag = '1' then CleanPxClk <='0';
flag:='1';
end if;
end if;
end process;
FirstPass <= fPass;
PixelCounter: process(Clk)
variable flag : std_logic := '1';
variable flagPass : std_logic := '0';
begin
if Clk'Event and Clk='1' then
if CleanPxClk = '1' then
if SigLastRow='1' then C_Add <= (others=>'0');
if SigLastPixel ='1' then L_Add <= (others=>'0');
if flagPass = '0' then fPass <= '0';
flagPass := '1';
else fPass <= '1';
flagPass := '0';
end if;
else L_Add <= L_Add + 1;
end if;
else C_Add <= C_Add + 1;
end if;
end if;
end if;
end process;
Col <= C_Add;
Lig <= L_Add;
LastRow <= SigLastRow;
LastPixel <= SigLastPixel;
PxValOut <= PxVal;
end Behavioral;
| bsd-2-clause | 544dd88d7d9896441ffa997cd77c56cc | 0.475806 | 3.839709 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd | 4 | 1,832 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity reg_read_selector is
end entity reg_read_selector;
architecture test of reg_read_selector is
constant reg0 : std_logic_vector(7 downto 0) := "00000000";
constant reg1 : std_logic_vector(7 downto 0) := "11111111";
signal dbus : std_logic_vector(7 downto 0);
signal reg_sel, read, reg_addr : X01 := '0';
begin
-- code from book
reg_read_selector : block (reg_sel = '1' and read = '1') is
begin
dbus <= reg0 when guard and reg_addr = '0' else
reg1 when guard and reg_addr = '1' else
"ZZZZZZZZ";
end block reg_read_selector;
-- end code from book
stimulus : process is
begin
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_sel <= '0'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_addr <= '1'; wait for 10 ns;
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 86822409c02336615233d680ce6a03f0 | 0.668668 | 3.54352 | false | true | false | false |
tgingold/ghdl | testsuite/synth/case02/case03.vhdl | 1 | 834 | library ieee;
use ieee.std_logic_1164.all;
entity case03 is
port (
clk : in std_logic;
opc : in std_logic_vector (2 downto 0);
arg : in std_logic_vector (7 downto 0);
res : out std_logic_vector (7 downto 0);
par : out std_logic);
end case03;
architecture behav of case03 is
signal result : std_logic_vector(7 downto 0);
signal parity : std_logic;
begin
process (clk)
begin
if rising_edge(clk) then
res <= result;
par <= parity;
end if;
end process;
op : process (opc, arg)
variable t : std_logic_vector(7 downto 0);
variable p : std_logic;
begin
p := '0';
case opc is
when "000" | "001" | "010" | "011" =>
t := not arg;
for i in t'range loop
p := p xor t(i);
end loop;
when others =>
t := arg;
end case;
result <= t;
parity <= p;
end process;
end behav;
| gpl-2.0 | 507eeb78a918ac97c8122cb24689e851 | 0.607914 | 2.856164 | false | false | false | false |
tgingold/ghdl | testsuite/synth/rec01/tb_rec01.vhdl | 1 | 772 | entity tb_rec01 is
end tb_rec01;
library ieee;
use ieee.std_logic_1164.all;
use work.rec01_pkg.all;
architecture behav of tb_rec01 is
signal inp : myrec;
signal clk : std_logic;
signal rst : std_logic;
signal r : std_logic;
begin
dut: entity work.rec01
port map (inp => inp, clk => clk, rst => rst, o => r);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
assert r = '1' severity failure;
rst <= '0';
inp <= (a => "0010", b => '1');
pulse;
assert r = '1' severity failure;
rst <= '0';
inp <= (a => "0001", b => '1');
pulse;
assert r = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 49639426a9c0b84b4ea153f78902eda7 | 0.549223 | 3.138211 | false | false | false | false |
nickg/nvc | test/regress/signal27.vhd | 1 | 724 | entity signal27 is
end entity;
architecture test of signal27 is
type rec is record
x, y : integer;
z : bit_vector(1 to 3);
end record;
procedure update(signal r : inout rec) is
begin
r <= (r.x + 1, r.y + 1, not r.z);
wait for 1 ns;
end procedure;
signal a : integer := 0;
signal b : integer := 5;
signal c : bit_vector(1 to 3) := "101";
begin
p1: process is
begin
update(r.x => a, r.y => b, r.z => c);
assert a = 1;
assert b = 6;
assert c = "010";
update(r.x => b, r.y => a, r.z => c);
assert a = 2;
assert b = 7;
assert c = "101";
wait;
end process;
end architecture;
| gpl-3.0 | 2094888323708d7e3ef8c7c4a5e889cb | 0.491713 | 3.261261 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_14.vhd | 3 | 2,286 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_14.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity decoder_3_to_8 is
generic ( Tpd_01, Tpd_10 : delay_length );
port ( s0, s1, s2 : in bit;
enable : in bit;
y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
end entity decoder_3_to_8;
-- not in book
architecture basic of decoder_3_to_8 is
subtype bv_vec3 is bit_vector (2 downto 0);
begin
process (enable, s2, s1, s0) is
begin
if enable = '0' then
(y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000000");
else
case bv_vec3'(s2, s1, s0) is
when "000" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000001");
when "001" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000010");
when "010" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000100");
when "011" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00001000");
when "100" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00010000");
when "101" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00100000");
when "110" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("01000000");
when "111" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("10000000");
end case;
end if;
end process;
end architecture basic;
-- end not in book
| gpl-2.0 | c7f91042cbf74deebdbaaad2389332a5 | 0.570429 | 2.949677 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc763.vhd | 4 | 8,105 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc763.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00763pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00763pkg;
use work.c01s01b01x01p05n02i00763pkg.ALL;
ENTITY c01s01b01x01p05n02i00763ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00763ent;
ARCHITECTURE c01s01b01x01p05n02i00763arch OF c01s01b01x01p05n02i00763ent IS
signal Vgen1 : boolean := true;
signal Vgen2 : bit := '1';
signal Vgen3 : character := 's';
signal Vgen4 : severity_level:= note;
signal Vgen5 : integer := 3;
signal Vgen6 : real := 3.0;
signal Vgen7 : time := 3 ns;
signal Vgen8 : natural := 1;
signal Vgen9 : positive := 1;
signal Vgen70 : boolean_vector_st :=(others => Cgen1);
signal Vgen71 : severity_level_vector_st :=(others => Cgen4);
signal Vgen72 : integer_vector_st :=(others => Cgen5);
signal Vgen73 : real_vector_st :=(others => Cgen6);
signal Vgen74 : time_vector_st :=(others => Cgen7);
signal Vgen75 : natural_vector_st :=(others => Cgen8);
signal Vgen76 : positive_vector_st :=(others => Cgen9);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00763"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00763 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00763arch;
| gpl-2.0 | 9c96c25ee30b107574e16890421a196a | 0.602344 | 3.833964 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd | 4 | 1,257 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
wait until clk = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
end process incrementer;
end architecture behavior;
| gpl-2.0 | 53e839aa334881b94a6fe401230aa382 | 0.684169 | 4.304795 | false | false | false | false |
nickg/nvc | test/regress/issue414.vhd | 1 | 1,639 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue414 is
end issue414;
architecture behavioral of issue414 is
signal clk : std_logic := '0';
signal addr : std_logic_vector(55 downto 0);
signal wdata : std_logic_vector(31 downto 0);
subtype uword64 is unsigned(63 downto 0);
signal running : boolean := true;
begin
process (clk, running)
begin
if running then
clk <= not clk after 5 ns;
end if;
end process;
process
procedure wr_data(address_in : std_logic_vector; data : std_logic_vector;
do_wait : boolean) is
-- Without this things work!
constant address : std_logic_vector(address_in'length - 1 downto 0) := address_in;
begin
-- Without this I get, for high enough loop counts (1000000+):
-- zsh: segmentation fault nvc -a bug4.vhd -e bug4 -r
if do_wait then
wait until clk = '1';
end if;
end;
procedure wr_data(address : unsigned; data : unsigned;
do_wait : boolean) is
begin
wr_data(std_logic_vector(address), std_logic_vector(data), do_wait);
end;
variable addr : unsigned(55 downto 0) := (others => '0');
variable slvdata : unsigned(31 downto 0) := (others => '0');
begin
-- 1000 is OK
for n in 0 to 4000 loop
wr_data(addr, slvdata, do_wait => true); -- SIGBUS crash
end loop;
for n in 0 to 1000000 loop
wr_data(addr, slvdata, do_wait => false); -- Stack overflow
end loop;
assert false report "Test OK" severity warning;
running <= false;
wait;
end process;
end behavioral;
| gpl-3.0 | 429d141fadccb3d9300b64a9416f9245 | 0.621721 | 3.634146 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/uart_dcfifo_out.vhd | 1 | 7,864 | -- megafunction wizard: %LPM_FIFO+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: uart_dcfifo_out.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY uart_dcfifo_out IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END uart_dcfifo_out;
ARCHITECTURE SYN OF uart_dcfifo_out IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
wrclk : IN STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
rdempty <= sub_wire0;
q <= sub_wire1(7 DOWNTO 0);
rdusedw <= sub_wire2(5 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone II",
lpm_hint => "MAXIMIZE_SPEED=7,",
lpm_numwords => 64,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 6,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
wrclk => wrclk,
rdreq => rdreq,
aclr => aclr,
rdclk => rdclk,
wrreq => wrreq,
data => data,
rdempty => sub_wire0,
q => sub_wire1,
rdusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "64"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=7,"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: rdusedw 0 0 6 0 OUTPUT NODEFVAL rdusedw[5..0]
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: rdusedw 0 0 6 0 @rdusedw 0 0 6 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_out.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_out.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_out.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_out.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_out_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_out_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_out_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | c07e23dc425cf7ccdc24f189ad6eb3e2 | 0.652467 | 3.464317 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue30/alu.vhdl | 2 | 40,392 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity ccf_operation is
port(
flags_in: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_ccf_operation of ccf_operation is
begin
-- A point of disagreement has been found between the Z80 user manual
-- and Lance Levinthal's book entitled "Z80 Assembly Language Programming".
-- The Z80 user manual says the half-carry bit gets the previous carry;
-- Levinthal says the half-carry bit is unchanged. For now, go with
-- Levinthal's version as the Z80 users manual is inconsistent with
-- itself on other instructions. At this time, no such inconsistencies
-- have been found with Levinthal's work.
flags_out <= ( carry_bit => not flags_in(carry_bit),
half_carry_bit => flags_in(carry_bit),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sll8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sll8bit of sll8bit is
signal sll_result: std_logic_vector(7 downto 0);
begin
-- This operation is not documented by Zilog, but seems to work in their
-- finished chip. This code may not work the same way as the Z80 hardware
-- works. The functionality is assumed from the SRL instruction.
sll_result <= operand(6 downto 0) & '0';
output <= sll_result;
flags_out <= ( carry_bit => operand(7),
zero_bit => not (sll_result(7) or sll_result(6) or sll_result(5) or sll_result(4) or
sll_result(3) or sll_result(2) or sll_result(1) or sll_result(0)),
parity_overflow_bit => not (sll_result(7) xor sll_result(6) xor sll_result(5) xor
sll_result(4) xor sll_result(3) xor sll_result(2) xor
sll_result(1) xor sll_result(0)),
sign_bit => operand(6),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity srl8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_srl8bit of srl8bit is
signal srl_result: std_logic_vector(7 downto 0);
begin
srl_result <= '0' & operand(7 downto 1);
output <= srl_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (srl_result(7) or srl_result(6) or srl_result(5) or srl_result(4) or
srl_result(3) or srl_result(2) or srl_result(1) or srl_result(0)),
parity_overflow_bit => not (srl_result(7) xor srl_result(6) xor srl_result(5) xor
srl_result(4) xor srl_result(3) xor srl_result(2) xor
srl_result(1) xor srl_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity and8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_and8bit of and8bit is
signal and_result: std_logic_vector(7 downto 0);
begin
and_result <= operand1 and operand2;
flags_out <= ( sign_bit => and_result(7),
zero_bit => not (and_result(7) or and_result(6) or and_result(5) or and_result(4) or
and_result(3) or and_result(2) or and_result(1) or and_result(0)),
half_carry_bit => '1',
parity_overflow_bit => not (and_result(7) xor and_result(6) xor and_result(5) xor
and_result(4) xor and_result(3) xor and_result(2) xor
and_result(1) xor and_result(0)),
others => '0');
output <= and_result;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity or8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_or8bit of or8bit is
signal or_result: std_logic_vector(7 downto 0);
begin
or_result <= operand1 or operand2;
output <= or_result;
flags_out <= ( sign_bit => or_result(7),
half_carry_bit => '1',
zero_bit => not (or_result(7) or or_result(6) or or_result(5) or or_result(4) or
or_result(3) or or_result(2) or or_result(1) or or_result(0)),
parity_overflow_bit => not (or_result(7) xor or_result(6) xor or_result(5) xor
or_result(4) xor or_result(3) xor or_result(2) xor
or_result(1) xor or_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sra8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sra8bit of sra8bit is
signal sra_result: std_logic_vector(7 downto 0);
begin
sra_result <= operand(7) & operand(7 downto 1);
output <= sra_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (sra_result(7) or sra_result(6) or sra_result(5) or sra_result(4) or
sra_result(3) or sra_result(2) or sra_result(1) or sra_result(0)),
parity_overflow_bit => not (sra_result(7) xor sra_result(6) xor sra_result(5) xor
sra_result(4) xor sra_result(3) xor sra_result(2) xor
sra_result(1) xor sra_result(0)),
sign_bit => operand(7),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity xor8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_xor8bit of xor8bit is
signal xor_result: std_logic_vector(7 downto 0);
begin
xor_result <= operand1 xor operand2;
output <= xor_result;
flags_out <= ( sign_bit => xor_result(7),
half_carry_bit => '1',
zero_bit => not (xor_result(7) or xor_result(6) or xor_result(5) or xor_result(4) or
xor_result(3) or xor_result(2) or xor_result(1) or xor_result(0)),
parity_overflow_bit => not (xor_result(7) xor xor_result(6) xor xor_result(5) xor
xor_result(4) xor xor_result(3) xor xor_result(2) xor
xor_result(1) xor xor_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity sla8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_sla8bit of sla8bit is
signal sla_result: std_logic_vector(7 downto 0);
begin
sla_result <= operand(6 downto 0) & '0';
output <= sla_result;
flags_out <= ( sign_bit => sla_result(7),
half_carry_bit => '1',
zero_bit => not (sla_result(7) or sla_result(6) or sla_result(5) or sla_result(4) or
sla_result(3) or sla_result(2) or sla_result(1) or sla_result(0)),
parity_overflow_bit => not (sla_result(7) xor sla_result(6) xor sla_result(5) xor
sla_result(4) xor sla_result(3) xor sla_result(2) xor
sla_result(1) xor sla_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end;
architecture struct_subtractor of subtractor is
begin
-- These expressions were derived from the truth table of a single bit subtractor and simplified with
-- a Karnaugh map.
difference <= (borrow_in and (not minuend) and (not subtrahend)) or
((not borrow_in) and (not minuend) and subtrahend) or
(borrow_in and minuend and subtrahend) or
((not borrow_in) and minuend and (not subtrahend));
borrow_out <= (not minuend and subtrahend) or
(borrow_in and (not minuend)) or
(borrow_in and subtrahend);
end;
library ieee;
use ieee.std_logic_1164.all;
entity subtractorN is
generic(
N: positive
);
port(
minuend: in std_logic_vector((N-1) downto 0);
subtrahend: in std_logic_vector((N-1) downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector((N-1) downto 0);
borrow_out: out std_logic
);
end;
architecture struct_subtractorN of subtractorN is
component subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end component;
signal borrow: std_logic_vector(N downto 0);
begin
-- These expressions were derived from the truth table of a single bit subtractor and simplified with a
-- Karnaugh map.
-- d = difference, m = minuend, s = subtrahend, b = borrow
--
-- d(i) = (b(i) and (not m(i)) and (not s(i))) or
-- ((not b(i)) and (not m(i)) and s(i)) or
-- (b(i) and m(i) and s(i)) or
-- ((not b(i)) and m(i) and (not s(i)))
--
-- b(i+1) = (not m(i) and s(i)) or
-- (b(i) and (not m(i))) or
-- (b(i) and s(i)
borrow(0) <= borrow_in;
u1: for i in 0 to (N-1) generate
u: subtractor port map(
minuend => minuend(i),
subtrahend => subtrahend(i),
borrow_in => borrow(i),
difference => difference(i),
borrow_out => borrow(i+1)
);
end generate;
borrow_out <= borrow(N);
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity subtractor8x2 is
port(
minuend, subtrahend: in std_logic_vector(7 downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_subtractor8x2 of subtractor8x2 is
component subtractor is
port(
minuend, subtrahend: in std_logic;
borrow_in: in std_logic;
difference: out std_logic;
borrow_out: out std_logic
);
end component;
signal borrow: std_logic_vector(8 downto 0);
signal d: std_logic_vector(7 downto 0);
begin
borrow(0) <= borrow_in;
u1: for i in 0 to 7 generate
u: subtractor port map(
minuend => minuend(i),
subtrahend => subtrahend(i),
borrow_in => borrow(i),
difference => d(i),
borrow_out => borrow(i+1)
);
end generate;
difference <= d;
flags_out <= ( sign_bit => d(7),
zero_bit => not (d(0) or d(1) or d(2) or d(3) or d(4) or d(5) or d(6) or d(7)),
half_carry_bit => borrow(4),
parity_overflow_bit => (minuend(7) xor subtrahend(7)) and (minuend(7) xor d(7)),
add_sub_bit => '1',
carry_bit => borrow(8),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end;
architecture struct_adder of adder is
begin
-- These expressions are derived from a single bit full adder truth table and simplified with a
-- Karnaugh map.
sum <= ((not (carry_in)) and (not addend) and augend) or
((not carry_in) and addend and (not augend)) or
(carry_in and (not addend) and (not augend)) or
(carry_in and addend and augend);
carry_out <= (addend and augend) or
(carry_in and addend) or
(carry_in and augend);
end;
library ieee;
use ieee.std_logic_1164.all;
entity adderN is
generic(
N: positive
);
port(
addend: in std_logic_vector((N-1) downto 0);
augend: in std_logic_vector((N-1) downto 0);
carry_in: in std_logic;
sum: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end;
-- Tested with Modelsim 2015/12/11, works.
architecture struct_adderN of adderN is
component adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end component;
signal carry: std_logic_vector(N downto 0);
begin
carry(0) <= carry_in;
u1: for i in 0 to (N-1) generate
u: adder port map(
addend => addend(i),
augend => augend(i),
carry_in => carry(i),
sum => sum(i),
carry_out => carry(i+1)
);
end generate;
carry_out <= carry(N);
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity adder8x2 is
port(
addend, augend: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
sum: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
-- The adderN version is not used because access to carry out of bit 3 is required.
architecture struct_adder8x2 of adder8x2 is
component adder is
port(
addend, augend: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end component;
signal result: std_logic_vector(7 downto 0);
signal carry: std_logic_vector(8 downto 0);
begin
carry(0) <= carry_in;
u1: for i in 0 to 7 generate
u: adder port map(
addend => addend(i),
augend => augend(i),
carry_in => carry(i),
sum => result(i),
carry_out => carry(i+1)
);
end generate;
sum <= result;
flags_out <= ( sign_bit => result(7),
zero_bit => not (result(7) or result(6) or result(5) or result(4) or
result(3) or result(2) or result(1) or result(0)),
half_carry_bit => carry(4),
parity_overflow_bit => not (addend(7) xor augend(7)) and
(addend(7) xor result(7)),
add_sub_bit => '0',
carry_bit => carry(8),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity cpl is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_cpl of cpl is
begin
output <= not operand;
flags_out <= ( half_carry_bit => '1',
add_sub_bit => '1',
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rlc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rlc8bit of rlc8bit is
signal rlc_result: std_logic_vector(7 downto 0);
begin
rlc_result(7 downto 1) <= operand(6 downto 0);
rlc_result(0) <= operand(7);
output <= rlc_result;
flags_out <= ( carry_bit => operand(7),
parity_overflow_bit => not (rlc_result(7) xor rlc_result(6) xor rlc_result(5) xor
rlc_result(4) xor rlc_result(3) xor rlc_result(2) xor
rlc_result(1) xor rlc_result(0)),
zero_bit => not (rlc_result(7) or rlc_result(6) or rlc_result(5) or rlc_result(4) or
rlc_result(3) or rlc_result(2) or rlc_result(1) or rlc_result(0)),
sign_bit => rlc_result(7),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rrc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rrc8bit of rrc8bit is
signal rrc_result: std_logic_vector(7 downto 0);
begin
rrc_result(6 downto 0) <= operand(7 downto 1);
rrc_result(7) <= operand(0);
output <= rrc_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (rrc_result(7) or rrc_result(6) or rrc_result(5) or rrc_result(4) or
rrc_result(3) or rrc_result(2) or rrc_result(1) or rrc_result(0)),
parity_overflow_bit => not (rrc_result(7) xor rrc_result(6) xor rrc_result(5) xor
rrc_result(4) xor rrc_result(3) xor rrc_result(2) xor
rrc_result(1) xor rrc_result(0)),
sign_bit => operand(0),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rl8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rl8bit of rl8bit is
signal rl_result: std_logic_vector(7 downto 0);
begin
rl_result (7 downto 1) <= operand(6 downto 0);
rl_result(0) <= carry_in;
output <= rl_result;
flags_out <= ( carry_bit => operand(7),
zero_bit => not (rl_result(7) or rl_result(6) or rl_result(5) or rl_result(4) or
rl_result(3) or rl_result(2) or rl_result(1) or rl_result(0)),
parity_overflow_bit => not ((rl_result(7) xor rl_result(6) xor rl_result(5) xor
rl_result(4) xor rl_result(3) xor rl_result(2) xor
rl_result(1) xor rl_result(0))),
sign_bit => operand(6),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rr8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rr8bit of rr8bit is
signal rr_result: std_logic_vector(7 downto 0);
begin
rr_result(6 downto 0) <= operand(7 downto 1);
rr_result(7) <= carry_in;
output <= rr_result;
flags_out <= ( carry_bit => operand(0),
zero_bit => not (rr_result(7) or rr_result(6) or rr_result(5) or rr_result(4) or
rr_result(3) or rr_result(2) or rr_result(1) or rr_result(0)),
parity_overflow_bit => not (rr_result(7) xor rr_result(6) xor rr_result(5) xor
rr_result(4) xor rr_result(3) xor rr_result(2) xor
rr_result(1) xor rr_result(0)),
sign_bit => carry_in,
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
entity daa is
port(
operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Untested, this is nothing more than a stub with code to prevent unassigned variable warnings/errors.
architecture struct_daa of daa is
begin
output <= operand;
flags_out <= flags_in;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity bit_op is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_bit_op of bit_op is
signal zero: std_logic;
begin
zero <= '1' when (operand1 and operand2) = x"00" else '0';
flags_out <= ( zero_bit => zero,
half_carry_bit => '1',
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rld is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rld of rld is
signal primary_result: std_logic_vector(7 downto 0);
begin
primary_result(7 downto 4) <= primary_op(7 downto 4);
primary_result(3 downto 0) <= secondary_op(7 downto 4);
result <= primary_result;
secondary_result(7 downto 4) <= secondary_op(3 downto 0);
secondary_result(3 downto 0) <= primary_op(3 downto 0);
flags_out <= ( sign_bit => primary_result(7),
zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
primary_result(4) or primary_result(3) or primary_result(2) or
primary_result(1) or primary_result(0)),
parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
primary_result(5) xor primary_result(4) xor
primary_result(3) xor primary_result(2) xor
primary_result(1) xor primary_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity rrd is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_rrd of rrd is
signal primary_result: std_logic_vector(7 downto 0);
begin
primary_result(7 downto 4) <= primary_op(7 downto 4);
primary_result(3 downto 0) <= secondary_op(3 downto 0);
result <= primary_result;
secondary_result(7 downto 4) <= primary_op(3 downto 0);
secondary_result(3 downto 0) <= secondary_op(7 downto 4);
flags_out <= ( sign_bit => primary_result(7),
zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
primary_result(4) or primary_result(3) or primary_result(2) or
primary_result(1) or primary_result(0)),
parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
primary_result(5) xor primary_result(4) xor
primary_result(3) xor primary_result(2) xor
primary_result(1) xor primary_result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity in_rc_flags is
port(
operand: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_in_rc_flags of in_rc_flags is
begin
flags_out <= ( zero_bit => not (operand(7) or operand(6) or operand(5) or operand(4) or
operand(3) or operand(2) or operand(1) or operand(0)),
sign_bit => operand(7),
parity_overflow_bit => not (operand(7) xor operand(6) xor operand(5) xor
operand(4) xor operand(3) xor operand(2) xor
operand(1) xor operand(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity bmtc is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested with Modelsim 2015/11/25, works.
architecture struct_bmtc of bmtc is
signal result: std_logic_vector(7 downto 0);
begin
result <= operand1 or operand2;
output <= result;
flags_out <= ( parity_overflow_bit => not (result(7) or result(6) or result(5) or result(4) or
result(3) or result(2) or result(1) or result(0)),
others => '0');
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.definitions.all;
entity alu is
port(
-- control
operation: in std_logic_vector(4 downto 0);
-- operands
primary_operand: in std_logic_vector(7 downto 0);
secondary_operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
-- results
output, flags_out: out std_logic_vector(7 downto 0);
secondary_out: out std_logic_vector(7 downto 0)
);
end;
-- Tested 2016/11/22, works on Modelsim simulator along with all components.
architecture struct_alu of alu is
component bmtc is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component srl8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sll8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sra8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component sla8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component in_rc_flags is
port(
operand: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component ccf_operation is
port(
flags_in: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component cpl is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component xor8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component or8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component and8bit is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component subtractor8x2 is
port(
minuend, subtrahend: in std_logic_vector(7 downto 0);
borrow_in: in std_logic;
difference: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component adder8x2 is
port(
addend, augend: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
sum: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component magnitudeN is
generic(
N: positive
);
port(
a: in std_logic_vector((N-1) downto 0);
b: in std_logic_vector((N-1) downto 0);
equal: out std_logic;
lt: out std_logic; -- '1' if a < b
gt: out std_logic -- '1' if a > b
);
end component;
component rrd is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rld is
port(
primary_op: in std_logic_vector(7 downto 0);
secondary_op: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
secondary_result: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rlc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rl8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rrc8bit is
port(
operand: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component rr8bit is
port(
operand: in std_logic_vector(7 downto 0);
carry_in: in std_logic;
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component daa is
port(
operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component bit_op is
port(
operand1: in std_logic_vector(7 downto 0);
operand2: in std_logic_vector(7 downto 0);
flags_out: out std_logic_vector(7 downto 0)
);
end component;
component encoder32xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
data8: in std_logic_vector((N-1) downto 0);
data9: in std_logic_vector((N-1) downto 0);
data10: in std_logic_vector((N-1) downto 0);
data11: in std_logic_vector((N-1) downto 0);
data12: in std_logic_vector((N-1) downto 0);
data13: in std_logic_vector((N-1) downto 0);
data14: in std_logic_vector((N-1) downto 0);
data15: in std_logic_vector((N-1) downto 0);
data16: in std_logic_vector((N-1) downto 0);
data17: in std_logic_vector((N-1) downto 0);
data18: in std_logic_vector((N-1) downto 0);
data19: in std_logic_vector((N-1) downto 0);
data20: in std_logic_vector((N-1) downto 0);
data21: in std_logic_vector((N-1) downto 0);
data22: in std_logic_vector((N-1) downto 0);
data23: in std_logic_vector((N-1) downto 0);
data24: in std_logic_vector((N-1) downto 0);
data25: in std_logic_vector((N-1) downto 0);
data26: in std_logic_vector((N-1) downto 0);
data27: in std_logic_vector((N-1) downto 0);
data28: in std_logic_vector((N-1) downto 0);
data29: in std_logic_vector((N-1) downto 0);
data30: in std_logic_vector((N-1) downto 0);
data31: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(4 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end component;
component encoder2xN_oe is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
selector: in std_logic;
enable: in std_logic;
output: out std_logic_vector((N-1) downto 0)
);
end component;
signal add_result: std_logic_vector(7 downto 0);
signal add_carry_in: std_logic;
signal add_flags: std_logic_vector(7 downto 0);
signal and_result: std_logic_vector(7 downto 0);
signal and_flags: std_logic_vector(7 downto 0);
signal or_result: std_logic_vector(7 downto 0);
signal or_flags: std_logic_vector(7 downto 0);
signal xor_result: std_logic_vector(7 downto 0);
signal xor_flags: std_logic_vector(7 downto 0);
signal cpl_result: std_logic_vector(7 downto 0);
signal cpl_flags: std_logic_vector(7 downto 0);
signal subtract_result: std_logic_vector(7 downto 0);
signal subtract_borrow_in: std_logic;
signal subtract_flags: std_logic_vector(7 downto 0);
signal rlc_result: std_logic_vector(7 downto 0);
signal rlc_flags: std_logic_vector(7 downto 0);
signal rrc_result: std_logic_vector(7 downto 0);
signal rrc_flags: std_logic_vector(7 downto 0);
signal rl_result: std_logic_vector(7 downto 0);
signal rl_flags: std_logic_vector(7 downto 0);
signal rr_result: std_logic_vector(7 downto 0);
signal rr_flags: std_logic_vector(7 downto 0);
signal daa_result: std_logic_vector(7 downto 0);
signal daa_flags: std_logic_vector(7 downto 0);
signal scf_flags: std_logic_vector(7 downto 0);
signal ccf_carry: std_logic;
signal ccf_flags: std_logic_vector(7 downto 0);
signal bit_zero: std_logic;
signal bit_flags: std_logic_vector(7 downto 0);
signal in_flags: std_logic_vector(7 downto 0); -- flags for IN r, C instruction
signal secondary_out_enable: std_logic; -- '1' when executing a rrd/rld
-- instruction
signal rld_result: std_logic_vector(7 downto 0);
signal secondary_rld_result: std_logic_vector(7 downto 0);
signal rld_flags: std_logic_vector(7 downto 0);
signal is_rld: std_logic;
signal rrd_result: std_logic_vector(7 downto 0);
signal secondary_rrd_result: std_logic_vector(7 downto 0);
signal rrd_flags: std_logic_vector(7 downto 0);
signal is_rrd: std_logic;
signal sla_result: std_logic_vector(7 downto 0);
signal sla_flags: std_logic_vector(7 downto 0);
signal sra_result: std_logic_vector(7 downto 0);
signal sra_flags: std_logic_vector(7 downto 0);
signal sll_result: std_logic_vector(7 downto 0);
signal sll_flags: std_logic_vector(7 downto 0);
signal srl_result: std_logic_vector(7 downto 0);
signal srl_flags: std_logic_vector(7 downto 0);
signal bmtc_result: std_logic_vector(7 downto 0);
signal bmtc_flags: std_logic_vector(7 downto 0); -- block move termination criterion
-- flags
begin
-- result multiplexer, 32x8
u1: encoder32xN
generic map(
N => 8
)
port map(
data0 => add_result, -- add, ignore carry bit
data1 => add_result, -- add, add carry bit
data2 => subtract_result, -- sub, ignore borrow bit
data3 => subtract_result, -- sub, subtract borrow bit
data4 => and_result, -- and
data5 => xor_result, -- xor
data6 => or_result, -- or
data7 => subtract_result, -- compare (no-borrow sub with result
-- discarded, used to set flags)
data8 => rlc_result, -- RLC
data9 => rrc_result, -- RRC
data10 => rl_result, -- RL
data11 => rr_result, -- RR
data12 => daa_result, -- DAA
data13 => cpl_result, -- CPL
data14 => primary_operand, -- SCF
data15 => primary_operand, -- CCF
data16 => sla_result, -- SLA
data17 => sra_result, -- SRA
data18 => sll_result, -- SLL
data19 => srl_result, -- SRL
data20 => secondary_operand, -- BIT
data21 => and_result, -- RES
data22 => or_result, -- SET
data23 => primary_operand, -- IN r, (C)
data24 => rld_result, -- RLD
data25 => rrd_result, -- RRD
data26 => bmtc_result, -- block move termination criterion
data27 => (others => '0'), -- reserved
data28 => (others => '0'), -- reserved
data29 => (others => '0'), -- reserved
data30 => (others => '0'), -- reserved
data31 => (others => '0'), -- reserved
address => operation,
output => output
);
-- result flags multiplexer
u2: encoder32xN
generic map(
N => 8
)
port map(
data0 => add_flags, -- add
data1 => add_flags, -- adc
data2 => subtract_flags, -- sub
data3 => subtract_flags, -- sbc
data4 => and_flags, -- and
data5 => xor_flags, -- xor
data6 => or_flags, -- or
data7 => subtract_flags, -- cmp
data8 => rlc_flags, -- rlc
data9 => rrc_flags, -- rrc
data10 => rl_flags, -- rl
data11 => rr_flags, -- rr
data12 => daa_flags, -- daa
data13 => cpl_flags, -- cpl
data14 => scf_flags, -- scf
data15 => ccf_flags, -- ccf
data16 => sla_flags, -- SLA
data17 => sra_flags, -- SRA
data18 => sll_flags, -- SLL
data19 => srl_flags, -- SRL
data20 => bit_flags, -- BIT
data21 => (others => '0'), -- RES, no flags affected
data22 => (others => '0'), -- SET, no flags affected
data23 => in_flags, -- IN r, (C)
data24 => rld_flags, -- RLD
data25 => rrd_flags, -- RRD
data26 => bmtc_flags, -- block move termination criterion
data27 => (others => '0'), -- reserved
data28 => (others => '0'), -- reserved
data29 => (others => '0'), -- reserved
data30 => (others => '0'), -- reserved
data31 => (others => '0'), -- reserved
address => operation,
output => flags_out
);
scf_flags <= (carry_bit => '1', others => '0');
-- adder: This version gets flagged by ModelSim on the carry_in line as an error. Only signals or
-- maybe variables are allowed. Expressions are not.
-- u3: adder8x2 port map(
-- addend => primary_operand,
-- augend => secondary_operand,
-- carry_in => (flags_in(carry_bit) and operation(0)), -- carry only with adc opcode, others
-- -- made irrelevant by result mux
-- sum => add_result,
-- carry_out => carry_out,
-- overflow => add_overflow,
-- interdigit_carry => interdigit_carry,
-- zero => add_zero
-- );
-- adder
u3: adder8x2 port map(
addend => primary_operand,
augend => secondary_operand,
carry_in => add_carry_in,
sum => add_result,
flags_out => add_flags
);
add_carry_in <= flags_in(carry_bit) and operation(0); -- carry only with adc opcode, others made
-- irrelevant by result mux
-- subtractor
u4: subtractor8x2 port map(
minuend => primary_operand,
subtrahend => secondary_operand,
borrow_in => subtract_borrow_in,
difference => subtract_result,
flags_out => subtract_flags
);
-- borrow only with sbc opcode, must remove compare opcode (operation(2 downto 0) = "111"), others
-- made irrelevant by result mux
subtract_borrow_in <= flags_in(carry_bit) and (not operation(2)) and operation(1) and operation(0);
-- bitwise and operation
u5: and8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => and_result,
flags_out => and_flags
);
-- bitwise exclusive-or operation
u6: xor8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => xor_result,
flags_out => xor_flags
);
-- bitwise or operation
u7: or8bit port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => or_result,
flags_out => or_flags
);
-- RLC generator
u8: rlc8bit port map(
operand => primary_operand,
output => rlc_result,
flags_out => rlc_flags
);
-- RRC generator
u9: rrc8bit port map(
operand => primary_operand,
output => rrc_result,
flags_out => rrc_flags
);
-- RL generator
u10: rl8bit port map(
operand => primary_operand,
carry_in => flags_in(carry_bit),
output => rl_result,
flags_out => rl_flags
);
-- RR generator
u11: rr8bit port map(
operand => primary_operand,
carry_in => flags_in(carry_bit),
output => rr_result,
flags_out => rr_flags
);
-- DAA
u12: daa port map(
operand => primary_operand,
flags_in => flags_in,
output => daa_result,
flags_out => daa_flags
);
-- bit testing of secondary operand against mask in primary operand
u13: bit_op port map(
operand1 => primary_operand,
operand2 => secondary_operand,
flags_out => bit_flags
);
u14: rld port map(
primary_op => primary_operand,
secondary_op => secondary_operand,
result => rld_result,
secondary_result => secondary_rld_result,
flags_out => rld_flags
);
u15: magnitudeN
generic map(
N => 5
)
port map(
a => operation,
b => rrd_operation,
equal => is_rrd,
lt => open,
gt => open
);
u16: magnitudeN
generic map(
N => 5
)
port map(
a => operation,
b => rld_operation,
equal => is_rld,
lt => open,
gt => open
);
u17: rrd port map(
primary_op => primary_operand,
secondary_op => secondary_operand,
result => rrd_result,
secondary_result => secondary_rrd_result,
flags_out => rrd_flags
);
u18: encoder2xN_oe
generic map(
N => 8
)
port map(
data0 => secondary_rld_result,
data1 => secondary_rrd_result,
selector => is_rrd,
enable => secondary_out_enable,
output => secondary_out
);
secondary_out_enable <= is_rrd or is_rld;
u19: cpl port map(
operand => primary_operand,
output => cpl_result,
flags_out => cpl_flags
);
u20: ccf_operation port map(
flags_in => flags_in,
flags_out => ccf_flags
);
u21: in_rc_flags port map(
operand => primary_operand,
flags_out => in_flags
);
u22: sla8bit port map(
operand => primary_operand,
output => sla_result,
flags_out => sla_flags
);
u23: sra8bit port map(
operand => primary_operand,
output => sra_result,
flags_out => sra_flags
);
u24: sll8bit port map(
operand => primary_operand,
output => sll_result,
flags_out => sll_flags
);
u25: srl8bit port map(
operand => primary_operand,
output => srl_result,
flags_out => srl_flags
);
u26: bmtc port map(
operand1 => primary_operand,
operand2 => secondary_operand,
output => bmtc_result,
flags_out => bmtc_flags
);
end;
| gpl-2.0 | 283ad6188f44cb7260a60fcefad02072 | 0.654857 | 2.705063 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug019/PoC/src/io/uart/uart_tx.vhdl | 3 | 3,665 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: UART Transmitter
--
-- Description:
-- ------------------------------------
-- TODO
--
-- old comments:
-- Serial configuration: 8 data bits, 1 stop bit, no parity
--
-- bclk = bit clk is rising
-- stb = strobe, i.e. transmit byte @ din
-- rdy = ready
--
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.components.all;
entity uart_tx is
port (
clk : in std_logic;
rst : in std_logic;
bclk : in std_logic;
stb : in std_logic;
din : in std_logic_vector(7 downto 0);
rdy : out std_logic;
txd : out std_logic
);
end entity;
architecture rtl of uart_tx is
type states is (IDLE, TDATA);
signal state : states := IDLE;
signal next_state : states;
-- register
signal sr : std_logic_vector(9 downto 1) := (others => '0');
signal sr0 : std_logic := '1'; -- current bit to transmit
signal shift_cnt : unsigned(3 downto 0) := (others => '0');
signal shift_done : STD_LOGIC;
-- control signals
signal start_tx : std_logic;
signal shift_sr : std_logic;
begin
process (state, stb, bclk, shift_done)
begin
next_state <= state;
start_tx <= '0';
shift_sr <= '0';
case state is
when IDLE =>
if stb = '1' then
-- start_tx triggers register initialization
start_tx <= '1';
next_state <= TDATA;
end if;
when TDATA =>
if bclk = '1' then
-- also shift stop bit into sr0!
shift_sr <= '1';
if (shift_done = '1') then
-- condition is true at beginning of sending the stop-bit
-- synchronization to the bitclk ensures that stop-bit is
-- transmitted fully
next_state <= IDLE;
end if;
end if;
when others => null;
end case;
end process;
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
state <= IDLE;
else
state <= next_state;
end if;
if start_tx = '1' then
-- data, start bit
sr <= din & '0';
elsif shift_sr = '1' then
sr <= '1' & sr(sr'left downto sr'right+1);
end if;
if rst = '1' then
sr0 <= '1'; -- idle
elsif shift_sr = '1' then
sr0 <= sr(1);
end if;
end if;
end process;
shift_cnt <= upcounter_next(cnt => shift_cnt, rst => start_tx, en => shift_sr) when rising_edge(clk);
shift_done <= upcounter_equal(cnt => shift_cnt, value => 9);
-- outputs
txd <= sr0;
rdy <= '1' when state = IDLE else '0';
end;
| gpl-2.0 | 1ff24c31a6520cabbefb9ba6333fc413 | 0.561801 | 3.34093 | false | false | false | false |
nickg/nvc | test/regress/gensub2.vhd | 1 | 714 | entity gensub2 is
end entity;
architecture test of gensub2 is
function adder generic (type t;
function "+"(l, r : t) return t is <>;
n : t) (x : t) return t is
begin
return x + n;
end function;
function add1 is new adder generic map (t => integer, n => 1);
function add1 is new adder generic map (t => real, n => 1.0);
signal s : integer;
signal r : real;
begin
p1: process is
begin
assert add1(1) = 2;
assert add1(2.0) = 3.0;
s <= 5;
r <= 4.0;
wait for 1 ns;
assert add1(s) = 6;
assert add1(r) = 5.0;
wait;
end process;
end architecture;
| gpl-3.0 | 3da3d52c17a89d3ff1e608d3d9bb84b9 | 0.498599 | 3.58794 | false | false | false | false |
tgingold/ghdl | testsuite/synth/arr03/mdim01.vhdl | 1 | 718 | library ieee;
use ieee.std_logic_1164.all;
entity mdim01 is
port (a0, a1 : std_logic_vector (3 downto 0);
o0 : out std_logic_vector (3 downto 0));
end mdim01;
architecture behav of mdim01 is
type t_matrix is array (0 to 1, 3 downto 0) of boolean;
constant mat : t_matrix :=
(0 => (3 => true, 2 => true, 1 => false, 0 => false),
1 => (3 => true, 2 => false, 1 => true, 0 => false));
begin
process (a0, a1)
variable b : std_logic;
begin
for i in t_matrix'range(2) loop
if mat (0, i) then
b := a0 (i);
else
b := '0';
end if;
if mat (1, i) then
b := b xor a1 (i);
end if;
o0 (i) <= b;
end loop;
end process;
end behav;
| gpl-2.0 | fe28b391deff5e458588629339b82742 | 0.533426 | 2.906883 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm-b.vhd | 4 | 1,532 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_regm-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavior of reg_multiple_out is
begin
reg: process ( d, latch_en, out_en ) is
variable latched_value : dlx_word;
begin
if To_bit(latch_en) = '1' then
latched_value := To_X01(d);
end if;
for index in out_en'range loop
if To_bit(out_en(index)) = '1' then
q(index) <= latched_value after Tpd;
else
q(index) <= disabled_dlx_word after Tpd;
end if;
end loop;
end process reg;
end architecture behavior;
| gpl-2.0 | abea443940909b1c311880efed1ca9b4 | 0.609008 | 3.948454 | false | false | false | false |
tgingold/ghdl | testsuite/synth/arr01/arr11.vhdl | 1 | 696 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arr11 is
port (val : std_logic_vector(3 downto 0);
res : out natural);
end arr11;
architecture behav of arr11 is
function find (s : string; c : character) return natural is
begin
for i in s'range loop
if s (i) = c then
return i;
end if;
end loop;
return 0;
end find;
constant str1 : string := "hello world";
constant pos1 : natural := find (str1, 'w');
alias str2 : string (str1'length downto 1) is str1;
constant str3 : string := str2;
constant pos3 : natural := find (str3, 'w');
begin
assert pos1 = 7;
assert pos3 = 5;
res <= pos1;
end behav;
| gpl-2.0 | 101da6145879325ce8a53fee21e44f17 | 0.625 | 3.237209 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug043/sha256.vhd | 2 | 6,755 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use IEEE.std_logic_unsigned.all;
ENTITY sha256forBTC is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
--data input signals
data : in STD_LOGIC_VECTOR (511 downto 0);
enable : in STD_LOGIC;
busy : out STD_LOGIC;
--hash output signals
digest : out STD_LOGIC_VECTOR (255 downto 0);
ready : out STD_LOGIC);
end sha256forBTC;
ARCHITECTURE Behavioral of sha256forBTC is
type hT is array (0 to 7) of STD_LOGIC_VECTOR(31 downto 0);
constant hInit : hT :=
(x"6a09e667", x"bb67ae85", x"3c6ef372", x"a54ff53a", x"510e527f", x"9b05688c", x"1f83d9ab", x"5be0cd19");
type kT is array (0 to 63) of STD_LOGIC_VECTOR(31 downto 0);
constant k : kT :=
(x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2");
signal a,b,c,d,e,f,g,h,h0,h1,h2,h3,h4,h5,h6,h7,s0,s1,su0,su1,maj,ch,temp1,temp2 : STD_LOGIC_VECTOR(31 downto 0);
type wT is array (15 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
signal w : wT;
signal wCNT, chunkCNT : STD_LOGIC_VECTOR(6 downto 0);
signal intEnable : STD_LOGIC;
BEGIN
fsm: process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
chunkCNT <= "1000000";
else
if chunkCNT = "1000000" then
if enable = '1' then
chunkCNT <= "0000000";
end if;
else
chunkCNT <= std_logic_vector(unsigned(chunkCNT) + 1);
end if;
end if;
ready <= not intEnable;
end if;
end process;
intEnable <= not chunkCNT(6);
busy <= intEnable;
extension_pipe: process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
w(0) <= data(31 downto 0);
w(1) <= data(63 downto 32);
w(2) <= data(95 downto 64);
w(3) <= data(127 downto 96);
w(4) <= data(159 downto 128);
w(5) <= data(191 downto 160);
w(6) <= data(223 downto 192);
w(7) <= data(255 downto 224);
w(8) <= data(287 downto 256);
w(9) <= data(319 downto 288);
w(10) <= data(351 downto 320);
w(11) <= data(383 downto 352);
w(12) <= data(415 downto 384);
w(13) <= data(447 downto 416);
w(14) <= data(479 downto 448);
w(15) <= data(511 downto 480);
elsif intEnable = '1' then
w <= w(14 downto 0) & std_logic_vector(unsigned(w(15)) + unsigned(s0) + unsigned(w(6)) + unsigned(s1));
end if;
end if;
end process;
--extension_pipe asynchron circuitry
s0 <= (w(14)(6 downto 0) & w(14)(31 downto 7)) xor (w(14)(17 downto 0) & w(14)(31 downto 18)) xor ("000" & w(14)(31 downto 3));
s1 <= (w(1)(16 downto 0) & w(1)(31 downto 17)) xor (w(1)(18 downto 0) & w(1)(31 downto 19)) xor ("0000000000" & w(1)(31 downto 10));
--end of extension_pipe asynchron circuitry
main_loop_pipe: process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
a <= hInit(0);
b <= hInit(1);
c <= hInit(2);
d <= hInit(3);
e <= hInit(4);
f <= hInit(5);
g <= hInit(6);
h <= hInit(7);
elsif intEnable = '0' then
a <= std_logic_vector(unsigned(h0) + unsigned(a));
b <= std_logic_vector(unsigned(h1) + unsigned(b));
c <= std_logic_vector(unsigned(h2) + unsigned(c));
d <= std_logic_vector(unsigned(h3) + unsigned(d));
e <= std_logic_vector(unsigned(h4) + unsigned(e));
f <= std_logic_vector(unsigned(h5) + unsigned(f));
g <= std_logic_vector(unsigned(h6) + unsigned(g));
h <= std_logic_vector(unsigned(h7) + unsigned(h));
else
h <= g;
g <= f;
f <= e;
e <= std_logic_vector(unsigned(d) + unsigned(temp1));
d <= c;
c <= b;
b <= a;
a <= temp2;
end if;
end if;
end process;
--main_loop_pipe asynchron circuitry
su1 <= (e(5 downto 0) & e(31 downto 6)) xor (e(10 downto 0) & e(31 downto 11)) xor (e(24 downto 0) & e(31 downto 25));
ch <= (e and f) xor ((not e) and g);
temp1 <= std_logic_vector(unsigned(h) +
unsigned(su1) +
unsigned(ch) +
unsigned(k(to_integer(unsigned(chunkCNT(5 downto 0))))) +
unsigned(w(15)));
su0 <= (a(1 downto 0) & a(31 downto 2)) xor (a(12 downto 0) & a(31 downto 13)) xor (a(21 downto 0) & a(31 downto 22));
maj <= (a and (b xor c)) xor (b and c);
temp2 <= std_logic_vector(unsigned(temp1) + unsigned(su0) + unsigned(maj));
--end of main_loop_pipe asynchron circuitry
add_hash_chunk: process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
h0 <= x"00000000";
h1 <= x"00000000";
h2 <= x"00000000";
h3 <= x"00000000";
h4 <= x"00000000";
h5 <= x"00000000";
h6 <= x"00000000";
h7 <= x"00000000";
else
if intEnable = '0' then
h0 <= std_logic_vector(unsigned(h0) + unsigned(a));
h1 <= std_logic_vector(unsigned(h1) + unsigned(b));
h2 <= std_logic_vector(unsigned(h2) + unsigned(c));
h3 <= std_logic_vector(unsigned(h3) + unsigned(d));
h4 <= std_logic_vector(unsigned(h4) + unsigned(e));
h5 <= std_logic_vector(unsigned(h5) + unsigned(f));
h6 <= std_logic_vector(unsigned(h6) + unsigned(g));
h7 <= std_logic_vector(unsigned(h7) + unsigned(h));
end if;
end if;
end if;
end process;
digest <= h0 & h1 & h2 & h3 & h4 & h5 & h6 & h7;
end Behavioral;
| gpl-2.0 | a10aad7e856e8946b4b769d4408e3001 | 0.533087 | 2.945922 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1063/matching.vhdl | 1 | 327 | library ieee;
use ieee.std_logic_1164.all;
entity matching is
end matching;
architecture behav of matching is
constant ceq11 : std_logic := '1' ?= '1';
constant ceq1h : std_logic := '1' ?= 'H';
constant ceq1w : std_logic := '1' ?= 'W';
begin
assert ceq11 = '1';
assert ceq1h = '1';
assert ceq1w = 'X';
end behav;
| gpl-2.0 | a283890119c9189b440cfb9c8be9d776 | 0.633028 | 2.725 | false | false | false | false |
nickg/nvc | test/regress/issue433.vhd | 1 | 934 | entity SAMPLE is
generic (NAME: string := ""; delay : delay_length);
end entity;
architecture MODEL of SAMPLE is
begin
process begin
wait for delay;
assert (FALSE) report NAME & ":OK" severity NOTE;
wait;
end process;
end MODEL;
entity SAMPLE_NG is
generic (NAME: string := ""; delay : delay_length);
end entity;
architecture MODEL of SAMPLE_NG is
component SAMPLE generic(NAME: STRING := ""; delay : delay_length); end component;
begin
U: SAMPLE generic map (NAME => NAME & "(" & ")", delay => delay);
end MODEL;
entity issue433 is
generic (NAME: string := "TEST_NG");
end entity;
architecture MODEL of issue433 is
component SAMPLE_NG generic(NAME: STRING := ""; delay : delay_length); end component;
begin
U1: SAMPLE_NG generic map(NAME => NAME & string'(":U1"), delay => 1 ns);
U2: SAMPLE_NG generic map(NAME => NAME & string'(":U2"), delay => 2 ns);
end MODEL;
| gpl-3.0 | 89614f0bbc6934af15b32920b628a1a4 | 0.646681 | 3.796748 | false | false | false | false |
nickg/nvc | test/regress/driver14.vhd | 1 | 618 | entity driver14 is
end entity;
architecture test of driver14 is
type rec is record
x, y : natural;
end record;
type rec_array is array (natural range <>) of rec;
function resolved (x : rec_array) return rec is
begin
return x(0); -- Returns pointer to its argument
end function;
subtype rrec is resolved rec;
signal s : rrec;
begin
p1: s <= (1, 2);
p2: s <= (3, 4);
p3: process is
begin
assert s = (0, 0);
wait for 0 ns;
assert s = (1, 2) or s = (3, 4);
wait;
end process;
end architecture;
| gpl-3.0 | 06aa9a2643503c9c45f950860a99cce7 | 0.545307 | 3.635294 | false | false | false | false |
nickg/nvc | test/simp/cfold.vhd | 1 | 3,491 | entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5);
constant a3 : int_array(1 to 9) := (8 => 24, others => 0);
constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5);
constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1);
begin
process is
variable b : boolean;
variable d : time;
begin
x <= c / 2;
y <= t'high;
y <= t'left;
b := t'right = 8;
b := (t'right - t'left) = 2;
b := t'high /= 2;
b := true and true;
b := true and false;
b := true or false;
b := true xor true;
b := not true;
b := not false;
b := true xnor false;
b := false nand false;
b := false nor true;
b := 7 > 5 and 6 < 2;
x <= a1(2);
x <= a2(1);
x <= a2(3);
x <= a3(8);
x <= a1'length;
x <= a4(2);
x <= a5(4);
x <= 2 ** 4;
d := -5 ns;
end process;
process is
begin
if true then
x <= 1;
end if;
if false then
x <= 5;
end if;
if false then
null;
else
x <= 5;
end if;
while false loop
null;
end loop;
if true then
x <= 1;
x <= 5;
null;
end if;
end process;
process is
variable r : real;
variable b : boolean;
begin
r := 1.0 + 0.0;
r := 1.5 * 4.0;
r := 2.0 / 2.0;
b := 4.6 > 1.2;
end process;
process
variable k : time;
begin
end process;
process
type int2_vec is array (66 to 67) of integer;
variable b : boolean;
begin
b := a1'length = 5;
b := a1'low(1) = 1;
b := a1'high(1) = 5;
b := a1'left = 1;
b := a1'right = 5;
b := int2_vec'length = 2;
b := int2_vec'low = 66;
end process;
process is
begin
case 1 is
when 1 => null;
when others => report "bang";
end case;
end process;
process is
variable r : real;
begin
r := 1.5 * 2;
r := 3 * 0.2;
r := 5.0 / 2;
r := 2.0 ** 4;
end process;
process is
constant one : bit := '1';
variable b : boolean;
begin
b := one = '1';
b := '0' /= one;
end process;
-- Billowitch tc3170
tc3170: process is
constant L : REAL := -10.0;
constant R : REAL := 10.0;
type RT1 is range L to R;
begin
assert ( RT1'right = RT1(R) ); -- Should be removed
end process;
bitvec: process is
constant x : bit_vector(1 to 3) := "101";
constant y : bit_vector(1 to 3) := "110";
constant z : bit_vector(3 downto 1) := "011";
variable b : boolean;
begin
b := (x and y) = "100";
b := (y and z) = "010";
b := (x or y) = "111";
b := not x = "010";
b := (x xor y) = "011";
b := (x xnor y) = "100";
b := (x nand y) = "011";
b := (x nor y) = "000";
end process;
end architecture;
| gpl-3.0 | c5b7070902db9ebb9a87ea666329e7ed | 0.421083 | 3.334288 | false | false | false | false |
nickg/nvc | lib/ieee/numeric_std-body.vhdl | 1 | 86,923 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number
-- : in vector form
-- : -- > SIGNED: represents a SIGNED number
-- : in vector form
-- : The base element type is type STD_ULOGIC.
-- : The element subtypes are the same subtype as STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library nvc;
use nvc.sim_pkg.ieee_warnings;
package body NUMERIC_STD is
-- null range array constants
constant NAU : UNSIGNED (0 downto 1) := (others => '0');
constant NAS : SIGNED (0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := not ieee_warnings;
-- =========================Local Subprograms =================================
function MAXIMUM (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAXIMUM;
function MINIMUM (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MINIMUM;
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNSIGNED; C : STD_LOGIC)
return UNSIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNSIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : SIGNED; C : STD_LOGIC)
return SIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(L_LEFT downto 0) is R;
variable RESULT : SIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
-----------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNSIGNED;
XQUOT, XREMAIN : out UNSIGNED) is
variable TEMP : UNSIGNED(NUM'length downto 0);
variable QUOT : UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1
downto 0);
alias DENOM : UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_STD.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_LOGIC_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)
return STD_LOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
-----------------Local Subprograms - Relational ops---------------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : SIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R : SIGNED) return BOOLEAN is
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNSIGNED)
return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- =========================Exported Functions ==========================
-- Id: A.1
function "abs" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := TO_01(XARG, 'X');
if (RESULT(RESULT'left) = 'X') then return RESULT;
end if;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
variable RESULT, XARG01 : SIGNED(ARG_LEFT downto 0);
variable CBIT : STD_LOGIC := '1';
begin
if ARG'length < 1 then return NAS;
end if;
XARG01 := TO_01(ARG, 'X');
if (XARG01(XARG01'left) = 'X') then return XARG01;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG01(I)) xor CBIT;
CBIT := CBIT and not(XARG01(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, R01, '0');
end function "+";
-- Id: A.4
function "+" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, R01, '0');
end function "+";
-- Id: A.5
function "+" (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.9R
function "-" (L : UNSIGNED; R : STD_ULOGIC)
return UNSIGNED
is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-" (L : STD_ULOGIC; R : UNSIGNED)
return UNSIGNED
is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10
function "-" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.10R
function "-" (L : SIGNED; R : STD_ULOGIC)
return SIGNED
is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-" (L : STD_ULOGIC; R : SIGNED)
return SIGNED
is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.11
function "-" (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNSIGNED(L_LEFT downto 0);
variable XR : UNSIGNED(R_LEFT downto 0);
variable RESULT : UNSIGNED((L'length+R'length-1) downto 0) :=
(others => '0');
variable ADVAL : UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : SIGNED(L_LEFT downto 0);
variable XR : SIGNED(R_LEFT downto 0);
variable RESULT : SIGNED((L_LEFT+R_LEFT+1) downto 0) :=
(others => '0');
variable ADVAL : SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := TO_01(L, 'X');
XR := TO_01(R, 'X');
if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNSIGNED(L_LEFT downto 0);
variable XR : UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return FQUOT;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : SIGNED(L_LEFT downto 0) is L;
alias XXR : SIGNED(R_LEFT downto 0) is R;
variable XL : SIGNED(L_LEFT downto 0);
variable XR : SIGNED(R_LEFT downto 0);
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return SIGNED(FQUOT);
end if;
if XL(XL'left) = '1' then
XNUM := UNSIGNED(-XL);
QNEG := true;
else
XNUM := UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNSIGNED(-XR);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNSIGNED; R : NATURAL)
return UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNSIGNED)
return UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNSIGNED(L_LEFT downto 0);
variable XR : UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : SIGNED(L_LEFT downto 0) is L;
alias XXR : SIGNED(R_LEFT downto 0) is R;
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XNUM := UNSIGNED(TO_01(XXL, 'X'));
XDENOM := UNSIGNED(TO_01(XXR, 'X'));
if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then
FREMAIN := (others => 'X');
return SIGNED(FREMAIN);
end if;
if XNUM(XNUM'left) = '1' then
XNUM := UNSIGNED(-SIGNED(XNUM));
RNEG := true;
else
XNUM := UNSIGNED(XNUM);
end if;
if XDENOM(XDENOM'left) = '1' then
XDENOM := UNSIGNED(-SIGNED(XDENOM));
else
XDENOM := UNSIGNED(XDENOM);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNSIGNED; R : NATURAL)
return UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := L rem XR;
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNSIGNED)
return UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := XL rem R;
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : SIGNED; R : INTEGER)
return SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : SIGNED)
return SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNSIGNED(L_LEFT downto 0);
variable XR : UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : SIGNED(L_LEFT downto 0) is L;
alias XXR : SIGNED(R_LEFT downto 0) is R;
variable XL : SIGNED(L_LEFT downto 0);
variable XR : SIGNED(R_LEFT downto 0);
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return SIGNED(FREMAIN);
end if;
if XL(XL'left) = '1' then
XNUM := UNSIGNED(-XL);
else
XNUM := UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNSIGNED(-XR);
RNEG := true;
else
XDENOM := UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNSIGNED; R : NATURAL)
return UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNSIGNED)
return UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : SIGNED; R : INTEGER)
return SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : SIGNED)
return SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function ">";
-- Id: C.5
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function ">";
-- Id: C.6
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function "<";
-- Id: C.11
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function "<";
-- Id: C.12
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.17
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "<=";
-- Id: C.18
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.23
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function ">=";
-- Id: C.24
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "=";
-- Id: C.29
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "=";
-- Id: C.30
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.35
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)));
end function "/=";
-- Id: C.36
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)));
end function "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XXARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable XARG : UNSIGNED(ARG_LEFT downto 0);
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(XXARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : SIGNED) return INTEGER is
variable XARG : SIGNED(ARG'length-1 downto 0);
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(ARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if XARG(XARG'left) = '0' then
return TO_INTEGER(UNSIGNED(XARG));
else
return (- (TO_INTEGER(UNSIGNED(- (XARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED is
variable RESULT : UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED is
variable RESULT : SIGNED(SIZE-1 downto 0);
variable B_VAL : STD_LOGIC := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL)
return SIGNED
is
alias INVEC : SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : SIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL)
return UNSIGNED
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNSIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(STD_ULOGIC_VECTOR(L) and
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(STD_ULOGIC_VECTOR(L) or
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(STD_ULOGIC_VECTOR(L) nor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(STD_ULOGIC_VECTOR(L) xor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- ============================================================================
-- support constants for STD_MATCH:
type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE : BOOLEAN_TABLE := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(false, false, false, false, false, false, false, false, true), -- | U |
(false, false, false, false, false, false, false, false, true), -- | X |
(false, false, true, false, false, false, true, false, true), -- | 0 |
(false, false, false, true, false, false, false, true, true), -- | 1 |
(false, false, false, false, false, false, false, false, true), -- | Z |
(false, false, false, false, false, false, false, false, true), -- | W |
(false, false, true, false, false, false, true, false, true), -- | L |
(false, false, false, true, false, false, false, true, true), -- | H |
(true, true, true, true, true, true, true, true, true) -- | - |
);
-- Id: M.1
function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is
begin
return MATCH_TABLE(L, R);
end function STD_MATCH;
-- Id: M.2
function STD_MATCH (L, R : UNSIGNED) return BOOLEAN is
alias LV : UNSIGNED(1 to L'length) is L;
alias RV : UNSIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.3
function STD_MATCH (L, R : SIGNED) return BOOLEAN is
alias LV : SIGNED(1 to L'length) is L;
alias RV : SIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.4
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN is
alias LV: STD_LOGIC_VECTOR(1 to L'LENGTH) is L;
alias RV: STD_LOGIC_VECTOR(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.5
function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L;
alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- ============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED is
variable RESULT: UNSIGNED(S'LENGTH-1 downto 0);
variable BAD_ELEMENT: BOOLEAN := FALSE;
alias XS: UNSIGNED(S'LENGTH-1 downto 0) is S;
begin
if (S'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAU"
severity WARNING;
return NAU;
end if;
for I in RESULT'RANGE loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := TRUE;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'RANGE loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
-- Id: T.2
function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED is
variable RESULT: SIGNED(S'LENGTH-1 downto 0);
variable BAD_ELEMENT: BOOLEAN := FALSE;
alias XS: SIGNED(S'LENGTH-1 downto 0) is S;
begin
if (S'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAS"
severity WARNING;
return NAS;
end if;
for I in RESULT'RANGE loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := TRUE;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'RANGE loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
end package body NUMERIC_STD;
| gpl-3.0 | f9a704868278054bed04114e1958bae0 | 0.563464 | 3.646405 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_doImgProc_0_2/sim/design_1_doImgProc_0_2.vhd | 1 | 17,986 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls_video:doImgProc:1.0
-- IP Revision: 1606211642
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doImgProc_0_2 IS
PORT (
s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CRTL_BUS_WVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_BREADY : IN STD_LOGIC;
s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_RREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END design_1_doImgProc_0_2;
ARCHITECTURE design_1_doImgProc_0_2_arch OF design_1_doImgProc_0_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doImgProc_0_2_arch: ARCHITECTURE IS "yes";
COMPONENT doImgProc IS
GENERIC (
C_S_AXI_CRTL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CRTL_BUS_DATA_WIDTH : INTEGER;
C_S_AXI_KERNEL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_KERNEL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CRTL_BUS_WVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_BREADY : IN STD_LOGIC;
s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_RREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT doImgProc;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TID";
BEGIN
U0 : doImgProc
GENERIC MAP (
C_S_AXI_CRTL_BUS_ADDR_WIDTH => 5,
C_S_AXI_CRTL_BUS_DATA_WIDTH => 32,
C_S_AXI_KERNEL_BUS_ADDR_WIDTH => 5,
C_S_AXI_KERNEL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CRTL_BUS_AWADDR => s_axi_CRTL_BUS_AWADDR,
s_axi_CRTL_BUS_AWVALID => s_axi_CRTL_BUS_AWVALID,
s_axi_CRTL_BUS_AWREADY => s_axi_CRTL_BUS_AWREADY,
s_axi_CRTL_BUS_WDATA => s_axi_CRTL_BUS_WDATA,
s_axi_CRTL_BUS_WSTRB => s_axi_CRTL_BUS_WSTRB,
s_axi_CRTL_BUS_WVALID => s_axi_CRTL_BUS_WVALID,
s_axi_CRTL_BUS_WREADY => s_axi_CRTL_BUS_WREADY,
s_axi_CRTL_BUS_BRESP => s_axi_CRTL_BUS_BRESP,
s_axi_CRTL_BUS_BVALID => s_axi_CRTL_BUS_BVALID,
s_axi_CRTL_BUS_BREADY => s_axi_CRTL_BUS_BREADY,
s_axi_CRTL_BUS_ARADDR => s_axi_CRTL_BUS_ARADDR,
s_axi_CRTL_BUS_ARVALID => s_axi_CRTL_BUS_ARVALID,
s_axi_CRTL_BUS_ARREADY => s_axi_CRTL_BUS_ARREADY,
s_axi_CRTL_BUS_RDATA => s_axi_CRTL_BUS_RDATA,
s_axi_CRTL_BUS_RRESP => s_axi_CRTL_BUS_RRESP,
s_axi_CRTL_BUS_RVALID => s_axi_CRTL_BUS_RVALID,
s_axi_CRTL_BUS_RREADY => s_axi_CRTL_BUS_RREADY,
s_axi_KERNEL_BUS_AWADDR => s_axi_KERNEL_BUS_AWADDR,
s_axi_KERNEL_BUS_AWVALID => s_axi_KERNEL_BUS_AWVALID,
s_axi_KERNEL_BUS_AWREADY => s_axi_KERNEL_BUS_AWREADY,
s_axi_KERNEL_BUS_WDATA => s_axi_KERNEL_BUS_WDATA,
s_axi_KERNEL_BUS_WSTRB => s_axi_KERNEL_BUS_WSTRB,
s_axi_KERNEL_BUS_WVALID => s_axi_KERNEL_BUS_WVALID,
s_axi_KERNEL_BUS_WREADY => s_axi_KERNEL_BUS_WREADY,
s_axi_KERNEL_BUS_BRESP => s_axi_KERNEL_BUS_BRESP,
s_axi_KERNEL_BUS_BVALID => s_axi_KERNEL_BUS_BVALID,
s_axi_KERNEL_BUS_BREADY => s_axi_KERNEL_BUS_BREADY,
s_axi_KERNEL_BUS_ARADDR => s_axi_KERNEL_BUS_ARADDR,
s_axi_KERNEL_BUS_ARVALID => s_axi_KERNEL_BUS_ARVALID,
s_axi_KERNEL_BUS_ARREADY => s_axi_KERNEL_BUS_ARREADY,
s_axi_KERNEL_BUS_RDATA => s_axi_KERNEL_BUS_RDATA,
s_axi_KERNEL_BUS_RRESP => s_axi_KERNEL_BUS_RRESP,
s_axi_KERNEL_BUS_RVALID => s_axi_KERNEL_BUS_RVALID,
s_axi_KERNEL_BUS_RREADY => s_axi_KERNEL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
outStream_TVALID => outStream_TVALID,
outStream_TREADY => outStream_TREADY,
outStream_TDATA => outStream_TDATA,
outStream_TDEST => outStream_TDEST,
outStream_TKEEP => outStream_TKEEP,
outStream_TSTRB => outStream_TSTRB,
outStream_TUSER => outStream_TUSER,
outStream_TLAST => outStream_TLAST,
outStream_TID => outStream_TID
);
END design_1_doImgProc_0_2_arch;
| gpl-3.0 | c8f6d5bf45d5837023b1090ff7977c5b | 0.709274 | 3.22272 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/numeric_std-body.vhdl | 1 | 139,714 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number
-- : in vector form
-- : -- > UNRESOLVED_SIGNED: represents a SIGNED number
-- : in vector form
-- : The base element type is type STD_ULOGIC.
-- : Aliases U_UNSIGNED and U_SIGNED are defined for the types
-- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively.
-- : Two numeric subtypes are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The element subtypes are the same subtype as STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body NUMERIC_STD is
-- null range array constants
constant NAU : UNRESOLVED_UNSIGNED (0 downto 1) := (others => '0');
constant NAS : UNRESOLVED_SIGNED (0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
-- =========================Local Subprograms =================================
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------
-- this internal function computes the addition of two UNRESOLVED_UNSIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNRESOLVED_UNSIGNED; C : STD_LOGIC)
return UNRESOLVED_UNSIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two UNRESOLVED_SIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : UNRESOLVED_SIGNED; C : STD_LOGIC)
return UNRESOLVED_SIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(L_LEFT downto 0) is R;
variable RESULT : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
-----------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNRESOLVED_UNSIGNED;
XQUOT, XREMAIN : out UNRESOLVED_UNSIGNED) is
variable TEMP : UNRESOLVED_UNSIGNED(NUM'length downto 0);
variable QUOT : UNRESOLVED_UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1
downto 0);
alias DENOM : UNRESOLVED_UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_STD.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
-----------------Local Subprograms - Relational ops---------------------------
--
-- General "=" for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_LESS (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1);
variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_UNSIGNED)
return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1);
variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- =========================Exported Functions ==========================
-- Id: A.1
function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNRESOLVED_SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := TO_01(XARG, 'X');
if (RESULT(RESULT'left) = 'X') then return RESULT;
end if;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
variable RESULT, XARG01 : UNRESOLVED_SIGNED(ARG_LEFT downto 0);
variable CBIT : STD_LOGIC := '1';
begin
if ARG'length < 1 then return NAS;
end if;
XARG01 := TO_01(ARG, 'X');
if (XARG01(XARG01'left) = 'X') then return XARG01;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG01(I)) xor CBIT;
CBIT := CBIT and not(XARG01(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, R01, '0');
end function "+";
-- Id: A.3R
function "+" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED
is
variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4
function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, R01, '0');
end function "+";
-- Id: A.4R
function "+" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED
is
variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.5
function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.9R
function "-" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED
is
variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10
function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.10R
function "-" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED
is
variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.11
function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable RESULT : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0) :=
(others => '0');
variable ADVAL : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable RESULT : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0) :=
(others => '0');
variable ADVAL : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := TO_01(L, 'X');
XR := TO_01(R, 'X');
if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return FQUOT;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return UNRESOLVED_SIGNED(FQUOT);
end if;
if XL(XL'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-XL);
QNEG := true;
else
XNUM := UNRESOLVED_UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-XR);
QNEG := not QNEG;
else
XDENOM := UNRESOLVED_UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return UNRESOLVED_SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XNUM := UNRESOLVED_UNSIGNED(TO_01(XXL, 'X'));
XDENOM := UNRESOLVED_UNSIGNED(TO_01(XXR, 'X'));
if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then
FREMAIN := (others => 'X');
return UNRESOLVED_SIGNED(FREMAIN);
end if;
if XNUM(XNUM'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XNUM));
RNEG := true;
else
XNUM := UNRESOLVED_UNSIGNED(XNUM);
end if;
if XDENOM(XDENOM'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XDENOM));
else
XDENOM := UNRESOLVED_UNSIGNED(XDENOM);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return UNRESOLVED_SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := L rem XR;
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := XL rem R;
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return UNRESOLVED_SIGNED(FREMAIN);
end if;
if XL(XL'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-XL);
else
XNUM := UNRESOLVED_UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-XR);
RNEG := true;
else
XDENOM := UNRESOLVED_UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return UNRESOLVED_SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: A.39
function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.40
function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- Id: A.42
function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function ">";
-- Id: C.5
function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function ">";
-- Id: C.6
function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function "<";
-- Id: C.11
function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function "<";
-- Id: C.12
function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.17
function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "<=";
-- Id: C.18
function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.23
function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function ">=";
-- Id: C.24
function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "=";
-- Id: C.29
function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "=";
-- Id: C.30
function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.35
function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)));
end function "/=";
-- Id: C.36
function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)));
end function "/=";
-- ============================================================================
-- Id: C.37
function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if UNSIGNED_LESS(L01, R01) then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.38
function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if SIGNED_LESS(L01, R01) then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- ============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if UNSIGNED_LESS(L01, R01) then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- Id: C.44
function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if SIGNED_LESS(L01, R01) then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
-- ============================================================================
-- Id: C.49
function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
-- Id: C.50
function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
-- Id: C.51
function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?> R;
end function "?>";
-- Id: C.52
function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?> R;
end function "?>";
-- Id: C.53
function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?> TO_UNSIGNED(R, L'length);
end function "?>";
-- Id: C.54
function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?> TO_SIGNED(R, L'length);
end function "?>";
-- ============================================================================
-- Id: C.55
function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
-- Id: C.56
function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
-- Id: C.57
function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?< R;
end function "?<";
-- Id: C.58
function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?< R;
end function "?<";
-- Id: C.59
function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?< TO_UNSIGNED(R, L'length);
end function "?<";
-- Id: C.60
function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?< TO_SIGNED(R, L'length);
end function "?<";
-- ============================================================================
-- Id: C.61
function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
-- Id: C.62
function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
-- Id: C.63
function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?<= R;
end function "?<=";
-- Id: C.64
function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?<= R;
end function "?<=";
-- Id: C.65
function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?<= TO_UNSIGNED(R, L'length);
end function "?<=";
-- Id: C.66
function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?<= TO_SIGNED(R, L'length);
end function "?<=";
-- ============================================================================
-- Id: C.67
function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
-- Id: C.68
function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
-- Id: C.69
function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?>= R;
end function "?>=";
-- Id: C.70
function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?>= R;
end function "?>=";
-- Id: C.71
function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?>= TO_UNSIGNED(R, L'length);
end function "?>=";
-- Id: C.72
function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?>= TO_SIGNED(R, L'length);
end function "?>=";
-- ============================================================================
-- Id: C.73
function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := LX(i) ?= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function "?=";
-- Id: C.74
function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := LX(i) ?= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function "?=";
-- Id: C.75
function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?= R;
end function "?=";
-- Id: C.76
function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?= R;
end function "?=";
-- Id: C.77
function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?= TO_UNSIGNED(R, L'length);
end function "?=";
-- Id: C.78
function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?= TO_SIGNED(R, L'length);
end function "?=";
-- ============================================================================
-- Id: C.79
function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := LX(i) ?/= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function "?/=";
-- Id: C.80
function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := LX(i) ?/= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function "?/=";
-- Id: C.81
function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?/= R;
end function "?/=";
-- Id: C.82
function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?/= R;
end function "?/=";
-- Id: C.83
function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?/= TO_UNSIGNED(R, L'length);
end function "?/=";
-- Id: C.84
function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?/= TO_SIGNED(R, L'length);
end function "?/=";
-- ============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XSRL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XSRA(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- ============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XXARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0);
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(XXARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER is
variable XARG : UNRESOLVED_SIGNED(ARG'length-1 downto 0);
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(ARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if XARG(XARG'left) = '0' then
return TO_INTEGER(UNRESOLVED_UNSIGNED(XARG));
else
return (- (TO_INTEGER(UNRESOLVED_UNSIGNED(- (XARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable B_VAL : STD_LOGIC := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL)
return UNRESOLVED_SIGNED
is
alias INVEC : UNRESOLVED_SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) and
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) or
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.15
function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L and STD_ULOGIC_VECTOR(R));
end function "and";
-- Id: L.16
function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) and R);
end function "and";
-- Id: L.17
function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L or STD_ULOGIC_VECTOR(R));
end function "or";
-- Id: L.18
function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) or R);
end function "or";
-- Id: L.19
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L nand STD_ULOGIC_VECTOR(R));
end function "nand";
-- Id: L.20
function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nand R);
end function "nand";
-- Id: L.21
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L nor STD_ULOGIC_VECTOR(R));
end function "nor";
-- Id: L.22
function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nor R);
end function "nor";
-- Id: L.23
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L xor STD_ULOGIC_VECTOR(R));
end function "xor";
-- Id: L.24
function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L xnor STD_ULOGIC_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xnor R);
end function "xnor";
-- Id: L.27
function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L and STD_ULOGIC_VECTOR(R));
end function "and";
-- Id: L.28
function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) and R);
end function "and";
-- Id: L.29
function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L or STD_ULOGIC_VECTOR(R));
end function "or";
-- Id: L.30
function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) or R);
end function "or";
-- Id: L.31
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L nand STD_ULOGIC_VECTOR(R));
end function "nand";
-- Id: L.32
function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nand R);
end function "nand";
-- Id: L.33
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L nor STD_ULOGIC_VECTOR(R));
end function "nor";
-- Id: L.34
function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nor R);
end function "nor";
-- Id: L.35
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L xor STD_ULOGIC_VECTOR(R));
end function "xor";
-- Id: L.36
function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L xnor STD_ULOGIC_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xnor R);
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return and (STD_ULOGIC_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return and (STD_ULOGIC_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return nand (STD_ULOGIC_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return nand (STD_ULOGIC_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return or (STD_ULOGIC_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return or (STD_ULOGIC_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return nor (STD_ULOGIC_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return nor (STD_ULOGIC_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return xor (STD_ULOGIC_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return xor (STD_ULOGIC_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return xnor (STD_ULOGIC_VECTOR (L));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return xnor (STD_ULOGIC_VECTOR (L));
end function "xnor";
-- ============================================================================
-- support constants for STD_MATCH:
type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE : BOOLEAN_TABLE := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(false, false, false, false, false, false, false, false, true), -- | U |
(false, false, false, false, false, false, false, false, true), -- | X |
(false, false, true, false, false, false, true, false, true), -- | 0 |
(false, false, false, true, false, false, false, true, true), -- | 1 |
(false, false, false, false, false, false, false, false, true), -- | Z |
(false, false, false, false, false, false, false, false, true), -- | W |
(false, false, true, false, false, false, true, false, true), -- | L |
(false, false, false, true, false, false, false, true, true), -- | H |
(true, true, true, true, true, true, true, true, true) -- | - |
);
-- Id: M.1
function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is
begin
return MATCH_TABLE(L, R);
end function STD_MATCH;
-- Id: M.2
function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
alias LV : UNRESOLVED_UNSIGNED(1 to L'length) is L;
alias RV : UNRESOLVED_UNSIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.3
function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
alias LV : UNRESOLVED_SIGNED(1 to L'length) is L;
alias RV : UNRESOLVED_SIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.5
function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L;
alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- ============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0')
return UNRESOLVED_UNSIGNED is
begin
if (S'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAU"
severity warning;
return NAU;
end if;
return UNRESOLVED_UNSIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP));
end function TO_01;
-- Id: T.2
function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0')
return UNRESOLVED_SIGNED is
begin
if (S'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAS"
severity warning;
return NAS;
end if;
return UNRESOLVED_SIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP));
end function TO_01;
-- Id: T.3
function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_X01(STD_ULOGIC_VECTOR(S)));
end function TO_X01;
-- Id: T.4
function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_X01(STD_ULOGIC_VECTOR(S)));
end function TO_X01;
-- Id: T.5
function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S)));
end function TO_X01Z;
-- Id: T.6
function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S)));
end function TO_X01Z;
-- Id: T.7
function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_UX01(STD_ULOGIC_VECTOR(S)));
end function TO_UX01;
-- Id: T.8
function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_UX01(STD_ULOGIC_VECTOR(S)));
end function TO_UX01;
-- Id: T.9
function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return IS_X(STD_ULOGIC_VECTOR(S));
end function IS_X;
-- Id: T.10
function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN is
begin
return IS_X(STD_ULOGIC_VECTOR(S));
end function IS_X;
-- ============================================================================
-- string conversion and write operations
-- ============================================================================
function TO_OSTRING (value : UNRESOLVED_UNSIGNED) return STRING is
begin
return TO_OSTRING(STD_ULOGIC_VECTOR (value));
end function TO_OSTRING;
function TO_OSTRING (value : UNRESOLVED_SIGNED) return STRING is
constant result_length : INTEGER := (value'length+2)/3;
constant pad : STD_ULOGIC_VECTOR(1 to (result_length*3 -
value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return TO_OSTRING(pad & STD_ULOGIC_VECTOR (value));
end function TO_OSTRING;
function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING is
begin
return to_hstring(STD_ULOGIC_VECTOR (value));
end function to_hstring;
function to_hstring (value : UNRESOLVED_SIGNED) return STRING is
constant result_length : INTEGER := (value'length+3)/4;
constant pad : STD_ULOGIC_VECTOR(1 to (result_length*4 -
value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_hstring(pad & STD_ULOGIC_VECTOR (value));
end function to_hstring;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.OREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.HREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
OWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : STD_ULOGIC_VECTOR(0 to (ne*3 - VALUE'length) - 1)
:= (others => VALUE (VALUE'left));
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
OWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
HWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : STD_ULOGIC_VECTOR(0 to (ne*4 - VALUE'length) - 1)
:= (others => VALUE(VALUE'left));
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
HWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
end package body NUMERIC_STD;
| gpl-2.0 | bab56fb52e10cf5a474e6573ceaf3f4a | 0.569105 | 3.852798 | false | false | false | false |
nickg/nvc | test/parse/error3.vhd | 1 | 2,906 | package AlertLogPkg is
-- type AlertLogIDType is range integer'low to integer'high ; -- next revision
subtype AlertLogIDType is integer ;
type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype AlertIndexType is AlertType range FAILURE to WARNING ;
type AlertCountType is array (AlertIndexType) of integer ;
type AlertEnableType is array(AlertIndexType) of boolean ;
type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType
subtype LogIndexType is LogType range DEBUG to PASSED ;
type LogEnableType is array (LogIndexType) of boolean ;
type AlertLogStructPType is protected
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) ;
end protected AlertLogStructPType ;
end AlertLogPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body AlertLogPkg is
-- synthesis translate_off
-- instead of justify(to_upper(to_string())), just look up the upper case, left justified values
type AlertNameType is array(AlertType) of string(1 to 7) ;
constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER "
--- ///////////////////////////////////////////////////////////////////////////
type AlertLogStructPType is protected body
------------------------------------------------------------
-- Report formatting settings, with defaults
variable PrintPassedVar : boolean := TRUE ;
variable PrintAffirmationsVar : boolean := FALSE ;
variable PrintDisabledAlertsVar : boolean := FALSE ;
variable PrintRequirementsVar : boolean := FALSE ;
variable HasRequirementsVar : boolean := FALSE ;
variable PrintIfHaveRequirementsVar : boolean := TRUE ;
variable DefaultPassedGoalVar : integer := 1 ;
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) is
begin
report ALERT_NAME(Level); -- Lower crash here
end procedure alert ;
end protected body AlertLogStructPType ;
end package body AlertLogPkg ;
-------------------------------------------------------------------------------
-- "GC removed all objects from arena ???" crash here
entity e is
end entity;
| gpl-3.0 | ccff280c0e1d52c8473b2098aa6c6d00 | 0.515829 | 5.754455 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/numeric_std_unsigned.vhdl | 2 | 25,976 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type STD_ULOGIC_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the STD_ULOGIC_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright IEEE P1076 WG. Licensed Apache 2.0";
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
end package NUMERIC_STD_UNSIGNED;
| gpl-2.0 | b853e7862f21bd07ae57a685221c572c | 0.580882 | 4.095869 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2265.vhd | 4 | 1,842 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2265.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02265ent IS
END c07s02b06x00p11n01i02265ent;
ARCHITECTURE c07s02b06x00p11n01i02265arch OF c07s02b06x00p11n01i02265ent IS
BEGIN
TESTING: PROCESS
variable V1,V2,V3 : Integer ;
variable A : Integer := 10 ;
variable B : Integer := 5 ;
BEGIN
V1 := -(A/B) ;
V2 := A/(-B) ;
assert NOT(V1 = V2)
report "***PASSED TEST: c07s02b06x00p11n01i02265"
severity NOTE;
assert (V1 = V2)
report "***FAILED TEST: c07s02b06x00p11n01i02265 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02265arch;
| gpl-2.0 | 8d25297798e3bceb2b88672da8ee0186 | 0.653637 | 3.528736 | false | true | false | false |
nickg/nvc | test/eopt/pcall1.vhd | 1 | 791 | entity pcall1 is
end entity;
architecture behav of pcall1 is
type point is record
x : integer;
y : integer;
z : boolean;
end record point;
type point_array is array (natural range <>) of point;
signal points : point_array(1 to 4) := (others => (x => 1, y => 1, z => true));
procedure update(signal pa : out point_array) is
begin
pa(3).x <= 7;
end procedure;
begin
p1: process
begin
assert points(3).x = 1;
points(2).y <= 4;
wait for 2 ns;
update(points);
wait;
end process;
p2: process is
begin
wait for 1 ns;
assert points(2) = (1, 4, true);
wait for 2 ns;
assert points(3) = (7, 1, true);
wait;
end process;
end behav;
| gpl-3.0 | 3a7b6d82fb72f9b2e44cde2aead4a72f | 0.532238 | 3.611872 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket96/ent.vhd | 2 | 673 | entity ent is
end entity;
architecture a of ent is
procedure proc(
constant seq : in string;
signal clk : in bit) is
begin
for i in seq'left to seq'right loop
report ("left=" & integer'image(seq'left) &
", right=" & integer'image(seq'right) &
", i=" & integer'image(i));
report "seq(i)=" & character'image(seq(i));
wait until rising_edge(clk);
end loop;
end procedure;
signal clk : bit := '0';
begin
clk <= not clk after 1 ns;
main : process
variable var : string(1 to 10 - 1);
begin
var := (others => '0');
proc(var & "0", clk);
wait;
end process;
end architecture;
| gpl-2.0 | bfac707587138bb5ed273360d81aa656 | 0.566122 | 3.52356 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue17/cond_assign_proc.vhdl | 2 | 616 | library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_proc is
end entity cond_assign_proc ;
architecture doit of cond_assign_proc is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (Clk)
variable A : std_logic ;
begin
A := 'H' when Clk = '1' else 'L' ;
Y <= A ;
-- Y <= 'H' when Clk = '1' else 'L' ;
end process ;
-- Y <= 'H' when Clk = '1' else 'L' ;
process
begin
wait for 500 ns ;
std.env.stop ;
end process ;
end architecture doit ;
| gpl-2.0 | 1a95c1cd9db67fea16b23a5f702ddde6 | 0.543831 | 3.126904 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/math_complex-body.vhdl | 3 | 52,648 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_COMPLEX package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common COMPLEX
-- : constants and common COMPLEX mathematical functions and
-- : operators.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use WORK.MATH_REAL.all;
package body MATH_COMPLEX is
--
-- Equality and Inequality Operators for COMPLEX_POLAR
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return TRUE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return TRUE;
end if;
return FALSE;
end function "=";
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return FALSE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return FALSE;
end if;
return TRUE;
end function "/=";
--
-- Other Functions Start Here
--
function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(X, Y);
end function CMPLX;
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Check if already a principal value
if ( X > -MATH_PI and X <= MATH_PI ) then
return PRINCIPAL_VALUE'(X);
end if;
-- Get principal value
TEMP := X;
while ( TEMP <= -MATH_PI ) loop
TEMP := TEMP + MATH_2_PI;
end loop;
while (TEMP > MATH_PI ) loop
TEMP := TEMP - MATH_2_PI;
end loop;
return PRINCIPAL_VALUE'(TEMP);
end function GET_PRINCIPAL_VALUE;
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.IM > 0.0 ) then
return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2);
else
return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.RE > 0.0 ) then
return COMPLEX_POLAR'(Z.RE, 0.0);
else
return COMPLEX_POLAR'(-Z.RE, MATH_PI);
end if;
end if;
-- Get principal value for general case
TEMP := ARCTAN(Z.IM, Z.RE);
return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM),
GET_PRINCIPAL_VALUE(TEMP));
end function COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns MATH_CZERO on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)"
severity ERROR;
return MATH_CZERO;
end if;
-- Get value for general case
return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
end function POLAR_TO_COMPLEX;
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
begin
-- Get value for general case
return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM));
end function "ABS";
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = Z.MAG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ABS(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.MAG;
end function "ABS";
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = ARCTAN(Z.IM, Z.RE)
variable ZTEMP : COMPLEX_POLAR;
begin
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
return ZTEMP.ARG;
end function ARG;
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = Z.ARG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ARG(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.ARG;
end function ARG;
function "-" (Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns -x -jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(-Z.RE, -Z.IM);
end function "-";
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (Z.MAG, Z.ARG + MATH_PI)
-- b) Returns Z on error
variable TEMP: REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in -(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
TEMP := REAL'(Z.ARG) + MATH_PI;
return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP));
end function "-";
function CONJ (Z: in COMPLEX) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns x - jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(Z.RE, -Z.IM);
end function CONJ;
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG)
-- b) Returns Z on error
--
variable TEMP: PRINCIPAL_VALUE;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in CONJ(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then
TEMP := Z.ARG;
else
TEMP := -Z.ARG;
end if;
return COMPLEX_POLAR'(Z.MAG, TEMP);
end function CONJ;
function SQRT(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable ZTEMP : COMPLEX_POLAR;
variable ZOUT : COMPLEX;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CZERO;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TMAG := SQRT(ZTEMP.MAG);
TARG := 0.5*ZTEMP.ARG;
if ( COS(TARG) > 0.0 ) then
ZOUT.RE := TMAG*COS(TARG);
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
if ( COS(TARG) < 0.0 ) then
ZOUT.RE := TMAG*COS(TARG + MATH_PI);
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end if;
if ( SIN(TARG) > 0.0 ) then
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end function SQRT;
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZOUT : COMPLEX_POLAR;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SQRT(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return Z;
end if;
-- Get principal value for general case
TMAG := SQRT(Z.MAG);
TARG := 0.5*Z.ARG;
ZOUT.MAG := POSITIVE_REAL'(TMAG);
if ( COS(TARG) < 0.0 ) then
TARG := TARG + MATH_PI;
end if;
if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then
TARG := TARG + MATH_PI;
end if;
ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG);
return ZOUT;
end function SQRT;
function EXP(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 0.0 ) then
if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then
return COMPLEX'(-1.0, 0.0);
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return COMPLEX'(0.0, -1.0);
end if;
end if;
-- Get value for general case
TEMP := EXP(Z.RE);
return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM));
end function EXP;
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in EXP(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or
Z.ARG = -MATH_PI_OVER_2 )) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 ) then
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get principal value for general case
ZTEMP := POLAR_TO_COMPLEX(Z);
ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE));
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM);
return ZOUT;
end function EXP;
function LOG(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = -1.0 ) then
return COMPLEX'(0.0, MATH_PI);
end if;
if ( Z.RE = MATH_E ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
if ( Z.RE = 0.0 ) then
if (Z.IM = 1.0) then
return COMPLEX'(0.0, MATH_PI_OVER_2);
end if;
if (Z.IM = -1.0) then
return COMPLEX'(0.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, ZTEMP.ARG);
end function LOG;
function LOG2(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 2.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG);
end function LOG2;
function LOG10(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 10.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG);
end function LOG10;
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 ) then
if ( Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2);
end if;
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG);
ZTEMP.IM := Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG;
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG2;
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG10;
function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMPRE : REAL;
variable TEMPIM : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = BASE ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMPRE := LOG(ZTEMP.MAG, BASE);
TEMPIM := ZTEMP.ARG/LOG(BASE);
return COMPLEX'(TEMPRE, TEMPIM);
end function LOG;
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = BASE and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG, BASE);
ZTEMP.IM := Z.ARG/LOG(BASE);
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG;
function SIN(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 or Z.RE = MATH_PI) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM));
end function SIN;
function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SIN(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function SIN;
function COS(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM));
end function COS;
function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COS(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function COS;
function SINH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then
return MATH_CZERO;
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return -MATH_CBASE_J;
end if;
end if;
-- Get value for general case
return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM));
end function SINH;
function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SINH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function SINH;
function COSH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI ) then
return -MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM));
end function COSH;
function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COSH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function COSH;
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R.RE, L.IM + R.IM);
end function "+";
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L + R.RE, R.IM);
end function "+";
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R, L.IM);
end function "+";
function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM));
return ZOUT;
end function "+";
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM));
return ZOUT;
end function "+";
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM));
return ZOUT;
end function "+";
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R.RE, L.IM - R.IM);
end function "-";
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L - R.RE, -1.0 * R.IM);
end function "-";
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R, L.IM);
end function "-";
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM));
return ZOUT;
end function "-";
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM));
return ZOUT;
end function "-";
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM));
return ZOUT;
end function "-";
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE);
end function "*";
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L * R.RE, L * R.IM);
end function "*";
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R, L.IM * R);
end function "*";
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG);
return ZOUT;
end function "*";
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if ( L < 0.0 ) then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG);
return ZOUT;
end function "*";
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if ( R < 0.0 ) then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG * ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG);
return ZOUT;
end function "*";
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
constant TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP,
(L.IM * R.RE - L.RE * R.IM) / TEMP);
end function "/";
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
TEMP := L / TEMP;
return COMPLEX'( TEMP * R.RE, -TEMP * R.IM );
end function "/";
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by 0.0"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'(L.RE / R, L.IM / R);
end function "/";
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG);
return ZOUT;
end function "/";
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by 0.0"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if R < 0.0 then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG/ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG);
return ZOUT;
end function "/";
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_P in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if L < 0.0 then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG);
return ZOUT;
end function "/";
end package body MATH_COMPLEX;
| gpl-2.0 | b293b10a7b1df9555dd7feef9a9a09a5 | 0.475194 | 4.140296 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue301/src/dec_viterbi.vhd | 1 | 12,311 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Viterbi decoder top entity, connecting all decoder units.
--! @author Markus Fehrenz
--! @date 2011/12/05
--!
--! @details
--! The AXI std_logic_vector input is mapped to an internal information type.
--! Further the correct output order is handled.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
use dec_viterbi.pkg_components.all;
use dec_viterbi.pkg_trellis.all;
entity dec_viterbi_top is
port(
--
-- The core only uses AXI4-Stream interfaces,
-- based on AMBA4 AXI4-Stream Protocol with restrictions according to
-- Xilinx Migration, described in Xilinx AXI Reference UG761 (v13.3).
--
aclk : in std_logic;
-- Synchronous reset, active low.
aresetn : in std_logic;
--
-- Slave (input) data signals
-- Delivers the parity LLR values, one byte per LLR value.
--
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic_vector(31 downto 0);
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
--
-- Master (output) data signals
-- Delivers the decoded systematic (payload) bits.
--
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic;
m_axis_output_tlast : out std_logic;
m_axis_output_tready : in std_logic;
--
-- Slave (input) configuration signals
-- Configures window length and acquisition length.
--
s_axis_ctrl_tvalid : in std_logic;
s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
s_axis_ctrl_tlast : in std_logic;
s_axis_ctrl_tready : out std_logic
);
end entity dec_viterbi_top;
architecture rtl of dec_viterbi_top is
alias clk is aclk;
signal rst : std_logic;
-- split tdata into input array
signal input : t_input_block;
-- buffer signals
signal buffer_tdata : std_logic_vector(31 downto 0);
signal buffer_tvalid : std_logic;
signal buffer_tlast : std_logic;
-- branch signals
signal branch_tvalid : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
signal branch_tdata : t_branch;
signal branch_tlast : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
signal branch_tready : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
-- acs signals
signal acs_tvalid : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
signal acs_tlast : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
signal acs_tready : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
signal acs_dec_tdata : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
signal acs_prob_tdata : t_node;
-- ram signals
signal ram_tready : std_logic;
signal ram_tvalid, ram_tlast, ram_window_tuser, ram_last_tuser : std_logic_vector(1 downto 0);
signal ram_tdata : t_ram_rd_data;
-- traceback signals
signal traceback_tvalid, traceback_tdata : std_logic_vector(1 downto 0);
signal traceback_tready, traceback_tlast : std_logic_vector(1 downto 0);
signal traceback_last_tuser : std_logic_vector(1 downto 0);
-- reorder signals
signal reorder_tready, reorder_tvalid : std_logic_vector(1 downto 0);
signal reorder_tdata, reorder_tlast : std_logic_vector(1 downto 0);
signal reorder_last_tuser : std_logic_vector(1 downto 0);
-- output signals
signal output_tready : std_logic_vector(1 downto 0);
signal current_active : integer range 1 downto 0;
begin
--
-- There is always one byte of data for each LLR value, even though each
-- LLR value is represented with BW_LLR_INPUT bits. Hence, only
-- BW_LLR_INPUT bits are extracted from the byte.
--
gen_input_assignment: for i in NUMBER_PARITY_BITS - 1 downto 0 generate
begin
input(i) <= signed(buffer_tdata(8 * i + BW_LLR_INPUT - 1 downto 8 * i));
end generate gen_input_assignment;
rst <= not aresetn;
------------------------------
--- Portmapping components ---
------------------------------
-------------------------------------
-- AXI4S input buffer
--------------------------------------
inst_axi4s_buffer: axi4s_buffer
generic map(
DATA_WIDTH => 32
)
port map(
clk => clk,
rst => rst,
input => s_axis_input_tdata,
input_valid => s_axis_input_tvalid,
input_last => s_axis_input_tlast,
input_accept => s_axis_input_tready,
output => buffer_tdata,
output_valid => buffer_tvalid,
output_last => buffer_tlast,
output_accept => branch_tready(0)
);
-------------------------------------
-- Branch metric unit
--------------------------------------
gen_branch_distance : for i in NUMBER_BRANCH_UNITS - 1 downto 0 generate
begin
inst_branch_distance : branch_distance
generic map(
EDGE_WEIGHT => std_logic_vector(to_unsigned(i, NUMBER_PARITY_BITS))
)
port map(
clk => clk,
rst => rst,
s_axis_input_tvalid => buffer_tvalid,
s_axis_input_tdata => input,
s_axis_input_tlast => buffer_tlast,
s_axis_input_tready => branch_tready(i),
m_axis_output_tvalid => branch_tvalid(i),
m_axis_output_tdata => branch_tdata(i),
m_axis_output_tlast => branch_tlast(i),
m_axis_output_tready => acs_tready(0)
);
end generate gen_branch_distance;
-------------------------------------
-- ACS unit (path metric calculation)
--------------------------------------
gen_acs : for i in 0 to NUMBER_TRELLIS_STATES - 1 generate
signal inbranch_tdata_low : std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
signal inbranch_tdata_high : std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
signal inprev_tdata_low : std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
signal inprev_tdata_high : std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
begin
inbranch_tdata_low <= branch_tdata(to_integer(unsigned(TRANSITIONS(i)(0))));
inbranch_tdata_high <= branch_tdata(to_integer(unsigned(TRANSITIONS(i)(1))));
inprev_tdata_low <= acs_prob_tdata(to_integer(unsigned(PREVIOUS_STATES(i)(0))));
inprev_tdata_high <= acs_prob_tdata(to_integer(unsigned(PREVIOUS_STATES(i)(1))));
inst_acs : acs
generic map(
initialize_value => INITIALIZE_TRELLIS(i)
)
port map(
clk => clk,
rst => rst,
s_axis_inbranch_tvalid => branch_tvalid(0),
s_axis_inbranch_tdata_low => inbranch_tdata_low,
s_axis_inbranch_tdata_high => inbranch_tdata_high,
s_axis_inbranch_tlast => branch_tlast(0),
s_axis_inbranch_tready => acs_tready(i),
s_axis_inprev_tvalid => '1',
s_axis_inprev_tdata_low => inprev_tdata_low,
s_axis_inprev_tdata_high => inprev_tdata_high,
s_axis_inprev_tready => open,
m_axis_outprob_tvalid => open,
m_axis_outprob_tdata => acs_prob_tdata(i),
m_axis_outprob_tready => '1',
m_axis_outdec_tvalid => acs_tvalid(i),
m_axis_outdec_tdata => acs_dec_tdata(i),
m_axis_outdec_tlast => acs_tlast(i),
m_axis_outdec_tready => ram_tready
);
end generate gen_acs;
-------------------------------
-- Traceback
-------------------------------
inst_ram_ctrl : ram_ctrl
port map (
clk => clk,
rst => rst,
s_axis_input_tvalid => acs_tvalid(0),
s_axis_input_tdata => acs_dec_tdata,
s_axis_input_tlast => acs_tlast(0),
s_axis_input_tready => ram_tready,
m_axis_output_tvalid => ram_tvalid,
m_axis_output_tdata => ram_tdata,
m_axis_output_tlast => ram_tlast,
m_axis_output_tready => traceback_tready,
m_axis_output_window_tuser => ram_window_tuser,
m_axis_output_last_tuser => ram_last_tuser,
s_axis_ctrl_tvalid => s_axis_ctrl_tvalid,
s_axis_ctrl_tdata => s_axis_ctrl_tdata,
s_axis_ctrl_tready => s_axis_ctrl_tready
);
gen_inst_trellis_traceback : for i in 1 downto 0 generate
begin
inst_trellis_traceback : trellis_traceback
port map(
clk => clk,
rst => rst,
s_axis_input_tvalid => ram_tvalid(i),
s_axis_input_tdata => ram_tdata(i),
s_axis_input_tlast => ram_tlast(i),
s_axis_input_tready => traceback_tready(i),
s_axis_input_window_tuser => ram_window_tuser(i),
s_axis_input_last_tuser => ram_last_tuser(i),
m_axis_output_tvalid => traceback_tvalid(i),
m_axis_output_tdata => traceback_tdata(i),
m_axis_output_tlast => traceback_tlast(i),
m_axis_output_last_tuser => traceback_last_tuser(i),
m_axis_output_tready => reorder_tready(i)
);
end generate gen_inst_trellis_traceback;
-------------------------------
-- Reverse output order
-------------------------------
gen_inst_reorder : for i in 1 downto 0 generate
begin
inst_reorder : reorder
port map(
clk => clk,
rst => rst,
s_axis_input_tvalid => traceback_tvalid(i),
s_axis_input_tdata => traceback_tdata(i),
s_axis_input_tlast => traceback_tlast(i),
s_axis_input_last_tuser => traceback_last_tuser(i),
s_axis_input_tready => reorder_tready(i),
m_axis_output_tvalid => reorder_tvalid(i),
m_axis_output_tdata => reorder_tdata(i),
m_axis_output_tlast => reorder_tlast(i),
m_axis_output_last_tuser => reorder_last_tuser(i),
m_axis_output_tready => output_tready(i)
);
end generate gen_inst_reorder;
------------------------------
-- Recursive codes handling --
------------------------------
gen_inst_recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
signal reorder_recursion_tvalid : std_logic;
signal reorder_recursion_tdata : std_logic;
signal reorder_recursion_tlast : std_logic;
signal recursion_tready : std_logic;
begin
inst_recursion : recursionx
port map(
clk => clk,
rst => rst,
s_axis_input_tvalid => reorder_recursion_tvalid,
s_axis_input_tdata => reorder_recursion_tdata,
s_axis_input_tlast => reorder_recursion_tlast,
s_axis_input_tready => recursion_tready,
m_axis_output_tvalid => m_axis_output_tvalid,
m_axis_output_tdata => m_axis_output_tdata,
m_axis_output_tlast => m_axis_output_tlast,
m_axis_output_tready => m_axis_output_tready
);
-------------------------------
-- Output interface handling
-------------------------------
reorder_recursion_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
'0';
reorder_recursion_tdata <= reorder_tdata(0) when current_active = 0 else
reorder_tdata(1);
reorder_recursion_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
'0';
output_tready(0) <= '1' when (current_active = 0) and m_axis_output_tready = '1' else
'0';
output_tready(1) <= '1' when (current_active = 1) and m_axis_output_tready = '1' else
'0';
end generate gen_inst_recursion;
no_recursion: if FEEDBACK_POLYNOMIAL = 0 generate
-------------------------------
-- Output interface handling
-------------------------------
m_axis_output_tdata <= reorder_tdata(0) when current_active = 0 else
reorder_tdata(1);
m_axis_output_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
'0';
m_axis_output_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
'0';
output_tready(0) <= '1' when (current_active = 0) and m_axis_output_tready = '1' else
'0';
output_tready(1) <= '1' when (current_active = 1) and m_axis_output_tready = '1' else
'0';
end generate no_recursion;
recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
begin
end generate recursion;
-- Check and merge reordering outputs and block if necessary.
pr_reorder_tready : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
current_active <= 0;
else
if reorder_tvalid(current_active) = '1' and m_axis_output_tready = '1' and reorder_last_tuser(current_active) = '1' then
current_active <= 1 - current_active;
end if;
end if;
end if;
end process pr_reorder_tready;
end architecture rtl;
| gpl-2.0 | 6f6dc426df4a30ed1f0f79e3eaa16b59 | 0.617497 | 3.184428 | false | false | false | false |
nickg/nvc | test/bounds/bounds.vhd | 1 | 7,226 | entity bounds is
end entity;
architecture test of bounds is
type foo is range 1 to 5;
type my_vec1 is array (positive range <>) of integer;
type my_vec2 is array (foo range <>) of integer;
signal s : my_vec1(1 to 10);
signal n : my_vec1(1 downto 10);
subtype bool_true is boolean range true to true;
function fun(x : in bit_vector(7 downto 0)) return bit;
procedure proc(x : in bit_vector(7 downto 0));
function natfunc(x : in natural) return boolean;
function enumfunc(x : in bool_true) return boolean;
function realfunc(x : in real) return boolean;
type matrix is array (integer range <>, integer range <>) of integer;
procedure proc2(x : in matrix(1 to 3, 1 to 3));
begin
process is
variable a : my_vec1(0 to 10); -- Error
variable b : my_vec2(1 to 60); -- Error
begin
end process;
s(-52) <= 5; -- Error
s(1 to 11) <= (others => 0); -- Error
s(0 to 2) <= (others => 0); -- Error
process is
begin
report (0 => 'a'); -- Error
end process;
process is
variable v1 : bit_vector(3 downto 0);
variable v2 : bit_vector(8 downto 1);
variable m1 : matrix(1 to 3, 2 to 4);
variable m2 : matrix(1 to 3, 1 to 4);
begin
assert fun(v1) = '1'; -- Error
proc(v1); -- Error
proc(v2); -- OK
proc2(m1); -- OK
proc2(m2); -- Error
end process;
s <= s(1 to 9); -- Error
n <= s(1 to 2); -- Error
n <= (1, 2, 3); -- Error
process is
variable v : my_vec1(1 to 3);
begin
v := s; -- Error
end process;
process is
variable x : integer;
begin
x := s(11); -- Error!
x := s(-1); -- Error!
end process;
process is
variable a : my_vec1(1 to 3);
begin
a := (1, 2, 3); -- OK
a := (5 => 1, 1 => 2, 0 => 3); -- Error
end process;
process is
subtype alpha is character range 'a' to 'z';
variable a : alpha;
variable p : positive;
begin
a := 'c'; -- OK
a := '1'; -- Error
p := 0; -- Error
end process;
process is
begin
assert s'length(5) = 5; -- Error
end process;
process is
begin
assert natfunc(-1); -- Error
end process;
process is
subtype str is string;
constant c : str := "hello"; -- OK
begin
end process;
process is
variable a : my_vec1(1 to 3);
begin
a := (1, others => 2); -- OK
a := (5 => 1, others => 2); -- Error
end process;
process is
type mat2d is array (integer range <>, integer range <>)
of integer;
procedure p(m : in mat2d);
begin
p(((0, 1, 2, 3), (1 to 2 => 5))); -- Error
end process;
-- Reduced from Billowitch tc1374
process is
type t_rec3 is record
f1 : boolean;
end record;
subtype st_rec3 is t_rec3 ;
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype st_arr3 is t_arr3 (1 to 5, true downto false) ;
variable v_st_arr3 : st_arr3;
begin
v_st_arr3(1, true) := (f1 => false);
end process;
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
begin
assert i'a(14) = '0'; -- Error
end process;
process is
constant FPO_LOG_MAX_ITERATIONS : integer := 9;
type T_FPO_LOG_ALPHA is array (0 to FPO_LOG_MAX_ITERATIONS-1) of integer;
variable alpha : T_FPO_LOG_ALPHA;
begin
if alpha(0 to 5) = (5, 4, 6, 6, 6, 6) then -- OK
null;
end if;
end process;
process is
procedure real_proc(x : in real range 0.0 to 1.0);
begin
real_proc(0.0); -- OK
real_proc(1.0); -- OK
real_proc(2.0); -- Error
end process;
process is
type e is (one, two, three, four, five);
subtype se is e range two to four;
type t_arr is array (se range <>) of boolean;
constant c1 : t_arr(two to four) := (true, true);
constant c2 : t_arr(two to four) := (true, true, true, true);
procedure enum_proc(
arg1 : e range two to four;
arg2 : e range three downto two
) is
begin
end procedure;
begin
enum_proc(arg1 => two, arg2 => two); -- ok
enum_proc(arg1 => three, arg2 => one); -- Error
enum_proc(arg1 => four, arg2 => four); -- Error
enum_proc(arg1 => one, arg2 => three); -- Error
enum_proc(arg1 => five, arg2 => three); -- Error
end process;
process is
type e is (one, two, three, four, five);
type t_arr is array (two to four) of integer;
variable a : t_arr;
begin
a := (1, others => 2); -- OK
a := (two => 1, others => 2); -- OK
a := (one => 1, others => 2); -- Error
a := (two to four => 1, others => 2); -- OK
a := (one to five => 1, others => 2); -- Error
end process;
process is
type e is (one, two, three, four, five);
type mat2d is array (e range <>, e range <>) of integer;
procedure p(m : in mat2d);
begin
p(((0, 1, 2, 3), (one to three => 5))); -- Error
end process;
process is
type e is (one, two, three, four, five);
subtype se is e range two to three;
type arr is array (se range <>) of integer;
variable v1 : arr(two to three); -- OK
variable v2 : arr(one to four); -- Error
begin
end process;
process is
procedure phys_proc_to(a : in time range 0 ns to 10 ns) is
begin
end procedure;
procedure phys_proc_dt(a : in time range 10 sec downto 20 us) is
begin
end procedure;
begin
phys_proc_to(5 ns); -- OK
phys_proc_to(-5 ns); -- Error
phys_proc_dt(1 ms); -- OK
phys_proc_dt(5 ns); -- Error
end process;
process
variable t : time range -10 ns to 10 ns;
begin
t := 200 ns; -- Error
t := -200 ns; -- Error
t := 0 ns; -- OK
end process;
process is
type char_map is array (character range 'a' to 'z') of integer;
variable m : char_map;
begin
m('A') := 1; -- Error
m('1' to '3') := (others => 3); -- Error
end process;
process is
variable v : bit_vector(1 to 3);
alias a : bit_vector(1 to 4) is v; -- Error
begin
a(4) := '1'; -- OK
end process;
end architecture;
| gpl-3.0 | 65f20faaa7cefc6b34d297d5fc296005 | 0.473014 | 3.751817 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_avlmm_pr_freeze_bridge_0/ghrd_10as066n2_avlmm_pr_freeze_bridge_0_inst.vhd | 1 | 7,590 | component ghrd_10as066n2_avlmm_pr_freeze_bridge_0 is
port (
clock : in std_logic := 'X'; -- clk
freeze_conduit_freeze : in std_logic := 'X'; -- freeze
freeze_conduit_illegal_request : out std_logic; -- illegal_request
reset_n : in std_logic := 'X'; -- reset_n
slv_bridge_to_pr_read : out std_logic; -- read
slv_bridge_to_pr_waitrequest : in std_logic := 'X'; -- waitrequest
slv_bridge_to_pr_write : out std_logic; -- write
slv_bridge_to_pr_address : out std_logic_vector(9 downto 0); -- address
slv_bridge_to_pr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
slv_bridge_to_pr_writedata : out std_logic_vector(31 downto 0); -- writedata
slv_bridge_to_pr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
slv_bridge_to_pr_burstcount : out std_logic_vector(2 downto 0); -- burstcount
slv_bridge_to_pr_readdatavalid : in std_logic := 'X'; -- readdatavalid
slv_bridge_to_pr_beginbursttransfer : out std_logic; -- beginbursttransfer
slv_bridge_to_pr_debugaccess : out std_logic; -- debugaccess
slv_bridge_to_pr_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
slv_bridge_to_pr_lock : out std_logic; -- lock
slv_bridge_to_pr_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
slv_bridge_to_sr_read : in std_logic := 'X'; -- read
slv_bridge_to_sr_waitrequest : out std_logic; -- waitrequest
slv_bridge_to_sr_write : in std_logic := 'X'; -- write
slv_bridge_to_sr_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
slv_bridge_to_sr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
slv_bridge_to_sr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
slv_bridge_to_sr_readdata : out std_logic_vector(31 downto 0); -- readdata
slv_bridge_to_sr_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
slv_bridge_to_sr_readdatavalid : out std_logic; -- readdatavalid
slv_bridge_to_sr_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
slv_bridge_to_sr_debugaccess : in std_logic := 'X'; -- debugaccess
slv_bridge_to_sr_response : out std_logic_vector(1 downto 0); -- response
slv_bridge_to_sr_lock : in std_logic := 'X'; -- lock
slv_bridge_to_sr_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component ghrd_10as066n2_avlmm_pr_freeze_bridge_0;
u0 : component ghrd_10as066n2_avlmm_pr_freeze_bridge_0
port map (
clock => CONNECTED_TO_clock, -- clock.clk
freeze_conduit_freeze => CONNECTED_TO_freeze_conduit_freeze, -- freeze_conduit.freeze
freeze_conduit_illegal_request => CONNECTED_TO_freeze_conduit_illegal_request, -- .illegal_request
reset_n => CONNECTED_TO_reset_n, -- reset_n.reset_n
slv_bridge_to_pr_read => CONNECTED_TO_slv_bridge_to_pr_read, -- slv_bridge_to_pr.read
slv_bridge_to_pr_waitrequest => CONNECTED_TO_slv_bridge_to_pr_waitrequest, -- .waitrequest
slv_bridge_to_pr_write => CONNECTED_TO_slv_bridge_to_pr_write, -- .write
slv_bridge_to_pr_address => CONNECTED_TO_slv_bridge_to_pr_address, -- .address
slv_bridge_to_pr_byteenable => CONNECTED_TO_slv_bridge_to_pr_byteenable, -- .byteenable
slv_bridge_to_pr_writedata => CONNECTED_TO_slv_bridge_to_pr_writedata, -- .writedata
slv_bridge_to_pr_readdata => CONNECTED_TO_slv_bridge_to_pr_readdata, -- .readdata
slv_bridge_to_pr_burstcount => CONNECTED_TO_slv_bridge_to_pr_burstcount, -- .burstcount
slv_bridge_to_pr_readdatavalid => CONNECTED_TO_slv_bridge_to_pr_readdatavalid, -- .readdatavalid
slv_bridge_to_pr_beginbursttransfer => CONNECTED_TO_slv_bridge_to_pr_beginbursttransfer, -- .beginbursttransfer
slv_bridge_to_pr_debugaccess => CONNECTED_TO_slv_bridge_to_pr_debugaccess, -- .debugaccess
slv_bridge_to_pr_response => CONNECTED_TO_slv_bridge_to_pr_response, -- .response
slv_bridge_to_pr_lock => CONNECTED_TO_slv_bridge_to_pr_lock, -- .lock
slv_bridge_to_pr_writeresponsevalid => CONNECTED_TO_slv_bridge_to_pr_writeresponsevalid, -- .writeresponsevalid
slv_bridge_to_sr_read => CONNECTED_TO_slv_bridge_to_sr_read, -- slv_bridge_to_sr.read
slv_bridge_to_sr_waitrequest => CONNECTED_TO_slv_bridge_to_sr_waitrequest, -- .waitrequest
slv_bridge_to_sr_write => CONNECTED_TO_slv_bridge_to_sr_write, -- .write
slv_bridge_to_sr_address => CONNECTED_TO_slv_bridge_to_sr_address, -- .address
slv_bridge_to_sr_byteenable => CONNECTED_TO_slv_bridge_to_sr_byteenable, -- .byteenable
slv_bridge_to_sr_writedata => CONNECTED_TO_slv_bridge_to_sr_writedata, -- .writedata
slv_bridge_to_sr_readdata => CONNECTED_TO_slv_bridge_to_sr_readdata, -- .readdata
slv_bridge_to_sr_burstcount => CONNECTED_TO_slv_bridge_to_sr_burstcount, -- .burstcount
slv_bridge_to_sr_readdatavalid => CONNECTED_TO_slv_bridge_to_sr_readdatavalid, -- .readdatavalid
slv_bridge_to_sr_beginbursttransfer => CONNECTED_TO_slv_bridge_to_sr_beginbursttransfer, -- .beginbursttransfer
slv_bridge_to_sr_debugaccess => CONNECTED_TO_slv_bridge_to_sr_debugaccess, -- .debugaccess
slv_bridge_to_sr_response => CONNECTED_TO_slv_bridge_to_sr_response, -- .response
slv_bridge_to_sr_lock => CONNECTED_TO_slv_bridge_to_sr_lock, -- .lock
slv_bridge_to_sr_writeresponsevalid => CONNECTED_TO_slv_bridge_to_sr_writeresponsevalid -- .writeresponsevalid
);
| mit | 19cc32d12d1bff524fcda443b6f0673e | 0.498946 | 3.971743 | false | false | false | false |
nickg/nvc | test/lower/issue215.vhd | 1 | 775 | entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
PROC_B(I,O);
end procedure;
variable oo : integer;
begin
PROC_A(I,oo);
O <= oo;
end process;
end MODEL;
entity TOP is
end TOP;
architecture MODEL of TOP is
component SUB is
port (I:in integer;O:out integer);
end component;
signal A_I, A_O : integer;
signal B_I, B_O : integer;
begin
A: SUB port map(I => A_I, O => A_O);
B: SUB port map(I => B_I, O => B_O);
end MODEL;
| gpl-3.0 | 5366ba97b7fa5db155263273a2170348 | 0.543226 | 3.297872 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug07/repro.vhdl | 3 | 424 | entity repro is
end repro;
architecture behav of repro is
type int_vector is array (natural range <>) of integer;
constant c1 : int_vector (0 to 1) := 12 & 13;
constant c2 : int_vector (0 to 1) := 14 & 15;
constant p : boolean := c1 = c2;
constant p1 : boolean := c1 < c2;
begin
process
begin
case true is
when p => null;
when true => null;
end case;
wait;
end process;
end behav;
| gpl-2.0 | aa383cdcdf122862612d086d5f081479 | 0.613208 | 3.338583 | false | false | false | false |
tgingold/ghdl | testsuite/synth/fsm03/ent.vhdl | 1 | 516 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : std_logic;
req : std_logic;
val : std_logic;
ack : out std_logic);
end ent;
architecture behav of ent is
signal cnt : natural range 0 to 5;
begin
process (clk)
begin
if rising_edge(clk) then
if cnt < 5 then
cnt <= cnt + 1;
else
cnt <= 0;
end if;
if req = '1' and cnt = 0 then
ack <= '1';
else
ack <= '0';
end if;
end if;
end process;
end behav;
| gpl-2.0 | 0c87337071812dd3bc17b3dd95bfd5dc | 0.534884 | 3.265823 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/dff10.vhdl | 1 | 526 | library ieee;
use ieee.std_logic_1164.all;
entity dff10 is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic;
rst : std_logic;
en : std_logic);
end dff10;
architecture behav of dff10 is
begin
process (clk, rst) is
constant rval : std_logic_vector(7 downto 0) := x"55";
begin
if rst = '1' then
q <= rval;
elsif rising_edge (clk) then
if en = '1' then
q <= d;
end if;
end if;
end process;
end behav;
| gpl-2.0 | cd42e7c7a26fef5a0512a0a663c6ff25 | 0.576046 | 3.149701 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2097.vhd | 4 | 2,143 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2097.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02097ent IS
END c07s02b04x00p20n01i02097ent;
ARCHITECTURE c07s02b04x00p20n01i02097arch OF c07s02b04x00p20n01i02097ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4 is boolean_v (1 to 4);
SUBTYPE boolean_8 is boolean_v (1 to 8);
BEGIN
TESTING : PROCESS
variable result : boolean_8;
variable l_operand : boolean_4 := (true,false,true,false);
variable r_operand : boolean_4 := (false,false,true,true);
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result = (true,false,true,false,false,false,true,true))
report "***PASSED TEST: c07s02b04x00p20n01i02097"
severity NOTE;
assert (result = (true,false,true,false,false,false,true,true))
report "***FAILED TEST: c07s02b04x00p20n01i02097 - Variable concatenation did not succeed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02097arch;
| gpl-2.0 | 65ce939ec873162cdde1ef314c36b645 | 0.670089 | 3.601681 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1081/test.vhdl | 1 | 780 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port(
clk: in std_ulogic;
a_in : in std_ulogic_vector(1 downto 0);
b_out : out std_ulogic_vector(2 downto 0)
);
end test;
architecture rtl of test is
function test_fn(a: std_ulogic_vector(1 downto 0)) return std_ulogic_vector is
variable n : integer range 0 to 3;
begin
case a is
when "11" =>
n := 0;
when "10" =>
n:= 1;
when others =>
--n := 0;
return "000";
end case;
return "1" & std_ulogic_vector(to_unsigned(n, 2));
end;
begin
process(clk)
begin
b_out <= test_fn(a_in);
end process;
end;
| gpl-2.0 | f454da06dd390ac007cfc7d07fcc9135 | 0.507692 | 3.513514 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/output_split7.vhd | 2 | 1,410 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split7 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split7;
architecture augh of output_split7 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 0b9e373ec479d2de6e9fddcd39959c35 | 0.673759 | 2.895277 | false | false | false | false |
nickg/nvc | test/regress/driver8.vhd | 1 | 3,255 | library ieee;
use ieee.std_logic_1164.all;
entity sub is
generic ( n : natural range 0 to 1 );
port ( x : inout std_logic );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert x = 'U';
wait for 1 ns;
case n is
when 0 =>
x <= 'L';
wait for 0 ns;
assert x'active;
assert x'event;
assert x = '0' report "expected '0' got " & std_logic'image(x);
wait for 0 ns;
assert x'active;
assert x'event;
wait for 0 ns;
assert x'active;
assert x'event;
x <= '1';
wait for 0 ns;
assert x'active;
assert x'event;
when 1 =>
x <= '0';
wait for 0 ns;
assert x = '0' report "expected '0' got " & std_logic'image(x);
assert x'active;
assert x'event report "no event: " & std_logic'image(x'last_value)
& " -> " & std_logic'image(x);
x <= '1';
wait for 0 ns;
assert x'active;
assert x'event;
assert x = '1' report "expected '1' got " & std_logic'image(x);
x <= 'Z';
wait for 0 ns;
assert x'active;
assert x'event;
assert x = 'L' report "expected 'L' got " & std_logic'image(x);
wait for 0 ns;
assert x'active;
assert x'event;
assert x = '1' report "expected '1' got " & std_logic'image(x);
wait for 5 ns;
assert x = 'X' report "expected 'X' got " & std_logic'image(x);
x <= '1';
wait for 0 ns;
assert x'active;
assert not x'event;
end case;
wait;
end process;
p2: process is
begin
x <= 'Z';
for i in 1 to 4 loop
wait on x;
end loop;
assert x = '1';
wait for 1 ns;
x <= '0';
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity driver8 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver8 is
signal y : std_logic;
begin
sub1: entity work.sub generic map ( 0 ) port map ( y );
sub2: entity work.sub generic map ( 1 ) port map ( y );
p1: process is
begin
assert y = 'U';
wait for 1 ns;
assert y = 'U' report "expected 'U' got " & std_logic'image(y);
wait for 0 ns;
assert y = '0' report "expected '0' got " & std_logic'image(y);
wait for 0 ns;
assert y = '1' report "expected '1' got " & std_logic'image(y);
wait for 0 ns;
assert y = 'L' report "expected 'L' got " & std_logic'image(y);
wait for 1 ns;
assert y = '1' report "expected '1' got " & std_logic'image(y);
wait for 5 ns;
assert y = 'X' report "expected 'X' got " & std_logic'image(y);
wait;
end process;
end architecture;
| gpl-3.0 | 68fddefc3dcf22b86b14ce1329683ea8 | 0.445161 | 3.907563 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd | 4 | 2,844 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
library IEEE; use IEEE.std_logic_1164.all;
entity tb_timer_w_stim is
end tb_timer_w_stim;
architecture TB_timer_w_stim of tb_timer_w_stim is
-- Component declarations
-- Signal declarations
terminal in_src, rc_ext : electrical;
signal trig, rst : std_ulogic;
signal tim_out : std_ulogic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_constant(ideal)
generic map(
level => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
R1 : entity work.resistor(simple)
generic map(
resistance => 10.0e3
)
port map(
pos => in_src,
neg => rc_ext
);
C1 : entity work.capacitor(ideal)
generic map(
cap => 10.0e-6
)
port map(
p1 => rc_ext,
p2 => electrical_ref
);
timer1 : entity work.timer(behavioral)
generic map(
threshold => 2.0,
clamp_on_resistance => 1.0e-3,
clamp_off_resistance => 1.0e6
)
port map(
trigger_n => trig,
reset => rst,
q => tim_out,
rc_ext => rc_ext
);
-- rst
P_rst :
process
begin
wait for 0.000 ns; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait for 100.000 ms; rst <= '1';
wait for 1.000 ms; rst <= '0';
wait;
end process;
-- trig
P_trig :
process
begin
wait for 0.0 ns; trig <= '0';
wait for 5.000 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait for 40.0 ms; trig <= '1';
wait for 1.0 ms; trig <= '0';
wait for 1.0 ms; trig <= '1';
wait;
end process;
end TB_timer_w_stim;
| gpl-2.0 | 7a35be3848326fd43c88804d561e7909 | 0.555907 | 3.541719 | false | false | false | false |
nickg/nvc | test/elab/issue374.vhd | 2 | 1,805 | -- test_ng.vhd
entity SUB_NG is
generic (
DATA_BITS : integer := 32
);
port (
I_DATA : in bit_vector(DATA_BITS-1 downto 0);
O_DATA : out bit_vector(DATA_BITS-1 downto 0)
);
end SUB_NG;
architecture MODEL of SUB_NG is
begin
T2M: block
type INFO_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
BITS : integer;
end record;
function SET_INFO_RANGE return INFO_RANGE_TYPE is
variable param : INFO_RANGE_TYPE;
variable index : integer;
begin
index := 0;
param.DATA_LO := index;
param.DATA_HI := index + DATA_BITS - 1;
index := index + DATA_BITS;
param.BITS := index;
return param;
end function;
constant INFO_RANGE : INFO_RANGE_TYPE := SET_INFO_RANGE;
signal i_info : bit_vector(INFO_RANGE.BITS-1 downto 0);
signal o_info : bit_vector(INFO_RANGE.BITS-1 downto 0);
begin
i_info(INFO_RANGE.DATA_HI downto INFO_RANGE.DATA_LO) <= I_DATA;
o_info <= i_info;
O_DATA <= o_info(INFO_RANGE.DATA_HI downto INFO_RANGE.DATA_LO);
end block;
end MODEL;
entity issue374 is
end issue374;
architecture MODEL of issue374 is
signal data_0 : bit_vector(12 downto 0);
signal data_1 : bit_vector(13 downto 0);
begin
U0: entity WORK.SUB_NG
generic map (
DATA_BITS => data_0'length
)
port map (
I_DATA => data_0
);
U1: entity WORK.SUB_NG
generic map (
DATA_BITS => data_1'length
)
port map (
I_DATA => data_1
);
end MODEL;
| gpl-3.0 | ef9364a847b67d1fab6bfa3f3e8dbebe | 0.513019 | 3.617234 | false | false | false | false |
tgingold/ghdl | testsuite/synth/arr02/tb_arr01.vhdl | 1 | 879 | entity tb_arr01 is
end tb_arr01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr01 is
signal a : std_logic_vector (31 downto 0);
signal sel : natural range 0 to 3;
signal clk : std_logic;
signal res : std_logic_vector (7 downto 0);
begin
dut: entity work.arr01
port map (a, sel, clk, res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= x"a1b2c3d4";
sel <= 0;
pulse;
pulse;
assert res = x"a1" severity failure;
sel <= 1;
pulse;
assert res = x"a1" severity failure;
sel <= 2;
pulse;
assert res = x"b2" severity failure;
sel <= 3;
pulse;
assert res = x"c3" severity failure;
sel <= 0;
pulse;
assert res = x"d4" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | cd43c40074a6510020bacc2aae5b5219 | 0.585893 | 3.196364 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_09.vhd | 4 | 1,744 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- not in book
entity alarm_clock is
end entity alarm_clock;
-- end not in book
architecture top_level of alarm_clock is
--use work.counter_types.digit;
use work.counter_types.all;
signal reset_to_midnight, seconds_clk : bit;
signal seconds_units, seconds_tens : digit;
-- . . .
begin
seconds : configuration work.counter_down_to_gate_level
port map ( clk => seconds_clk, clr => reset_to_midnight,
q0 => seconds_units, q1 => seconds_tens );
-- . . .
-- not in book
clk_gen : seconds_clk <= not seconds_clk after 20 ns;
clr_gen : reset_to_midnight <= '1' after 95 ns,
'0' after 135 ns;
-- end not in book;
end architecture top_level;
| gpl-2.0 | ad34efa254887ec14d02e208c7fbc3f6 | 0.624427 | 3.774892 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd | 4 | 2,004 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity motor_system_wa is
port ( terminal vp, vm, px1, px2, px3 : electrical); -- 2 inputs, 3 outputs
end entity motor_system_wa;
----------------------------------------------------------------
architecture simple of motor_system_wa is
quantity v_in across vp to vm; -- Inout voltage/Current
quantity x1 across ix1 through px1 to electrical_ref;
quantity x2 across ix2 through px2 to electrical_ref;
quantity x3 across ix3 through px3 to electrical_ref;
constant Tfb : real := 0.001;
constant Kfb : real := 1.0;
constant Te : real := 0.001;
constant Ke : real := 1.0;
constant Tm : real := 0.1;
constant Km : real := 1.0;
constant c11 : real := -1.0/Tfb;
constant c12 : real := 0.0;
constant c13 : real := Kfb/Tfb;
constant c21 : real := -Ke/Te;
constant c22 : real := -1.0/Te;
constant c23 : real := 0.0;
constant c31 : real := 0.0;
constant c32 : real := Km/Tm;
constant c33 : real := -1.0/Tm;
begin -- architecture simple
x1'dot == c11*x1 + c12*x2 + c13*x3;
x2'dot == c21*x1 + c22*x2 + c23*x3 + (Ke/Te)*v_in;
x3'dot == c31*x1 + c32*x2 + c33*x3;
end architecture simple;
| gpl-2.0 | 0d175320cb2cd2b885d4c3aeffb156f6 | 0.662675 | 3.351171 | false | false | false | false |
tgingold/ghdl | testsuite/synth/stmt01/tb_forloop2.vhdl | 1 | 650 | entity tb_forloop2 is
end tb_forloop2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_forloop2 is
signal vin : std_logic_vector (7 downto 0);
signal vout : std_logic_vector (3 downto 0);
signal clk : std_logic;
signal b : std_logic;
signal c : std_logic;
signal z : std_logic;
begin
dut: entity work.forloop2
port map (vin => vin, vout => vout, clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
vin <= x"00";
pulse;
assert vout = x"0" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | efef4ebf4fb23962c74a4e2ef28780c2 | 0.618462 | 3.233831 | false | false | false | false |
tgingold/ghdl | testsuite/synth/fsm01/fsm_3s.vhdl | 1 | 851 | library ieee;
use ieee.std_logic_1164.all;
entity fsm_3s is
port (clk : std_logic;
rst : std_logic;
d : std_logic;
done : out std_logic);
end fsm_3s;
architecture behav of fsm_3s is
type state_t is (S0_1, S1_0, S2_1);
signal s : state_t;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
s <= S0_1;
done <= '0';
else
-- Reset by default
s <= S0_1;
done <= '0';
case s is
when S0_1 =>
if d = '1' then
s <= S1_0;
end if;
when S1_0 =>
if d = '0' then
s <= S2_1;
end if;
when S2_1 =>
if d = '1' then
done <= '1';
end if;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | f8c7afa396f1e1a158a29ac966c755be | 0.427732 | 3.187266 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | CSA/8bits/CSA8bits/CSA8bits.vhd | 1 | 2,736 | -- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY CSA8bits IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (7 downto 0);
SomaResult: out std_logic_vector (7 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END CSA8bits ;
ARCHITECTURE strc_CSA8bits OF CSA8bits IS
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL Outs10, Outs11, Outs20, Outs21: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Couts10, Couts11, Couts20, Couts21: STD_LOGIC;
SIGNAL sel1: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SomaT1,SomaT2:STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg8Bit
port(
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
END COMPONENT ;
COMPONENT RCA
port (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (3 downto 0);
SomaResult: out std_logic_vector (3 downto 0);
CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT mux84
port (
In0, In1: in std_logic_vector(3 downto 0);
sel: in std_logic;
Outs : out std_logic_vector(3 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg8Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg8Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg8Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som10: RCA PORT MAP (
val1 => A_sig(3 DOWNTO 0),
val2 => B_sig(3 DOWNTO 0),
CarryIn=>'0',
CarryOut=>Couts10,
SomaResult=>Outs10
);
Som11: RCA PORT MAP (
val1 => A_sig(3 DOWNTO 0),
val2 => B_sig(3 DOWNTO 0),
CarryIn=>'1',
CarryOut=>Couts11,
SomaResult=>Outs11
);
Mux1: mux84 PORT MAP (
In1=>Outs11,
In0=>Outs10,
sel=>Cin_sig,
Outs=>SomaT1
);
sel1 <= Couts10 OR (Couts11 AND Cin_sig);
Som20: RCA PORT MAP (
val1 => A_sig(7 DOWNTO 4),
val2 => B_sig(7 DOWNTO 4),
CarryIn=>'0',
CarryOut=>Couts20,
SomaResult=>Outs20
);
Som21: RCA PORT MAP (
val1 => A_sig(7 DOWNTO 4),
val2 => B_sig(7 DOWNTO 4),
CarryIn=>'1',
CarryOut=>Couts21,
SomaResult=>Outs21
);
Mux2: mux84 PORT MAP (
In1=>Outs21,
In0=>Outs20,
sel=>sel1,
Outs=>SomaT2
);
Cout_sig <= Couts20 OR (Couts21 AND sel1);
Out_sig <= SomaT2 & SomaT1;
END strc_CSA8bits ; | mit | c64a8dd216a0cdc9f8ca1383869005c8 | 0.637061 | 2.566604 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_22.vhd | 4 | 1,435 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_22.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration controller_with_timing of control_section is
for structural
for flag_reg : reg
generic map ( t_setup => 200 ps, t_hold => 150 ps,
t_pd => 150 ps, width => width )
-- workaround for MTI bug mt023
-- port map ( reset_n => '1');
;
-- end workaround
end for;
-- . . .
end for;
end configuration controller_with_timing;
| gpl-2.0 | 913e03a34e6f3b880eadf9c1f01be6a9 | 0.602091 | 4.208211 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd | 4 | 1,736 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp is
port ( terminal positive_supply, negative_supply : electrical;
terminal plus_in, minus_in, output : electrical );
end entity opamp;
----------------------------------------------------------------
architecture saturating of opamp is
constant gain : real := 50.0;
quantity v_pos across positive_supply;
quantity v_neg across negative_supply;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : voltage;
begin
if v_in'above(v_pos / gain) use
v_amplified == v_pos;
elsif not v_in'above(v_neg / gain) use
v_amplified == v_neg;
else
v_amplified == gain * v_in;
end use;
break on v_in'above(v_pos/gain), v_in'above(v_neg/gain);
v_out == v_amplified'slew(1.0e6,-1.0e6);
end architecture saturating;
| gpl-2.0 | 6482caf4ed87cc1604d1f536795560ae | 0.669931 | 3.936508 | false | false | false | false |
tgingold/ghdl | testsuite/synth/mem02/tb_ram6.vhdl | 1 | 700 | entity tb_ram6 is
end tb_ram6;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram6 is
signal val : std_logic_vector(7 downto 0);
signal waddr : std_logic_vector(2 downto 0);
signal wdat : std_logic;
signal clk : std_logic;
begin
dut: entity work.ram6
port map (waddr => waddr, wdat => wdat, val => val,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
waddr <= "000";
wdat <= '0';
pulse;
waddr <= "001";
wdat <= '1';
pulse;
assert (val and x"c0") = x"40" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 2205fecd8e8ad22f6571daac46883d34 | 0.572857 | 3.286385 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1039/ent.vhdl | 1 | 590 | library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity ent is
port (
clk : in std_logic;
addr : in std_logic_vector(2 downto 0);
wr_data : in std_logic_vector(3 downto 0);
rd_data : out std_logic_vector(3 downto 0)
);
end ent;
architecture a of ent is
type ram_type is array (0 to 7) of std_logic_vector(3 downto 0);
signal ram : ram_type := (others => (others => '0'));
begin
process(clk)
begin
if rising_edge(clk) then
ram(to_integer(unsigned(addr))) <= wr_data;
rd_data <= ram(to_integer(unsigned(addr)));
end if;
end process;
end;
| gpl-2.0 | 42862d2923756866de89da950c5eb069 | 0.652542 | 2.718894 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1090.vhd | 4 | 1,979 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1090.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p02n01i01090ent IS
END c06s05b00x00p02n01i01090ent;
ARCHITECTURE c06s05b00x00p02n01i01090arch OF c06s05b00x00p02n01i01090ent IS
BEGIN
TESTING: PROCESS
type I1 is range 0 to 11;
type ABASE is array (I1 range <>) of BOOLEAN;
subtype A1 is ABASE(I1);
variable V1 : A1 ; -- := A1'(others=>TRUE);
BEGIN
V1(5 to 6) := V1(1 to 10)(2 to 9)(3 to 8)(4 to 7)(5 to 6);
assert NOT(V1(5 to 6)=(false,false))
report "***PASSED TEST: c06s05b00x00p02n01i01090"
severity NOTE;
assert (V1(5 to 6)=(false,false))
report "***FAILED TEST: c06s05b00x00p02n01i01090 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01090arch;
| gpl-2.0 | 8b7b15ed5ec7164e9395a6601e51bb86 | 0.656392 | 3.559353 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd | 4 | 2,771 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity bottom is
port ( terminal Tb : electrical; -- ... );
-- not in book
terminal Tz : electrical );
-- end not in book
end entity bottom;
-- end code from book
architecture bottom_arch of bottom is
-- code from book
quantity -- ...
i_b1 through Tb to Tz; -- ...;
quantity -- ...
i_b2 through Tb to Tz; -- ...;
quantity -- ...
i_b3 through Tz to Tb; -- ... to Tb;
quantity -- ...
i_b4 through Tz to Tb; -- ... to Tb;
-- end code from book
begin
assert
-- code from book
Tb'contribution = ( i_b1 + i_b2 ) - ( i_b3 + i_b4 )
-- end code from book
;
end architecture bottom_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity other_ent is
port ( terminal Tx, Tz : electrical );
end entity other_ent;
architecture other_arch of other_ent is
begin
end architecture other_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_03a is
end entity inline_03a;
architecture test of inline_03a is
terminal Ty, Tb, Tx : electrical;
-- code from book
terminal T : electrical;
quantity -- ...
i_t1, i_t2 through T to Ty; -- ...;
quantity -- ...
i_t3 through Ty to T; -- ... to T;
-- ...
-- end code from book
begin
-- code from book
comp1 : entity work.bottom(bottom_arch)
port map ( Tb => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
comp2 : entity work.other_ent(other_arch)
port map ( Tx => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
-- end code from book
assert
-- code from book
T'contribution = ( i_t1 + i_t2 ) - ( i_t3 ) + ( Tb'contribution + Tx'contribution )
-- end code from book
;
end architecture test;
| gpl-2.0 | 5ba64c192a432bb7cea3180acc0fc861 | 0.613497 | 3.770068 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1483.vhd | 4 | 1,827 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1483.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n03i01483ent IS
END c08s08b00x00p04n03i01483ent;
ARCHITECTURE c08s08b00x00p04n03i01483arch OF c08s08b00x00p04n03i01483ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable i : integer := 2;
BEGIN
case i is
when 1 | 2 => k := 5;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n03i01483"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n03i01483 - one alternative can consist of serveral choices"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n03i01483arch;
| gpl-2.0 | f24a673be39f58c06bc38e900442f6c6 | 0.655172 | 3.654 | false | true | false | false |
nickg/nvc | lib/ieee.08/fixed_generic_pkg-body.vhdl | 1 | 216,284 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Fixed-point package (Generic package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point arithmetic
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_generic_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (l = INTEGER'low or r = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (l, r);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (l = INTEGER'low or r = INTEGER'low) then
report fixed_generic_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (l, r);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed
is
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_generic_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed
is
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_generic_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNRESOLVED_UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : UNRESOLVED_SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNRESOLVED_UNSIGNED
is
subtype t is UNRESOLVED_UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return UNRESOLVED_SIGNED
is
subtype t is UNRESOLVED_SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNRESOLVED_UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : UNRESOLVED_SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed
is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed
is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR
is
variable intermediate_result : UNRESOLVED_ufixed(arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
intermediate_result := arg;
return STD_ULOGIC_VECTOR (intermediate_result);
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR
is
variable intermediate_result : UNRESOLVED_sfixed(arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
intermediate_result := arg;
return STD_ULOGIC_VECTOR (intermediate_result);
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_sulv(arg);
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_sulv(arg);
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report fixed_generic_pkg'instance_name & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNRESOLVED_UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report fixed_generic_pkg'instance_name & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => UNRESOLVED_SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : UNRESOLVED_SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed
is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : UNRESOLVED_SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed -- ufixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed -- sfixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
variable result_slv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed -- ufixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed -- sfixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
variable result_slv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed -- ufixed(a+c+1 downto b+d)
is
variable lslv : UNRESOLVED_UNSIGNED (l'length-1 downto 0);
variable rslv : UNRESOLVED_UNSIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed -- sfixed(a+c+1 downto b+d)
is
variable lslv : UNRESOLVED_SIGNED (l'length-1 downto 0);
variable rslv : UNRESOLVED_SIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNRESOLVED_UNSIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report fixed_generic_pkg'instance_name
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
variable rslv : UNRESOLVED_SIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report fixed_generic_pkg'instance_name
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed
is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNRESOLVED_UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report fixed_generic_pkg'instance_name
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(L'high, R'high)+1;
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable cx : UNRESOLVED_UNSIGNED (0 downto 0); -- Carry in
begin
if (L'length < 1 or R'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index-right_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(L'high, R'high)+1;
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_SIGNED (left_index-right_index
downto 0);
variable cx : UNRESOLVED_SIGNED (1 downto 0); -- Carry in
begin
if (L'length < 1 or R'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index-right_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_ufixed (ARG'range);
begin
argslv := to_uns (ARG);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_ufixed (ARG'range);
begin
argslv := to_uns (ARG);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_ufixed (ARG'range);
begin
argslv := to_uns (ARG);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_ufixed (ARG'range);
begin
argslv := to_uns (ARG);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_ufixed (ARG'range);
begin
argslv := to_uns (ARG);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_ufixed (ARG'range);
begin
argslv := to_uns (ARG);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_sfixed (ARG'range);
begin
argslv := to_s (ARG);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_sfixed (ARG'range);
begin
argslv := to_s (ARG);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_sfixed (ARG'range);
begin
argslv := to_s (ARG);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_sfixed (ARG'range);
begin
argslv := to_s (ARG);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_sfixed (ARG'range);
begin
argslv := to_s (ARG);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (ARG'length-1 downto 0);
variable result : UNRESOLVED_sfixed (ARG'range);
begin
argslv := to_s (ARG);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert no_warning
report fixed_generic_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operators
function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
-- End reduction operators
function "?=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?= rslv;
end if;
end function "?=";
function "?/=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?/= rslv;
end if;
end function "?/=";
function "?>" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?> rslv;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?>= rslv;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?< rslv;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?<= rslv;
end if;
end function "?<=";
function "?=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?= rslv;
end if;
end function "?=";
function "?/=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?/= rslv;
end if;
end function "?/=";
function "?>" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?> rslv;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?>= rslv;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?< rslv;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(L'high, R'high);
constant right_index : INTEGER := mins(L'low, R'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((L'length < 1) or (R'length < 1)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (L, left_index, right_index);
rresize := resize (R, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?<= rslv;
end if;
end function "?<=";
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert no_warning
report fixed_generic_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert no_warning
report fixed_generic_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert no_warning
report fixed_generic_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(maximum(to_uns(lresize), to_uns(rresize)),
left_index, right_index);
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(maximum(to_s(lresize), to_s(rresize)),
left_index, right_index);
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(minimum(to_uns(lresize), to_uns(rresize)),
left_index, right_index);
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(minimum(to_s(lresize), to_s(rresize)),
left_index, right_index);
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert no_warning
report fixed_generic_pkg'instance_name
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert no_warning
report fixed_generic_pkg'instance_name
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report fixed_generic_pkg'instance_name
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert no_warning report fixed_generic_pkg'instance_name
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert no_warning report fixed_generic_pkg'instance_name
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is arg;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNRESOLVED_UNSIGNED) -- unsigned
return UNRESOLVED_ufixed
is
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is arg;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(XARG);
end function to_ufixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is arg;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : UNRESOLVED_SIGNED) -- signed
return UNRESOLVED_sfixed
is
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is arg;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(XARG);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_generic_pkg'instance_name
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_generic_pkg'instance_name
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNRESOLVED_UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : UNRESOLVED_SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := To_X01(cleanvec(arg));
if (Is_X(arg_int)) then
assert no_warning
report fixed_generic_pkg'instance_name
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_X01(cleanvec(arg));
if (Is_X(arg_int)) then
assert no_warning
report fixed_generic_pkg'instance_name
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL
is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNRESOLVED_UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert no_warning
report fixed_generic_pkg'instance_name
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER
is
constant left_index : INTEGER := arg'high;
variable arg_s : UNRESOLVED_SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert no_warning
report fixed_generic_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed
is
begin
if (s'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed
is
begin
if (s'length < 1) then
assert no_warning
report fixed_generic_pkg'instance_name
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN
is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN
is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function to_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function to_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function to_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?= to_ufixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?/= to_ufixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?>= to_ufixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?<= to_ufixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?> to_ufixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?< to_ufixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?= to_ufixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?/= to_ufixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?>= to_ufixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?<= to_ufixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?> to_ufixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?< to_ufixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?= to_sfixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?/= to_sfixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?>= to_sfixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?<= to_sfixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?> to_sfixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?< to_sfixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?= to_sfixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?/= to_sfixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?>= to_sfixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?<= to_sfixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?> to_sfixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?< to_sfixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable c : CHARACTER;
variable left : positive;
begin
while L /= null and L.all'length /= 0 loop
left := L.all'left;
c := L.all(left);
if (c = ' ' or c = NBSP or c = HT) then
read (L, c);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in VALUE'high downto VALUE'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
write(L, s, JUSTIFIED, FIELD);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in VALUE'high downto VALUE'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
write(L, s, JUSTIFIED, FIELD);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (L, c, readOk);
i := VALUE'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = VALUE'high then
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, readOk);
i := VALUE'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = VALUE'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (L, c, readOk);
i := VALUE'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = VALUE'high then
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => TO_OSTRING (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => TO_OSTRING (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case C is
when '0' => RESULT := o"0"; GOOD := true;
when '1' => RESULT := o"1"; GOOD := true;
when '2' => RESULT := o"2"; GOOD := true;
when '3' => RESULT := o"3"; GOOD := true;
when '4' => RESULT := o"4"; GOOD := true;
when '5' => RESULT := o"5"; GOOD := true;
when '6' => RESULT := o"6"; GOOD := true;
when '7' => RESULT := o"7"; GOOD := true;
when 'Z' => RESULT := "ZZZ"; GOOD := true;
when 'X' => RESULT := "XXX"; GOOD := true;
when others =>
assert not ISSUE_ERROR
report fixed_generic_pkg'instance_name
& "OREAD Error: Read a '" & C &
"', expected an Octal character (0-7)."
severity error;
RESULT := "UUU";
GOOD := false;
end case;
end procedure Char2TriBits;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_generic_pkg'instance_name
& "OREAD(sfixed) "
& mess
severity error;
else
report fixed_generic_pkg'instance_name
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (L, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2TriBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_generic_pkg'instance_name
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert no_warning
report fixed_generic_pkg'instance_name
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
GOOD := true;
else
GOOD := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_generic_pkg'instance_name
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert no_warning
report fixed_generic_pkg'instance_name
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
GOOD := true;
else
GOOD := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => TO_HSTRING (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => TO_HSTRING (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case C is
when '0' => RESULT := x"0"; GOOD := true;
when '1' => RESULT := x"1"; GOOD := true;
when '2' => RESULT := x"2"; GOOD := true;
when '3' => RESULT := x"3"; GOOD := true;
when '4' => RESULT := x"4"; GOOD := true;
when '5' => RESULT := x"5"; GOOD := true;
when '6' => RESULT := x"6"; GOOD := true;
when '7' => RESULT := x"7"; GOOD := true;
when '8' => RESULT := x"8"; GOOD := true;
when '9' => RESULT := x"9"; GOOD := true;
when 'A' | 'a' => RESULT := x"A"; GOOD := true;
when 'B' | 'b' => RESULT := x"B"; GOOD := true;
when 'C' | 'c' => RESULT := x"C"; GOOD := true;
when 'D' | 'd' => RESULT := x"D"; GOOD := true;
when 'E' | 'e' => RESULT := x"E"; GOOD := true;
when 'F' | 'f' => RESULT := x"F"; GOOD := true;
when 'Z' => RESULT := "ZZZZ"; GOOD := true;
when 'X' => RESULT := "XXXX"; GOOD := true;
when others =>
assert not ISSUE_ERROR
report fixed_generic_pkg'instance_name
& "HREAD Error: Read a '" & C &
"', expected a Hex character (0-F)."
severity error;
RESULT := "UUUU";
GOOD := false;
end case;
end procedure Char2QuadBits;
-- purpose: Routines common to the HREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_generic_pkg'instance_name
& "HREAD(sfixed) "
& mess
severity error;
else
report fixed_generic_pkg'instance_name
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (L, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_generic_pkg'instance_name
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert no_warning
report fixed_generic_pkg'instance_name
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
GOOD := true;
else
GOOD := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_generic_pkg'instance_name
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert no_warning
report fixed_generic_pkg'instance_name
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
GOOD := true;
else
GOOD := false;
end if;
end procedure HREAD;
-- TO_STRING functions. Useful in "report" statements.
-- Example: report "result was " & TO_STRING(result);
function TO_STRING (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return TO_STRING (resize (sfixed(value), 0, value'low));
else
return TO_STRING (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return TO_STRING(subval);
else
return TO_STRING (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function TO_STRING;
function TO_STRING (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return TO_STRING (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return TO_STRING(subval);
else
return TO_STRING (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function TO_STRING;
function TO_OSTRING (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-value'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + value'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return TO_OSTRING (resize (sfixed(value), 2, value'low));
else
return TO_OSTRING (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return TO_OSTRING(subval);
else
return TO_OSTRING (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return TO_OSTRING(slv(slv'high downto slv'high-value'high))
& "."
& TO_OSTRING(slv(slv'high-value'high-1 downto 0) & lpad);
end if;
end if;
end function TO_OSTRING;
function TO_HSTRING (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-value'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + value'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return TO_HSTRING (resize (sfixed(value), 3, value'low));
else
return TO_HSTRING (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return TO_HSTRING(subval);
else
return TO_HSTRING (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return TO_HSTRING(slv(slv'high downto slv'high-value'high))
& "."
& TO_HSTRING(slv(slv'high-value'high-1 downto 0)&lpad);
end if;
end if;
end function TO_HSTRING;
function TO_OSTRING (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-value'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + value'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'high - value'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return TO_OSTRING (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return TO_OSTRING(subval);
else
return TO_OSTRING (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return TO_OSTRING(pad & slv(slv'high downto slv'high-value'high))
& "."
& TO_OSTRING(slv(slv'high-value'high-1 downto 0) & lpad);
end if;
end if;
end function TO_OSTRING;
function TO_HSTRING (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-value'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + value'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return TO_HSTRING (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return TO_HSTRING(subval);
else
return TO_HSTRING (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return TO_HSTRING(pad & slv(slv'high downto slv'high-value'high))
& "."
& TO_HSTRING(slv(slv'high-value'high-1 downto 0) & lpad);
end if;
end if;
end function TO_HSTRING;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report fixed_generic_pkg'instance_name
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report fixed_generic_pkg'instance_name
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
end package body fixed_generic_pkg;
| gpl-3.0 | 67c3929da1b1f1b9007243f7d3830966 | 0.563375 | 3.978734 | false | false | false | false |
nickg/nvc | test/regress/gentype3.vhd | 1 | 2,668 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
type T;
DEPTH : positive );
port (
clk : in std_logic;
pop : in std_logic;
push : in std_logic;
full : out std_logic;
valid : out std_logic;
din : in T;
dout : out T );
end entity;
architecture test of fifo is
type fifo_data_t is array (0 to DEPTH - 1) of T;
signal wptr, rptr : natural := 1;
signal data : fifo_data_t;
begin
full <= '1' when (wptr + 1) mod DEPTH = rptr else '0';
valid <= '1' when wptr /= rptr else '0';
dout <= data(rptr);
behav: process (clk) is
begin
if rising_edge(clk) then
if push = '1' then
assert full = '0';
data(wptr) <= din;
wptr <= (wptr + 1) mod DEPTH;
end if;
if pop = '1' then
assert valid = '1';
rptr <= (rptr + 1) mod DEPTH;
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity gentype3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of gentype3 is
signal clk : std_logic;
signal pop : std_logic;
signal push : std_logic;
signal din : std_logic_vector(7 downto 0);
signal dout : std_logic_vector(7 downto 0);
signal full : std_logic;
signal valid : std_logic;
procedure pulse (signal clk : out std_logic) is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end procedure;
begin
u: entity work.fifo
generic map ( T => std_logic_vector(7 downto 0), depth => 4 )
port map (
clk => clk,
pop => pop,
push => push,
din => din,
dout => dout,
full => full,
valid => valid );
main: process is
begin
wait for 1 ns;
assert full = '0';
assert valid = '0';
din <= X"05";
push <= '1';
pulse(clk);
assert full = '0';
assert valid = '1';
assert dout = X"05";
din <= X"07";
pulse(clk);
assert full = '0';
assert valid = '1';
assert dout = X"05";
push <= '0';
pop <= '1';
pulse(clk);
assert full = '0';
assert valid = '1';
assert dout = X"07";
pulse(clk);
assert full = '0';
assert valid = '0';
wait;
end process;
end architecture;
| gpl-3.0 | ed750ae2bf88228f43cd15ba8bf79e01 | 0.463268 | 3.805991 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1728.vhd | 4 | 1,800 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1728.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p02n01i01728ent IS
END c09s03b00x00p02n01i01728ent;
ARCHITECTURE c09s03b00x00p02n01i01728arch OF c09s03b00x00p02n01i01728ent IS
procedure check (x: in integer; y: in boolean) is
begin
assert NOT( x=3 and y=true )
report "***PASSED TEST: c09s03b00x00p02n01i01728"
severity NOTE;
assert ( x=3 and y=true )
report "***FAILED TEST: c09s03b00x00p02n01i01728 - Procedure call statement syntax diagram did not pass."
severity ERROR;
end;
signal p: integer := 3;
signal q: boolean := true;
BEGIN
check (p,q); -- No_failure_here
END c09s03b00x00p02n01i01728arch;
| gpl-2.0 | def5da33fd27c523538ae8f650bda1a3 | 0.668889 | 3.6 | false | true | false | false |
nickg/nvc | test/regress/agg8.vhd | 1 | 644 | entity agg8 is
end entity;
architecture test of agg8 is
type rec is record
x : integer;
y : bit_vector;
end record;
type rec_array is array (natural range <>) of rec;
signal s : rec(y(1 to 3)) := ( 1, "101" );
signal t : rec_array(1 to 2)(y(1 to 3));
begin
p1: process is
variable v : t'subtype;
begin
t <= (others => s);
wait for 1 ns;
assert t(2).x = 1;
assert t(1).y = "101";
t(2) <= (2, "110");
wait for 1 ns;
v := t;
assert v(1).x = 1;
assert v(2).y = "110";
wait;
end process;
end architecture;
| gpl-3.0 | b130ea9fea869b1fdb5abff545b214d6 | 0.486025 | 3.236181 | false | false | false | false |
nickg/nvc | test/sem/attr.vhd | 1 | 6,745 | entity e is
end entity;
architecture a1 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of x : signal is 6; -- OK
attribute bar of y : signal is "hello"; -- OK
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
signal i : int_vec(1 to 3);
attribute foo of i : signal is 6; -- OK
begin
process is
variable v : integer;
begin
v := x'foo; -- OK
report y'bar; -- OK
end process;
process is
begin
report z'foo; -- Error
end process;
process is
variable v : int_vec_ptr;
begin
assert v'length = 5; -- OK
assert v.all'length = 62; -- OK
end process;
process is
begin
report e'path_name; -- OK
report e'instance_name; -- OK
report a1'path_name; -- OK
report a1'instance_name; -- OK
end process;
process is
begin
assert i'event; -- OK
assert i(1)'event; -- OK
assert i(x)'event; -- OK
assert i'foo = 1; -- OK
assert i(1)'foo = 2; -- Error
end process;
end architecture;
architecture a2 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of z : signal is string'("boo"); -- Error
attribute bar of x : signal is 73; -- Error
attribute foo of q : signal is 71; -- Error
attribute foo of yah : label is 12; -- Ignored
begin
end architecture;
architecture a3 of e is
type int10_vec is array (integer range 1 to 10) of integer;
begin
process is
variable x : integer;
begin
assert int10_vec'low = 1; -- OK
assert int10_vec'high = 10; -- OK
assert int10_vec'left = 1; -- OK
assert int10_vec'right = 10; -- OK
assert int10_vec'low(1) = 1; -- OK
assert int10_vec'left(x) = 2; -- Error
end process;
end architecture;
package pack is
function func(x : in integer) return integer;
attribute p : POSITIVE;
attribute p of pack : package is 10; -- OK
end package;
package body pack is
function func(x : in integer) return integer is
begin
report func'instance_name; -- OK
report x'simple_name; -- OK
report true'simple_name; -- Error
report pack'path_name; -- OK
report integer'path_name; -- Error
return x + 1;
end function;
end package body;
entity issue39 is
generic (
g : bit := '0'
);
begin
assert (g = '0' or g = '1')
report issue39'instance_name & "oops!"
severity failure;
end entity issue39;
architecture a4 of e is
begin
process is
begin
assert integer'image(0)(0) = '0'; -- OK
end process;
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
attribute b : integer;
attribute b of i : variable is 4;
begin
assert i'a(1) = '0'; -- OK
assert i'b(1) = 1; -- Error
end process;
process is
variable i : integer;
attribute a : boolean;
attribute a of i : signal is true; -- Error
begin
end process;
process is
variable x : integer;
begin
assert x'last_event = 0 ns; -- Error
end process;
process is
type bv_ptr is access bit_vector;
variable a : bv_ptr;
type r is record
x : integer;
end record;
variable b : r;
begin
a(a'range) := "110101"; -- OK
a(bit_vector'range) := "110101"; -- Error
a(b'range) := "101010"; -- Error
a(e'range) := "110101"; -- Error
end process;
process is
function func(x : integer) return bit_vector;
variable a : bit_vector(1 to 10);
begin
a(func(4)'range) := (others => '1'); -- OK
end process;
process is
type bvptr is access bit_vector;
variable b : bvptr;
begin
for i in b.all'range loop -- OK
end loop;
for i in b'range loop -- OK
end loop;
end process;
b1: block is
function fie return string is
begin
return "11010011";
end function;
function fie2(x : integer := 4) return string is
begin
-- report fie2'instance_name; ???
return "101";
end function;
begin
process
begin
assert fie'RIGHT = 1; -- OK
assert fie2'RIGHT = 1; -- OK
end process;
end block;
process
type int2_vec is array (66 to 67) of integer;
variable b : boolean;
variable x : int2_vec;
begin
b := a4'length = 5; -- Error
b := x'length = 5; -- OK
b := x'low(1) = 1; -- OK
b := x'high(1) = 5; -- OK
b := x'left = 1; -- OK
b := x'right = 5; -- OK
b := int2_vec'length = 2; -- OK
b := int2_vec'low = 66; -- OK
report int2_vec'image(x); -- Error
end process;
process is
subtype my_int is integer range 1 to 20;
subtype my_bool is boolean range true to true;
variable x : integer;
begin
assert my_int'base'left = 1; -- OK
assert x'base'left = 2; -- Error
assert my_int'base = 5; -- Error
assert my_bool'base'pos(true) = 1; -- OK
report my_bool'base'image(true); -- OK
end process;
end architecture;
use work.pack.all;
entity tc3109 is
attribute p of tc3109 : entity is 20; -- OK
end tc3109;
architecture tc3109arch of tc3109 is
attribute p of tc3109arch : architecture is 30; -- OK
begin
testing: process
begin
assert not( tc3109'p = 20 and -- OK
tc3109arch'p = 30 ); -- OK
assert ( tc3109'p = 20 and -- OK
tc3109arch'p = 30 ); -- OK
wait;
end process testing;
end;
ARCHITECTURE c07s04b01x00p08n01i02565arch OF e IS
SUBTYPE s10 IS STRING (1 TO 4);
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF s10 : SUBTYPE IS 4; -- OK
begin
TESTING: PROCESS
VARIABLE v : s10;
BEGIN
v := (1 | s10'attr1 => 'a', OTHERS => 'b' ); -- OK
wait for 5 ns;
wait;
END PROCESS TESTING;
END c07s04b01x00p08n01i02565arch;
| gpl-3.0 | c5bd69cafd20ffe8b0378eea59bb0dce | 0.515641 | 3.768156 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/output_split0.vhd | 2 | 1,410 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split0 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split0;
architecture augh of output_split0 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | ad638821692f5f6290b8b38abc809346 | 0.673759 | 2.895277 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket94/tb2.vhd | 2 | 518 |
library ieee;
use ieee.std_logic_1164.all;
library alib;
use alib.acomp;
entity tb2 is
end;
architecture arch of tb2 is
signal a, b : std_logic := '0';
begin
ainst: alib.apkg.acomp
port map (a, b);
process is
begin
a <= '0';
wait for 1 ns;
assert b = '0' report "component is missing" severity failure;
a <= '1';
wait for 1 ns;
assert b = '1' report "component is missing" severity failure;
wait;
end process;
end architecture;
| gpl-2.0 | 2f6a0dcf06bfb526cd95535f0ca8cd8d | 0.584942 | 3.430464 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_05.vhd | 4 | 2,320 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_05 is
end entity fg_a_05;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_05 is
signal clk, reset, a, b, x, q : std_ulogic;
begin
-- code from book
ff2 : process (reset, clk) is
begin
if reset = '1' then
q <= '0';
elsif rising_edge(clk) then
if x = '1' then
q <= a;
else
q <= b;
end if;
end if;
end process ff2;
-- end code from book
stimulus : process is
begin
reset <= '0'; clk <= '0'; x <= '1'; a <= '1'; b <= '0'; wait for 10 ns;
reset <= '1', '0' after 30 ns;
clk <= '1' after 10 ns, '0' after 20 ns;
wait for 40 ns;
clk <= '1', '0' after 2 ns,
'1' after 12 ns, '0' after 14 ns,
'1' after 17 ns, '0' after 19 ns,
'1' after 22 ns, '0' after 24 ns,
'1' after 27 ns, '0' after 29 ns,
'1' after 32 ns, '0' after 34 ns,
'1' after 37 ns, '0' after 39 ns,
'1' after 42 ns, '0' after 44 ns,
'1' after 47 ns, '0' after 49 ns;
a <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
b <= '0' after 15 ns, '1' after 25 ns, '0' after 35 ns, '1' after 45 ns;
x <= '0' after 30 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | f2cb21d7a13d9e335d88eef466b48a1b | 0.556466 | 3.352601 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_s2mm_basic_wrap.vhd | 7 | 49,604 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_reset;
use axi_sg_v4_1_2.axi_sg_cmd_status;
use axi_sg_v4_1_2.axi_sg_scc_wr;
use axi_sg_v4_1_2.axi_sg_addr_cntl;
use axi_sg_v4_1_2.axi_sg_wrdata_cntl;
use axi_sg_v4_1_2.axi_sg_wr_status_cntl;
Use axi_sg_v4_1_2.axi_sg_skid2mm_buf;
Use axi_sg_v4_1_2.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0); --
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_sg_s2mm_basic_wrap;
architecture implementation of axi_sg_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := 1;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_2.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_2.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_sg_v4_1_2.axi_sg_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_2.axi_sg_scc_wr
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_2.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_S2MM_STRM_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => S2MM_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => s2mm_aclk ,
-- arst => sig_mmap_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => s2mm_strm_wvalid ,
-- s_ready => s2mm_strm_wready ,
-- s_data => s2mm_strm_wdata ,
-- s_strb => s2mm_strm_wstrb ,
-- s_last => s2mm_strm_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => skid2wdc_wvalid ,
-- m_ready => wdc2skid_wready ,
-- m_data => skid2wdc_wdata ,
-- m_strb => skid2wdc_wstrb ,
-- m_last => skid2wdc_wlast
--
-- );
--
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_sg_v4_1_2.axi_sg_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_skid2axi_wdata,-- sig_data2skid_wdata ,
data2skid_wstrb => sig_skid2axi_wstrb,-- sig_data2skid_wstrb ,
data2skid_wlast => sig_skid2axi_wlast,-- sig_data2skid_wlast ,
data2skid_wvalid => sig_skid2axi_wvalid,-- sig_data2skid_wvalid ,
skid2data_wready => sig_axi2skid_wready,-- sig_skid2data_wready ,
s2mm_strm_wvalid => s2mm_strm_wvalid, --skid2wdc_wvalid ,
s2mm_strm_wready => s2mm_strm_wready, --wdc2skid_wready ,
s2mm_strm_wdata => s2mm_strm_wdata, --skid2wdc_wdata ,
s2mm_strm_wstrb => s2mm_strm_wstrb, --skid2wdc_wstrb ,
s2mm_strm_wlast => s2mm_strm_wlast, --skid2wdc_wlast ,
s2mm_strm_eop => s2mm_strm_wlast, --skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
-- I_S2MM_MMAP_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid2mm_buf
-- generic map (
--
-- C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
-- C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
-- C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- ACLK => s2mm_aclk ,
-- ARST => sig_stream_rst ,
--
-- -- Slave Side (Wr Data Controller Input Side )
-- S_ADDR_LSB => sig_data2skid_addr_lsb,
-- S_VALID => sig_data2skid_wvalid ,
-- S_READY => sig_skid2data_wready ,
-- S_Data => sig_data2skid_wdata ,
-- S_STRB => sig_data2skid_wstrb ,
-- S_Last => sig_data2skid_wlast ,
--
-- -- Master Side (MMap Write Data Output Side)
-- M_VALID => sig_skid2axi_wvalid ,
-- M_READY => sig_axi2skid_wready ,
-- M_Data => sig_skid2axi_wdata ,
-- M_STRB => sig_skid2axi_wstrb ,
-- M_Last => sig_skid2axi_wlast
--
-- );
--
end implementation;
| gpl-3.0 | 19d37ad1375ce4ce0d6da50dc13d03e1 | 0.439702 | 4.066235 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug23165/mwe_working/counter.vhd | 6 | 598 | -- counter
-- clk: clock input
-- en: enable input
-- rst: reset input
-- dir: direction pin (1 = up, 0 = down)
-- q: output
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic (
width : positive := 16
);
port (
clk : in std_logic;
q : out std_logic_vector(width-1 downto 0)
);
end counter;
architecture behav of counter is
signal cnt : unsigned(width-1 downto 0) := to_unsigned(0, width);
begin
process
begin
wait until rising_edge(clk);
cnt <= cnt + to_unsigned(1, cnt'length);
end process;
q <= std_logic_vector(cnt);
end behav;
| gpl-2.0 | fbaa2bed559e23112ff25d440978cb93 | 0.667224 | 2.834123 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1787.vhd | 4 | 6,100 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1787.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c09s06b00x00p04n05i01787ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end c09s06b00x00p04n05i01787ent_a;
architecture c09s06b00x00p04n05i01787arch_a of c09s06b00x00p04n05i01787ent_a is
begin
port0 <= g0 after 11 ns;
port1 <= g1 after 11 ns;
port2 <= g2 after 11 ns;
port3 <= g3 after 11 ns;
port4 <= g4 after 11 ns;
port5 <= g5 after 11 ns;
port6 <= g6 after 11 ns;
port7 <= g7 after 11 ns;
port8 <= g8 after 11 ns;
port9 <= g9 after 11 ns;
portA <= gA after 11 ns;
end c09s06b00x00p04n05i01787arch_a;
ENTITY c09s06b00x00p04n05i01787ent IS
END c09s06b00x00p04n05i01787ent;
ARCHITECTURE c09s06b00x00p04n05i01787arch OF c09s06b00x00p04n05i01787ent IS
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01787ent_a(c09s06b00x00p04n05i01787arch_a);
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
signal signal0 : Boolean ;
signal signal1 : Bit ;
signal signal2 : Character ;
signal signal3 : SEVERITY_LEVEL ;
signal signal4 : Integer ;
signal signal5 : Real ;
signal signal6 : TIME ;
signal signal7 : Natural ;
signal signal8 : Positive ;
signal signal9 : String16 ;
signal signalA : Reg32 ;
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100"
)
port map (
signal0 ,
signal1 ,
signal2 ,
signal3 ,
signal4 ,
signal5 ,
signal6 ,
signal7 ,
signal8 ,
signal9 ,
signalA
);
TESTING: PROCESS
BEGIN
wait on signal0,signal1,signal2,signal3,signal4,signal5,signal6,signal7,signal8;
assert NOT( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***PASSED TEST: c09s06b00x00p04n05i01787"
severity NOTE;
assert ( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***FAILED TEST: c09s06b00x00p04n05i01787 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s06b00x00p04n05i01787arch;
| gpl-2.0 | f000d0835d0dc2abd79324d2db6fc2ca | 0.515738 | 3.751538 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue616/mwe.vhdl | 1 | 1,470 | library ieee;
use ieee.std_logic_1164.all;
entity mwe is
generic (
wait_us : integer := 400;
clk_period : time := 10 ns
);
end entity;
architecture sim of mwe is
signal clk : std_logic := '0';
signal runsim : boolean := true;
function slv_all(constant width : in integer; constant value : in std_logic) return std_logic_vector is
variable slv_v : std_logic_vector(width - 1 downto 0) := (others => value);
begin
return slv_v;
end function;
function slv_ones(constant width : in integer) return std_logic_vector is
begin
return slv_all(width, '1');
end function;
begin
p_clk: process
begin
while runsim loop
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end loop;
wait;
end process;
p_check_requests: process
function return_true return boolean is
constant ones_c : std_logic_vector(31 downto 0) := slv_ones(32);
begin
return true;
end function;
variable ones_v : std_logic_vector(31 downto 0);
variable result_v : boolean;
begin
wait until rising_edge(clk);
while runsim loop
wait until rising_edge(clk);
result_v := return_true;
-- uncommenting the following lines speeds up the design
-- ones_v := slv_ones(32);
end loop;
wait;
end process;
p_main: process
begin
wait for wait_us * 1 us;
runsim <= false;
wait;
end process;
end architecture;
| gpl-2.0 | 98a976710b82f6cf8874aee7b46937ff | 0.627891 | 3.602941 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd | 4 | 2,032 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
-- code from book:
disconnect address_bus : resolved_word after 3 ns;
disconnect others : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | cd91d62fe7d2dbe45717158fcf6bbb3d | 0.662402 | 3.976517 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1529.vhd | 4 | 2,494 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1529.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01529ent IS
END c08s09b00x00p08n01i01529ent;
ARCHITECTURE c08s09b00x00p08n01i01529arch OF c08s09b00x00p08n01i01529ent IS
BEGIN
TESTING: PROCESS
variable INTV : INTEGER := 0;
variable COUNTV : INTEGER := 0;
variable I : INTEGER := 0;
variable k : integer := 0;
BEGIN
-- While condition is FALSE, so no stmts are executed.
while (FALSE) loop
assert (FALSE)
report "First loop was executed when it should not have been.";
k := 1;
end loop;
-- While condition is FALSE, so no stmts are executed.
while (I /= 0) loop
assert (FALSE)
report "Second loop was executed when it should not have been.";
k := 1;
end loop;
-- Verify that loop is executed right number of times.
COUNTV := 0;
while (I /= 10) loop
I := I + 1;
COUNTV := COUNTV + 1;
end loop;
if (I /= 10 and COUNTV /= 10) then
k := 1;
end if;
assert (I = 10);
assert (COUNTV = 10);
assert NOT(k=0)
report "***PASSED TEST: c08s09b00x00p08n01i01529"
severity NOTE;
assert (k=0)
report "***FAILED TEST: c08s09b00x00p08n01i01529 - while condition is not boolean expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01529arch;
| gpl-2.0 | 8cec08fdb4d17b901f490c510f4b7c7b | 0.632719 | 3.71131 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc3131.vhd | 4 | 2,473 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3131.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p12n01i03131ent_a IS
generic ( g1 : boolean := false );
END c05s02b01x02p12n01i03131ent_a;
ARCHITECTURE c05s02b01x02p12n01i03131arch_a OF c05s02b01x02p12n01i03131ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert g1 report "g1=false" severity FAILURE;
assert NOT( g1 = true )
report "***PASSED TEST: c05s02b01x02p12n01i03131"
severity NOTE;
assert ( g1 = true )
report "***FAILED TEST: c05s02b01x02p12n01i03131 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p12n01i03131arch_a;
ENTITY c05s02b01x02p12n01i03131ent IS
END c05s02b01x02p12n01i03131ent;
ARCHITECTURE c05s02b01x02p12n01i03131arch OF c05s02b01x02p12n01i03131ent IS
BEGIN
labeled : block
component ic_socket
generic ( local_g1 : Boolean := true );
end component;
for instance : ic_socket use entity work .c05s02b01x02p12n01i03131ent_a (c05s02b01x02p12n01i03131arch_a)
generic map ( true );
begin
instance : ic_socket;
end block;
END c05s02b01x02p12n01i03131arch;
configuration c05s02b01x02p12n01i03131cfg of c05s02b01x02p12n01i03131ent is
for c05s02b01x02p12n01i03131arch
end for;
end c05s02b01x02p12n01i03131cfg;
| gpl-2.0 | 429adb9afbe17465ae98e19057e0f4be | 0.704812 | 3.292943 | false | true | false | false |
nickg/nvc | test/regress/wait18.vhd | 1 | 580 | entity wait18 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of wait18 is
signal clk, d, q : std_logic := '0';
begin
process (clk) is
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
process is
begin
clk <= '1' after 10 ns;
d <= '1';
wait for 11 ns;
assert q = '1';
wait;
end process;
postponed process (clk) is
begin
if rising_edge(clk) then
assert q = '1';
end if;
end process;
end architecture;
| gpl-3.0 | 440c22e45242196472069629f902c702 | 0.525862 | 3.625 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd | 4 | 1,970 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity bv_lt is
end entity bv_lt;
architecture test of bv_lt is
-- code from book
procedure bv_lt ( bv1, bv2 : in bit_vector; result : out boolean ) is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
result := tmp1 < tmp2;
end procedure bv_lt;
-- end code from book
begin
stimulus : process is
subtype byte is bit_vector(0 to 7);
variable result : boolean;
begin
bv_lt( byte'(X"02"), byte'(X"04"), result );
assert result;
bv_lt( byte'(X"02"), byte'(X"02"), result );
assert not result;
bv_lt( byte'(X"02"), byte'(X"02"), result );
assert not result;
bv_lt( byte'(X"FC"), byte'(X"04"), result );
assert result;
bv_lt( byte'(X"04"), byte'(X"FC"), result );
assert not result;
bv_lt( byte'(X"FC"), byte'(X"FC"), result );
assert not result;
bv_lt( byte'(X"FC"), byte'(X"FE"), result );
assert result;
bv_lt( byte'(X"FE"), byte'(X"FC"), result );
assert not result;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 7b36264005c2b420ce334a7fc9a606bc | 0.652792 | 3.474427 | false | false | false | false |
nickg/nvc | test/sem/func.vhd | 1 | 8,301 | package func is
function sum(x, y, z : in integer) return integer;
function invalid(x : out integer) return integer; -- Error
type uenum is (A, B, C);
type uenum_vector is array (integer range <>) of uenum;
function resolved(v : uenum_vector) return uenum;
subtype enum is resolved uenum;
subtype enum_ab is resolved uenum range A to B;
function resolved2(v : uenum) return uenum;
subtype enum_bad1 is resolved2 uenum; -- Error
function resolved3(v : uenum; x : integer) return uenum;
subtype enum_bad2 is resolved3 uenum; -- Error
subtype enum_bad3 is uenum uenum; -- Error
function default(x : in uenum := 6) return uenum; -- Error
function foo return integer is -- Error
begin
return 4;
end function;
end package;
package body bad is -- Error
end package body;
package body func is
function sum(x, y, z : in integer) return integer is
begin
return x + y; -- OK
end function;
function test1(x : integer) return integer is
begin
return A; -- Wrong return type
end function;
function test2(x : out integer) return integer is -- Invalid mode
begin
return 0;
end function;
function test3(x : integer) return integer is
begin
null; -- Missing return statement
end function;
function foo(x, y, z : in integer) return integer;
function foo(x, y, z : in integer) return integer; -- Duplicate
function test4(x : uenum_vector) return uenum is
begin
return x(x'low);
end function;
function test5(x, y : uenum) return uenum is
type uenum2d is array (uenum, uenum) of uenum;
constant table : uenum2d :=
( ( A, A, A ),
( A, B, C ),
( A, C, B ) );
begin
return table(x, y);
end function;
function test6(x : uenum_vector) return uenum_vector is
variable tmp : uenum_vector(1 to x'length);
begin
for i in tmp'range loop
tmp(i) := A;
end loop;
return tmp;
end function;
function test7(x : uenum_vector) return uenum_vector is
subtype rtype is uenum_vector(x'length downto 0);
variable r : rtype;
begin
return r;
end function;
function test8(x : uenum) return uenum_vector is
begin
return test7((1 to 3 => x));
end function;
function default2(y : in integer := 6) return integer is
begin
return y * 2;
end function;
function test9 return integer is
begin
return default2;
end function;
function test10(k : in integer) return integer is
variable v : integer;
variable u : uenum;
begin
v := sum(x => 4, 1, 2); -- Error
v := sum(1, x => 4, x => 4); -- Error
v := sum(1, y => k, z => 4); -- OK
u := resolved3(A, x => 4); -- OK
u := resolved3(x => 3, v => B); -- OK
return v;
end function;
function test11(constant c : in bit) return bit; -- OK
function test12(variable v : in bit) return bit; -- Error
type ft is file of bit;
function test13(file f : ft) return bit; -- OK
function test14(signal s : bit) return bit; -- OK
procedure modify(variable b : inout bit) is
begin
b := '1';
end procedure;
function test15(file f : ft) return bit is
variable b : bit;
begin
read(f, b); -- OK
return b;
end function;
function test16(x : in bit) return bit is
begin
modify(x); -- Error
return x;
end function;
impure function test17(x : in bit) return bit is
begin
if now = 10 ns then
return '1';
else
return '0';
end if;
end function;
function test18(x : in bit) return bit is
begin
return not test17(x); -- Error, test18 not impure
end function;
type int_ptr is access integer;
function test19(x : in int_ptr) return integer; -- Error
function recur(x : in integer) return integer is
begin
if x = 0 then
return 1;
else
return x * recur(x - 1);
end if;
end function;
function test20(x : integer := 5; y : real) return integer is
variable k : integer;
begin
k := test20(6.5); -- Error
k := test20(5); -- Error
k := test20(y => 7); -- Error
return k;
end function;
function test21a(x : string) return integer;
function test21a(x : bit_vector) return integer;
function test21 return integer is
begin
return test21a(';' & LF); -- OK
end function;
function test22a(x : integer) return integer is
begin
return x + 1;
end function;
function test22a(x : integer) return real is
begin
return real(x) + 1.0;
end function;
function test22 return integer is
begin
assert test22a(1) = 2; -- OK
assert test22a(1) = 2.0; -- OK
return 1;
end function;
impure function test23 return integer is
variable x : integer;
impure function sub(y : in integer) return integer is
begin
return x + y;
end function;
begin
x := 5;
return sub(2);
end function;
function test24f(x : integer; r : real := 1.0) return integer;
function test24f(y : integer; b : boolean := true) return integer;
function test24 return integer is
begin
return test24f(x => 1) + test24f(y => 2);
end function;
end package body;
package func2 is
procedure test25(constant x : integer);
end package;
package body func2 is
procedure test25(variable x : integer) is -- Error
begin
end procedure;
function test26(signal x : integer) return integer;
function test26(x : integer) return integer is -- Error
begin
return 1;
end function;
end package body;
package func3 is
end package;
package body func3 is
-- default class should be treated identically to constant class
-- (ie, this should not produce an error)
function issue182(bitv : bit_vector) return integer is
function nested_fun return integer is
begin
return bitv'length; -- OK
end function;
begin
return nested_fun;
end function;
function issue123(signal x : integer) return integer is
function nested return integer is
begin
return x + 1; -- Error
end function;
begin
return nested;
end function;
function constpure(x : integer) return integer is
function nested return integer is
begin
return x + 1; -- OK
end function;
begin
return nested;
end function;
procedure notdef(x : integer) is
begin
fnork(x + 1); -- Error
end procedure;
procedure not_a_procedure is
begin
constpure(1); -- Error
assert notdef(2) = 1; -- Error
end procedure;
constant bad_c : bad_type := foo; -- Error
function bad_param ( constant x : bad_type := bad_c ) return bad_type; -- Error
function func1 (x : integer) return integer;
function func1 (x : integer := 2) return integer is -- Error
begin
return 1;
end function;
function func2 (x : integer := 1) return integer;
function func2 (x : integer := 2) return integer is -- Error
begin
return 1;
end function;
function func3 (x : bit := '1') return integer;
function func3 (x : bit := '0') return integer is -- Error
begin
return 1;
end function;
function func4 (x : integer) return integer;
impure function func4 (x : integer) return integer is -- Error
begin
return 1;
end function;
impure function func5 (x : integer) return integer;
function func5 (x : integer) return integer is -- Error
begin
return 1;
end function;
end package body;
| gpl-3.0 | 45f33b2533203c80aaf9d5d4849ea6b1 | 0.568847 | 4.087149 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd | 4 | 2,550 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
subtype word is bit_vector(0 to 31);
type word_vector is array (natural range <>) of word;
function resolve_unique ( drivers : word_vector ) return word is
begin
return drivers(drivers'left);
end function resolve_unique;
signal source1, source2 : resolve_unique word register;
-- . . .
-- not in book
type alu_op_type is (pass1, pass2, add, subtract);
procedure perform_alu_op ( signal alu_opcode : in alu_op_type;
signal source1, source2 : in word;
signal destination : out word;
constant ignored : in integer := 0 ) is
begin
null;
end procedure perform_alu_op;
signal phase1, source1_reg_out_en,other_signal : bit;
signal alu_opcode : alu_op_type;
signal destination : word;
-- end not in book
begin
source1_reg : process (phase1, source1_reg_out_en, -- . . .) is
-- not in book
other_signal) is
-- end not in book
variable stored_value : word;
begin
-- . . .
if source1_reg_out_en = '1' and phase1 = '1' then
source1 <= stored_value;
-- not in book
stored_value := not stored_value;
-- end not in book
else
source1 <= null;
end if;
end process source1_reg;
alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . );
-- not in book
open );
-- end not in book
-- . . .
-- not in book
process is
begin
wait for 10 ns;
source1_reg_out_en <= '1';
phase1 <= '1', '0' after 10 ns;
wait for 20 ns;
source1_reg_out_en <= '1';
phase1 <= '1', '0' after 10 ns;
wait;
end process;
-- end not in book
end architecture rtl;
-- end code from book
| gpl-2.0 | be24a050fe7bb2f4f9091a139dfbac46 | 0.653725 | 3.674352 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/numeric_std.vhdl | 1 | 75,853 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number
-- : in vector form
-- : -- > UNRESOLVED_SIGNED: represents a SIGNED number
-- : in vector form
-- : The base element type is type STD_ULOGIC.
-- : Aliases U_UNSIGNED and U_SIGNED are defined for the types
-- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively.
-- : Two numeric subtypes are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The element subtypes are the same subtype as STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
constant CopyRightNotice : STRING
:= "Copyright © 2008 IEEE. All rights reserved.";
--============================================================================
-- Numeric Array Type Definitions
--============================================================================
type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;
subtype U_UNSIGNED is UNRESOLVED_UNSIGNED;
subtype U_SIGNED is UNRESOLVED_SIGNED;
subtype UNSIGNED is (resolved) UNRESOLVED_UNSIGNED;
subtype SIGNED is (resolved) UNRESOLVED_SIGNED;
--============================================================================
-- Arithmetic Operators:
--===========================================================================
-- Id: A.1
function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the absolute value of an UNRESOLVED_SIGNED vector ARG.
-- Id: A.2
function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the value of the unary minus operation on a
-- UNRESOLVED_SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two UNRESOLVED_UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit UNRESOLVED_UNSIGNED
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNRESOLVED_UNSIGNED
-- Id: A.4
function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two UNRESOLVED_SIGNED vectors that may be of different lengths.
-- Id: A.4R
function "+"(L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.4 where R is bit 0 of a non-negative.
-- Id: A.4L
function "+"(L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.4 where L is bit 0 of a non-negative.
-- Id: A.5
function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Adds an UNRESOLVED_UNSIGNED vector, L, with a nonnegative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Adds a nonnegative INTEGER, L, with an UNRESOLVED_UNSIGNED vector, R.
-- Id: A.7
function "+" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Adds an INTEGER, L(may be positive or negative), to an UNRESOLVED_SIGNED
-- vector, R.
-- Id: A.8
function "+" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Adds an UNRESOLVED_SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts two UNRESOLVED_UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNRESOLVED_UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNRESOLVED_UNSIGNED
-- Id: A.10
function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts an UNRESOLVED_SIGNED vector, R, from another UNRESOLVED_SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.10R
function "-"(L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.10L
function "-"(L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.11
function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts a nonnegative INTEGER, R, from an UNRESOLVED_UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts an UNRESOLVED_UNSIGNED vector, R, from a nonnegative INTEGER, L.
-- Id: A.13
function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts an INTEGER, R, from an UNRESOLVED_SIGNED vector, L.
-- Id: A.14
function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts an UNRESOLVED_SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Performs the multiplication operation on two UNRESOLVED_UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two UNRESOLVED_SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_UNSIGNED vector, L, with a nonnegative
-- INTEGER, R. R is converted to an UNRESOLVED_UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_UNSIGNED vector, R, with a nonnegative
-- INTEGER, L. L is converted to an UNRESOLVED_UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
-- Id: A.19
function "*" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_SIGNED vector, L, with an INTEGER, R. R is
-- converted to an UNRESOLVED_SIGNED vector of SIZE L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_SIGNED vector, R, with an INTEGER, L. L is
-- converted to an UNRESOLVED_SIGNED vector of SIZE R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_UNSIGNED vector, L, by another UNRESOLVED_UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_SIGNED vector, L, by another UNRESOLVED_SIGNED vector, R.
-- Id: A.23
function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_UNSIGNED vector, L, by a nonnegative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a nonnegative INTEGER, L, by an UNRESOLVED_UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by an UNRESOLVED_SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNRESOLVED_UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNRESOLVED_SIGNED vectors.
-- Id: A.29
function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNRESOLVED_UNSIGNED vector and R is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNRESOLVED_UNSIGNED vector and L is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is UNRESOLVED_SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is UNRESOLVED_SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNRESOLVED_UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNRESOLVED_SIGNED vectors.
-- Id: A.35
function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNRESOLVED_UNSIGNED vector and R
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNRESOLVED_UNSIGNED vector and L
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.40
function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.42
function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.4
function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.5
function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.6
function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNRESOLVED_SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.10
function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.11
function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.12
function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.16
function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.17
function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.18
function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.22
function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.23
function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.24
function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.28
function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.29
function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.30
function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.34
function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.35
function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.36
function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the lesser of two UNRESOLVED_UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.38
function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the lesser of two UNRESOLVED_SIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNRESOLVED_UNSIGNED vector, R.
-- Id: C.40
function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the lesser of an INTEGER, L, and an UNRESOLVED_SIGNED
-- vector, R.
-- Id: C.41
function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the lesser of an UNRESOLVED_UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.42
function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the lesser of an UNRESOLVED_SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the greater of two UNRESOLVED_UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.44
function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the greater of two UNRESOLVED_SIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNRESOLVED_UNSIGNED vector, R.
-- Id: C.46
function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the greater of an INTEGER, L, and an UNRESOLVED_SIGNED
-- vector, R.
-- Id: C.47
function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the greater of an UNRESOLVED_UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.48
function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the greater of an UNRESOLVED_SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.50
function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.52
function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.53
function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.54
function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNRESOLVED_SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.56
function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.58
function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.59
function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.60
function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.62
function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.64
function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.65
function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.66
function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.68
function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.70
function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.71
function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.72
function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.74
function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.76
function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.77
function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.78
function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.80
function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.82
function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.83
function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.84
function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNRESOLVED_UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNRESOLVED_UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
-- Id: S.3
function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNRESOLVED_SIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNRESOLVED_SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost
-- element, ARG'LEFT. The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNRESOLVED_UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNRESOLVED_UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of an UNRESOLVED_SIGNED
-- vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of an UNRESOLVED_SIGNED
-- vector COUNT times.
--============================================================================
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE StdL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNRESOLVED_SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNRESOLVED_SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNRESOLVED_UNSIGNED vector.
-- Result: Converts the UNRESOLVED_UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts an UNRESOLVED_SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a UNRESOLVED_SIGNED vector of the specified SIZE.
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.15
function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.16
function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.17
function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.18
function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.19
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.20
function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.21
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.22
function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.23
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.24
function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
-- Id: L.27
function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.28
function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.29
function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.30
function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.31
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.32
function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.33
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.34
function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.35
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.36
function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
--============================================================================
-- Match Functions
--============================================================================
-- Id: M.1
function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.2
function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.3
function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.5
function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.2
function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.3
function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.4
function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.5
function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L'|'Z' are translated to 'X'.
-- Id: T.6
function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L'|'Z' are translated to 'X'.
-- Id: T.7
function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than 'U'|'0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.8
function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than 'U'|'0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.9
function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: TRUE if S contains a 'U'|'X'|'Z'|'W'|'-' value, FALSE otherwise.
-- Id: T.10
function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: TRUE if S contains a 'U'|'X'|'Z'|'W'|'-' value, FALSE otherwise.
--============================================================================
-- string conversion and write operations
--============================================================================
-- the following operations are predefined
-- function TO_STRING (value : UNRESOLVED_UNSIGNED) return STRING;
-- function TO_STRING (value : UNRESOLVED_SIGNED) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [UNRESOLVED_UNSIGNED return STRING];
alias TO_BSTRING is TO_STRING [UNRESOLVED_SIGNED return STRING];
alias to_binary_string is TO_STRING [UNRESOLVED_UNSIGNED return STRING];
alias to_binary_string is TO_STRING [UNRESOLVED_SIGNED return STRING];
function TO_OSTRING (value : UNRESOLVED_UNSIGNED) return STRING;
function TO_OSTRING (value : UNRESOLVED_SIGNED) return STRING;
alias to_octal_string is TO_OSTRING [UNRESOLVED_UNSIGNED return STRING];
alias to_octal_string is TO_OSTRING [UNRESOLVED_SIGNED return STRING];
function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING;
function to_hstring (value : UNRESOLVED_SIGNED) return STRING;
alias to_hex_string is to_hstring [UNRESOLVED_UNSIGNED return STRING];
alias to_hex_string is to_hstring [UNRESOLVED_SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED);
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_UNSIGNED];
alias BREAD is READ [LINE, UNRESOLVED_SIGNED];
alias BINARY_READ is READ [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_UNSIGNED];
alias BINARY_READ is READ [LINE, UNRESOLVED_SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_UNSIGNED];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED);
alias HEX_READ is HREAD [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_UNSIGNED];
alias HEX_READ is HREAD [LINE, UNRESOLVED_SIGNED];
alias BWRITE is WRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
end package NUMERIC_STD;
| gpl-2.0 | 1f18345be8f32ef034cc294f443fa9d9 | 0.600306 | 4.32334 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1018/test.vhdl | 1 | 640 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port(
clk : in std_logic;
wr_addr : in std_logic_vector(0 downto 0);
wr_data : in std_logic_vector(7 downto 0)
);
end test;
architecture rtl of test is
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
begin
process(clk)
variable widx : integer range 0 to 1;
begin
if rising_edge(clk) then
widx := to_integer(unsigned(wr_addr));
ram(widx) <= wr_data;
end if;
end process;
end;
| gpl-2.0 | ddfdb40619cefa3e85e14e656434438f | 0.58125 | 3.316062 | false | true | false | false |
nickg/nvc | test/regress/concat6.vhd | 1 | 2,913 | entity concat6 is
end entity;
architecture test of concat6 is
-- Examples from LRM 93 section 7.2.5
type R1 is range 0 to 7;
type R2 is range 7 downto 0;
type T1 is array (R1 range <>) of Bit;
type T2 is array (R2 range <>) of Bit;
subtype S1 is T1(R1);
subtype S2 is T2(R2);
constant K1: S1 := (others => '0');
constant K2: T1 := K1(1 to 3) & K1(3 to 4); -- K2'Left = 0 and K2'Right = 4
constant K3: T1 := K1(5 to 7) & K1(1 to 2); -- K3'Left = 0 and K3'Right = 4
constant K4: T1 := K1(2 to 1) & K1(1 to 2); -- K4'Left = 0 and K4'Right = 1
constant K5: S2 := (others => '0');
constant K6: T2 := K5(3 downto 1) & K5(4 downto 3); -- K6'Left = 7 and K6'Right = 3
constant K7: T2 := K5(7 downto 5) & K5(2 downto 1); -- K7'Left = 7 and K7'Right = 3
constant K8: T2 := K5(1 downto 2) & K5(2 downto 1); -- K8'Left = 7 and K8'Right = 6
function get_left(x : T1) return R1 is
begin
return x'left;
end function;
function get_left(x : T2) return R2 is
begin
return x'left;
end function;
function get_right(x : T1) return R1 is
begin
return x'right;
end function;
function get_right(x : T2) return R2 is
begin
return x'right;
end function;
begin
main: process is
begin
assert K2'left = 0 report R1'image(K2'left);
assert get_left(K2) = 0 report R1'image(K2'left);
assert K2'right = 4 report R1'image(K2'right);
assert get_right(K2) = 4 report R1'image(K2'right);
assert K2'ascending;
assert K3'left = 0 report R1'image(K3'left);
assert get_left(K3) = 0 report R1'image(K3'left);
assert K3'right = 4 report R1'image(K3'right);
assert get_right(K3) = 4 report R1'image(K3'right);
assert K3'ascending;
assert K4'left = 0 report R1'image(K4'left);
assert get_left(K4) = 0 report R1'image(K4'left);
assert K4'right = 1 report R1'image(K4'right);
assert get_right(K4) = 1 report R1'image(K4'right);
assert K4'ascending;
assert K6'left = 7 report R2'image(K6'left);
assert get_left(K6) = 7 report R2'image(K6'left);
assert K6'right = 3 report R2'image(K6'right);
assert get_right(K6) = 3 report R2'image(K6'right);
assert not K6'ascending;
assert K7'left = 7 report R2'image(K7'left);
assert get_left(K7) = 7 report R2'image(K7'left);
assert K7'right = 3 report R2'image(K7'right);
assert get_right(K7) = 3 report R2'image(K7'right);
assert not K6'ascending;
assert K8'left = 7 report R2'image(K8'left);
assert get_left(K8) = 7 report R2'image(K8'left);
assert K8'right = 6 report R2'image(K8'right);
assert get_right(K8) = 6 report R2'image(K8'right);
assert not K6'ascending;
wait;
end process;
end architecture;
| gpl-3.0 | acd763fd9b918a82b6fc788d08436df1 | 0.592173 | 2.869951 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/bounded_buffer_adt.vhd | 4 | 4,357 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package bounded_buffer_adt is
subtype byte is bit_vector(0 to 7);
type bounded_buffer_object; -- private
type bounded_buffer is access bounded_buffer_object;
function new_bounded_buffer ( size : in positive ) return bounded_buffer;
-- creates a bounded buffer object with 'size' bytes of storage
procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
is_empty : out boolean );
-- tests whether the bounded buffer is empty (i.e., no data to read)
procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
is_full : out boolean );
-- tests whether the bounded buffer is full (i.e., no data can be written)
procedure write ( the_bounded_buffer : inout bounded_buffer; data : in byte );
-- if the bounded buffer is not full, writes the data
-- if it is full, assertion violation with severity failure
procedure read ( the_bounded_buffer : inout bounded_buffer; data : out byte );
-- if the bounded buffer is not empty, read the first byte of data
-- if it is empty, assertion violation with severity failure
----------------------------------------------------------------
-- the following types are private to the ADT
type store_array is array (natural range <>) of byte;
type store_ptr is access store_array;
type bounded_buffer_object is record
byte_count : natural;
head_index, tail_index : natural;
store : store_ptr;
end record bounded_buffer_object;
end package bounded_buffer_adt;
package body bounded_buffer_adt is
function new_bounded_buffer ( size : in positive ) return bounded_buffer is
begin
return new bounded_buffer_object'(
byte_count => 0, head_index => 0, tail_index => 0,
store => new store_array(0 to size - 1) );
end function new_bounded_buffer;
procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
is_empty : out boolean ) is
begin
is_empty := the_bounded_buffer.byte_count = 0;
end procedure test_empty;
procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
is_full : out boolean ) is
begin
is_full := the_bounded_buffer.byte_count = the_bounded_buffer.store'length;
end procedure test_full;
procedure write ( the_bounded_buffer : inout bounded_buffer; data : in byte ) is
variable buffer_full : boolean;
begin
test_full(the_bounded_buffer, buffer_full);
if buffer_full then
report "write to full bounded buffer" severity failure;
else
the_bounded_buffer.store(the_bounded_buffer.tail_index) := data;
the_bounded_buffer.tail_index := (the_bounded_buffer.tail_index + 1)
mod the_bounded_buffer.store'length;
the_bounded_buffer.byte_count := the_bounded_buffer.byte_count + 1;
end if;
end procedure write;
procedure read ( the_bounded_buffer : inout bounded_buffer; data : out byte ) is
variable buffer_empty : boolean;
begin
test_empty(the_bounded_buffer, buffer_empty);
if buffer_empty then
report "read from empty bounded buffer" severity failure;
else
data := the_bounded_buffer.store(the_bounded_buffer.head_index);
the_bounded_buffer.head_index := (the_bounded_buffer.head_index + 1)
mod the_bounded_buffer.store'length;
the_bounded_buffer.byte_count := the_bounded_buffer.byte_count - 1;
end if;
end procedure read;
end package body bounded_buffer_adt;
| gpl-2.0 | 021154a9f0fb392bf1ddb3db9dd3456e | 0.67294 | 4.114259 | false | true | false | false |
nickg/nvc | test/simp/issue331.vhd | 1 | 2,148 | -- issue331.vhd
entity ISSUE331 is
generic (
INFO_BITS : integer := 1;
INFO_1_VAL : integer := 0
);
port (
I_INFO_0 : in bit_vector(INFO_BITS-1 downto 0);
I_INFO_1 : in bit_vector(INFO_BITS-1 downto 0);
O_INFO_0 : out bit_vector(INFO_BITS-1 downto 0);
O_INFO_1 : out bit_vector(INFO_BITS-1 downto 0)
);
end ISSUE331;
architecture MODEL of ISSUE331 is
type INFO_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
end record;
type VEC_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
INFO_0 : INFO_RANGE_TYPE;
INFO_1 : INFO_RANGE_TYPE;
end record;
function SET_VEC_RANGE return VEC_RANGE_TYPE is
variable d_pos : integer;
variable v : VEC_RANGE_TYPE;
procedure SET_INFO_RANGE(INFO_RANGE: inout INFO_RANGE_TYPE; BITS: in integer) is
begin
INFO_RANGE.DATA_LO := d_pos;
INFO_RANGE.DATA_HI := d_pos + BITS-1;
d_pos := d_pos + BITS;
end procedure;
begin
d_pos := 0;
v.DATA_LO := d_pos;
SET_INFO_RANGE(v.INFO_0, INFO_BITS);
if (INFO_1_VAL /= 0) then
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
end if;
v.DATA_HI := d_pos - 1;
if (INFO_1_VAL = 0) then
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
end if;
return v;
end function;
constant VEC_RANGE : VEC_RANGE_TYPE := SET_VEC_RANGE;
signal i_data : bit_vector(VEC_RANGE.DATA_HI downto VEC_RANGE.DATA_LO);
begin
i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO) <= I_INFO_0;
O_INFO_0 <= i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO);
INFO_1: if (INFO_1_VAL /= 0) generate
i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO) <= I_INFO_1;
O_INFO_1 <= i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO);
end generate;
end MODEL;
| gpl-3.0 | e114c9d66687f2075edeaff9506fafbd | 0.532123 | 3.158824 | false | false | false | false |
cdsteinkuehler/AXI_Reg | DE0_Nano_Reg.vhd | 1 | 22,635 | -- Copyright (C) 2015, Charles Steinkuehler
-- <charles AT steinkuehler DOT net>
-- All rights reserved
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of the copyright holder nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.Reg_Pkg.all;
library soc_system;
entity DE0_Nano_Reg is
port (
----------------
-- ADC --
----------------
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
----------------
-- ARDUINO --
----------------
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
----------------
-- CLK --
----------------
CLK_I2C_SCL : inout std_logic;
CLK_I2C_SDA : inout std_logic;
----------------
-- FPGA --
----------------
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
----------------
-- GPIO --
----------------
GPIO_0 : inout std_logic_vector(35 downto 0);
GPIO_1 : inout std_logic_vector(35 downto 0);
----------------
-- HPS --
----------------
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector( 2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector( 3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector( 3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector( 3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector( 3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector( 3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector( 3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector( 7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic;
----------------
-- KEY --
----------------
KEY : in std_logic_vector( 1 downto 0);
----------------
-- LED --
----------------
LED : out std_logic_vector( 7 downto 0);
----------------
-- SW --
----------------
SW : in std_logic_vector( 3 downto 0) );
end DE0_Nano_Reg;
architecture arch of DE0_Nano_Reg is
signal axi_reg_awid : std_logic_vector(13 downto 0); -- axs_s1_awid
signal axi_reg_awaddr : std_logic_vector(13 downto 0); -- axs_s1_awaddr
signal axi_reg_awlen : std_logic_vector(7 downto 0); -- axs_s1_awlen
signal axi_reg_awsize : std_logic_vector(2 downto 0); -- axs_s1_awsize
signal axi_reg_awburst : std_logic_vector(1 downto 0); -- axs_s1_awburst
signal axi_reg_awvalid : std_logic; -- axs_s1_awvalid
signal axi_reg_awready : std_logic := '0'; -- axs_s1_awready
signal axi_reg_wdata : std_logic_vector(31 downto 0); -- axs_s1_wdata
signal axi_reg_wstrb : std_logic_vector(3 downto 0); -- axs_s1_wstrb
signal axi_reg_wvalid : std_logic; -- axs_s1_wvalid
signal axi_reg_wready : std_logic := '0'; -- axs_s1_wready
signal axi_reg_bid : std_logic_vector(13 downto 0) := (others => '0'); -- axs_s1_bid
signal axi_reg_bvalid : std_logic := '0'; -- axs_s1_bvalid
signal axi_reg_bready : std_logic; -- axs_s1_bready
signal axi_reg_arid : std_logic_vector(13 downto 0); -- axs_s1_arid
signal axi_reg_araddr : std_logic_vector(13 downto 0); -- axs_s1_araddr
signal axi_reg_arlen : std_logic_vector(7 downto 0); -- axs_s1_arlen
signal axi_reg_arsize : std_logic_vector(2 downto 0); -- axs_s1_arsize
signal axi_reg_arburst : std_logic_vector(1 downto 0); -- axs_s1_arburst
signal axi_reg_arvalid : std_logic; -- axs_s1_arvalid
signal axi_reg_arready : std_logic := '0'; -- axs_s1_arready
signal axi_reg_rid : std_logic_vector(13 downto 0) := (others => '0'); -- axs_s1_rid
signal axi_reg_rdata : std_logic_vector(31 downto 0) := (others => '0'); -- axs_s1_rdata
signal axi_reg_rlast : std_logic := '0'; -- axs_s1_rlast
signal axi_reg_rvalid : std_logic := '0'; -- axs_s1_rvalid
signal axi_reg_rready : std_logic; -- axs_s1_rready
signal axi_reg_clk : std_logic; -- clk_o
signal axi_reg_reset : std_logic; -- reset_o
signal fpga_led_internal : std_logic_vector(3 downto 0);
signal hps_fpga_reset_n : std_logic;
signal Bank1RegWr : RegWrA_T;
signal Bank2RegWr : RegWrA_T;
signal FIFORegWr : FIFORegWrA_T;
signal Bank2RegRd : RegRd_A(255 downto 0);
signal Bank1RegRd : RegRd_A(255 downto 0);
signal ctrlreg : std_logic_vector(63 downto 0);
begin
SoC : entity soc_system.soc_system
port map (
-- Clock & Reset
clk_clk => FPGA_CLK1_50, -- clk.clk
reset_reset_n => '1', -- reset.reset_n
-- HPS DDR3
memory_mem_a => HPS_DDR3_ADDR, -- memory.mem_a
memory_mem_ba => HPS_DDR3_BA, -- .mem_ba
memory_mem_ck => HPS_DDR3_CK_P, -- .mem_ck
memory_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n
memory_mem_cke => HPS_DDR3_CKE, -- .mem_cke
memory_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n
memory_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n
memory_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n
memory_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n
memory_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n
memory_mem_dq => HPS_DDR3_DQ, -- .mem_dq
memory_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs
memory_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n
memory_mem_odt => HPS_DDR3_ODT, -- .mem_odt
memory_mem_dm => HPS_DDR3_DM, -- .mem_dm
memory_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin
-- HPS ethernet
hps_0_hps_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, -- .hps_0_hps_io.hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), -- .hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), -- .hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- .hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- .hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- .hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- .hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- .hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- .hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, -- .hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, -- .hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, -- .hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, -- .hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
-- HPS SD card
hps_0_hps_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, -- .hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, -- .hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- .hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- .hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- .hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- .hps_io_sdio_inst_D3
-- HPS USB
hps_0_hps_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- .hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- .hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- .hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- .hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- .hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- .hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- .hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- .hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, -- .hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP => HPS_USB_STP, -- .hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, -- .hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, -- .hps_io_usb1_inst_NXT
-- HPS SPI
hps_0_hps_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK, -- .hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI, -- .hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO, -- .hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS, -- .hps_io_spim1_inst_SS0
-- HPS UART
hps_0_hps_io_hps_io_uart0_inst_RX => HPS_UART_RX, -- .hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX => HPS_UART_TX, -- .hps_io_uart0_inst_TX
-- HPS I2C1
hps_0_hps_io_hps_io_i2c0_inst_SDA => HPS_I2C0_SDAT, -- .hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL => HPS_I2C0_SCLK, -- .hps_io_i2c0_inst_SCL
-- HPS I2C2
hps_0_hps_io_hps_io_i2c1_inst_SDA => HPS_I2C1_SDAT, -- .hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL => HPS_I2C1_SCLK, -- .hps_io_i2c1_inst_SCL
-- HPS GPIO
hps_0_hps_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N, -- .hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N, -- .hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO, -- .hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 => HPS_LED, -- .hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 => HPS_KEY, -- .hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT, -- .hps_io_gpio_inst_GPIO61
-- HPS Resets
hps_0_f2h_stm_hw_events_stm_hwevents => (others=>'0'), -- hps_0_f2h_stm_hw_events.stm_hwevents
hps_0_h2f_reset_reset_n => hps_fpga_reset_n, -- hps_0_h2f_reset.reset_n
hps_0_f2h_warm_reset_req_reset_n => '1', -- hps_0_f2h_warm_reset_req.reset_n
hps_0_f2h_debug_reset_req_reset_n => '1', -- hps_0_f2h_debug_reset_req.reset_n
hps_0_f2h_cold_reset_req_reset_n => '1', -- hps_0_f2h_cold_reset_req.reset_n
-- AXI Conduit for register I/O
axi_conduit_0_axi_out_axs_s1_awid => axi_reg_awid,
axi_conduit_0_axi_out_axs_s1_awaddr => axi_reg_awaddr,
axi_conduit_0_axi_out_axs_s1_awlen => axi_reg_awlen,
axi_conduit_0_axi_out_axs_s1_awsize => axi_reg_awsize,
axi_conduit_0_axi_out_axs_s1_awburst => axi_reg_awburst,
axi_conduit_0_axi_out_axs_s1_awvalid => axi_reg_awvalid,
axi_conduit_0_axi_out_axs_s1_awready => axi_reg_awready,
axi_conduit_0_axi_out_axs_s1_wdata => axi_reg_wdata,
axi_conduit_0_axi_out_axs_s1_wstrb => axi_reg_wstrb,
axi_conduit_0_axi_out_axs_s1_wvalid => axi_reg_wvalid,
axi_conduit_0_axi_out_axs_s1_wready => axi_reg_wready,
axi_conduit_0_axi_out_axs_s1_bid => axi_reg_bid,
axi_conduit_0_axi_out_axs_s1_bvalid => axi_reg_bvalid,
axi_conduit_0_axi_out_axs_s1_bready => axi_reg_bready,
axi_conduit_0_axi_out_axs_s1_arid => axi_reg_arid,
axi_conduit_0_axi_out_axs_s1_araddr => axi_reg_araddr,
axi_conduit_0_axi_out_axs_s1_arlen => axi_reg_arlen,
axi_conduit_0_axi_out_axs_s1_arsize => axi_reg_arsize,
axi_conduit_0_axi_out_axs_s1_arburst => axi_reg_arburst,
axi_conduit_0_axi_out_axs_s1_arvalid => axi_reg_arvalid,
axi_conduit_0_axi_out_axs_s1_arready => axi_reg_arready,
axi_conduit_0_axi_out_axs_s1_rid => axi_reg_rid,
axi_conduit_0_axi_out_axs_s1_rdata => axi_reg_rdata,
axi_conduit_0_axi_out_axs_s1_rlast => axi_reg_rlast,
axi_conduit_0_axi_out_axs_s1_rvalid => axi_reg_rvalid,
axi_conduit_0_axi_out_axs_s1_rready => axi_reg_rready,
axi_conduit_0_axi_out_clk_o => axi_reg_clk,
axi_conduit_0_axi_out_reset_o => axi_reg_reset
);
axi_reg_wr : entity work.AXI_Reg_Wr_E
port map (
clk => axi_reg_clk,
rst => axi_reg_reset,
-- Write Address Channel
axi_awid => axi_reg_awid,
axi_awaddr => axi_reg_awaddr,
axi_awlen => axi_reg_awlen,
axi_awsize => axi_reg_awsize,
axi_awburst => axi_reg_awburst,
--axi_awlock : in std_logic_vector(1 downto 0);
--axi_awcache : in std_logic_vector(3 downto 0);
--axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid => axi_reg_awvalid,
axi_awready => axi_reg_awready,
-- Write Data Channel
axi_wdata => axi_reg_wdata,
axi_wstrb => axi_reg_wstrb,
--axi_wlast : in std_logic;
axi_wvalid => axi_reg_wvalid,
axi_wready => axi_reg_wready,
-- Write Response Channel
axi_bid => axi_reg_bid,
--axi_bresp : out std_logic_vector(1 downto 0);
axi_bvalid => axi_reg_bvalid,
axi_bready => axi_reg_bready,
-- Register write interface
Bank1RegWr => Bank1RegWr,
Bank2RegWr => Bank2RegWr,
FIFORegWr => FIFORegWr );
AXI_rd : entity work.AXI_Reg_Rd_E
port map (
clk => axi_reg_clk,
rst => axi_reg_reset,
-- Read Address Channel
axi_arid => axi_reg_arid,
axi_araddr => axi_reg_araddr,
axi_arlen => axi_reg_arlen,
axi_arsize => axi_reg_arsize,
axi_arburst => axi_reg_arburst,
axi_arvalid => axi_reg_arvalid,
axi_arready => axi_reg_arready,
-- Read Data Channel
axi_rid => axi_reg_rid,
axi_rdata => axi_reg_rdata,
axi_rlast => axi_reg_rlast,
axi_rvalid => axi_reg_rvalid,
axi_rready => axi_reg_rready,
-- Register read data
Bank1RegRd => Bank1RegRd,
Bank2RegRd => Bank2RegRd );
-----------------------------
-- Control register writes --
-----------------------------
process(axi_reg_clk)
begin
if rising_edge(axi_reg_clk) then
if axi_reg_reset='1' then
ctrlreg <= (others=>'0');
else
if Bank1RegWr.we(0)='1' then
for index in 0 to 63 loop
if Bank1RegWr.be(index/8)='1' then
ctrlreg(index) <= Bank1RegWr.data(index);
end if;
end loop;
end if;
end if;
end if;
end process;
Bank1RegRd <= (0=>ctrlreg,1=>x"1111111111111111",2=>x"2222222222222222",others=>(others=>'0'));
Bank2RegRd <= (others=>(others=>'0'));
end arch;
| bsd-3-clause | 7af188effdd624ed2986825186076e9d | 0.495958 | 3.289493 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug037/sim_simulation.v08.vhdl | 2 | 17,705 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.sim_global.all;
use PoC.sim_types.all;
use PoC.sim_protected.all;
package simulation is
-- Legacy interface for pre VHDL-2002
-- ===========================================================================
procedure simInitialize;
procedure simFinalize;
impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID;
impure function simRegisterProcess(Name : STRING) return T_SIM_PROCESS_ID;
procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID);
impure function simIsStopped return BOOLEAN;
procedure simWriteMessage(Message : in STRING := "");
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure simFail(Message : in STRING := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure simAssertion(cond : in BOOLEAN; Message : in STRING := "");
-- Random Numbers
-- ===========================================================================
type T_SIM_SEED is record
Seed1 : INTEGER;
Seed2 : INTEGER;
end record;
procedure initializeSeed(Seed : inout T_SIM_SEED);
procedure getUniformDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; Minimum : in REAL; Maximum : in REAL);
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0);
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL);
-- clock generation
-- ===========================================================================
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DutyCycle := 50 percent; constant Wander : in T_WANDER := 0 permil);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DutyCycle := 50 percent; constant Wander : in T_WANDER := 0 permil);
procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE);
procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE);
procedure simGenerateClock2(signal Clock : out STD_LOGIC; signal Debug : out INTEGER; constant Period : in TIME);
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package;
package body simulation is
-- legacy procedures
-- ===========================================================================
-- TODO: undocumented group
procedure simInitialize is
begin
globalSimulationStatus.initialize;
end procedure;
procedure simFinalize is
begin
globalSimulationStatus.finalize;
end procedure;
impure function simCreateTest(Name : STRING) return T_SIM_TEST_ID is
begin
return globalSimulationStatus.createTest(Name);
end function;
impure function simRegisterProcess(Name : STRING) return T_SIM_PROCESS_ID is
begin
return globalSimulationStatus.registerProcess(Name);
end function;
procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID) is
begin
globalSimulationStatus.deactivateProcess(ProcID);
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return globalSimulationStatus.isStopped;
end function;
-- TODO: undocumented group
procedure simWriteMessage(Message : in STRING := "") is
begin
globalSimulationStatus.writeMessage(Message);
end procedure;
procedure simFail(Message : in STRING := "") is
begin
globalSimulationStatus.fail(Message);
end procedure;
procedure simAssertion(cond : in BOOLEAN; Message : in STRING := "") is
begin
globalSimulationStatus.assertion(cond, Message);
end procedure;
-- ===========================================================================
-- Random Numbers
-- ===========================================================================
procedure initializeSeed(Seed : inout T_SIM_SEED) is
begin
Seed.Seed1 := 5;
Seed.Seed2 := 3423;
end procedure;
procedure getUniformDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; Minimum : in REAL; Maximum : in REAL) is
variable rand : REAL;
begin
if (Maximum < Minimum) then report "getUniformDistibutedRandomValue: Maximum must be greater than Minimum." severity FAILURE; end if;
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand);
Value := scale(rand, Minimum, Maximum);
end procedure ;
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL := 1.0; Mean : in REAL := 0.0) is
variable rand1 : REAL;
variable rand2 : REAL;
begin
if StandardDeviation < 0.0 then report "getNormalDistibutedRandomValue: Standard deviation must be >= 0.0" severity FAILURE; end if;
-- Box Muller transformation
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand1);
ieee.math_real.Uniform(Seed.Seed1, Seed.Seed2, rand2);
-- standard normal distribution: mean 0, variance 1
Value := StandardDeviation * (sqrt(-2.0 * log(rand1)) * cos(MATH_2_PI * rand2)) + Mean;
end procedure;
procedure getNormalDistibutedRandomValue(Seed : inout T_SIM_SEED; Value : inout REAL; StandardDeviation : in REAL; Mean : in REAL; Minimum : in REAL; Maximum : in REAL) is
variable rand : REAL;
begin
if (Maximum < Minimum) then report "getUniformDistibutedRandomValue: Maximum must be greater than Minimum." severity FAILURE; end if;
if StandardDeviation < 0.0 then report "getNormalDistibutedRandomValue: Standard deviation must be >= 0.0" severity FAILURE; end if;
while (TRUE) loop
getNormalDistibutedRandomValue(Seed, rand, StandardDeviation, Mean);
exit when ((Minimum <= rand) and (rand <= Maximum));
end loop;
Value := rand;
end procedure;
-- clock generation
-- ===========================================================================
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant Phase : in T_PHASE := 0 deg; constant DutyCycle : in T_DUTYCYCLE := 50 percent; constant Wander : in T_WANDER := 0 permil) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, Phase, DutyCycle, Wander);
end procedure;
procedure simGenerateClock(
signal Clock : out STD_LOGIC;
constant Period : in TIME;
constant Phase : in T_PHASE := 0 deg;
constant DutyCycle : in T_DUTYCYCLE := 50 percent;
constant Wander : in T_WANDER := 0 permil
) is
constant NormalizedPhase : T_PHASE := ite((Phase >= 0 deg), Phase, Phase + 360 deg); -- move Phase into the range of 0° to 360°
constant PhaseAsFactor : REAL := real(NormalizedPhase / 1 second) / 1296000.0; -- 1,296,000 = 3,600 seconds * 360 degree per cycle
constant WanderAsFactor : REAL := real(Wander / 1 ppb) / 1.0e9;
constant DutyCycleAsFactor : REAL := real(DutyCycle / 1 permil) / 1000.0;
constant Delay : TIME := Period * PhaseAsFactor;
constant TimeHigh : TIME := Period * DutyCycleAsFactor + (Period * (WanderAsFactor / 2.0)); -- add 50% wander to the high level
constant TimeLow : TIME := Period - TimeHigh + (Period * WanderAsFactor); -- and 50% to the low level
constant ClockAfterRun_cy : POSITIVE := 1;
begin
report "simGenerateClock: (Instance: '" & Clock'instance_name & "')" & CR &
"Period: " & TIME'image(Period) & CR &
"Phase: " & T_PHASE'image(Phase) & CR &
"DutyCycle: " & T_DUTYCYCLE'image(DutyCycle) & CR &
"PhaseAsFactor: " & REAL'image(PhaseAsFactor) & CR &
"WanderAsFactor: " & REAL'image(WanderAsFactor) & CR &
"DutyCycleAsFactor: " & REAL'image(DutyCycleAsFactor) & CR &
"Delay: " & TIME'image(Delay) & CR &
"TimeHigh: " & TIME'image(TimeHigh) & CR &
"TimeLow: " & TIME'image(TimeLow)
severity NOTE;
if (Delay = 0 ns) then
null;
elsif (Delay <= TimeLow) then
Clock <= '0';
wait for Delay;
else
Clock <= '1';
wait for Delay - TimeLow;
Clock <= '0';
wait for TimeLow;
end if;
Clock <= '1';
while (not globalSimulationStatus.isStopped) loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
-- create N more cycles to allow other processes to recognize the stop condition (clock after run)
for i in 1 to ClockAfterRun_cy loop
wait for TimeHigh;
Clock <= '0';
wait for TimeLow;
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
type T_SIM_NORMAL_DIST_PARAMETER is record
StandardDeviation : REAL;
Mean : REAL;
end record;
type T_JITTER_DISTRIBUTION is array (NATURAL range <>) of T_SIM_NORMAL_DIST_PARAMETER;
procedure simGenerateClock2(signal Clock : out STD_LOGIC; signal Debug : out INTEGER; constant Period : in TIME) is
constant TimeHigh : TIME := Period * 0.5;
constant TimeLow : TIME := Period - TimeHigh;
constant JitterPeakPeak : REAL := 0.1; -- UI
constant JitterAsFactor : REAL := JitterPeakPeak / 4.0; -- Maximum jitter per edge
constant JitterDistribution : T_JITTER_DISTRIBUTION := (0 => (0.6, 0.0)); --((0.2, -0.3), (0.3, -0.1), (0.5, 0.0), (0.3, 0.1), (0.2, 0.3));
variable Seed : T_SIM_SEED;
variable rand : REAL;
variable sum : REAL;
variable Jitter : REAL;
begin
Clock <= '1';
initializeSeed(Seed);
while (not globalSimulationStatus.isStopped) loop
sum := 0.0;
for i in JitterDistribution'range loop
getNormalDistibutedRandomValue(Seed, rand, JitterDistribution(i).StandardDeviation, JitterDistribution(i).Mean, -1.0, 1.0);
sum := sum + rand;
end loop;
Debug <= integer(sum * 1000.0);
Jitter := JitterAsFactor * sum;
-- Debug <= integer(rand * 256.0 + 256.0);
wait for TimeHigh + (Period * Jitter);
Clock <= '0';
wait for TimeLow + (Period * Jitter);
Clock <= '1';
end loop;
Clock <= '0';
end procedure;
procedure simWaitUntilRisingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is
begin
for i in 1 to Times loop
wait until rising_edge(Clock);
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simWaitUntilFallingEdge(signal Clock : in STD_LOGIC; constant Times : in POSITIVE) is
begin
for i in 1 to Times loop
wait until falling_edge(Clock);
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
exit when globalSimulationStatus.isStopped;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
variable p : TIME;
variable rp : TIME;
begin
-- WORKAROUND: for QuestaSim/ModelSim
-- Version: 10.4c
-- Issue:
-- return (0 => Pause, 1 => ResetPulse); always evaluates to (0 ns, 10 ns),
-- regardless of the passed function parameters
p := Pause;
rp := ResetPulse;
return (0 => p, 1 => rp);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
| gpl-2.0 | c1983622715390e53df07c444b8223b9 | 0.641756 | 3.721463 | false | false | false | false |
tgingold/ghdl | testsuite/synth/mem02/tb_ram3.vhdl | 1 | 704 | entity tb_ram3 is
end tb_ram3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram3 is
signal val : std_logic_vector(7 downto 0);
signal waddr : std_logic_vector(2 downto 0);
signal wdat : std_logic;
signal clk : std_logic;
begin
dut: entity work.ram3
port map (waddr => waddr, wdat => wdat, val => val,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
waddr <= "000";
wdat <= '0';
pulse;
waddr <= "001";
wdat <= '1';
pulse;
assert (val and x"03") = x"02" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 1f23fe54c6c8c88c785ea0d36d54fb4d | 0.569602 | 3.320755 | false | false | false | false |
gralco/FPGA-Elevator-Project | MyHDL/pck_myhdl_081.vhd | 1 | 3,363 | -- File: pck_myhdl_081.vhd
-- Generated by MyHDL 0.8.1
-- Date: Sun Jun 14 22:11:56 2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_081 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_081;
package body pck_myhdl_081 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_081;
| gpl-2.0 | 5181768c14d408524373145a818ea5f4 | 0.601249 | 4.022727 | false | false | false | false |
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