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tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_10.vhd | 4 | 1,789 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_10.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_10 is
end entity ch_03_10;
architecture test of ch_03_10 is
type opcode_type is (nop, add, subtract);
signal opcode : opcode_type := nop;
begin
process_3_3_a : process (opcode) is
variable Acc : integer := 0;
constant operand : integer := 1;
begin
-- code from book:
case opcode is
when add =>
Acc := Acc + operand;
when subtract =>
Acc := Acc - operand;
when nop =>
null;
end case;
-- end of code from book
end process process_3_3_a;
stimulus : process is
begin
opcode <= add after 10 ns, subtract after 20 ns, nop after 30 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | da3bb54d0fa79842f19b15e8103b0a44 | 0.59251 | 4.199531 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/tb_asgn08.vhdl | 1 | 1,185 | entity tb_asgn08 is
end tb_asgn08;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn08 is
signal s0 : std_logic;
signal clk : std_logic;
signal ce : std_logic;
signal r : std_logic_vector (65 downto 0);
begin
dut: entity work.asgn08
port map (clk => clk, ce => ce, s0 => s0, r => r);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
s0 <= '0';
ce <= '1';
pulse;
assert r (0) = '1' severity failure;
assert r (65) = '0' severity failure;
s0 <= '1';
pulse;
assert r (0) = '1' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cccc" severity failure;
assert r (65) = '1' severity failure;
s0 <= '0';
ce <= '0';
pulse;
assert r (0) = '1' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cccc" severity failure;
assert r (65) = '1' severity failure;
ce <= '1';
pulse;
assert r (0) = '1' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cc7c" severity failure;
assert r (65) = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 32a469a50c2bea787c5eee3997391326 | 0.577215 | 3.077922 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug094/topa.vhdl | 1 | 536 | entity topa is
end topa;
architecture behav of topa is
signal clk : bit;
signal v : bit_vector (31 downto 0);
signal done : boolean := false;
begin
dut : entity work.enta
port map (clk => clk,
data => v);
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
if done then
wait;
end if;
end process;
process
begin
v <= x"12345678";
wait for 40 ns;
v <= x"00000000";
wait for 80 ns;
done <= true;
wait;
end process;
end behav;
| gpl-2.0 | 8365d8ab211c11faf9d8498efa587899 | 0.55597 | 3.458065 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | BSA/16bits/BSA16bits/BSA16bits.vhd | 1 | 1,602 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY BSA16bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC
);
END BSA16bits;
architecture strc_BSA16bits of BSA16bits is
SIGNAL Cin_temp, Cout_temp, Cout_sig, done: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(15 DOWNTO 0);
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg16Bit
PORT (
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end component;
begin
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cin_temp,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
process(clk,rst,done)
variable counter: integer range 0 to 16 := 0;
begin
if rst = '1' then
Cin_temp <= '0';
elsif (clk='1' and clk'event) then
Out_sig(counter) <= (A_sig(counter) XOR B_sig(counter)) XOR Cin_temp;
Cin_temp <= (A_sig(counter) AND B_sig(counter)) OR (Cin_temp AND A_sig(counter)) OR (Cin_temp AND B_sig(counter));
counter := counter + 1;
end if;
end process;
end strc_BSA16bits; | mit | 54143e2ec79571b3779fba596f563d37 | 0.661673 | 2.600649 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth12/tb_lut.vhdl | 1 | 566 | entity tb_lut is
end tb_lut;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_lut is
signal c : std_logic;
signal s : std_logic_vector(1 downto 0);
begin
dut: entity work.lut
port map (s, c);
process
begin
s <= "00";
wait for 1 ns;
assert c = '1' severity failure;
s <= "01";
wait for 1 ns;
assert c = '0' severity failure;
s <= "10";
wait for 1 ns;
assert c = '1' severity failure;
s <= "11";
wait for 1 ns;
assert c = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 1c3db2fae013ae79cc2b086ce934483a | 0.586572 | 3.144444 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc870.vhd | 4 | 12,340 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc870.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00870pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
subtype dumy is integer range 0 to 3;
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00870pkg;
use work.c01s03b01x00p12n01i00870pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00870pkg.all;
entity test1 is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test1 of test1 is
begin
sigout1 <= false;
sigout2 <= '0';
sigout4 <= error;
sigout5 <= 6;
sigout6 <= 6.0;
sigout7 <= 6 ns;
sigout8 <= 6;
sigout9 <= 6;
sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
end;
configuration test1bench of test1 is
for test1
end for;
end;
use work.c01s03b01x00p12n01i00870pkg.all;
ENTITY c01s03b01x00p12n01i00870ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
port(
dumy : inout bit_vector(zero to three));
END c01s03b01x00p12n01i00870ent;
ARCHITECTURE c01s03b01x00p12n01i00870arch OF c01s03b01x00p12n01i00870ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test1
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test1
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
variable dumb : bit_vector(zero to three);
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***PASSED TEST: c01s03b01x00p12n01i00870"
severity NOTE;
assert ( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***FAILED TEST: c01s03b01x00p12n01i00870 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00870arch;
configuration c01s03b01x00p12n01i00870cfg of c01s03b01x00p12n01i00870ent is
for c01s03b01x00p12n01i00870arch
for K
for others:test1 use configuration work.test1bench;
end for;
for G(0 to 3)
for all :test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 | cb1681e7801d9d5c54378115c9aa9cbe | 0.572204 | 3.350529 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue317/PoC/src/common/vectors.vhdl | 2 | 39,259 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Common functions and types
--
-- Description:
-- -------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
package vectors is
-- ==========================================================================
-- Type declarations
-- ==========================================================================
-- STD_LOGIC_VECTORs
subtype T_SLV_2 is std_logic_vector(1 downto 0);
subtype T_SLV_3 is std_logic_vector(2 downto 0);
subtype T_SLV_4 is std_logic_vector(3 downto 0);
subtype T_SLV_8 is std_logic_vector(7 downto 0);
subtype T_SLV_12 is std_logic_vector(11 downto 0);
subtype T_SLV_16 is std_logic_vector(15 downto 0);
subtype T_SLV_24 is std_logic_vector(23 downto 0);
subtype T_SLV_32 is std_logic_vector(31 downto 0);
subtype T_SLV_48 is std_logic_vector(47 downto 0);
subtype T_SLV_64 is std_logic_vector(63 downto 0);
subtype T_SLV_96 is std_logic_vector(95 downto 0);
subtype T_SLV_128 is std_logic_vector(127 downto 0);
subtype T_SLV_256 is std_logic_vector(255 downto 0);
subtype T_SLV_512 is std_logic_vector(511 downto 0);
-- STD_LOGIC_VECTOR_VECTORs
-- type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR; -- VHDL 2008 syntax - not yet supported by Xilinx
type T_SLVV_2 is array(natural range <>) of T_SLV_2;
type T_SLVV_3 is array(natural range <>) of T_SLV_3;
type T_SLVV_4 is array(natural range <>) of T_SLV_4;
type T_SLVV_8 is array(natural range <>) of T_SLV_8;
type T_SLVV_12 is array(natural range <>) of T_SLV_12;
type T_SLVV_16 is array(natural range <>) of T_SLV_16;
type T_SLVV_24 is array(natural range <>) of T_SLV_24;
type T_SLVV_32 is array(natural range <>) of T_SLV_32;
type T_SLVV_48 is array(natural range <>) of T_SLV_48;
type T_SLVV_64 is array(natural range <>) of T_SLV_64;
type T_SLVV_128 is array(natural range <>) of T_SLV_128;
type T_SLVV_256 is array(natural range <>) of T_SLV_256;
type T_SLVV_512 is array(natural range <>) of T_SLV_512;
-- STD_LOGIC_MATRIXs
type T_SLM is array(natural range <>, natural range <>) of std_logic;
-- ATTENTION:
-- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
-- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z'));
-- 2. Xilinx iSIM bug: DON'T use myMatrix'range(n) for n >= 2
-- myMatrix'range(2) returns always myMatrix'range(1); see work-around notes below
--
-- USAGE NOTES:
-- dimension 1 => rows - e.g. Words
-- dimension 2 => columns - e.g. Bits/Bytes in a word
--
-- WORKAROUND: for Xilinx ISE/iSim
-- Version: 14.2
-- Issue: myMatrix'range(n) for n >= 2 returns always myMatrix'range(1)
-- ==========================================================================
-- Function declarations
-- ==========================================================================
-- slicing boundary calulations
function low (lenvec : T_POSVEC; index : natural) return natural;
function high(lenvec : T_POSVEC; index : natural) return natural;
-- Assign procedures: assign_*
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural); -- assign vector to complete row
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural); -- assign short vector to row starting at position
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural); -- assign short vector to row in range high:low
procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural); -- assign vector to complete column
-- ATTENTION: see T_SLM definition for further details and work-arounds
-- Matrix to matrix conversion: slm_slice*
function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width
function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all rows in RowIndex range high:low
function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all columns in ColIndex range high:low
-- Boolean Operators
function "not" (a : t_slm) return t_slm;
function "and" (a, b : t_slm) return t_slm;
function "or" (a, b : t_slm) return t_slm;
function "xor" (a, b : t_slm) return t_slm;
function "nand"(a, b : t_slm) return t_slm;
function "nor" (a, b : t_slm) return t_slm;
function "xnor"(a, b : t_slm) return t_slm;
-- Matrix concatenation: slm_merge_*
function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM;
function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM;
-- Matrix to vector conversion: get_*
function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector; -- get a matrix column
function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector; -- get a matrix row
function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector; -- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector; -- get a sub vector of a matrix row at high:low
-- Convert to vector: to_slv
function to_slv(slvv : T_SLVV_2) return std_logic_vector; -- convert vector-vector to flatten vector
function to_slv(slvv : T_SLVV_4) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_8) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_12) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_16) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_24) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_32) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_64) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_128) return std_logic_vector; -- ...
function to_slv(slm : T_SLM) return std_logic_vector; -- convert matrix to flatten vector
-- Convert flat vector to avector-vector: to_slvv_*
function to_slvv_4(slv : std_logic_vector) return T_SLVV_4; --
function to_slvv_8(slv : std_logic_vector) return T_SLVV_8; --
function to_slvv_12(slv : std_logic_vector) return T_SLVV_12; --
function to_slvv_16(slv : std_logic_vector) return T_SLVV_16; --
function to_slvv_32(slv : std_logic_vector) return T_SLVV_32; --
function to_slvv_64(slv : std_logic_vector) return T_SLVV_64; --
function to_slvv_128(slv : std_logic_vector) return T_SLVV_128; --
function to_slvv_256(slv : std_logic_vector) return T_SLVV_256; --
function to_slvv_512(slv : std_logic_vector) return T_SLVV_512; --
-- Convert matrix to avector-vector: to_slvv_*
function to_slvv_4(slm : T_SLM) return T_SLVV_4; --
function to_slvv_8(slm : T_SLM) return T_SLVV_8; --
function to_slvv_12(slm : T_SLM) return T_SLVV_12; --
function to_slvv_16(slm : T_SLM) return T_SLVV_16; --
function to_slvv_32(slm : T_SLM) return T_SLVV_32; --
function to_slvv_64(slm : T_SLM) return T_SLVV_64; --
function to_slvv_128(slm : T_SLM) return T_SLVV_128; --
function to_slvv_256(slm : T_SLM) return T_SLVV_256; --
function to_slvv_512(slm : T_SLM) return T_SLVV_512; --
-- Convert vector-vector to matrix: to_slm
function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM; -- create matrix from vector
function to_slm(slvv : T_SLVV_4) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_8) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_12) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_16) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_32) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_48) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_64) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_128) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_256) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_512) return T_SLM; -- create matrix from vector-vector
-- Change vector direction
function dir(slvv : T_SLVV_8) return T_SLVV_8;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4;
function rev(slvv : T_SLVV_8) return T_SLVV_8;
function rev(slvv : T_SLVV_12) return T_SLVV_12;
function rev(slvv : T_SLVV_16) return T_SLVV_16;
function rev(slvv : T_SLVV_32) return T_SLVV_32;
function rev(slvv : T_SLVV_64) return T_SLVV_64;
function rev(slvv : T_SLVV_128) return T_SLVV_128;
function rev(slvv : T_SLVV_256) return T_SLVV_256;
function rev(slvv : T_SLVV_512) return T_SLVV_512;
-- TODO:
function resize(slm : T_SLM; size : positive) return T_SLM;
-- to_string
function to_string(slvv : T_SLVV_8; sep : character := ':') return string;
function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string;
end package vectors;
package body vectors is
-- slicing boundary calulations
-- ==========================================================================
function low(lenvec : T_POSVEC; index : natural) return natural is
variable pos : natural := 0;
begin
for i in lenvec'low to index - 1 loop
pos := pos + lenvec(i);
end loop;
return pos;
end function;
function high(lenvec : T_POSVEC; index : natural) return natural is
variable pos : natural := 0;
begin
for i in lenvec'low to index loop
pos := pos + lenvec(i);
end loop;
return pos - 1;
end function;
-- Assign procedures: assign_*
-- ==========================================================================
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural) is
variable temp : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural) is
variable temp : std_logic_vector(Position + slv'length - 1 downto Position);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural) is
variable temp : std_logic_vector(High downto Low);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural) is
variable temp : std_logic_vector(slm'range(1));
begin
temp := slv;
for i in temp'range loop
slm(i, ColIndex) <= temp(i);
end loop;
end procedure;
-- Matrix to matrix conversion: slm_slice*
-- ==========================================================================
function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM is
variable Result : T_SLM(Height - 1 downto 0, Width - 1 downto 0) := (others => (others => '0'));
begin
for i in 0 to Height - 1 loop
for j in 0 to Width - 1 loop
Result(i, j) := slm(RowIndex + i, ColIndex + j);
end loop;
end loop;
return Result;
end function;
function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM is
variable Result : T_SLM(High - Low downto 0, slm'length(2) - 1 downto 0) := (others => (others => '0'));
begin
for i in 0 to High - Low loop
for j in 0 to slm'length(2) - 1 loop
Result(i, j) := slm(Low + i, slm'low(2) + j);
end loop;
end loop;
return Result;
end function;
function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM is
variable Result : T_SLM(slm'length(1) - 1 downto 0, High - Low downto 0) := (others => (others => '0'));
begin
for i in 0 to slm'length(1) - 1 loop
for j in 0 to High - Low loop
Result(i, j) := slm(slm'low(1) + i, Low + j);
end loop;
end loop;
return Result;
end function;
-- Boolean Operators
function "not"(a : t_slm) return t_slm is
variable res : t_slm(a'range(1), a'range(2));
begin
for i in res'range(1) loop
for j in res'range(2) loop
res(i, j) := not a(i, j);
end loop;
end loop;
return res;
end function;
function "and"(a, b : t_slm) return t_slm is
variable bb, res : t_slm(a'range(1), a'range(2));
begin
bb := b;
for i in res'range(1) loop
for j in res'range(2) loop
res(i, j) := a(i, j) and bb(i, j);
end loop;
end loop;
return res;
end function;
function "or"(a, b : t_slm) return t_slm is
variable bb, res : t_slm(a'range(1), a'range(2));
begin
bb := b;
for i in res'range(1) loop
for j in res'range(2) loop
res(i, j) := a(i, j) or bb(i, j);
end loop;
end loop;
return res;
end function;
function "xor"(a, b : t_slm) return t_slm is
variable bb, res : t_slm(a'range(1), a'range(2));
begin
bb := b;
for i in res'range(1) loop
for j in res'range(2) loop
res(i, j) := a(i, j) xor bb(i, j);
end loop;
end loop;
return res;
end function;
function "nand"(a, b : t_slm) return t_slm is
begin
return not(a and b);
end function;
function "nor"(a, b : t_slm) return t_slm is
begin
return not(a or b);
end function;
function "xnor"(a, b : t_slm) return t_slm is
begin
return not(a xor b);
end function;
-- Matrix concatenation: slm_merge_*
function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is
constant ROWS : positive := slm1'length(1) + slm2'length(1);
constant COLUMNS : positive := slm1'length(2);
variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0);
begin
for i in slm1'range(1) loop
for j in slm1'low(2) to slm1'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slm(i, j) := slm1(i, j);
end loop;
end loop;
for i in slm2'range(1) loop
for j in slm2'low(2) to slm2'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slm(slm1'length(1) + i, j) := slm2(i, j);
end loop;
end loop;
return slm;
end function;
function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is
constant ROWS : positive := slm1'length(1);
constant COLUMNS : positive := slm1'length(2) + slm2'length(2);
variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0);
begin
for i in slm1'range(1) loop
for j in slm1'low(2) to slm1'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slm(i, j) := slm1(i, j);
end loop;
for j in slm2'low(2) to slm2'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slm(i, slm1'length(2) + j) := slm2(i, j);
end loop;
end loop;
return slm;
end function;
-- Matrix to vector conversion: get_*
-- ==========================================================================
-- get a matrix column
function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector is
variable slv : std_logic_vector(slm'range(1));
begin
for i in slm'range(1) loop
slv(i) := slm(i, ColIndex);
end loop;
return slv;
end function;
-- get a matrix row
function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector is
variable slv : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector is
begin
return get_row(slm, RowIndex, (Length - 1), 0);
end function;
-- get a sub vector of a matrix row at high:low
function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector is
variable slv : std_logic_vector(High downto Low);
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- Convert to vector: to_slv
-- ==========================================================================
-- convert vector-vector to flatten vector
function to_slv(slvv : T_SLVV_2) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 2) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 2) + 1 downto (i * 2)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_4) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 4) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 4) + 3 downto (i * 4)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_8) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 8) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 8) + 7 downto (i * 8)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_12) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 12) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 12) + 11 downto (i * 12)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_16) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 16) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 16) + 15 downto (i * 16)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_24) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 24) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 24) + 23 downto (i * 24)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_32) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 32) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 32) + 31 downto (i * 32)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_64) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 64) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 64) + 63 downto (i * 64)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_128) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 128) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 128) + 127 downto (i * 128)) := slvv(i);
end loop;
return slv;
end function;
-- convert matrix to flatten vector
function to_slv(slm : T_SLM) return std_logic_vector is
variable slv : std_logic_vector((slm'length(1) * slm'length(2)) - 1 downto 0);
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slv((i * slm'length(2)) + j) := slm(i, j);
end loop;
end loop;
return slv;
end function;
-- Convert flat vector to a vector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from vector (4 bit)
function to_slvv_4(slv : std_logic_vector) return T_SLVV_4 is
variable Result : T_SLVV_4((slv'length / 4) - 1 downto 0);
begin
if ((slv'length mod 4) /= 0) then report "to_slvv_4: width mismatch - slv'length is no multiple of 4 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 4) + 3 downto (i * 4));
end loop;
return Result;
end function;
-- create vector-vector from vector (8 bit)
function to_slvv_8(slv : std_logic_vector) return T_SLVV_8 is
variable Result : T_SLVV_8((slv'length / 8) - 1 downto 0);
begin
if ((slv'length mod 8) /= 0) then report "to_slvv_8: width mismatch - slv'length is no multiple of 8 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 8) + 7 downto (i * 8));
end loop;
return Result;
end function;
-- create vector-vector from vector (12 bit)
function to_slvv_12(slv : std_logic_vector) return T_SLVV_12 is
variable Result : T_SLVV_12((slv'length / 12) - 1 downto 0);
begin
if ((slv'length mod 12) /= 0) then report "to_slvv_12: width mismatch - slv'length is no multiple of 12 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 12) + 11 downto (i * 12));
end loop;
return Result;
end function;
-- create vector-vector from vector (16 bit)
function to_slvv_16(slv : std_logic_vector) return T_SLVV_16 is
variable Result : T_SLVV_16((slv'length / 16) - 1 downto 0);
begin
if ((slv'length mod 16) /= 0) then report "to_slvv_16: width mismatch - slv'length is no multiple of 16 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 16) + 15 downto (i * 16));
end loop;
return Result;
end function;
-- create vector-vector from vector (32 bit)
function to_slvv_32(slv : std_logic_vector) return T_SLVV_32 is
variable Result : T_SLVV_32((slv'length / 32) - 1 downto 0);
begin
if ((slv'length mod 32) /= 0) then report "to_slvv_32: width mismatch - slv'length is no multiple of 32 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 32) + 31 downto (i * 32));
end loop;
return Result;
end function;
-- create vector-vector from vector (64 bit)
function to_slvv_64(slv : std_logic_vector) return T_SLVV_64 is
variable Result : T_SLVV_64((slv'length / 64) - 1 downto 0);
begin
if ((slv'length mod 64) /= 0) then report "to_slvv_64: width mismatch - slv'length is no multiple of 64 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 64) + 63 downto (i * 64));
end loop;
return Result;
end function;
-- create vector-vector from vector (128 bit)
function to_slvv_128(slv : std_logic_vector) return T_SLVV_128 is
variable Result : T_SLVV_128((slv'length / 128) - 1 downto 0);
begin
if ((slv'length mod 128) /= 0) then report "to_slvv_128: width mismatch - slv'length is no multiple of 128 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 128) + 127 downto (i * 128));
end loop;
return Result;
end function;
-- create vector-vector from vector (256 bit)
function to_slvv_256(slv : std_logic_vector) return T_SLVV_256 is
variable Result : T_SLVV_256((slv'length / 256) - 1 downto 0);
begin
if ((slv'length mod 256) /= 0) then report "to_slvv_256: width mismatch - slv'length is no multiple of 256 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 256) + 255 downto (i * 256));
end loop;
return Result;
end function;
-- create vector-vector from vector (512 bit)
function to_slvv_512(slv : std_logic_vector) return T_SLVV_512 is
variable Result : T_SLVV_512((slv'length / 512) - 1 downto 0);
begin
if ((slv'length mod 512) /= 0) then report "to_slvv_512: width mismatch - slv'length is no multiple of 512 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 512) + 511 downto (i * 512));
end loop;
return Result;
end function;
-- Convert matrix to avector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from matrix (4 bit)
function to_slvv_4(slm : T_SLM) return T_SLVV_4 is
variable Result : T_SLVV_4(slm'range(1));
begin
if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (8 bit)
function to_slvv_8(slm : T_SLM) return T_SLVV_8 is
variable Result : T_SLVV_8(slm'range(1));
begin
if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (12 bit)
function to_slvv_12(slm : T_SLM) return T_SLVV_12 is
variable Result : T_SLVV_12(slm'range(1));
begin
if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (16 bit)
function to_slvv_16(slm : T_SLM) return T_SLVV_16 is
variable Result : T_SLVV_16(slm'range(1));
begin
if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (32 bit)
function to_slvv_32(slm : T_SLM) return T_SLVV_32 is
variable Result : T_SLVV_32(slm'range(1));
begin
if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (64 bit)
function to_slvv_64(slm : T_SLM) return T_SLVV_64 is
variable Result : T_SLVV_64(slm'range(1));
begin
if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (128 bit)
function to_slvv_128(slm : T_SLM) return T_SLVV_128 is
variable Result : T_SLVV_128(slm'range(1));
begin
if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (256 bit)
function to_slvv_256(slm : T_SLM) return T_SLVV_256 is
variable Result : T_SLVV_256(slm'range);
begin
if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (512 bit)
function to_slvv_512(slm : T_SLM) return T_SLVV_512 is
variable Result : T_SLVV_512(slm'range(1));
begin
if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- Convert vector-vector to matrix: to_slm
-- ==========================================================================
-- create matrix from vector
function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM is
variable slm : T_SLM(ROWS - 1 downto 0, COLS - 1 downto 0);
begin
for i in 0 to ROWS - 1 loop
for j in 0 to COLS - 1 loop
slm(i, j) := slv((i * COLS) + j);
end loop;
end loop;
return slm;
end function;
-- create matrix from vector-vector
function to_slm(slvv : T_SLVV_4) return T_SLM is
variable slm : T_SLM(slvv'range, 3 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_4'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_8) return T_SLM is
-- variable test : STD_LOGIC_VECTOR(T_SLV_8'range);
-- variable slm : T_SLM(slvv'range, test'range); -- BUG: iSIM 14.5 cascaded 'range accesses let iSIM break down
-- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimension 2
variable slm : T_SLM(slvv'range, 7 downto 0); -- WORKAROUND: use constant range
begin
-- report "slvv: slvv.length=" & INTEGER'image(slvv'length) & " slm.dim0.length=" & INTEGER'image(slm'length(1)) & " slm.dim1.length=" & INTEGER'image(slm'length(2)) severity NOTE;
-- report "T_SLV_8: .length=" & INTEGER'image(T_SLV_8'length) & " .high=" & INTEGER'image(T_SLV_8'high) & " .low=" & INTEGER'image(T_SLV_8'low) severity NOTE;
-- report "test: test.length=" & INTEGER'image(test'length) & " .high=" & INTEGER'image(test'high) & " .low=" & INTEGER'image(test'low) severity NOTE;
for i in slvv'range loop
for j in T_SLV_8'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_12) return T_SLM is
variable slm : T_SLM(slvv'range, 11 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_12'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_16) return T_SLM is
variable slm : T_SLM(slvv'range, 15 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_16'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_32) return T_SLM is
variable slm : T_SLM(slvv'range, 31 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_32'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_48) return T_SLM is
variable slm : T_SLM(slvv'range, 47 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_48'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_64) return T_SLM is
variable slm : T_SLM(slvv'range, 63 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_64'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_128) return T_SLM is
variable slm : T_SLM(slvv'range, 127 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_128'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_256) return T_SLM is
variable slm : T_SLM(slvv'range, 255 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_256'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_512) return T_SLM is
variable slm : T_SLM(slvv'range, 511 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_512'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
-- Change vector direction
-- ==========================================================================
function dir(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'reverse_range);
begin
Result := slvv;
return Result;
end function;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4 is
variable Result : T_SLVV_4(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_12) return T_SLVV_12 is
variable Result : T_SLVV_12(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_16) return T_SLVV_16 is
variable Result : T_SLVV_16(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_32) return T_SLVV_32 is
variable Result : T_SLVV_32(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_64) return T_SLVV_64 is
variable Result : T_SLVV_64(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_128) return T_SLVV_128 is
variable Result : T_SLVV_128(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_256) return T_SLVV_256 is
variable Result : T_SLVV_256(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_512) return T_SLVV_512 is
variable Result : T_SLVV_512(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
-- Resize functions
-- ==========================================================================
-- Resizes the vector to the specified length. Input vectors larger than the specified size are truncated from the left side. Smaller input
-- vectors are extended on the left by the provided fill value (default: '0'). Use the resize functions of the numeric_std package for
-- value-preserving resizes of the signed and unsigned data types.
function resize(slm : T_SLM; size : positive) return T_SLM is
variable Result : T_SLM(size - 1 downto 0, slm'high(2) downto slm'low(2)) := (others => (others => '0')); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
Result(i, j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_string(slvv : T_SLVV_8; sep : character := ':') return string is
constant hex_len : positive := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1);
variable Result : string(1 to hex_len) := (others => sep);
variable pos : positive := 1;
begin
for i in slvv'range loop
Result(pos to pos + 1) := to_string(slvv(i), 'h');
pos := pos + ite((sep = C_POC_NUL), 2, 3);
end loop;
return Result;
end function;
function to_string_bin(slm : T_SLM; groups : positive := 4; format : character := 'h') return string is
variable PerLineOverheader : positive := div_ceil(slm'length(2), groups);
variable Result : string(1 to (slm'length(1) * (slm'length(2) + PerLineOverheader)) + 10);
variable Writer : positive;
variable GroupCounter : natural;
begin
Result := (others => C_POC_NUL);
Result(1) := LF;
Writer := 2;
GroupCounter := 0;
for i in slm'low(1) to slm'high(1) loop
for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
Result(Writer) := to_char(slm(i, j));
Writer := Writer + 1;
GroupCounter := GroupCounter + 1;
if GroupCounter = groups then
Result(Writer) := ' ';
Writer := Writer + 1;
GroupCounter := 0;
end if;
end loop;
Result(Writer - 1) := LF;
GroupCounter := 0;
end loop;
return str_trim(Result);
end function;
function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string is
begin
if (format = 'b') then
return to_string_bin(slm, groups);
else
return "Format not supported.";
end if;
end function;
end package body;
| gpl-2.0 | 6ab6a826ddf30d40478c7a878d586c8c | 0.626863 | 2.967198 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue563/repro.vhdl | 1 | 1,204 | -- library ieee;
-- library vunit_lib;
-- context vunit_lib.vunit_context;
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity tb_counter is
-- generic (runner_cfg : string);
end tb_counter;
architecture arch_tb_counter of tb_counter is
-- component counter is
-- port (
-- key0: in std_logic;
-- key3: in std_logic;
-- counter_out: out std_logic_vector(3 downto 0)
-- );
-- end component;
-- signal key0, key3: std_logic;
-- signal counter_out: std_logic_vector(3 downto 0);
-- function trigger_rising() return std_logic_vector is
-- begin
-- key0 <= '0';
-- wait for 1 ns;
-- key0 <= '1';
-- wait for 1 ns;
-- end;
begin
-- uut: counter port map(
-- key0 => key0,
-- key3 => key3,
-- counter_out => counter_out
-- );
main: process
begin
-- test_runner_setup(runner, runner_cfg);
-- for j in 0 to 8 loop
-- trigger_rising();
-- check_match( counter_out, (std_logic_vector(to_unsigned(j + 1, 4))) );
-- end loop;
check_match(counter_out, ())))
-- test_runner_cleanup(runner); -- Simulation ends here
end process;
end arch_tb_counter ; -- arch_tb_counter
| gpl-2.0 | 6a06d86f4ad137e822dcb12dc6c6e0b1 | 0.587209 | 3.111111 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket89/x_ieee_proposed/src/standard_additions_c.vhdl | 3 | 63,492 | ------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
package standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN;
function \?<\ (L, R : BOOLEAN) return BOOLEAN;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN;
function \?>\ (L, R : BOOLEAN) return BOOLEAN;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;
function \?=\ (L, R : BIT) return BIT;
function \?/=\ (L, R : BIT) return BIT;
function \?<\ (L, R : BIT) return BIT;
function \?<=\ (L, R : BIT) return BIT;
function \?>\ (L, R : BIT) return BIT;
function \?>=\ (L, R : BIT) return BIT;
function MINIMUM (L, R : BIT) return BIT;
function MAXIMUM (L, R : BIT) return BIT;
function \??\ (L : BIT) return BOOLEAN;
function RISING_EDGE (signal S : BIT) return BOOLEAN;
function FALLING_EDGE (signal S : BIT) return BOOLEAN;
function MINIMUM (L, R : CHARACTER) return CHARACTER;
function MAXIMUM (L, R : CHARACTER) return CHARACTER;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;
function MINIMUM (L, R : INTEGER) return INTEGER;
function MAXIMUM (L, R : INTEGER) return INTEGER;
function MINIMUM (L, R : REAL) return REAL;
function MAXIMUM (L, R : REAL) return REAL;
function "mod" (L, R : TIME) return TIME;
function "rem" (L, R : TIME) return TIME;
function MINIMUM (L, R : TIME) return TIME;
function MAXIMUM (L, R : TIME) return TIME;
function MINIMUM (L, R : STRING) return STRING;
function MAXIMUM (L, R : STRING) return STRING;
function MINIMUM (L : STRING) return CHARACTER;
function MAXIMUM (L : STRING) return CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR;
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR;
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR;
-- function "=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;
-- function "&" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
function and_reduce (L : BIT_VECTOR) return BIT;
function or_reduce (L : BIT_VECTOR) return BIT;
function nand_reduce (L : BIT_VECTOR) return BIT;
function nor_reduce (L : BIT_VECTOR) return BIT;
function xor_reduce (L : BIT_VECTOR) return BIT;
function xnor_reduce (L : BIT_VECTOR) return BIT;
function \?=\ (L, R : BIT_VECTOR) return BIT;
function \?/=\ (L, R : BIT_VECTOR) return BIT;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
function MINIMUM (L : BIT_VECTOR) return BIT;
function MAXIMUM (L : BIT_VECTOR) return BIT;
function TO_STRING (VALUE : BIT_VECTOR) return STRING;
alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN;
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN;
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN;
function "/=" (L, R : REAL_VECTOR) return BOOLEAN;
function "<" (L, R : REAL_VECTOR) return BOOLEAN;
function "<=" (L, R : REAL_VECTOR) return BOOLEAN;
function ">" (L, R : REAL_VECTOR) return BOOLEAN;
function ">=" (L, R : REAL_VECTOR) return BOOLEAN;
-- function "&" (L : REAL_VECTOR; R : REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L : REAL; R : REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;
function MINIMUM (L : REAL_VECTOR) return REAL;
function MAXIMUM (L : REAL_VECTOR) return REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN;
function "/=" (L, R : TIME_VECTOR) return BOOLEAN;
function "<" (L, R : TIME_VECTOR) return BOOLEAN;
function "<=" (L, R : TIME_VECTOR) return BOOLEAN;
function ">" (L, R : TIME_VECTOR) return BOOLEAN;
function ">=" (L, R : TIME_VECTOR) return BOOLEAN;
-- function "&" (L : TIME_VECTOR; R : TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L : TIME; R : TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;
function MINIMUM (L : TIME_VECTOR) return TIME;
function MAXIMUM (L : TIME_VECTOR) return TIME;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;
-- predefined TO_STRING operations on scalar types
function TO_STRING (VALUE : BOOLEAN) return STRING;
function TO_STRING (VALUE : BIT) return STRING;
function TO_STRING (VALUE : CHARACTER) return STRING;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;
function TO_STRING (VALUE : INTEGER) return STRING;
function TO_STRING (VALUE : REAL) return STRING;
function TO_STRING (VALUE : TIME) return STRING;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;
-- predefined overloaded TO_STRING operations
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;
end package standard_additions;
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
use std.textio.all;
package body standard_additions is
function \?=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
function \?<\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L < R;
end function \?<\;
function \?<=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L <= R;
end function \?<=\;
function \?>\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L > R;
end function \?>\;
function \?>=\ (L, R : BOOLEAN) return BOOLEAN is
begin
return L >= R;
end function \?>=\;
function MINIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BOOLEAN) return STRING is
begin
return BOOLEAN'image(VALUE);
end function TO_STRING;
function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = true) and (s'last_value = false));
end function rising_edge;
function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is
begin
return (s'event and (s = false) and (s'last_value = true));
end function falling_edge;
function \?=\ (L, R : BIT) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function \?<\ (L, R : BIT) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function \?<\;
function \?<=\ (L, R : BIT) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function \?<=\;
function \?>\ (L, R : BIT) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function \?>\;
function \?>=\ (L, R : BIT) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function \?>=\;
function MINIMUM (L, R : BIT) return BIT is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT) return BIT is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : BIT) return STRING is
begin
if VALUE = '1' then
return "1";
else
return "0";
end if;
end function TO_STRING;
function \??\ (L : BIT) return BOOLEAN is
begin
return L = '1';
end function \??\;
function RISING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '1') and (s'last_value = '0'));
end function rising_edge;
function FALLING_EDGE (signal S : BIT) return BOOLEAN is
begin
return (s'event and (s = '0') and (s'last_value = '1'));
end function falling_edge;
function MINIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : CHARACTER) return CHARACTER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : CHARACTER) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := VALUE;
return result;
end function TO_STRING;
function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is
begin
return SEVERITY_LEVEL'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER) return INTEGER is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : INTEGER) return STRING is
begin
return INTEGER'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : REAL) return REAL is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL) return REAL is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : REAL) return STRING is
begin
return REAL'image (VALUE);
end function TO_STRING;
function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is
begin
return to_string (VALUE, "%1." & INTEGER'image(DIGITS) & "f");
end function TO_STRING;
function "mod" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint mod rint) * 1.0 ns;
end function "mod";
function "rem" (L, R : TIME) return TIME is
variable lint, rint : INTEGER;
begin
lint := L / 1.0 ns;
rint := R / 1.0 ns;
return (lint rem rint) * 1.0 ns;
end function "rem";
function MINIMUM (L, R : TIME) return TIME is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME) return TIME is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : TIME) return STRING is
begin
return TIME'image (VALUE);
end function TO_STRING;
function MINIMUM (L, R : STRING) return STRING is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : STRING) return STRING is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : STRING) return CHARACTER is
variable result : CHARACTER := CHARACTER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
-- The predefined operations for this type are as follows:
function "and" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) and rv(i));
end loop;
end if;
return result;
end function "and";
function "or" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) or rv(i));
end loop;
end if;
return result;
end function "or";
function "nand" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nand rv(i));
end loop;
end if;
return result;
end function "nand";
function "nor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) nor rv(i));
end loop;
end if;
return result;
end function "nor";
function "xor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xor rv(i));
end loop;
end if;
return result;
end function "xor";
function "xnor" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := (lv(i) xnor rv(i));
end loop;
end if;
return result;
end function "xnor";
function "not" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not (lv(i));
end loop;
return result;
end function "not";
function "and" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nand r;
end loop;
return result;
end function "nand";
function "nand" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nand rv(i);
end loop;
return result;
end function "nand";
function "nor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) nor r;
end loop;
return result;
end function "nor";
function "nor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l nor rv(i);
end loop;
return result;
end function "nor";
function "xor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BOOLEAN_VECTOR; R : BOOLEAN)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xnor r;
end loop;
return result;
end function "xnor";
function "xnor" (L : BOOLEAN; R : BOOLEAN_VECTOR)
return BOOLEAN_VECTOR is
alias rv : BOOLEAN_VECTOR (1 to r'length) is r;
variable result : BOOLEAN_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xnor rv(i);
end loop;
return result;
end function "xnor";
function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := true;
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := false;
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function "sll" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
function "srl" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
function "sla" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'high);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sla";
function "sra" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
begin
for i in L'range loop
result (i) := L(L'low);
end loop;
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l sra -r;
end if;
return result;
end function "sra";
function "rol" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
function "ror" (L : BOOLEAN_VECTOR; R : INTEGER)
return BOOLEAN_VECTOR is
alias lv : BOOLEAN_VECTOR (1 to l'length) is l;
variable result : BOOLEAN_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-- function "=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "/=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function "<=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
-- function ">=" (L, R: BOOLEAN_VECTOR) return BOOLEAN;
function \?=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L = R;
end function \?=\;
function \?/=\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is
begin
return L /= R;
end function \?/=\;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)
-- return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;
-- function "&" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;
function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is
variable result : BOOLEAN := BOOLEAN'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function "and" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return result;
end function "and";
function "and" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end function "and";
function "or" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return result;
end function "or";
function "or" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return result;
end function "or";
function "nand" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) and r;
end loop;
return not result;
end function "nand";
function "nand" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return not result;
end function "nand";
function "nor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) or r;
end loop;
return not result;
end function "nor";
function "nor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l or rv(i);
end loop;
return not result;
end function "nor";
function "xor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return result;
end function "xor";
function "xor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return result;
end function "xor";
function "xnor" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
alias lv : BIT_VECTOR (1 to l'length) is l;
variable result : BIT_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := lv(i) xor r;
end loop;
return not result;
end function "xnor";
function "xnor" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
alias rv : BIT_VECTOR (1 to r'length) is r;
variable result : BIT_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := l xor rv(i);
end loop;
return not result;
end function "xnor";
function and_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return result;
end function and_reduce;
function or_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return result;
end function or_reduce;
function nand_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '1';
begin
for i in l'reverse_range loop
result := l(i) and result;
end loop;
return not result;
end function nand_reduce;
function nor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) or result;
end loop;
return not result;
end function nor_reduce;
function xor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return result;
end function xor_reduce;
function xnor_reduce (L : BIT_VECTOR) return BIT is
variable result : BIT := '0';
begin
for i in l'reverse_range loop
result := l(i) xor result;
end loop;
return not result;
end function xnor_reduce;
function \?=\ (L, R : BIT_VECTOR) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function \?=\;
function \?/=\ (L, R : BIT_VECTOR) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function \?/=\;
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : BIT_VECTOR) return BIT is
variable result : BIT := BIT'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];
-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];
function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : BIT_VECTOR(0 to 2);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := ivalue(3*i to 3*i+2);
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
end case;
end loop;
return result;
end function to_ostring;
-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];
function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');
variable ivalue : BIT_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : BIT_VECTOR(0 to 3);
begin
if value'length < 1 then
return "";
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := ivalue(4*i to 4*i+3);
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
end case;
end loop;
return result;
end function to_hstring;
-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];
-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
-- The predefined operations for this type are as follows:
function "=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : INTEGER_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)
-- return INTEGER_VECTOR;
-- function "&" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;
-- function "&" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;
function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is
variable result : INTEGER := INTEGER'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type REAL_VECTOR is array (NATURAL range <>) of REAL;
-- The predefined operations for this type are as follows:
function "=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : REAL_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: REAL_VECTOR; R: REAL_VECTOR)
-- return REAL_VECTOR;
-- function "&" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;
-- function "&" (L: REAL; R: REAL) return REAL_VECTOR;
function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : REAL_VECTOR) return REAL is
variable result : REAL := REAL'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
-- type TIME_VECTOR is array (NATURAL range <>) of TIME;
-- The predefined implicit operations for this type are as follows:
function "=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length or L'length < 1 or R'length < 1 then
return false;
else
for i in l'range loop
if L(i) /= R(i) then
return false;
end if;
end loop;
return true;
end if;
end function "=";
function "/=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
return not (L = R);
end function "/=";
function "<" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function "<";
function "<=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length < R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) < R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function "<=";
function ">" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return false;
end if;
end function ">";
function ">=" (L, R : TIME_VECTOR) return BOOLEAN is
begin
if L'length /= R'length then
return L'length > R'length;
else
for i in l'range loop
if L(i) /= R(i) then
if L(i) > R(i) then
return true;
else
return false;
end if;
end if;
end loop;
return true;
end if;
end function ">=";
-- function "&" (L: TIME_VECTOR; R: TIME_VECTOR)
-- return TIME_VECTOR;
-- function "&" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;
-- function "&" (L: TIME; R: TIME) return TIME_VECTOR;
function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function MINIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'high;
begin
for i in l'range loop
result := minimum (l(i), result);
end loop;
return result;
end function MINIMUM;
function MAXIMUM (L : TIME_VECTOR) return TIME is
variable result : TIME := TIME'low;
begin
for i in l'range loop
result := maximum (l(i), result);
end loop;
return result;
end function MAXIMUM;
function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is
begin
return FILE_OPEN_KIND'image(VALUE);
end function TO_STRING;
function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return R;
else return L;
end if;
end function MINIMUM;
function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is
begin
if L > R then return L;
else return R;
end if;
end function MAXIMUM;
function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is
begin
return FILE_OPEN_STATUS'image(VALUE);
end function TO_STRING;
-- USED INTERNALLY!
function justify (
value : in STRING;
justified : in SIDE := right;
field : in width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is
variable L : LINE; -- pointer
begin
deallocate (L);
write (L => L,
VALUE => VALUE,
UNIT => UNIT);
return L.all;
end function to_string;
function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is
constant czero : CHARACTER := '0'; -- zero
constant half : REAL := 0.4999999999; -- almost 0.5
-- Log10 funciton
function log10 (arg : REAL) return INTEGER is
variable i : INTEGER := 1;
begin
if ((arg = 0.0)) then
return 0;
elsif arg >= 1.0 then
while arg >= 10.0**i loop
i := i + 1;
end loop;
return (i-1);
else
while arg < 10.0**i loop
i := i - 1;
end loop;
return i;
end if;
end function log10;
-- purpose: writes a fractional real number into a line
procedure writefrc (
variable L : inout LINE; -- LINE
variable cdes : in CHARACTER;
variable precision : in INTEGER; -- number of decimal places
variable value : in REAL) is -- real value
variable rvar : REAL; -- temp variable
variable xint : INTEGER;
variable xreal : REAL;
begin
xreal := (10.0**(-precision));
write (L, '.');
rvar := value;
for i in 1 to precision loop
rvar := rvar * 10.0;
xint := INTEGER(rvar-0.49999999999); -- round
write (L, xint);
rvar := rvar - REAL(xint);
xreal := xreal * 10.0;
if (cdes = 'g') and (rvar < xreal) then
exit;
end if;
end loop;
end procedure writefrc;
-- purpose: replace the "." with a "@", and "e" with "j" to get around
-- read ("6.") and read ("2e") issues.
function subdot (
constant format : STRING)
return STRING is
variable result : STRING (format'range);
begin
for i in format'range loop
if (format(i) = '.') then
result(i) := '@'; -- Because the parser reads 6.2 as REAL
elsif (format(i) = 'e') then
result(i) := 'j'; -- Because the parser read 2e as REAL
elsif (format(i) = 'E') then
result(i) := 'J'; -- Because the parser reads 2E as REAL
else
result(i) := format(i);
end if;
end loop;
return result;
end function subdot;
-- purpose: find a . in a STRING
function isdot (
constant format : STRING)
return BOOLEAN is
begin
for i in format'range loop
if (format(i) = '@') then
return true;
end if;
end loop;
return false;
end function isdot;
variable exp : INTEGER; -- integer version of baseexp
variable bvalue : REAL; -- base value
variable roundvar, tvar : REAL; -- Rounding values
variable frcptr : INTEGER; -- integer version of number
variable fwidth, dwidth : INTEGER; -- field width and decimal width
variable dash, dot : BOOLEAN := false;
variable cdes, ddes : CHARACTER := ' ';
variable L : LINE; -- line type
begin
-- Perform the same function that "printf" does
-- examples "%6.2f" "%-7e" "%g"
if not (format(format'left) = '%') then
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end if;
L := new STRING'(subdot(format));
read (L, ddes); -- toss the '%'
case L.all(1) is
when '-' => dash := true;
when '@' => dash := true; -- in FP, a "-" and a "." are the same
when 'f' => cdes := 'f';
when 'F' => cdes := 'F';
when 'g' => cdes := 'g';
when 'G' => cdes := 'G';
when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j
when 'J' => cdes := 'E';
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;
when others =>
report "to_string: Illegal format string """ & format & '"'
severity error;
return "";
end case;
if (dash or (cdes /= ' ')) then
read (L, ddes); -- toss the next character
end if;
if (cdes = ' ') then
if (isdot(L.all)) then -- if you see a . two numbers
read (L, fwidth); -- read field width
read (L, ddes); -- toss the next character .
read (L, dwidth); -- read decimal width
else
read (L, fwidth); -- read field width
dwidth := 6; -- the default decimal width is 6
end if;
read (L, cdes);
if (cdes = 'j') then
cdes := 'e'; -- because 2e reads as "REAL".
elsif (cdes = 'J') then
cdes := 'E';
end if;
else
if (cdes = 'E' or cdes = 'e') then
fwidth := 10; -- default for e and E is %10.6e
else
fwidth := 0; -- default for f and g is %0.6f
end if;
dwidth := 6;
end if;
deallocate (L); -- reclame the pointer L.
-- assert (not debug) report "Format: " & format & " "
-- & INTEGER'image(fwidth) & "." & INTEGER'image(dwidth) & cdes
-- severity note;
if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'
or cdes = 'e' or cdes = 'E')) then
report "to_string: Illegal format """ & format & '"' severity error;
return "";
end if;
if (VALUE < 0.0) then
bvalue := -value;
write (L, '-');
else
bvalue := value;
end if;
case cdes is
when 'e' | 'E' => -- 7.000E+01
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half); -- Write a single digit.
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
writefrc (-- Write out the fraction
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
write (L, cdes); -- e or E
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then -- we need another "0".
write (L, czero);
end if;
write (L, exp);
when 'f' | 'F' => -- 70.0
exp := log10(bvalue);
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
if (exp < 0) then -- 0.X case
write (L, czero);
else -- loop because real'high > integer'high
while (exp >= 0) loop
frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);
write (L, frcptr);
bvalue := bvalue - (REAL(frcptr) * (10.0**exp));
exp := exp-1;
end loop;
end if;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
when 'g' | 'G' => -- 70
exp := log10(bvalue);
roundvar := half*(10.0**(exp-dwidth)); -- small number
bvalue := bvalue + roundvar; -- round
exp := log10(bvalue); -- because we CAN overflow
frcptr := INTEGER(bvalue-half);
tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number
if (exp < dwidth)
and (tvar < roundvar and tvar > -roundvar) then
-- and ((bvalue-roundvar) = real(frcptr)) then
write (L, frcptr); -- Just a short integer, write it.
elsif (exp >= dwidth) or (exp < -4) then
-- in "e" format (modified)
bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX
frcptr := INTEGER(bvalue-half);
write (L, frcptr);
bvalue := bvalue - REAL(frcptr);
if (bvalue > (10.0**(1-dwidth))) then
dwidth := dwidth - 1;
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
if (cdes = 'G') then
write (L, 'E');
else
write (L, 'e');
end if;
if (exp < 0) then
write (L, '-');
else
write (L, '+');
end if;
exp := abs(exp);
if (exp < 10) then
write (L, czero);
end if;
write (L, exp);
else
-- in "f" format (modified)
if (exp < 0) then
write (L, czero);
dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.
bvalue := bvalue - roundvar; -- recalculate rounding
roundvar := half*(10.0**(-dwidth));
bvalue := bvalue + roundvar;
else
write (L, frcptr); -- integer part (always small)
bvalue := bvalue - (REAL(frcptr));
dwidth := dwidth - exp - 1;
end if;
if (bvalue > roundvar) then
writefrc (
L => L,
cdes => cdes,
precision => dwidth,
value => bvalue);
end if;
end if;
when others => return "";
end case;
-- You don't truncate real numbers.
-- if (dot) then -- truncate
-- if (L.all'length > fwidth) then
-- return justify (value => L.all (1 to fwidth),
-- justified => RIGHT,
-- field => fwidth);
-- else
-- return justify (value => L.all,
-- justified => RIGHT,
-- field => fwidth);
-- end if;
if (dash) then -- fill to fwidth
return justify (value => L.all,
justified => left,
field => fwidth);
else
return justify (value => L.all,
justified => right,
field => fwidth);
end if;
end function to_string;
end package body standard_additions;
| gpl-2.0 | 4c5c7ebca798a9f1725cbc0552e290c8 | 0.569584 | 3.742308 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd | 4 | 2,135 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
library ieee; use ieee.numeric_bit.all;
architecture test of inline_08 is
begin
process_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bit_vector( "+"(signed(left), signed(right)) );
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bit_vector( "-"(signed(right)) );
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_5_b;
end architecture test;
| gpl-2.0 | fe0afb0defe4a9ace984370c700a1ffa | 0.618735 | 4.097889 | false | false | false | false |
nickg/nvc | test/parse/visibility1.vhd | 1 | 533 | package p1 is
constant k : integer := 1;
constant j : integer := 5;
type t is (FOO, BAR);
end package;
package p2 is
constant k : integer := 2;
constant j : integer := 7;
type t is (BAR, BAZ);
end package;
use work.p1.all;
use work.p2.all;
package p3 is
constant x : integer := k; -- Error
constant j : integer := 2; -- OK
constant y : integer := j; -- OK
constant z : t := FOO; -- Error
constant b : boolean := BAR; -- Error
end package;
| gpl-3.0 | 63685dfc4cbebe7f2390cb7afe4961ad | 0.530957 | 3.461039 | false | false | false | false |
nickg/nvc | test/regress/record21.vhd | 1 | 1,220 | entity record21 is
end entity;
architecture test of record21 is
type rec is record
t : character;
-- Three bytes padding
x, y : integer;
z : character;
-- Three bytes padding
end record;
type rec_array is array (positive range <>) of rec;
function resolve(x : rec_array) return rec is
variable r : rec := ('0', 0, 0, 'q');
begin
assert x'left = 1;
assert x'right = x'length;
for i in x'range loop
report "x(" & integer'image(i) & ") = (" & integer'image(x(i).x)
& ", " & integer'image(x(i).y) & ")";
r.x := r.x + x(i).x;
r.y := r.y + x(i).y;
end loop;
return r;
end function;
subtype resolved_rec is resolve rec;
signal sig : resolved_rec := ('0', 0, 0, '0');
begin
p1: process is
begin
sig <= ('a', 1, 2, 'x');
wait for 1 ns;
sig.x <= 5;
wait;
end process;
p2: process is
begin
sig <= ('b', 4, 5, 'y');
wait for 1 ns;
assert sig = ('0', 5, 7, 'q');
wait for 1 ns;
assert sig = ('0', 9, 7, 'q');
wait;
end process;
end architecture;
| gpl-3.0 | 405322059baf31e960c678f2c163f86f | 0.47377 | 3.456091 | false | false | false | false |
tgingold/ghdl | testsuite/synth/var01/var02.vhdl | 1 | 868 | library ieee;
use ieee.std_logic_1164.all;
entity var02 is
port (clk : std_logic;
mask : std_logic_vector (3 downto 0);
val : std_logic_vector (31 downto 0);
res : out std_logic_vector (31 downto 0));
end var02;
architecture behav of var02 is
signal r : std_logic_vector (31 downto 0) := (others => '0');
signal r_up : std_logic_vector (31 downto 0) := (others => '0');
begin
process (all)
variable t : std_logic_vector (31 downto 0) := (others => '0');
variable hi, lo : natural;
begin
t := r;
for i in 0 to 3 loop
if mask (i) = '1' then
lo := i * 8;
hi := lo + 7;
t (hi downto lo) := val (hi downto lo);
end if;
end loop;
r_up <= t;
end process;
process (clk)
begin
if rising_edge (clk) then
r <= r_up;
end if;
end process;
res <= r;
end behav;
| gpl-2.0 | 1ad231db9645cf889a64c2cb2e2474d2 | 0.5553 | 3.133574 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1080/repro3_1.vhdl | 1 | 764 | library ieee;
use ieee.std_logic_1164.all;
entity repro3_1 is
port (
clk : std_logic;
led : out std_logic_vector(7 downto 0));
end;
architecture behav of repro3_1 is
constant LOOKUP_LEN : integer := 6;
constant LOOKUP_TABLE : std_logic_vector(LOOKUP_LEN*8-1 downto 0) :=
x"010205" & x"060708";
-- x"010205060708";
-- -> const_bit (0x5060708, 0x102)
begin
lookup_p : process(Clk)
variable idx : integer range 0 to LOOKUP_LEN-1 := LOOKUP_LEN-1;
begin
if rising_edge(Clk) then
led <= lookup_table(8*idx+7 downto 8*idx);
if idx /= 0 then
idx := idx - 1;
else
idx := LOOKUP_LEN-1;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 0767ac39660bf26a1ba4f6cf97fc850f | 0.562827 | 3.293103 | false | false | false | false |
tgingold/ghdl | testsuite/synth/fsm01/fsm_7s.vhdl | 1 | 1,259 | library ieee;
use ieee.std_logic_1164.all;
entity fsm_7s is
port (clk : std_logic;
rst : std_logic;
d : std_logic;
done : out std_logic);
end fsm_7s;
architecture behav of fsm_7s is
type state_t is (S0_1, S1_0, S2_0, S3_1, S4_0, S5_1, S6_0);
signal s : state_t;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
s <= S0_1;
done <= '0';
else
-- Reset by default
s <= S0_1;
done <= '0';
case s is
when S0_1 =>
if d = '1' then
s <= S1_0;
end if;
when S1_0 =>
if d = '0' then
s <= S2_0;
end if;
when S2_0 =>
if d = '0' then
s <= S3_1;
end if;
when S3_1 =>
if d = '1' then
s <= S4_0;
end if;
when S4_0 =>
if d = '0' then
s <= S5_1;
end if;
when S5_1 =>
if d = '1' then
s <= S6_0;
end if;
when S6_0 =>
if d = '0' then
done <= '1';
end if;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 201aaed1909468c2c7e3a00181ad96ed | 0.374901 | 3.187342 | false | false | false | false |
nickg/nvc | test/regress/protected8.vhd | 1 | 978 | entity protected8 is
end entity;
architecture test of protected8 is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
shared variable v : SharedCounter;
begin
p1: v.increment(n => 5);
p2: process is
begin
wait for 1 ns;
assert v.value = 5;
wait;
end process;
end architecture;
| gpl-3.0 | 014925302f150453dc30cdf449fa6ebf | 0.603272 | 4.964467 | false | false | false | false |
tgingold/ghdl | libraries/openieee/v87/std_logic_1164-body.vhdl | 2 | 19,746 | -- This -*- vhdl -*- file was generated from std_logic_1164-body.proto
-- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
-- on the specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
-- This is a template file. To avoid errors and duplication, the python
-- script build.py generate most of the bodies.
package body std_logic_1164 is
type table_1d is array (std_ulogic) of std_ulogic;
type table_2d is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution : table_2d :=
-- UX01ZWLH-
("UUUUUUUUU", -- U
"UXXXXXXXX", -- X
"UX0X0000X", -- 0
"UXX11111X", -- 1
"UX01ZWLHX", -- Z
"UX01WWWWX", -- W
"UX01LWLWX", -- L
"UX01HWWHX", -- H
"UXXXXXXXX" -- -
);
function resolved (s : std_ulogic_vector) return std_ulogic
is
variable res : std_ulogic := 'Z';
begin
for I in s'range loop
res := resolution (res, s (I));
end loop;
return res;
end resolved;
constant and_table : table_2d :=
-- UX01ZWLH-
("UU0UUU0UU", -- U
"UX0XXX0XX", -- X
"000000000", -- 0
"UX01XX01X", -- 1
"UX0XXX0XX", -- Z
"UX0XXX0XX", -- W
"000000000", -- L
"UX01XX01X", -- H
"UX0XXX0XX" -- -
);
constant nand_table : table_2d :=
-- UX01ZWLH-
("UU1UUU1UU", -- U
"UX1XXX1XX", -- X
"111111111", -- 0
"UX10XX10X", -- 1
"UX1XXX1XX", -- Z
"UX1XXX1XX", -- W
"111111111", -- L
"UX10XX10X", -- H
"UX1XXX1XX" -- -
);
constant or_table : table_2d :=
-- UX01ZWLH-
("UUU1UUU1U", -- U
"UXX1XXX1X", -- X
"UX01XX01X", -- 0
"111111111", -- 1
"UXX1XXX1X", -- Z
"UXX1XXX1X", -- W
"UX01XX01X", -- L
"111111111", -- H
"UXX1XXX1X" -- -
);
constant nor_table : table_2d :=
-- UX01ZWLH-
("UUU0UUU0U", -- U
"UXX0XXX0X", -- X
"UX10XX10X", -- 0
"000000000", -- 1
"UXX0XXX0X", -- Z
"UXX0XXX0X", -- W
"UX10XX10X", -- L
"000000000", -- H
"UXX0XXX0X" -- -
);
constant xor_table : table_2d :=
-- UX01ZWLH-
("UUUUUUUUU", -- U
"UXXXXXXXX", -- X
"UX01XX01X", -- 0
"UX10XX10X", -- 1
"UXXXXXXXX", -- Z
"UXXXXXXXX", -- W
"UX01XX01X", -- L
"UX10XX10X", -- H
"UXXXXXXXX" -- -
);
constant not_table : table_1d :=
-- UX01ZWLH-
"UX10XX10X";
function "and" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return and_table (l, r);
end "and";
function "nand" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return nand_table (l, r);
end "nand";
function "or" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return or_table (l, r);
end "or";
function "nor" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return nor_table (l, r);
end "nor";
function "xor" (l : std_ulogic; r : std_ulogic) return UX01 is
begin
return xor_table (l, r);
end "xor";
function "not" (l : std_ulogic) return UX01 is
begin
return not_table (l);
end "not";
function "and" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := and_table (la (I), ra (I));
end loop;
end if;
return res;
end "and";
function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nand_table (la (I), ra (I));
end loop;
end if;
return res;
end "nand";
function "or" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := or_table (la (I), ra (I));
end loop;
end if;
return res;
end "or";
function "nor" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nor_table (la (I), ra (I));
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_ulogic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xor";
function "not" (l : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to l'length);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not_table (la (I));
end loop;
return res;
end "not";
function "and" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := and_table (la (I), ra (I));
end loop;
end if;
return res;
end "and";
function "nand" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nand_table (la (I), ra (I));
end loop;
end if;
return res;
end "nand";
function "or" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := or_table (la (I), ra (I));
end loop;
end if;
return res;
end "or";
function "nor" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := nor_table (la (I), ra (I));
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
alias ra : std_logic_vector (1 to r'length) is r;
variable res : res_type;
begin
if la'length /= ra'length then
assert false
report "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for I in res_type'range loop
res (I) := xor_table (la (I), ra (I));
end loop;
end if;
return res;
end "xor";
function "not" (l : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to l'length);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not_table (la (I));
end loop;
return res;
end "not";
-- Conversion functions.
-- The result range (for vectors) is S'Length - 1 downto 0.
-- XMAP is return for values not in '0', '1', 'L', 'H'.
function to_bit (s : std_ulogic; xmap : bit := '0') return bit is
begin
case s is
when '0' | 'L' =>
return '0';
when '1' | 'H' =>
return '1';
when others =>
return xmap;
end case;
end to_bit;
type bit_to_std_table is array (bit) of std_ulogic;
constant bit_to_std : bit_to_std_table := "01";
function to_bitvector (s : std_ulogic_vector; xmap : bit := '0')
return bit_vector
is
subtype res_range is natural range s'length - 1 downto 0;
alias as : std_ulogic_vector (res_range) is s;
variable res : bit_vector (res_range);
variable b : bit;
begin
for I in res_range loop
-- Inline for efficiency.
case as (I) is
when '0' | 'L' =>
b := '0';
when '1' | 'H' =>
b := '1';
when others =>
b := xmap;
end case;
res (I) := b;
end loop;
return res;
end to_bitvector;
function to_bitvector (s : std_logic_vector; xmap : bit := '0')
return bit_vector
is
subtype res_range is natural range s'length - 1 downto 0;
alias as : std_logic_vector (res_range) is s;
variable res : bit_vector (res_range);
variable b : bit;
begin
for I in res_range loop
-- Inline for efficiency.
case as (I) is
when '0' | 'L' =>
b := '0';
when '1' | 'H' =>
b := '1';
when others =>
b := xmap;
end case;
res (I) := b;
end loop;
return res;
end to_bitvector;
function to_stdulogicvector (b : bit_vector) return std_ulogic_vector is
subtype res_range is natural range b'length - 1 downto 0;
alias ab : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for I in res_range loop
res (I) := bit_to_std (ab (I));
end loop;
return res;
end to_stdulogicvector;
function to_stdlogicvector (b : bit_vector) return std_logic_vector is
subtype res_range is natural range b'length - 1 downto 0;
alias ab : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for I in res_range loop
res (I) := bit_to_std (ab (I));
end loop;
return res;
end to_stdlogicvector;
function to_stdulogicvector (s : std_logic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (s'length - 1 downto 0);
begin
return res_type (s);
end to_stdulogicvector;
function to_stdlogicvector (s : std_ulogic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (s'length - 1 downto 0);
begin
return res_type (s);
end to_stdlogicvector;
function to_stdulogic (b : bit) return std_ulogic is
begin
return bit_to_std (b);
end to_stdulogic;
-- Normalization.
type table_std_x01 is array (std_ulogic) of X01;
constant std_to_x01 : table_std_x01 := ('U' | 'X' | 'Z' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1');
type table_bit_x01 is array (bit) of X01;
constant bit_to_x01 : table_bit_x01 := ('0' => '0',
'1' => '1');
type table_std_x01z is array (std_ulogic) of X01Z;
constant std_to_x01z : table_std_x01z := ('U' | 'X' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1',
'Z' => 'Z');
type table_std_ux01 is array (std_ulogic) of UX01;
constant std_to_ux01 : table_std_ux01 := ('U' => 'U',
'X' | 'Z' | 'W' | '-' => 'X',
'0' | 'L' => '0',
'1' | 'H' => '1');
function to_X01 (s : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01 (sa (i));
end loop;
return res;
end to_X01;
function to_X01 (s : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01 (sa (i));
end loop;
return res;
end to_X01;
function to_X01 (s : std_ulogic) return X01 is
begin
return std_to_x01 (s);
end to_X01;
function to_X01 (b : bit_vector) return std_ulogic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01;
function to_X01 (b : bit_vector) return std_logic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01;
function to_X01 (b : bit) return X01 is
begin
return bit_to_x01 (b);
end to_X01;
function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01z (sa (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (s : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_x01z (sa (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (s : std_ulogic) return X01Z is
begin
return std_to_x01z (s);
end to_X01Z;
function to_X01Z (b : bit_vector) return std_ulogic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (b : bit_vector) return std_logic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_X01Z;
function to_X01Z (b : bit) return X01Z is
begin
return bit_to_x01 (b);
end to_X01Z;
function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector
is
subtype res_type is std_ulogic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_ux01 (sa (i));
end loop;
return res;
end to_UX01;
function to_UX01 (s : std_logic_vector) return std_logic_vector
is
subtype res_type is std_logic_vector (1 to s'length);
alias sa : res_type is s;
variable res : res_type;
begin
for i in res_type'range loop
res (i) := std_to_ux01 (sa (i));
end loop;
return res;
end to_UX01;
function to_UX01 (s : std_ulogic) return UX01 is
begin
return std_to_ux01 (s);
end to_UX01;
function to_UX01 (b : bit_vector) return std_ulogic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_ulogic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_UX01;
function to_UX01 (b : bit_vector) return std_logic_vector
is
subtype res_range is natural range 1 to b'length;
alias ba : bit_vector (res_range) is b;
variable res : std_logic_vector (res_range);
begin
for i in res_range loop
res (i) := bit_to_x01 (ba (i));
end loop;
return res;
end to_UX01;
function to_UX01 (b : bit) return UX01 is
begin
return bit_to_x01 (b);
end to_UX01;
function rising_edge (signal s : std_ulogic) return boolean is
begin
return s'event
and to_x01 (s'last_value) = '0'
and to_x01 (s) = '1';
end rising_edge;
function falling_edge (signal s : std_ulogic) return boolean is
begin
return s'event
and to_x01 (s'last_value) = '1'
and to_x01 (s) = '0';
end falling_edge;
type std_x_array is array (std_ulogic) of boolean;
constant std_x : std_x_array := ('U' | 'X' | 'Z' | 'W' | '-' => true,
'0' | '1' | 'L' | 'H' => false);
function is_X (s : std_ulogic_vector) return boolean is
begin
for i in s'range loop
if std_x (s (i)) then
return true;
end if;
end loop;
return false;
end is_X;
function is_X (s : std_logic_vector) return boolean is
begin
for i in s'range loop
if std_x (s (i)) then
return true;
end if;
end loop;
return false;
end is_X;
function is_X (s : std_ulogic) return boolean is
begin
return std_x (s);
end is_X;
end std_logic_1164;
| gpl-2.0 | 79978af9e9fdf311dabca4fb3e3b4555 | 0.5748 | 3.238642 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1999.vhd | 4 | 1,970 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1999.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i01999ent IS
END c07s02b02x00p07n02i01999ent;
ARCHITECTURE c07s02b02x00p07n02i01999arch OF c07s02b02x00p07n02i01999ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 1 to 1000
units
A;
B = 10 A;
C = 10 B;
end units;
variable k : integer := 0;
variable m : PHYS := 10 A;
BEGIN
if (m = 1 B) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i01999"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i01999 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i01999arch;
| gpl-2.0 | 172cb05aa618d233ae75c0331771224c | 0.645685 | 3.654917 | false | true | false | false |
nickg/nvc | test/regress/genpack12.vhd | 1 | 739 | package sigpack is
generic (width : positive);
signal s : bit_vector(1 to width);
signal t : integer;
end package;
entity genpack12 is
end entity;
package p1 is new work.sigpack generic map (3);
use work.p1.all;
architecture test of genpack12 is
package p2 is new work.sigpack generic map (4);
package p3 is new work.sigpack generic map (5);
begin
s <= "110";
t <= 5;
p2.s <= "1010";
p2.t <= 7;
p3.s <= "11001";
p3.t <= 3;
check: process is
begin
wait for 1 ns;
assert s = "110";
assert p2.s = "1010";
assert p3.s = "11001";
assert t = 5;
assert p2.t = 7;
assert p3.t = 3;
wait;
end process;
end architecture;
| gpl-3.0 | 4cbbcb94a2177935c91bcf8c6f48ee34 | 0.562923 | 3.199134 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/asgn03.vhdl | 1 | 424 | library ieee;
use ieee.std_logic_1164.all;
entity asgn03 is
port (s0 : std_logic;
s1 : std_logic;
r : out std_logic_vector (2 downto 0));
end asgn03;
architecture behav of asgn03 is
begin
process (s0, s1) is
begin
r <= "000";
if s0 = '1' then
r (1) <= '1';
if s1 = '1' then
--r(1 downto 0) <= "01";
r(0) <= '1';
end if;
end if;
end process;
end behav;
| gpl-2.0 | 9e3a11397ecdcc0b3eb24884244c617b | 0.525943 | 2.807947 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1004/test2.vhdl | 1 | 1,194 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity test2 is
generic(
MEMORY_SIZE : natural := 32;
RAM_INIT_FILE : string := "firmware.hex"
);
port (addr : std_logic_vector (1 downto 0);
data : out std_logic_vector (63 downto 0));
end entity test2;
architecture behaviour of test2 is
type ram_t is array(0 to (MEMORY_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
impure function init_ram(name : STRING) return ram_t is
file ram_file : text open read_mode is name;
variable ram_line : line;
variable temp_word : std_logic_vector(63 downto 0);
variable temp_ram : ram_t := (others => (others => '0'));
begin
for i in 0 to (MEMORY_SIZE/8)-1 loop
exit when endfile(ram_file);
readline(ram_file, ram_line);
report "read: " & ram_line.all;
hread(ram_line, temp_word);
temp_ram(i) := temp_word;
end loop;
return temp_ram;
end function;
signal memory : ram_t := init_ram(RAM_INIT_FILE);
begin
data <= memory (to_integer (unsigned (addr)));
end architecture behaviour;
| gpl-2.0 | a9c32875700dae4384d8fc136532b2bd | 0.598827 | 3.501466 | false | true | false | false |
nickg/nvc | test/regress/issue428.vhd | 1 | 4,428 | library ieee;
use ieee.std_logic_1164.all;
package SYNC is
constant SYNC_MAX_PLUG_SIZE : integer := 4;
subtype SYNC_PLUG_NUM_TYPE is integer range 1 to SYNC_MAX_PLUG_SIZE;
subtype SYNC_SIG_TYPE is std_logic_vector(1 to SYNC_MAX_PLUG_SIZE);
subtype SYNC_REQ_TYPE is integer;
subtype SYNC_ACK_TYPE is std_logic;
type SYNC_REQ_VECTOR is array (INTEGER range <>) of SYNC_REQ_TYPE;
type SYNC_ACK_VECTOR is array (INTEGER range <>) of SYNC_ACK_TYPE;
component SYNC_SIG_DRIVER
generic (
PLUG_NUM : SYNC_PLUG_NUM_TYPE := 1
);
port (
SYNC : inout SYNC_SIG_TYPE := (others => 'Z'); -- Was 'U'
REQ : in SYNC_REQ_TYPE;
ACK : out SYNC_ACK_TYPE
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.SYNC.all;
entity SYNC_SIG_DRIVER_SUB_UNIT is
port (
SYNC_I : in SYNC_SIG_TYPE;
SYNC_O : out std_logic;
REQ : in SYNC_REQ_TYPE;
ACK : out SYNC_ACK_TYPE
);
end SYNC_SIG_DRIVER_SUB_UNIT;
architecture MODEL of SYNC_SIG_DRIVER_SUB_UNIT is
function ALL_ONE(SYNC : SYNC_SIG_TYPE) return boolean is
variable sync_vec : SYNC_SIG_TYPE;
constant all_1 : SYNC_SIG_TYPE := (others => '1');
begin
for i in SYNC'range loop
if (SYNC(i) = '0') then
sync_vec(i) := '0';
else
sync_vec(i) := '1';
end if;
end loop;
if (sync_vec = all_1) then
return true;
else
return false;
end if;
end function;
begin
process begin
SYNC_O <= 'Z';
ACK <= '0';
SYNC_LOOP: loop
if (REQ > 0) then
SYNC_O <= 'H';
wait until (ALL_ONE(SYNC_I)); -- This line causes an error
SYNC_O <= '0';
ACK <= '1';
wait until (REQ = 0);
ACK <= '0';
elsif (REQ = 0) then
SYNC_O <= '0';
else
SYNC_O <= 'Z';
end if;
wait on REQ;
end loop;
end process;
end MODEL;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library WORK;
use WORK.SYNC.all;
entity SYNC_SIG_DRIVER is
generic (
PLUG_NUM : SYNC_PLUG_NUM_TYPE := 1
);
port (
SYNC : inout SYNC_SIG_TYPE := (others => 'Z'); -- Was 'U'
REQ : in SYNC_REQ_TYPE;
ACK : out SYNC_ACK_TYPE
);
end SYNC_SIG_DRIVER;
architecture MODEL of SYNC_SIG_DRIVER is
component SYNC_SIG_DRIVER_SUB_UNIT is
port (
SYNC_I : in SYNC_SIG_TYPE;
SYNC_O : out std_logic;
REQ : in SYNC_REQ_TYPE;
ACK : out SYNC_ACK_TYPE
);
end component;
begin
U: SYNC_SIG_DRIVER_SUB_UNIT
port map(
SYNC_I => SYNC,
SYNC_O => SYNC(PLUG_NUM),
REQ => REQ,
ACK => ACK
);
end MODEL;
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.SYNC.all;
entity issue428 is
end issue428;
architecture MODEL of issue428 is
constant PLUG_SIZE : integer := 2;
signal SYNC : SYNC_SIG_TYPE;
signal REQ : SYNC_REQ_VECTOR(1 to PLUG_SIZE);
signal ACK : SYNC_ACK_VECTOR(1 to PLUG_SIZE);
begin
PLUG : for i in 1 to PLUG_SIZE generate
DRIVER : SYNC_SIG_DRIVER
generic map (PLUG_NUM => i)
port map (SYNC => SYNC, REQ => REQ(i), ACK => ACK(i));
end generate;
process begin
REQ(1) <= 0;
wait;
end process;
process begin
assert sync = "UUUU";
wait for 0 ns;
assert sync = "UUUU";
wait for 5 ns;
REQ(2) <= 1;
wait for 10 ns;
report std_logic'image(sync(1));
report std_logic'image(sync(2));
report std_logic'image(sync(3));
report std_logic'image(sync(4));
assert sync = "XX11"; -- Aldec has UXUU (with SYNC default of
-- 'U')
assert ack(2) = '1';
wait;
end process;
sync <= (others => '1') after 10 ns;
end MODEL;
| gpl-3.0 | 126728ce0788794f49d03bef41b2809d | 0.494128 | 3.562349 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/synth/design_1_axi_dma_0_0.vhd | 1 | 26,132 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_9;
USE axi_dma_v7_1_9.axi_dma;
ENTITY design_1_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_dma_0_0;
ARCHITECTURE design_1_axi_dma_0_0_arch OF design_1_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_dma_0_0_arch : ARCHITECTURE IS "design_1_axi_dma_0_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "design_1_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=23,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_" &
"AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=8,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=8,C_INCLUDE_S2MM_DRE=1,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 8,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 8,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_1_axi_dma_0_0_arch;
| gpl-3.0 | dbb6ebc79172eadd52ab8939ff13602f | 0.677751 | 2.744958 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/OSVVM/ScoreboardGenericPkg.vhd | 1 | 61,844 | --
-- File Name: ScoreBoardGenericPkg.vhd
-- Design Unit Name: ScoreBoardGenericPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
--
-- Description:
-- Defines types and methods to implement a FIFO based Scoreboard
-- Defines type ScoreBoardPType
-- Defines methods for putting values the scoreboard
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Latest standard version available at:
-- http://www.SynthWorks.com/downloads
--
-- Revision History:
-- Date Version Description
-- 12/2006: 2006.12 Initial revision
-- 08/2010 2010.08 Added Tailpointer
-- 05/2012 2012.05 Changed FIFO to store pointers to ExpectedType
-- Allows usage of unconstrained arrays
-- 08/2012 2012.08 Added Type and Subprogram Generics
-- 08/2013 2013.08 Generics: to_string replaced write, Match replaced check
-- Added Tags - Experimental
-- Added Array of Scoreboards
-- 09/2013 2013.09 Added file handling, Check Count, Finish Status
-- Find, Flush
-- 06/2015 2015.06 Added Alerts, SetAlertLogID, Revised LocalPush, GetDropCount,
-- Deprecated SetFinish and ReportMode - REPORT_NONE, FileOpen
-- Deallocate, Initialized, Function SetName
-- 11/2016 2016.11 Released as part of OSVVM
--
--
--
-- Copyright (c) 2006 - 2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TranscriptPkg.all ;
use work.AlertLogPkg.all ;
use work.NamePkg.all ;
package ScoreboardGenericPkg is
generic (
type ExpectedType ;
type ActualType ;
function Match(Actual : ActualType ; -- defaults
Expected : ExpectedType) return boolean ; -- is "=" ;
function expected_to_string(A : ExpectedType) return string ; -- is to_string ;
function actual_to_string (A : ActualType) return string -- is to_string ;
) ;
-- -- For a VHDL-2002 package, comment out the generics and
-- -- uncomment the following, it replaces a generic instance of the package.
-- -- As a result, you will have multiple copies of the entire package.
-- -- Inconvenient, but ok as it still works the same.
-- subtype ExpectedType is std_logic_vector ;
-- subtype ActualType is std_logic_vector ;
-- alias Match is std_match [ActualType, ExpectedType return boolean] ; -- for std_logic_vector
-- alias expected_to_string is to_hstring [ExpectedType return string]; -- VHDL-2008
-- alias actual_to_string is to_hstring [ActualType return string]; -- VHDL-2008
-- ScoreboardReportType is deprecated
-- Replaced by Affirmations. ERROR is the default. ALL turns on PASSED flag
type ScoreboardReportType is (REPORT_ERROR, REPORT_ALL, REPORT_NONE) ; -- replaced by affirmations
type ScoreBoardPType is protected
------------------------------------------------------------
-- Emulate arrays of scoreboards
procedure SetArrayIndex(L, R : integer) ; -- supports integer indices
procedure SetArrayIndex(R : natural) ; -- indicies 1 to R
impure function GetArrayIndex return integer_vector ;
impure function GetArrayLength return natural ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Push (
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Push (
constant Index : in integer ;
constant Item : in ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Push (
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- ------------------------------------------------------------
-- -- Push items into the scoreboard/FIFO
-- -- Function form supports chaining of operations
-- -- In 2013, this caused overloading issues in some simulators, will retest later
--
-- -- Simple Scoreboard, no tag
-- impure function Push (Item : ExpectedType) return ExpectedType ;
--
-- -- Simple Tagged Scoreboard
-- impure function Push (
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Scoreboards, no tag
-- impure function Push (
-- constant Index : in integer ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Tagged Scoreboards
-- impure function Push (
-- constant Index : in integer ;
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ; -- for chaining of operations
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) ;
-- Simple Tagged Scoreboard
procedure Check (
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Array of Scoreboards, no tag
procedure Check (
constant Index : in integer ;
constant ActualData : in ActualType
) ;
-- Array of Tagged Scoreboards
procedure Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Pop (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Pop (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- ------------------------------------------------------------
-- -- Pop the top item (FIFO) from the scoreboard/FIFO
-- -- Function form supports chaining of operations
-- -- In 2013, this caused overloading issues in some simulators, will retest later
--
-- -- Simple Scoreboard, no tag
-- impure function Pop return ExpectedType ;
--
-- -- Simple Tagged Scoreboard
-- impure function Pop (
-- constant Tag : in string
-- ) return ExpectedType ;
--
-- -- Array of Scoreboards, no tag
-- impure function Pop (Index : integer) return ExpectedType ;
--
-- -- Array of Tagged Scoreboards
-- impure function Pop (
-- constant Index : in integer ;
-- constant Tag : in string
-- ) return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
impure function Empty return boolean ; -- Simple
impure function Empty (Tag : String) return boolean ; -- Simple, Tagged
impure function Empty (Index : integer) return boolean ; -- Array
impure function Empty (Index : integer; Tag : String) return boolean ; -- Array, Tagged
------------------------------------------------------------
-- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
procedure SetAlertLogID(Index : Integer ; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
-- Use when an AlertLogID is used by multiple items (BFM or Scoreboards). See also AlertLogPkg.GetAlertLogID
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) ;
procedure SetAlertLogID (A : AlertLogIDType) ;
impure function GetAlertLogID(Index : Integer) return AlertLogIDType ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
-- Set a scoreboard name.
-- Used when scoreboard AlertLogID is shared between different sources.
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
impure function GetName (DefaultName : string := "Scoreboard") return string ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount return integer ; -- Simple, with or without tags
impure function GetItemCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items checked by scoreboard
impure function GetCheckCount return integer ; -- Simple, with or without tags
impure function GetCheckCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount return integer ; -- Simple, with or without tags
impure function GetDropCount (Index : integer) return integer ; -- Arrays, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
-- Array of Simple Scoreboards
impure function Find (
constant Index : in integer ;
constant ActualData : in ActualType
) return integer ;
-- Array of Tagged Scoreboards
impure function Find (
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboard
procedure Flush (
constant ItemNumber : in integer
) ;
-- Tagged Scoreboard - only removes items that also match the tag
procedure Flush (
constant Tag : in string ;
constant ItemNumber : in integer
) ;
-- Array of Simple Scoreboards
procedure Flush (
constant Index : in integer ;
constant ItemNumber : in integer
) ;
-- Array of Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate ; -- Deletes all allocated items
procedure Initialize ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Use alerts directly instead.
-- AlertIF(SB.GetCheckCount < 10, ....) ;
-- AlertIf(Not SB.Empty, ...) ;
------------------------------------------------------------
-- Set alerts if scoreboard not empty or if CheckCount <
-- Use if need to check empty or CheckCount for a specific scoreboard.
-- Simple Scoreboards, with or without tag
procedure CheckFinish (
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
-- Array of Scoreboards, with or without tag
procedure CheckFinish (
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Simple Scoreboards, with or without tag
impure function GetErrorCount return integer ;
-- Array of Scoreboards, with or without tag
impure function GetErrorCount(Index : integer) return integer ;
------------------------------------------------------------
-- Error count manipulation
-- IncErrorCount - not recommended, use alerts instead - may be deprecated in the future
procedure IncErrorCount ; -- Simple, with or without tags
procedure IncErrorCount (Index : integer) ; -- Arrays, with or without tags
-- Clear error counter. Caution does not change AlertCounts, must also use AlertLogPkg.ClearAlerts
procedure SetErrorCountZero ; -- Simple, with or without tags
procedure SetErrorCountZero (Index : integer) ; -- Arrays, with or without tags
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Names changed. Maintained for backward compatibility - would prefer an alias
------------------------------------------------------------
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) ; -- Replaced by TranscriptPkg.TranscriptOpen
procedure PutExpectedData (ExpectedData : ExpectedType) ; -- Replaced by push
procedure CheckActualData (ActualData : ActualType) ; -- Replaced by Check
impure function GetItemNumber return integer ; -- Replaced by GetItemCount
procedure SetMessage (MessageIn : String) ; -- Replaced by SetName
impure function GetMessage return string ; -- Replaced by GetName
-- Deprecated and may be deleted in a future revision
procedure SetFinish ( -- Replaced by CheckFinish
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
procedure SetFinish ( -- Replaced by CheckFinish
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (ReportModeIn : ScoreboardReportType) ;
impure function GetReportMode return ScoreboardReportType ;
end protected ScoreBoardPType ;
end ScoreboardGenericPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body ScoreboardGenericPkg is
type ScoreBoardPType is protected body
type ExpectedPointerType is access ExpectedType ;
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
ItemNumber : integer ;
TagPtr : line ;
ExpectedPtr : ExpectedPointerType ;
NextPtr : ListPointerType ;
end record ;
type ListArrayType is array (integer range <>) of ListPointerType ;
type ListArrayPointerType is access ListArrayType ;
variable ArrayLengthVar : integer := 1 ;
variable HeadPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
variable TailPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
variable PopListPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
type IntegerArrayType is array (integer range <>) of Integer ;
type IntegerArrayPointerType is access IntegerArrayType ;
variable ErrCntVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable DropCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable ItemNumberVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable CheckCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable AlertLogIDVar : IntegerArrayPointerType := new IntegerArrayType'(1 => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
variable NameVar : NamePType ;
variable ReportModeVar : ScoreboardReportType ;
variable FirstIndexVar : integer := 1 ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName (DefaultName : string := "Scoreboard") return string is
------------------------------------------------------------
begin
return NameVar.Get(DefaultName) ;
end function GetName ;
------------------------------------------------------------
procedure SetReportMode (ReportModeIn : ScoreboardReportType) is
------------------------------------------------------------
begin
ReportModeVar := ReportModeIn ;
if ReportModeVar = REPORT_ALL then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: To turn off REPORT_ALL, use osvvm.AlertLogPkg.SetLogEnable(PASSED, FALSE)", WARNING) ;
for i in AlertLogIDVar'range loop
SetLogEnable(AlertLogIDVar(i), PASSED, TRUE) ;
end loop ;
end if ;
if ReportModeVar = REPORT_NONE then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: ReportMode REPORT_NONE has been deprecated and will be removed in next revision. Please contact OSVVM architect Jim Lewis if you need this capability.", WARNING) ;
end if ;
end procedure SetReportMode ;
------------------------------------------------------------
impure function GetReportMode return ScoreboardReportType is
------------------------------------------------------------
begin
return ReportModeVar ;
end function GetReportMode ;
------------------------------------------------------------
procedure SetArrayIndex(L, R : integer) is
------------------------------------------------------------
variable OldHeadPointer, OldTailPointer, OldPopListPointer : ListArrayPointerType ;
variable OldErrCnt, OldDropCount, OldItemNumber, OldCheckCount, OldAlertLogIDVar : IntegerArrayPointerType ;
variable Min, Max, Len, OldLen, OldMax : integer ;
begin
Min := minimum(L, R) ;
Max := maximum(L, R) ;
OldLen := ArrayLengthVar ;
OldMax := Min + ArrayLengthVar - 1 ;
Len := Max - Min + 1 ;
ArrayLengthVar := Len ;
if Len >= OldLen then
FirstIndexVar := Min ;
OldHeadPointer := HeadPointer ;
HeadPointer := new ListArrayType(Min to Max) ;
if OldHeadPointer /= NULL then
HeadPointer(Min to OldMax) := OldHeadPointer.all ; -- (OldHeadPointer'range) ;
Deallocate(OldHeadPointer) ;
end if ;
OldTailPointer := TailPointer ;
TailPointer := new ListArrayType(Min to Max) ;
if OldTailPointer /= NULL then
TailPointer(Min to OldMax) := OldTailPointer.all ;
Deallocate(OldTailPointer) ;
end if ;
OldPopListPointer := PopListPointer ;
PopListPointer := new ListArrayType(Min to Max) ;
if OldPopListPointer /= NULL then
PopListPointer(Min to OldMax) := OldPopListPointer.all ;
Deallocate(OldPopListPointer) ;
end if ;
OldErrCnt := ErrCntVar ;
ErrCntVar := new IntegerArrayType'(Min to Max => 0) ;
if OldErrCnt /= NULL then
ErrCntVar(Min to OldMax) := OldErrCnt.all ;
Deallocate(OldErrCnt) ;
end if ;
OldDropCount := DropCountVar ;
DropCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldDropCount /= NULL then
DropCountVar(Min to OldMax) := OldDropCount.all ;
Deallocate(OldDropCount) ;
end if ;
OldItemNumber := ItemNumberVar ;
ItemNumberVar := new IntegerArrayType'(Min to Max => 0) ;
if OldItemNumber /= NULL then
ItemNumberVar(Min to OldMax) := OldItemNumber.all ;
Deallocate(OldItemNumber) ;
end if ;
OldCheckCount := CheckCountVar ;
CheckCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldCheckCount /= NULL then
CheckCountVar(Min to OldMax) := OldCheckCount.all ;
Deallocate(OldCheckCount) ;
end if ;
OldAlertLogIDVar := AlertLogIDVar ;
AlertLogIDVar := new IntegerArrayType'(Min to Max => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
if OldAlertLogIDVar /= NULL then
AlertLogIDVar(Min to OldMax) := OldAlertLogIDVar.all ;
Deallocate(OldAlertLogIDVar) ;
end if ;
elsif Len < OldLen then
report "ScoreboardGenericPkg: SetArrayIndex, new array Length <= current array length"
severity failure ;
end if ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure SetArrayIndex(R : natural) is
------------------------------------------------------------
begin
SetArrayIndex(1, R) ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
variable CurListPtr, LastListPtr : ListPointerType ;
begin
for Index in HeadPointer'range loop
-- Deallocate contents in the scoreboards
CurListPtr := HeadPointer(Index) ;
while CurListPtr /= Null loop
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
LastListPtr := CurListPtr ;
CurListPtr := CurListPtr.NextPtr ;
Deallocate(LastListPtr) ;
end loop ;
end loop ;
for Index in PopListPointer'range loop
-- Deallocate PopListPointer - only has single element
CurListPtr := PopListPointer(Index) ;
if CurListPtr /= NULL then
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
deallocate(CurListPtr) ;
end if ;
end loop ;
-- Deallocate arrays of pointers
Deallocate(HeadPointer) ;
Deallocate(TailPointer) ;
Deallocate(PopListPointer) ;
-- Deallocate supporting arrays
Deallocate(ErrCntVar) ;
Deallocate(DropCountVar) ;
Deallocate(ItemNumberVar) ;
Deallocate(CheckCountVar) ;
Deallocate(AlertLogIDVar) ;
-- Deallocate NameVar - NamePType
NameVar.Deallocate ;
ArrayLengthVar := 0 ;
end procedure Deallocate ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize is
------------------------------------------------------------
begin
SetArrayIndex(1, 1) ;
end procedure Initialize ;
------------------------------------------------------------
impure function GetArrayIndex return integer_vector is
------------------------------------------------------------
begin
return (1 => HeadPointer'left, 2 => HeadPointer'right) ;
end function GetArrayIndex ;
------------------------------------------------------------
impure function GetArrayLength return natural is
------------------------------------------------------------
begin
return ArrayLengthVar ; -- HeadPointer'length ;
end function GetArrayLength ;
------------------------------------------------------------
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Index : Integer ; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Index : Integer) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(Index) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(FirstIndexVar) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function LocalOutOfRange(
------------------------------------------------------------
constant Index : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_SCOREBOARD_ALERTLOG_ID, Index < HeadPointer'Low or Index > HeadPointer'High,
GetName & " " & Name & " Index: " & to_string(Index) &
"is not in the range (" & to_string(HeadPointer'Low) &
"to " & to_string(HeadPointer'High) & ")",
FAILURE ) ;
end function LocalOutOfRange ;
------------------------------------------------------------
procedure LocalPush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
ItemNumberVar(Index) := ItemNumberVar(Index) + 1 ;
ExpectedPtr := new ExpectedType'(Item) ;
TagPtr := new string'(Tag) ;
if HeadPointer(Index) = NULL then
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- HeadPointer(Index) := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
HeadPointer(Index) := new ListType ;
HeadPointer(Index).ItemNumber := ItemNumberVar(Index) ;
HeadPointer(Index).TagPtr := TagPtr ;
HeadPointer(Index).ExpectedPtr := ExpectedPtr ;
HeadPointer(Index).NextPtr := NULL ;
TailPointer(Index) := HeadPointer(Index) ;
else
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- TailPointer(Index).NextPtr := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
TailPointer(Index).NextPtr := new ListType ;
TailPointer(Index).NextPtr.ItemNumber := ItemNumberVar(Index) ;
TailPointer(Index).NextPtr.TagPtr := TagPtr ;
TailPointer(Index).NextPtr.ExpectedPtr := ExpectedPtr ;
TailPointer(Index).NextPtr.NextPtr := NULL ;
TailPointer(Index) := TailPointer(Index).NextPtr ;
end if ;
end procedure LocalPush ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) is
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Push (Item : ExpectedType) return ExpectedType is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Local Only
-- Pops highest element matching Tag into PopListPointer(Index)
procedure LocalPop (Index : integer ; Tag : string; Name : string) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Pop/Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during " & Name, FAILURE) ;
return ;
end if ;
-- deallocate previous pointer
if PopListPointer(Index) /= NULL then
deallocate(PopListPointer(Index).TagPtr) ;
deallocate(PopListPointer(Index).ExpectedPtr) ;
deallocate(PopListPointer(Index)) ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
PopListPointer(Index) := HeadPointer(Index) ;
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Pop/Check (" & Name & "), tag: " & Tag & " not found", FAILURE) ;
exit ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
PopListPointer(Index) := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
if CurPtr.NextPtr = NULL then
TailPointer(Index) := CurPtr ;
end if ;
exit ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end procedure LocalPop ;
------------------------------------------------------------
-- Local Only
procedure LocalCheck (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable CurrentItem : integer ;
variable WriteBuf : line ;
variable FoundError : boolean ;
begin
CheckCountVar(Index) := CheckCountVar(Index) + 1 ;
ExpectedPtr := PopListPointer(Index).ExpectedPtr ;
CurrentItem := PopListPointer(Index).ItemNumber ;
if not Match(ActualData, ExpectedPtr.all) then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
FoundError := TRUE ;
else
FoundError := FALSE ;
end if ;
IncAffirmCheckCount ;
-- if FoundError or ReportModeVar = REPORT_ALL then
if FoundError or GetLogEnable(AlertLogIDVar(Index), PASSED) then
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
write(WriteBuf, " (" & to_string(Index) & ") ") ;
end if ;
write(WriteBuf, " Expected: " & expected_to_string(ExpectedPtr.all)) ;
write(WriteBuf, " Actual: " & actual_to_string(ActualData)) ;
if PopListPointer(Index).TagPtr.all /= "" then
write(WriteBuf, " Tag: " & PopListPointer(Index).TagPtr.all) ;
end if;
write(WriteBuf, " Item Number: " & to_string(CurrentItem)) ;
if FoundError then
if ReportModeVar /= REPORT_NONE then
-- Affirmation Failed
Alert(AlertLogIDVar(Index), WriteBuf.all, ERROR) ;
else
-- Affirmation Failed, but silent, unless in DEBUG mode
Log(AlertLogIDVar(Index), "ERROR " & WriteBuf.all, DEBUG) ;
IncAlertCount(AlertLogIDVar(Index)) ; -- Silent Counted Alert
end if ;
else
-- Affirmation passed
Log(AlertLogIDVar(Index), WriteBuf.all, PASSED) ;
end if ;
deallocate(WriteBuf) ;
end if ;
end procedure LocalCheck ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) is
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) is
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Pop (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, Tag, "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType is
------------------------------------------------------------
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, "", "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Pop (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Empty (Index : integer; Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := HeadPointer(Index) ;
while CurPtr /= NULL loop
if CurPtr.TagPtr.all = Tag then
return FALSE ; -- Found Tag
end if ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return TRUE ; -- Tag not found
end function Empty ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Empty (Index : integer) return boolean is
------------------------------------------------------------
begin
return HeadPointer(Index) = NULL ;
end function Empty ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Empty (Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
return Empty(FirstIndexVar, Tag) ;
end function Empty ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Empty return boolean is
------------------------------------------------------------
begin
return HeadPointer(FirstIndexVar) = NULL ;
end function Empty ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
variable EmptyError : Boolean ;
variable WriteBuf : line ;
begin
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
if WriteBuf.all /= "" then
swrite(WriteBuf, " ") ;
end if ;
write(WriteBuf, "Index(" & to_string(Index) & "), ") ;
else
if WriteBuf.all /= "" then
swrite(WriteBuf, ", ") ;
end if ;
end if ;
if FinishEmpty then
AffirmIf(AlertLogIDVar(Index), Empty(Index), WriteBuf.all & "Checking Empty: " & to_string(Empty(Index)) &
" FinishEmpty: " & to_string(FinishEmpty)) ;
if not Empty(Index) then
-- Increment internal count on FinishEmpty Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
end if ;
AffirmIf(AlertLogIDVar(Index), CheckCountVar(Index) >= FinishCheckCount, WriteBuf.all &
"Checking CheckCount: " & to_string(CheckCountVar(Index)) &
" >= Expected: " & to_string(FinishCheckCount)) ;
if not (CheckCountVar(Index) >= FinishCheckCount) then
-- Increment internal count on FinishCheckCount Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
deallocate(WriteBuf) ;
end procedure CheckFinish ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
for AlertLogID in AlertLogIDVar'range loop
CheckFinish(AlertLogID, FinishCheckCount, FinishEmpty) ;
end loop ;
end procedure CheckFinish ;
------------------------------------------------------------
impure function GetErrorCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ErrCntVar(Index) ;
end function GetErrorCount ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
variable TotalErrorCount : integer := 0 ;
begin
for Index in AlertLogIDVar'range loop
TotalErrorCount := TotalErrorCount + GetErrorCount(Index) ;
end loop ;
return TotalErrorCount ;
end function GetErrorCount ;
------------------------------------------------------------
procedure IncErrorCount (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
IncAlertCount(AlertLogIDVar(Index), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure IncErrorCount is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := ErrCntVar(FirstIndexVar) + 1 ;
IncAlertCount(AlertLogIDVar(FirstIndexVar), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure SetErrorCountZero (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := 0;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetErrorCountZero is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := 0 ;
end procedure SetErrorCountZero ;
------------------------------------------------------------
impure function GetItemCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetCheckCount (Index : integer) return integer is
------------------------------------------------------------
begin
return CheckCountVar(Index) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetCheckCount return integer is
------------------------------------------------------------
begin
return CheckCountVar(FirstIndexVar) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetDropCount (Index : integer) return integer is
------------------------------------------------------------
begin
return DropCountVar(Index) ;
end function GetDropCount ;
------------------------------------------------------------
impure function GetDropCount return integer is
------------------------------------------------------------
begin
return DropCountVar(FirstIndexVar) ;
end function GetDropCount ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
Alert(AlertLogIDVar(Index), "OSVVM.ScoreboardGenericPkg.SetFinish: Deprecated and removed. See CheckFinish", ERROR) ;
end procedure SetFinish ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
SetFinish(FirstIndexVar, FCheckCount, FEmpty, FStatus) ;
end procedure SetFinish ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Find Element with Matching Tag and ActualData
-- Returns integer'left if no match found
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return integer'left ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Failed to find it
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
if Tag /= "" then
Alert(AlertLogIDVar(Index),
GetName & " Did not find Tag: " & Tag & " and Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
else
Alert(AlertLogIDVar(Index),
GetName & " Did not find Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
end if ;
return integer'left ;
elsif CurPtr.TagPtr.all = Tag and
Match(ActualData, CurPtr.ExpectedPtr.all) then
-- Found it. Return Index.
return CurPtr.ItemNumber ;
else -- Descend
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end function Find ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return integer is
begin
return Find(Index, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Simple Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
variable CurPtr, RemovePtr, LastPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
LastPtr := NULL ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif CurPtr.TagPtr.all = Tag then
if ItemNumber >= CurPtr.ItemNumber then
-- remove it
RemovePtr := CurPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := LastPtr ;
end if ;
if CurPtr = HeadPointer(Index) then
HeadPointer(Index) := CurPtr.NextPtr ;
else -- if LastPtr /= NULL then
LastPtr.NextPtr := LastPtr.NextPtr.NextPtr ;
end if ;
CurPtr := CurPtr.NextPtr ;
-- LastPtr := LastPtr ; -- no change
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(RemovePtr.TagPtr) ;
deallocate(RemovePtr.ExpectedPtr) ;
deallocate(RemovePtr) ;
else
-- Done
return ;
end if ;
else
-- Descend
LastPtr := CurPtr ;
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant ItemNumber : in integer
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif ItemNumber >= CurPtr.ItemNumber then
-- Descend, Check Tail, Deallocate
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := NULL ;
end if ;
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(CurPtr.TagPtr) ;
deallocate(CurPtr.ExpectedPtr) ;
deallocate(CurPtr) ;
CurPtr := HeadPointer(Index) ;
else
-- Done
return ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Simple Scoreboard
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
------------------------------------------------------------
-- Remaining Deprecated.
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
-- Use TranscriptPkg.TranscriptOpen
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
-- WriteFileInit := TRUE ;
-- file_open( WriteFile , FileName , OpenKind );
TranscriptOpen(FileName, OpenKind) ;
end procedure FileOpen ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure PutExpectedData (ExpectedData : ExpectedType) is
------------------------------------------------------------
begin
Push(ExpectedData) ;
end procedure PutExpectedData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure CheckActualData (ActualData : ActualType) is
------------------------------------------------------------
begin
Check(ActualData) ;
end procedure CheckActualData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetItemNumber return integer is
------------------------------------------------------------
begin
return GetItemCount(FirstIndexVar) ;
end GetItemNumber ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure SetMessage (MessageIn : String) is
------------------------------------------------------------
begin
-- deallocate(Message) ;
-- Message := new string'(MessageIn) ;
SetName(MessageIn) ;
end procedure SetMessage ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetMessage return string is
------------------------------------------------------------
begin
-- return Message.all ;
return GetName("Scoreboard") ;
end function GetMessage ;
end protected body ScoreBoardPType ;
end ScoreboardGenericPkg ; | gpl-2.0 | 2e4786f0cae5498015cd6b6e3c8159b3 | 0.505773 | 5.884301 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/sub_220.vhd | 2 | 1,730 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_220 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_220;
architecture augh of sub_220 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
end architecture;
| gpl-2.0 | 078f63463221d06d05907649d39de984 | 0.624277 | 2.578241 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd | 4 | 1,399 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_S_R_flipflop is
end entity tb_S_R_flipflop;
architecture test of tb_S_R_flipflop is
signal s, r : bit := '0';
signal q, q_n : bit;
begin
dut : entity work.S_R_flipflop(functional)
port map ( s => s, r => r, q => q, q_n => q_n );
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 0210a5887d3e572c37830bada9aff8a2 | 0.658327 | 3.454321 | false | true | false | false |
tgingold/ghdl | testsuite/synth/case02/tb_case01.vhdl | 1 | 559 | entity tb_case01 is
end tb_case01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_case01 is
signal a : std_logic_vector (1 downto 0);
signal o : std_logic_vector (1 downto 0);
signal clk : std_logic;
begin
dut: entity work.case01
port map (a, clk, o);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= "00";
pulse;
a <= "10";
pulse;
assert o = "00" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | f7a8f5f9104fe138b99632217bb26c7f | 0.592129 | 3.212644 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2001.vhd | 4 | 2,014 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2001.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i02001ent IS
END c07s02b02x00p07n02i02001ent;
ARCHITECTURE c07s02b02x00p07n02i02001arch OF c07s02b02x00p07n02i02001ent IS
BEGIN
TESTING: PROCESS
type CHAR_RECORD is record
C1, C2, C3 : CHARACTER;
end record;
variable k : integer := 0;
variable m : CHAR_RECORD := ('a','b','c');
BEGIN
if (m = CHAR_RECORD'('a','b','c')) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i02001"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i02001 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i02001arch;
| gpl-2.0 | 9b046c6f4a03ac8e2e56cd20b1c03a28 | 0.641013 | 3.736549 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2292.vhd | 4 | 4,155 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2292.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02292ent IS
END c07s02b06x00p32n01i02292ent;
ARCHITECTURE c07s02b06x00p32n01i02292arch OF c07s02b06x00p32n01i02292ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
wait for 5 ns;
assert ((1 A * 10.0) > 1 A)
report "Assertion error.(1)";
assert ((1 nm * 1000.0) > 1 nm)
report "Assertion error.(2)";
assert ((1 um * 1000.0) > 1 um)
report "Assertion error.(3)";
assert ((1 mm * 10.0) > 1 mm)
report "Assertion error.(4)";
assert ((10.0 * 1 A) > 1 A)
report "Assertion error.(6)";
assert ((1000.0 * 1 nm) > 1 nm)
report "Assertion error.(7)";
assert ((1000.0 * 1 um) > 1 um)
report "Assertion error.(8)";
assert ((10.0 * 1 mm) > 1 mm)
report "Assertion error.(9)";
assert ((1 A * 254000.0) > 1 A)
report "Assertion error.(16)";
assert ((1 mil * 1000.0) > 1 mil)
report "Assertion error.(17)";
assert ((254000.0 * 1 A) > 1 A)
report "Assertion error.(20)";
assert ((1000.0 * 1 mil) > 1 mil)
report "Assertion error.(21)";
assert NOT( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***PASSED TEST: c07s02b06x00p32n01i02292"
severity NOTE;
assert ( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***FAILED TEST: c07s02b06x00p32n01i02292 - Multiplication of a physical type by an floating point test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02292arch;
| gpl-2.0 | 02fbab0aaececbd4cfd7df7476e50126 | 0.510951 | 3.491597 | false | true | false | false |
tgingold/ghdl | libraries/openieee/math_real-body.vhdl | 2 | 4,817 | -- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.2 math_real package body.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
package body MATH_REAL is
function SIGN (X : REAL) return REAL is
begin
if X > 0.0 then
return 1.0;
elsif X < 0.0 then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : REAL) return REAL is
begin
assert false severity failure;
end CEIL;
function FLOOR (X : REAL) return REAL is
begin
assert false severity failure;
end FLOOR;
function ROUND (X : REAL) return REAL is
begin
assert false severity failure;
end ROUND;
function TRUNC (X : REAL) return REAL is
begin
assert false severity failure;
end;
function fmod (X, Y : REAL) return REAL;
attribute foreign of fmod : function is "VHPIDIRECT fmod";
function fmod (X, Y : REAL) return REAL is
begin
assert false severity failure;
end;
function "mod" (X, Y : REAL) return REAL
is
variable res : real;
begin
assert y /= 0.0 report "ieee.math_real.""mod"": dividend is 0.0"
severity failure;
res := fmod (x, y);
if res /= 0.0 then
if x > 0.0 xor y > 0.0 then
res := res + y;
end if;
end if;
return res;
end "mod";
function REALMAX (X, Y : REAL) return REAL is
begin
assert false severity failure;
end;
function REALMIN (X, Y : REAL) return REAL is
begin
assert false severity failure;
end;
procedure UNIFORM (SEED1, SEED2 : inout POSITIVE; X : out REAL)
is
variable z, k : Integer;
variable s1, s2 : Integer;
begin
k := seed1 / 53668;
s1 := 40014 * (seed1 - k * 53668) - k * 12211;
if s1 < 0 then
seed1 := s1 + 2147483563;
else
seed1 := s1;
end if;
k := seed2 / 52774;
s2 := 40692 * (seed2 - k * 52774) - k * 3791;
if s2 < 0 then
seed2 := s2 + 2147483399;
else
seed2 := s2;
end if;
z := seed1 - seed2;
if z < 1 then
z := z + 2147483562;
end if;
x := real (z) * 4.656613e-10;
end UNIFORM;
function SQRT (X : REAL) return REAL is
begin
assert false severity failure;
end;
function CBRT (X : REAL) return REAL is
begin
assert false severity failure;
end;
function "**" (X : INTEGER; Y : REAL) return REAL is
begin
return real (x) ** y;
end "**";
function "**" (X : REAL; Y : REAL) return REAL is
begin
assert false severity failure;
end;
function EXP (X : REAL) return REAL is
begin
assert false severity failure;
end;
function LOG (X : REAL) return REAL is
begin
assert false severity failure;
end;
function LOG2 (X : REAL) return REAL is
begin
assert false severity failure;
end;
function LOG10 (X : REAL) return REAL is
begin
assert false severity failure;
end;
function LOG (X : REAL; BASE : REAL) return REAL is
begin
return log (x) / log (base);
end log;
function SIN (X : REAL) return REAL is
begin
assert false severity failure;
end;
function COS (X : REAL) return REAL is
begin
assert false severity failure;
end;
function TAN (X : REAL) return REAL is
begin
assert false severity failure;
end;
function ARCSIN (X : REAL) return REAL is
begin
assert false severity failure;
end;
function ARCCOS (X : REAL) return REAL is
begin
assert false severity failure;
end;
function ARCTAN (Y : REAL) return REAL is
begin
assert false severity failure;
end;
function ARCTAN (Y, X : REAL) return REAL is
begin
assert false severity failure;
end;
function SINH (X : REAL) return REAL is
begin
assert false severity failure;
end;
function COSH (X : REAL) return REAL is
begin
assert false severity failure;
end;
function TANH (X : REAL) return REAL is
begin
assert false severity failure;
end;
function ARCSINH (X : REAL) return REAL is
begin
assert false severity failure;
end;
function ARCCOSH (X : REAL) return REAL is
begin
assert false severity failure;
end;
function ARCTANH (Y : REAL) return REAL is
begin
assert false severity failure;
end;
end MATH_REAL;
| gpl-2.0 | 50c30ebbe56e83ad85fbd81566a9ce87 | 0.641063 | 3.742813 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_spi/sim/BLK_MEM_GEN_V6_1.vhd | 1 | 203,480 | -------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: BLK_MEM_GEN_V6_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (BLK_MEM_GEN_V6_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
-----FLOP CODING -----
----- process(S_ARESETN, S_ACLK)
----- begin
----- if (S_ARESETN = '1') then
----- present_state_FSM_FFd1_13 <= '0';
----- elsif (rising_edge(S_ACLK)) then
----- present_state_FSM_FFd1_13 <= present_state_FSM_FFd1_In after 100 ps;
----- end if;
----- end process;
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
----- MUXF7_process : process (N8, N9,present_state_FSM_FFd1_13)
----- begin
----- if (present_state_FSM_FFd1_13 = '0') then
----- present_state_FSM_FFd1_In <= N8;
----- else
----- present_state_FSM_FFd1_In <= N9;
----- end if;
----- end process;
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_V6_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex5";
C_XDEVICEFAMILY : STRING := "virtex5";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_V6_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF BLK_MEM_GEN_V6_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN ((C_USE_ECC=1 AND (C_FAMILY="virtex6")) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF ((C_FAMILY = "spartan6") AND C_RST_TYPE = "ASYNC") THEN --Asynchronous Reset
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val;
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val;
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END IF;--Priority conditions
ELSE --Synchronous Reset
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END IF;--RST TYPE
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF ((C_FAMILY = "spartan6") AND C_RST_TYPE = "ASYNC") THEN --Asynchronous Reset
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val;
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--CLK
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val;
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END IF;--Priority conditions
IF (CLK'EVENT AND CLK = '1') THEN
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1);
END LOOP;
out_regs(0) <= DIN;
END IF;
END IF;
ELSE --Synchronous Reset
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END IF;--RST TYPE
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (BLK_MEM_GEN_V6_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_V6_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_V6_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF BLK_MEM_GEN_V6_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_V6_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v6_1";
C_FAMILY : STRING := "virtex6";
C_XDEVICEFAMILY : STRING := "virtex6";
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_V6_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF BLK_MEM_GEN_V6_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
-- the memory type
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
VARIABLE index : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT BLK_MEM_GEN_V6_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex5";
C_XDEVICEFAMILY : STRING := "virtex5";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_V6_1_output_stage;
COMPONENT BLK_MEM_GEN_V6_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_V6_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 2 ns;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex6") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
----- COMMENTED FOR CR550771-------------------------------------------------
----- VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := (1 => '1', 0 => '1',OTHERS=>'0');
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
----- COMMENTED FOR CR550771-------------------------------------------------
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator CORE Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex6") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex6") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
----- ELSE
----- sbiterr_in <= '0' AFTER FLOP_DELAY;
----- dbiterr_in <= '0' AFTER FLOP_DELAY;
----- rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
----- END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
----- --assert softecc sbiterr and dbiterr signals
----- IF (C_USE_SOFTECC = 1) THEN
----- rdaddrecc_in <= addr AFTER FLOP_DELAY;
----- IF (errbit_memory(address_i) = "01") THEN
----- sbiterr_in <= '1' AFTER FLOP_DELAY;
----- ELSE
----- sbiterr_in <= '0' AFTER FLOP_DELAY;
----- END IF;
----- IF (errbit_memory(address_i) = "10") THEN
----- dbiterr_in <= '1' AFTER FLOP_DELAY;
----- ELSE
----- dbiterr_in <= '0' AFTER FLOP_DELAY;
----- END IF;
----- ELSE
----- sbiterr_in <= '0' AFTER FLOP_DELAY;
----- dbiterr_in <= '0' AFTER FLOP_DELAY;
----- rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
----- END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--*************************************************************************
-- Asynchronous reset of Port A and Port B are performed here
-- Note that the asynchronous reset feature is only supported in Spartan6
-- devices
--*************************************************************************
IF((C_FAMILY = "spartan6") AND C_RST_TYPE="ASYNC") THEN
IF (C_RST_PRIORITY_A="CE") THEN
IF (rea_i='1') THEN
reset_a(reseta_i);
END IF;
ELSE
reset_a(reseta_i);
END IF;
IF (C_RST_PRIORITY_B="CE") THEN
IF (reb_i='1') THEN
reset_b(resetb_i);
END IF;
ELSE
reset_b(resetb_i);
END IF;
END IF;
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1' AND web_i=WEB0) THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1' AND web_i=WEB0) THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1' AND wea_i=WEA0) THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1' AND wea_i=WEA0) THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1' AND wea_i=WEA0) THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1' AND web_i=WEB0) THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
WHEN "01" => -- read_first
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_A="SR") THEN
IF (reseta_i='1') THEN
reset_a(reseta_i);
ELSE
IF (rea_i='1' AND wea_i=WEA0) THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
ELSE
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
WHEN "01" => -- read_first
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF ((C_FAMILY = "spartan6") AND C_RST_PRIORITY_B="SR") THEN
IF (resetb_i='1') THEN
reset_b(resetb_i);
ELSE
IF (reb_i='1' AND web_i=WEB0) THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
ELSE
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
reg_a : BLK_MEM_GEN_V6_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => ENA,
REGCE => REGCEA,
DIN => memory_out_a,
DOUT => DOUTA,
SBITERR_IN => '0',
DBITERR_IN => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN => (OTHERS => '0'),
RDADDRECC => OPEN
);
-- Port B
reg_b : BLK_MEM_GEN_V6_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => ENB,
REGCE => REGCEB,
DIN => memory_out_b,
DOUT => doutb_i,
SBITERR_IN => sbiterr_in,
DBITERR_IN => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN => rdaddrecc_in,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: BLK_MEM_GEN_V6_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
IF (ena_i='1' AND enb_i='1') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
IF (ena_i='1' AND enb_i='1') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
IF (ena_i='1' AND enb_i='1') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1') THEN
is_collision_delay_b := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_V6_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v6_1";
C_FAMILY : STRING := "virtex6";
C_XDEVICEFAMILY : STRING := "virtex6";
C_INTERFACE_TYPE : INTEGER := 0;
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_V6_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF BLK_MEM_GEN_V6_1 IS
COMPONENT BLK_MEM_GEN_V6_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v6_1";
C_FAMILY : STRING := "virtex6";
C_XDEVICEFAMILY : STRING := "virtex6";
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_V6_1_mem_module;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
BEGIN -- Architecture
--***************************************************************************
-- NO INPUT STAGE
--***************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--****************************************************************************
-- WITH INPUT STAGE
--****************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--****************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--****************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0) GENERATE
mem_module: BLK_MEM_GEN_V6_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX6L"),"virtex6",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex6",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex6",if_then_else(equalIgnoreCase(C_FAMILY,"SPARTAN6L"),"spartan6",if_then_else(equalIgnoreCase(C_FAMILY,"ASPARTAN6"),"spartan6",if_then_else(equalIgnoreCase(C_FAMILY,"ASPARTAN3ADSP"),"spartan3adsp",if_then_else(equalIgnoreCase(C_FAMILY,"ASPARTAN3A"),"spartan3a",C_FAMILY))))))),
---- C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => rsta_in,
ENA => ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB,
ENB => ENB,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
axi_mem_module: IF (C_INTERFACE_TYPE /= 0) GENERATE
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
S_AXI_RRESP <= (OTHERS => '0');
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: BLK_MEM_GEN_V6_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX6L"),"virtex6",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex6",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex6",if_then_else(equalIgnoreCase(C_FAMILY,"SPARTAN6L"),"spartan6",if_then_else(equalIgnoreCase(C_FAMILY,"ASPARTAN6"),"spartan6",if_then_else(equalIgnoreCase(C_FAMILY,"ASPARTAN3ADSP"),"spartan3adsp",if_then_else(equalIgnoreCase(C_FAMILY,"ASPARTAN3A"),"spartan3a",C_FAMILY))))))),
---- C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => REGCEB,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => S_AXI_RDATA,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => S_AXI_RID,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
| mit | 2536a3dfacf923d3e6b13007f5bb743d | 0.501091 | 3.587953 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue207/pack.vhd | 2 | 2,033 | --------------------------------------------------------------------------------
--
-- Package demo with two simple overloaded procedures
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pack is
procedure inc(signal val:inout std_logic_vector);
procedure inc(signal val:inout unsigned);
procedure inc(signal val:inout signed);
procedure inc(signal val:inout integer);
procedure inc(variable val:inout unsigned);
procedure inc(variable val:inout integer);
procedure dec(signal val:inout std_logic_vector);
procedure dec(signal val:inout unsigned);
procedure dec(signal val:inout signed);
procedure dec(signal val:inout integer);
procedure dec(variable val:inout unsigned);
procedure dec(variable val:inout integer);
end pack;
package body pack is
procedure inc(signal val:inout std_logic_vector) is
begin
val<= std_logic_vector(unsigned(val) + 1);
end;
procedure inc(signal val:inout signed) is
begin
val<= val + 1;
end;
procedure inc(signal val:inout unsigned) is
begin
val<= val + 1;
end;
procedure inc(signal val:inout integer) is
begin
val<= val + 1;
end;
procedure inc(variable val:inout unsigned) is
begin
val := val + 1;
end;
procedure inc(variable val:inout integer) is
begin
val := val + 1;
end;
procedure dec(signal val:inout std_logic_vector) is
begin
val<= std_logic_vector(unsigned(val) - 1);
end;
procedure dec(signal val:inout unsigned) is
begin
val<= val - 1;
end;
procedure dec(signal val:inout signed) is
begin
val<= val - 1;
end;
procedure dec(signal val:inout integer) is
begin
val<= val - 1;
end;
procedure dec(variable val:inout unsigned) is
begin
val := val - 1;
end;
procedure dec(variable val:inout integer) is
begin
val := val - 1;
end;
end;
| gpl-2.0 | a842b01dd030ff48f82b823d17b92881 | 0.602558 | 4.066 | false | false | false | false |
tgingold/ghdl | libraries/ieee/numeric_bit.vhdl | 5 | 32,879 | -- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --!V87
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --!V87
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --!V87
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --!V87
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --!V87
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
| gpl-2.0 | 143a2a2251544eb35cbf211614f6bbb8 | 0.565924 | 4.212556 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_sysid_qsys_0/pr_region_default_sysid_qsys_0_inst.vhd | 1 | 687 | component pr_region_default_sysid_qsys_0 is
port (
clock : in std_logic := 'X'; -- clk
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X'; -- address
reset_n : in std_logic := 'X' -- reset_n
);
end component pr_region_default_sysid_qsys_0;
u0 : component pr_region_default_sysid_qsys_0
port map (
clock => CONNECTED_TO_clock, -- clk.clk
readdata => CONNECTED_TO_readdata, -- control_slave.readdata
address => CONNECTED_TO_address, -- .address
reset_n => CONNECTED_TO_reset_n -- reset.reset_n
);
| mit | 92d85fbabfabc47bd49a35c271294ee6 | 0.537118 | 3.302885 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd | 4 | 1,684 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_mux4 is
end entity tb_mux4;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture test_demo of tb_mux4 is
signal sel : work.mux4_types.sel_range := 0;
signal d0, d1, d2, d3, z : std_ulogic;
begin
dut : entity work.mux4(demo)
port map ( sel => sel,
d0 => d0, d1 => d1, d2 => d2, d3 => d3,
z => z );
stimulus : process is
begin
wait for 5 ns;
d0 <= '1'; wait for 5 ns;
d1 <= 'H'; wait for 5 ns;
sel <= 1; wait for 5 ns;
d1 <= 'L'; wait for 5 ns;
sel <= 2; wait for 5 ns;
d0 <= '0'; wait for 5 ns;
d2 <= '1'; wait for 5 ns;
d2 <= '0'; wait for 5 ns;
sel <= 3; wait for 5 ns;
d3 <= '1'; wait for 5 ns;
d3 <= '0'; wait for 5 ns;
wait;
end process stimulus;
end architecture test_demo;
| gpl-2.0 | e7b75e2a6582803f5c73190c0bf16509 | 0.604513 | 3.368 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_axi_bridge_0/ghrd_10as066n2_axi_bridge_0_inst.vhd | 1 | 17,572 | component ghrd_10as066n2_axi_bridge_0 is
generic (
USE_PIPELINE : integer := 1;
USE_M0_AWID : integer := 1;
USE_M0_AWREGION : integer := 1;
USE_M0_AWLEN : integer := 1;
USE_M0_AWSIZE : integer := 1;
USE_M0_AWBURST : integer := 1;
USE_M0_AWLOCK : integer := 1;
USE_M0_AWCACHE : integer := 1;
USE_M0_AWQOS : integer := 1;
USE_S0_AWREGION : integer := 1;
USE_S0_AWLOCK : integer := 1;
USE_S0_AWCACHE : integer := 1;
USE_S0_AWQOS : integer := 1;
USE_S0_AWPROT : integer := 1;
USE_M0_WSTRB : integer := 1;
USE_S0_WLAST : integer := 1;
USE_M0_BID : integer := 1;
USE_M0_BRESP : integer := 1;
USE_S0_BRESP : integer := 1;
USE_M0_ARID : integer := 1;
USE_M0_ARREGION : integer := 1;
USE_M0_ARLEN : integer := 1;
USE_M0_ARSIZE : integer := 1;
USE_M0_ARBURST : integer := 1;
USE_M0_ARLOCK : integer := 1;
USE_M0_ARCACHE : integer := 1;
USE_M0_ARQOS : integer := 1;
USE_S0_ARREGION : integer := 1;
USE_S0_ARLOCK : integer := 1;
USE_S0_ARCACHE : integer := 1;
USE_S0_ARQOS : integer := 1;
USE_S0_ARPROT : integer := 1;
USE_M0_RID : integer := 1;
USE_M0_RRESP : integer := 1;
USE_M0_RLAST : integer := 1;
USE_S0_RRESP : integer := 1;
M0_ID_WIDTH : integer := 8;
S0_ID_WIDTH : integer := 8;
DATA_WIDTH : integer := 32;
WRITE_ADDR_USER_WIDTH : integer := 64;
READ_ADDR_USER_WIDTH : integer := 64;
WRITE_DATA_USER_WIDTH : integer := 64;
WRITE_RESP_USER_WIDTH : integer := 64;
READ_DATA_USER_WIDTH : integer := 64;
ADDR_WIDTH : integer := 11;
USE_S0_AWUSER : integer := 0;
USE_S0_ARUSER : integer := 0;
USE_S0_WUSER : integer := 0;
USE_S0_RUSER : integer := 0;
USE_S0_BUSER : integer := 0;
USE_M0_AWUSER : integer := 0;
USE_M0_ARUSER : integer := 0;
USE_M0_WUSER : integer := 0;
USE_M0_RUSER : integer := 0;
USE_M0_BUSER : integer := 0;
AXI_VERSION : string := "AXI3"
);
port (
aclk : in std_logic := 'X'; -- clk
aresetn : in std_logic := 'X'; -- reset_n
m0_awid : out std_logic_vector(2 downto 0); -- awid
m0_awaddr : out std_logic_vector(31 downto 0); -- awaddr
m0_awlen : out std_logic_vector(7 downto 0); -- awlen
m0_awsize : out std_logic_vector(2 downto 0); -- awsize
m0_awburst : out std_logic_vector(1 downto 0); -- awburst
m0_awlock : out std_logic_vector(0 downto 0); -- awlock
m0_awcache : out std_logic_vector(3 downto 0); -- awcache
m0_awprot : out std_logic_vector(2 downto 0); -- awprot
m0_awqos : out std_logic_vector(3 downto 0); -- awqos
m0_awregion : out std_logic_vector(3 downto 0); -- awregion
m0_awvalid : out std_logic; -- awvalid
m0_awready : in std_logic := 'X'; -- awready
m0_wdata : out std_logic_vector(511 downto 0); -- wdata
m0_wstrb : out std_logic_vector(63 downto 0); -- wstrb
m0_wlast : out std_logic; -- wlast
m0_wvalid : out std_logic; -- wvalid
m0_wready : in std_logic := 'X'; -- wready
m0_bid : in std_logic_vector(2 downto 0) := (others => 'X'); -- bid
m0_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
m0_bvalid : in std_logic := 'X'; -- bvalid
m0_bready : out std_logic; -- bready
m0_arid : out std_logic_vector(2 downto 0); -- arid
m0_araddr : out std_logic_vector(31 downto 0); -- araddr
m0_arlen : out std_logic_vector(7 downto 0); -- arlen
m0_arsize : out std_logic_vector(2 downto 0); -- arsize
m0_arburst : out std_logic_vector(1 downto 0); -- arburst
m0_arlock : out std_logic_vector(0 downto 0); -- arlock
m0_arcache : out std_logic_vector(3 downto 0); -- arcache
m0_arprot : out std_logic_vector(2 downto 0); -- arprot
m0_arqos : out std_logic_vector(3 downto 0); -- arqos
m0_arregion : out std_logic_vector(3 downto 0); -- arregion
m0_arvalid : out std_logic; -- arvalid
m0_arready : in std_logic := 'X'; -- arready
m0_rid : in std_logic_vector(2 downto 0) := (others => 'X'); -- rid
m0_rdata : in std_logic_vector(511 downto 0) := (others => 'X'); -- rdata
m0_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
m0_rlast : in std_logic := 'X'; -- rlast
m0_rvalid : in std_logic := 'X'; -- rvalid
m0_rready : out std_logic; -- rready
s0_awid : in std_logic_vector(5 downto 0) := (others => 'X'); -- awid
s0_awaddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- awaddr
s0_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen
s0_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
s0_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
s0_awlock : in std_logic_vector(0 downto 0) := (others => 'X'); -- awlock
s0_awcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- awcache
s0_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
s0_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- awqos
s0_awregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- awregion
s0_awvalid : in std_logic := 'X'; -- awvalid
s0_awready : out std_logic; -- awready
s0_wdata : in std_logic_vector(511 downto 0) := (others => 'X'); -- wdata
s0_wstrb : in std_logic_vector(63 downto 0) := (others => 'X'); -- wstrb
s0_wlast : in std_logic := 'X'; -- wlast
s0_wvalid : in std_logic := 'X'; -- wvalid
s0_wready : out std_logic; -- wready
s0_bid : out std_logic_vector(5 downto 0); -- bid
s0_bresp : out std_logic_vector(1 downto 0); -- bresp
s0_bvalid : out std_logic; -- bvalid
s0_bready : in std_logic := 'X'; -- bready
s0_arid : in std_logic_vector(5 downto 0) := (others => 'X'); -- arid
s0_araddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- araddr
s0_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen
s0_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
s0_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
s0_arlock : in std_logic_vector(0 downto 0) := (others => 'X'); -- arlock
s0_arcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- arcache
s0_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
s0_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- arqos
s0_arregion : in std_logic_vector(3 downto 0) := (others => 'X'); -- arregion
s0_arvalid : in std_logic := 'X'; -- arvalid
s0_arready : out std_logic; -- arready
s0_rid : out std_logic_vector(5 downto 0); -- rid
s0_rdata : out std_logic_vector(511 downto 0); -- rdata
s0_rresp : out std_logic_vector(1 downto 0); -- rresp
s0_rlast : out std_logic; -- rlast
s0_rvalid : out std_logic; -- rvalid
s0_rready : in std_logic := 'X' -- rready
);
end component ghrd_10as066n2_axi_bridge_0;
u0 : component ghrd_10as066n2_axi_bridge_0
generic map (
USE_PIPELINE => INTEGER_VALUE_FOR_USE_PIPELINE,
USE_M0_AWID => INTEGER_VALUE_FOR_USE_M0_AWID,
USE_M0_AWREGION => INTEGER_VALUE_FOR_USE_M0_AWREGION,
USE_M0_AWLEN => INTEGER_VALUE_FOR_USE_M0_AWLEN,
USE_M0_AWSIZE => INTEGER_VALUE_FOR_USE_M0_AWSIZE,
USE_M0_AWBURST => INTEGER_VALUE_FOR_USE_M0_AWBURST,
USE_M0_AWLOCK => INTEGER_VALUE_FOR_USE_M0_AWLOCK,
USE_M0_AWCACHE => INTEGER_VALUE_FOR_USE_M0_AWCACHE,
USE_M0_AWQOS => INTEGER_VALUE_FOR_USE_M0_AWQOS,
USE_S0_AWREGION => INTEGER_VALUE_FOR_USE_S0_AWREGION,
USE_S0_AWLOCK => INTEGER_VALUE_FOR_USE_S0_AWLOCK,
USE_S0_AWCACHE => INTEGER_VALUE_FOR_USE_S0_AWCACHE,
USE_S0_AWQOS => INTEGER_VALUE_FOR_USE_S0_AWQOS,
USE_S0_AWPROT => INTEGER_VALUE_FOR_USE_S0_AWPROT,
USE_M0_WSTRB => INTEGER_VALUE_FOR_USE_M0_WSTRB,
USE_S0_WLAST => INTEGER_VALUE_FOR_USE_S0_WLAST,
USE_M0_BID => INTEGER_VALUE_FOR_USE_M0_BID,
USE_M0_BRESP => INTEGER_VALUE_FOR_USE_M0_BRESP,
USE_S0_BRESP => INTEGER_VALUE_FOR_USE_S0_BRESP,
USE_M0_ARID => INTEGER_VALUE_FOR_USE_M0_ARID,
USE_M0_ARREGION => INTEGER_VALUE_FOR_USE_M0_ARREGION,
USE_M0_ARLEN => INTEGER_VALUE_FOR_USE_M0_ARLEN,
USE_M0_ARSIZE => INTEGER_VALUE_FOR_USE_M0_ARSIZE,
USE_M0_ARBURST => INTEGER_VALUE_FOR_USE_M0_ARBURST,
USE_M0_ARLOCK => INTEGER_VALUE_FOR_USE_M0_ARLOCK,
USE_M0_ARCACHE => INTEGER_VALUE_FOR_USE_M0_ARCACHE,
USE_M0_ARQOS => INTEGER_VALUE_FOR_USE_M0_ARQOS,
USE_S0_ARREGION => INTEGER_VALUE_FOR_USE_S0_ARREGION,
USE_S0_ARLOCK => INTEGER_VALUE_FOR_USE_S0_ARLOCK,
USE_S0_ARCACHE => INTEGER_VALUE_FOR_USE_S0_ARCACHE,
USE_S0_ARQOS => INTEGER_VALUE_FOR_USE_S0_ARQOS,
USE_S0_ARPROT => INTEGER_VALUE_FOR_USE_S0_ARPROT,
USE_M0_RID => INTEGER_VALUE_FOR_USE_M0_RID,
USE_M0_RRESP => INTEGER_VALUE_FOR_USE_M0_RRESP,
USE_M0_RLAST => INTEGER_VALUE_FOR_USE_M0_RLAST,
USE_S0_RRESP => INTEGER_VALUE_FOR_USE_S0_RRESP,
M0_ID_WIDTH => INTEGER_VALUE_FOR_M0_ID_WIDTH,
S0_ID_WIDTH => INTEGER_VALUE_FOR_S0_ID_WIDTH,
DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH,
WRITE_ADDR_USER_WIDTH => INTEGER_VALUE_FOR_WRITE_ADDR_USER_WIDTH,
READ_ADDR_USER_WIDTH => INTEGER_VALUE_FOR_READ_ADDR_USER_WIDTH,
WRITE_DATA_USER_WIDTH => INTEGER_VALUE_FOR_WRITE_DATA_USER_WIDTH,
WRITE_RESP_USER_WIDTH => INTEGER_VALUE_FOR_WRITE_RESP_USER_WIDTH,
READ_DATA_USER_WIDTH => INTEGER_VALUE_FOR_READ_DATA_USER_WIDTH,
ADDR_WIDTH => INTEGER_VALUE_FOR_ADDR_WIDTH,
USE_S0_AWUSER => INTEGER_VALUE_FOR_USE_S0_AWUSER,
USE_S0_ARUSER => INTEGER_VALUE_FOR_USE_S0_ARUSER,
USE_S0_WUSER => INTEGER_VALUE_FOR_USE_S0_WUSER,
USE_S0_RUSER => INTEGER_VALUE_FOR_USE_S0_RUSER,
USE_S0_BUSER => INTEGER_VALUE_FOR_USE_S0_BUSER,
USE_M0_AWUSER => INTEGER_VALUE_FOR_USE_M0_AWUSER,
USE_M0_ARUSER => INTEGER_VALUE_FOR_USE_M0_ARUSER,
USE_M0_WUSER => INTEGER_VALUE_FOR_USE_M0_WUSER,
USE_M0_RUSER => INTEGER_VALUE_FOR_USE_M0_RUSER,
USE_M0_BUSER => INTEGER_VALUE_FOR_USE_M0_BUSER,
AXI_VERSION => STRING_VALUE_FOR_AXI_VERSION
)
port map (
aclk => CONNECTED_TO_aclk, -- clk.clk
aresetn => CONNECTED_TO_aresetn, -- clk_reset.reset_n
m0_awid => CONNECTED_TO_m0_awid, -- m0.awid
m0_awaddr => CONNECTED_TO_m0_awaddr, -- .awaddr
m0_awlen => CONNECTED_TO_m0_awlen, -- .awlen
m0_awsize => CONNECTED_TO_m0_awsize, -- .awsize
m0_awburst => CONNECTED_TO_m0_awburst, -- .awburst
m0_awlock => CONNECTED_TO_m0_awlock, -- .awlock
m0_awcache => CONNECTED_TO_m0_awcache, -- .awcache
m0_awprot => CONNECTED_TO_m0_awprot, -- .awprot
m0_awqos => CONNECTED_TO_m0_awqos, -- .awqos
m0_awregion => CONNECTED_TO_m0_awregion, -- .awregion
m0_awvalid => CONNECTED_TO_m0_awvalid, -- .awvalid
m0_awready => CONNECTED_TO_m0_awready, -- .awready
m0_wdata => CONNECTED_TO_m0_wdata, -- .wdata
m0_wstrb => CONNECTED_TO_m0_wstrb, -- .wstrb
m0_wlast => CONNECTED_TO_m0_wlast, -- .wlast
m0_wvalid => CONNECTED_TO_m0_wvalid, -- .wvalid
m0_wready => CONNECTED_TO_m0_wready, -- .wready
m0_bid => CONNECTED_TO_m0_bid, -- .bid
m0_bresp => CONNECTED_TO_m0_bresp, -- .bresp
m0_bvalid => CONNECTED_TO_m0_bvalid, -- .bvalid
m0_bready => CONNECTED_TO_m0_bready, -- .bready
m0_arid => CONNECTED_TO_m0_arid, -- .arid
m0_araddr => CONNECTED_TO_m0_araddr, -- .araddr
m0_arlen => CONNECTED_TO_m0_arlen, -- .arlen
m0_arsize => CONNECTED_TO_m0_arsize, -- .arsize
m0_arburst => CONNECTED_TO_m0_arburst, -- .arburst
m0_arlock => CONNECTED_TO_m0_arlock, -- .arlock
m0_arcache => CONNECTED_TO_m0_arcache, -- .arcache
m0_arprot => CONNECTED_TO_m0_arprot, -- .arprot
m0_arqos => CONNECTED_TO_m0_arqos, -- .arqos
m0_arregion => CONNECTED_TO_m0_arregion, -- .arregion
m0_arvalid => CONNECTED_TO_m0_arvalid, -- .arvalid
m0_arready => CONNECTED_TO_m0_arready, -- .arready
m0_rid => CONNECTED_TO_m0_rid, -- .rid
m0_rdata => CONNECTED_TO_m0_rdata, -- .rdata
m0_rresp => CONNECTED_TO_m0_rresp, -- .rresp
m0_rlast => CONNECTED_TO_m0_rlast, -- .rlast
m0_rvalid => CONNECTED_TO_m0_rvalid, -- .rvalid
m0_rready => CONNECTED_TO_m0_rready, -- .rready
s0_awid => CONNECTED_TO_s0_awid, -- s0.awid
s0_awaddr => CONNECTED_TO_s0_awaddr, -- .awaddr
s0_awlen => CONNECTED_TO_s0_awlen, -- .awlen
s0_awsize => CONNECTED_TO_s0_awsize, -- .awsize
s0_awburst => CONNECTED_TO_s0_awburst, -- .awburst
s0_awlock => CONNECTED_TO_s0_awlock, -- .awlock
s0_awcache => CONNECTED_TO_s0_awcache, -- .awcache
s0_awprot => CONNECTED_TO_s0_awprot, -- .awprot
s0_awqos => CONNECTED_TO_s0_awqos, -- .awqos
s0_awregion => CONNECTED_TO_s0_awregion, -- .awregion
s0_awvalid => CONNECTED_TO_s0_awvalid, -- .awvalid
s0_awready => CONNECTED_TO_s0_awready, -- .awready
s0_wdata => CONNECTED_TO_s0_wdata, -- .wdata
s0_wstrb => CONNECTED_TO_s0_wstrb, -- .wstrb
s0_wlast => CONNECTED_TO_s0_wlast, -- .wlast
s0_wvalid => CONNECTED_TO_s0_wvalid, -- .wvalid
s0_wready => CONNECTED_TO_s0_wready, -- .wready
s0_bid => CONNECTED_TO_s0_bid, -- .bid
s0_bresp => CONNECTED_TO_s0_bresp, -- .bresp
s0_bvalid => CONNECTED_TO_s0_bvalid, -- .bvalid
s0_bready => CONNECTED_TO_s0_bready, -- .bready
s0_arid => CONNECTED_TO_s0_arid, -- .arid
s0_araddr => CONNECTED_TO_s0_araddr, -- .araddr
s0_arlen => CONNECTED_TO_s0_arlen, -- .arlen
s0_arsize => CONNECTED_TO_s0_arsize, -- .arsize
s0_arburst => CONNECTED_TO_s0_arburst, -- .arburst
s0_arlock => CONNECTED_TO_s0_arlock, -- .arlock
s0_arcache => CONNECTED_TO_s0_arcache, -- .arcache
s0_arprot => CONNECTED_TO_s0_arprot, -- .arprot
s0_arqos => CONNECTED_TO_s0_arqos, -- .arqos
s0_arregion => CONNECTED_TO_s0_arregion, -- .arregion
s0_arvalid => CONNECTED_TO_s0_arvalid, -- .arvalid
s0_arready => CONNECTED_TO_s0_arready, -- .arready
s0_rid => CONNECTED_TO_s0_rid, -- .rid
s0_rdata => CONNECTED_TO_s0_rdata, -- .rdata
s0_rresp => CONNECTED_TO_s0_rresp, -- .rresp
s0_rlast => CONNECTED_TO_s0_rlast, -- .rlast
s0_rvalid => CONNECTED_TO_s0_rvalid, -- .rvalid
s0_rready => CONNECTED_TO_s0_rready -- .rready
);
| mit | 395e59b2b985126d1fa5c9ca7498febd | 0.499545 | 3.050165 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc682.vhd | 4 | 2,545 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc682.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00682ent IS
END c03s04b01x00p23n01i00682ent;
ARCHITECTURE c03s04b01x00p23n01i00682arch OF c03s04b01x00p23n01i00682ent IS
type FT is file of INTEGER;
BEGIN
TESTING: PROCESS
variable i3, i2, i1: INTEGER;
file S1: FT open read_mode is "iofile.47";
BEGIN
wait for 10 ns;
READ(S1,i3);
READ(S1,i2);
READ(S1,i1);
wait for 10 ns;
assert NOT( (i3 = 3) and (i2 = 2) and (i1 = 1) )
report "***PASSED TEST: c03s04b01x00p23n01i00682"
severity NOTE;
assert ( (i3 = 3) and (i2 = 2) and (i1 = 1) )
report "***FAILED TEST: c03s04b01x00p23n01i00682 - Procedure READ retrieves the next value from a file."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00682arch;
| gpl-2.0 | cabd31eceaa46a1f6266e6541b766d1b | 0.550098 | 3.753687 | false | true | false | false |
tgingold/ghdl | testsuite/synth/synth36/bram.vhdl | 1 | 805 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bram is
generic (
addr_width : integer := 9;
data_width : integer := 8
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector(addr_width-1 downto 0);
data_in : in std_logic_vector(data_width-1 downto 0);
data_out : out std_logic_vector(data_width-1 downto 0)
);
end bram;
architecture rtl of bram is
type mem_type is array (0 to (2**addr_width)-1) of std_logic_vector(data_width-1 downto 0);
signal mem : mem_type;
begin
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
mem(to_integer(unsigned(addr))) <= data_in;
end if;
end if;
end process;
data_out <= mem(to_integer(unsigned(addr)));
end rtl;
| gpl-2.0 | 96d45393eda362ebf98a5753e44fb91b | 0.618634 | 3.060837 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ctrl-b.vhd | 4 | 43,143 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ctrl-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
library work;
use work.dlx_instr.all;
architecture behavior of controller is
begin -- behavior
sequencer : process is
variable current_instruction_bv : dlx_bv_word;
alias IR_opcode : dlx_opcode is current_instruction_bv(0 to 5);
alias IR_sp_func : dlx_sp_func is current_instruction_bv(26 to 31);
alias IR_fp_func : dlx_fp_func is current_instruction_bv(27 to 31);
alias IR_rs1 : reg_file_addr is current_instruction(6 to 10);
alias IR_rs2 : reg_file_addr is current_instruction(11 to 15);
alias IR_Itype_rd : reg_file_addr is current_instruction(11 to 15);
alias IR_Rtype_rd : reg_file_addr is current_instruction(16 to 20);
variable result_of_set_is_1, branch_taken : boolean;
variable disassembled_instr : string(1 to 40);
variable disassembled_instr_len : positive;
variable instr_count : natural := 0;
procedure bus_instruction_fetch is
begin
-- use PC as address
mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
-- set up memory control signals
width <= dlx_mem_width_word after Tpd_clk_ctrl;
ifetch <= '1' after Tpd_clk_ctrl;
write_enable <= '0' after Tpd_clk_ctrl;
mem_enable <= '1' after Tpd_clk_ctrl;
-- wait until phi2, then enable IR input
wait until rising_edge(phi2);
ir_latch_en <= '1' after Tpd_clk_ctrl;
-- wait until memory is ready at end of phi2
loop
wait until falling_edge(phi2);
if To_bit(reset) = '1' then
return;
end if;
exit when To_bit(ready) = '1';
end loop;
-- disable IR input and memory control signals
ir_latch_en <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
end procedure bus_instruction_fetch;
procedure bus_data_read ( read_width : in dlx_mem_width ) is
begin
-- use MAR as address
mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
-- set up memory control signals
width <= read_width after Tpd_clk_ctrl;
ifetch <= '0' after Tpd_clk_ctrl;
write_enable <= '0' after Tpd_clk_ctrl;
mem_enable <= '1' after Tpd_clk_ctrl;
-- wait until phi2, then enable MDR input
wait until rising_edge(phi2);
mdr_mux_sel <= '1' after Tpd_clk_ctrl;
mdr_latch_en <= '1' after Tpd_clk_ctrl;
-- wait until memory is ready at end of phi2
loop
wait until falling_edge(phi2);
if To_bit(reset) = '1' then
return;
end if;
exit when To_bit(ready) = '1';
end loop;
-- disable MDR input and memory control signals
mdr_latch_en <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
end procedure bus_data_read;
procedure bus_data_write ( write_width : in dlx_mem_width ) is
begin
-- use MAR as address
mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
-- enable MDR output
mdr_out_en3 <= '1' after Tpd_clk_ctrl;
-- set up memory control signals
width <= write_width after Tpd_clk_ctrl;
ifetch <= '0' after Tpd_clk_ctrl;
write_enable <= '1' after Tpd_clk_ctrl;
mem_enable <= '1' after Tpd_clk_ctrl;
-- wait until memory is ready at end of phi2
loop
wait until falling_edge(phi2);
if To_bit(reset) = '1' then
return;
end if;
exit when To_bit(ready) = '1';
end loop;
-- disable MDR output and memory control signals
write_enable <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
mdr_out_en3 <= '0' after Tpd_clk_ctrl;
end procedure bus_data_write;
procedure do_set_result is
begin
wait until rising_edge(phi1);
if result_of_set_is_1 then
const2 <= X"0000_0001" after Tpd_clk_const;
else
const2 <= X"0000_0000" after Tpd_clk_const;
end if;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
const2 <= disabled_dlx_word after Tpd_clk_const;
wait until rising_edge(phi2);
c_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
c_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_set_result;
procedure do_EX_set_unsigned ( immed : boolean ) is
begin
wait until rising_edge(phi1);
a_out_en <= '1' after Tpd_clk_ctrl;
if immed then
ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
ir_immed2_unsigned <= '1' after Tpd_clk_ctrl;
ir_immed2_en <= '1' after Tpd_clk_ctrl;
else
b_out_en <= '1' after Tpd_clk_ctrl;
end if;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_subu after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
if immed then
ir_immed2_en <= '0' after Tpd_clk_ctrl;
else
b_out_en <= '0' after Tpd_clk_ctrl;
end if;
wait until falling_edge(phi2);
if immed then
case IR_opcode is
when op_sequi =>
result_of_set_is_1 := To_bit(alu_zero) = '1';
when op_sneui =>
result_of_set_is_1 := To_bit(alu_zero) /= '1';
when op_sltui =>
result_of_set_is_1 := To_bit(alu_overflow) = '1';
when op_sgtui =>
result_of_set_is_1 := To_bit(alu_overflow) /= '1' and To_bit(alu_zero) /= '1';
when op_sleui =>
result_of_set_is_1 := To_bit(alu_overflow) = '1' or To_bit(alu_zero) = '1';
when op_sgeui =>
result_of_set_is_1 := To_bit(alu_overflow) /= '1';
when others =>
null;
end case;
else
case IR_sp_func is
when sp_func_sequ =>
result_of_set_is_1 := To_bit(alu_zero) = '1';
when sp_func_sneu =>
result_of_set_is_1 := To_bit(alu_zero) /= '1';
when sp_func_sltu =>
result_of_set_is_1 := To_bit(alu_overflow) = '1';
when sp_func_sgtu =>
result_of_set_is_1 := To_bit(alu_overflow) /= '1' and To_bit(alu_zero) /= '1';
when sp_func_sleu =>
result_of_set_is_1 := To_bit(alu_overflow) = '1' or To_bit(alu_zero) = '1';
when sp_func_sgeu =>
result_of_set_is_1 := To_bit(alu_overflow) /= '1';
when others =>
null;
end case;
end if;
do_set_result;
end procedure do_EX_set_unsigned;
procedure do_EX_set_signed ( immed : boolean ) is
begin
wait until rising_edge(phi1);
a_out_en <= '1' after Tpd_clk_ctrl;
if immed then
ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
ir_immed2_en <= '1' after Tpd_clk_ctrl;
else
b_out_en <= '1' after Tpd_clk_ctrl;
end if;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_sub after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
if immed then
ir_immed2_en <= '0' after Tpd_clk_ctrl;
else
b_out_en <= '0' after Tpd_clk_ctrl;
end if;
wait until falling_edge(phi2);
if immed then
case IR_opcode is
when op_seqi =>
result_of_set_is_1 := To_bit(alu_zero) = '1';
when op_snei =>
result_of_set_is_1 := To_bit(alu_zero) /= '1';
when op_slti =>
result_of_set_is_1 := To_bit(alu_negative) = '1';
when op_sgti =>
result_of_set_is_1 := To_bit(alu_negative) /= '1' and To_bit(alu_zero) /= '1';
when op_slei =>
result_of_set_is_1 := To_bit(alu_negative) = '1' or To_bit(alu_zero) = '1';
when op_sgei =>
result_of_set_is_1 := To_bit(alu_negative) /= '1';
when others =>
null;
end case;
else
case IR_sp_func is
when sp_func_seq =>
result_of_set_is_1 := To_bit(alu_zero) = '1';
when sp_func_sne =>
result_of_set_is_1 := To_bit(alu_zero) /= '1';
when sp_func_slt =>
result_of_set_is_1 := To_bit(alu_negative) = '1';
when sp_func_sgt =>
result_of_set_is_1 := To_bit(alu_negative) /= '1' and To_bit(alu_zero) /= '1';
when sp_func_sle =>
result_of_set_is_1 := To_bit(alu_negative) = '1' or To_bit(alu_zero) = '1';
when sp_func_sge =>
result_of_set_is_1 := To_bit(alu_negative) /= '1';
when others =>
null;
end case;
end if;
do_set_result;
end procedure do_EX_set_signed;
procedure do_EX_arith_logic is
begin
wait until rising_edge(phi1);
a_out_en <= '1' after Tpd_clk_ctrl;
b_out_en <= '1' after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
case IR_sp_func is
when sp_func_add =>
alu_function <= alu_add after Tpd_clk_ctrl;
when sp_func_addu =>
alu_function <= alu_addu after Tpd_clk_ctrl;
when sp_func_sub =>
alu_function <= alu_sub after Tpd_clk_ctrl;
when sp_func_subu =>
alu_function <= alu_subu after Tpd_clk_ctrl;
when sp_func_and =>
alu_function <= alu_and after Tpd_clk_ctrl;
when sp_func_or =>
alu_function <= alu_or after Tpd_clk_ctrl;
when sp_func_xor =>
alu_function <= alu_xor after Tpd_clk_ctrl;
when sp_func_sll =>
alu_function <= alu_sll after Tpd_clk_ctrl;
when sp_func_srl =>
alu_function <= alu_srl after Tpd_clk_ctrl;
when sp_func_sra =>
alu_function <= alu_sra after Tpd_clk_ctrl;
when others =>
null;
end case; -- IR_sp_func
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
b_out_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
c_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
c_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_EX_arith_logic;
procedure do_EX_arith_logic_immed is
begin
wait until rising_edge(phi1);
a_out_en <= '1' after Tpd_clk_ctrl;
ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
if IR_opcode = op_addi or IR_opcode = op_subi then
ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
else
ir_immed2_unsigned <= '1' after Tpd_clk_ctrl;
end if;
ir_immed2_en <= '1' after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
case IR_opcode is
when op_addi =>
alu_function <= alu_add after Tpd_clk_ctrl;
when op_subi =>
alu_function <= alu_sub after Tpd_clk_ctrl;
when op_addui =>
alu_function <= alu_addu after Tpd_clk_ctrl;
when op_subui =>
alu_function <= alu_subu after Tpd_clk_ctrl;
when op_andi =>
alu_function <= alu_and after Tpd_clk_ctrl;
when op_ori =>
alu_function <= alu_or after Tpd_clk_ctrl;
when op_xori =>
alu_function <= alu_xor after Tpd_clk_ctrl;
when op_slli =>
alu_function <= alu_sll after Tpd_clk_ctrl;
when op_srli =>
alu_function <= alu_srl after Tpd_clk_ctrl;
when op_srai =>
alu_function <= alu_sra after Tpd_clk_ctrl;
when others =>
null;
end case; -- IR_opcode
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
ir_immed2_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
c_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
c_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_EX_arith_logic_immed;
procedure do_EX_link is
begin
wait until rising_edge(phi1);
pc_out_en1 <= '1' after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
c_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
c_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_EX_link;
procedure do_EX_lhi is
begin
wait until rising_edge(phi1);
ir_immed1_size_26 <= '0' after Tpd_clk_ctrl;
ir_immed1_unsigned <= '1' after Tpd_clk_ctrl;
ir_immed1_en <= '1' after Tpd_clk_ctrl;
const2 <= X"0000_0010" after Tpd_clk_const; -- shift by 16 bits
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_sll after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
ir_immed1_en <= '0' after Tpd_clk_ctrl;
const2 <= disabled_dlx_word after Tpd_clk_const;
wait until rising_edge(phi2);
c_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
c_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_EX_lhi;
procedure do_EX_branch is
begin
wait until rising_edge(phi1);
a_out_en <= '1' after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
if IR_opcode = op_beqz then
branch_taken := To_bit(alu_zero) = '1';
else
branch_taken := To_bit(alu_zero) /= '1';
end if;
end procedure do_EX_branch;
procedure do_EX_load_store is
begin
wait until rising_edge(phi1);
a_out_en <= '1' after Tpd_clk_ctrl;
ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
ir_immed2_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
ir_immed2_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
mar_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
mar_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_EX_load_store;
procedure do_MEM_jump is
begin
wait until rising_edge(phi1);
pc_out_en1 <= '1' after Tpd_clk_ctrl;
ir_immed2_size_26 <= '1' after Tpd_clk_ctrl;
ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
ir_immed2_en <= '1' after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
ir_immed2_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
pc_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
pc_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_MEM_jump;
procedure do_MEM_jump_reg is
begin
wait until rising_edge(phi1);
a_out_en <= '1' after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
pc_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
pc_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_MEM_jump_reg;
procedure do_MEM_branch is
begin
wait until rising_edge(phi1);
pc_out_en1 <= '1' after Tpd_clk_ctrl;
ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
ir_immed2_en <= '1' after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
wait until falling_edge(phi1);
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
ir_immed2_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
pc_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
pc_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_MEM_branch;
procedure do_MEM_load is
subtype ls_2_addr_bits is bit_vector(1 downto 0);
begin
wait until rising_edge(phi1);
if IR_opcode = op_lb or IR_opcode = op_lbu then
bus_data_read(dlx_mem_width_byte);
elsif IR_opcode = op_lh or IR_opcode = op_lhu then
bus_data_read(dlx_mem_width_halfword);
else
bus_data_read(dlx_mem_width_word);
end if;
if To_bit(reset) = '1' then
return;
end if;
if ( (IR_opcode = op_lb or IR_opcode = op_lbu) and To_bitvector(mem_addr) /= "00" )
or ( (IR_opcode = op_lh or IR_opcode = op_lhu) and To_bit(mem_addr(1)) /= '0' ) then
-- first step of extension: left-justify byte or halfword -> mdr
wait until rising_edge(phi1);
mdr_out_en1 <= '1' after Tpd_clk_ctrl;
if IR_opcode = op_lb or IR_opcode = op_lbu then
case ls_2_addr_bits'(To_bitvector(mem_addr)) is
when "00" =>
null;
when "01" =>
const2 <= X"0000_0008" after Tpd_clk_const;
when "10" =>
const2 <= X"0000_0010" after Tpd_clk_const;
when "11" =>
const2 <= X"0000_0018" after Tpd_clk_const;
end case;
else
const2 <= X"0000_0010" after Tpd_clk_const;
end if;
alu_function <= alu_sll after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi1);
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
const2 <= disabled_dlx_word after Tpd_clk_const;
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
mdr_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
mdr_latch_en <= '0' after Tpd_clk_ctrl;
end if;
wait until rising_edge(phi1);
mdr_out_en1 <= '1' after Tpd_clk_ctrl;
if IR_opcode = op_lb or IR_opcode = op_lbu then
const2 <= X"0000_0018" after Tpd_clk_const;
elsif IR_opcode = op_lh or IR_opcode = op_lhu then
const2 <= X"0000_0010" after Tpd_clk_const;
else
const2 <= X"0000_0000" after Tpd_clk_const;
end if;
if IR_opcode = op_lbu or IR_opcode = op_lhu then
alu_function <= alu_srl after Tpd_clk_ctrl;
else
alu_function <= alu_sra after Tpd_clk_ctrl;
end if;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi1);
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
const2 <= disabled_dlx_word after Tpd_clk_const;
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
c_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
c_latch_en <= '0' after Tpd_clk_ctrl;
end procedure do_MEM_load;
procedure do_MEM_store is
subtype ls_2_addr_bits is bit_vector(1 downto 0);
begin
wait until rising_edge(phi1);
b_out_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi1);
b_out_en <= '0' after Tpd_clk_ctrl;
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
mdr_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
mdr_latch_en <= '0' after Tpd_clk_ctrl;
if ( IR_opcode = op_sb and To_bitvector(mem_addr) /= "11" )
or ( IR_opcode = op_sh and To_bit(mem_addr(1)) /= '1' ) then
-- align byte or halfword -> mdr
wait until rising_edge(phi1);
mdr_out_en1 <= '1' after Tpd_clk_ctrl;
if IR_opcode = op_sb then
case ls_2_addr_bits'(To_bitvector(mem_addr)) is
when "00" =>
const2 <= X"0000_0018" after Tpd_clk_const;
when "01" =>
const2 <= X"0000_0010" after Tpd_clk_const;
when "10" =>
const2 <= X"0000_0008" after Tpd_clk_const;
when "11" =>
null;
end case;
else
const2 <= X"0000_0010" after Tpd_clk_const;
end if;
alu_function <= alu_sll after Tpd_clk_ctrl;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi1);
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
const2 <= disabled_dlx_word after Tpd_clk_const;
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
wait until rising_edge(phi2);
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
mdr_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
mdr_latch_en <= '0' after Tpd_clk_ctrl;
end if;
wait until rising_edge(phi1);
if IR_opcode = op_sb then
bus_data_write(dlx_mem_width_byte);
elsif IR_opcode = op_sh then
bus_data_write(dlx_mem_width_halfword);
else
bus_data_write(dlx_mem_width_word);
end if;
end procedure do_MEM_store;
procedure do_WB ( Rd : reg_file_addr ) is
begin
wait until rising_edge(phi1);
reg_dest_addr <= Rd after Tpd_clk_ctrl;
reg_write <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
reg_write <= '0' after Tpd_clk_ctrl;
end procedure do_WB;
procedure execute_op_special is
begin
case IR_sp_func is
when sp_func_nop =>
null;
when sp_func_add | sp_func_addu | sp_func_sub | sp_func_subu
| sp_func_sll | sp_func_srl | sp_func_sra
| sp_func_and | sp_func_or | sp_func_xor =>
do_EX_arith_logic;
do_WB(IR_Rtype_rd);
when sp_func_sequ | sp_func_sneu | sp_func_sltu
| sp_func_sgtu | sp_func_sleu | sp_func_sgeu =>
do_EX_set_unsigned(immed => false);
do_WB(IR_Rtype_rd);
when sp_func_seq | sp_func_sne | sp_func_slt
| sp_func_sgt | sp_func_sle | sp_func_sge =>
do_EX_set_signed(immed => false);
do_WB(IR_Rtype_rd);
when sp_func_movi2s | sp_func_movs2i
| sp_func_movf | sp_func_movd
| sp_func_movfp2i | sp_func_movi2fp =>
report sp_func_names(bv_to_natural(IR_sp_func))
& " instruction not implemented" severity warning;
when others =>
report "undefined special instruction function" severity error;
end case;
end procedure execute_op_special;
procedure execute_op_fparith is
begin
case IR_fp_func is
when fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu
| fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
| fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
| fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f
| fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d
| fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf
| fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned
| fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
report fp_func_names(bv_to_natural(IR_fp_func))
& " instruction not implemented" severity warning;
when others =>
report "undefined floating point instruction function" severity error;
end case;
end procedure execute_op_fparith;
begin -- sequencer
----------------------------------------------------------------
-- initialize all control signals
----------------------------------------------------------------
if debug > none then
report "initializing";
end if;
halt <= '0' after Tpd_clk_ctrl;
width <= dlx_mem_width_word after Tpd_clk_ctrl;
write_enable <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
ifetch <= '0' after Tpd_clk_ctrl;
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
reg_s1_addr <= B"00000" after Tpd_clk_ctrl;
reg_s2_addr <= B"00000" after Tpd_clk_ctrl;
reg_dest_addr <= B"00000" after Tpd_clk_ctrl;
reg_write <= '0' after Tpd_clk_ctrl;
c_latch_en <= '0' after Tpd_clk_ctrl;
a_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
b_latch_en <= '0' after Tpd_clk_ctrl;
b_out_en <= '0' after Tpd_clk_ctrl;
temp_latch_en <= '0' after Tpd_clk_ctrl;
temp_out_en1 <= '0' after Tpd_clk_ctrl;
temp_out_en2 <= '0' after Tpd_clk_ctrl;
iar_latch_en <= '0' after Tpd_clk_ctrl;
iar_out_en1 <= '0' after Tpd_clk_ctrl;
iar_out_en2 <= '0' after Tpd_clk_ctrl;
pc_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
pc_out_en2 <= '0' after Tpd_clk_ctrl;
mar_latch_en <= '0' after Tpd_clk_ctrl;
mar_out_en1 <= '0' after Tpd_clk_ctrl;
mar_out_en2 <= '0' after Tpd_clk_ctrl;
mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
mdr_latch_en <= '0' after Tpd_clk_ctrl;
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
mdr_out_en2 <= '0' after Tpd_clk_ctrl;
mdr_out_en3 <= '0' after Tpd_clk_ctrl;
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
ir_latch_en <= '0' after Tpd_clk_ctrl;
ir_immed1_size_26 <= '0' after Tpd_clk_ctrl;
ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
ir_immed1_en <= '0' after Tpd_clk_ctrl;
ir_immed2_en <= '0' after Tpd_clk_ctrl;
const1 <= disabled_dlx_word after Tpd_clk_const;
const2 <= disabled_dlx_word after Tpd_clk_const;
instr_count := 0;
wait on phi2 until falling_edge(phi2) and To_bit(reset) = '0';
----------------------------------------------------------------
-- control loop
----------------------------------------------------------------
loop
exit when To_bit(reset) = '1';
----------------------------------------------------------------
-- fetch next instruction (IF)
----------------------------------------------------------------
wait until rising_edge(phi1);
instr_count := instr_count + 1;
if debug = msg_every_100_instructions and instr_count mod 100 = 0 then
report "instruction count = " & natural'image(instr_count);
end if;
if debug >= msg_each_instruction then
report "fetching instruction";
end if;
bus_instruction_fetch;
exit when To_bit(reset) = '1';
current_instruction_bv := To_bitvector(current_instruction);
if debug >= trace_each_instruction then
disassemble(current_instruction_bv, disassembled_instr, disassembled_instr_len);
report disassembled_instr(1 to disassembled_instr_len);
end if;
----------------------------------------------------------------
-- instruction decode, source register read and PC increment (ID)
----------------------------------------------------------------
wait until rising_edge(phi1);
if debug = trace_each_step then
report "decode, source register read and PC increment";
end if;
reg_s1_addr <= IR_rs1 after Tpd_clk_ctrl;
reg_s2_addr <= IR_rs2 after Tpd_clk_ctrl;
a_latch_en <= '1' after Tpd_clk_ctrl;
b_latch_en <= '1' after Tpd_clk_ctrl;
pc_out_en1 <= '1' after Tpd_clk_ctrl;
const2 <= X"0000_0004" after Tpd_clk_const;
alu_in_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_addu after Tpd_clk_ctrl;
wait until falling_edge(phi1);
a_latch_en <= '0' after Tpd_clk_ctrl;
b_latch_en <= '0' after Tpd_clk_ctrl;
alu_in_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
const2 <= disabled_dlx_word after Tpd_clk_const;
wait until rising_edge(phi2);
pc_latch_en <= '1' after Tpd_clk_ctrl;
wait until falling_edge(phi2);
pc_latch_en <= '0' after Tpd_clk_ctrl;
----------------------------------------------------------------
-- execute instruction, (EX, MEM, WB)
----------------------------------------------------------------
if debug = trace_each_step then
report "execute";
end if;
case IR_opcode is
when op_special =>
execute_op_special;
when op_fparith =>
execute_op_fparith;
when op_j =>
do_MEM_jump;
when op_jal =>
do_EX_link;
do_MEM_jump;
do_WB(To_X01(natural_to_bv(link_reg, 5)));
when op_jr =>
do_MEM_jump_reg;
when op_jalr =>
do_EX_link;
do_MEM_jump_reg;
do_WB(To_X01(natural_to_bv(link_reg, 5)));
when op_beqz | op_bnez =>
do_EX_branch;
if branch_taken then
do_MEM_branch;
end if;
when op_addi | op_subi | op_addui | op_subui
| op_slli | op_srli | op_srai
| op_andi | op_ori | op_xori =>
do_EX_arith_logic_immed;
do_WB(IR_Itype_rd);
when op_lhi =>
do_EX_lhi;
do_WB(IR_Itype_rd);
when op_sequi | op_sneui | op_sltui
| op_sgtui | op_sleui | op_sgeui =>
do_EX_set_unsigned(immed => true);
do_WB(IR_Itype_rd);
when op_seqi | op_snei | op_slti
| op_sgti | op_slei | op_sgei =>
do_EX_set_signed(immed => true);
do_WB(IR_Itype_rd);
when op_trap =>
report "TRAP instruction encountered, execution halted"
severity note;
wait until rising_edge(phi1);
halt <= '1' after Tpd_clk_ctrl;
wait until reset = '1';
exit;
when op_lb | op_lh | op_lw | op_lbu | op_lhu =>
do_EX_load_store;
do_MEM_load;
exit when reset = '1';
do_WB(IR_Itype_rd);
when op_sb | op_sh | op_sw =>
do_EX_load_store;
do_MEM_store;
exit when reset = '1';
when op_rfe | op_bfpt | op_bfpf | op_lf | op_ld | op_sf | op_sd =>
report opcode_names(bv_to_natural(IR_opcode))
& " instruction not implemented" severity warning;
when others =>
report "undefined instruction" severity error;
end case;
-- overflow and divide-by-zero exception handing
-- (not implemented)
if debug = trace_each_step then
report "end of execution";
end if;
end loop;
-- loop is only exited when reset active:
-- process interpreter starts again from beginning
end process sequencer;
end architecture behavior;
| gpl-2.0 | f6a3d1a02317a9222b085b48dae4dea5 | 0.417032 | 4.329453 | false | false | false | false |
snow4life/PipelinedDLX | alu/shifter_generic.vhd | 2 | 1,363 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
entity SHIFTER_GENERIC is
generic(N: integer);
port( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(4 downto 0);
LOGIC_ARITH: in std_logic; -- 1 = logic, 0 = arith
LEFT_RIGHT: in std_logic; -- 1 = left, 0 = right
SHIFT_ROTATE: in std_logic; -- 1 = shift, 0 = rotate
OUTPUT: out std_logic_vector(N-1 downto 0)
);
end entity SHIFTER_GENERIC;
architecture BEHAVIORAL of SHIFTER_GENERIC is
begin
SHIFT: process (A, B, LOGIC_ARITH, LEFT_RIGHT, SHIFT_ROTATE) is
begin
if SHIFT_ROTATE = '0' then
if LEFT_RIGHT = '0' then
OUTPUT <= to_StdLogicVector((to_bitvector(A)) ror (conv_integer(B)));
else
OUTPUT <= to_StdLogicVector((to_bitvector(A)) rol (conv_integer(B)));
end if;
else
if LEFT_RIGHT = '0' then
if LOGIC_ARITH = '0' then
OUTPUT <= to_StdLogicVector((to_bitvector(A)) sra (conv_integer(B)));
else
OUTPUT <= to_StdLogicVector((to_bitvector(A)) srl (conv_integer(B)));
end if;
else
if LOGIC_ARITH = '0' then
OUTPUT <= to_StdLogicVector((to_bitvector(A)) sla (conv_integer(B)));
else
OUTPUT <= to_StdLogicVector((to_bitvector(A)) sll (conv_integer(B)));
end if;
end if;
end if;
end process;
end architecture BEHAVIORAL;
| lgpl-2.1 | 4b7758a8b1316e894f336b66c87c5152 | 0.652238 | 2.963043 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1225.vhd | 4 | 3,436 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1225.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p28n01i01225ent IS
END c08s01b00x00p28n01i01225ent;
ARCHITECTURE c08s01b00x00p28n01i01225arch OF c08s01b00x00p28n01i01225ent IS
-- Local signals.
signal A : BIT;
BEGIN
TESTING: PROCESS
-- Local variables.
variable ShouldBeTime : TIME;
variable I : INTEGER;
variable k : integer := 0;
BEGIN
-- Make sure it takes an EVENT to trigger the WAIT statement.
A <= A after 2 ns, -- NOT an event.
(not A) after 4 ns; -- an event.
ShouldBeTime := NOW + 4 ns; -- Should wait for event.
wait on A;
if (ShouldBeTime /= Now) then
k := 1;
end if;
assert (ShouldBeTime = NOW)
report "Did not wait for 4ns";
-- If the value of the condition is FALSE, resuspend.
-- If the value is TRUE, the process will resume.
A <= '1' after 2 ns,
'0' after 4 ns;
-- Make sure that we wait until the second one for
-- the following wait statement to resume.
ShouldBeTime := NOW + 4 ns;
wait until (A = '0');
if (ShouldBeTime /= Now and A /= '0') then
k := 1;
end if;
assert (ShouldBeTime = NOW)
report "Did not wait for 4ns";
assert (A = '0')
report "Did not assign the correct value.";
-- Such resuspension does not involve the recalculation of the timeout interval.
-- If the value of the condition is FALSE, resuspend.
-- IF the value is TRUE, the process will resume.
A <= '1' after 2 ns,
'0' after 4 ns;
-- Make sure that we wait until the second one for
-- the following wait statement to resume.
ShouldBeTime := NOW + 3 ns;
wait until (A = '0') for 3 ns;
if (ShouldBeTime /= Now and A /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW)
report "Did not wait for 3ns";
assert (A = '1')
report "Did not assign the correct value to A.";
assert NOT( k=0 )
report "***PASSED TEST: c08s01b00x00p28n01i01225"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s01b00x00p28n01i01225 - The process will resume if the result of an event occuring on sentivity set is TRUE."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p28n01i01225arch;
| gpl-2.0 | 6911531df5b8eeda44a0785aec2b1267 | 0.624563 | 3.834821 | false | true | false | false |
tgingold/ghdl | testsuite/gna/ticket49/bug.vhdl | 3 | 471 | entity ent is
end entity;
architecture a of ent is
procedure set(x : integer; value : integer := 0) is
begin
end procedure;
procedure set(x : integer; y : integer; value : integer := 0) is
begin
end procedure;
procedure set(x : integer; y : integer; z : integer; value : integer := 0) is
begin
end procedure;
begin
main : process
begin
set(0, value => 1); -- Works
set(0, 1, value => 1); -- Does not work
end process;
end architecture;
| gpl-2.0 | e52b7a4b6cb17f0cfb35251551a9dd87 | 0.643312 | 3.568182 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_sofeof_gen.vhd | 3 | 19,880 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_sofeof_gen.vhd
-- Description: This entity manages
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_sofeof_gen is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axis_tready : in std_logic ; --
axis_tvalid : in std_logic ; --
axis_tlast : in std_logic ; --
--
packet_sof : out std_logic ; --
packet_eof : out std_logic --
--
);
end axi_dma_sofeof_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_sofeof_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_ready : std_logic := '0';
signal p_valid : std_logic := '0';
signal p_valid_d1 : std_logic := '0';
signal p_valid_re : std_logic := '0';
signal p_last : std_logic := '0';
signal p_last_d1 : std_logic := '0';
signal p_last_re : std_logic := '0';
signal s_ready : std_logic := '0';
signal s_valid : std_logic := '0';
signal s_valid_d1 : std_logic := '0';
signal s_valid_re : std_logic := '0';
signal s_last : std_logic := '0';
signal s_last_d1 : std_logic := '0';
signal s_last_re : std_logic := '0';
signal s_sof_d1_cdc_tig : std_logic := '0';
signal s_sof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_sof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_sof_d2 : SIGNAL IS "true";
signal s_sof_d3 : std_logic := '0';
signal s_sof_re : std_logic := '0';
signal s_sof : std_logic := '0';
signal p_sof : std_logic := '0';
signal s_eof_d1_cdc_tig : std_logic := '0';
signal s_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_eof_d2 : SIGNAL IS "true";
signal s_eof_d3 : std_logic := '0';
signal s_eof_re : std_logic := '0';
signal p_eof : std_logic := '0';
signal p_eof_d1_cdc_tig : std_logic := '0';
signal p_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_eof_d2 : SIGNAL IS "true";
signal p_eof_d3 : std_logic := '0';
signal p_eof_clr : std_logic := '0';
signal s_sof_generated : std_logic := '0';
signal sof_generated_fe : std_logic := '0';
signal s_eof_re_latch : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- pass internal version out
packet_sof <= s_sof_re;
packet_eof <= s_eof_re;
-- Generate for when primary clock is asynchronous
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---------------------------------------------------------------------------
-- Generate Packet SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid <= '0';
p_last <= '0';
p_ready <= '0';
else
p_valid <= axis_tvalid;
p_last <= axis_tlast ;
p_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid_d1 <= '0';
p_last_d1 <= '0';
p_last_re <= '0';
else
p_valid_d1 <= p_valid and p_ready;
p_last_d1 <= p_last and p_valid and p_ready;
-- register to aligne with setting of p_sof
p_last_re <= p_ready and p_valid and p_last and not p_last_d1;
end if;
end if;
end process REG_FOR_RE;
p_valid_re <= p_ready and p_valid and not p_valid_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- clear at end of packet
if(p_reset_n = '0' or p_eof_clr = '1')then
p_sof <= '0';
-- assert at beginning of packet hold to allow
-- clock crossing to slower secondary clk
elsif(p_valid_re = '1')then
p_sof <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_sof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_sof_d2,
scndry_vect_out => open
);
SOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_sof_d1_cdc_tig <= '0';
-- s_sof_d2 <= '0';
s_sof_d3 <= '0';
else
-- s_sof_d1_cdc_tig <= p_sof;
-- s_sof_d2 <= s_sof_d1_cdc_tig;
s_sof_d3 <= s_sof_d2;
end if;
end if;
end process SOF_REG2SCNDRY1;
s_sof_re <= s_sof_d2 and not s_sof_d3;
---------------------------------------------------------------------------
-- Generate Packet EOF
---------------------------------------------------------------------------
-- Sample and hold valid re to create sof
EOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or p_eof_clr = '1')then
p_eof <= '0';
-- if p_last but p_sof not set then it means between pkt
-- gap was too small to catch new sof. therefor do not
-- generate eof
elsif(p_last_re = '1' and p_sof = '0')then
p_eof <= '0';
elsif(p_last_re = '1')then
p_eof <= '1';
end if;
end if;
end process EOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
-- CDC register has to be a pure flop
EOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_eof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_eof_d2,
scndry_vect_out => open
);
EOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_eof_d1_cdc_tig <= '0';
-- s_eof_d2 <= '0';
s_eof_d3 <= '0'; -- CR605883
else
-- s_eof_d1_cdc_tig <= p_eof;
-- s_eof_d2 <= s_eof_d1_cdc_tig;
s_eof_d3 <= s_eof_d2; -- CR605883
end if;
end if;
end process EOF_REG2SCNDRY1;
s_eof_re <= s_eof_d2 and not s_eof_d3;
EOF_latch : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_eof_re_latch <= '0';
elsif (s_eof_re = '1') then
s_eof_re_latch <= not s_eof_re_latch;
end if;
end if;
end process EOF_latch;
-- Register s_sof_re back into primary clock domain to use
-- as clear of p_sof.
EOF_REG2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_eof_re_latch,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_eof_d2,
scndry_vect_out => open
);
EOF_REG2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_eof_d1_cdc_tig <= '0';
-- p_eof_d2 <= '0';
p_eof_d3 <= '0';
else
-- p_eof_d1_cdc_tig <= s_eof_re_latch;
-- p_eof_d2 <= p_eof_d1_cdc_tig;
p_eof_d3 <= p_eof_d2;
end if;
end if;
end process EOF_REG2PRMRY1;
-- p_eof_clr <= p_eof_d2 and not p_eof_d3;-- CR565366
-- drive eof clear for minimum of 2 scndry clocks
-- to guarentee secondary capture. this allows
-- new valid assertions to not be missed in
-- creating next sof.
p_eof_clr <= p_eof_d2 xor p_eof_d3;
end generate GEN_FOR_ASYNC;
-- Generate for when primary clock is synchronous
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
---------------------------------------------------------------------------
-- Generate Packet EOF and SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid <= '0';
s_last <= '0';
s_ready <= '0';
else
s_valid <= axis_tvalid;
s_last <= axis_tlast ;
s_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid_d1 <= '0';
s_last_d1 <= '0';
else
s_valid_d1 <= s_valid and s_ready;
s_last_d1 <= s_last and s_valid and s_ready;
end if;
end if;
end process REG_FOR_RE;
-- CR565366 investigating delay interurpt issue discovered
-- this coding issue.
-- s_valid_re <= s_ready and s_valid and not s_last_d1;
s_valid_re <= s_ready and s_valid and not s_valid_d1;
s_last_re <= s_ready and s_valid and s_last and not s_last_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(p_reset_n = '0' or s_eof_re = '1')then
s_sof_generated <= '0';
-- new
elsif((s_valid_re = '1')
or (sof_generated_fe = '1' and s_ready = '1' and s_valid = '1'))then
s_sof_generated <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_sof_d1_cdc_tig <= '0';
else
s_sof_d1_cdc_tig <= s_sof_generated;
end if;
end if;
end process SOF_REG2SCNDRY;
-- generate falling edge pulse on end of packet for use if
-- need to generate an immediate sof.
sof_generated_fe <= not s_sof_generated and s_sof_d1_cdc_tig;
-- generate SOF on rising edge of valid if not already in a packet OR...
s_sof_re <= '1' when (s_valid_re = '1' and s_sof_generated = '0')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1') -- and valid asserted
else '0';
-- generate eof on rising edge of valid last assertion OR...
s_eof_re <= '1' when (s_last_re = '1')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1' -- and valid asserted
and s_last = '1') -- and last asserted
else '0';
end generate GEN_FOR_SYNC;
end implementation;
| gpl-3.0 | e3851ddf2c21ff24fdffb1fb9a5c2fe9 | 0.443511 | 4.08046 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/input_split1.vhd | 2 | 1,822 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity input_split1 is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
wa0_en : in std_logic;
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(4 downto 0);
ra3_data : out std_logic_vector(31 downto 0);
ra3_addr : in std_logic_vector(4 downto 0);
clk : in std_logic
);
end input_split1;
architecture augh of input_split1 is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
ra3_data <= ram( to_integer(ra3_addr) );
ra1_data <= ram( to_integer(ra1_addr) );
ra2_data <= ram( to_integer(ra2_addr) );
end architecture;
| gpl-2.0 | a906bdd48df95d995ac2e32a980991ab | 0.670143 | 2.781679 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue418/tc749.vhdl | 1 | 17,811 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY tc749 IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END tc749;
ARCHITECTURE arch OF tc749 IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st := (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a :record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records:= (C50,C51,C53,C77,C54b);
constant C86: array_rec_cons (0 to 7) :=(others => C51);
signal V1 : boolean_vector(zero to fifteen) ;
signal V2 : severity_level_vector(zero to fifteen);
signal V3 : integer_vector(zero to fifteen) ;
signal V4 : real_vector(zero to fifteen) ;
signal V5 : time_vector (zero to fifteen);
signal V6 : natural_vector(zero to fifteen);
signal V7 : positive_vector(zero to fifteen);
signal V8 : boolean_cons_vector;
signal V9 : severity_level_cons_vector ;
signal V10 : integer_cons_vector;
signal V11 : real_cons_vector;
signal V12 : time_cons_vector ;
signal V13 : natural_cons_vector ;
signal V14 : positive_cons_vector ;
signal V15 : boolean_cons_vectorofvector ;
signal V16 : severity_level_cons_vectorofvector;
signal V17 : integer_cons_vectorofvector;
signal V18 : real_cons_vectorofvector;
signal V19 : time_cons_vectorofvector;
signal V20 : natural_cons_vectorofvector;
signal V21 : positive_cons_vectorofvector;
signal V22 : record_std_package;
signal V23 : record_cons_array ;
signal V24 : record_cons_arrayofarray ;
signal V25 : boolean_vector_st ;
signal V26 : severity_level_vector_st ;
signal V27 : integer_vector_st ;
signal V28 : real_vector_st ;
signal V29 : time_vector_st ;
signal V30 : natural_vector_st ;
signal V31 : positive_vector_st ;
signal V32 : record_array_st ;
signal V33 : record_array_st ;
signal V34 : record_array_new ;
signal V35 : record_of_records ;
signal V49 : array_rec_cons(zero to seven) ;
BEGIN
V1 <= (zero to fifteen => C1);
V2 <= (zero to fifteen => C4);
V3 <= (zero to fifteen => C5);
V4 <= (zero to fifteen => C6);
V5 <= (zero to fifteen => C7);
V6 <= (zero to fifteen => C8);
V7 <= (zero to fifteen => C9);
V8 <= C19;
V9 <= C20;
V10 <= C21;
V11 <= C22;
V12 <= C23;
V13 <= C24;
V14 <= C25;
V15 <= C26;
V16 <= C27;
V17 <= C28;
V18 <= C29;
V19 <= C30;
V20 <= C31;
V21 <= C32;
V22 <= C50;
V23 <= C51;
V24 <= C53;
V25 <= C70;
V26 <= C71;
V27 <= C72;
V28 <= C73;
V29 <= C74;
V30 <= C75;
V31 <= C76;
V32 <= C54a;
V33 <= C54a;
V34 <= C54b;
V35 <= C55;
V49 <= C86;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V49= C86 )
report "***PASSED TEST: c01s01b01x01p05n02i00749"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V49= C86 )
report "***FAILED TEST: c01s01b01x01p05n02i00749 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END arch;
| gpl-2.0 | 3c5f55b9b0a9a837e72ec41f768d5427 | 0.541632 | 3.752845 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sts_mngr.vhd | 3 | 11,867 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
| gpl-3.0 | 8a3f1ef391fce70e683a23c8c50bf5df | 0.447965 | 4.459602 | false | false | false | false |
nickg/nvc | lib/synopsys/std_logic_misc.vhd | 1 | 32,988 | --------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
| gpl-3.0 | 40f66464e070a92cbf64127f6aeb281c | 0.406572 | 3.366466 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug071/atod.vhdl | 1 | 1,272 | entity atod is
end atod;
architecture behav of atod is
type real_array is array (natural range <>) of real;
constant csts : real_array :=
(1.0,
0.0,
-- Corner cases from
-- http://www.exploringbinary.com/
-- decimal-to-realing-point-needs-arbitrary-precision/
7.8459735791271921e65,
-- In binary:
-- 1.11011100 11010000 00001000 10011100 00010011 00010100 1110 e218
-- 1. d c d 0 0 8 9 c 1 3 1 4 e
3.571e266,
-- 1.01100010 01100100 01001100 01100001 11010100 00011010 1010 e885
-- 1. 6 2 6 4 4 c 6 1 d 4 1 a a
3.08984926168550152811E-32,
-- 1.01000000 11011110 01001000 01100111 01100110 01010011 1011 e-105
-- 1. 4 0 d e 4 8 6 7 6 6 5 3 b
7.4505805969238281e-09
-- 1.00000000 e-27
);
begin
process
variable v : real;
begin
for i in csts'range loop
report to_string (csts (i), "%a") severity note;
end loop;
v := csts (2);
assert to_string (v, "%.13a") = "0x1.dcd0089c1314ep+218" severity failure;
v := csts (3);
assert to_string (v, "%.13a") = "0x1.62644c61d41aap+885" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 5698842bf7bac833f44c95b6c20bc2bb | 0.569182 | 2.930876 | false | false | false | false |
nickg/nvc | test/regress/array1.vhd | 1 | 715 | entity array1 is
end entity;
architecture test of array1 is
type matrix_t is array (integer range <>, integer range <>) of integer;
constant c : matrix_t(0 to 1, 0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
process is
variable m : matrix_t(1 to 3, 1 to 3) := (
( 1, 2, 3 ),
( 4, 5, 6 ),
( 7, 8, 9 ) );
begin
report integer'image(m(1, 3));
report integer'image(m(2, 2));
assert m(2, 2) = 5;
assert m(3, 1) = 7;
report integer'image(c(1, 0));
assert c(1, 0) = 3;
assert c = ( (1, 2), (3, 4) );
assert c /= ( (1, 2), (3, 5) );
wait;
end process;
end architecture;
| gpl-3.0 | 65bbc16618b8a632440b8183eedcad21 | 0.453147 | 3.135965 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug060/corelib.v08.vhdl | 2 | 1,483 | -- EMACS settings: -*- tab-width: 2;indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2;replace-tabs off;indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Protected type implementations.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
package corelib is
-- Lists
package Integer_List_Pkg is new work.corelib_List
generic map (ELEMENT_TYPE => integer);
alias Integer_List is Integer_List_Pkg.PT_List;
end package;
| gpl-2.0 | d3fffb995bbb4d5ad10044f0d695172b | 0.581254 | 4.563077 | false | false | false | false |
tgingold/ghdl | testsuite/synth/func01/tb_func08.vhdl | 1 | 604 | entity tb_func08 is
end tb_func08;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func08 is
signal v : std_ulogic_vector(31 downto 0);
signal r : integer;
begin
dut: entity work.func08
port map (v, r);
process
begin
v <= x"00000000";
wait for 1 ns;
assert r = 32 severity failure;
v <= x"0000_0001";
wait for 1 ns;
assert r = 31 severity failure;
v <= x"8000_0000";
wait for 1 ns;
assert r = 0 severity failure;
v <= x"0001_00f0";
wait for 1 ns;
assert r = 15 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 02ed3946a9322f29a6bdc4f88b5521a1 | 0.622517 | 3.247312 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue797/pkg_c.vhdl | 1 | 1,673 | package pkg_c is
type byte_vector_access_t is access string;
type extbuf_access_t is access string(1 to integer'high);
impure function
get_addr(
id : integer
) return extbuf_access_t;
attribute foreign of get_addr : function is "VHPIDIRECT get_addr";
impure function
get_baddr(
id : integer
) return byte_vector_access_t;
attribute foreign of get_baddr : function is "VHPIDIRECT get_baddr";
procedure
set(
index : natural;
value : natural
);
impure function
get(
index : natural
) return natural;
end pkg_c;
package body pkg_c is
impure function
get_addr(
id : integer
) return extbuf_access_t is begin
assert false report "VHPI get_addr" severity failure;
end;
impure function
get_baddr(
id : integer
) return byte_vector_access_t is begin
assert false report "VHPI get_baddr" severity failure;
end;
procedure
set(
index : natural;
value : natural
) is
variable a : extbuf_access_t := get_addr(0);
variable b : byte_vector_access_t := get_baddr(0);
variable c : byte_vector_access_t(1 to integer'high) := get_baddr(0);
begin
a(index+1) := character'val(value);
--b(index+1) := character'val(value);
c(index+1) := character'val(value);
end;
impure function
get(
index : natural
) return natural is
variable a : extbuf_access_t := get_addr(0);
variable b : byte_vector_access_t := get_baddr(0);
variable c : byte_vector_access_t(1 to integer'high) := get_baddr(0);
begin
return character'pos(a(index+1));
--return character'pos(b(index+1));
return character'pos(c(index+1));
end;
end pkg_c;
| gpl-2.0 | 58bb462adcb0ca50b4a58c0c88a34e93 | 0.653915 | 3.442387 | false | false | false | false |
mistryalok/FPGA | Xilinx/ISE/Basics/T_flipflop/T_flipflop.vhd | 1 | 1,177 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:12:57 05/02/2013
-- Design Name:
-- Module Name: T_flipflop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity T_flipflop is
Port ( clk : in STD_LOGIC;
T : in STD_LOGIC;
Q : inout STD_LOGIC;
Qn : inout STD_LOGIC);
end T_flipflop;
architecture Behavioral of T_flipflop is
begin
Q <= '0';
Qn <= '0';
process(T,clk)
variable temp : std_logic;
begin
temp := Q;
if(clk'event and clk = '1') then
Q <= not temp;
Qn <= temp;
end if;
end process;
end Behavioral;
| gpl-3.0 | 380c6870c1fd874bffd18554825931a7 | 0.527613 | 3.621538 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | CLAH/CLA4bits/CLA4bits.vhd | 1 | 993 | LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLA4bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
P, G: OUT STD_LOGIC
);
END CLA4bits;
ARCHITECTURE strc_cla4bits of CLA4bits is
SIGNAL Sum,Gen,Prop,Carry:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- soma dos valores e propagação do carry --
Sum<=val1 xor val2;
Prop<=val1 or val2;
Gen<=val1 and val2;
PROCESS (Gen,Prop,Carry)
BEGIN
Carry(1) <= Gen(0) OR (Prop(0) AND CarryIn);
inst: FOR i IN 1 TO 2 LOOP
Carry(i+1) <= Gen(i) OR (Prop(i) AND Carry(i));
END LOOP;
END PROCESS;
SomaResult(0) <= Sum(0) XOR CarryIn;
SomaResult(3 DOWNTO 1) <= Sum(3 DOWNTO 1) XOR Carry(3 DOWNTO 1);
P <= Prop(3) AND Prop(2) AND Prop(1) AND Prop(0);
G <= Gen(3) OR (Prop(3) AND Gen(2)) OR (Prop(3) AND Prop(2) AND Gen(1)) OR (Prop(3) AND Prop(2) AND Prop(1) AND Gen(0));
END strc_cla4bits; | mit | 13d5604c071e26ae145793f817478e15 | 0.64149 | 2.67655 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue238/proc1.vhdl | 2 | 423 | entity proc1 is
end;
use work.pkg.all;
architecture behav of proc1 is
procedure proc (v : inout rec) is
begin
v.a := 5;
assert v.a = 5 severity failure;
v.s := "Good";
assert v.a = 5 severity failure;
assert v.s = "Good" severity failure;
assert false report "ok" severity note;
end proc;
begin
process
variable v : rec_4;
begin
proc (v);
wait;
end process;
end behav;
| gpl-2.0 | 747ccb4444492266bcc773daa6c8d33f | 0.621749 | 3.27907 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug090/crash14.vhdl | 1 | 1,038 | library ieee;
use ieee.std_logic_1164.all;
entity clkgen is
generic (period : time :type ns);
# port (signal clk : out std_lo
cclk : clkgen
generic map (period => 20 ns)
port map (clk => clk);
rst_n <= '0' after 0 ns, '1' after 4 ns;
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else q <= d;
end if;
end if;
end process p;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report "start of tb" severity note;
for i in 0 to 10 loop
case i is
when 0 | 3 =>
for i in din'range loop
din(i) <= '0';
end loop;
when 1 => din <= b"00110011";
when 2 => v := 0;
while v < 7 loop
din (v) <= '1';
v := v + 1;
end loop;
when 4 to 5 | 8 => din <= x"a5"; when others =>
null;
end case;
end loop;
wait until clk = '0';
end process;
assert false report "Hello world" severity note;
end behav;
| gpl-2.0 | a0c22f81fdbb49525f2c101d021def74 | 0.520231 | 3.28481 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1735.vhd | 4 | 3,686 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1735.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p06n01i01735ent IS
END c09s04b00x00p06n01i01735ent;
ARCHITECTURE c09s04b00x00p06n01i01735arch OF c09s04b00x00p06n01i01735ent IS
signal arch_s1 : bit;
signal arch_s2 : boolean;
signal arch_s3 : character;
signal arch_s4 : severity_level;
signal arch_s5 : integer;
signal arch_s6 : real;
signal arch_s7 : time;
signal arch_s8 : positive;
signal arch_s9 : natural;
BEGIN
ASSERT arch_s1 /= bit'left
REPORT "bit concurrent assertion"
severity NOTE;
ASSERT arch_s2 /= boolean'left
REPORT "boolean concurrent assertion"
severity NOTE;
ASSERT arch_s3 /= character'left
REPORT "character concurrent assertion"
severity NOTE;
ASSERT arch_s4 /= severity_level'left
REPORT "severity_level concurrent assertion"
severity NOTE;
ASSERT arch_s5 /= integer'left
REPORT "integer concurrent assertion"
severity NOTE;
ASSERT arch_s6 /= real'left
REPORT "real concurrent assertion"
severity NOTE;
ASSERT arch_s7 /= time'left
REPORT "time concurrent assertion"
severity NOTE;
ASSERT arch_s8 /= positive'left
REPORT "positive concurrent assertion"
severity NOTE;
ASSERT arch_s9 /= natural'left
REPORT "natural concurrent assertion"
severity NOTE;
TESTING: PROCESS
BEGIN
ASSERT arch_s1 /= bit'left
REPORT "bit concurrent assertion"
severity NOTE;
ASSERT arch_s2 /= boolean'left
REPORT "boolean concurrent assertion"
severity NOTE;
ASSERT arch_s3 /= character'left
REPORT "character concurrent assertion"
severity NOTE;
ASSERT arch_s4 /= severity_level'left
REPORT "severity_level concurrent assertion"
severity NOTE;
ASSERT arch_s5 /= integer'left
REPORT "integer concurrent assertion"
severity NOTE;
ASSERT arch_s6 /= real'left
REPORT "real concurrent assertion"
severity NOTE;
ASSERT arch_s7 /= time'left
REPORT "time concurrent assertion"
severity NOTE;
ASSERT arch_s8 /= positive'left
REPORT "positive concurrent assertion"
severity NOTE;
ASSERT arch_s9 /= natural'left
REPORT "natural concurrent assertion"
severity NOTE;
assert FALSE
report "***PASSED TEST: c09s04b00x00p06n01i01735 - This need manual check - The concurrent assertion statement and the sequential assertion should print out the same ASSERTION NOTES."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s04b00x00p06n01i01735arch;
| gpl-2.0 | 32f8c68ca15585112a635351e22d64b1 | 0.680141 | 4.12766 | false | false | false | false |
tgingold/ghdl | libraries/std/textio-body.vhdl | 1 | 41,830 | -- Std.Textio package body. This file is part of GHDL.
-- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
package body textio is
attribute foreign : string; --V87
--START-V08
-- LRM08 16.4
-- The JUSTIFY operation formats a string value within a field that is at
-- least at long as required to contain the value. Parameter FIELD
-- specifies the desired field width. Since the actual field width will
-- always be at least large enough to hold the string value, the default
-- value 0 for the FIELD parameter has the effect of causing the string
-- value to be contained in a field of exactly the right widteh (i.e., no
-- additional leading or tailing spaces). Parameter JUSTIFIED specified
-- whether the string value is to be right- or left-justified within the
-- field; the default is right-justified. If the FIELD parameter describes
-- a field width larger than the number of characters in the string value,
-- space characters are used to fill the remaining characters in the field.
--
-- TG: Note that the bounds of the result are not specified!
function Justify (Value: String;
Justified : Side := Right;
Field: Width := 0 ) return String
is
constant len : Width := Value'Length;
begin
if Field <= Len then
return Value;
else
case Justified is
when Right =>
return (1 to Field - Len => ' ') & Value;
when Left =>
return Value & (1 to Field - Len => ' ');
end case;
end if;
end Justify;
--END-V08
-- output routines for standard types
-- TIME_NAMES associates time units with textual names.
-- Textual names are in lower cases, since according to LRM93 14.3:
-- when written, the identifier is expressed in lowercase characters.
-- The length of the names are 3 characters, the last one may be a space
-- for 2 characters long names.
type time_unit is
record
val : time;
name : string (1 to 3);
end record;
type time_names_type is array (1 to 8) of time_unit;
constant time_names : time_names_type :=
((fs, "fs "), (ps, "ps "), (ns, "ns "), (us, "us "),
(ms, "ms "), (sec, "sec"), (min, "min"), (hr, "hr "));
-- Non breaking space character. --!V87
constant nbsp : character := character'val (160); --!V87
function is_whitespace (c : character) return Boolean is
begin
case c is
when ' '
| NBSP --!V87
| HT =>
return True;
when others =>
return False;
end case;
end is_Whitespace;
procedure writeline (variable f: out text; l: inout line) is --V87
procedure writeline (file f: text; l: inout line) is --!V87
begin
if l = null then
-- LRM93 14.3
-- If parameter L contains a null access value at the start of the call,
-- the a null string is written to the file.
null;
else
-- LRM93 14.3
-- Procedure WRITELINE causes the current line designated by parameter L
-- to be written to the file and returns with the value of parameter L
-- designating a null string.
write (f, l.all);
deallocate (l);
l := new string'("");
end if;
write (f, (1 => LF));
end writeline;
--START-V08
procedure Tee (file f : Text; L : inout LINE) is
begin
-- LRM08 16.4 Package TEXTIO
-- The procedure TEE additionally causes the current line to be written
-- to the file OUTPUT.
if l = null then
null;
else
write (f, l.all);
write (Output, l.all);
deallocate (l);
l := new string'("");
end if;
write (f, (1 => LF));
write (output, (1 => LF));
end Tee;
--END-V08
procedure write
(l: inout line; value: in string;
justified: in side := right; field: in width := 0)
is
variable length: natural;
variable nl: line;
begin
-- l can be null.
if l = null then
length := 0;
else
length := l.all'length;
end if;
if value'length < field then
nl := new string (1 to length + field);
if length /= 0 then
nl (1 to length) := l.all;
end if;
if justified = right then
nl (length + 1 to length + field - value'length) := (others => ' ');
nl (nl.all'high - value'length + 1 to nl.all'high) := value;
else
nl (length + 1 to length + value'length) := value;
nl (length + value'length + 1 to nl.all'high) := (others => ' ');
end if;
else
nl := new string (1 to length + value'length);
if length /= 0 then
nl (1 to length) := l.all;
end if;
nl (length + 1 to nl.all'high) := value;
end if;
deallocate (l);
l := nl;
end write;
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0)
is
variable str: string (11 downto 1);
variable val: integer := value;
variable digit: natural;
variable index: natural := 0;
begin
-- Note: the absolute value of VAL cannot be directly taken, since
-- it may be greather that the maximum value of an INTEGER.
loop
-- LRM93 7.2.6
-- (A rem B) has the sign of A and an absolute value less then
-- the absoulte value of B.
digit := abs (val rem 10);
val := val / 10;
index := index + 1;
str (index) := character'val(48 + digit);
exit when val = 0;
end loop;
if value < 0 then
index := index + 1;
str(index) := '-';
end if;
write (l, str (index downto 1), justified, field);
end write;
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0)
is
begin
if value then
write (l, string'("TRUE"), justified, field);
else
write (l, string'("FALSE"), justified, field);
end if;
end write;
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0)
is
variable str: string (1 to 1);
begin
str (1) := value;
write (l, str, justified, field);
end write;
function bit_to_char (value : in bit) return character is
begin
case value is
when '0' =>
return '0';
when '1' =>
return '1';
end case;
end bit_to_char;
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0)
is
variable str : string (1 to 1);
begin
str (1) := bit_to_char (value);
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0)
is
constant length : natural := value'length;
alias n_value : bit_vector (1 to value'length) is value;
variable str : string (1 to length);
begin
for i in str'range loop
str (i) := bit_to_char (n_value (i));
end loop;
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns)
is
-- Copy of VALUE on which we are working.
variable val : time := value;
-- Copy of UNIT on which we are working.
variable un : time := unit;
-- Digit extract from VAL/UN.
variable d : integer; -- natural range 0 to 9;
-- Index for unit name.
variable n : integer;
-- Result.
variable str : string (1 to 28);
-- Current character in RES.
variable pos : natural := 1;
-- Add a character to STR.
procedure add_char (c : character) is
begin
str (pos) := c;
pos := pos + 1;
end add_char;
begin
-- Note:
-- Care is taken to avoid overflow. Time may be 64 bits while integer
-- may be only 32 bits.
-- Handle sign.
-- Note: VAL cannot be negated since its range may be not symetric
-- around 0.
if val < 0 ns then
add_char ('-');
end if;
-- Search for the first digit.
-- Note: we must start from unit, since all units are not a power of 10.
-- Note: UN can be multiplied only after we know it is possible. This
-- is a to avoid overflow.
if un <= 0 sec then
assert false report "UNIT argument is not positive" severity error;
un := ns;
end if;
while val / 10 >= un or val / 10 <= -un loop
un := un * 10;
end loop;
-- Extract digits one per one.
loop
d := val / un;
add_char (character'val (abs d + character'pos ('0')));
val := val - d * un;
exit when val = 0 ns and un <= unit;
if un = unit then
add_char ('.');
end if;
-- Stop as soon as precision will be lost.
-- This can happen only for hr and min.
-- FIXME: change the algorithm to display all the digits.
exit when (un / 10) * 10 /= un;
un := un / 10;
end loop;
add_char (' ');
-- Search the time unit name in the time table.
n := 0;
for i in time_names'range loop
if time_names (i).val = unit then
n := i;
exit;
end if;
end loop;
assert n /= 0 report "UNIT argument is not a unit name" severity error;
if n = 0 then
add_char ('?');
else
add_char (time_names (n).name (1));
add_char (time_names (n).name (2));
if time_names (n).name (3) /= ' ' then
add_char (time_names (n).name (3));
end if;
end if;
-- Write the result.
write (l, str (1 to pos - 1), justified, field);
end write;
procedure textio_write_real
(s : out string; len : out natural; value: real; ndigits : natural);
attribute foreign of textio_write_real : procedure is "GHDL intrinsic";
procedure textio_write_real
(s : out string; len : out natural; value: real; ndigits : natural) is
begin
assert false report "must not be called" severity failure;
end textio_write_real;
-- Parameter DIGITS specifies how many digits to the right of the decimal
-- point are to be output when writing a real number; the default value 0
-- indicates that the number should be output in standard form, consisting
-- of a normalized mantissa plus exponent (e.g., 1.079236E23). If DIGITS is
-- nonzero, then the real number is output as an integer part followed by
-- '.' followed by the fractional part, using the specified number of digits
-- (e.g., 3.14159).
-- Note: Nan, +Inf, -Inf are not to be considered, since these numbers are
-- not in the bounds defined by any real range.
procedure write (L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0)
is
-- STR contains the result of the conversion.
variable str : string (1 to 320);
variable len : natural;
begin
textio_write_real (str, len, value, digits);
assert len <= str'length severity failure;
write (l, str (1 to len), justified, field);
end write;
--START-V08
procedure Owrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0) is
begin
write (l, to_ostring (value), justified, field);
end Owrite;
procedure Hwrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0) is
begin
write (l, to_hstring (value), justified, field);
end Hwrite;
--END-V08
procedure untruncated_text_read --V87
(variable f : text; str : out string; len : out natural); --V87
procedure untruncated_text_read --!V87
(file f : text; str : out string; len : out natural); --!V87
attribute foreign of untruncated_text_read : procedure is "GHDL intrinsic";
procedure untruncated_text_read
(variable f : text; str : out string; len : out natural) is --V87
(file f : text; str : out string; len : out natural) is --!V87
begin
assert false report "must not be called" severity failure;
end untruncated_text_read;
procedure readline (variable f: in text; l: inout line) --V87
procedure readline (file f: text; l: inout line) --!V87
is
variable len, nlen, posn : natural;
variable nl, old_l : line;
variable str : string (1 to 128);
variable is_eol : boolean;
begin
-- LRM93 14.3
-- If parameter L contains a non-null access value at the start of the
-- call, the object designated by that value is deallocated before the
-- new object is created.
if l /= null then
deallocate (l);
end if;
-- End of file is not expected. The user should check endfile before
-- calling readline.
assert not endfile (f)
report "eof in std.textio.readline" severity failure;
-- We read the input in 128-byte chunks.
-- We keep reading until we reach a newline or there is no more input.
-- The loop invariant is that old_l is allocated and contains the
-- previous chunks read, and posn = old_l.all'length.
posn := 0;
loop
untruncated_text_read (f, str, len);
exit when len = 0;
if str (len) = LF then
-- LRM 14.3
-- The representation of the line does not contain the representation
-- of the end of the line.
is_eol := true;
len := len - 1;
-- End of line is any of LF/CR/CR+LF. This is now handled
-- by untruncated_text_read because we need to do a look-ahead.
elsif endfile (f) then
is_eol := true;
else
is_eol := false;
end if;
l := new string (1 to posn + len);
if old_l /= null then
l (1 to posn) := old_l (1 to posn);
deallocate (old_l);
end if;
l (posn + 1 to posn + len) := str (1 to len);
exit when is_eol;
posn := posn + len;
old_l := l;
end loop;
end readline;
-- Replaces L with L (LEFT to/downto L'RIGHT)
procedure trim (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
if left > l'right then
nl := new string'("");
else
nl := new string (left to l'right);
-- nl := new string (1 to l'right + 1 - left);
nl.all := l (left to l'right);
end if;
else
-- Descending
if left < l'right then
nl := new string'("");
else
nl := new string (left downto l'right);
-- nl := new string (left - l'right + 1 downto 1);
nl.all := l (left downto l'right);
end if;
end if;
deallocate (l);
l := nl;
end trim;
-- Replaces L with L (LEFT + 1 to L'RIGHT or LEFT - 1 downto L'RIGHT)
procedure trim_next (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
trim (l, left + 1);
else
-- Descending
trim (l, left - 1);
end if;
end trim_next;
function to_lower (c : character) return character is
begin
if c >= 'A' and c <= 'Z' then
return character'val (character'pos (c) + 32);
else
return c;
end if;
end to_lower;
procedure read (l: inout line; value: out character; good: out boolean)
is
variable nl : line;
begin
if l = null or l'length = 0 then
good := false;
else
value := l (l'left);
trim_next (l, l'left);
good := true;
end if;
end read;
procedure read (l: inout line; value: out character)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "character read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit; good: out boolean)
is
begin
good := false;
for i in l'range loop
case l(i) is
when ' '
| NBSP --!V87
| HT =>
null;
when '1' =>
value := '1';
good := true;
trim_next (l, i);
return;
when '0' =>
value := '0';
good := true;
trim_next (l, i);
return;
when others =>
return;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out bit)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit_vector; good: out boolean)
is
-- Number of bit to parse.
variable len : natural;
variable pos, last : natural;
variable res : bit_vector (1 to value'length);
-- State of the previous byte:
-- LEADING: blank before the bit vector.
-- FOUND: bit of the vector.
type state_type is (leading, found);
variable state : state_type;
begin
-- Initialization.
len := value'length;
if len = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := leading;
pos := res'left;
for i in l'range loop
case l(i) is
when ' '
| NBSP --!V87
| HT =>
case state is
when leading =>
null;
when found =>
return;
end case;
when '1' | '0' =>
case state is
when leading =>
state := found;
when found =>
null;
end case;
if l(i) = '0' then
res (pos) := '0';
else
res (pos) := '1';
end if;
pos := pos + 1;
len := len - 1;
last := i;
exit when len = 0;
when others =>
return;
end case;
end loop;
if len /= 0 then
-- Not enough bits.
return;
end if;
-- Note: if LEN = 0, then FIRST and LAST have been set.
good := true;
value := res;
trim_next (l, last);
return;
end read;
procedure read (l: inout line; value: out bit_vector)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit_vector read failure"
severity failure;
end read;
procedure read (l: inout line; value: out boolean; good: out boolean)
is
-- State:
-- BLANK: space are being scaned.
-- L_TF : T(rue) or F(alse) has been scanned.
-- L_RA : (t)R(ue) or (f)A(lse) has been scanned.
-- L_UL : (tr)U(e) or (fa)L(se) has been scanned.
-- L_ES : (tru)E or (fal)S(e) has been scanned.
type state_type is (blank, l_tf, l_ra, l_ul, l_es);
variable state : state_type;
-- Set to TRUE if T has been scanned, to FALSE if F has been scanned.
variable res : boolean;
variable c : character;
begin
-- By default, it is a failure.
good := false;
state := blank;
for i in l'range loop
c := l (i);
case state is
when blank =>
if is_whitespace (c) then
null;
elsif c = 'f' or c = 'T' then
res := true;
state := l_tf;
elsif c = 'f' or c = 'F' then
res := false;
state := l_tf;
else
return;
end if;
when l_tf =>
if res = true and (c = 'r' or c = 'R') then
state := l_ra;
elsif res = false and (c = 'a' or C = 'A') then
state := l_ra;
else
return;
end if;
when l_ra =>
if res = true and (c = 'u' or C = 'U') then
state := l_ul;
elsif res = false and (c = 'l' or c = 'L') then
state := l_ul;
else
return;
end if;
when l_ul =>
if res = true and (c = 'e' or c = 'E') then
trim_next (l, i);
good := true;
value := true;
return;
elsif res = false and (c = 's' or c = 'S') then
state := l_es;
else
return;
end if;
when l_es =>
if res = false and (c = 'e' or c = 'E') then
trim_next (l, i);
good := true;
value := false;
return;
else
return;
end if;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out boolean)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "boolean read failure"
severity failure;
end read;
function char_to_nat (c : character) return natural
is
begin
return character'pos (c) - character'pos ('0');
end char_to_nat;
procedure read (l: inout line; value: out integer; good: out boolean)
is
variable val : integer;
variable d : natural;
type state_t is (leading, sign, digits);
variable cur_state : state_t := leading;
begin
val := 1;
for i in l'range loop
case cur_state is
when leading =>
case l(i) is
when ' '
| NBSP --!V87
| ht =>
null;
when '+' =>
cur_state := sign;
when '-' =>
val := -1;
cur_state := sign;
when '0' to '9' =>
val := char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when sign =>
case l(i) is
when '0' to '9' =>
val := val * char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when digits =>
case l(i) is
when '0' to '9' =>
d := char_to_nat (l(i));
val := val * 10;
if val < 0 then
val := val - d;
else
val := val + d;
end if;
when others =>
trim (l, i);
good := true;
value := val;
return;
end case;
end case;
end loop;
deallocate (l);
l := new string'("");
if cur_state /= leading then
good := true;
value := val;
else
good := false;
end if;
end read;
procedure read (l: inout line; value: out integer)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "integer read failure"
severity failure;
end read;
function textio_read_real (s : string) return real;
attribute foreign of textio_read_real : function is "GHDL intrinsic";
function textio_read_real (s : string) return real is
begin
assert false report "must not be called" severity failure;
return 0.0;
end textio_read_real;
procedure read (l: inout line; value: out real; good: out boolean)
is
-- The parsing is done with a state machine.
-- LEADING: leading blank suppression.
-- SIGN: a sign has been found.
-- DIGITS: integer parts
-- DECIMALS, DECIMALS2: digits after the dot.
-- EXPONENT_SIGN: sign after "E"
-- EXPONENT_1: first digit of the exponent.
-- EXPONENT: digits of the exponent.
type state_t is (leading, sign, digits, decimals, decimals2,
exponent_sign, exponent_1, exponent);
variable state : state_t := leading;
variable left : positive;
procedure set_value (right : positive; off : natural) is
begin
if right > left then
value := textio_read_real (l (left to right - off));
else
value := textio_read_real (l (left downto right + off));
end if;
good := True;
end set_value;
begin
-- By default, parsing has failed.
good := false;
-- Iterate over all characters of the string.
-- Return immediatly in case of parse error.
-- Trim L and call SET_VALUE and return in case of success.
for i in l'range loop
case state is
when leading =>
left := i;
case l (i) is
when ' '
| NBSP --!V87
| ht =>
null;
when '+' | '-' =>
state := sign;
when '0' to '9' =>
state := digits;
when others =>
return;
end case;
when sign =>
case l (i) is
when '0' to '9' =>
state := digits;
when others =>
return;
end case;
when digits =>
case l (i) is
when '0' to '9' =>
null;
when '.' =>
state := decimals;
when others =>
-- A "." (dot) is required in the string.
return;
end case;
when decimals | decimals2 =>
case l (i) is
when '0' to '9' =>
state := decimals2;
when 'e' | 'E' =>
-- "nnn.E" is erroneous.
if state = decimals then
return;
end if;
state := exponent_sign;
when others =>
-- "nnn.XX" is erroneous.
if state = decimals then
return;
end if;
set_value (i, 1);
trim (l, i);
return;
end case;
when exponent_sign =>
case l (i) is
when '+' | '-' =>
state := exponent_1;
when '0' to '9' =>
state := exponent;
when others =>
-- Error.
return;
end case;
when exponent_1 | exponent =>
case l (i) is
when '0' to '9' =>
state := exponent;
when others =>
set_value (i, 1);
trim (l, i);
return;
end case;
end case;
end loop;
-- End of string.
case state is
when leading | sign | digits =>
-- Erroneous.
return;
when decimals =>
-- "nnn.XX" is erroneous.
return;
when decimals2 =>
null;
when exponent_sign =>
-- Erroneous ("NNN.NNNE")
return;
when exponent_1 =>
-- "NNN.NNNE-"
return;
when exponent =>
null;
end case;
set_value (l'right, 0);
deallocate (l);
l := new string'("");
end read;
procedure read (l: inout line; value: out real)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "real read failure"
severity failure;
end read;
procedure read (l: inout line; value: out time; good: out boolean)
is
-- The result.
variable res : time;
-- UNIT is computed from the unit name, the exponent and the number of
-- digits before the dot. UNIT is the weight of the current digit.
variable unit : time;
-- Number of digits before the dot.
variable nbr_digits : integer;
-- True if a unit name has been found. Used temporaly to know the status
-- at the end of the search loop.
variable unit_found : boolean;
-- True if the number is negative.
variable is_neg : boolean;
-- Value of the exponent.
variable exp : integer;
-- True if the exponent is negative.
variable exp_neg : boolean;
-- Unit name extracted from the string.
variable unit_name : string (1 to 3);
-- state is the kind of the previous character parsed.
-- LEADING: leading blanks
-- SIGN: + or - as the first character of the number.
-- DIGITS: digit of the integer part of the number.
-- DOT: dot (.) after the integer part and before the decimal part.
-- DECIMALS: digit of the decimal part.
-- EXPONENT_MARK: e or E.
-- EXPONENT_SIGN: + or - just after the exponent mark (E).
-- EXPONENT: digit of the exponent.
-- UNIT_BLANK: blank after the exponent.
-- UNIT_1, UNIT_2, UNIT_3: first, second, third character of the unit.
type state_type is (leading, sign, digits, dot, decimals,
exponent_mark, exponent_sign, exponent,
unit_blank, unit_1, unit_2, unit_3);
variable state : state_type;
-- Used during the second scan of the string, TRUE is digits is being
-- scaned.
variable has_digits : boolean;
-- Position at the end of the string.
variable pos : integer;
-- Used to compute POS.
variable length : integer;
begin
-- Initialization.
-- Fail by default; therefore, in case of error, a return statement is
-- ok.
good := false;
nbr_digits := 0;
is_neg := false;
exp := 0;
exp_neg := false;
res := 0 sec;
-- Look for exponent and unit name.
-- Parse the string: this loop checks the correctness of the format, and
-- must return (GOOD has been set to FALSE) in case of error.
-- Set: NBR_DIGITS, IS_NEG, EXP, EXP_NEG.
state := leading;
for i in l'range loop
case l (i) is
when ' '
| NBSP --!V87
| HT =>
case state is
when leading | unit_blank =>
null;
when sign | dot | exponent_mark | exponent_sign =>
return;
when digits | decimals | exponent =>
state := unit_blank;
when unit_1 | unit_2 =>
exit;
when unit_3 =>
-- Cannot happen, since an exit is performed at unit_3.
assert false report "internal error" severity failure;
end case;
when '+' | '-' =>
case state is
when leading =>
if l(i) = '-' then
is_neg := true;
end if;
state := sign;
when exponent_mark =>
if l(i) = '-' then
exp_neg := true;
end if;
state := exponent_sign;
when others =>
return;
end case;
when '0' to '9' =>
case state is
when exponent_mark | exponent_sign | exponent =>
exp := exp * 10 + char_to_nat (l (i));
state := exponent;
when leading | sign | digits =>
-- Leading "0" are not significant.
if nbr_digits > 0 or l (i) /= '0' then
nbr_digits := nbr_digits + 1;
end if;
state := digits;
when decimals =>
null;
when dot =>
state := decimals;
when others =>
return;
end case;
when 'a' to 'z' | 'A' to 'Z' =>
case state is
when digits | decimals =>
-- "E" has exponent mark.
if l (i) = 'e' or l(i) = 'E' then
state := exponent_mark;
else
return;
end if;
when unit_blank =>
unit_name (1) := to_lower (l(i));
state := unit_1;
when unit_1 =>
unit_name (2) := to_lower (l(i));
state := unit_2;
pos := i;
when unit_2 =>
unit_name (3) := to_lower (l(i));
state := unit_3;
exit;
when others =>
return;
end case;
when '.' =>
case state is
when digits =>
state := decimals;
when others =>
exit;
end case;
when others =>
exit;
end case;
end loop;
-- A unit name (2 or 3 letters) must have been found.
-- The string may end anywhere.
if state /= unit_2 and state /= unit_3 then
return;
end if;
-- Compute EXP with the sign.
if exp_neg then
exp := -exp;
end if;
-- Search the unit name in the list of time names.
unit_found := false;
for i in time_names'range loop
-- The first two characters must match (case insensitive).
-- The third character must match if:
-- * the unit name is a three characters identifier (ie, not a blank).
-- * there is a third character in STR.
if time_names (i).name (1) = unit_name (1)
and time_names (i).name (2) = unit_name (2)
and (time_names (i).name (3) = ' '
or time_names (i).name (3) = unit_name (3))
then
unit := time_names (i).val;
unit_found := true;
-- POS is set to the position of the first invalid character.
if time_names (i).name (3) = ' ' then
length := 1;
else
length := 2;
end if;
if l'left < l'right then
pos := pos + length;
else
pos := pos - length;
end if;
exit;
end if;
end loop;
if not unit_found then
return;
end if;
-- Compute UNIT, the weight of the first non-significant character.
nbr_digits := nbr_digits + exp - 1;
if nbr_digits < 0 then
unit := unit / 10 ** (-nbr_digits);
else
unit := unit * 10 ** nbr_digits;
end if;
-- HAS_DIGITS will be set as soon as a digit is found.
-- No error is expected here (this has been checked during the first
-- pass).
has_digits := false;
for i in l'range loop
case l (i) is
when ' '
| NBSP --!V87
| HT =>
if has_digits then
exit;
end if;
when '+' | '-' =>
if not has_digits then
has_digits := true;
else
assert false report "internal error" severity failure;
return;
end if;
when '0' to '9' =>
-- Leading "0" are not significant.
if l (i) /= '0' or res /= 0 sec then
res := res + char_to_nat (l (i)) * unit;
unit := unit / 10;
end if;
has_digits := true;
when 'a' to 'z' | 'A' to 'Z' =>
if has_digits then
exit;
else
assert false report "internal error" severity failure;
return;
end if;
when '.' =>
if not has_digits then
assert false report "internal error" severity failure;
return;
end if;
when others =>
assert false report "internal error" severity failure;
return;
end case;
end loop;
-- Set VALUE.
if is_neg then
value := -res;
else
value := res;
end if;
good := true;
trim (l, pos);
return;
end read;
procedure read (l: inout line; value: out time)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "time read failure"
severity failure;
end read;
procedure read (l: inout line; value: out string; good: out boolean)
is
constant len : natural := value'length;
begin
if l'length < len then
good := false;
return;
end if;
good := true;
if len = 0 then
return;
end if;
if l'left < l'right then
-- Ascending (expected common case).
value := l (l'left to l'left + len - 1);
trim (l, l'left + len);
elsif l'left = l'right then
-- String of 1 character. We don't know the direction and therefore
-- can't use the code below which does a slice.
value := l.all;
deallocate (l);
l := new string'("");
else
-- Descending.
value := l (l'left downto l'left - len + 1);
trim (l, l'left - len);
end if;
end read;
procedure read (l: inout line; value: out string)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "string read failure"
severity failure;
end read;
--START-V08
procedure Sread (L : inout Line; Value : out String; Strlen : out Natural)
is
constant maxlen : natural := Value'Length;
alias value1 : string (1 to maxlen) is Value;
variable skipping : boolean := True;
variable f, len, nl_left : natural;
variable nl : line;
begin
-- Skip leading spaces. F designates the index of the first non-space
-- character, LEN the length of the extracted string.
len := 0;
for i in l'range loop
if skipping then
if not is_whitespace (l (i)) then
skipping := false;
f := i;
len := 1;
end if;
else
exit when is_whitespace (l (i));
len := len + 1;
exit when len = maxlen;
end if;
end loop;
-- Copy string.
if l'ascending then
value1 (1 to len) := l (f to f + len - 1);
else
value1 (1 to len) := l (f downto f - len + 1);
end if;
strlen := len;
if l'ascending then
if len = 0 then
f := l'right + 1;
end if;
nl_left := f + len;
nl := new string (nl_left to l'right);
nl.all := l (nl_left to l'right);
else
if len = 0 then
f := l'right - 1;
end if;
nl_left := f - len;
nl := new string (nl_left downto l'right);
nl.all := l (nl_left downto l'right);
end if;
deallocate (l);
l := nl;
end sread;
subtype bv4 is bit_vector (1 to 4);
function char_to_bv4 (c : character) return bv4 is
begin
case c is
when '0' => return "0000";
when '1' => return "0001";
when '2' => return "0010";
when '3' => return "0011";
when '4' => return "0100";
when '5' => return "0101";
when '6' => return "0110";
when '7' => return "0111";
when '8' => return "1000";
when '9' => return "1001";
when 'a' | 'A' => return "1010";
when 'b' | 'B' => return "1011";
when 'c' | 'C' => return "1100";
when 'd' | 'D' => return "1101";
when 'e' | 'E' => return "1110";
when 'f' | 'F' => return "1111";
when others =>
assert false report "bad hexa digit" severity failure;
end case;
end char_to_bv4;
procedure Oread (L : inout Line; Value : out Bit_Vector; Good : out Boolean)
is
-- Length of Value
constant vlen : natural := value'length;
-- Number of octal digits for Value
constant olen : natural := (vlen + 2) / 3;
variable res : bit_vector (1 to olen * 3);
-- Number of bit to parse.
variable len : natural;
variable pos : natural;
-- Last character from LEN to be removed
variable last : integer;
-- State of the previous byte:
-- SKIP: blank before the bit vector.
-- DIGIT: previous character was a digit
-- UNDERSCORE: was '_'
type state_type is (skip, digit, underscore);
variable state : state_type;
begin
-- Initialization.
if vlen = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := skip;
pos := res'left;
if l'ascending then
last := l'left - 1;
else
last := l'left + 1;
end if;
for i in l'range loop
case l (i) is
when ' '
| NBSP
| HT =>
exit when state /= skip;
when '_' =>
exit when state /= digit;
state := underscore;
when '0' to '7' =>
res (pos to pos + 2) := char_to_bv4 (l (i)) (2 to 4);
last := i;
state := digit;
pos := pos + 3;
-- LRM08 16.4
-- Character removal and compostion also stops when the expected
-- number of digits have been removed.
exit when pos = res'right + 1;
when others =>
exit;
end case;
end loop;
-- LRM08 16.4
-- The OREAD or HEAD procedure does not succeed if less than the expected
-- number of digits are removed.
if pos /= res'right + 1 then
return;
end if;
-- LRM08 16.4
-- The rightmost value'length bits of the binary number are used to form
-- the result for the VALUE parameter, [with a '0' element corresponding
-- to a 0 bit and a '1' element corresponding to a 1 bit]. The OREAD or
-- HREAD procedure does not succeed if any unused bits are 1.
for i in 1 to res'right - vlen loop
if res (i) = '1' then
return;
end if;
end loop;
Value := res (res'right - vlen + 1 to res'right);
good := true;
trim_next (l, last);
end Oread;
procedure Oread (L : inout Line; Value : out Bit_Vector)
is
variable res : boolean;
begin
Oread (l, value, res);
assert res = true
report "octal bit_vector read failure"
severity failure;
end Oread;
procedure Hread (L : inout Line; Value : out Bit_Vector; Good : out Boolean)
is
-- Length of Value
constant vlen : natural := value'length;
-- Number of hexa digits for Value
constant hlen : natural := (vlen + 3) / 4;
variable res : bit_vector (1 to hlen * 4);
-- Number of bit to parse.
variable len : natural;
variable pos : natural;
-- Last character from LEN to be removed
variable last : integer;
-- State of the previous byte:
-- SKIP: blank before the bit vector.
-- DIGIT: previous character was a digit
-- UNDERSCORE: was '_'
type state_type is (skip, digit, underscore);
variable state : state_type;
begin
-- Initialization.
if vlen = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := skip;
pos := res'left;
if l'ascending then
last := l'left - 1;
else
last := l'left + 1;
end if;
for i in l'range loop
case l (i) is
when ' '
| NBSP
| HT =>
exit when state /= skip;
when '_' =>
exit when state /= digit;
state := underscore;
when '0' to '9' | 'a' to 'f' | 'A' to 'F' =>
res (pos to pos + 3) := char_to_bv4 (l (i));
last := i;
state := digit;
pos := pos + 4;
-- LRM08 16.4
-- Character removal and compostion also stops when the expected
-- number of digits have been removed.
exit when pos = res'right + 1;
when others =>
exit;
end case;
end loop;
-- LRM08 16.4
-- The OREAD or HEAD procedure does not succeed if less than the expected
-- number of digits are removed.
if pos /= res'right + 1 then
return;
end if;
-- LRM08 16.4
-- The rightmost value'length bits of the binary number are used to form
-- the result for the VALUE parameter, [with a '0' element corresponding
-- to a 0 bit and a '1' element corresponding to a 1 bit]. The OREAD or
-- HREAD procedure does not succeed if any unused bits are 1.
for i in 1 to res'right - vlen loop
if res (i) = '1' then
return;
end if;
end loop;
Value := res (res'right - vlen + 1 to res'right);
good := true;
trim_next (l, last);
end Hread;
procedure Hread (L : inout Line; Value : out Bit_Vector)
is
variable res : boolean;
begin
Hread (l, value, res);
assert res = true
report "hexa bit_vector read failure"
severity failure;
end Hread;
--END-V08
end textio;
| gpl-2.0 | 7fe37411ccb8e62de3c4731c6e2a7080 | 0.566388 | 3.620391 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue382/tb_demo.vhd | 1 | 1,322 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_demo is
end entity;
architecture v1 of tb_demo is
signal clk,reset: std_logic;
component demo is
port (
clk,reset: in std_logic;
load: in std_logic;
load_val: in unsigned(7 downto 0);
qout: out unsigned(7 downto 0);
is5: out std_logic
);
end component;
signal load, is5: std_logic;
signal load_val,qout: unsigned(7 downto 0);
begin
UUT1: demo port map (clk, reset, load, load_val, qout, is5);
process
begin
load<='0';
for i in 0 to 3 loop
wait until clk='1';
end loop;
load<='1';
load_val<=x"42";
wait until clk='1';
end process;
process
begin
reset<='1';
clk<='0';
wait for 2 sec;
reset<='0';
while 1=1 loop
clk<='0';
wait for 0.5 sec;
clk<='1';
wait for 0.5 sec;
end loop;
end process;
end v1;
| gpl-2.0 | 0323454bae2ffdb1448ce013ae369eb6 | 0.408472 | 4.481356 | false | false | false | false |
nickg/nvc | test/regress/issue116.vhd | 5 | 581 | entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
process
begin
assert intstat(7) = '0';
intstat(6 downto 0) <= "0000001";
wait for 1 ns;
assert INT_int = '1';
intstat(6 downto 0) <= "0000000";
wait for 1 ns;
assert INT_int = '1';
wait;
end process;
end behav;
| gpl-3.0 | ad6fc6cc1f33606f7de450a80ff6c38b | 0.58864 | 3.32 | false | false | false | false |
nickg/nvc | test/regress/elab18.vhd | 1 | 993 | entity sub is
port (
a : in bit_vector(1 downto 0);
b, c : out bit_vector(1 downto 0);
d : out bit_vector(1 downto 0) := "00" );
end entity;
architecture test of sub is
begin
p1: (b(0), c(0)) <= a;
p2: (b(1), c(1)) <= a;
p3: d(1) <= '1';
end architecture;
-------------------------------------------------------------------------------
entity elab18 is
end entity;
architecture test of elab18 is
signal a1, b1, a2, b2 : bit_vector(1 downto 0);
begin
sub1_i: entity work.sub
port map (
a => a1,
b => b1,
c => open );
p4: process is
begin
a1 <= "01";
wait for 1 ns;
assert b1 = "00";
wait;
end process;
sub2_i: entity work.sub
port map (
a => a2,
b => b2 );
p5: process is
begin
a2 <= "10";
wait for 1 ns;
assert b2 = "11";
wait;
end process;
end architecture;
| gpl-3.0 | fd5b61339567675f30d448701b014303 | 0.429003 | 3.389078 | false | false | false | false |
tgingold/ghdl | testsuite/synth/iassoc01/tb_iassoc04.vhdl | 1 | 483 | entity tb_iassoc04 is
end tb_iassoc04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc04 is
signal a, b : bit_vector (3 downto 0);
signal res : bit;
begin
dut: entity work.iassoc04
port map (a, b, res);
process
begin
a <= "0001";
b <= "0000";
wait for 1 ns;
assert res = '1' severity failure;
a <= "0000";
b <= "0000";
wait for 1 ns;
assert res = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 5028d68bac69f57241a8299f670d9c02 | 0.608696 | 3.177632 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/numeric_bit_unsigned-body.vhdl | 2 | 17,135 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
package body NUMERIC_BIT_UNSIGNED is
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L mod UNSIGNED(R));
end function "mod";
--============================================================================
-- Id: A.39
function find_leftmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function "?>" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?> UNSIGNED(R);
end function "?>";
-- Id: C.51
function "?>" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?> UNSIGNED(R);
end function "?>";
-- Id: C.53
function "?>" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?> R;
end function "?>";
--============================================================================
-- Id: C.55
function "?<" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?< UNSIGNED(R);
end function "?<";
-- Id: C.57
function "?<" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?< UNSIGNED(R);
end function "?<";
-- Id: C.59
function "?<" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?< R;
end function "?<";
--============================================================================
-- Id: C.61
function "?<=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.63
function "?<=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.65
function "?<=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?<= R;
end function "?<=";
--============================================================================
-- Id: C.67
function "?>=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.69
function "?>=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.71
function "?>=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?>= R;
end function "?>=";
--============================================================================
-- Id: C.73
function "?=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?= UNSIGNED(R);
end function "?=";
-- Id: C.75
function "?=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?= UNSIGNED(R);
end function "?=";
-- Id: C.77
function "?=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?= R;
end function "?=";
--============================================================================
-- Id: C.79
function "?/=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.81
function "?/=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.83
function "?/=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?/= R;
end function "?/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (shift_left (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (shift_right (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (rotate_left (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (rotate_right (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.9
function "sll" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) sll COUNT);
end function "sll";
-- Id: S.11
function "srl" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) srl COUNT);
end function "srl";
-- Id: S.13
function "rol" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) rol COUNT);
end function "rol";
-- Id: S.15
function "ror" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) ror COUNT);
end function "ror";
-- Id: S.17
function "sla" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (
resize (arg => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL is
begin
return TO_INTEGER (UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE));
end function To_BitVector;
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR is
begin
return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE_RES'length));
end function To_BitVector;
end package body NUMERIC_BIT_UNSIGNED;
| gpl-2.0 | 5d857be94f60e8b74b61155571118a67 | 0.528509 | 4.07782 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1051/psi_common_math_pkg.vhd | 1 | 5,646 | ------------------------------------------------------------------------------
-- Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
-- Authors: Oliver Bruendler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_array_pkg.all;
------------------------------------------------------------------------------
-- Package Header
------------------------------------------------------------------------------
package psi_common_math_pkg is
function log2(arg : in natural) return natural;
function log2ceil(arg : in natural) return natural;
function log2ceil(arg : in real) return natural;
function isLog2(arg : in natural) return boolean;
function max( a : in integer;
b : in integer) return integer;
function min( a : in integer;
b : in integer) return integer;
-- choose t if s=true else f
function choose( s : in boolean;
t : in std_logic;
f : in std_logic) return std_logic;
function choose( s : in boolean;
t : in std_logic_vector;
f : in std_logic_vector) return std_logic_vector;
function choose( s : in boolean;
t : in integer;
f : in integer) return integer;
function choose( s : in boolean;
t : in string;
f : in string) return string;
function choose( s : in boolean;
t : in real;
f : in real) return real;
function choose( s : in boolean;
t : in unsigned;
f : in unsigned) return unsigned;
-- count occurence of a value inside an array
function count( a : in t_ainteger;
v : in integer) return integer;
function count( a : in t_abool;
v : in boolean) return integer;
function count( a : in std_logic_vector;
v : in std_logic) return integer;
end psi_common_math_pkg;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body psi_common_math_pkg is
-- *** Log2 integer ***
function log2(arg : in natural) return natural is
variable v : natural := arg;
variable r : natural := 0;
begin
while v > 1 loop
v := v/2;
r := r+1;
end loop;
return r;
end function;
-- *** Log2Ceil integer ***
function log2ceil(arg : in natural) return natural is
begin
if arg = 0 then
return 0;
end if;
return log2(arg*2-1);
end function;
-- *** Log2Ceil real ***
function log2ceil(arg : in real) return natural is
variable v : real := arg;
variable r : natural := 0;
begin
while v > 1.0 loop
v := v/2.0;
r := r+1;
end loop;
return r;
end function;
-- *** isLog2 ***
function isLog2(arg : in natural) return boolean is
begin
if log2(arg) = log2ceil(arg) then
return true;
else
return false;
end if;
end function;
-- *** Max ***
function max( a : in integer;
b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- *** Min ***
function min( a : in integer;
b : in integer) return integer is
begin
if a > b then
return b;
else
return a;
end if;
end function;
-- *** Choose (std_logic) ***
function choose( s : in boolean;
t : in std_logic;
f : in std_logic) return std_logic is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (std_logic_vector) ***
function choose( s : in boolean;
t : in std_logic_vector;
f : in std_logic_vector) return std_logic_vector is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (integer) ***
function choose( s : in boolean;
t : in integer;
f : in integer) return integer is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (string) ***
function choose( s : in boolean;
t : in string;
f : in string) return string is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (real) ***
function choose( s : in boolean;
t : in real;
f : in real) return real is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (unsigned) ***
function choose( s : in boolean;
t : in unsigned;
f : in unsigned) return unsigned is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** count (integer) ***
function count( a : in t_ainteger;
v : in integer) return integer is
variable cnt_v : integer := 0;
begin
for idx in a'low to a'high loop
if a(idx) = v then
cnt_v := cnt_v+1;
end if;
end loop;
return cnt_v;
end function;
-- *** count (bool) ***
function count( a : in t_abool;
v : in boolean) return integer is
variable cnt_v : integer := 0;
begin
for idx in a'low to a'high loop
if a(idx) = v then
cnt_v := cnt_v+1;
end if;
end loop;
return cnt_v;
end function;
-- *** count (std_logic) ***
function count( a : in std_logic_vector;
v : in std_logic) return integer is
variable cnt_v : integer := 0;
begin
for idx in a'low to a'high loop
if a(idx) = v then
cnt_v := cnt_v+1;
end if;
end loop;
return cnt_v;
end function;
end psi_common_math_pkg;
| gpl-2.0 | 8efc51ee2a5bb0670a79551bfa6fd1bc | 0.532944 | 3.18623 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rddata_cntl.vhd | 3 | 75,297 | -------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_rdmux;
-------------------------------------------------------------------------------
entity axi_datamover_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_rddata_cntl;
architecture implementation of axi_datamover_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast ;
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
GEN_MM2S_TKEEP_ENABLE5 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
end generate GEN_MM2S_TKEEP_ENABLE5;
GEN_MM2S_TKEEP_DISABLE5 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE5;
-- MM2S Supplimental Controls
mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
sig_next_cmd_cmplt_reg) or
(sig_halt_reg and
sig_dqual_reg_full and
not(sig_no_posted_cmds) and
not(sig_calc_error_reg));
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_datamover_v5_1_10.axi_datamover_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH
)
port map (
mmap_read_data_in => mm2s_rdata ,
mux_data_out => mm2s_strm_wdata ,
mstr2data_saddr_lsb => sig_addr_lsb_reg
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When (mm2s_rresp = DECERR and mm2s_rvalid = '1')
Else '0';
sig_slverr <= '1'
When (mm2s_rresp = SLVERR and mm2s_rvalid = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-3.0 | 4a7c1c15f78d6d19e87d93a1e0e34638 | 0.402473 | 5.080769 | false | false | false | false |
nickg/nvc | test/regress/conv5.vhd | 1 | 1,681 | package pack is
type int_vector is array (natural range <>) of natural;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( size : natural );
port ( o1 : out int_vector(1 to size);
o2 : out int_vector(1 to 3);
i1 : in integer );
end entity;
architecture test of sub is
begin
p1: process is
variable tmp : int_vector(1 to size);
begin
assert i1 = 0;
for i in 1 to size loop
tmp(i) := i;
end loop;
o1 <= tmp;
o2 <= (5, 6, 7);
wait for 1 ns;
assert i1 = 150;
o1(1) <= 10;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity conv5 is
end entity;
use work.pack.all;
architecture test of conv5 is
signal x1 : integer;
signal x2 : integer;
signal y : int_vector(1 to 5);
function sum_ints(v : in int_vector) return integer is
variable result : integer := 0;
begin
for i in v'range loop
result := result + v(i);
end loop;
return result;
end function;
begin
uut1: entity work.sub
generic map ( size => 5)
port map ( sum_ints(o1) => x1,
sum_ints(o2) => x2,
i1 => sum_ints(y) );
p2: process is
begin
assert x1 = 0;
assert x2 = 0;
y <= (10, 20, 30, 40, 50);
wait for 1 ns;
assert x1 = 15;
assert x2 = 18;
wait for 1 ns;
assert x1 = 24;
wait;
end process;
end architecture;
| gpl-3.0 | 9101bf589ff955874477df36bf9bb2e9 | 0.466389 | 3.803167 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1292/issue.vhdl | 1 | 1,616 | library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
ch <= seq(index);
data <= to_bit(ch);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (
clk : in std_logic
);
end entity issue;
architecture psl of issue is
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
signal a, b, c : std_logic;
begin
-- 012345678901234
SEQ_A : sequencer generic map ("_-______-______") port map (clk, a);
SEQ_B : sequencer generic map ("___-__-___-__-_") port map (clk, b);
SEQ_C : sequencer generic map ("______-___-____") port map (clk, c);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion holds
NEXT_EVENT_a : assert always (a -> next_event_e(b)[1 to 2](c));
end architecture psl;
| gpl-2.0 | 47ead0b929282e5fd32c0ba00b036c25 | 0.564356 | 3.475269 | false | false | false | false |
nickg/nvc | test/regress/wave6.vhd | 1 | 617 | entity wave6 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of wave6 is
type pair is record
a, b : integer;
end record;
type rec is record
x : integer;
y : std_logic_vector;
z : pair;
end record;
subtype rec_c is rec(y(1 to 3));
signal r : rec_c;
begin
main: process is
begin
wait for 1 ns;
r.y <= "101";
wait for 1 ns;
r.z.b <= 5;
r.z.a <= 6;
wait for 1 ns;
r.x <= 2;
r.z.a <= 1;
r.y <= "010";
wait;
end process;
end architecture;
| gpl-3.0 | 319f58b4164fa7e0e0184d14fa3a5940 | 0.494327 | 3.247368 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd | 4 | 1,524 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_comparator is
end tb_comparator;
architecture TB_comparator of tb_comparator is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
signal cmp_out : std_logic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
C1 : entity work.comparator(ideal)
port map(
a => in_src,
d => cmp_out
);
end TB_comparator;
| gpl-2.0 | a88f46c0e262628b0a0e94a3f0525a43 | 0.669291 | 4.175342 | false | false | false | false |
nickg/nvc | test/regress/genpack7.vhd | 1 | 1,567 | package poly is
generic (a, b, def : integer);
function apply (x : integer := def) return integer;
end package;
package body poly is
function apply (x : integer := def) return integer is
begin
return x * a + b;
end function;
end package body;
-------------------------------------------------------------------------------
package wrapper is
generic ( package p is new work.poly generic map ( <> ) );
function wrapped_apply (n : integer) return integer;
end package;
package body wrapper is
use p.all;
function wrapped_apply (n : integer) return integer is
begin
return apply;
end function;
end package body;
-------------------------------------------------------------------------------
package my_poly1 is new work.poly generic map (a => 2, b => 3, def => 10);
package my_wrap1 is new work.wrapper generic map (p => work.my_poly1);
package my_poly2 is new work.poly generic map (a => 5, b => 1, def => 1);
package my_wrap2 is new work.wrapper generic map (p => work.my_poly2);
-------------------------------------------------------------------------------
entity genpack7 is
end entity;
use work.my_wrap1;
use work.my_wrap2;
architecture test of genpack7 is
begin
main: process is
variable v : integer := 5;
begin
assert my_wrap1.wrapped_apply(2) = 23;
wait for 1 ns;
assert my_wrap1.wrapped_apply(v) = 23;
assert my_wrap2.wrapped_apply(2) = 6;
assert my_wrap2.wrapped_apply(v) = 6;
wait;
end process;
end architecture;
| gpl-3.0 | d928ee9538871256890d20cf1a7296d8 | 0.545629 | 3.987277 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/idctbuff.vhd | 2 | 1,833 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity idctbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(8 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(8 downto 0);
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end idctbuff;
architecture augh of idctbuff is
-- Embedded RAM
type ram_type is array (0 to 383) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra1_data <= ram( to_integer(ra1_addr) ) when to_integer(ra1_addr) < 384 else (others => '-');
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 384 else (others => '-');
ra2_data <= ram( to_integer(ra2_addr) ) when to_integer(ra2_addr) < 384 else (others => '-');
end architecture;
| gpl-2.0 | a58c45ac01be60758811679c0550826e | 0.666667 | 2.846273 | false | false | false | false |
nickg/nvc | test/regress/vests37.vhd | 1 | 4,849 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1781.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c09s06b00x00p04n05i01781pkg is
type info is record
field_1 : integer;
field_2 : real;
end record;
type stuff is array (Integer range 1 to 2) of info;
end c09s06b00x00p04n05i01781pkg;
use work.c09s06b00x00p04n05i01781pkg.all;
entity c09s06b00x00p04n05i01781ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end c09s06b00x00p04n05i01781ent_a;
use work.c09s06b00x00p04n05i01781pkg.all;
architecture c09s06b00x00p04n05i01781arch_a of c09s06b00x00p04n05i01781ent_a is
-- Check that the data was passed...
begin
TESTING: PROCESS
BEGIN
assert NOT( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***PASSED TEST: c09s06b00x00p04n05i01781"
severity NOTE;
assert ( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***FAILED TEST: c09s06b00x00p04n05i01781 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
end c09s06b00x00p04n05i01781arch_a;
-------------------------------------------------------------------------
ENTITY vests37 IS
END vests37;
use work.c09s06b00x00p04n05i01781pkg.all;
ARCHITECTURE c09s06b00x00p04n05i01781arch OF vests37 IS
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01781ent_a(c09s06b00x00p04n05i01781arch_a);
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100",
gB(2) => ( 890, 135.7 ),
gB(1) => ( 123, 456.7 )
);
END c09s06b00x00p04n05i01781arch;
| gpl-3.0 | e8fa1a023ba5821d5add602a19245abd | 0.505465 | 3.800157 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug090/crash9.vhdl | 1 | 1,732 | library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
t_n : in std_logic;
d : c_vector (len - 1 downto 0);
q : out stdector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process p;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : std_logic;
signal rst_n : std_logic;
signal din, dout, dout2 : std_logic_vector (7 downto 0);
component dff is
generic (len : natural := 8);
port (clk : in std_logic;
st_n : in std_logic;
d : std_logic_vector (len - 1 downto 0);
q : out std_logic_vector (len - 1 downto 0));
end component;
begin
mydff : entity work.dff
generic m!p (} => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout);
dff2 : dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
rst_n <= '0' after 0 ns, '1' after 4 ns;
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
chkr: process (clk)
begin
if rst_n = '0' then
null;
elsif rising_edge (clk) then
assert dout = dout2 report "incoherence" severity failure;
end if;
end process chkr;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report "start of tb" severity note;
for i in din'range loop
din(i) <= '0';
end loop;
wait until clk = '0';
end process;
assert false report "Hello world" severity note;
end behav;
| gpl-2.0 | 2fde681a33df8bc5cc92675eb1544ea4 | 0.571594 | 3.183824 | false | false | false | false |
nickg/nvc | test/sem/gentype.vhd | 1 | 2,523 | entity sub is
generic (
type t; -- OK
INIT : t ); -- OK
end entity;
architecture test of sub is
constant myconst : t := INIT; -- OK
signal mysig : t; -- OK
subtype mysub is t range 1 to 2; -- Error
begin
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
component comp1 is
generic (
type t; -- OK
INIT : t ); -- OK
end component;
component comp2 is
end component;
component comp3 is
generic (
type t; -- OK
function func1 (x : t) return t; -- OK
procedure proc1 (x : t) is <> ); -- OK
end component;
component comp4 is
generic (
type t; -- OK
function func1 (x : t) return t is my_func; -- OK
procedure proc1 (x : t) is <> ); -- OK
end component;
for u3: comp2 use entity work.sub
generic map ( t => real, init => 5.1 ); -- OK
procedure proc1 ( a : integer );
procedure proc1 ( b : real );
function my_func (a : integer) return integer;
function my_func (a : real) return real;
function some_other_func (a, b : integer) return integer;
begin
u1: entity work.sub
generic map ( t => integer, init => 5 ); -- OK
u2: component comp1
generic map ( t => integer, init => 5 ); -- OK
u3: component comp2; -- OK
u4: entity work.sub
generic map ( t => integer, init => 1.2 ); -- Error
u5: entity work.sub
generic map ( real, "=", "/=", 5.2 ); -- OK (but weird?)
u6: entity work.sub
generic map ( t => 5, init => 2 ); -- Error
u7: component comp3
generic map ( t => integer, func1 => my_func, proc1 => proc1 ); -- OK
u8: component comp3
generic map ( t => integer, func1 => my_func ); -- OK
u9: component comp3
generic map ( func1 => my_func ); -- Error
u10: component comp3
generic map ( t => bit, func1 => my_func ); -- Error
u11: component comp3
generic map ( t => real, func1 => my_func ); -- OK
u12: component comp1
generic map ( t => my_func, init => 5 ); -- Error
u13: component comp1
generic map ( t => u12, init => 5 ); -- Error
end architecture;
| gpl-3.0 | a4d52332c09aed1486b7c271538d4e1d | 0.479588 | 3.966981 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3045.vhd | 4 | 2,296 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3045.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p02n03i03045ent IS
END c12s02b02x00p02n03i03045ent;
ARCHITECTURE c12s02b02x00p02n03i03045arch OF c12s02b02x00p02n03i03045ent IS
BEGIN
bl1: block
generic (i1:integer; i2:integer; i3:integer; i4:integer);
generic map(3, -5, i4=>-4, i3=>6);
begin
assert (i1=3)
report "Generic association for first element I1 incorrect"
severity failure;
assert (i2=-5)
report "Generic association for second element I2 incorrect"
severity failure;
assert (i3=6)
report "Generic association for third element I3 incorrect"
severity failure;
assert (i4=-4)
report "Generic association for fourth element I4 incorrect"
severity failure;
assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***PASSED TEST: c12s02b02x00p02n03i03045"
severity NOTE;
assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***FAILED TEST: c12s02b02x00p02n03i03045 - Named association and positional association of generics creates constnats without the correct values."
severity ERROR;
end block;
END c12s02b02x00p02n03i03045arch;
| gpl-2.0 | 98ae439ec3e59345f1e461518ba0d381 | 0.676394 | 3.638669 | false | true | false | false |
tgingold/ghdl | testsuite/synth/oper02/tb_max01.vhdl | 1 | 398 | entity tb_max01 is
end tb_max01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_max01 is
signal l, r : natural;
signal res : natural;
begin
max01_1: entity work.max01
port map (
a => l,
b => r,
o => res);
process
begin
l <= 12;
r <= 15;
wait for 1 ns;
assert res = 15 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 8015b6a0c1b5eb5a90bc6952e261f2c9 | 0.58794 | 3.085271 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id_inst.vhd | 1 | 660 | component ghrd_10as066n2_sys_id is
port (
clock : in std_logic := 'X'; -- clk
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X'; -- address
reset_n : in std_logic := 'X' -- reset_n
);
end component ghrd_10as066n2_sys_id;
u0 : component ghrd_10as066n2_sys_id
port map (
clock => CONNECTED_TO_clock, -- clk.clk
readdata => CONNECTED_TO_readdata, -- control_slave.readdata
address => CONNECTED_TO_address, -- .address
reset_n => CONNECTED_TO_reset_n -- reset.reset_n
);
| mit | 39748a5dd928918a12605fae43e3a531 | 0.527273 | 3.173077 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | RCA/8bits/RCA/Reg8Bit.vhd | 5 | 534 | library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg8Bit is
port(
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end Reg8Bit;
architecture strc_Reg8Bit of Reg8Bit is
signal Temp: std_logic_vector(7 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "00000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg8Bit; | mit | 189efa23812d07bdebb1253ae6116250 | 0.677903 | 2.738462 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc740.vhd | 4 | 7,665 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc740.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n02i00740pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
end c01s01b01x01p04n02i00740pkg;
use work.c01s01b01x01p04n02i00740pkg.all;
ENTITY c01s01b01x01p04n02i00740ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen10 : string := "shishir";
Cgen11 : bit_vector := B"0011";
Cgen12 : boolean_vector := (true,false);
Cgen13 : severity_level_vector := (note,error);
Cgne14 : integer_vector := (1,2,3,4);
Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Cgen17 : natural_vector := (1,2,3,4);
Cgen18 : positive_vector := (1,2,3,4));
END c01s01b01x01p04n02i00740ent;
ARCHITECTURE c01s01b01x01p04n02i00740arch OF c01s01b01x01p04n02i00740ent IS
BEGIN
TESTING: PROCESS
variable Vgen1 : boolean := true;
variable Vgen2 : bit := '1';
variable Vgen3 : character := 's';
variable Vgen4 : severity_level := note;
variable Vgen5 : integer := 3;
variable Vgen6 : real := 3.0;
variable Vgen7 : time := 3 ns;
variable Vgen8 : natural := 1;
variable Vgen9 : positive := 1;
variable Vgen10 : string (one to seven):= "shishir";
variable Vgen11 : bit_vector(zero to three) := B"0011";
variable Vgen12 : boolean_vector(zero to one) := (true,false);
variable Vgen13 : severity_level_vector(zero to one) := (note,error);
variable Vgen14 : integer_vector(zero to three) := (1,2,3,4);
variable Vgen15 : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
variable Vgen16 : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
variable Vgen17 : natural_vector(zero to three) := (1,2,3,4);
variable Vgen18 : positive_vector(zero to three) := (1,2,3,4);
BEGIN
assert Vgen1 = C1 report "Initializing variable with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing variable with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing variable with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing variable with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing variable with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing variable with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing variable with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing variable with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing variable with generic Vgen9 does not work" severity error;
assert Vgen10 = C10 report "Initializing variable with generic Vgen10 does not work" severity error;
assert Vgen11 = C11 report "Initializing variable with generic Vgen11 does not work" severity error;
assert Vgen12 = C12 report "Initializing variable with generic Vgen12 does not work" severity error;
assert Vgen13 = C13 report "Initializing variable with generic Vgen13 does not work" severity error;
assert Vgen14 = C14 report "Initializing variable with generic Vgen14 does not work" severity error;
assert Vgen15 = C15 report "Initializing variable with generic Vgen15 does not work" severity error;
assert Vgen16 = C16 report "Initializing variable with generic Vgen16 does not work" severity error;
assert Vgen17 = C17 report "Initializing variable with generic Vgen17 does not work" severity error;
assert Vgen18 = C18 report "Initializing variable with generic Vgen18 does not work" severity error;
assert NOT(
Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***PASSED TEST: c01s01b01x01p04n02i00740"
severity NOTE;
assert (
Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***FAILED TEST: c01s01b01x01p04n02i00740 - Initializing variable with generic does not work."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p04n02i00740arch;
| gpl-2.0 | bdf8dbb2bd72155266ac089f83ec93b3 | 0.646967 | 3.568436 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue332/ilos_sim_pkg.vhd | 1 | 1,649 |
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ilos_sim_pkg is
procedure clk_gen(
signal clk : out std_logic;
constant FREQ : real; PHASE : time := 0 fs;
signal run : std_logic
);
end package ilos_sim_pkg;
package body ilos_sim_pkg is
-- Advanced procedure for clock generation, with period adjust to match frequency over time, and run control by signal
procedure clk_gen(signal clk : out std_logic; constant FREQ : real; PHASE : time := 0 fs; signal run : std_logic) is
constant HIGH_TIME : time := 0.5 sec / FREQ; -- High time as fixed value
variable low_time_v : time; -- Low time calculated per cycle; always >= HIGH_TIME
variable cycles_v : real := 0.0; -- Number of cycles
variable freq_time_v : time := 0 fs; -- Time used for generation of cycles
begin
-- Check the arguments
assert (HIGH_TIME /= 0 fs) report "clk_gen: High time is zero; time resolution to large for frequency" severity FAILURE;
-- Initial phase shift
clk <= '0';
wait for PHASE;
-- Generate cycles
loop
-- Only high pulse if run is '1' or 'H'
if (run = '1') or (run = 'H') then
clk <= run;
end if;
wait for HIGH_TIME;
-- Low part of cycle
clk <= '0';
low_time_v := 1 sec * ((cycles_v + 1.0) / FREQ) - freq_time_v - HIGH_TIME; -- + 1.0 for cycle after current
wait for low_time_v;
-- Cycle counter and time passed update
cycles_v := cycles_v + 1.0;
freq_time_v := freq_time_v + HIGH_TIME + low_time_v;
end loop;
end procedure;
end package body ilos_sim_pkg; | gpl-2.0 | 6eba48f8f1a8f2cf7fb580812b008a56 | 0.618557 | 3.407025 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue476/test_op.vhd | 1 | 3,366 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_op is
generic (
NBITS_IN : natural := 1;
NBR_OF_CHROMA_IN : natural := 1;
NBR_OF_ROW_IN : natural := 1;
NBR_OF_COL_IN : natural := 1;
NBITS_OUT : natural := 2;
NBR_OF_CHROMA_OUT : natural := 1;
NBR_OF_ROW_OUT : natural := 1;
NBR_OF_COL_OUT : natural := 1;
NBR_OF_MATRIX_IN : natural := 1;
NBR_OF_MATRIX_OUT : natural := 1);
port (
signal clock, rst : in std_logic;
signal in_data : in std_logic_vector(NBR_OF_MATRIX_IN*NBR_OF_COL_IN*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN*NBITS_IN-1 downto 0);
signal out_data : out std_logic_vector(NBR_OF_MATRIX_OUT*NBR_OF_COL_OUT*NBR_OF_ROW_OUT*NBR_OF_CHROMA_OUT*NBITS_OUT-1 downto 0));
end entity test_op;
architecture rtl of test_op is
package local_pixel_pkg is new work.pixel_pkg
generic map (
NBITS_IN => NBITS_IN,
NBR_OF_CHROMA_IN => NBR_OF_CHROMA_IN,
NBITS_OUT => NBITS_OUT,
NBR_OF_CHROMA_OUT => NBR_OF_CHROMA_OUT
);
package local_pixel_column_pkg is new work.pixel_column_pkg
generic map (
NBITS_IN => NBITS_IN,
NBR_OF_CHROMA_IN => NBR_OF_CHROMA_IN,
NBR_OF_ROW_IN => NBR_OF_ROW_IN,
NBITS_OUT => NBITS_OUT,
NBR_OF_CHROMA_OUT => NBR_OF_CHROMA_OUT,
NBR_OF_ROW_OUT => NBR_OF_ROW_OUT,
local_pixel_pkg => local_pixel_pkg
);
package local_pixel_matrix_pkg is new work.pixel_matrix_pkg
generic map (
NBITS_IN => NBITS_IN,
NBR_OF_CHROMA_IN => NBR_OF_CHROMA_IN,
NBR_OF_ROW_IN => NBR_OF_ROW_IN,
NBR_OF_COL_IN => NBR_OF_COL_IN,
NBITS_OUT => NBITS_OUT,
NBR_OF_CHROMA_OUT => NBR_OF_CHROMA_OUT,
NBR_OF_ROW_OUT => NBR_OF_ROW_OUT,
NBR_OF_COL_OUT => NBR_OF_COL_OUT,
local_pixel_column_pkg => local_pixel_column_pkg
);
use local_pixel_matrix_pkg.all;
signal input_pixel_matrix : TYPE_PIXEL_MATRIX_IN;
signal output_pixel_matrix : TYPE_PIXEL_MATRIX_OUT;
begin
-- As soon as a function from the local_pixel_matrix_pkg is used it breaks
input_pixel_matrix <= std_logic_vector_to_pixel_matrix_in(in_data(NBR_OF_COL_IN*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN*NBITS_IN-1 downto 0));
-- Note: Commented out more complex operation to show that the error is generated regardless
-- Uncomment to have more "complete" code
--output_pixel_matrix <= not input_pixel_matrix;
out_data <= (others => '0'); --pixel_matrix_out_to_std_logic_vector(output_pixel_matrix);
--out_data <= in_data(NBR_OF_MATRIX_OUT*NBR_OF_COL_OUT*NBR_OF_ROW_OUT*NBR_OF_CHROMA_OUT*NBITS_OUT-1 downto 0);
end architecture rtl;
| gpl-2.0 | 890e03a54c0be63f6ffd22054f221658 | 0.502377 | 3.596154 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_01.vhd | 4 | 2,356 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_a_01 is
end entity fg_a_01;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_01 is
signal clk, d : std_ulogic;
begin
stimulus : process is
begin
clk <= '0'; d <= '0'; wait for 10 ns;
clk <= '1', '0' after 10 ns; wait for 20 ns;
d <= '1'; wait for 10 ns;
clk <= '1', '0' after 20 ns; d <= '0' after 10 ns;
wait;
end process stimulus;
b1 : block is
signal q : std_ulogic;
begin
-- code from book
process (clk) is
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
-- end code from book
end block b1;
b2 : block is
signal q : std_ulogic;
begin
-- code from book
process is
begin
wait until rising_edge(clk);
q <= d;
end process;
-- end code from book
end block b2;
b3 : block is
signal q : std_ulogic;
begin
-- code from book
q <= d when rising_edge(clk) else
q;
-- end code from book
end block b3;
b4 : block is
signal q : std_ulogic;
begin
-- code from book
b : block ( rising_edge(clk)
and not clk'stable ) is
begin
q <= guarded d;
end block b;
-- end code from book
end block b4;
end architecture test;
| gpl-2.0 | 1329ec884baeb4b951a95b5c2dfff06e | 0.569185 | 3.781701 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc32.vhd | 4 | 18,103 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc32.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p01n01i00032ent IS
END c04s03b01x01p01n01i00032ent;
ARCHITECTURE c04s03b01x01p01n01i00032arch OF c04s03b01x01p01n01i00032ent IS
--
-- Declaration of composite types
--
TYPE U1 IS ARRAY (CHARACTER RANGE <>) OF INTEGER; -- unconstrained array type
TYPE C1 IS ARRAY (5 TO 9) OF BIT; -- constrained array type
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE R1 IS
RECORD
month : month_name;
day : INTEGER RANGE 0 TO 31;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
-- Declaration of composite - composite types
--
TYPE US1 IS ARRAY (INTEGER RANGE <> ) OF STRING ( 1 TO 8 );
TYPE UV1 IS ARRAY (INTEGER RANGE <> ) OF BIT_VECTOR ( 3 DOWNTO 0 );
TYPE UU1 IS ARRAY (INTEGER RANGE <> ) OF U1 ('a' TO 'd');
TYPE UC1 IS ARRAY (INTEGER RANGE <> ) OF C1;
TYPE UR1 IS ARRAY (INTEGER RANGE <> ) OF R1;
TYPE CS1 IS ARRAY (INTEGER RANGE 0 TO 3) OF STRING ( 1 TO 8 );
TYPE CV1 IS ARRAY (INTEGER RANGE 0 TO 3) OF BIT_VECTOR ( 3 DOWNTO 0 );
TYPE CU1 IS ARRAY (INTEGER RANGE 0 TO 3) OF U1 ('a' TO 'd');
TYPE CC1 IS ARRAY (INTEGER RANGE 0 TO 3) OF C1;
TYPE CR1 IS ARRAY (INTEGER RANGE 0 TO 3) OF R1;
TYPE RAR IS RECORD
eS1 : STRING ( 1 TO 8 );
eV1 : BIT_VECTOR ( 3 DOWNTO 0 );
eU1 : U1 ('a' TO 'd');
eC1 : C1 ;
eR1 : R1 ;
END RECORD;
----------------------------------------------------------------------------------------
--
-- CONSTANT declarations - initial aggregate value
-- NOTE: index constraints for the unconstrained types are
-- established by the intial value.
--
CONSTANT US1_con_1 : US1 := (
(NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL),
(BS, HT, LF, VT, FF, CR, SO, SI ),
(DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB),
(CAN, EM, SUB, ESC, FSP, GSP, RSP, USP)
);
CONSTANT UV1_con_1 : UV1 := (
('0', '1', '0', '0'),
('1', '0', '1', '1'),
('1', '0', '0', '0'),
('0', '1', '0', '1')
);
CONSTANT UU1_con_1 : UU1 := (
( 1, 2, 3, 4),
( 5, 6, 7, 8),
( 9, 10, 11, 12),
( 13, 14, 15, 16)
);
CONSTANT UC1_con_1 : UC1 := (
('0', '1', '0', '0', '1'),
('0', '1', '1', '1', '0'),
('0', '0', '0', '1', '0'),
('1', '0', '0', '0', '1')
);
CONSTANT UR1_con_1 : UR1 := ( (Feb,05,1701),
(Apr,10,1802),
(Jun,15,1903),
(Aug,20,2004) );
CONSTANT CS1_con_1 : CS1 := (
(NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL),
(BS, HT, LF, VT, FF, CR, SO, SI ),
(DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB),
(CAN, EM, SUB, ESC, FSP, GSP, RSP, USP)
);
CONSTANT CV1_con_1 : CV1 := (
('0', '1', '0', '0'),
('1', '0', '1', '1'),
('1', '0', '0', '0'),
('0', '1', '0', '1')
);
CONSTANT CU1_con_1 : CU1 := (
( 1, 2, 3, 4),
( 5, 6, 7, 8),
( 9, 10, 11, 12),
( 13, 14, 15, 16)
);
CONSTANT CC1_con_1 : CC1 := (
('0', '1', '0', '0', '1'),
('0', '1', '1', '1', '0'),
('0', '0', '0', '1', '0'),
('1', '0', '0', '0', '1')
);
CONSTANT CR1_con_1 : CR1 := ( (Feb,05,1701),
(Apr,10,1802),
(Jun,15,1903),
(Aug,20,2004) );
CONSTANT RAR_con_1 : RAR := (
(SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS ),
('1', '1', '0', '0'),
( 1, 2, 3, 4),
('0', '1', '0', '0', '1'),
(Feb,29,0108) );
--
-- CONSTANT declarations - aggregate of strings initial value
--
CONSTANT US1_con_2 : US1 := ( "@ABCDEFG", "HIJKLMNO", "PQRSTUVW", "XYZ[\]^_" );
CONSTANT UV1_con_2 : UV1 := ( B"0100", B"1011", B"1000", B"0101" );
CONSTANT UC1_con_2 : UC1 := ( B"01001", B"01110", B"00010", B"10001" );
CONSTANT CS1_con_2 : CS1 := ( "@ABCDEFG", "HIJKLMNO", "PQRSTUVW", "XYZ[\]^_" );
CONSTANT CV1_con_2 : CV1 := ( B"0100", B"1011", B"1000", B"0101" );
CONSTANT CC1_con_2 : CC1 := ( B"01001", B"01110", B"00010", B"10001" );
CONSTANT RAR_con_2 : RAR := ( "@ABCDEFG", B"1100", (1,2,3,4), B"01001", (Feb,29,0108) );
-----------------------------------------------------------------------------------------
BEGIN
TESTING: PROCESS
--
-- Declarationi for generation of BIT test pattern
--
VARIABLE bval : BIT;
VARIABLE index : INTEGER;
VARIABLE ii : INTEGER;
variable k : integer := 0;
PROCEDURE pattern ( index : INOUT INTEGER; bval : OUT BIT ) IS
--
-- if starting index value is 59, the
-- test pattern is 01001011100001010001111 (repeats)
--
BEGIN
IF index > 100
THEN bval := '1';
index := index - 100;
ELSE bval := '0';
END IF;
index := index * 2;
END;
BEGIN
----------------------------------------------------------------------------------------
--
-- Verify initial values
--
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 1 TO 8 LOOP
if (US1_con_1(ii)(J) /= CHARACTER'VAL((I*8)+(J-1))) then
k := 1;
end if;
ASSERT US1_con_1(ii)(J) = CHARACTER'VAL((I*8)+(J-1))
REPORT "ERROR: Bad initial value of US1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 3 DOWNTO 0 LOOP
pattern ( index, bval );
if (UV1_con_1(ii)(J) /= bval) then
k := 1;
end if;
ASSERT UV1_con_1(ii)(J) = bval
REPORT "ERROR: Bad initial value of UV1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 0;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 'a' TO 'd' LOOP
index := index + 1;
if (UU1_con_1(ii)(J) /= index) then
k := 1;
end if;
ASSERT UU1_con_1(ii)(J) = index
REPORT "ERROR: Bad initial value of UU1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (UC1_con_1(ii)(J) /= bval) then
k := 1;
end if;
ASSERT UC1_con_1(ii)(J) = bval
REPORT "ERROR: Bad initial value of UC1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
if (UR1_con_1(ii).month /= month_name'VAL((I*2)+1)) then
k := 1;
end if;
ASSERT UR1_con_1(ii).month = month_name'VAL((I*2)+1)
REPORT "ERROR: Bad initial value of UR1_con_1(ii).month" SEVERITY FAILURE;
if (UR1_con_1(ii).day /= I*5 +5) then
k := 1;
end if;
ASSERT UR1_con_1(ii).day = I*5 + 5
REPORT "ERROR: Bad initial value of UR1_con_1(ii).day" SEVERITY FAILURE;
if (UR1_con_1(ii).year /= 1701 +(I*101)) then
k := 1;
end if;
ASSERT UR1_con_1(ii).year = 1701 + (I*101)
REPORT "ERROR: Bad initial value of UR1_con_1(ii).year" SEVERITY FAILURE;
END LOOP;
--
FOR I IN 0 TO 3 LOOP
FOR J IN 1 TO 8 LOOP
if (CS1_con_1(I)(J) /= CHARACTER'VAL((I*8)+(J-1))) then
k := 1;
end if;
ASSERT CS1_con_1(I)(J) = CHARACTER'VAL((I*8)+(J-1))
REPORT "ERROR: Bad initial value of CS1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP
FOR J IN 3 DOWNTO 0 LOOP
pattern ( index, bval );
if (CV1_con_1(I)(J) /= bval) then
k := 1;
end if;
ASSERT CV1_con_1(I)(J) = bval
REPORT "ERROR: Bad initial value of CV1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 0;
FOR I IN 0 TO 3 LOOP
FOR J IN 'a' TO 'd' LOOP
index := index + 1;
if (CU1_con_1(I)(J) /= index) then
k := 1;
end if;
ASSERT CU1_con_1(I)(J) = index
REPORT "ERROR: Bad initial value of CU1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (CC1_con_1(I)(J) /= bval) then
k := 1;
end if;
ASSERT CC1_con_1(I)(J) = bval
REPORT "ERROR: Bad initial value of CC1_con_1" SEVERITY FAILURE;
END LOOP;
END LOOP;
FOR I IN 0 TO 3 LOOP
if (CR1_con_1(I).month /= month_name'VAL((I*2)+1)) then
k := 1;
end if;
ASSERT CR1_con_1(I).month = month_name'VAL((I*2)+1)
REPORT "ERROR: Bad initial value of CR1_con_1(I).month" SEVERITY FAILURE;
if (CR1_con_1(I).day /= (I+1)*5) then
k := 1;
end if;
ASSERT CR1_con_1(I).day = (I+1)*5
REPORT "ERROR: Bad initial value of CR1_con_1(I).day" SEVERITY FAILURE;
if (CR1_con_1(I).year /= 1701 + (I*101)) then
k := 1;
end if;
ASSERT CR1_con_1(I).year = 1701 + (I*101)
REPORT "ERROR: Bad initial value of CR1_con_1(I).year" SEVERITY FAILURE;
END LOOP;
--
FOR J IN 1 TO 8 LOOP
if (RAR_con_1.eS1(J) /= CHARACTER'VAL(J)) then
k := 1;
end if;
ASSERT RAR_con_1.eS1(J) = CHARACTER'VAL(J)
REPORT "ERROR: Bad initial value of RAR_con_1.eS1" SEVERITY FAILURE;
END LOOP;
FOR J IN 3 DOWNTO 0 LOOP
if (RAR_con_1.eV1(J) /= BIT'VAL(J/2)) then
k := 1;
end if;
ASSERT RAR_con_1.eV1(J) = BIT'VAL(J/2)
REPORT "ERROR: Bad initial value of RAR_con_1.eV1" SEVERITY FAILURE;
END LOOP;
index := 0;
FOR J IN 'a' TO 'd' LOOP
index := index + 1;
if (RAR_con_1.eU1(J) /= index) then
k := 1;
end if;
ASSERT RAR_con_1.eU1(J) = index
REPORT "ERROR: Bad initial value of RAR_con_1.eU1" SEVERITY FAILURE;
END LOOP;
index := 59;
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (RAR_con_1.eC1(J) /= bval) then
k := 1;
end if;
ASSERT RAR_con_1.eC1(J) = bval
REPORT "ERROR: Bad initial value of RAR_con_1.eC1" SEVERITY FAILURE;
END LOOP;
if (RAR_con_1.eR1.month /= FEB) then
k := 1;
end if;
ASSERT RAR_con_1.eR1.month = FEB
REPORT "ERROR: Bad initial value of RAR_con_1.eR1.month" SEVERITY FAILURE;
if (RAR_con_1.eR1.day /= 29) then
k := 1;
end if;
ASSERT RAR_con_1.eR1.day = 29
REPORT "ERROR: Bad initial value of RAR_con_1.eR1.day" SEVERITY FAILURE;
if (RAR_con_1.eR1.year /= 0108) then
k := 1;
end if;
ASSERT RAR_con_1.eR1.year = 0108
REPORT "ERROR: Bad initial value of RAR_con_1.eR1.year" SEVERITY FAILURE;
-- ----------------------------------------------------------------------------------
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 1 TO 8 LOOP
if (US1_con_2(ii)(J) /= CHARACTER'VAL((I*8)+(J-1)+64)) then
k := 1;
end if;
ASSERT US1_con_2(ii)(J) = CHARACTER'VAL((I*8)+(J-1)+64)
REPORT "ERROR: Bad initial value of US1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 3 DOWNTO 0 LOOP
pattern ( index, bval );
if (UV1_con_2(ii)(J) /= bval) then
k := 1;
end if;
ASSERT UV1_con_2(ii)(J) = bval
REPORT "ERROR: Bad initial value of UV1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP ii := INTEGER'LEFT + I;
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (UC1_con_2(ii)(J) /= bval) then
k := 1;
end if;
ASSERT UC1_con_2(ii)(J) = bval
REPORT "ERROR: Bad initial value of UC1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
--
FOR I IN 0 TO 3 LOOP
FOR J IN 1 TO 8 LOOP
if (CS1_con_2(I)(J) /= CHARACTER'VAL((I*8)+(J-1)+64)) then
k := 1;
end if;
ASSERT CS1_con_2(I)(J) = CHARACTER'VAL((I*8)+(J-1)+64)
REPORT "ERROR: Bad initial value of CS1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP
FOR J IN 3 DOWNTO 0 LOOP
pattern ( index, bval );
if (CV1_con_2(I)(J) /= bval) then
k := 1;
end if;
ASSERT CV1_con_2(I)(J) = bval
REPORT "ERROR: Bad initial value of CV1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
index := 59;
FOR I IN 0 TO 3 LOOP
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (CC1_con_2(I)(J) /= bval) then
k := 1;
end if;
ASSERT CC1_con_2(I)(J) = bval
REPORT "ERROR: Bad initial value of CC1_con_2" SEVERITY FAILURE;
END LOOP;
END LOOP;
--
FOR J IN 1 TO 8 LOOP
if (RAR_con_2.eS1(J) /= CHARACTER'VAL((J-1)+64)) then
k := 1;
end if;
ASSERT RAR_con_2.eS1(J) = CHARACTER'VAL((J-1)+64)
REPORT "ERROR: Bad initial value of RAR_con_2.eS1" SEVERITY FAILURE;
END LOOP;
FOR J IN 3 DOWNTO 0 LOOP
if (RAR_con_2.eV1(J) /= BIT'VAL(J/2)) then
k := 1;
end if;
ASSERT RAR_con_2.eV1(J) = BIT'VAL(J/2)
REPORT "ERROR: Bad initial value of RAR_con_2.eV1" SEVERITY FAILURE;
END LOOP;
index := 0;
FOR J IN 'a' TO 'd' LOOP
index := index + 1;
if (RAR_con_2.eU1(J) /= index) then
k := 1;
end if;
ASSERT RAR_con_2.eU1(J) = index
REPORT "ERROR: Bad initial value of RAR_con_2.eU1" SEVERITY FAILURE;
END LOOP;
index := 59;
FOR J IN 5 TO 9 LOOP
pattern ( index, bval );
if (RAR_con_2.eC1(J) /= bval) then
k := 1;
end if;
ASSERT RAR_con_2.eC1(J) = bval
REPORT "ERROR: Bad initial value of RAR_con_2.eC1" SEVERITY FAILURE;
END LOOP;
if (RAR_con_2.eR1.month /= FEB) then
k := 1;
end if;
ASSERT RAR_con_2.eR1.month = FEB
REPORT "ERROR: Bad initial value of RAR_con_2.eR1.month" SEVERITY FAILURE;
if (RAR_con_2.eR1.day /=29) then
k := 1;
end if;
ASSERT RAR_con_2.eR1.day = 29
REPORT "ERROR: Bad initial value of RAR_con_2.eR1.day" SEVERITY FAILURE;
if (RAR_con_2.eR1.year /= 0108) then
k := 1;
end if;
ASSERT RAR_con_2.eR1.year = 0108
REPORT "ERROR: Bad initial value of RAR_con_1.eR1.year" SEVERITY
FAILURE;
---------------------------------------------------------------------------------------------
assert NOT( k = 0 )
report "***PASSED TEST: c04s03b01x01p01n01i00032"
severity NOTE;
assert ( k = 0 )
report "***FAILED TEST:c04s03b01x01p01n01i00032 - A constant declares a constant of the specified type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p01n01i00032arch;
| gpl-2.0 | fa4661506fbab51705b391adb7b8e4ad | 0.454234 | 3.459392 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1197/generics_1.vhdl | 1 | 1,064 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity addern is
generic(
width : integer := 8
);
port(
A, B : in std_logic_vector(width - 1 downto 0);
Y : out std_logic_vector(width - 1 downto 0)
);
end addern;
architecture bhv of addern is
begin
Y <= A + B;
end bhv;
Library IEEE;
use IEEE.std_logic_1164.all;
entity generics_1 is
port(
X, Y, Z : in std_logic_vector(12 downto 0);
A, B : in std_logic_vector(4 downto 0);
S : out std_logic_vector(17 downto 0));
end generics_1;
architecture bhv of generics_1 is
component addern
generic(width : integer := 8);
port(
A, B : in std_logic_vector(width - 1 downto 0);
Y : out std_logic_vector(width - 1 downto 0));
end component;
for all : addern use entity work.addern(bhv);
signal C1 : std_logic_vector(12 downto 0);
signal C2, C3 : std_logic_vector(17 downto 0);
begin
U1 : addern generic map(width => 13) port map(X, Y, C1);
C2 <= C1 & A;
C3 <= Z & B;
U2 : addern generic map(width => 18) port map(C2, C3, S);
end bhv;
| gpl-2.0 | 0379d49cb093efa78fa402e2c8ffd750 | 0.644737 | 2.84492 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug088/assemble.vhdl | 1 | 985 | library ieee;
use ieee.std_logic_1164.all;
entity assemble is
port (
A: in std_logic_vector(31 downto 0);
B: in std_logic_vector(31 downto 0);
C: in std_logic_vector(31 downto 0);
F: out std_logic_vector(31 downto 0)
);
end entity;
architecture foo of assemble is
type std_logic_2d is array
(integer range <>, integer range <>) of std_logic;
signal data: std_logic_2d (31 downto 0, 2 downto 0);
function to_std_logic_2d (i0,i1,i2: std_logic_vector (31 downto 0))
return std_logic_2d is
variable retdat: std_logic_2d (data'range(0), data'range(1));
begin
for i in i0'range loop
retdat(i, 0) := i0(i);
retdat(i, 1) := i1(i);
retdat(i, 2) := i2(i);
end loop;
return retdat;
end function;
begin
data <= to_std_logic_2d(A, B, C);
F <= (others => data (15, 1)); -- B(15)
end architecture;
| gpl-2.0 | 01dc43d24ef66324af8b9ba99b793b00 | 0.546193 | 3.177419 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/w_split7.vhd | 2 | 1,359 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split7 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split7;
architecture augh of w_split7 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | b0b2b1a41c3d6dfeea10872d272ba7f6 | 0.66961 | 2.843096 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/top.vhd | 2 | 171,765 | library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
cp_ok : out std_logic;
cp_en : in std_logic;
cp_rest : in std_logic;
cp_din : in std_logic_vector(63 downto 0);
cp_dout : out std_logic_vector(63 downto 0);
stdout_data : out std_logic_vector(7 downto 0);
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_data : in std_logic_vector(31 downto 0);
stdin_rdy : out std_logic;
stdin_ack : in std_logic
);
end top;
architecture augh of top is
-- Declaration of components
component output_split2 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split3 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component sub_159 is
port (
gt : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end component;
component add_165 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component output_split1 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split0 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component add_172 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_176 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_181 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_187 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_189 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(13 downto 0)
);
end component;
component add_191 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(30 downto 0)
);
end component;
component mul_192 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(10 downto 0)
);
end component;
component mul_193 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_198 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_199 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(13 downto 0)
);
end component;
component sub_209 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_212 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_213 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_214 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_215 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_216 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_217 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_218 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_219 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_220 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_223 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_227 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_157 is
port (
ge : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end component;
component add_163 is
port (
result : out std_logic_vector(15 downto 0);
in_a : in std_logic_vector(15 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component cmp_164 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end component;
component add_170 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_174 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_180 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component sub_186 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_190 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_196 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(10 downto 0)
);
end component;
component sub_200 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_206 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_210 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_171 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_177 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_179 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component mul_195 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_197 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_207 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_230 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_185 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_211 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_226 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_235 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_314 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component sub_160 is
port (
le : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end component;
component add_173 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_182 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_188 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_243 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_262 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component output_split4 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split5 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split6 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component output_split7 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end component;
component input_split0 is
port (
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(4 downto 0);
ra3_data : out std_logic_vector(31 downto 0);
ra3_addr : in std_logic_vector(4 downto 0);
clk : in std_logic;
wa2_data : in std_logic_vector(31 downto 0);
wa2_addr : in std_logic_vector(4 downto 0);
wa2_en : in std_logic
);
end component;
component add_194 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(29 downto 0)
);
end component;
component add_205 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_254 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_276 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component sub_284 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component input_split1 is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
wa0_en : in std_logic;
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(4 downto 0);
ra3_data : out std_logic_vector(31 downto 0);
ra3_addr : in std_logic_vector(4 downto 0);
clk : in std_logic
);
end component;
component add_166 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_168 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_178 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_183 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_332 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_341 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_357 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_365 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_368 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_369 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_370 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_377 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component cmp_398 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_400 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_404 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_406 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_408 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_410 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_412 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component sub_429 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_466 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_496 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_521 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_528 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component fsm_23 is
port (
clock : in std_logic;
reset : in std_logic;
in0 : in std_logic;
out181 : out std_logic;
out182 : out std_logic;
out183 : out std_logic;
out184 : out std_logic;
out185 : out std_logic;
out8 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out16 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
in2 : in std_logic;
out23 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out31 : out std_logic;
out33 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out38 : out std_logic;
out40 : out std_logic;
out42 : out std_logic;
in3 : in std_logic;
out44 : out std_logic;
out46 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out52 : out std_logic;
out54 : out std_logic;
out56 : out std_logic;
out57 : out std_logic;
out58 : out std_logic;
in4 : in std_logic;
out60 : out std_logic;
in5 : in std_logic;
out164 : out std_logic;
out165 : out std_logic;
out167 : out std_logic;
out168 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out174 : out std_logic;
out176 : out std_logic;
out178 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
in1 : in std_logic;
out4 : out std_logic;
out90 : out std_logic;
out91 : out std_logic;
out97 : out std_logic;
out99 : out std_logic;
out101 : out std_logic;
in6 : in std_logic;
out103 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out135 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
out138 : out std_logic;
in11 : in std_logic;
out140 : out std_logic;
out141 : out std_logic;
out142 : out std_logic;
out143 : out std_logic;
out145 : out std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out153 : out std_logic;
out154 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out157 : out std_logic;
out158 : out std_logic;
out159 : out std_logic;
out160 : out std_logic;
out161 : out std_logic;
out162 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out120 : out std_logic;
out121 : out std_logic;
out122 : out std_logic;
out123 : out std_logic;
out124 : out std_logic;
out125 : out std_logic;
out126 : out std_logic;
in7 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
in8 : in std_logic;
out131 : out std_logic;
in9 : in std_logic;
out132 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
in10 : in std_logic;
out186 : out std_logic;
out187 : out std_logic;
out190 : out std_logic;
out195 : out std_logic;
out197 : out std_logic;
out198 : out std_logic;
out199 : out std_logic;
out200 : out std_logic;
out201 : out std_logic;
out203 : out std_logic;
out204 : out std_logic;
out206 : out std_logic;
out207 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out215 : out std_logic;
out217 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out222 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out231 : out std_logic;
out232 : out std_logic;
out234 : out std_logic;
out235 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out243 : out std_logic;
out245 : out std_logic;
out248 : out std_logic;
out249 : out std_logic;
out250 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out254 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out257 : out std_logic;
out259 : out std_logic;
out260 : out std_logic;
out262 : out std_logic;
out263 : out std_logic;
out265 : out std_logic;
out266 : out std_logic;
out268 : out std_logic;
out269 : out std_logic;
out271 : out std_logic;
out273 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out278 : out std_logic;
out279 : out std_logic;
out280 : out std_logic;
out281 : out std_logic;
out282 : out std_logic;
out283 : out std_logic;
out284 : out std_logic;
out285 : out std_logic;
out286 : out std_logic;
out287 : out std_logic;
out288 : out std_logic;
out289 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out292 : out std_logic;
out293 : out std_logic;
out294 : out std_logic;
out295 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out298 : out std_logic;
out311 : out std_logic;
out312 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
out315 : out std_logic;
out316 : out std_logic;
out318 : out std_logic;
out321 : out std_logic;
out322 : out std_logic;
out323 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out327 : out std_logic;
out328 : out std_logic;
out329 : out std_logic;
out333 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out343 : out std_logic;
out344 : out std_logic;
out345 : out std_logic;
out346 : out std_logic;
out349 : out std_logic;
out350 : out std_logic;
out351 : out std_logic;
out352 : out std_logic;
out353 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out357 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out366 : out std_logic;
out367 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out382 : out std_logic;
out383 : out std_logic;
out385 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out398 : out std_logic;
out400 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out404 : out std_logic;
out406 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out411 : out std_logic;
out412 : out std_logic;
out413 : out std_logic;
out414 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out422 : out std_logic;
out423 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
out428 : out std_logic;
out429 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out435 : out std_logic;
out436 : out std_logic;
out437 : out std_logic;
out438 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out455 : out std_logic;
out457 : out std_logic;
out458 : out std_logic;
out459 : out std_logic;
out460 : out std_logic;
out461 : out std_logic;
out462 : out std_logic;
out463 : out std_logic;
out464 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out469 : out std_logic;
out472 : out std_logic;
out475 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out483 : out std_logic;
out484 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
out491 : out std_logic;
out495 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out499 : out std_logic;
out500 : out std_logic;
out501 : out std_logic;
out512 : out std_logic;
out513 : out std_logic;
out517 : out std_logic;
out518 : out std_logic;
out519 : out std_logic;
out521 : out std_logic;
out522 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out531 : out std_logic;
out540 : out std_logic;
out542 : out std_logic;
out544 : out std_logic;
out545 : out std_logic;
out554 : out std_logic;
out555 : out std_logic;
out559 : out std_logic;
out560 : out std_logic;
out561 : out std_logic;
out562 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out567 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
out578 : out std_logic;
out580 : out std_logic;
out581 : out std_logic
);
end component;
component add_167 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_169 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_175 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_255 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component sub_362 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_376 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_420 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component sub_446 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_456 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_457 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_461 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_517 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_560 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_565 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_578 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component muxb_162 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component add_184 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component muxb_201 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component cmp_202 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end component;
component cmp_203 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component cmp_204 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component sub_208 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_236 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component muxb_263 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component muxb_265 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component add_277 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component add_295 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_296 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component sub_303 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_315 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component muxb_322 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end component;
component add_323 is
port (
result : out std_logic_vector(15 downto 0);
in_a : in std_logic_vector(15 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component cmp_324 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end component;
component cmp_325 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component mul_328 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_331 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_337 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_338 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_344 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_345 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_350 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_353 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_354 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_373 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component add_382 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_383 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_390 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_391 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component cmp_392 is
port (
ne : out std_logic;
in0 : in std_logic_vector(31 downto 0);
in1 : in std_logic_vector(31 downto 0)
);
end component;
component add_393 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component cmp_396 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_402 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_411 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end component;
component cmp_413 is
port (
ne : out std_logic;
in0 : in std_logic_vector(31 downto 0);
in1 : in std_logic_vector(31 downto 0)
);
end component;
component mul_416 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_419 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_430 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_437 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_442 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_445 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_447 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_448 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_449 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_460 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_469 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_474 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_477 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_478 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_483 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_484 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_487 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_488 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_489 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_492 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_495 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_499 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_502 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_503 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_508 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_511 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_516 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_520 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_524 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_527 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_531 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_534 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_537 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_540 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_543 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_544 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_547 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component add_552 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_553 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_556 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_559 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_561 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_562 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_563 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_564 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_566 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_567 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_570 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_573 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_574 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_577 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_579 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_580 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_585 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_586 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_589 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component mul_592 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component sub_593 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component mul_594 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
component mul_595 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end component;
component sub_596 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component sub_599 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_600 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end component;
component add_601 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end component;
component add_602 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end component;
component mul_605 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end component;
-- Declaration of signals
signal sig_clock : std_logic;
signal sig_reset : std_logic;
signal augh_test_9 : std_logic;
signal augh_test_11 : std_logic;
signal sig_start : std_logic;
signal test_cp_0_16 : std_logic;
signal test_cp_1_17 : std_logic;
signal memextrct_loop_sig_21 : std_logic;
signal psc_loop_sig_20 : std_logic;
signal memextrct_loop_sig_22 : std_logic;
signal sig_606 : std_logic_vector(30 downto 0);
signal sig_607 : std_logic_vector(19 downto 0);
signal sig_608 : std_logic_vector(26 downto 0);
signal sig_609 : std_logic_vector(31 downto 0);
signal sig_610 : std_logic_vector(31 downto 0);
signal sig_611 : std_logic_vector(31 downto 0);
signal sig_612 : std_logic_vector(31 downto 0);
signal sig_613 : std_logic_vector(31 downto 0);
signal sig_614 : std_logic_vector(31 downto 0);
signal sig_615 : std_logic_vector(31 downto 0);
signal sig_616 : std_logic_vector(31 downto 0);
signal sig_617 : std_logic_vector(31 downto 0);
signal sig_618 : std_logic_vector(31 downto 0);
signal sig_619 : std_logic_vector(31 downto 0);
signal sig_620 : std_logic_vector(31 downto 0);
signal sig_621 : std_logic_vector(30 downto 0);
signal sig_622 : std_logic_vector(31 downto 0);
signal sig_623 : std_logic_vector(30 downto 0);
signal sig_624 : std_logic_vector(31 downto 0);
signal sig_625 : std_logic_vector(31 downto 0);
signal sig_626 : std_logic_vector(31 downto 0);
signal sig_627 : std_logic_vector(31 downto 0);
signal sig_628 : std_logic_vector(31 downto 0);
signal sig_629 : std_logic_vector(31 downto 0);
signal sig_630 : std_logic_vector(31 downto 0);
signal sig_631 : std_logic_vector(30 downto 0);
signal sig_632 : std_logic_vector(30 downto 0);
signal sig_633 : std_logic_vector(31 downto 0);
signal sig_634 : std_logic_vector(31 downto 0);
signal sig_635 : std_logic_vector(30 downto 0);
signal sig_636 : std_logic_vector(31 downto 0);
signal sig_637 : std_logic_vector(31 downto 0);
signal sig_638 : std_logic_vector(31 downto 0);
signal sig_639 : std_logic_vector(31 downto 0);
signal sig_640 : std_logic_vector(30 downto 0);
signal sig_641 : std_logic_vector(30 downto 0);
signal sig_642 : std_logic_vector(31 downto 0);
signal sig_643 : std_logic_vector(31 downto 0);
signal sig_644 : std_logic_vector(30 downto 0);
signal sig_645 : std_logic_vector(31 downto 0);
signal sig_646 : std_logic_vector(30 downto 0);
signal sig_647 : std_logic_vector(31 downto 0);
signal sig_648 : std_logic_vector(31 downto 0);
signal sig_649 : std_logic_vector(31 downto 0);
signal sig_650 : std_logic_vector(31 downto 0);
signal sig_651 : std_logic_vector(31 downto 0);
signal sig_652 : std_logic_vector(31 downto 0);
signal sig_653 : std_logic_vector(31 downto 0);
signal sig_654 : std_logic_vector(31 downto 0);
signal sig_655 : std_logic_vector(31 downto 0);
signal sig_656 : std_logic_vector(31 downto 0);
signal sig_657 : std_logic_vector(31 downto 0);
signal sig_658 : std_logic_vector(31 downto 0);
signal sig_659 : std_logic_vector(30 downto 0);
signal sig_660 : std_logic_vector(31 downto 0);
signal sig_661 : std_logic_vector(30 downto 0);
signal sig_662 : std_logic_vector(31 downto 0);
signal sig_663 : std_logic_vector(31 downto 0);
signal sig_664 : std_logic_vector(31 downto 0);
signal sig_665 : std_logic_vector(31 downto 0);
signal sig_666 : std_logic_vector(31 downto 0);
signal sig_667 : std_logic_vector(31 downto 0);
signal sig_668 : std_logic_vector(31 downto 0);
signal sig_669 : std_logic_vector(31 downto 0);
signal sig_670 : std_logic_vector(26 downto 0);
signal sig_671 : std_logic_vector(30 downto 0);
signal sig_672 : std_logic;
signal sig_673 : std_logic;
signal sig_674 : std_logic;
signal sig_675 : std_logic_vector(31 downto 0);
signal sig_676 : std_logic_vector(31 downto 0);
signal sig_677 : std_logic_vector(31 downto 0);
signal sig_678 : std_logic_vector(30 downto 0);
signal sig_679 : std_logic_vector(31 downto 0);
signal sig_680 : std_logic_vector(31 downto 0);
signal sig_681 : std_logic_vector(31 downto 0);
signal sig_682 : std_logic_vector(30 downto 0);
signal sig_683 : std_logic_vector(31 downto 0);
signal sig_684 : std_logic_vector(31 downto 0);
signal sig_685 : std_logic_vector(31 downto 0);
signal sig_686 : std_logic_vector(31 downto 0);
signal sig_687 : std_logic_vector(31 downto 0);
signal sig_688 : std_logic_vector(31 downto 0);
signal sig_689 : std_logic_vector(31 downto 0);
signal sig_690 : std_logic;
signal sig_691 : std_logic_vector(15 downto 0);
signal sig_692 : std_logic;
signal sig_693 : std_logic_vector(19 downto 0);
signal sig_694 : std_logic_vector(31 downto 0);
signal sig_695 : std_logic_vector(19 downto 0);
signal sig_696 : std_logic_vector(26 downto 0);
signal sig_697 : std_logic_vector(19 downto 0);
signal sig_698 : std_logic;
signal sig_699 : std_logic;
signal sig_700 : std_logic_vector(19 downto 0);
signal sig_701 : std_logic_vector(31 downto 0);
signal sig_702 : std_logic;
signal sig_703 : std_logic;
signal sig_704 : std_logic_vector(31 downto 0);
signal sig_705 : std_logic;
signal sig_706 : std_logic_vector(31 downto 0);
signal sig_707 : std_logic_vector(31 downto 0);
signal sig_708 : std_logic_vector(31 downto 0);
signal sig_709 : std_logic_vector(31 downto 0);
signal sig_710 : std_logic_vector(31 downto 0);
signal sig_711 : std_logic_vector(31 downto 0);
signal sig_712 : std_logic_vector(30 downto 0);
signal sig_713 : std_logic_vector(31 downto 0);
signal sig_714 : std_logic_vector(19 downto 0);
signal sig_715 : std_logic_vector(31 downto 0);
signal sig_716 : std_logic_vector(31 downto 0);
signal sig_717 : std_logic_vector(19 downto 0);
signal sig_718 : std_logic_vector(26 downto 0);
signal sig_719 : std_logic_vector(26 downto 0);
signal sig_720 : std_logic_vector(26 downto 0);
signal sig_721 : std_logic;
signal sig_722 : std_logic;
signal sig_723 : std_logic;
signal sig_724 : std_logic;
signal sig_725 : std_logic;
signal sig_726 : std_logic;
signal sig_727 : std_logic;
signal sig_728 : std_logic;
signal sig_729 : std_logic;
signal sig_730 : std_logic;
signal sig_731 : std_logic;
signal sig_732 : std_logic;
signal sig_733 : std_logic;
signal sig_734 : std_logic;
signal sig_735 : std_logic;
signal sig_736 : std_logic;
signal sig_737 : std_logic;
signal sig_738 : std_logic;
signal sig_739 : std_logic;
signal sig_740 : std_logic;
signal sig_741 : std_logic;
signal sig_742 : std_logic;
signal sig_743 : std_logic;
signal sig_744 : std_logic;
signal sig_745 : std_logic;
signal sig_746 : std_logic;
signal sig_747 : std_logic;
signal sig_748 : std_logic;
signal sig_749 : std_logic;
signal sig_750 : std_logic;
signal sig_751 : std_logic;
signal sig_752 : std_logic;
signal sig_753 : std_logic;
signal sig_754 : std_logic;
signal sig_755 : std_logic;
signal sig_756 : std_logic;
signal sig_757 : std_logic;
signal sig_758 : std_logic;
signal sig_759 : std_logic;
signal sig_760 : std_logic;
signal sig_761 : std_logic;
signal sig_762 : std_logic;
signal sig_763 : std_logic;
signal sig_764 : std_logic;
signal sig_765 : std_logic;
signal sig_766 : std_logic;
signal sig_767 : std_logic;
signal sig_768 : std_logic;
signal sig_769 : std_logic;
signal sig_770 : std_logic;
signal sig_771 : std_logic;
signal sig_772 : std_logic;
signal sig_773 : std_logic;
signal sig_774 : std_logic;
signal sig_775 : std_logic;
signal sig_776 : std_logic;
signal sig_777 : std_logic;
signal sig_778 : std_logic;
signal sig_779 : std_logic;
signal sig_780 : std_logic;
signal sig_781 : std_logic;
signal sig_782 : std_logic;
signal sig_783 : std_logic;
signal sig_784 : std_logic;
signal sig_785 : std_logic;
signal sig_786 : std_logic;
signal sig_787 : std_logic;
signal sig_788 : std_logic;
signal sig_789 : std_logic;
signal sig_790 : std_logic;
signal sig_791 : std_logic;
signal sig_792 : std_logic;
signal sig_793 : std_logic;
signal sig_794 : std_logic;
signal sig_795 : std_logic;
signal sig_796 : std_logic;
signal sig_797 : std_logic;
signal sig_798 : std_logic;
signal sig_799 : std_logic;
signal sig_800 : std_logic;
signal sig_801 : std_logic;
signal sig_802 : std_logic;
signal sig_803 : std_logic;
signal sig_804 : std_logic;
signal sig_805 : std_logic;
signal sig_806 : std_logic;
signal sig_807 : std_logic;
signal sig_808 : std_logic;
signal sig_809 : std_logic;
signal sig_810 : std_logic;
signal sig_811 : std_logic;
signal sig_812 : std_logic;
signal sig_813 : std_logic;
signal sig_814 : std_logic;
signal sig_815 : std_logic;
signal sig_816 : std_logic;
signal sig_817 : std_logic;
signal sig_818 : std_logic;
signal sig_819 : std_logic;
signal sig_820 : std_logic;
signal sig_821 : std_logic;
signal sig_822 : std_logic;
signal sig_823 : std_logic;
signal sig_824 : std_logic;
signal sig_825 : std_logic;
signal sig_826 : std_logic;
signal sig_827 : std_logic;
signal sig_828 : std_logic;
signal sig_829 : std_logic;
signal sig_830 : std_logic;
signal sig_831 : std_logic;
signal sig_832 : std_logic;
signal sig_833 : std_logic;
signal sig_834 : std_logic;
signal sig_835 : std_logic;
signal sig_836 : std_logic;
signal sig_837 : std_logic;
signal sig_838 : std_logic;
signal sig_839 : std_logic;
signal sig_840 : std_logic;
signal sig_841 : std_logic;
signal sig_842 : std_logic;
signal sig_843 : std_logic;
signal sig_844 : std_logic;
signal sig_845 : std_logic;
signal sig_846 : std_logic;
signal sig_847 : std_logic;
signal sig_848 : std_logic;
signal sig_849 : std_logic;
signal sig_850 : std_logic;
signal sig_851 : std_logic;
signal sig_852 : std_logic;
signal sig_853 : std_logic;
signal sig_854 : std_logic;
signal sig_855 : std_logic;
signal sig_856 : std_logic;
signal sig_857 : std_logic;
signal sig_858 : std_logic;
signal sig_859 : std_logic;
signal sig_860 : std_logic;
signal sig_861 : std_logic;
signal sig_862 : std_logic;
signal sig_863 : std_logic;
signal sig_864 : std_logic;
signal sig_865 : std_logic;
signal sig_866 : std_logic;
signal sig_867 : std_logic;
signal sig_868 : std_logic;
signal sig_869 : std_logic;
signal sig_870 : std_logic;
signal sig_871 : std_logic;
signal sig_872 : std_logic;
signal sig_873 : std_logic;
signal sig_874 : std_logic;
signal sig_875 : std_logic;
signal sig_876 : std_logic;
signal sig_877 : std_logic;
signal sig_878 : std_logic;
signal sig_879 : std_logic;
signal sig_880 : std_logic;
signal sig_881 : std_logic;
signal sig_882 : std_logic;
signal sig_883 : std_logic;
signal sig_884 : std_logic;
signal sig_885 : std_logic;
signal sig_886 : std_logic;
signal sig_887 : std_logic;
signal sig_888 : std_logic;
signal sig_889 : std_logic;
signal sig_890 : std_logic;
signal sig_891 : std_logic;
signal sig_892 : std_logic;
signal sig_893 : std_logic;
signal sig_894 : std_logic;
signal sig_895 : std_logic;
signal sig_896 : std_logic;
signal sig_897 : std_logic;
signal sig_898 : std_logic;
signal sig_899 : std_logic;
signal sig_900 : std_logic;
signal sig_901 : std_logic;
signal sig_902 : std_logic;
signal sig_903 : std_logic;
signal sig_904 : std_logic;
signal sig_905 : std_logic;
signal sig_906 : std_logic;
signal sig_907 : std_logic;
signal sig_908 : std_logic;
signal sig_909 : std_logic;
signal sig_910 : std_logic;
signal sig_911 : std_logic;
signal sig_912 : std_logic;
signal sig_913 : std_logic;
signal sig_914 : std_logic;
signal sig_915 : std_logic;
signal sig_916 : std_logic;
signal sig_917 : std_logic;
signal sig_918 : std_logic;
signal sig_919 : std_logic;
signal sig_920 : std_logic;
signal sig_921 : std_logic;
signal sig_922 : std_logic;
signal sig_923 : std_logic;
signal sig_924 : std_logic;
signal sig_925 : std_logic;
signal sig_926 : std_logic;
signal sig_927 : std_logic;
signal sig_928 : std_logic;
signal sig_929 : std_logic;
signal sig_930 : std_logic;
signal sig_931 : std_logic;
signal sig_932 : std_logic;
signal sig_933 : std_logic;
signal sig_934 : std_logic;
signal sig_935 : std_logic;
signal sig_936 : std_logic;
signal sig_937 : std_logic;
signal sig_938 : std_logic;
signal sig_939 : std_logic;
signal sig_940 : std_logic;
signal sig_941 : std_logic;
signal sig_942 : std_logic;
signal sig_943 : std_logic;
signal sig_944 : std_logic;
signal sig_945 : std_logic;
signal sig_946 : std_logic;
signal sig_947 : std_logic;
signal sig_948 : std_logic;
signal sig_949 : std_logic;
signal sig_950 : std_logic;
signal sig_951 : std_logic;
signal sig_952 : std_logic;
signal sig_953 : std_logic;
signal sig_954 : std_logic;
signal sig_955 : std_logic;
signal sig_956 : std_logic;
signal sig_957 : std_logic;
signal sig_958 : std_logic;
signal sig_959 : std_logic;
signal sig_960 : std_logic;
signal sig_961 : std_logic;
signal sig_962 : std_logic;
signal sig_963 : std_logic;
signal sig_964 : std_logic;
signal sig_965 : std_logic;
signal sig_966 : std_logic;
signal sig_967 : std_logic;
signal sig_968 : std_logic;
signal sig_969 : std_logic;
signal sig_970 : std_logic;
signal sig_971 : std_logic;
signal sig_972 : std_logic;
signal sig_973 : std_logic;
signal sig_974 : std_logic;
signal sig_975 : std_logic;
signal sig_976 : std_logic;
signal sig_977 : std_logic;
signal sig_978 : std_logic;
signal sig_979 : std_logic;
signal sig_980 : std_logic;
signal sig_981 : std_logic;
signal sig_982 : std_logic;
signal sig_983 : std_logic;
signal sig_984 : std_logic;
signal sig_985 : std_logic;
signal sig_986 : std_logic;
signal sig_987 : std_logic;
signal sig_988 : std_logic;
signal sig_989 : std_logic;
signal sig_990 : std_logic;
signal sig_991 : std_logic;
signal sig_992 : std_logic;
signal sig_993 : std_logic;
signal sig_994 : std_logic;
signal sig_995 : std_logic;
signal sig_996 : std_logic;
signal sig_997 : std_logic;
signal sig_998 : std_logic;
signal sig_999 : std_logic;
signal sig_1000 : std_logic;
signal sig_1001 : std_logic;
signal sig_1002 : std_logic;
signal sig_1003 : std_logic;
signal sig_1004 : std_logic;
signal sig_1005 : std_logic;
signal sig_1006 : std_logic;
signal sig_1007 : std_logic;
signal sig_1008 : std_logic;
signal sig_1009 : std_logic;
signal sig_1010 : std_logic;
signal sig_1011 : std_logic;
signal sig_1012 : std_logic;
signal sig_1013 : std_logic;
signal sig_1014 : std_logic;
signal sig_1015 : std_logic;
signal sig_1016 : std_logic;
signal sig_1017 : std_logic;
signal sig_1018 : std_logic;
signal sig_1019 : std_logic;
signal sig_1020 : std_logic;
signal sig_1021 : std_logic;
signal sig_1022 : std_logic;
signal sig_1023 : std_logic;
signal sig_1024 : std_logic;
signal sig_1025 : std_logic;
signal sig_1026 : std_logic;
signal sig_1027 : std_logic;
signal sig_1028 : std_logic;
signal sig_1029 : std_logic;
signal sig_1030 : std_logic;
signal sig_1031 : std_logic;
signal sig_1032 : std_logic;
signal sig_1033 : std_logic;
signal sig_1034 : std_logic;
signal sig_1035 : std_logic;
signal sig_1036 : std_logic;
signal sig_1037 : std_logic;
signal sig_1038 : std_logic;
signal sig_1039 : std_logic;
signal sig_1040 : std_logic;
signal sig_1041 : std_logic;
signal sig_1042 : std_logic;
signal sig_1043 : std_logic;
signal sig_1044 : std_logic;
signal sig_1045 : std_logic;
signal sig_1046 : std_logic;
signal sig_1047 : std_logic;
signal sig_1048 : std_logic;
signal sig_1049 : std_logic;
signal sig_1050 : std_logic;
signal sig_1051 : std_logic;
signal sig_1052 : std_logic;
signal sig_1053 : std_logic;
signal sig_1054 : std_logic;
signal sig_1055 : std_logic;
signal sig_1056 : std_logic;
signal sig_1057 : std_logic;
signal sig_1058 : std_logic;
signal sig_1059 : std_logic_vector(31 downto 0);
signal sig_1060 : std_logic_vector(31 downto 0);
signal sig_1061 : std_logic_vector(31 downto 0);
signal sig_1062 : std_logic_vector(31 downto 0);
signal sig_1063 : std_logic_vector(31 downto 0);
signal sig_1064 : std_logic;
signal sig_1065 : std_logic;
signal sig_1066 : std_logic;
signal sig_1067 : std_logic;
signal sig_1068 : std_logic;
signal sig_1069 : std_logic;
signal sig_1070 : std_logic;
signal sig_1071 : std_logic_vector(31 downto 0);
signal sig_1072 : std_logic_vector(31 downto 0);
signal sig_1073 : std_logic_vector(31 downto 0);
signal sig_1074 : std_logic_vector(31 downto 0);
signal sig_1075 : std_logic_vector(31 downto 0);
signal sig_1076 : std_logic_vector(30 downto 0);
signal sig_1077 : std_logic_vector(31 downto 0);
signal sig_1078 : std_logic_vector(31 downto 0);
signal sig_1079 : std_logic_vector(31 downto 0);
signal sig_1080 : std_logic_vector(19 downto 0);
signal sig_1081 : std_logic_vector(19 downto 0);
signal sig_1082 : std_logic_vector(19 downto 0);
signal sig_1083 : std_logic_vector(31 downto 0);
signal sig_1084 : std_logic_vector(31 downto 0);
signal sig_1085 : std_logic_vector(31 downto 0);
signal sig_1086 : std_logic_vector(31 downto 0);
signal sig_1087 : std_logic_vector(31 downto 0);
signal sig_1088 : std_logic_vector(26 downto 0);
signal sig_1089 : std_logic_vector(26 downto 0);
signal sig_1090 : std_logic_vector(31 downto 0);
signal sig_1091 : std_logic_vector(29 downto 0);
signal sig_1092 : std_logic_vector(31 downto 0);
signal sig_1093 : std_logic_vector(31 downto 0);
signal sig_1094 : std_logic_vector(31 downto 0);
signal sig_1095 : std_logic_vector(31 downto 0);
signal sig_1096 : std_logic_vector(7 downto 0);
signal sig_1097 : std_logic_vector(7 downto 0);
signal sig_1098 : std_logic_vector(7 downto 0);
signal sig_1099 : std_logic_vector(7 downto 0);
signal sig_1100 : std_logic_vector(31 downto 0);
signal sig_1101 : std_logic_vector(31 downto 0);
signal sig_1102 : std_logic_vector(31 downto 0);
signal sig_1103 : std_logic_vector(31 downto 0);
signal sig_1104 : std_logic_vector(26 downto 0);
signal sig_1105 : std_logic_vector(31 downto 0);
signal sig_1106 : std_logic;
signal sig_1107 : std_logic_vector(26 downto 0);
signal sig_1108 : std_logic_vector(26 downto 0);
signal sig_1109 : std_logic_vector(31 downto 0);
signal sig_1110 : std_logic_vector(31 downto 0);
signal sig_1111 : std_logic_vector(31 downto 0);
signal sig_1112 : std_logic_vector(30 downto 0);
signal sig_1113 : std_logic_vector(31 downto 0);
signal sig_1114 : std_logic_vector(31 downto 0);
signal sig_1115 : std_logic_vector(31 downto 0);
signal sig_1116 : std_logic_vector(26 downto 0);
signal sig_1117 : std_logic_vector(26 downto 0);
signal sig_1118 : std_logic_vector(26 downto 0);
signal sig_1119 : std_logic_vector(31 downto 0);
signal sig_1120 : std_logic_vector(31 downto 0);
signal sig_1121 : std_logic_vector(31 downto 0);
signal sig_1122 : std_logic_vector(29 downto 0);
signal sig_1123 : std_logic_vector(31 downto 0);
signal sig_1124 : std_logic_vector(31 downto 0);
signal sig_1125 : std_logic_vector(19 downto 0);
signal sig_1126 : std_logic_vector(19 downto 0);
signal sig_1127 : std_logic_vector(19 downto 0);
signal sig_1128 : std_logic_vector(15 downto 0);
signal sig_1129 : std_logic_vector(31 downto 0);
signal sig_1130 : std_logic;
signal sig_1131 : std_logic_vector(31 downto 0);
signal sig_1132 : std_logic_vector(30 downto 0);
signal sig_1133 : std_logic_vector(31 downto 0);
signal sig_1134 : std_logic_vector(31 downto 0);
signal sig_1135 : std_logic_vector(31 downto 0);
signal sig_1136 : std_logic_vector(31 downto 0);
signal sig_1137 : std_logic_vector(31 downto 0);
signal sig_1138 : std_logic_vector(31 downto 0);
signal sig_1139 : std_logic_vector(31 downto 0);
signal sig_1140 : std_logic_vector(31 downto 0);
signal sig_1141 : std_logic_vector(31 downto 0);
signal sig_1142 : std_logic_vector(31 downto 0);
signal sig_1143 : std_logic_vector(30 downto 0);
signal sig_1144 : std_logic_vector(31 downto 0);
signal sig_1145 : std_logic_vector(31 downto 0);
signal sig_1146 : std_logic_vector(29 downto 0);
signal sig_1147 : std_logic_vector(30 downto 0);
signal sig_1148 : std_logic_vector(30 downto 0);
signal sig_1149 : std_logic_vector(31 downto 0);
signal sig_1150 : std_logic_vector(31 downto 0);
signal sig_1151 : std_logic_vector(19 downto 0);
signal sig_1152 : std_logic_vector(19 downto 0);
signal sig_1153 : std_logic_vector(7 downto 0);
signal sig_1154 : std_logic_vector(7 downto 0);
signal sig_1155 : std_logic_vector(26 downto 0);
signal sig_1156 : std_logic_vector(31 downto 0);
signal sig_1157 : std_logic;
signal sig_1158 : std_logic_vector(7 downto 0);
signal sig_1159 : std_logic_vector(7 downto 0);
signal sig_1160 : std_logic_vector(19 downto 0);
signal sig_1161 : std_logic_vector(31 downto 0);
signal sig_1162 : std_logic_vector(31 downto 0);
signal sig_1163 : std_logic_vector(19 downto 0);
signal sig_1164 : std_logic_vector(31 downto 0);
signal sig_1165 : std_logic_vector(19 downto 0);
signal sig_1166 : std_logic_vector(19 downto 0);
signal sig_1167 : std_logic_vector(19 downto 0);
signal sig_1168 : std_logic_vector(19 downto 0);
signal sig_1169 : std_logic_vector(19 downto 0);
signal sig_1170 : std_logic_vector(31 downto 0);
signal sig_1171 : std_logic_vector(19 downto 0);
signal sig_1172 : std_logic_vector(19 downto 0);
signal sig_1173 : std_logic_vector(19 downto 0);
signal sig_1174 : std_logic_vector(31 downto 0);
signal sig_1175 : std_logic_vector(31 downto 0);
signal sig_1176 : std_logic_vector(31 downto 0);
signal sig_1177 : std_logic_vector(31 downto 0);
signal sig_1178 : std_logic_vector(31 downto 0);
signal sig_1179 : std_logic_vector(19 downto 0);
signal sig_1180 : std_logic_vector(19 downto 0);
signal sig_1181 : std_logic_vector(19 downto 0);
signal sig_1182 : std_logic_vector(19 downto 0);
signal sig_1183 : std_logic_vector(19 downto 0);
-- Other inlined components
signal mux_66 : std_logic_vector(2 downto 0);
signal mux_30 : std_logic;
signal mux_32 : std_logic;
signal mux_33 : std_logic;
signal mux_34 : std_logic;
signal augh_main_k : std_logic_vector(31 downto 0) := (others => '0');
signal read32_ret0_10 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_58 : std_logic_vector(2 downto 0);
signal mux_59 : std_logic_vector(2 downto 0);
signal mux_60 : std_logic;
signal mux_61 : std_logic_vector(7 downto 0);
signal mux_62 : std_logic_vector(2 downto 0);
signal mux_63 : std_logic_vector(2 downto 0);
signal mux_64 : std_logic;
signal mux_65 : std_logic_vector(7 downto 0);
signal mux_35 : std_logic;
signal mux_36 : std_logic;
signal mux_37 : std_logic_vector(15 downto 0);
signal mux_38 : std_logic;
signal mux_39 : std_logic_vector(31 downto 0);
signal idct_2d_r : std_logic_vector(31 downto 0) := (others => '0');
signal mux_45 : std_logic_vector(4 downto 0);
signal mux_46 : std_logic_vector(4 downto 0);
signal mux_47 : std_logic_vector(4 downto 0);
signal mux_48 : std_logic_vector(4 downto 0);
signal mux_49 : std_logic_vector(4 downto 0);
signal mux_40 : std_logic_vector(4 downto 0);
signal mux_41 : std_logic_vector(4 downto 0);
signal mux_42 : std_logic;
signal mux_43 : std_logic_vector(4 downto 0);
signal mux_44 : std_logic_vector(4 downto 0);
signal write8_u8 : std_logic_vector(7 downto 0) := (others => '0');
signal mux_50 : std_logic_vector(31 downto 0);
signal mux_51 : std_logic_vector(4 downto 0);
signal mux_52 : std_logic;
signal mux_53 : std_logic_vector(7 downto 0);
signal mux_54 : std_logic_vector(2 downto 0);
signal mux_55 : std_logic_vector(2 downto 0);
signal mux_56 : std_logic;
signal mux_57 : std_logic_vector(7 downto 0);
signal idct_z3_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z3_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z3_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z3_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_88 : std_logic;
signal mux_67 : std_logic_vector(2 downto 0);
signal mux_68 : std_logic;
signal mux_69 : std_logic_vector(31 downto 0);
signal mux_71 : std_logic_vector(31 downto 0);
signal mux_73 : std_logic_vector(31 downto 0);
signal mux_75 : std_logic_vector(31 downto 0);
signal mux_77 : std_logic_vector(31 downto 0);
signal mux_79 : std_logic_vector(31 downto 0);
signal mux_81 : std_logic_vector(31 downto 0);
signal mux_83 : std_logic_vector(31 downto 0);
signal mux_85 : std_logic_vector(7 downto 0);
signal mux_86 : std_logic_vector(2 downto 0);
signal mux_87 : std_logic_vector(2 downto 0);
signal mux_28 : std_logic;
signal idct_z1_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z1_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_z2_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_109 : std_logic_vector(31 downto 0);
signal mux_154 : std_logic;
signal mux_156 : std_logic_vector(7 downto 0);
signal idct_2d_yc_reg0 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg1 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg2 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg3 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg4 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg5 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg6 : std_logic_vector(31 downto 0) := (others => '0');
signal idct_2d_yc_reg7 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_89 : std_logic_vector(7 downto 0);
signal mux_90 : std_logic_vector(2 downto 0);
signal mux_134 : std_logic;
signal mux_91 : std_logic_vector(2 downto 0);
signal mux_92 : std_logic;
signal mux_158 : std_logic_vector(7 downto 0);
signal mux_111 : std_logic_vector(31 downto 0);
signal mux_113 : std_logic_vector(31 downto 0);
signal mux_115 : std_logic_vector(31 downto 0);
signal mux_117 : std_logic_vector(31 downto 0);
signal mux_119 : std_logic_vector(31 downto 0);
signal mux_121 : std_logic_vector(31 downto 0);
signal mux_123 : std_logic_vector(31 downto 0);
signal or_224 : std_logic_vector(31 downto 0);
signal and_225 : std_logic_vector(31 downto 0);
signal or_231 : std_logic_vector(31 downto 0);
signal and_232 : std_logic_vector(31 downto 0);
signal or_250 : std_logic_vector(31 downto 0);
signal and_251 : std_logic_vector(31 downto 0);
signal or_260 : std_logic_vector(31 downto 0);
signal and_261 : std_logic_vector(31 downto 0);
signal or_282 : std_logic_vector(31 downto 0);
signal and_283 : std_logic_vector(31 downto 0);
signal or_285 : std_logic_vector(31 downto 0);
signal and_286 : std_logic_vector(31 downto 0);
signal or_289 : std_logic_vector(31 downto 0);
signal and_290 : std_logic_vector(31 downto 0);
signal or_291 : std_logic_vector(31 downto 0);
signal and_292 : std_logic_vector(31 downto 0);
signal or_297 : std_logic_vector(31 downto 0);
signal and_298 : std_logic_vector(31 downto 0);
signal or_299 : std_logic_vector(31 downto 0);
signal and_300 : std_logic_vector(31 downto 0);
signal or_320 : std_logic_vector(31 downto 0);
signal and_321 : std_logic_vector(31 downto 0);
signal or_326 : std_logic_vector(31 downto 0);
signal and_327 : std_logic_vector(31 downto 0);
signal or_333 : std_logic_vector(31 downto 0);
signal and_334 : std_logic_vector(31 downto 0);
signal or_363 : std_logic_vector(31 downto 0);
signal and_364 : std_logic_vector(31 downto 0);
signal and_403 : std_logic_vector(7 downto 0);
signal and_405 : std_logic_vector(7 downto 0);
signal and_407 : std_logic_vector(7 downto 0);
signal and_409 : std_logic_vector(7 downto 0);
signal and_415 : std_logic_vector(30 downto 0);
signal or_464 : std_logic_vector(31 downto 0);
signal and_465 : std_logic_vector(31 downto 0);
signal or_470 : std_logic_vector(31 downto 0);
signal and_471 : std_logic_vector(31 downto 0);
signal or_472 : std_logic_vector(31 downto 0);
signal and_473 : std_logic_vector(31 downto 0);
signal or_500 : std_logic_vector(31 downto 0);
signal and_501 : std_logic_vector(31 downto 0);
signal or_504 : std_logic_vector(31 downto 0);
signal and_505 : std_logic_vector(31 downto 0);
signal or_506 : std_logic_vector(31 downto 0);
signal and_507 : std_logic_vector(31 downto 0);
signal or_514 : std_logic_vector(31 downto 0);
signal and_515 : std_logic_vector(31 downto 0);
signal or_522 : std_logic_vector(31 downto 0);
signal and_523 : std_logic_vector(31 downto 0);
signal psc_loop_reg_13 : std_logic_vector(15 downto 0) := (others => '0');
signal cp_id_reg_14 : std_logic := '0';
signal cp_id_reg_stable_15 : std_logic := '0';
signal psc_stuff_reg_18 : std_logic_vector(23 downto 0) := (others => '0');
signal psc_stuff_reg_19 : std_logic_vector(62 downto 0) := "000000000000000000000000000000000000000000000000000000000000000";
signal mux_129 : std_logic_vector(31 downto 0);
signal mux_133 : std_logic_vector(7 downto 0);
signal mux_135 : std_logic_vector(31 downto 0);
signal mux_137 : std_logic_vector(7 downto 0);
signal mux_138 : std_logic_vector(2 downto 0);
signal mux_139 : std_logic_vector(2 downto 0);
signal mux_140 : std_logic;
signal mux_141 : std_logic_vector(7 downto 0);
signal mux_142 : std_logic_vector(2 downto 0);
signal mux_143 : std_logic_vector(2 downto 0);
signal mux_144 : std_logic;
signal mux_147 : std_logic;
signal mux_149 : std_logic_vector(31 downto 0);
signal mux_150 : std_logic;
signal mux_151 : std_logic;
signal mux_152 : std_logic_vector(63 downto 0);
signal mux_155 : std_logic;
signal or_221 : std_logic_vector(31 downto 0);
signal and_222 : std_logic_vector(31 downto 0);
signal or_233 : std_logic_vector(31 downto 0);
signal and_234 : std_logic_vector(31 downto 0);
signal or_237 : std_logic_vector(31 downto 0);
signal and_238 : std_logic_vector(31 downto 0);
signal or_252 : std_logic_vector(31 downto 0);
signal and_253 : std_logic_vector(31 downto 0);
signal or_256 : std_logic_vector(31 downto 0);
signal and_257 : std_logic_vector(31 downto 0);
signal or_268 : std_logic_vector(31 downto 0);
signal and_269 : std_logic_vector(31 downto 0);
signal or_270 : std_logic_vector(31 downto 0);
signal and_271 : std_logic_vector(31 downto 0);
signal or_274 : std_logic_vector(31 downto 0);
signal and_275 : std_logic_vector(31 downto 0);
signal or_278 : std_logic_vector(31 downto 0);
signal and_279 : std_logic_vector(31 downto 0);
signal or_310 : std_logic_vector(31 downto 0);
signal and_311 : std_logic_vector(31 downto 0);
signal or_316 : std_logic_vector(31 downto 0);
signal and_317 : std_logic_vector(31 downto 0);
signal or_358 : std_logic_vector(31 downto 0);
signal and_359 : std_logic_vector(31 downto 0);
signal or_366 : std_logic_vector(31 downto 0);
signal and_367 : std_logic_vector(31 downto 0);
signal or_374 : std_logic_vector(31 downto 0);
signal and_375 : std_logic_vector(31 downto 0);
signal or_417 : std_logic_vector(31 downto 0);
signal and_418 : std_logic_vector(31 downto 0);
signal or_421 : std_logic_vector(31 downto 0);
signal and_422 : std_logic_vector(31 downto 0);
signal or_435 : std_logic_vector(31 downto 0);
signal and_436 : std_logic_vector(31 downto 0);
signal or_452 : std_logic_vector(31 downto 0);
signal and_453 : std_logic_vector(31 downto 0);
signal and_494 : std_logic_vector(31 downto 0);
signal and_498 : std_logic_vector(31 downto 0);
signal or_509 : std_logic_vector(30 downto 0);
signal and_510 : std_logic_vector(30 downto 0);
signal or_550 : std_logic_vector(31 downto 0);
signal and_551 : std_logic_vector(31 downto 0);
signal or_581 : std_logic_vector(31 downto 0);
signal and_582 : std_logic_vector(31 downto 0);
signal or_583 : std_logic_vector(31 downto 0);
signal and_584 : std_logic_vector(31 downto 0);
signal or_587 : std_logic_vector(31 downto 0);
signal and_588 : std_logic_vector(31 downto 0);
signal and_161 : std_logic;
signal or_228 : std_logic_vector(31 downto 0);
signal and_229 : std_logic_vector(31 downto 0);
signal or_239 : std_logic_vector(31 downto 0);
signal and_240 : std_logic_vector(31 downto 0);
signal or_241 : std_logic_vector(31 downto 0);
signal and_242 : std_logic_vector(31 downto 0);
signal or_244 : std_logic_vector(31 downto 0);
signal and_245 : std_logic_vector(31 downto 0);
signal or_246 : std_logic_vector(31 downto 0);
signal and_247 : std_logic_vector(31 downto 0);
signal or_248 : std_logic_vector(31 downto 0);
signal and_249 : std_logic_vector(31 downto 0);
signal or_258 : std_logic_vector(31 downto 0);
signal and_259 : std_logic_vector(31 downto 0);
signal not_264 : std_logic;
signal or_266 : std_logic_vector(31 downto 0);
signal and_267 : std_logic_vector(31 downto 0);
signal or_272 : std_logic_vector(31 downto 0);
signal and_273 : std_logic_vector(31 downto 0);
signal or_280 : std_logic_vector(31 downto 0);
signal and_281 : std_logic_vector(31 downto 0);
signal or_287 : std_logic_vector(31 downto 0);
signal and_288 : std_logic_vector(31 downto 0);
signal or_293 : std_logic_vector(31 downto 0);
signal and_294 : std_logic_vector(31 downto 0);
signal or_301 : std_logic_vector(31 downto 0);
signal and_302 : std_logic_vector(31 downto 0);
signal or_304 : std_logic_vector(31 downto 0);
signal and_305 : std_logic_vector(31 downto 0);
signal or_306 : std_logic_vector(31 downto 0);
signal and_307 : std_logic_vector(31 downto 0);
signal or_308 : std_logic_vector(31 downto 0);
signal and_309 : std_logic_vector(31 downto 0);
signal or_312 : std_logic_vector(31 downto 0);
signal and_313 : std_logic_vector(31 downto 0);
signal or_318 : std_logic_vector(31 downto 0);
signal and_319 : std_logic_vector(31 downto 0);
signal or_329 : std_logic_vector(31 downto 0);
signal and_330 : std_logic_vector(31 downto 0);
signal or_335 : std_logic_vector(31 downto 0);
signal and_336 : std_logic_vector(31 downto 0);
signal or_339 : std_logic_vector(31 downto 0);
signal and_340 : std_logic_vector(31 downto 0);
signal or_342 : std_logic_vector(31 downto 0);
signal and_343 : std_logic_vector(31 downto 0);
signal or_346 : std_logic_vector(31 downto 0);
signal and_347 : std_logic_vector(31 downto 0);
signal or_348 : std_logic_vector(31 downto 0);
signal and_349 : std_logic_vector(31 downto 0);
signal or_351 : std_logic_vector(30 downto 0);
signal and_352 : std_logic_vector(30 downto 0);
signal or_355 : std_logic_vector(30 downto 0);
signal and_356 : std_logic_vector(30 downto 0);
signal or_360 : std_logic_vector(31 downto 0);
signal and_361 : std_logic_vector(31 downto 0);
signal or_371 : std_logic_vector(31 downto 0);
signal and_372 : std_logic_vector(31 downto 0);
signal or_378 : std_logic_vector(31 downto 0);
signal and_379 : std_logic_vector(31 downto 0);
signal or_380 : std_logic_vector(31 downto 0);
signal and_381 : std_logic_vector(31 downto 0);
signal or_384 : std_logic_vector(31 downto 0);
signal and_385 : std_logic_vector(31 downto 0);
signal or_386 : std_logic_vector(31 downto 0);
signal and_387 : std_logic_vector(31 downto 0);
signal or_388 : std_logic_vector(31 downto 0);
signal and_389 : std_logic_vector(31 downto 0);
signal or_394 : std_logic_vector(7 downto 0);
signal and_395 : std_logic_vector(7 downto 0);
signal and_397 : std_logic_vector(7 downto 0);
signal and_399 : std_logic_vector(7 downto 0);
signal and_401 : std_logic_vector(7 downto 0);
signal or_414 : std_logic_vector(30 downto 0);
signal or_423 : std_logic_vector(31 downto 0);
signal and_424 : std_logic_vector(31 downto 0);
signal or_425 : std_logic_vector(31 downto 0);
signal and_426 : std_logic_vector(31 downto 0);
signal or_427 : std_logic_vector(31 downto 0);
signal and_428 : std_logic_vector(31 downto 0);
signal or_431 : std_logic_vector(31 downto 0);
signal and_432 : std_logic_vector(31 downto 0);
signal or_433 : std_logic_vector(31 downto 0);
signal and_434 : std_logic_vector(31 downto 0);
signal or_438 : std_logic_vector(31 downto 0);
signal and_439 : std_logic_vector(31 downto 0);
signal or_440 : std_logic_vector(31 downto 0);
signal and_441 : std_logic_vector(31 downto 0);
signal or_443 : std_logic_vector(31 downto 0);
signal and_444 : std_logic_vector(31 downto 0);
signal or_450 : std_logic_vector(31 downto 0);
signal and_451 : std_logic_vector(31 downto 0);
signal or_454 : std_logic_vector(30 downto 0);
signal and_455 : std_logic_vector(30 downto 0);
signal or_458 : std_logic_vector(31 downto 0);
signal and_459 : std_logic_vector(31 downto 0);
signal or_462 : std_logic_vector(31 downto 0);
signal and_463 : std_logic_vector(31 downto 0);
signal or_467 : std_logic_vector(30 downto 0);
signal and_468 : std_logic_vector(30 downto 0);
signal or_475 : std_logic_vector(30 downto 0);
signal and_476 : std_logic_vector(30 downto 0);
signal or_479 : std_logic_vector(31 downto 0);
signal and_480 : std_logic_vector(31 downto 0);
signal or_481 : std_logic_vector(31 downto 0);
signal and_482 : std_logic_vector(31 downto 0);
signal or_485 : std_logic_vector(31 downto 0);
signal and_486 : std_logic_vector(31 downto 0);
signal or_490 : std_logic_vector(31 downto 0);
signal and_491 : std_logic_vector(31 downto 0);
signal or_493 : std_logic_vector(31 downto 0);
signal or_497 : std_logic_vector(31 downto 0);
signal or_512 : std_logic_vector(31 downto 0);
signal and_513 : std_logic_vector(31 downto 0);
signal or_518 : std_logic_vector(30 downto 0);
signal and_519 : std_logic_vector(30 downto 0);
signal or_525 : std_logic_vector(31 downto 0);
signal and_526 : std_logic_vector(31 downto 0);
signal or_529 : std_logic_vector(30 downto 0);
signal and_530 : std_logic_vector(30 downto 0);
signal or_532 : std_logic_vector(30 downto 0);
signal and_533 : std_logic_vector(30 downto 0);
signal or_535 : std_logic_vector(31 downto 0);
signal and_536 : std_logic_vector(31 downto 0);
signal or_538 : std_logic_vector(31 downto 0);
signal and_539 : std_logic_vector(31 downto 0);
signal or_541 : std_logic_vector(31 downto 0);
signal and_542 : std_logic_vector(31 downto 0);
signal or_545 : std_logic_vector(30 downto 0);
signal and_546 : std_logic_vector(30 downto 0);
signal or_548 : std_logic_vector(31 downto 0);
signal and_549 : std_logic_vector(31 downto 0);
signal or_554 : std_logic_vector(30 downto 0);
signal and_555 : std_logic_vector(30 downto 0);
signal or_557 : std_logic_vector(30 downto 0);
signal and_558 : std_logic_vector(30 downto 0);
signal or_568 : std_logic_vector(31 downto 0);
signal and_569 : std_logic_vector(31 downto 0);
signal or_571 : std_logic_vector(30 downto 0);
signal and_572 : std_logic_vector(30 downto 0);
signal or_575 : std_logic_vector(30 downto 0);
signal and_576 : std_logic_vector(30 downto 0);
signal or_590 : std_logic_vector(31 downto 0);
signal and_591 : std_logic_vector(31 downto 0);
signal or_597 : std_logic_vector(31 downto 0);
signal and_598 : std_logic_vector(31 downto 0);
signal or_603 : std_logic_vector(30 downto 0);
signal and_604 : std_logic_vector(30 downto 0);
-- This utility function is used for to generate concatenations of std_logic
-- Little utility function to ease concatenation of an std_logic
-- and explicitely return an std_logic_vector
function repeat(N: natural; B: std_logic) return std_logic_vector is
variable result: std_logic_vector(N-1 downto 0);
begin
result := (others => B);
return result;
end;
begin
-- Instantiation of components
output_split2_i : output_split2 port map (
wa0_data => mux_141,
wa0_addr => mux_142,
ra0_data => sig_1159,
ra0_addr => mux_143,
wa0_en => mux_144,
clk => sig_clock
);
output_split3_i : output_split3 port map (
wa0_data => mux_137,
wa0_addr => mux_138,
ra0_data => sig_1158,
ra0_addr => mux_139,
wa0_en => mux_140,
clk => sig_clock
);
sub_159_i : sub_159 port map (
gt => sig_1157,
result => sig_1156,
in_a => idct_2d_r,
in_b => "00000000000000000000000011111111",
sign => '1'
);
add_165_i : add_165 port map (
result => sig_1155,
in_a => idct_2d_yc_reg7(31 downto 5),
in_b => "000000000000000000000000001"
);
output_split1_i : output_split1 port map (
wa0_data => mux_89,
wa0_addr => mux_90,
ra0_data => sig_1154,
ra0_addr => mux_91,
wa0_en => mux_92,
clk => sig_clock
);
output_split0_i : output_split0 port map (
wa0_data => mux_85,
wa0_addr => mux_86,
ra0_data => sig_1153,
ra0_addr => mux_87,
wa0_en => mux_88,
clk => sig_clock
);
add_172_i : add_172 port map (
result => sig_1152,
in_a => sig_1183,
in_b => "00000000000000000001"
);
add_176_i : add_176 port map (
result => sig_1151,
in_a => sig_1182,
in_b => "00000000000000000001"
);
add_181_i : add_181 port map (
result => sig_1150,
in_a => idct_z2_reg0,
in_b => idct_z3_reg7
);
sub_187_i : sub_187 port map (
result => sig_1149,
in_a => idct_z2_reg1,
in_b => idct_z3_reg6
);
mul_189_i : mul_189 port map (
result => sig_1148,
in_a => idct_z2_reg4(30 downto 0),
in_b => "01000111000111"
);
add_191_i : add_191 port map (
result => sig_1147,
in_a => sig_1148,
in_b => sig_1123(31 downto 1)
);
mul_192_i : mul_192 port map (
result => sig_1146,
in_a => idct_z2_reg5(29 downto 0),
in_b => "01100011111"
);
mul_193_i : mul_193 port map (
result => sig_1145,
in_a => idct_z2_reg6,
in_b => "011111011000101"
);
mul_198_i : mul_198 port map (
result => sig_1144,
in_a => idct_z2_reg4,
in_b => "011010100110111"
);
mul_199_i : mul_199 port map (
result => sig_1143,
in_a => idct_z2_reg7(30 downto 0),
in_b => "01000111000111"
);
sub_209_i : sub_209 port map (
result => sig_1142,
in_a => idct_2d_yc_reg1,
in_b => idct_2d_yc_reg7
);
add_212_i : add_212 port map (
result => sig_1141,
in_a => idct_z1_reg1,
in_b => idct_z1_reg2
);
sub_213_i : sub_213 port map (
result => sig_1140,
in_a => idct_z1_reg1,
in_b => idct_z1_reg2
);
sub_214_i : sub_214 port map (
result => sig_1139,
in_a => idct_z1_reg0,
in_b => idct_z1_reg3
);
mul_215_i : mul_215 port map (
result => sig_1138,
in_a => idct_2d_yc_reg2,
in_b => "0101001110011111"
);
mul_216_i : mul_216 port map (
result => sig_1137,
in_a => idct_2d_yc_reg6,
in_b => "010001010100011"
);
sub_217_i : sub_217 port map (
result => sig_1136,
in_a => sig_1138,
in_b => sig_1137
);
mul_218_i : mul_218 port map (
result => sig_1135,
in_a => idct_2d_yc_reg2,
in_b => "010001010100011"
);
mul_219_i : mul_219 port map (
result => sig_1134,
in_a => idct_2d_yc_reg6,
in_b => "0101001110011111"
);
sub_220_i : sub_220 port map (
result => sig_1133,
in_a => sig_1135,
in_b => sig_1134
);
mul_223_i : mul_223 port map (
result => sig_1132,
in_a => idct_2d_yc_reg5(30 downto 0),
in_b => "010110101000001"
);
sub_227_i : sub_227 port map (
result => sig_1131,
in_a => idct_2d_yc_reg0,
in_b => idct_2d_yc_reg4
);
sub_157_i : sub_157 port map (
ge => sig_1130,
result => sig_1129,
in_a => idct_2d_r,
in_b => "00000000000000000000000000000000",
sign => '1'
);
add_163_i : add_163 port map (
result => sig_1128,
in_a => psc_loop_reg_13,
in_b => "0000000000000001"
);
cmp_164_i : cmp_164 port map (
ne => memextrct_loop_sig_21,
in0 => "0000000000011111",
in1 => psc_loop_reg_13
);
add_170_i : add_170 port map (
result => sig_1127,
in_a => sig_1181,
in_b => "00000000000000000001"
);
add_174_i : add_174 port map (
result => sig_1126,
in_a => sig_1180,
in_b => "00000000000000000001"
);
add_180_i : add_180 port map (
result => sig_1125,
in_a => sig_1179,
in_b => "00000000000000000001"
);
sub_186_i : sub_186 port map (
result => sig_1124,
in_a => idct_z2_reg2,
in_b => idct_z3_reg5
);
mul_190_i : mul_190 port map (
result => sig_1123,
in_a => idct_z2_reg7,
in_b => "011010100110111"
);
mul_196_i : mul_196 port map (
result => sig_1122,
in_a => idct_z2_reg6(29 downto 0),
in_b => "01100011111"
);
sub_200_i : sub_200 port map (
result => sig_1121,
in_a => sig_1144,
in_b => sig_1178
);
add_206_i : add_206 port map (
result => sig_1120,
in_a => idct_z1_reg4,
in_b => idct_z1_reg6
);
add_210_i : add_210 port map (
result => sig_1119,
in_a => idct_2d_yc_reg1,
in_b => idct_2d_yc_reg7
);
add_171_i : add_171 port map (
result => sig_1118,
in_a => idct_2d_yc_reg4(31 downto 5),
in_b => "000000000000000000000000001"
);
add_177_i : add_177 port map (
result => sig_1117,
in_a => idct_2d_yc_reg1(31 downto 5),
in_b => "000000000000000000000000001"
);
add_179_i : add_179 port map (
result => sig_1116,
in_a => idct_2d_yc_reg0(31 downto 5),
in_b => "000000000000000000000000001"
);
mul_195_i : mul_195 port map (
result => sig_1115,
in_a => idct_z2_reg5,
in_b => "011111011000101"
);
sub_197_i : sub_197 port map (
result => sig_1114,
in_a => sig_1115,
in_b => sig_1177
);
sub_207_i : sub_207 port map (
result => sig_1113,
in_a => idct_z1_reg7,
in_b => idct_z1_reg5
);
mul_230_i : mul_230 port map (
result => sig_1112,
in_a => idct_2d_yc_reg3(30 downto 0),
in_b => "010110101000001"
);
sub_185_i : sub_185 port map (
result => sig_1111,
in_a => idct_z2_reg3,
in_b => idct_z3_reg4
);
add_211_i : add_211 port map (
result => sig_1110,
in_a => idct_z1_reg0,
in_b => idct_z1_reg3
);
add_226_i : add_226 port map (
result => sig_1109,
in_a => idct_2d_yc_reg0,
in_b => idct_2d_yc_reg4
);
add_235_i : add_235 port map (
result => sig_1108,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_314_i : add_314 port map (
result => sig_1107,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
sub_160_i : sub_160 port map (
le => sig_1106,
result => sig_1105,
in_a => idct_2d_r,
in_b => "00000000000000000000000011111111",
sign => '1'
);
add_173_i : add_173 port map (
result => sig_1104,
in_a => idct_2d_yc_reg3(31 downto 5),
in_b => "000000000000000000000000001"
);
add_182_i : add_182 port map (
result => sig_1103,
in_a => idct_z2_reg1,
in_b => idct_z3_reg6
);
sub_188_i : sub_188 port map (
result => sig_1102,
in_a => idct_z2_reg0,
in_b => idct_z3_reg7
);
sub_243_i : sub_243 port map (
result => sig_1101,
in_a => sig_1115,
in_b => sig_1176
);
sub_262_i : sub_262 port map (
result => sig_1100,
in_a => sig_1115,
in_b => sig_1175
);
output_split4_i : output_split4 port map (
wa0_data => mux_65,
wa0_addr => mux_66,
ra0_data => sig_1099,
ra0_addr => mux_67,
wa0_en => mux_68,
clk => sig_clock
);
output_split5_i : output_split5 port map (
wa0_data => mux_61,
wa0_addr => mux_62,
ra0_data => sig_1098,
ra0_addr => mux_63,
wa0_en => mux_64,
clk => sig_clock
);
output_split6_i : output_split6 port map (
wa0_data => mux_57,
wa0_addr => mux_58,
ra0_data => sig_1097,
ra0_addr => mux_59,
wa0_en => mux_60,
clk => sig_clock
);
output_split7_i : output_split7 port map (
wa0_data => mux_53,
wa0_addr => mux_54,
ra0_data => sig_1096,
ra0_addr => mux_55,
wa0_en => mux_56,
clk => sig_clock
);
input_split0_i : input_split0 port map (
ra0_data => sig_1095,
ra0_addr => mux_46,
ra1_data => sig_1094,
ra1_addr => mux_47,
ra2_data => sig_1093,
ra2_addr => mux_48,
ra3_data => sig_1092,
ra3_addr => mux_49,
clk => sig_clock,
wa2_data => mux_50,
wa2_addr => mux_51,
wa2_en => mux_52
);
add_194_i : add_194 port map (
result => sig_1091,
in_a => sig_1146,
in_b => sig_1145(31 downto 2)
);
add_205_i : add_205 port map (
result => sig_1090,
in_a => idct_z1_reg7,
in_b => idct_z1_reg5
);
add_254_i : add_254 port map (
result => sig_1089,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_276_i : add_276 port map (
result => sig_1088,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
sub_284_i : sub_284 port map (
result => sig_1087,
in_a => sig_1115,
in_b => sig_1174
);
input_split1_i : input_split1 port map (
wa0_data => mux_39,
wa0_addr => mux_40,
ra0_data => sig_1086,
ra0_addr => mux_41,
wa0_en => mux_42,
ra1_data => sig_1085,
ra1_addr => mux_43,
ra2_data => sig_1084,
ra2_addr => mux_44,
ra3_data => sig_1083,
ra3_addr => mux_45,
clk => sig_clock
);
add_166_i : add_166 port map (
result => sig_1082,
in_a => sig_1173,
in_b => "00000000000000000001"
);
add_168_i : add_168 port map (
result => sig_1081,
in_a => sig_1172,
in_b => "00000000000000000001"
);
add_178_i : add_178 port map (
result => sig_1080,
in_a => sig_1171,
in_b => "00000000000000000001"
);
add_183_i : add_183 port map (
result => sig_1079,
in_a => idct_z2_reg2,
in_b => idct_z3_reg5
);
sub_332_i : sub_332 port map (
result => sig_1078,
in_a => sig_689,
in_b => sig_688
);
mul_341_i : mul_341 port map (
result => sig_1077,
in_a => or_339,
in_b => "0101001110011111"
);
mul_357_i : mul_357 port map (
result => sig_1076,
in_a => or_355,
in_b => "010110101000001"
);
mul_365_i : mul_365 port map (
result => sig_1075,
in_a => or_363,
in_b => "010001010100011"
);
mul_368_i : mul_368 port map (
result => sig_1074,
in_a => or_366,
in_b => "0101001110011111"
);
sub_369_i : sub_369 port map (
result => sig_1073,
in_a => sig_1075,
in_b => sig_1074
);
sub_370_i : sub_370 port map (
result => sig_1072,
in_a => sig_1115,
in_b => sig_1170
);
sub_377_i : sub_377 port map (
result => sig_1071,
in_a => sig_680,
in_b => sig_715
);
cmp_398_i : cmp_398 port map (
eq => sig_1070,
in0 => "110",
in1 => augh_main_k(2 downto 0)
);
cmp_400_i : cmp_400 port map (
eq => sig_1069,
in0 => "101",
in1 => augh_main_k(2 downto 0)
);
cmp_404_i : cmp_404 port map (
eq => sig_1068,
in0 => "011",
in1 => augh_main_k(2 downto 0)
);
cmp_406_i : cmp_406 port map (
eq => sig_1067,
in0 => "010",
in1 => augh_main_k(2 downto 0)
);
cmp_408_i : cmp_408 port map (
eq => sig_1066,
in0 => "001",
in1 => augh_main_k(2 downto 0)
);
cmp_410_i : cmp_410 port map (
eq => sig_1065,
in0 => "000",
in1 => augh_main_k(2 downto 0)
);
cmp_412_i : cmp_412 port map (
eq => sig_1064,
in0 => '0',
in1 => augh_main_k(0)
);
sub_429_i : sub_429 port map (
result => sig_1063,
in_a => or_421,
in_b => or_427
);
add_466_i : add_466 port map (
result => sig_1062,
in_a => or_462,
in_b => or_464
);
sub_496_i : sub_496 port map (
result => sig_1061,
in_a => sig_652,
in_b => sig_651
);
sub_521_i : sub_521 port map (
result => sig_1060,
in_a => or_438,
in_b => or_464
);
sub_528_i : sub_528 port map (
result => sig_1059,
in_a => sig_643,
in_b => sig_642
);
fsm_23_i : fsm_23 port map (
clock => sig_clock,
reset => sig_reset,
in0 => memextrct_loop_sig_21,
out181 => sig_1058,
out182 => sig_1057,
out183 => sig_1056,
out184 => sig_1055,
out185 => sig_1054,
out8 => sig_1053,
out13 => sig_1052,
out14 => sig_1051,
out16 => sig_1050,
out18 => sig_1049,
out19 => sig_1048,
out20 => sig_1047,
out21 => sig_1046,
out22 => sig_1045,
in2 => sig_start,
out23 => sig_1044,
out24 => sig_1043,
out25 => sig_1042,
out26 => sig_1041,
out27 => sig_1040,
out28 => sig_1039,
out29 => sig_1038,
out30 => sig_1037,
out31 => sig_1036,
out33 => sig_1035,
out35 => sig_1034,
out36 => sig_1033,
out38 => sig_1032,
out40 => sig_1031,
out42 => sig_1030,
in3 => memextrct_loop_sig_22,
out44 => sig_1029,
out46 => sig_1028,
out48 => sig_1027,
out49 => sig_1026,
out50 => sig_1025,
out52 => sig_1024,
out54 => sig_1023,
out56 => sig_1022,
out57 => sig_1021,
out58 => sig_1020,
in4 => test_cp_0_16,
out60 => sig_1019,
in5 => test_cp_1_17,
out164 => sig_1018,
out165 => sig_1017,
out167 => sig_1016,
out168 => sig_1015,
out170 => sig_1014,
out171 => sig_1013,
out173 => sig_1012,
out174 => sig_1011,
out176 => sig_1010,
out178 => sig_1009,
out0 => sig_1008,
out1 => sig_1007,
out2 => sig_1006,
in1 => cp_rest,
out4 => sig_1005,
out90 => sig_1004,
out91 => sig_1003,
out97 => sig_1002,
out99 => sig_1001,
out101 => sig_1000,
in6 => stdout_ack,
out103 => sig_999,
out105 => sig_998,
out106 => sig_997,
out107 => sig_996,
out108 => sig_995,
out135 => sig_994,
out136 => sig_993,
out137 => sig_992,
out138 => sig_991,
in11 => augh_test_9,
out140 => sig_990,
out141 => sig_989,
out142 => sig_988,
out143 => sig_987,
out145 => sig_986,
out146 => sig_985,
out148 => sig_984,
out150 => sig_983,
out153 => sig_982,
out154 => sig_981,
out155 => sig_980,
out156 => sig_979,
out157 => sig_978,
out158 => sig_977,
out159 => sig_976,
out160 => sig_975,
out161 => sig_974,
out162 => sig_973,
out111 => sig_972,
out112 => sig_971,
out114 => sig_970,
out116 => sig_969,
out118 => sig_968,
out120 => sig_967,
out121 => sig_966,
out122 => sig_965,
out123 => sig_964,
out124 => sig_963,
out125 => sig_962,
out126 => sig_961,
in7 => cp_en,
out129 => sig_960,
out130 => sig_959,
in8 => stdin_ack,
out131 => sig_958,
in9 => psc_loop_sig_20,
out132 => sig_957,
out133 => sig_956,
out134 => sig_955,
in10 => augh_test_11,
out186 => sig_954,
out187 => sig_953,
out190 => sig_952,
out195 => sig_951,
out197 => sig_950,
out198 => sig_949,
out199 => sig_948,
out200 => sig_947,
out201 => sig_946,
out203 => sig_945,
out204 => sig_944,
out206 => sig_943,
out207 => sig_942,
out209 => sig_941,
out210 => sig_940,
out212 => sig_939,
out213 => sig_938,
out215 => sig_937,
out217 => sig_936,
out220 => sig_935,
out221 => sig_934,
out222 => sig_933,
out223 => sig_932,
out224 => sig_931,
out225 => sig_930,
out226 => sig_929,
out227 => sig_928,
out228 => sig_927,
out229 => sig_926,
out231 => sig_925,
out232 => sig_924,
out234 => sig_923,
out235 => sig_922,
out237 => sig_921,
out238 => sig_920,
out240 => sig_919,
out241 => sig_918,
out243 => sig_917,
out245 => sig_916,
out248 => sig_915,
out249 => sig_914,
out250 => sig_913,
out251 => sig_912,
out252 => sig_911,
out253 => sig_910,
out254 => sig_909,
out255 => sig_908,
out256 => sig_907,
out257 => sig_906,
out259 => sig_905,
out260 => sig_904,
out262 => sig_903,
out263 => sig_902,
out265 => sig_901,
out266 => sig_900,
out268 => sig_899,
out269 => sig_898,
out271 => sig_897,
out273 => sig_896,
out276 => sig_895,
out277 => sig_894,
out278 => sig_893,
out279 => sig_892,
out280 => sig_891,
out281 => sig_890,
out282 => sig_889,
out283 => sig_888,
out284 => sig_887,
out285 => sig_886,
out286 => sig_885,
out287 => sig_884,
out288 => sig_883,
out289 => sig_882,
out290 => sig_881,
out291 => sig_880,
out292 => sig_879,
out293 => sig_878,
out294 => sig_877,
out295 => sig_876,
out296 => sig_875,
out297 => sig_874,
out298 => sig_873,
out311 => sig_872,
out312 => sig_871,
out313 => sig_870,
out314 => sig_869,
out315 => sig_868,
out316 => sig_867,
out318 => sig_866,
out321 => sig_865,
out322 => sig_864,
out323 => sig_863,
out324 => sig_862,
out325 => sig_861,
out326 => sig_860,
out327 => sig_859,
out328 => sig_858,
out329 => sig_857,
out333 => sig_856,
out341 => sig_855,
out342 => sig_854,
out343 => sig_853,
out344 => sig_852,
out345 => sig_851,
out346 => sig_850,
out349 => sig_849,
out350 => sig_848,
out351 => sig_847,
out352 => sig_846,
out353 => sig_845,
out354 => sig_844,
out355 => sig_843,
out357 => sig_842,
out361 => sig_841,
out362 => sig_840,
out363 => sig_839,
out364 => sig_838,
out366 => sig_837,
out367 => sig_836,
out371 => sig_835,
out372 => sig_834,
out373 => sig_833,
out382 => sig_832,
out383 => sig_831,
out385 => sig_830,
out393 => sig_829,
out394 => sig_828,
out395 => sig_827,
out396 => sig_826,
out398 => sig_825,
out400 => sig_824,
out401 => sig_823,
out402 => sig_822,
out404 => sig_821,
out406 => sig_820,
out407 => sig_819,
out408 => sig_818,
out409 => sig_817,
out410 => sig_816,
out411 => sig_815,
out412 => sig_814,
out413 => sig_813,
out414 => sig_812,
out416 => sig_811,
out417 => sig_810,
out418 => sig_809,
out419 => sig_808,
out422 => sig_807,
out423 => sig_806,
out425 => sig_805,
out426 => sig_804,
out428 => sig_803,
out429 => sig_802,
out430 => sig_801,
out431 => sig_800,
out433 => sig_799,
out434 => sig_798,
out435 => sig_797,
out436 => sig_796,
out437 => sig_795,
out438 => sig_794,
out440 => sig_793,
out441 => sig_792,
out443 => sig_791,
out444 => sig_790,
out445 => sig_789,
out446 => sig_788,
out447 => sig_787,
out450 => sig_786,
out451 => sig_785,
out454 => sig_784,
out455 => sig_783,
out457 => sig_782,
out458 => sig_781,
out459 => sig_780,
out460 => sig_779,
out461 => sig_778,
out462 => sig_777,
out463 => sig_776,
out464 => sig_775,
out465 => sig_774,
out466 => sig_773,
out467 => sig_772,
out468 => sig_771,
out469 => sig_770,
out472 => sig_769,
out475 => sig_768,
out481 => sig_767,
out482 => sig_766,
out483 => sig_765,
out484 => sig_764,
out487 => sig_763,
out488 => sig_762,
out491 => sig_761,
out495 => sig_760,
out496 => sig_759,
out497 => sig_758,
out498 => sig_757,
out499 => sig_756,
out500 => sig_755,
out501 => sig_754,
out512 => sig_753,
out513 => sig_752,
out517 => sig_751,
out518 => sig_750,
out519 => sig_749,
out521 => sig_748,
out522 => sig_747,
out524 => sig_746,
out525 => sig_745,
out526 => sig_744,
out527 => sig_743,
out528 => sig_742,
out531 => sig_741,
out540 => sig_740,
out542 => sig_739,
out544 => sig_738,
out545 => sig_737,
out554 => sig_736,
out555 => sig_735,
out559 => sig_734,
out560 => sig_733,
out561 => sig_732,
out562 => sig_731,
out563 => sig_730,
out566 => sig_729,
out567 => sig_728,
out570 => sig_727,
out572 => sig_726,
out575 => sig_725,
out577 => sig_724,
out578 => sig_723,
out580 => sig_722,
out581 => sig_721
);
add_167_i : add_167 port map (
result => sig_720,
in_a => idct_2d_yc_reg6(31 downto 5),
in_b => "000000000000000000000000001"
);
add_169_i : add_169 port map (
result => sig_719,
in_a => idct_2d_yc_reg5(31 downto 5),
in_b => "000000000000000000000000001"
);
add_175_i : add_175 port map (
result => sig_718,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_255_i : add_255 port map (
result => sig_717,
in_a => sig_1169,
in_b => "00000000000000000001"
);
sub_362_i : sub_362 port map (
result => sig_716,
in_a => or_358,
in_b => or_360
);
mul_376_i : mul_376 port map (
result => sig_715,
in_a => or_374,
in_b => "010001010100011"
);
add_420_i : add_420 port map (
result => sig_714,
in_a => sig_1168,
in_b => "00000000000000000001"
);
sub_446_i : sub_446 port map (
result => sig_713,
in_a => sig_667,
in_b => sig_666
);
mul_456_i : mul_456 port map (
result => sig_712,
in_a => or_454,
in_b => "010110101000001"
);
mul_457_i : mul_457 port map (
result => sig_711,
in_a => or_450,
in_b => "0101001110011111"
);
sub_461_i : sub_461 port map (
result => sig_710,
in_a => sig_711,
in_b => sig_662
);
sub_517_i : sub_517 port map (
result => sig_709,
in_a => or_512,
in_b => or_514
);
mul_560_i : mul_560 port map (
result => sig_708,
in_a => or_435,
in_b => "010001010100011"
);
mul_565_i : mul_565 port map (
result => sig_707,
in_a => or_363,
in_b => "0101001110011111"
);
mul_578_i : mul_578 port map (
result => sig_706,
in_a => or_431,
in_b => "010001010100011"
);
muxb_162_i : muxb_162 port map (
in_sel => cp_en,
out_data => sig_705,
in_data0 => '0',
in_data1 => '1'
);
add_184_i : add_184 port map (
result => sig_704,
in_a => idct_z2_reg3,
in_b => idct_z3_reg4
);
muxb_201_i : muxb_201 port map (
in_sel => cp_en,
out_data => sig_703,
in_data0 => '0',
in_data1 => '1'
);
cmp_202_i : cmp_202 port map (
ne => memextrct_loop_sig_22,
in0 => "0000000000000111",
in1 => psc_loop_reg_13
);
cmp_203_i : cmp_203 port map (
eq => test_cp_1_17,
in0 => '1',
in1 => cp_id_reg_stable_15
);
cmp_204_i : cmp_204 port map (
eq => sig_702,
in0 => '0',
in1 => cp_id_reg_stable_15
);
sub_208_i : sub_208 port map (
result => sig_701,
in_a => idct_z1_reg4,
in_b => idct_z1_reg6
);
add_236_i : add_236 port map (
result => sig_700,
in_a => sig_1167,
in_b => "00000000000000000001"
);
muxb_263_i : muxb_263 port map (
in_sel => not_264,
out_data => sig_699,
in_data0 => '0',
in_data1 => '1'
);
muxb_265_i : muxb_265 port map (
in_sel => not_264,
out_data => sig_698,
in_data0 => '0',
in_data1 => '1'
);
add_277_i : add_277 port map (
result => sig_697,
in_a => sig_1166,
in_b => "00000000000000000001"
);
add_295_i : add_295 port map (
result => sig_696,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_296_i : add_296 port map (
result => sig_695,
in_a => sig_1165,
in_b => "00000000000000000001"
);
sub_303_i : sub_303 port map (
result => sig_694,
in_a => sig_1115,
in_b => sig_1164
);
add_315_i : add_315 port map (
result => sig_693,
in_a => sig_1163,
in_b => "00000000000000000001"
);
muxb_322_i : muxb_322 port map (
in_sel => cp_en,
out_data => sig_692,
in_data0 => '0',
in_data1 => '1'
);
add_323_i : add_323 port map (
result => sig_691,
in_a => psc_loop_reg_13,
in_b => "0000000000000001"
);
cmp_324_i : cmp_324 port map (
ne => psc_loop_sig_20,
in0 => "0000000000000001",
in1 => psc_loop_reg_13
);
cmp_325_i : cmp_325 port map (
eq => sig_690,
in0 => '0',
in1 => cp_id_reg_stable_15
);
mul_328_i : mul_328 port map (
result => sig_689,
in_a => or_326,
in_b => "010001010100011"
);
mul_331_i : mul_331 port map (
result => sig_688,
in_a => or_329,
in_b => "0101001110011111"
);
sub_337_i : sub_337 port map (
result => sig_687,
in_a => or_333,
in_b => or_335
);
add_338_i : add_338 port map (
result => sig_686,
in_a => or_333,
in_b => or_297
);
mul_344_i : mul_344 port map (
result => sig_685,
in_a => or_342,
in_b => "010001010100011"
);
sub_345_i : sub_345 port map (
result => sig_684,
in_a => sig_1077,
in_b => sig_685
);
add_350_i : add_350 port map (
result => sig_683,
in_a => or_346,
in_b => or_348
);
mul_353_i : mul_353 port map (
result => sig_682,
in_a => or_351,
in_b => "010110101000001"
);
sub_354_i : sub_354 port map (
result => sig_681,
in_a => or_346,
in_b => or_348
);
mul_373_i : mul_373 port map (
result => sig_680,
in_a => or_371,
in_b => "0101001110011111"
);
add_382_i : add_382 port map (
result => sig_679,
in_a => or_378,
in_b => or_380
);
mul_383_i : mul_383 port map (
result => sig_678,
in_a => idct_2d_yc_reg3(30 downto 0),
in_b => "010110101000001"
);
add_390_i : add_390 port map (
result => sig_677,
in_a => or_386,
in_b => or_388
);
sub_391_i : sub_391 port map (
result => sig_676,
in_a => or_386,
in_b => or_388
);
cmp_392_i : cmp_392 port map (
ne => augh_test_11,
in0 => "00000000000000000000000000111111",
in1 => augh_main_k
);
add_393_i : add_393 port map (
result => sig_675,
in_a => augh_main_k,
in_b => "00000000000000000000000000000001"
);
cmp_396_i : cmp_396 port map (
eq => sig_674,
in0 => "111",
in1 => augh_main_k(2 downto 0)
);
cmp_402_i : cmp_402 port map (
eq => sig_673,
in0 => "100",
in1 => augh_main_k(2 downto 0)
);
cmp_411_i : cmp_411 port map (
eq => sig_672,
in0 => '1',
in1 => augh_main_k(0)
);
cmp_413_i : cmp_413 port map (
ne => augh_test_9,
in0 => "00000000000000000000000000111111",
in1 => augh_main_k
);
mul_416_i : mul_416 port map (
result => sig_671,
in_a => or_414,
in_b => "010110101000001"
);
add_419_i : add_419 port map (
result => sig_670,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_430_i : add_430 port map (
result => sig_669,
in_a => or_421,
in_b => or_427
);
sub_437_i : sub_437 port map (
result => sig_668,
in_a => sig_1115,
in_b => sig_1162
);
mul_442_i : mul_442 port map (
result => sig_667,
in_a => or_440,
in_b => "0101001110011111"
);
mul_445_i : mul_445 port map (
result => sig_666,
in_a => or_443,
in_b => "010001010100011"
);
mul_447_i : mul_447 port map (
result => sig_665,
in_a => or_440,
in_b => "010001010100011"
);
mul_448_i : mul_448 port map (
result => sig_664,
in_a => or_443,
in_b => "0101001110011111"
);
sub_449_i : sub_449 port map (
result => sig_663,
in_a => sig_665,
in_b => sig_664
);
mul_460_i : mul_460 port map (
result => sig_662,
in_a => or_458,
in_b => "010001010100011"
);
mul_469_i : mul_469 port map (
result => sig_661,
in_a => or_467,
in_b => "010110101000001"
);
add_474_i : add_474 port map (
result => sig_660,
in_a => or_470,
in_b => or_472
);
mul_477_i : mul_477 port map (
result => sig_659,
in_a => or_475,
in_b => "010110101000001"
);
sub_478_i : sub_478 port map (
result => sig_658,
in_a => or_470,
in_b => or_472
);
add_483_i : add_483 port map (
result => sig_657,
in_a => or_479,
in_b => or_481
);
sub_484_i : sub_484 port map (
result => sig_656,
in_a => or_479,
in_b => or_481
);
add_487_i : add_487 port map (
result => sig_655,
in_a => or_425,
in_b => or_485
);
sub_488_i : sub_488 port map (
result => sig_654,
in_a => or_425,
in_b => or_485
);
sub_489_i : sub_489 port map (
result => sig_653,
in_a => or_378,
in_b => or_285
);
mul_492_i : mul_492 port map (
result => sig_652,
in_a => or_490,
in_b => "010001010100011"
);
mul_495_i : mul_495 port map (
result => sig_651,
in_a => or_493,
in_b => "0101001110011111"
);
mul_499_i : mul_499 port map (
result => sig_650,
in_a => or_435,
in_b => "0101001110011111"
);
mul_502_i : mul_502 port map (
result => sig_649,
in_a => or_500,
in_b => "010001010100011"
);
sub_503_i : sub_503 port map (
result => sig_648,
in_a => sig_650,
in_b => sig_649
);
add_508_i : add_508 port map (
result => sig_647,
in_a => or_504,
in_b => or_506
);
mul_511_i : mul_511 port map (
result => sig_646,
in_a => or_509,
in_b => "010110101000001"
);
add_516_i : add_516 port map (
result => sig_645,
in_a => or_512,
in_b => or_514
);
mul_520_i : mul_520 port map (
result => sig_644,
in_a => or_518,
in_b => "010110101000001"
);
mul_524_i : mul_524 port map (
result => sig_643,
in_a => or_522,
in_b => "010001010100011"
);
mul_527_i : mul_527 port map (
result => sig_642,
in_a => or_525,
in_b => "0101001110011111"
);
mul_531_i : mul_531 port map (
result => sig_641,
in_a => or_529,
in_b => "010110101000001"
);
mul_534_i : mul_534 port map (
result => sig_640,
in_a => or_532,
in_b => "010110101000001"
);
add_537_i : add_537 port map (
result => sig_639,
in_a => or_497,
in_b => or_535
);
mul_540_i : mul_540 port map (
result => sig_638,
in_a => or_538,
in_b => "0101001110011111"
);
mul_543_i : mul_543 port map (
result => sig_637,
in_a => or_541,
in_b => "010001010100011"
);
sub_544_i : sub_544 port map (
result => sig_636,
in_a => sig_638,
in_b => sig_637
);
mul_547_i : mul_547 port map (
result => sig_635,
in_a => or_545,
in_b => "010110101000001"
);
add_552_i : add_552 port map (
result => sig_634,
in_a => or_548,
in_b => or_550
);
sub_553_i : sub_553 port map (
result => sig_633,
in_a => or_548,
in_b => or_550
);
mul_556_i : mul_556 port map (
result => sig_632,
in_a => or_554,
in_b => "010110101000001"
);
mul_559_i : mul_559 port map (
result => sig_631,
in_a => or_557,
in_b => "010110101000001"
);
mul_561_i : mul_561 port map (
result => sig_630,
in_a => or_500,
in_b => "0101001110011111"
);
sub_562_i : sub_562 port map (
result => sig_629,
in_a => sig_708,
in_b => sig_630
);
sub_563_i : sub_563 port map (
result => sig_628,
in_a => or_504,
in_b => or_506
);
add_564_i : add_564 port map (
result => sig_627,
in_a => or_358,
in_b => or_360
);
mul_566_i : mul_566 port map (
result => sig_626,
in_a => or_366,
in_b => "010001010100011"
);
sub_567_i : sub_567 port map (
result => sig_625,
in_a => sig_707,
in_b => sig_626
);
add_570_i : add_570 port map (
result => sig_624,
in_a => or_417,
in_b => or_568
);
mul_573_i : mul_573 port map (
result => sig_623,
in_a => or_571,
in_b => "010110101000001"
);
sub_574_i : sub_574 port map (
result => sig_622,
in_a => or_417,
in_b => or_568
);
mul_577_i : mul_577 port map (
result => sig_621,
in_a => or_575,
in_b => "010110101000001"
);
mul_579_i : mul_579 port map (
result => sig_620,
in_a => or_541,
in_b => "0101001110011111"
);
sub_580_i : sub_580 port map (
result => sig_619,
in_a => sig_706,
in_b => sig_620
);
sub_585_i : sub_585 port map (
result => sig_618,
in_a => or_581,
in_b => or_583
);
sub_586_i : sub_586 port map (
result => sig_617,
in_a => sig_1115,
in_b => sig_1161
);
mul_589_i : mul_589 port map (
result => sig_616,
in_a => or_587,
in_b => "0101001110011111"
);
mul_592_i : mul_592 port map (
result => sig_615,
in_a => or_590,
in_b => "010001010100011"
);
sub_593_i : sub_593 port map (
result => sig_614,
in_a => sig_616,
in_b => sig_615
);
mul_594_i : mul_594 port map (
result => sig_613,
in_a => or_587,
in_b => "010001010100011"
);
mul_595_i : mul_595 port map (
result => sig_612,
in_a => or_590,
in_b => "0101001110011111"
);
sub_596_i : sub_596 port map (
result => sig_611,
in_a => sig_613,
in_b => sig_612
);
sub_599_i : sub_599 port map (
result => sig_610,
in_a => or_423,
in_b => or_597
);
add_600_i : add_600 port map (
result => sig_609,
in_a => or_423,
in_b => or_597
);
add_601_i : add_601 port map (
result => sig_608,
in_a => idct_2d_yc_reg2(31 downto 5),
in_b => "000000000000000000000000001"
);
add_602_i : add_602 port map (
result => sig_607,
in_a => sig_1160,
in_b => "00000000000000000001"
);
mul_605_i : mul_605 port map (
result => sig_606,
in_a => or_603,
in_b => "010110101000001"
);
-- Behaviour of component 'mux_66' model 'mux'
mux_66 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_947) and "110") or
(repeat(3, sig_945) and "101") or
(repeat(3, sig_943) and "100") or
(repeat(3, sig_941) and "011") or
(repeat(3, sig_949) and "111") or
(repeat(3, sig_939) and "010") or
(repeat(3, sig_937) and "001");
-- Behaviour of component 'mux_30' model 'mux'
mux_30 <=
(sig_873 and cp_en);
-- Behaviour of component 'mux_32' model 'mux'
mux_32 <=
(sig_1002 and sig_702) or
(sig_872 and sig_690);
-- Behaviour of component 'mux_33' model 'mux'
mux_33 <=
(sig_1039 and cp_din(0)) or
(sig_954 and '1');
-- Behaviour of component 'mux_34' model 'mux'
mux_34 <=
(sig_1038 and cp_rest) or
(sig_953 and '1');
-- Behaviour of component 'mux_58' model 'mux'
mux_58 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_966) and "110") or
(repeat(3, sig_957) and "101") or
(repeat(3, sig_956) and "100") or
(repeat(3, sig_990) and "011") or
(repeat(3, sig_996) and "111") or
(repeat(3, sig_986) and "010") or
(repeat(3, sig_984) and "001");
-- Behaviour of component 'mux_59' model 'mux'
mux_59 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_60' model 'mux'
mux_60 <=
(sig_1004 and and_161) or
(sig_995 and '1');
-- Behaviour of component 'mux_61' model 'mux'
mux_61 <=
(repeat(8, sig_1003) and cp_din(23 downto 16)) or
(repeat(8, sig_977) and mux_156);
-- Behaviour of component 'mux_62' model 'mux'
mux_62 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_974) and "110") or
(repeat(3, sig_1018) and "101") or
(repeat(3, sig_1016) and "100") or
(repeat(3, sig_1014) and "011") or
(repeat(3, sig_976) and "111") or
(repeat(3, sig_1012) and "010") or
(repeat(3, sig_1010) and "001");
-- Behaviour of component 'mux_63' model 'mux'
mux_63 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_64' model 'mux'
mux_64 <=
(sig_1004 and and_161) or
(sig_975 and '1');
-- Behaviour of component 'mux_65' model 'mux'
mux_65 <=
(repeat(8, sig_1003) and cp_din(31 downto 24)) or
(repeat(8, sig_950) and mux_156);
-- Behaviour of component 'mux_35' model 'mux'
mux_35 <=
(sig_954 and '1') or
(sig_874 and augh_main_k(0));
-- Behaviour of component 'mux_36' model 'mux'
mux_36 <=
(sig_953 and '1') or
(sig_873 and cp_en);
-- Behaviour of component 'mux_37' model 'mux'
mux_37 <=
(repeat(16, sig_1052) and sig_1128) or
(repeat(16, sig_874) and sig_691);
-- Behaviour of component 'mux_38' model 'mux'
mux_38 <=
(sig_1051 and cp_en) or
(sig_1049 and '1');
-- Behaviour of component 'mux_39' model 'mux'
mux_39 <=
(repeat(32, sig_1005) and cp_din(31 downto 0)) or
(repeat(32, sig_884) and sig_704) or
(repeat(32, sig_880) and sig_1124) or
(repeat(32, sig_862) and sig_1103) or
(repeat(32, sig_859) and sig_1102) or
(repeat(32, sig_887) and (sig_1084(28 downto 0) & "000")) or
(repeat(32, sig_831) and read32_ret0_10) or
(repeat(32, sig_733) and (sig_1085(28 downto 0) & "000"));
-- Behaviour of component 'mux_45' model 'mux'
mux_45 <=
(repeat(5, sig_857) and "01101") or
(repeat(5, sig_754) and "11011") or
(repeat(5, sig_742) and "10111") or
(repeat(5, sig_737) and "10001") or
(repeat(5, sig_770) and "11111");
-- Behaviour of component 'mux_46' model 'mux'
mux_46 <=
(repeat(5, sig_867) and "01010") or
(repeat(5, sig_852) and "01111") or
(repeat(5, sig_843) and "11110") or
(repeat(5, sig_769) and "11010") or
(repeat(5, sig_761) and "11111") or
(repeat(5, sig_857) and "01011") or
(repeat(5, sig_755) and "10110") or
(repeat(5, sig_741) and "10011");
-- Behaviour of component 'mux_47' model 'mux'
mux_47 <=
(repeat(5, sig_867) and "01011") or
(repeat(5, sig_852) and "01110") or
(repeat(5, sig_843) and "11111") or
(repeat(5, sig_788) and "00001") or
(repeat(5, sig_770) and "11011") or
(repeat(5, sig_730) and "00111") or
(repeat(5, sig_857) and "01001") or
(repeat(5, sig_764) and "00110") or
(repeat(5, sig_742) and "10010") or
(repeat(5, sig_735) and "10000") or
(repeat(5, sig_762) and "00010") or
(repeat(5, sig_761) and "11101") or
(repeat(5, sig_755) and "10111") or
(repeat(5, sig_752) and "11001");
-- Behaviour of component 'mux_48' model 'mux'
mux_48 <=
(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
(repeat(5, sig_865) and "01101") or
(repeat(5, sig_844) and "11101") or
(repeat(5, sig_823) and "11000") or
(repeat(5, sig_818) and "10100") or
(repeat(5, sig_810) and "00100") or
(repeat(5, sig_804) and "10001") or
(repeat(5, sig_797) and "10101") or
(repeat(5, sig_785) and "11001") or
(repeat(5, sig_758) and "10000") or
(repeat(5, sig_731) and "00101") or
(repeat(5, sig_1017) and "11011") or
(repeat(5, sig_1015) and "10111") or
(repeat(5, sig_1013) and "10011") or
(repeat(5, sig_1011) and "01111") or
(repeat(5, sig_918) and "01110") or
(repeat(5, sig_916) and "01010") or
(repeat(5, sig_915) and "00110") or
(repeat(5, sig_973) and "11111") or
(repeat(5, sig_913) and "00010") or
(repeat(5, sig_891) and "01001") or
(repeat(5, sig_871) and "01100") or
(repeat(5, sig_1009) and "01011") or
(repeat(5, sig_922) and "10110") or
(repeat(5, sig_920) and "10010") or
(repeat(5, sig_1058) and "00111") or
(repeat(5, sig_1056) and "00011") or
(repeat(5, sig_926) and "11110") or
(repeat(5, sig_924) and "11010");
-- Behaviour of component 'mux_49' model 'mux'
mux_49 <=
(repeat(5, sig_866) and "01000") or
(repeat(5, sig_842) and "11100") or
(repeat(5, sig_787) and "00011") or
(repeat(5, sig_770) and "11000") or
(repeat(5, sig_755) and "10100") or
(repeat(5, sig_850) and "01101") or
(repeat(5, sig_752) and "11011") or
(repeat(5, sig_742) and "10001") or
(repeat(5, sig_735) and "10010");
-- Behaviour of component 'mux_40' model 'mux'
mux_40 <=
(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
(repeat(5, sig_794) and "11000") or
(repeat(5, sig_782) and "10100") or
(repeat(5, sig_781) and "11100") or
(repeat(5, sig_780) and "11110") or
(repeat(5, sig_776) and "11001") or
(repeat(5, sig_773) and "01001") or
(repeat(5, sig_771) and "10011") or
(repeat(5, sig_763) and "10001") or
(repeat(5, sig_760) and "11010") or
(repeat(5, sig_759) and "10101") or
(repeat(5, sig_751) and "10110") or
(repeat(5, sig_750) and "00111") or
(repeat(5, sig_748) and "01011") or
(repeat(5, sig_744) and "01110") or
(repeat(5, sig_736) and "01100") or
(repeat(5, sig_883) and "00101") or
(repeat(5, sig_879) and "00010") or
(repeat(5, sig_875) and "00110") or
(repeat(5, sig_863) and "01010") or
(repeat(5, sig_828) and "10000") or
(repeat(5, sig_827) and "01111") or
(repeat(5, sig_886) and "01101") or
(repeat(5, sig_824) and "11011") or
(repeat(5, sig_807) and "00001") or
(repeat(5, sig_803) and "11111") or
(repeat(5, sig_861) and "00100") or
(repeat(5, sig_845) and "10111") or
(repeat(5, sig_831) and augh_main_k(5 downto 1)) or
(repeat(5, sig_860) and "10010") or
(repeat(5, sig_858) and "00011") or
(repeat(5, sig_854) and "01000") or
(repeat(5, sig_849) and "11101");
-- Behaviour of component 'mux_41' model 'mux'
mux_41 <=
(repeat(5, sig_857) and "01110") or
(repeat(5, sig_754) and "11010") or
(repeat(5, sig_742) and "10110") or
(repeat(5, sig_737) and "10010") or
(repeat(5, sig_770) and "11110");
-- Behaviour of component 'mux_42' model 'mux'
mux_42 <=
(sig_1053 and and_161) or
(sig_830 and sig_672) or
(sig_885 and '1');
-- Behaviour of component 'mux_43' model 'mux'
mux_43 <=
(repeat(5, sig_857) and "01111") or
(repeat(5, sig_826) and "00001") or
(repeat(5, sig_808) and "01011") or
(repeat(5, sig_768) and "11100") or
(repeat(5, sig_754) and "11000") or
(repeat(5, sig_836) and "00111") or
(repeat(5, sig_749) and "00101") or
(repeat(5, sig_728) and "00011") or
(repeat(5, sig_747) and "00110") or
(repeat(5, sig_742) and "10100") or
(repeat(5, sig_740) and "00010") or
(repeat(5, sig_737) and "10011");
-- Behaviour of component 'mux_44' model 'mux'
mux_44 <=
(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
(repeat(5, sig_902) and "10101") or
(repeat(5, sig_900) and "10001") or
(repeat(5, sig_898) and "01101") or
(repeat(5, sig_896) and "01001") or
(repeat(5, sig_895) and "00101") or
(repeat(5, sig_893) and "00001") or
(repeat(5, sig_856) and "01100") or
(repeat(5, sig_838) and "10100") or
(repeat(5, sig_837) and "00100") or
(repeat(5, sig_829) and "10000") or
(repeat(5, sig_821) and "01000") or
(repeat(5, sig_800) and "11000") or
(repeat(5, sig_958) and "11011") or
(repeat(5, sig_991) and "10111") or
(repeat(5, sig_987) and "10011") or
(repeat(5, sig_985) and "01111") or
(repeat(5, sig_938) and "01110") or
(repeat(5, sig_936) and "01010") or
(repeat(5, sig_935) and "00110") or
(repeat(5, sig_961) and "11111") or
(repeat(5, sig_933) and "00010") or
(repeat(5, sig_906) and "11101") or
(repeat(5, sig_904) and "11001") or
(repeat(5, sig_983) and "01011") or
(repeat(5, sig_942) and "10110") or
(repeat(5, sig_940) and "10010") or
(repeat(5, sig_982) and "00111") or
(repeat(5, sig_980) and "00011") or
(repeat(5, sig_946) and "11110") or
(repeat(5, sig_944) and "11010");
-- Behaviour of component 'mux_50' model 'mux'
mux_50 <=
(repeat(32, sig_1005) and cp_din(63 downto 32)) or
(repeat(32, sig_882) and sig_1111) or
(repeat(32, sig_877) and sig_1079) or
(repeat(32, sig_869) and sig_1149) or
(repeat(32, sig_847) and sig_1150) or
(repeat(32, sig_890) and (sig_1093(28 downto 0) & "000")) or
(repeat(32, sig_831) and read32_ret0_10) or
(repeat(32, sig_777) and (sig_1094(28 downto 0) & "000")) or
(repeat(32, sig_766) and (sig_1092(28 downto 0) & "000"));
-- Behaviour of component 'mux_51' model 'mux'
mux_51 <=
(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
(repeat(5, sig_796) and "10101") or
(repeat(5, sig_795) and "10110") or
(repeat(5, sig_793) and "11111") or
(repeat(5, sig_790) and "11101") or
(repeat(5, sig_779) and "11010") or
(repeat(5, sig_778) and "01011") or
(repeat(5, sig_775) and "11001") or
(repeat(5, sig_767) and "11100") or
(repeat(5, sig_765) and "01000") or
(repeat(5, sig_756) and "10000") or
(repeat(5, sig_753) and "10011") or
(repeat(5, sig_746) and "10010") or
(repeat(5, sig_745) and "01010") or
(repeat(5, sig_729) and "11110") or
(repeat(5, sig_881) and "00110") or
(repeat(5, sig_878) and "01111") or
(repeat(5, sig_876) and "00101") or
(repeat(5, sig_870) and "01100") or
(repeat(5, sig_817) and "10100") or
(repeat(5, sig_813) and "00010") or
(repeat(5, sig_812) and "00001") or
(repeat(5, sig_889) and "01001") or
(repeat(5, sig_809) and "00100") or
(repeat(5, sig_799) and "10001") or
(repeat(5, sig_798) and "11011") or
(repeat(5, sig_868) and "00011") or
(repeat(5, sig_831) and augh_main_k(5 downto 1)) or
(repeat(5, sig_819) and "10111") or
(repeat(5, sig_864) and "01101") or
(repeat(5, sig_855) and "01110") or
(repeat(5, sig_853) and "00111") or
(repeat(5, sig_846) and "11000");
-- Behaviour of component 'mux_52' model 'mux'
mux_52 <=
(sig_1053 and and_161) or
(sig_830 and sig_1064) or
(sig_888 and '1');
-- Behaviour of component 'mux_53' model 'mux'
mux_53 <=
(repeat(8, sig_1008) and mux_156) or
(repeat(8, sig_1003) and cp_din(7 downto 0));
-- Behaviour of component 'mux_54' model 'mux'
mux_54 <=
(repeat(3, sig_1007) and "111") or
(repeat(3, sig_1045) and "101") or
(repeat(3, sig_1043) and "100") or
(repeat(3, sig_1041) and "011") or
(repeat(3, sig_1037) and "010") or
(repeat(3, sig_1048) and "110") or
(repeat(3, sig_1035) and "001") or
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0));
-- Behaviour of component 'mux_55' model 'mux'
mux_55 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_56' model 'mux'
mux_56 <=
(sig_1006 and '1') or
(sig_1004 and and_161);
-- Behaviour of component 'mux_57' model 'mux'
mux_57 <=
(repeat(8, sig_1003) and cp_din(15 downto 8)) or
(repeat(8, sig_997) and mux_156);
-- Behaviour of component 'mux_88' model 'mux'
mux_88 <=
(sig_1004 and and_161) or
(sig_839 and '1');
-- Behaviour of component 'mux_67' model 'mux'
mux_67 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_68' model 'mux'
mux_68 <=
(sig_1004 and and_161) or
(sig_948 and '1');
-- Behaviour of component 'mux_69' model 'mux'
mux_69 <=
(repeat(32, sig_1026) and sig_1102) or
(repeat(32, sig_974) and or_244) or
(repeat(32, sig_947) and or_266) or
(repeat(32, sig_927) and or_285) or
(repeat(32, sig_907) and or_304) or
(repeat(32, sig_966) and or_221) or
(repeat(32, sig_802) and or_378) or
(repeat(32, sig_727) and or_371) or
(repeat(32, sig_723) and or_470);
-- Behaviour of component 'mux_71' model 'mux'
mux_71 <=
(repeat(32, sig_1026) and sig_1149) or
(repeat(32, sig_1018) and or_246) or
(repeat(32, sig_945) and or_268) or
(repeat(32, sig_925) and or_287) or
(repeat(32, sig_905) and or_306) or
(repeat(32, sig_957) and or_224) or
(repeat(32, sig_801) and or_433) or
(repeat(32, sig_789) and or_438) or
(repeat(32, sig_786) and or_450);
-- Behaviour of component 'mux_73' model 'mux'
mux_73 <=
(repeat(32, sig_1026) and sig_1124) or
(repeat(32, sig_1016) and or_248) or
(repeat(32, sig_943) and or_270) or
(repeat(32, sig_923) and or_289) or
(repeat(32, sig_903) and or_308) or
(repeat(32, sig_956) and or_228) or
(repeat(32, sig_840) and or_384) or
(repeat(32, sig_792) and or_435) or
(repeat(32, sig_774) and or_452);
-- Behaviour of component 'mux_75' model 'mux'
mux_75 <=
(repeat(32, sig_1026) and sig_1111) or
(repeat(32, sig_1014) and or_250) or
(repeat(32, sig_941) and or_272) or
(repeat(32, sig_921) and or_291) or
(repeat(32, sig_901) and or_310) or
(repeat(32, sig_990) and or_231) or
(repeat(32, sig_825) and or_417) or
(repeat(32, sig_805) and or_431) or
(repeat(32, sig_757) and or_497);
-- Behaviour of component 'mux_77' model 'mux'
mux_77 <=
(repeat(32, sig_1026) and sig_704) or
(repeat(32, sig_1012) and or_252) or
(repeat(32, sig_939) and or_274) or
(repeat(32, sig_919) and or_293) or
(repeat(32, sig_899) and or_312) or
(repeat(32, sig_986) and or_233) or
(repeat(32, sig_806) and or_363) or
(repeat(32, sig_783) and or_346) or
(repeat(32, sig_743) and or_358);
-- Behaviour of component 'mux_79' model 'mux'
mux_79 <=
(repeat(32, sig_1026) and sig_1079) or
(repeat(32, sig_1010) and or_256) or
(repeat(32, sig_937) and or_278) or
(repeat(32, sig_917) and or_297) or
(repeat(32, sig_897) and or_316) or
(repeat(32, sig_984) and or_237) or
(repeat(32, sig_822) and or_421) or
(repeat(32, sig_738) and or_333) or
(repeat(32, sig_726) and or_326);
-- Behaviour of component 'mux_81' model 'mux'
mux_81 <=
(repeat(32, sig_1026) and sig_1103) or
(repeat(32, sig_1057) and or_258) or
(repeat(32, sig_934) and or_280) or
(repeat(32, sig_914) and or_299) or
(repeat(32, sig_894) and or_318) or
(repeat(32, sig_981) and or_239) or
(repeat(32, sig_784) and or_386) or
(repeat(32, sig_734) and or_479) or
(repeat(32, sig_724) and or_587);
-- Behaviour of component 'mux_83' model 'mux'
mux_83 <=
(repeat(32, sig_1026) and sig_1150) or
(repeat(32, sig_1055) and or_260) or
(repeat(32, sig_932) and or_282) or
(repeat(32, sig_912) and or_301) or
(repeat(32, sig_892) and or_320) or
(repeat(32, sig_979) and or_241) or
(repeat(32, sig_820) and or_423) or
(repeat(32, sig_811) and or_425) or
(repeat(32, sig_722) and or_440);
-- Behaviour of component 'mux_85' model 'mux'
mux_85 <=
(repeat(8, sig_1003) and cp_din(63 downto 56)) or
(repeat(8, sig_841) and mux_156);
-- Behaviour of component 'mux_86' model 'mux'
mux_86 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_825) and "011") or
(repeat(3, sig_822) and "001") or
(repeat(3, sig_801) and "101") or
(repeat(3, sig_840) and "100") or
(repeat(3, sig_783) and "010") or
(repeat(3, sig_725) and "111") or
(repeat(3, sig_723) and "110");
-- Behaviour of component 'mux_87' model 'mux'
mux_87 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_28' model 'mux'
mux_28 <=
(sig_873 and cp_en);
-- Behaviour of component 'mux_109' model 'mux'
mux_109 <=
(repeat(32, sig_972) and sig_1119) or
(repeat(32, sig_836) and sig_677) or
(repeat(32, sig_808) and sig_669) or
(repeat(32, sig_770) and sig_660) or
(repeat(32, sig_754) and sig_645) or
(repeat(32, sig_857) and sig_683) or
(repeat(32, sig_742) and sig_634) or
(repeat(32, sig_737) and sig_624) or
(repeat(32, sig_728) and sig_609);
-- Behaviour of component 'mux_154' model 'mux'
mux_154 <=
(sig_952 and sig_699);
-- Behaviour of component 'mux_156' model 'mux'
mux_156 <=
(repeat(8, sig_1130) and mux_158);
-- Behaviour of component 'mux_89' model 'mux'
mux_89 <=
(repeat(8, sig_1003) and cp_din(55 downto 48)) or
(repeat(8, sig_816) and mux_156);
-- Behaviour of component 'mux_90' model 'mux'
mux_90 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_806) and "010") or
(repeat(3, sig_805) and "011") or
(repeat(3, sig_792) and "100") or
(repeat(3, sig_786) and "101") or
(repeat(3, sig_815) and "111") or
(repeat(3, sig_727) and "110") or
(repeat(3, sig_726) and "001");
-- Behaviour of component 'mux_134' model 'mux'
mux_134 <=
(sig_873 and cp_en) or
(sig_832 and '1');
-- Behaviour of component 'mux_91' model 'mux'
mux_91 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_92' model 'mux'
mux_92 <=
(sig_1004 and and_161) or
(sig_814 and '1');
-- Behaviour of component 'mux_158' model 'mux'
mux_158 <=
(repeat(8, sig_1157) and "11111111") or
(repeat(8, sig_1106) and idct_2d_r(7 downto 0));
-- Behaviour of component 'mux_111' model 'mux'
mux_111 <=
(repeat(32, sig_960) and (sig_1132 & '0')) or
(repeat(32, sig_770) and (sig_659 & '0')) or
(repeat(32, sig_754) and (sig_644 & '0')) or
(repeat(32, sig_747) and (sig_640 & '0')) or
(repeat(32, sig_742) and (sig_632 & '0')) or
(repeat(32, sig_857) and (sig_1076 & '0')) or
(repeat(32, sig_740) and (sig_631 & '0')) or
(repeat(32, sig_737) and (sig_621 & '0')) or
(repeat(32, sig_721) and (sig_606 & '0'));
-- Behaviour of component 'mux_113' model 'mux'
mux_113 <=
(repeat(32, sig_989) and (sig_1112 & '0')) or
(repeat(32, sig_843) and (sig_678 & '0')) or
(repeat(32, sig_826) and (sig_671 & '0')) or
(repeat(32, sig_772) and (sig_712 & '0')) or
(repeat(32, sig_770) and (sig_661 & '0')) or
(repeat(32, sig_857) and (sig_682 & '0')) or
(repeat(32, sig_754) and (sig_646 & '0')) or
(repeat(32, sig_749) and (sig_641 & '0')) or
(repeat(32, sig_742) and (sig_635 & '0')) or
(repeat(32, sig_737) and (sig_623 & '0'));
-- Behaviour of component 'mux_115' model 'mux'
mux_115 <=
(repeat(32, sig_972) and sig_1142) or
(repeat(32, sig_836) and sig_676) or
(repeat(32, sig_808) and sig_1063) or
(repeat(32, sig_770) and sig_658) or
(repeat(32, sig_754) and sig_709) or
(repeat(32, sig_857) and sig_681) or
(repeat(32, sig_742) and sig_633) or
(repeat(32, sig_737) and sig_622) or
(repeat(32, sig_728) and sig_610);
-- Behaviour of component 'mux_117' model 'mux'
mux_117 <=
(repeat(32, sig_965) and sig_1136) or
(repeat(32, sig_843) and sig_1071) or
(repeat(32, sig_787) and sig_713) or
(repeat(32, sig_770) and sig_710) or
(repeat(32, sig_754) and sig_648) or
(repeat(32, sig_857) and sig_684) or
(repeat(32, sig_742) and sig_636) or
(repeat(32, sig_737) and sig_625) or
(repeat(32, sig_730) and sig_614);
-- Behaviour of component 'mux_119' model 'mux'
mux_119 <=
(repeat(32, sig_963) and sig_1133) or
(repeat(32, sig_851) and sig_1073) or
(repeat(32, sig_787) and sig_663) or
(repeat(32, sig_761) and sig_1061) or
(repeat(32, sig_752) and sig_1059) or
(repeat(32, sig_867) and sig_1078) or
(repeat(32, sig_739) and sig_629) or
(repeat(32, sig_735) and sig_619) or
(repeat(32, sig_730) and sig_611);
-- Behaviour of component 'mux_121' model 'mux'
mux_121 <=
(repeat(32, sig_993) and sig_1131) or
(repeat(32, sig_851) and sig_716) or
(repeat(32, sig_764) and sig_656) or
(repeat(32, sig_762) and sig_654) or
(repeat(32, sig_761) and sig_653) or
(repeat(32, sig_867) and sig_687) or
(repeat(32, sig_752) and sig_1060) or
(repeat(32, sig_739) and sig_628) or
(repeat(32, sig_735) and sig_618);
-- Behaviour of component 'mux_123' model 'mux'
mux_123 <=
(repeat(32, sig_955) and sig_1109) or
(repeat(32, sig_843) and sig_679) or
(repeat(32, sig_770) and sig_1062) or
(repeat(32, sig_764) and sig_657) or
(repeat(32, sig_762) and sig_655) or
(repeat(32, sig_857) and sig_686) or
(repeat(32, sig_754) and sig_647) or
(repeat(32, sig_742) and sig_639) or
(repeat(32, sig_737) and sig_627);
-- Behaviour of component 'or_224' model 'or'
or_224 <=
and_225;
-- Behaviour of component 'and_225' model 'and'
and_225 <=
sig_1084;
-- Behaviour of component 'or_231' model 'or'
or_231 <=
and_232;
-- Behaviour of component 'and_232' model 'and'
and_232 <=
sig_1084;
-- Behaviour of component 'or_250' model 'or'
or_250 <=
and_251;
-- Behaviour of component 'and_251' model 'and'
and_251 <=
sig_1093;
-- Behaviour of component 'or_260' model 'or'
or_260 <=
and_261;
-- Behaviour of component 'and_261' model 'and'
and_261 <=
sig_1093;
-- Behaviour of component 'or_282' model 'or'
or_282 <=
and_283;
-- Behaviour of component 'and_283' model 'and'
and_283 <=
sig_1084;
-- Behaviour of component 'or_285' model 'or'
or_285 <=
and_286;
-- Behaviour of component 'and_286' model 'and'
and_286 <=
sig_1093;
-- Behaviour of component 'or_289' model 'or'
or_289 <=
and_290;
-- Behaviour of component 'and_290' model 'and'
and_290 <=
sig_1093;
-- Behaviour of component 'or_291' model 'or'
or_291 <=
and_292;
-- Behaviour of component 'and_292' model 'and'
and_292 <=
sig_1093;
-- Behaviour of component 'or_297' model 'or'
or_297 <=
and_298;
-- Behaviour of component 'and_298' model 'and'
and_298 <=
sig_1093;
-- Behaviour of component 'or_299' model 'or'
or_299 <=
and_300;
-- Behaviour of component 'and_300' model 'and'
and_300 <=
sig_1093;
-- Behaviour of component 'or_320' model 'or'
or_320 <=
and_321;
-- Behaviour of component 'and_321' model 'and'
and_321 <=
sig_1084;
-- Behaviour of component 'or_326' model 'or'
or_326 <=
and_327;
-- Behaviour of component 'and_327' model 'and'
and_327 <=
sig_1093;
-- Behaviour of component 'or_333' model 'or'
or_333 <=
and_334;
-- Behaviour of component 'and_334' model 'and'
and_334 <=
sig_1092;
-- Behaviour of component 'or_363' model 'or'
or_363 <=
and_364;
-- Behaviour of component 'and_364' model 'and'
and_364 <=
sig_1092;
-- Behaviour of component 'and_403' model 'and'
and_403 <=
sig_1158 and
repeat(8, sig_1068);
-- Behaviour of component 'and_405' model 'and'
and_405 <=
sig_1159 and
repeat(8, sig_1067);
-- Behaviour of component 'and_407' model 'and'
and_407 <=
sig_1154 and
repeat(8, sig_1066);
-- Behaviour of component 'and_409' model 'and'
and_409 <=
sig_1153 and
repeat(8, sig_1065);
-- Behaviour of component 'and_415' model 'and'
and_415 <=
sig_1085(30 downto 0);
-- Behaviour of component 'or_464' model 'or'
or_464 <=
and_465;
-- Behaviour of component 'and_465' model 'and'
and_465 <=
sig_1095;
-- Behaviour of component 'or_470' model 'or'
or_470 <=
and_471;
-- Behaviour of component 'and_471' model 'and'
and_471 <=
sig_1085;
-- Behaviour of component 'or_472' model 'or'
or_472 <=
and_473;
-- Behaviour of component 'and_473' model 'and'
and_473 <=
sig_1083;
-- Behaviour of component 'or_500' model 'or'
or_500 <=
and_501;
-- Behaviour of component 'and_501' model 'and'
and_501 <=
sig_1094;
-- Behaviour of component 'or_504' model 'or'
or_504 <=
and_505;
-- Behaviour of component 'and_505' model 'and'
and_505 <=
sig_1092;
-- Behaviour of component 'or_506' model 'or'
or_506 <=
and_507;
-- Behaviour of component 'and_507' model 'and'
and_507 <=
sig_1095;
-- Behaviour of component 'or_514' model 'or'
or_514 <=
and_515;
-- Behaviour of component 'and_515' model 'and'
and_515 <=
sig_1083;
-- Behaviour of component 'or_522' model 'or'
or_522 <=
and_523;
-- Behaviour of component 'and_523' model 'and'
and_523 <=
sig_1094;
-- Behaviour of component 'mux_129' model 'mux'
mux_129 <=
(repeat(32, sig_1021) and sig_1114) or
(repeat(32, sig_1054) and sig_1100) or
(repeat(32, sig_931) and sig_1087) or
(repeat(32, sig_911) and sig_694) or
(repeat(32, sig_848) and sig_1072) or
(repeat(32, sig_978) and sig_1101) or
(repeat(32, sig_791) and sig_668) or
(repeat(32, sig_732) and sig_617);
-- Behaviour of component 'mux_133' model 'mux'
mux_133 <=
(repeat(8, sig_874) and cp_din(39 downto 32)) or
(repeat(8, sig_833) and or_394);
-- Behaviour of component 'mux_135' model 'mux'
mux_135 <=
(repeat(32, sig_1047) and (repeat(5, sig_1082(19)) & sig_1082 & sig_1155(7 downto 1))) or
(repeat(32, sig_1042) and (repeat(5, sig_1127(19)) & sig_1127 & sig_719(7 downto 1))) or
(repeat(32, sig_1040) and (repeat(5, sig_1152(19)) & sig_1152 & sig_1118(7 downto 1))) or
(repeat(32, sig_1036) and (repeat(5, sig_1126(19)) & sig_1126 & sig_1104(7 downto 1))) or
(repeat(32, sig_1035) and (repeat(5, sig_1151(19)) & sig_1151 & sig_718(7 downto 1))) or
(repeat(32, sig_822) and (repeat(5, sig_714(19)) & sig_714 & sig_670(7 downto 1))) or
(repeat(32, sig_726) and (repeat(5, sig_607(19)) & sig_607 & sig_608(7 downto 1))) or
(repeat(32, sig_1044) and (repeat(5, sig_1081(19)) & sig_1081 & sig_720(7 downto 1))) or
(repeat(32, sig_1034) and (repeat(5, sig_1080(19)) & sig_1080 & sig_1117(7 downto 1))) or
(repeat(32, sig_917) and (repeat(5, sig_695(19)) & sig_695 & sig_696(7 downto 1))) or
(repeat(32, sig_897) and (repeat(5, sig_693(19)) & sig_693 & sig_1107(7 downto 1))) or
(repeat(32, sig_1033) and (repeat(5, sig_1125(19)) & sig_1125 & sig_1116(7 downto 1))) or
(repeat(32, sig_984) and (repeat(5, sig_700(19)) & sig_700 & sig_1108(7 downto 1))) or
(repeat(32, sig_1010) and (repeat(5, sig_717(19)) & sig_717 & sig_1089(7 downto 1))) or
(repeat(32, sig_937) and (repeat(5, sig_697(19)) & sig_697 & sig_1088(7 downto 1)));
-- Behaviour of component 'mux_137' model 'mux'
mux_137 <=
(repeat(8, sig_1003) and cp_din(39 downto 32)) or
(repeat(8, sig_930) and mux_156);
-- Behaviour of component 'mux_138' model 'mux'
mux_138 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_927) and "110") or
(repeat(3, sig_925) and "101") or
(repeat(3, sig_923) and "100") or
(repeat(3, sig_921) and "011") or
(repeat(3, sig_929) and "111") or
(repeat(3, sig_919) and "010") or
(repeat(3, sig_917) and "001");
-- Behaviour of component 'mux_139' model 'mux'
mux_139 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_140' model 'mux'
mux_140 <=
(sig_1004 and and_161) or
(sig_928 and '1');
-- Behaviour of component 'mux_141' model 'mux'
mux_141 <=
(repeat(8, sig_1003) and cp_din(47 downto 40)) or
(repeat(8, sig_910) and mux_156);
-- Behaviour of component 'mux_142' model 'mux'
mux_142 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_907) and "110") or
(repeat(3, sig_905) and "101") or
(repeat(3, sig_903) and "100") or
(repeat(3, sig_901) and "011") or
(repeat(3, sig_909) and "111") or
(repeat(3, sig_899) and "010") or
(repeat(3, sig_897) and "001");
-- Behaviour of component 'mux_143' model 'mux'
mux_143 <=
(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
(repeat(3, sig_833) and augh_main_k(5 downto 3));
-- Behaviour of component 'mux_144' model 'mux'
mux_144 <=
(sig_1004 and and_161) or
(sig_908 and '1');
-- Behaviour of component 'mux_147' model 'mux'
mux_147 <=
(sig_951 and not_264);
-- Behaviour of component 'mux_149' model 'mux'
mux_149 <=
(repeat(32, sig_874) and cp_din(31 downto 0)) or
(repeat(32, sig_835) and sig_675);
-- Behaviour of component 'mux_150' model 'mux'
mux_150 <=
(sig_873 and cp_en) or
(sig_834 and '1');
-- Behaviour of component 'mux_151' model 'mux'
mux_151 <=
(sig_1005 and sig_705) or
(sig_1003 and sig_703) or
(sig_874 and sig_692) or
(sig_1050 and '1');
-- Behaviour of component 'mux_152' model 'mux'
mux_152 <=
(repeat(64, sig_1005) and (sig_1093 & sig_1084)) or
(repeat(64, sig_874) and (psc_stuff_reg_19 & cp_id_reg_14)) or
(repeat(64, sig_1003) and (sig_1153 & sig_1154 & sig_1159 & sig_1158 & sig_1099 & sig_1098 & sig_1097 & sig_1096));
-- Behaviour of component 'mux_155' model 'mux'
mux_155 <=
(sig_951 and sig_698);
-- Behaviour of component 'or_221' model 'or'
or_221 <=
and_222;
-- Behaviour of component 'and_222' model 'and'
and_222 <=
sig_1084;
-- Behaviour of component 'or_233' model 'or'
or_233 <=
and_234;
-- Behaviour of component 'and_234' model 'and'
and_234 <=
sig_1084;
-- Behaviour of component 'or_237' model 'or'
or_237 <=
and_238;
-- Behaviour of component 'and_238' model 'and'
and_238 <=
sig_1084;
-- Behaviour of component 'or_252' model 'or'
or_252 <=
and_253;
-- Behaviour of component 'and_253' model 'and'
and_253 <=
sig_1093;
-- Behaviour of component 'or_256' model 'or'
or_256 <=
and_257;
-- Behaviour of component 'and_257' model 'and'
and_257 <=
sig_1093;
-- Behaviour of component 'or_268' model 'or'
or_268 <=
and_269;
-- Behaviour of component 'and_269' model 'and'
and_269 <=
sig_1084;
-- Behaviour of component 'or_270' model 'or'
or_270 <=
and_271;
-- Behaviour of component 'and_271' model 'and'
and_271 <=
sig_1084;
-- Behaviour of component 'or_274' model 'or'
or_274 <=
and_275;
-- Behaviour of component 'and_275' model 'and'
and_275 <=
sig_1084;
-- Behaviour of component 'or_278' model 'or'
or_278 <=
and_279;
-- Behaviour of component 'and_279' model 'and'
and_279 <=
sig_1084;
-- Behaviour of component 'or_310' model 'or'
or_310 <=
and_311;
-- Behaviour of component 'and_311' model 'and'
and_311 <=
sig_1084;
-- Behaviour of component 'or_316' model 'or'
or_316 <=
and_317;
-- Behaviour of component 'and_317' model 'and'
and_317 <=
sig_1084;
-- Behaviour of component 'or_358' model 'or'
or_358 <=
and_359;
-- Behaviour of component 'and_359' model 'and'
and_359 <=
sig_1093;
-- Behaviour of component 'or_366' model 'or'
or_366 <=
and_367;
-- Behaviour of component 'and_367' model 'and'
and_367 <=
sig_1095;
-- Behaviour of component 'or_374' model 'or'
or_374 <=
and_375;
-- Behaviour of component 'and_375' model 'and'
and_375 <=
sig_1094;
-- Behaviour of component 'or_417' model 'or'
or_417 <=
and_418;
-- Behaviour of component 'and_418' model 'and'
and_418 <=
sig_1084;
-- Behaviour of component 'or_421' model 'or'
or_421 <=
and_422;
-- Behaviour of component 'and_422' model 'and'
and_422 <=
sig_1084;
-- Behaviour of component 'or_435' model 'or'
or_435 <=
and_436;
-- Behaviour of component 'and_436' model 'and'
and_436 <=
sig_1093;
-- Behaviour of component 'or_452' model 'or'
or_452 <=
and_453;
-- Behaviour of component 'and_453' model 'and'
and_453 <=
sig_1093;
-- Behaviour of component 'and_494' model 'and'
and_494 <=
sig_1095;
-- Behaviour of component 'and_498' model 'and'
and_498 <=
sig_1093;
-- Behaviour of component 'or_509' model 'or'
or_509 <=
and_510;
-- Behaviour of component 'and_510' model 'and'
and_510 <=
sig_1084(30 downto 0);
-- Behaviour of component 'or_550' model 'or'
or_550 <=
and_551;
-- Behaviour of component 'and_551' model 'and'
and_551 <=
sig_1083;
-- Behaviour of component 'or_581' model 'or'
or_581 <=
and_582;
-- Behaviour of component 'and_582' model 'and'
and_582 <=
sig_1094;
-- Behaviour of component 'or_583' model 'or'
or_583 <=
and_584;
-- Behaviour of component 'and_584' model 'and'
and_584 <=
sig_1092;
-- Behaviour of component 'or_587' model 'or'
or_587 <=
and_588;
-- Behaviour of component 'and_588' model 'and'
and_588 <=
sig_1093;
-- Behaviour of component 'and_161' model 'and'
and_161 <=
cp_en and
cp_rest;
-- Behaviour of component 'or_228' model 'or'
or_228 <=
and_229;
-- Behaviour of component 'and_229' model 'and'
and_229 <=
sig_1084;
-- Behaviour of component 'or_239' model 'or'
or_239 <=
and_240;
-- Behaviour of component 'and_240' model 'and'
and_240 <=
sig_1084;
-- Behaviour of component 'or_241' model 'or'
or_241 <=
and_242;
-- Behaviour of component 'and_242' model 'and'
and_242 <=
sig_1084;
-- Behaviour of component 'or_244' model 'or'
or_244 <=
and_245;
-- Behaviour of component 'and_245' model 'and'
and_245 <=
sig_1093;
-- Behaviour of component 'or_246' model 'or'
or_246 <=
and_247;
-- Behaviour of component 'and_247' model 'and'
and_247 <=
sig_1093;
-- Behaviour of component 'or_248' model 'or'
or_248 <=
and_249;
-- Behaviour of component 'and_249' model 'and'
and_249 <=
sig_1093;
-- Behaviour of component 'or_258' model 'or'
or_258 <=
and_259;
-- Behaviour of component 'and_259' model 'and'
and_259 <=
sig_1093;
-- Behaviour of component 'not_264' model 'not'
not_264 <= not (
cp_en
);
-- Behaviour of component 'or_266' model 'or'
or_266 <=
and_267;
-- Behaviour of component 'and_267' model 'and'
and_267 <=
sig_1084;
-- Behaviour of component 'or_272' model 'or'
or_272 <=
and_273;
-- Behaviour of component 'and_273' model 'and'
and_273 <=
sig_1084;
-- Behaviour of component 'or_280' model 'or'
or_280 <=
and_281;
-- Behaviour of component 'and_281' model 'and'
and_281 <=
sig_1084;
-- Behaviour of component 'or_287' model 'or'
or_287 <=
and_288;
-- Behaviour of component 'and_288' model 'and'
and_288 <=
sig_1093;
-- Behaviour of component 'or_293' model 'or'
or_293 <=
and_294;
-- Behaviour of component 'and_294' model 'and'
and_294 <=
sig_1093;
-- Behaviour of component 'or_301' model 'or'
or_301 <=
and_302;
-- Behaviour of component 'and_302' model 'and'
and_302 <=
sig_1093;
-- Behaviour of component 'or_304' model 'or'
or_304 <=
and_305;
-- Behaviour of component 'and_305' model 'and'
and_305 <=
sig_1084;
-- Behaviour of component 'or_306' model 'or'
or_306 <=
and_307;
-- Behaviour of component 'and_307' model 'and'
and_307 <=
sig_1084;
-- Behaviour of component 'or_308' model 'or'
or_308 <=
and_309;
-- Behaviour of component 'and_309' model 'and'
and_309 <=
sig_1084;
-- Behaviour of component 'or_312' model 'or'
or_312 <=
and_313;
-- Behaviour of component 'and_313' model 'and'
and_313 <=
sig_1084;
-- Behaviour of component 'or_318' model 'or'
or_318 <=
and_319;
-- Behaviour of component 'and_319' model 'and'
and_319 <=
sig_1084;
-- Behaviour of component 'or_329' model 'or'
or_329 <=
and_330;
-- Behaviour of component 'and_330' model 'and'
and_330 <=
sig_1094;
-- Behaviour of component 'or_335' model 'or'
or_335 <=
and_336;
-- Behaviour of component 'and_336' model 'and'
and_336 <=
sig_1095;
-- Behaviour of component 'or_339' model 'or'
or_339 <=
and_340;
-- Behaviour of component 'and_340' model 'and'
and_340 <=
sig_1094;
-- Behaviour of component 'or_342' model 'or'
or_342 <=
and_343;
-- Behaviour of component 'and_343' model 'and'
and_343 <=
sig_1095;
-- Behaviour of component 'or_346' model 'or'
or_346 <=
and_347;
-- Behaviour of component 'and_347' model 'and'
and_347 <=
sig_1084;
-- Behaviour of component 'or_348' model 'or'
or_348 <=
and_349;
-- Behaviour of component 'and_349' model 'and'
and_349 <=
sig_1085;
-- Behaviour of component 'or_351' model 'or'
or_351 <=
and_352;
-- Behaviour of component 'and_352' model 'and'
and_352 <=
sig_1083(30 downto 0);
-- Behaviour of component 'or_355' model 'or'
or_355 <=
and_356;
-- Behaviour of component 'and_356' model 'and'
and_356 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_360' model 'or'
or_360 <=
and_361;
-- Behaviour of component 'and_361' model 'and'
and_361 <=
sig_1094;
-- Behaviour of component 'or_371' model 'or'
or_371 <=
and_372;
-- Behaviour of component 'and_372' model 'and'
and_372 <=
sig_1093;
-- Behaviour of component 'or_378' model 'or'
or_378 <=
and_379;
-- Behaviour of component 'and_379' model 'and'
and_379 <=
sig_1092;
-- Behaviour of component 'or_380' model 'or'
or_380 <=
and_381;
-- Behaviour of component 'and_381' model 'and'
and_381 <=
sig_1095;
-- Behaviour of component 'or_384' model 'or'
or_384 <=
and_385;
-- Behaviour of component 'and_385' model 'and'
and_385 <=
sig_1084;
-- Behaviour of component 'or_386' model 'or'
or_386 <=
and_387;
-- Behaviour of component 'and_387' model 'and'
and_387 <=
sig_1084;
-- Behaviour of component 'or_388' model 'or'
or_388 <=
and_389;
-- Behaviour of component 'and_389' model 'and'
and_389 <=
sig_1085;
-- Behaviour of component 'or_394' model 'or'
or_394 <=
and_395 or
and_399 or
and_401 or
and_403 or
and_405 or
and_397 or
and_407 or
and_409;
-- Behaviour of component 'and_395' model 'and'
and_395 <=
sig_1096 and
repeat(8, sig_674);
-- Behaviour of component 'and_397' model 'and'
and_397 <=
sig_1097 and
repeat(8, sig_1070);
-- Behaviour of component 'and_399' model 'and'
and_399 <=
sig_1098 and
repeat(8, sig_1069);
-- Behaviour of component 'and_401' model 'and'
and_401 <=
sig_1099 and
repeat(8, sig_673);
-- Behaviour of component 'or_414' model 'or'
or_414 <=
and_415;
-- Behaviour of component 'or_423' model 'or'
or_423 <=
and_424;
-- Behaviour of component 'and_424' model 'and'
and_424 <=
sig_1084;
-- Behaviour of component 'or_425' model 'or'
or_425 <=
and_426;
-- Behaviour of component 'and_426' model 'and'
and_426 <=
sig_1093;
-- Behaviour of component 'or_427' model 'or'
or_427 <=
and_428;
-- Behaviour of component 'and_428' model 'and'
and_428 <=
sig_1085;
-- Behaviour of component 'or_431' model 'or'
or_431 <=
and_432;
-- Behaviour of component 'and_432' model 'and'
and_432 <=
sig_1093;
-- Behaviour of component 'or_433' model 'or'
or_433 <=
and_434;
-- Behaviour of component 'and_434' model 'and'
and_434 <=
sig_1084;
-- Behaviour of component 'or_438' model 'or'
or_438 <=
and_439;
-- Behaviour of component 'and_439' model 'and'
and_439 <=
sig_1093;
-- Behaviour of component 'or_440' model 'or'
or_440 <=
and_441;
-- Behaviour of component 'and_441' model 'and'
and_441 <=
sig_1094;
-- Behaviour of component 'or_443' model 'or'
or_443 <=
and_444;
-- Behaviour of component 'and_444' model 'and'
and_444 <=
sig_1092;
-- Behaviour of component 'or_450' model 'or'
or_450 <=
and_451;
-- Behaviour of component 'and_451' model 'and'
and_451 <=
sig_1093;
-- Behaviour of component 'or_454' model 'or'
or_454 <=
and_455;
-- Behaviour of component 'and_455' model 'and'
and_455 <=
sig_1084(30 downto 0);
-- Behaviour of component 'or_458' model 'or'
or_458 <=
and_459;
-- Behaviour of component 'and_459' model 'and'
and_459 <=
sig_1094;
-- Behaviour of component 'or_462' model 'or'
or_462 <=
and_463;
-- Behaviour of component 'and_463' model 'and'
and_463 <=
sig_1092;
-- Behaviour of component 'or_467' model 'or'
or_467 <=
and_468;
-- Behaviour of component 'and_468' model 'and'
and_468 <=
sig_1084(30 downto 0);
-- Behaviour of component 'or_475' model 'or'
or_475 <=
and_476;
-- Behaviour of component 'and_476' model 'and'
and_476 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_479' model 'or'
or_479 <=
and_480;
-- Behaviour of component 'and_480' model 'and'
and_480 <=
sig_1093;
-- Behaviour of component 'or_481' model 'or'
or_481 <=
and_482;
-- Behaviour of component 'and_482' model 'and'
and_482 <=
sig_1094;
-- Behaviour of component 'or_485' model 'or'
or_485 <=
and_486;
-- Behaviour of component 'and_486' model 'and'
and_486 <=
sig_1094;
-- Behaviour of component 'or_490' model 'or'
or_490 <=
and_491;
-- Behaviour of component 'and_491' model 'and'
and_491 <=
sig_1094;
-- Behaviour of component 'or_493' model 'or'
or_493 <=
and_494;
-- Behaviour of component 'or_497' model 'or'
or_497 <=
and_498;
-- Behaviour of component 'or_512' model 'or'
or_512 <=
and_513;
-- Behaviour of component 'and_513' model 'and'
and_513 <=
sig_1085;
-- Behaviour of component 'or_518' model 'or'
or_518 <=
and_519;
-- Behaviour of component 'and_519' model 'and'
and_519 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_525' model 'or'
or_525 <=
and_526;
-- Behaviour of component 'and_526' model 'and'
and_526 <=
sig_1092;
-- Behaviour of component 'or_529' model 'or'
or_529 <=
and_530;
-- Behaviour of component 'and_530' model 'and'
and_530 <=
sig_1085(30 downto 0);
-- Behaviour of component 'or_532' model 'or'
or_532 <=
and_533;
-- Behaviour of component 'and_533' model 'and'
and_533 <=
sig_1085(30 downto 0);
-- Behaviour of component 'or_535' model 'or'
or_535 <=
and_536;
-- Behaviour of component 'and_536' model 'and'
and_536 <=
sig_1094;
-- Behaviour of component 'or_538' model 'or'
or_538 <=
and_539;
-- Behaviour of component 'and_539' model 'and'
and_539 <=
sig_1092;
-- Behaviour of component 'or_541' model 'or'
or_541 <=
and_542;
-- Behaviour of component 'and_542' model 'and'
and_542 <=
sig_1095;
-- Behaviour of component 'or_545' model 'or'
or_545 <=
and_546;
-- Behaviour of component 'and_546' model 'and'
and_546 <=
sig_1084(30 downto 0);
-- Behaviour of component 'or_548' model 'or'
or_548 <=
and_549;
-- Behaviour of component 'and_549' model 'and'
and_549 <=
sig_1085;
-- Behaviour of component 'or_554' model 'or'
or_554 <=
and_555;
-- Behaviour of component 'and_555' model 'and'
and_555 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_557' model 'or'
or_557 <=
and_558;
-- Behaviour of component 'and_558' model 'and'
and_558 <=
sig_1085(30 downto 0);
-- Behaviour of component 'or_568' model 'or'
or_568 <=
and_569;
-- Behaviour of component 'and_569' model 'and'
and_569 <=
sig_1085;
-- Behaviour of component 'or_571' model 'or'
or_571 <=
and_572;
-- Behaviour of component 'and_572' model 'and'
and_572 <=
sig_1083(30 downto 0);
-- Behaviour of component 'or_575' model 'or'
or_575 <=
and_576;
-- Behaviour of component 'and_576' model 'and'
and_576 <=
sig_1086(30 downto 0);
-- Behaviour of component 'or_590' model 'or'
or_590 <=
and_591;
-- Behaviour of component 'and_591' model 'and'
and_591 <=
sig_1094;
-- Behaviour of component 'or_597' model 'or'
or_597 <=
and_598;
-- Behaviour of component 'and_598' model 'and'
and_598 <=
sig_1085;
-- Behaviour of component 'or_603' model 'or'
or_603 <=
and_604;
-- Behaviour of component 'and_604' model 'and'
and_604 <=
sig_1084(30 downto 0);
-- Behaviour of all components of model 'reg'
-- Registers with clock = sig_clock and reset = sig_reset active '1'
process(sig_clock, sig_reset)
begin
if sig_reset = '1' then
psc_stuff_reg_19 <= "000000000000000000000000000000000000000000000000000000000000000";
else
if rising_edge(sig_clock) then
if mux_28 = '1' then
psc_stuff_reg_19 <= psc_stuff_reg_18 & write8_u8 & augh_main_k(31 downto 1);
end if;
end if;
end if;
end process;
-- Registers with clock = sig_clock and no reset
process(sig_clock)
begin
if rising_edge(sig_clock) then
if mux_30 = '1' then
psc_stuff_reg_18 <= cp_din(63 downto 40);
end if;
if mux_34 = '1' then
cp_id_reg_stable_15 <= mux_33;
end if;
if mux_36 = '1' then
cp_id_reg_14 <= mux_35;
end if;
if mux_38 = '1' then
psc_loop_reg_13 <= mux_37;
end if;
if sig_1024 = '1' then
idct_2d_yc_reg7 <= mux_69;
end if;
if sig_1025 = '1' then
idct_2d_yc_reg6 <= mux_71;
end if;
if sig_1027 = '1' then
idct_2d_yc_reg5 <= mux_73;
end if;
if sig_1028 = '1' then
idct_2d_yc_reg4 <= mux_75;
end if;
if sig_1029 = '1' then
idct_2d_yc_reg3 <= mux_77;
end if;
if sig_1030 = '1' then
idct_2d_yc_reg2 <= mux_79;
end if;
if sig_1031 = '1' then
idct_2d_yc_reg1 <= mux_81;
end if;
if sig_1032 = '1' then
idct_2d_yc_reg0 <= mux_83;
end if;
if sig_1001 = '1' then
idct_z2_reg7 <= sig_1090;
end if;
if sig_998 = '1' then
idct_z2_reg6 <= sig_701;
end if;
if sig_999 = '1' then
idct_z2_reg5 <= sig_1113;
end if;
if sig_1000 = '1' then
idct_z2_reg4 <= sig_1120;
end if;
if sig_967 = '1' then
idct_z2_reg3 <= sig_1139;
end if;
if sig_968 = '1' then
idct_z2_reg2 <= sig_1140;
end if;
if sig_969 = '1' then
idct_z2_reg1 <= sig_1141;
end if;
if sig_970 = '1' then
idct_z2_reg0 <= sig_1110;
end if;
if sig_971 = '1' then
idct_z1_reg7 <= mux_109;
end if;
if sig_959 = '1' then
idct_z1_reg6 <= mux_111;
end if;
if sig_988 = '1' then
idct_z1_reg5 <= mux_113;
end if;
if sig_971 = '1' then
idct_z1_reg4 <= mux_115;
end if;
if sig_964 = '1' then
idct_z1_reg3 <= mux_117;
end if;
if sig_962 = '1' then
idct_z1_reg2 <= mux_119;
end if;
if sig_992 = '1' then
idct_z1_reg1 <= mux_121;
end if;
if sig_994 = '1' then
idct_z1_reg0 <= mux_123;
end if;
if sig_1023 = '1' then
idct_z3_reg7 <= sig_1147 & idct_z2_reg7(0);
end if;
if sig_1022 = '1' then
idct_z3_reg6 <= sig_1091 & idct_z2_reg6(1 downto 0);
end if;
if sig_1020 = '1' then
idct_z3_reg5 <= mux_129;
end if;
if sig_1019 = '1' then
idct_z3_reg4 <= sig_1121;
end if;
if mux_134 = '1' then
write8_u8 <= mux_133;
end if;
if sig_1046 = '1' then
idct_2d_r <= mux_135;
end if;
if mux_147 = '1' then
read32_ret0_10 <= stdin_data;
end if;
if mux_150 = '1' then
augh_main_k <= mux_149;
end if;
end if;
end process;
-- Remaining signal assignments
-- Those who are not assigned by component instantiation
sig_clock <= clock;
sig_reset <= reset;
sig_start <= start;
test_cp_0_16 <= mux_32;
sig_1160 <= sig_608(26) & sig_608(26 downto 8);
sig_1161 <= sig_1122 & "00";
sig_1162 <= sig_1122 & "00";
sig_1163 <= sig_1107(26) & sig_1107(26 downto 8);
sig_1164 <= sig_1122 & "00";
sig_1165 <= sig_696(26) & sig_696(26 downto 8);
sig_1166 <= sig_1088(26) & sig_1088(26 downto 8);
sig_1167 <= sig_1108(26) & sig_1108(26 downto 8);
sig_1168 <= sig_670(26) & sig_670(26 downto 8);
sig_1169 <= sig_1089(26) & sig_1089(26 downto 8);
sig_1170 <= sig_1122 & "00";
sig_1171 <= sig_1117(26) & sig_1117(26 downto 8);
sig_1172 <= sig_720(26) & sig_720(26 downto 8);
sig_1173 <= sig_1155(26) & sig_1155(26 downto 8);
sig_1174 <= sig_1122 & "00";
sig_1175 <= sig_1122 & "00";
sig_1176 <= sig_1122 & "00";
sig_1177 <= sig_1122 & "00";
sig_1178 <= sig_1143 & '0';
sig_1179 <= sig_1116(26) & sig_1116(26 downto 8);
sig_1180 <= sig_1104(26) & sig_1104(26 downto 8);
sig_1181 <= sig_719(26) & sig_719(26 downto 8);
sig_1182 <= sig_718(26) & sig_718(26 downto 8);
sig_1183 <= sig_1118(26) & sig_1118(26 downto 8);
-- Remaining top-level ports assignments
-- Those who are not assigned by component instantiation
cp_ok <= mux_151;
cp_dout <= mux_152;
stdout_data <= write8_u8;
stdout_rdy <= mux_154;
stdin_rdy <= mux_155;
end architecture;
| gpl-2.0 | a66ab89ec479e74a115f17f762780958 | 0.633185 | 2.571448 | false | false | false | false |
nickg/nvc | test/regress/record30.vhd | 1 | 722 | entity record30 is
end entity;
architecture test of record30 is
type int_ptr is access integer;
type pair is record
x, y : natural;
end record;
type rec is record
x : bit_vector;
y : int_ptr;
z : pair;
end record;
begin
main: process is
variable s : rec(x(1 to 3));
begin
assert s.x = "000";
assert s = (x => "000", y => null, z => (0, 0));
s.x := "101";
assert s.x = "101";
assert s = (x => "101", y => null, z => (0, 0));
s := (x => "111", y => null, z => (0, 0));
assert s.x = "111";
assert s = (x => "111", y => null, z => (0, 0));
wait;
end process;
end architecture;
| gpl-3.0 | ea517914949ce7afa7856bbbb7c38b30 | 0.463989 | 3.266968 | false | false | false | false |
mistryalok/FPGA | Xilinx/ISE/Basics/encoder8x3/encoder8x3.vhd | 1 | 1,302 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:54:47 04/04/2013
-- Design Name:
-- Module Name: encoder8x3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity encoder8x3 is
Port ( i : in std_logic_VECTOR (7 downto 0);
o : out std_logic_VECTOR (2 downto 0));
end encoder8x3;
architecture Behavioral of encoder8x3 is
begin
process(i)
begin
case i is
when "00000001" => o <= "000";
when "00000010" => o <= "001";
when "00000100" => o <= "010";
when "00001000" => o <= "011";
when "00010000" => o <= "100";
when "00100000" => o <= "101";
when "01000000" => o <= "110";
when "10000000" => o <= "111";
end case;
end process;
end Behavioral;
| gpl-3.0 | 0eb94431c00f1ffe737c64821ebd1922 | 0.53149 | 3.547684 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | RCA/16bits/RCA/RCA.vhd | 1 | 1,806 | -- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (15 downto 0);
SomaResult: out std_logic_vector (15 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (15 downto 1);
signal CarryInTemp: std_logic;
signal CarryOutTemp0,CarryOutTemp1: std_logic;
signal A, B, Ssoma: std_logic_vector(15 downto 0);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg16Bit
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>CarryInTemp
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>CarryOutTemp0,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Ssoma,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
--somador--
Som0: Soma1 PORT MAP (
CarryInTemp,
A(0),
B(0),
Ssoma(0),
carry(1)
);
SOM: FOR i IN 1 TO 14 GENERATE
Som1: Soma1 PORT MAP (
carry(i),
A(i),
B(i),
Ssoma(i),
carry(i+1)
);
END GENERATE;
Som7: Soma1 PORT MAP (
carry(15),
A(15),
B(15),
Ssoma(15),
CarryOutTemp0
);
END strc_RCA ; | mit | 2133964219b703a8d7efdcf8f339d1b0 | 0.631783 | 2.57265 | false | false | false | false |
tgingold/ghdl | libraries/vital2000/memory_p.vhdl | 7 | 78,216 | -- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
-- : Jose De Castro, Consultant
-- : Prakash Bare, GDA Technologies
-- : William Yam, LSI Logic Corporation
-- : Dennis Brophy, Model Technology
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC memory models.
-- :
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Ver:|Auth:| Date:| Changes Made:
-- 0.1 | eb |071796| First prototye as part of VITAL memory proposal
-- 0.2 | jdc |012897| Initial prototyping with proposed MTM scheme
-- 0.3 | jdc |090297| Extensive updates for TAG review (functional)
-- 0.4 | eb |091597| Changed naming conventions for VitalMemoryTable
-- | | | Added interface of VitalMemoryCrossPorts() &
-- | | | VitalMemoryViolation().
-- 0.5 | jdc |092997| Completed naming changes thoughout package body.
-- | | | Testing with simgle port test model looks ok.
-- 0.6 | jdc |121797| Major updates to the packages:
-- | | | - Implement VitalMemoryCrossPorts()
-- | | | - Use new VitalAddressValueType
-- | | | - Use new VitalCrossPortModeType enum
-- | | | - Overloading without SamePort args
-- | | | - Honor erroneous address values
-- | | | - Honor ports disabled with 'Z'
-- | | | - Implement implicit read 'M' table symbol
-- | | | - Cleanup buses to use (H DOWNTO L)
-- | | | - Message control via MsgOn,HeaderMsg,PortName
-- | | | - Tested with 1P1RW,2P2RW,4P2R2W,4P4RW cases
-- 0.7 | jdc |052698| Bug fixes to the packages:
-- | | | - Fix failure with negative Address values
-- | | | - Added debug messages for VMT table search
-- | | | - Remove 'S' for action column (only 's')
-- | | | - Remove 's' for response column (only 'S')
-- | | | - Remove 'X' for action and response columns
-- 0.8 | jdc |061298| Implemented VitalMemoryViolation()
-- | | | - Minimal functionality violation tables
-- | | | - Missing:
-- | | | - Cannot handle wide violation variables
-- | | | - Cannot handle sub-word cases
-- | | | Fixed IIC version of MemoryMatch
-- | | | Fixed 'M' vs 'm' switched on debug output
-- | | | TO BE DONE:
-- | | | - Implement 'd' corrupting a single bit
-- | | | - Implement 'D' corrupting a single bit
-- 0.9 |eb/sc|080498| Added UNDEF value for VitalPortFlagType
-- 0.10|eb/sc|080798| Added CORRUPT value for VitalPortFlagType
-- 0.11|eb/sc|081798| Added overloaded function interface for
-- | | | VitalDeclareMemory
-- 0.14| jdc |113198| Merging of memory functionality and version
-- | | | 1.4 9/17/98 of timing package from Prakash
-- 0.15| jdc |120198| Major development of VMV functionality
-- 0.16| jdc |120298| Complete VMV functionlality for initial testing
-- | | | - New ViolationTableCorruptMask() procedure
-- | | | - New MemoryTableCorruptMask() procedure
-- | | | - HandleMemoryAction():
-- | | | - Removed DataOutBus bogus output
-- | | | - Replaced DataOutTmp with DataInTmp
-- | | | - Added CorruptMask input handling
-- | | | - Implemented 'd','D' using CorruptMask
-- | | | - CorruptMask on 'd','C','L','D','E'
-- | | | - CorruptMask ignored on 'c','l','e'
-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT
-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT
-- | | | - Changed 'c','l','d','e' to ignore HighBit, LowBit
-- | | | - Changed 'C','L','D','E' to use HighBit, LowBit
-- | | | - HandleDataAction():
-- | | | - Added CorruptMask input handling
-- | | | - Implemented 'd','D' using CorruptMask
-- | | | - CorruptMask on 'd','C','L','D','E'
-- | | | - CorruptMask ignored on 'l','e'
-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT
-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT
-- | | | - Changed 'l','d','e' to ignore HighBit, LowBit
-- | | | - Changed 'L','D','E' to use HighBit, LowBit
-- | | | - MemoryTableLookUp():
-- | | | - Added MsgOn table debug output
-- | | | - Uses new MemoryTableCorruptMask()
-- | | | - ViolationTableLookUp():
-- | | | - Uses new ViolationTableCorruptMask()
-- 0.17| jdc |120898| - Added VitalMemoryViolationSymbolType,
-- | | | VitalMemoryViolationTableType data
-- | | | types but not used yet (need to discuss)
-- | | | - Added overload for VitalMemoryViolation()
-- | | | which does not have array flags
-- | | | - Bug fixes for VMV functionality:
-- | | | - ViolationTableLookUp() not handling '-' in
-- | | | scalar violation matching
-- | | | - VitalMemoryViolation() now normalizes
-- | | | VFlagArrayTmp'LEFT as LSB before calling
-- | | | ViolationTableLookUp() for proper scanning
-- | | | - ViolationTableCorruptMask() had to remove
-- | | | normalization of CorruptMaskTmp and
-- | | | ViolMaskTmp for proper MSB:LSB corruption
-- | | | - HandleMemoryAction(), HandleDataAction()
-- | | | - Removed 'D','E' since not being used
-- | | | - Use XOR instead of OR for corrupt masks
-- | | | - Now 'd' is sensitive to HighBit, LowBit
-- | | | - Fixed LowBit overflow in bit writeable case
-- | | | - MemoryTableCorruptMask()
-- | | | - ViolationTableCorruptMask()
-- | | | - VitalMemoryTable()
-- | | | - VitalMemoryCrossPorts()
-- | | | - Fixed VitalMemoryViolation() failing on
-- | | | error AddressValue from earlier VMT()
-- | | | - Minor cleanup of code formatting
-- 0.18| jdc |032599| - In VitalDeclareMemory()
-- | | | - Added BinaryLoadFile formal arg and
-- | | | modified LoadMemory() to handle bin
-- | | | - Added NOCHANGE to VitalPortFlagType
-- | | | - For VitalCrossPortModeType
-- | | | - Added CpContention enum
-- | | | - In HandleDataAction()
-- | | | - Set PortFlag := NOCHANGE for 'S'
-- | | | - In HandleMemoryAction()
-- | | | - Set PortFlag := NOCHANGE for 's'
-- | | | - In VitalMemoryTable() and
-- | | | VitalMemoryViolation()
-- | | | - Honor PortFlag = NOCHANGE returned
-- | | | from HandleMemoryAction()
-- | | | - In VitalMemoryCrossPorts()
-- | | | - Fixed Address = AddressJ for all
-- | | | conditions of DoWrCont & DoCpRead
-- | | | - Handle CpContention like WrContOnly
-- | | | under CpReadOnly conditions, with
-- | | | associated memory message changes
-- | | | - Handle PortFlag = NOCHANGE like
-- | | | PortFlag = READ for actions
-- | | | - Modeling change:
-- | | | - Need to init PortFlag every delta
-- | | | PortFlag_A := (OTHES => UNDEF);
-- | | | - Updated InternalTimingCheck code
-- 0.19| jdc |042599| - Fixes for bit-writeable cases
-- | | | - Check PortFlag after HandleDataAction
-- | | | in VitalMemoryViolation()
-- 0.20| jdc |042599| - Merge PortFlag changes from Prakash
-- | | | and Willian:
-- | | | VitalMemorySchedulePathDelay()
-- | | | VitalMemoryExpandPortFlag()
-- 0.21| jdc |072199| - Changed VitalCrossPortModeType enums,
-- | | | added new CpReadAndReadContention.
-- | | | - Fixed VitalMemoryCrossPorts() parameter
-- | | | SamePortFlag to INOUT so that it can
-- | | | set CORRUPT or READ value.
-- | | | - Fixed VitalMemoryTable() where PortFlag
-- | | | setting by HandleDataAction() is being
-- | | | ignored when HandleMemoryAction() sets
-- | | | PortFlagTmp to NOCHANGE.
-- | | | - Fixed VitalMemoryViolation() to set
-- | | | all bits of PortFlag when violating.
-- 0.22| jdc |072399| - Added HIGHZ to PortFlagType. HandleData
-- | | | checks whether the previous state is HIGHZ.
-- | | | If yes then portFlag should be NOCHANGE
-- | | | for VMPD to ignore IORetain corruption.
-- | | | The idea is that the first Z should be
-- | | | propagated but later ones should be ignored.
-- | | |
-- 0.23| jdc |100499| - Took code checked in by Dennis 09/28/99
-- | | | - Changed VitalPortFlagType to record of
-- | | | new VitalPortStateType to hold current,
-- | | | previous values and separate disable.
-- | | | Also created VitalDefaultPortFlag const.
-- | | | Removed usage of PortFlag NOCHANGE
-- | | | - VitalMemoryTable() changes:
-- | | | Optimized return when all curr = prev
-- | | | AddressValue is now INOUT to optimize
-- | | | Transfer PF.MemoryCurrent to MemoryPrevious
-- | | | Transfer PF.DataCurrent to DataPrevious
-- | | | Reset PF.OutputDisable to FALSE
-- | | | Expects PortFlag init in declaration
-- | | | No need to init PortFlag every delta
-- | | | - VitalMemorySchedulePathDelay() changes:
-- | | | Initialize with VitalDefaultPortFlag
-- | | | Check PortFlag.OutputDisable
-- | | | - HandleMemoryAction() changes:
-- | | | Set value of PortFlag.MemoryCurrent
-- | | | Never set PortFlag.OutputDisable
-- | | | - HandleDataAction() changes:
-- | | | Set value of PortFlag.DataCurrent
-- | | | Set PortFlag.DataCurrent for HIGHZ
-- | | | - VitalMemoryCrossPorts() changes:
-- | | | Check/set value of PF.MemoryCurrent
-- | | | Check value of PF.OutputDisable
-- | | | - VitalMemoryViolation() changes:
-- | | | Fixed bug - not reading inout PF value
-- | | | Clean up setting of PortFlag
-- 0.24| jdc |100899| - Modified update of PF.OutputDisable
-- | | | to correctly accomodate 2P1W1R case:
-- | | | the read port should not exhibit
-- | | | IO retain corrupt when reading
-- | | | addr unrelated to addr being written.
-- 0.25| jdc |100999| - VitalMemoryViolation() change:
-- | | | Fixed bug with RDNWR mode incorrectly
-- | | | updating the PF.OutputDisable
-- 0.26| jdc |100999| - VitalMemoryCrossPorts() change:
-- | | | Fixed bugs with update of PF
-- 0.27| jdc |101499| - VitalMemoryCrossPorts() change:
-- | | | Added DoRdWrCont message (ErrMcpRdWrCo,
-- | | | Memory cross port read/write data only
-- | | | contention)
-- | | | - VitalMemoryTable() change:
-- | | | Set PF.OutputDisable := TRUE for the
-- | | | optimized cases.
-- 0.28| pb |112399| - Added 8 VMPD procedures for vector
-- | | | PathCondition support. Now the total
-- | | | number of overloadings for VMPD is 24.
-- | | | - Number of overloadings for SetupHold
-- | | | procedures increased to 5. Scalar violations
-- | | | are not supported anymore. Vector checkEnabled
-- | | | support is provided through the new overloading
-- 0.29| jdc |120999| - HandleMemoryAction() HandleDataAction()
-- | | | Reinstated 'D' and 'E' actions but
-- | | | with new PortFlagType
-- | | | - Updated file handling syntax, must compile
-- | | | with -93 syntax now.
-- 0.30| jdc |022300| - Formated for 80 column max width
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.Vital_Timing.ALL;
USE IEEE.Vital_Primitives.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
PACKAGE Vital_Memory IS
-- ----------------------------------------------------------------------------
-- Timing Section
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- Types and constants for Memory timing procedures
-- ----------------------------------------------------------------------------
TYPE VitalMemoryArcType IS (ParallelArc, CrossArc, SubwordArc);
TYPE OutputRetainBehaviorType IS (BitCorrupt, WordCorrupt);
TYPE VitalMemoryMsgFormatType IS (Vector, Scalar, VectorEnum);
TYPE X01ArrayT IS ARRAY (NATURAL RANGE <> ) OF X01;
TYPE X01ArrayPT IS ACCESS X01ArrayT;
TYPE VitalMemoryViolationType IS ACCESS X01ArrayT;
CONSTANT DefaultNumBitsPerSubword : INTEGER := -1;
-- Data type storing path delay and schedule information for output bits
TYPE VitalMemoryScheduleDataType IS RECORD
OutputData : std_ulogic;
NumBitsPerSubWord : INTEGER;
ScheduleTime : TIME;
ScheduleValue : std_ulogic;
LastOutputValue : std_ulogic;
PropDelay : TIME;
OutputRetainDelay : TIME;
InputAge : TIME;
END RECORD;
TYPE VitalMemoryTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
RefLastA : X01ArrayPT;
RefTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
TYPE VitalPeriodDataArrayType IS ARRAY (NATURAL RANGE <>) OF
VitalPeriodDataType;
-- Data type storing path delay and schedule information for output
-- vectors
TYPE VitalMemoryScheduleDataVectorType IS ARRAY (NATURAL RANGE <> ) OF
VitalMemoryScheduleDataType;
-- VitalPortFlagType records runtime mode of port sub-word slices
-- TYPE VitalPortFlagType IS (
-- UNDEF,
-- READ,
-- WRITE,
-- CORRUPT,
-- HIGHZ,
-- NOCHANGE
-- );
-- VitalPortFlagType records runtime mode of port sub-word slices
TYPE VitalPortStateType IS (
UNDEF,
READ,
WRITE,
CORRUPT,
HIGHZ
);
TYPE VitalPortFlagType IS RECORD
MemoryCurrent : VitalPortStateType;
MemoryPrevious : VitalPortStateType;
DataCurrent : VitalPortStateType;
DataPrevious : VitalPortStateType;
OutputDisable : BOOLEAN;
END RECORD;
CONSTANT VitalDefaultPortFlag : VitalPortFlagType := (
MemoryCurrent => READ,
MemoryPrevious => UNDEF,
DataCurrent => READ,
DataPrevious => UNDEF,
OutputDisable => FALSE
);
-- VitalPortFlagVectorType to be same width i as enables of a port
-- or j multiples thereof, where j is the number of cross ports
TYPE VitalPortFlagVectorType IS
ARRAY (NATURAL RANGE <>) OF VitalPortFlagType;
-- ----------------------------------------------------------------------------
-- Functions : VitalMemory path delay procedures
-- - VitalMemoryInitPathDelay
-- - VitalMemoryAddPathDelay
-- - VitalMemorySchedulePathDelay
--
-- Description: VitalMemoryInitPathDelay, VitalMemoryAddPathDelay and
-- VitalMemorySchedulePathDelay are Level 1 routines used
-- for selecting the propagation delay paths based on
-- path condition, transition type and delay values and
-- schedule a new output value.
--
-- Following features are implemented in these procedures:
-- o condition dependent path selection
-- o Transition dependent delay selection
-- o shortest delay path selection from multiple
-- candidate paths
-- o Scheduling of the computed values on the specified
-- signal.
-- o output retain behavior if outputRetain flag is set
-- o output mapping to alternate strengths to model
-- pull-up, pull-down etc.
--
-- <More details to be added here>
--
-- Following is information on overloading of the procedures.
--
-- VitalMemoryInitPathDelay is overloaded for ScheduleDataArray and
-- OutputDataArray
--
-- ----------------------------------------------------------------------------
-- ScheduleDataArray OutputDataArray
-- ----------------------------------------------------------------------------
-- Scalar Scalar
-- Vector Vector
-- ----------------------------------------------------------------------------
--
--
-- VitalMemoryAddPathDelay is overloaded for ScheduleDataArray,
-- PathDelayArray, InputSignal and delaytype.
--
-- ----------------------------------------------------------------------------
-- DelayType InputSignal ScheduleData PathDelay
-- Array Array
-- ----------------------------------------------------------------------------
-- VitalDelayType Scalar Scalar Scalar
-- VitalDelayType Scalar Vector Vector
-- VitalDelayType Vector Scalar Vector
-- VitalDelayType Vector Vector Vector
-- VitalDelayType01 Scalar Scalar Scalar
-- VitalDelayType01 Scalar Vector Vector
-- VitalDelayType01 Vector Scalar Vector
-- VitalDelayType01 Vector Vector Vector
-- VitalDelayType01Z Scalar Scalar Scalar
-- VitalDelayType01Z Scalar Vector Vector
-- VitalDelayType01Z Vector Scalar Vector
-- VitalDelayType01Z Vector Vector Vector
-- VitalDelayType01XZ Scalar Scalar Scalar
-- VitalDelayType01XZ Scalar Vector Vector
-- VitalDelayType01XZ Vector Scalar Vector
-- VitalDelayType01XZ Vector Vector Vector
-- ----------------------------------------------------------------------------
--
--
-- VitalMemorySchedulePathDelay is overloaded for ScheduleDataArray,
-- and OutSignal
--
-- ----------------------------------------------------------------------------
-- OutSignal ScheduleDataArray
-- ----------------------------------------------------------------------------
-- Scalar Scalar
-- Vector Vector
-- ----------------------------------------------------------------------------
--
-- Procedure Declarations:
--
--
-- Function : VitalMemoryInitPathDelay
--
-- Arguments:
--
-- INOUT Type Description
--
-- ScheduleDataArray/ VitalMemoryScheduleDataVectorType/
-- ScheduleData VitalMemoryScheduleDataType
-- Internal data variable for
-- storing delay and schedule
-- information for each output bit
--
--
-- IN
--
-- OutputDataArray/ STD_LOGIC_VECTOR/Array containing current output
-- OutputData STD_ULOGIC value
--
--
-- NumBitsPerSubWord INTEGER Number of bits per subword.
-- Default value of this argument
-- is DefaultNumBitsPerSubword
-- which is interpreted as no
-- subwords
--
-- ----------------------------------------------------------------------------
--
--
-- ScheduleDataArray - Vector
-- OutputDataArray - Vector
--
PROCEDURE VitalMemoryInitPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE OutputDataArray : IN STD_LOGIC_VECTOR;
CONSTANT NumBitsPerSubWord : IN INTEGER := DefaultNumBitsPerSubword
);
--
-- ScheduleDataArray - Scalar
-- OutputDataArray - Scalar
--
PROCEDURE VitalMemoryInitPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
VARIABLE OutputData : IN STD_ULOGIC
);
-- ----------------------------------------------------------------------------
--
-- Function : VitalMemoryAddPathDelay
--
-- Arguments
--
-- INOUT Type Description
--
-- ScheduleDataArray/ VitalMemoryScheduleDataVectorType/
-- ScheduleData VitalMemoryScheduleDataType
-- Internal data variable for
-- storing delay and schedule
-- information for each output bit
--
-- InputChangeTimeArray/ VitaltimeArrayT/Time
-- InputChangeTime Holds the time since the last
-- input change
--
-- IN
--
-- InputSignal STD_LOGIC_VECTOR
-- STD_ULOGIC/ Array holding the input value
--
-- OutputSignalName STRING The output signal name
--
-- PathDelayArray/ VitalDelayArrayType01ZX,
-- PathDelay VitalDelayArrayType01Z,
-- VitalDelayArrayType01,
-- VitalDelayArrayType/
-- VitalDelayType01ZX,
-- VitalDelayType01Z,
-- VitalDelayType01,
-- VitalDelayType Array of delay values
--
-- ArcType VitalMemoryArcType
-- Indicates the Path type. This
-- can be SubwordArc, CrossArc or
-- ParallelArc
--
-- PathCondition BOOLEAN If True, the transition in
-- the corresponding input signal
-- is considered while
-- caluculating the prop. delay
-- else the transition is ignored.
--
-- OutputRetainFlag BOOLEAN If specified TRUE,output retain
-- (hold) behavior is implemented.
--
-- ----------------------------------------------------------------------------
--
-- #1
-- DelayType - VitalDelayType
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelay : IN VitalDelayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #2
-- DelayType - VitalDelayType
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #3
-- DelayType - VitalDelayType
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT
);
-- #4
-- DelayType - VitalDelayType
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #5
-- DelayType - VitalDelayType
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #6
-- DelayType - VitalDelayType
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
);
-- #7
-- DelayType - VitalDelayType01
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelay : IN VitalDelayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #8
-- DelayType - VitalDelayType01
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #9
-- DelayType - VitalDelayType01
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT
);
-- #10
-- DelayType - VitalDelayType01
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #11
-- DelayType - VitalDelayType01
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #12
-- DelayType - VitalDelayType01
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
);
-- #13
-- DelayType - VitalDelayType01Z
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelay : IN VitalDelayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #14
-- DelayType - VitalDelayType01Z
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #15
-- DelayType - VitalDelayType01Z
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #16
-- DelayType - VitalDelayType01Z
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #17
-- DelayType - VitalDelayType01Z
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #18
-- DelayType - VitalDelayType01Z
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #19
-- DelayType - VitalDelayType01ZX
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelay : IN VitalDelayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #20
-- DelayType - VitalDelayType01ZX
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #21
-- DelayType - VitalDelayType01ZX
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #22
-- DelayType - VitalDelayType01ZX
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #23
-- DelayType - VitalDelayType01ZX
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #24
-- DelayType - VitalDelayType01ZX
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- ----------------------------------------------------------------------------
--
-- Function : VitalMemorySchedulePathDelay
--
-- Arguments:
--
-- OUT Type Description
-- OutSignal STD_LOGIC_VECTOR/ The output signal for
-- STD_ULOGIC scheduling
--
-- IN
-- OutputSignalName STRING The name of the output signal
--
-- IN
-- PortFlag VitalPortFlagType Port flag variable from
-- functional procedures
--
-- IN
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the
-- output can be mapped to
-- alternate strengths to model
-- tri-state devices, pull-ups
-- and pull-downs.
--
-- INOUT
-- ScheduleDataArray/ VitalMemoryScheduleDataVectorType/
-- ScheduleData VitalMemoryScheduleDataType
-- Internal data variable for
-- storing delay and schedule
-- information for each
-- output bit
--
-- ----------------------------------------------------------------------------
--
-- ScheduleDataArray - Vector
-- OutputSignal - Vector
--
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT std_logic_vector;
CONSTANT OutputSignalName : IN STRING := "";
CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType
);
--
-- ScheduleDataArray - Vector
-- OutputSignal - Vector
--
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT std_logic_vector;
CONSTANT OutputSignalName : IN STRING := "";
CONSTANT PortFlag : IN VitalPortFlagVectorType;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType
);
--
-- ScheduleDataArray - Scalar
-- OutputSignal - Scalar
--
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT std_ulogic;
CONSTANT OutputSignalName : IN STRING := "";
CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType
);
-- ----------------------------------------------------------------------------
FUNCTION VitalMemoryTimingDataInit RETURN VitalMemoryTimingDataType;
-- ----------------------------------------------------------------------------
--
-- Function Name: VitalMemorySetupHoldCheck
--
-- Description: The VitalMemorySetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal and reference signals. Parallel, Subword and
-- Cross Arc relationships between test and reference
-- signals are supported.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_logic_vector Value of test signal
-- TestSignalName STRING Name of test signal
-- TestDelay VitalDelayArrayType Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- std_logic_vector
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- VitalDelayArrayType with RefSignal
-- SetupHigh VitalDelayArrayType Absolute minimum time duration
-- before the transition of RefSignal
-- for which transitions of
-- TestSignal are allowed to proceed
-- to the "1" state without causing
-- a setup violation.
-- SetupLow VitalDelayArrayType Absolute minimum time duration
-- before the transition of RefSignal
-- for which transitions of
-- TestSignal are allowed to proceed
-- to the "0" state without causing
-- a setup violation.
-- HoldHigh VitalDelayArrayType Absolute minimum time duration
-- after the transition of RefSignal
-- for which transitions of
-- TestSignal are allowed to
-- proceed to the "1" state without
-- causing a hold violation.
-- HoldLow VitalDelayArrayType Absolute minimum time duration
-- after the transition of RefSignal
-- for which transitions of
-- TestSignal are allowed to
-- proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events
-- on the RefSignal which match the
-- edge spec. are used as reference
-- edges.
-- ArcType VitalMemoryArcType
-- NumBitsPerSubWord INTEGER
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output
-- parameter is set to "X".
-- Otherwise, Violation is always
-- set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are
-- generated, even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
-- MsgFormat VitalMemoryMsgFormatType
-- Format of the Test/Reference
-- signals in violation messages.
--
-- INOUT
-- TimingData VitalMemoryTimingDataType
-- VitalMemorySetupHoldCheck information
-- storage area. This is used
-- internally to detect reference
-- edges and record the time of the
-- last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
-- X01ArrayT Overloaded for array type.
--
--
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayType;
CONSTANT SetupLow : IN VitalDelayType;
CONSTANT HoldHigh : IN VitalDelayType;
CONSTANT HoldLow : IN VitalDelayType;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArrayType;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArrayType;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
--------------- following are not needed --------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArrayType;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
-- ----------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_logic_vector Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay VitalDelayArrayType
-- Model's internal delay associated
-- with TestSignal
-- Period VitalDelayArrayType
-- Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh VitalDelayArrayType
-- Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow VitalDelayArrayType
-- Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
-- MsgFormat VitalMemoryMsgFormatType
-- Format of the Test/Reference signals
-- in violation messages.
--
-- INOUT
-- PeriodData VitalPeriodDataArrayType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
-- X01ArrayT Overloaded for array type.
--
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryPeriodPulseCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE PeriodData : INOUT VitalPeriodDataArrayType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
CONSTANT Period : IN VitalDelayArrayType;
CONSTANT PulseWidthHigh : IN VitalDelayArrayType;
CONSTANT PulseWidthLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType
);
PROCEDURE VitalMemoryPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataArrayType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
CONSTANT Period : IN VitalDelayArrayType;
CONSTANT PulseWidthHigh : IN VitalDelayArrayType;
CONSTANT PulseWidthLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType
);
-- ----------------------------------------------------------------------------
-- Functionality Section
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- All Memory Types and Record definitions.
-- ----------------------------------------------------------------------------
TYPE MemoryWordType IS ARRAY (NATURAL RANGE <>) OF UX01;
TYPE MemoryWordPtr IS ACCESS MemoryWordType;
TYPE MemoryArrayType IS ARRAY (NATURAL RANGE <>) OF MemoryWordPtr;
TYPE MemoryArrayPtrType IS ACCESS MemoryArrayType;
TYPE VitalMemoryArrayRecType IS
RECORD
NoOfWords : POSITIVE;
NoOfBitsPerWord : POSITIVE;
NoOfBitsPerSubWord : POSITIVE;
NoOfBitsPerEnable : POSITIVE;
MemoryArrayPtr : MemoryArrayPtrType;
END RECORD;
TYPE VitalMemoryDataType IS ACCESS VitalMemoryArrayRecType;
TYPE VitalTimingDataVectorType IS
ARRAY (NATURAL RANGE <>) OF VitalTimingDataType;
TYPE VitalMemoryViolFlagSizeType IS ARRAY (NATURAL RANGE <>) OF INTEGER;
-- ----------------------------------------------------------------------------
-- Symbol Literals used for Memory Table Modeling
-- ----------------------------------------------------------------------------
-- Symbol literals from '/' to 'S' are closely related to MemoryTableMatch
-- lookup matching and the order cannot be arbitrarily changed.
-- The remaining symbol literals are interpreted directly and matchting is
-- handled in the MemoryMatch procedure itself.
TYPE VitalMemorySymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S', -- steady value
'g', -- Good address (no transition)
'u', -- Unknown address (no transition)
'i', -- Invalid address (no transition)
'G', -- Good address (with transition)
'U', -- Unknown address (with transition)
'I', -- Invalid address (with transition)
'w', -- Write data to memory
's', -- Retain previous memory contents
'c', -- Corrupt entire memory with 'X'
'l', -- Corrupt a word in memory with 'X'
'd', -- Corrupt a single bit in memory with 'X'
'e', -- Corrupt a word with 'X' based on data in
'C', -- Corrupt a sub-word entire memory with 'X'
'L', -- Corrupt a sub-word in memory with 'X'
-- The following entries are commented since their
-- interpretation overlap with existing definitions.
-- 'D', -- Corrupt a single bit of a sub-word with 'X'
-- 'E', -- Corrupt a sub-word with 'X' based on datain
'M', -- Implicit read data from memory
'm', -- Read data from memory
't' -- Immediate assign/transfer data in
);
TYPE VitalMemoryTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalMemorySymbolType;
TYPE VitalMemoryViolationSymbolType IS (
'X', -- Unknown level
'0', -- low level
'-' -- don't care
);
TYPE VitalMemoryViolationTableType IS
ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalMemoryViolationSymbolType;
TYPE VitalPortType IS (
UNDEF,
READ,
WRITE,
RDNWR
);
TYPE VitalCrossPortModeType IS (
CpRead, -- CpReadOnly,
WriteContention, -- WrContOnly,
ReadWriteContention, -- CpContention
CpReadAndWriteContention, -- WrContAndCpRead,
CpReadAndReadContention
);
SUBTYPE VitalAddressValueType IS INTEGER;
TYPE VitalAddressValueVectorType IS
ARRAY (NATURAL RANGE <>) OF VitalAddressValueType;
-- ----------------------------------------------------------------------------
-- Procedure: VitalDeclareMemory
-- Parameters: NoOfWords - Number of words in the memory
-- NoOfBitsPerWord - Number of bits per word in memory
-- NoOfBitsPerSubWord - Number of bits per sub word
-- MemoryLoadFile - Name of data file to load
-- Description: This function is intended to be used to initialize
-- memory data declarations, i.e. to be executed duing
-- simulation elaboration time. Handles the allocation
-- and initialization of memory for the memory data.
-- Default NoOfBitsPerSubWord is NoOfBits.
-- ----------------------------------------------------------------------------
IMPURE FUNCTION VitalDeclareMemory (
CONSTANT NoOfWords : IN POSITIVE;
CONSTANT NoOfBitsPerWord : IN POSITIVE;
CONSTANT NoOfBitsPerSubWord : IN POSITIVE;
CONSTANT MemoryLoadFile : IN string := "";
CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE
) RETURN VitalMemoryDataType;
IMPURE FUNCTION VitalDeclareMemory (
CONSTANT NoOfWords : IN POSITIVE;
CONSTANT NoOfBitsPerWord : IN POSITIVE;
CONSTANT MemoryLoadFile : IN string := "";
CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE
) RETURN VitalMemoryDataType;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryTable
-- Parameters: DataOutBus - Output candidate zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- PrevControls - Previous data in for edge detection
-- PrevEnableBus - Previous enables for edge detection
-- PrevDataInBus - Previous data bus for edge detection
-- PrevAddressBus - Previous address bus for edge detection
-- PortFlag - Indicates port operating mode
-- PortFlagArray - Vector form of PortFlag for sub-word
-- Controls - Agregate of scalar control lines
-- EnableBus - Concatenation of vector control lines
-- DataInBus - Input value of data bus in
-- AddressBus - Input value of address bus in
-- AddressValue - Decoded value of the AddressBus
-- MemoryTable - Input memory action table
-- PortType - The type of port (currently not used)
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- MsgSeverity - Control level of message generation
-- Description: This procedure implements the majority of the memory
-- modeling functionality via lookup of the memory action
-- tables and performing the specified actions if matches
-- are found, or the default actions otherwise. The
-- overloadings are provided for the word and sub-word
-- (using the EnableBus and PortFlagArray arguments) addressing
-- cases.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryTable (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PrevControls : INOUT std_logic_vector;
VARIABLE PrevDataInBus : INOUT std_logic_vector;
VARIABLE PrevAddressBus : INOUT std_logic_vector;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT Controls : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector;
VARIABLE AddressValue : INOUT VitalAddressValueType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType := UNDEF;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalMemoryTable (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PrevControls : INOUT std_logic_vector;
VARIABLE PrevEnableBus : INOUT std_logic_vector;
VARIABLE PrevDataInBus : INOUT std_logic_vector;
VARIABLE PrevAddressBus : INOUT std_logic_vector;
VARIABLE PortFlagArray : INOUT VitalPortFlagVectorType;
CONSTANT Controls : IN std_logic_vector;
CONSTANT EnableBus : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector;
VARIABLE AddressValue : INOUT VitalAddressValueType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType := UNDEF;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryCrossPorts
-- Parameters: DataOutBus - Output candidate zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- SamePortFlag - Operating mode for same port
-- SamePortAddressValue - Decoded AddressBus for same port
-- CrossPortFlagArray - Operating modes for cross ports
-- CrossPortAddressArray - Decoded AddressBus for cross ports
-- CrossPortMode - Write contention and crossport read control
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
--
-- Description: These procedures control the effect of memory operations
-- on a given port due to operations on other ports in a
-- multi-port memory.
-- This includes data write through when reading and writing
-- to the same address, as well as write contention when
-- there are multiple write to the same address.
-- If addresses do not match then data bus is unchanged.
-- The DataOutBus can be diabled with 'Z' value.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryCrossPorts (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE SamePortFlag : INOUT VitalPortFlagVectorType;
CONSTANT SamePortAddressValue : IN VitalAddressValueType;
CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType;
CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType;
CONSTANT CrossPortMode : IN VitalCrossPortModeType
:= CpReadAndWriteContention;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) ;
PROCEDURE VitalMemoryCrossPorts (
VARIABLE MemoryData : INOUT VitalMemoryDataType;
CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType;
CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType;
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) ;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryViolation
-- Parameters: DataOutBus - Output zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- PortFlag - Indicates port operating mode
-- DataInBus - Input value of data bus in
-- AddressValue - Decoded value of the AddressBus
-- ViolationFlags - Aggregate of scalar violation vars
-- ViolationFlagsArray - Concatenation of vector violation vars
-- ViolationTable - Input memory violation table
-- PortType - The type of port (currently not used)
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- MsgSeverity - Control level of message generation
-- Description: This procedure is intended to implement all actions on the
-- memory contents and data out bus as a result of timing viols.
-- It uses the memory action table to perform various corruption
-- policies specified by the user.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryViolation (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressValue : IN VitalAddressValueType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationFlagsArray : IN X01ArrayT;
CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) ;
PROCEDURE VitalMemoryViolation (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressValue : IN VitalAddressValueType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) ;
END Vital_Memory;
| gpl-2.0 | fabd77ddc153b59c38091576ceb5f5d4 | 0.56243 | 5.323714 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/v_split7.vhd | 2 | 1,357 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split7 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v_split7;
architecture augh of v_split7 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 65e38355ad28629ef07d7c4f08255c39 | 0.668386 | 2.856842 | false | false | false | false |
tgingold/ghdl | testsuite/synth/aggr01/tb_aggr03.vhdl | 1 | 494 | entity tb_aggr03 is
end tb_aggr03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_aggr03 is
signal a, b : std_logic_vector(7 downto 0);
begin
dut: entity work.aggr03
port map (a, b);
process
begin
a <= x"ff";
wait for 1 ns;
assert b = x"ff" severity failure;
a <= x"ee";
wait for 1 ns;
assert b = x"ef" severity failure;
a <= x"50";
wait for 1 ns;
assert b = x"53" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 102f38f852e36854d4613f603db417da | 0.61336 | 3.049383 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/lib_fifo_v1_0/hdl/src/vhdl/sync_fifo_fg.vhd | 3 | 70,413 | -- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_0
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_0;
use fifo_generator_v13_1_0.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_0.fifo_generator_v13_1_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
| gpl-3.0 | b346c6b7e39985d760e9c8b6dfce1905 | 0.425447 | 3.862056 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug035/strings.vhdl | 2 | 30,372 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- digit subtypes incl. error value (-1)
subtype T_DIGIT_BIN is INTEGER range -1 to 1;
subtype T_DIGIT_OCT is INTEGER range -1 to 7;
subtype T_DIGIT_DEC is INTEGER range -1 to 9;
subtype T_DIGIT_HEX is INTEGER range -1 to 15;
-- to_digit*
function to_digit_bin(chr : character) return T_DIGIT_BIN;
function to_digit_oct(chr : character) return T_DIGIT_OCT;
function to_digit_dec(chr : character) return T_DIGIT_DEC;
function to_digit_hex(chr : character) return T_DIGIT_HEX;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return T_DIGIT_BIN is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return T_DIGIT_OCT is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return T_DIGIT_DEC is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return T_DIGIT_HEX is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then -- workaround for Quartus II
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
| gpl-2.0 | 1294bace46a13a2fdeebef47399349e5 | 0.632128 | 3.214308 | false | false | false | false |
tgingold/ghdl | testsuite/synth/forgen01/forgen03.vhdl | 1 | 896 | library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (a, b, ci : std_logic;
o, co : out std_logic);
end fulladder;
architecture behav of fulladder is
begin
o <= a xor b xor ci;
co <= (a and b) or (a and ci) or (b and ci);
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity forgen03 is
generic (l : natural := 8;
structural : boolean := true);
port (a, b : std_logic_vector (l - 1 downto 0);
o : out std_logic_vector (l - 1 downto 0));
end forgen03;
architecture behav of forgen03
is
begin
gstr: if structural generate
signal carry : std_logic_vector (l downto 0);
begin
carry (0) <= '0';
gadd: for i in 0 to l - 1 generate
iadd: entity work.fulladder
port map (a => a (i), b => b (i), ci => carry (i),
o => o (i), co => carry (i + 1));
end generate;
end generate;
end behav;
| gpl-2.0 | 2ff76575bfd22a4d3cd69f3baf4a0fbc | 0.595982 | 3.132867 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd | 4 | 2,310 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
architecture test of inline_08 is
begin
process_2_c : process is
-- code from book:
type opcodes is
(nop, add, subtract, load, store, jump, jumpsub, branch, halt);
subtype control_transfer_opcodes is opcodes range jump to branch;
-- end of code from book
variable opcode : opcodes;
variable operand : integer;
constant memory_operand : integer := 1;
constant address_operand : integer := 2;
begin
for i in opcodes loop
opcode := i;
-- code from book:
case opcode is
when load | add | subtract =>
operand := memory_operand;
when store | jump | jumpsub | branch =>
operand := address_operand;
when others =>
operand := 0;
end case;
--
case opcode is
when add to load =>
operand := memory_operand;
when branch downto store =>
operand := address_operand;
when others =>
operand := 0;
end case;
-- end of code from book
case opcode is
when add to load =>
operand := memory_operand;
-- code from book:
when control_transfer_opcodes | store =>
operand := address_operand;
-- end of code from book
when others =>
operand := 0;
end case;
end loop;
wait;
end process process_2_c;
end architecture test;
| gpl-2.0 | b28d777e61fcbde7190686c446c64e29 | 0.610823 | 4.529412 | false | false | false | false |
tgingold/ghdl | libraries/openieee/v08/std_logic_1164.vhdl | 1 | 10,923 | -- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
-- on the specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
use std.textio.all;
package std_logic_1164 is
-- Unresolved logic state.
type std_ulogic is
(
'U', -- Uninitialized, this is also the default value.
'X', -- Unknown / conflict value (forcing level).
'0', -- 0 (forcing level).
'1', -- 1 (forcing level).
'Z', -- High impedance.
'W', -- Unknown / conflict (weak level).
'L', -- 0 (weak level).
'H', -- 1 (weak level).
'-' -- Don't care.
);
-- Vector of logic state.
type std_ulogic_vector is array (natural range <>) of std_ulogic;
-- Resolution function.
-- If S is empty, returns 'Z'.
-- If S has one element, return the element.
-- Otherwise, 'U' is the strongest.
-- then 'X'
-- then '0' and '1'
-- then 'W'
-- then 'H' and 'L'
-- then 'Z'.
function resolved (s : std_ulogic_vector) return std_ulogic;
-- Resolved logic state.
subtype std_logic is resolved std_ulogic;
-- Vector of std_logic.
subtype std_logic_vector is (resolved) std_ulogic_vector;
-- Subtypes of std_ulogic. The names give the values.
subtype X01 is resolved std_ulogic range 'X' to '1';
subtype X01Z is resolved std_ulogic range 'X' to 'Z';
subtype UX01 is resolved std_ulogic range 'U' to '1';
subtype UX01Z is resolved std_ulogic range 'U' to 'Z';
-- Logical operators.
-- For logical operations, the inputs are first normalized to UX01:
-- 0 and L are normalized to 0, 1 and 1 are normalized to 1, U isnt changed,
-- all other states are normalized to X.
-- Then the classical electric rules are followed.
function "and" (l : std_ulogic; r : std_ulogic) return UX01;
function "nand" (l : std_ulogic; r : std_ulogic) return UX01;
function "or" (l : std_ulogic; r : std_ulogic) return UX01;
function "nor" (l : std_ulogic; r : std_ulogic) return UX01;
function "xor" (l : std_ulogic; r : std_ulogic) return UX01;
function "xnor" (l : std_ulogic; r : std_ulogic) return UX01;
function "not" (l : std_ulogic) return UX01;
-- Logical operators for vectors.
-- An assertion of severity failure fails if the length of L and R aren't
-- equal. The result range is 1 to L'Length.
function "and" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "or" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "not" (l : std_ulogic_vector) return std_ulogic_vector;
function "and" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "and" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "nand" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "nand" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "or" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "or" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "nor" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "nor" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "xor" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "xor" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "xnor" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "xnor" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "and" (l : std_ulogic_vector) return std_ulogic;
function "nand" (l : std_ulogic_vector) return std_ulogic;
function "or" (l : std_ulogic_vector) return std_ulogic;
function "nor" (l : std_ulogic_vector) return std_ulogic;
function "xor" (l : std_ulogic_vector) return std_ulogic;
function "xnor" (l : std_ulogic_vector) return std_ulogic;
function "sll" (l : std_ulogic_vector; r : integer)
return std_ulogic_vector;
function "srl" (l : std_ulogic_vector; r : integer)
return std_ulogic_vector;
function "rol" (l : std_ulogic_vector; r : integer)
return std_ulogic_vector;
function "ror" (l : std_ulogic_vector; r : integer)
return std_ulogic_vector;
-- Conversion functions.
-- The result range (for vectors) is S'Length - 1 downto 0.
-- XMAP is return for values not in '0', '1', 'L', 'H'.
function to_bit (s : std_ulogic; xmap : bit := '0') return bit;
function to_bitvector (s : std_ulogic_vector; xmap : bit := '0')
return bit_vector;
function to_stdulogic (b : bit) return std_ulogic;
function to_stdlogicvector (b : bit_vector) return std_logic_vector;
function to_stdlogicvector (s : std_ulogic_vector) return std_logic_vector;
function to_stdulogicvector (b : bit_vector) return std_ulogic_vector;
function to_stdulogicvector (s : std_logic_vector) return std_ulogic_vector;
alias to_bit_vector is
to_bitvector[std_ulogic_vector, bit return bit_vector];
alias to_bv is
to_bitvector[std_ulogic_vector, bit return bit_vector];
alias to_std_logic_vector is
to_stdlogicvector[bit_vector return std_logic_vector];
alias to_slv is
to_stdlogicvector[bit_vector return std_logic_vector];
alias to_std_logic_vector is
to_stdlogicvector[std_ulogic_vector return std_logic_vector];
alias to_slv is
to_stdlogicvector[std_ulogic_vector return std_logic_vector];
alias to_std_ulogic_vector is
to_stdulogicvector[bit_vector return std_ulogic_vector];
alias to_sulv is
to_stdulogicvector[bit_vector return std_ulogic_vector];
alias to_std_ulogic_vector is
to_stdulogicvector[std_logic_vector return std_ulogic_vector];
alias to_sulv is
to_stdulogicvector[std_logic_vector return std_ulogic_vector];
-- Normalization.
-- The result range (for vectors) is 1 to S'Length.
function to_01 (s : std_ulogic_vector; xmap : std_ulogic := '0')
return std_ulogic_vector;
function to_01 (s : std_ulogic; xmap : std_ulogic := '0')
return std_ulogic;
function to_01 (s : bit_vector; xmap : std_ulogic := '0')
return std_ulogic_vector;
function to_01 (s : bit; xmap : std_ulogic := '0')
return std_ulogic;
function to_X01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01 (s : std_ulogic) return X01;
function to_X01 (b : bit_vector) return std_ulogic_vector;
function to_X01 (b : bit) return X01;
function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01Z (s : std_ulogic) return X01Z;
function to_X01Z (b : bit_vector) return std_ulogic_vector;
function to_X01Z (b : bit) return X01Z;
function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_UX01 (s : std_ulogic) return UX01;
function to_UX01 (b : bit_vector) return std_ulogic_vector;
function to_UX01 (b : bit) return UX01;
function "??" (l : std_ulogic) return boolean;
-- Edge detection.
-- An edge is detected in case of event on s, and X01 normalized value
-- rises from 0 to 1 or falls from 1 to 0.
function rising_edge (signal s : std_ulogic) return boolean;
function falling_edge (signal s : std_ulogic) return boolean;
-- Test for unknown. Only 0, 1, L and H are known values.
function is_X (s : std_ulogic_vector) return boolean;
function is_X (s : std_ulogic) return boolean;
-- String conversion
alias to_bstring is to_string [std_ulogic_vector return string];
alias to_binary_string is to_string [std_ulogic_vector return string];
function to_ostring (value : std_ulogic_vector) return string;
alias to_octal_string is to_ostring [std_ulogic_vector return string];
function to_hstring (value : std_ulogic_vector) return string;
alias to_hex_string is to_hstring [std_ulogic_vector return string];
-- Input/output
procedure write (l : inout line; value : std_ulogic;
justified : side := right; field : width := 0);
procedure write (l : inout line; value : std_ulogic_vector;
justified : side := right; field : width := 0);
alias bwrite is write [line, std_ulogic_vector, side, width];
alias binary_write is write [line, std_ulogic_vector, side, width];
procedure owrite (l : inout line; value : std_ulogic_vector;
justified : side := right; field : width := 0);
alias octal_write is owrite [line, std_ulogic_vector, side, width];
procedure hwrite (l : inout line; value : std_ulogic_vector;
justified : side := right; field : width := 0);
alias hex_write is hwrite [line, std_ulogic_vector, side, width];
procedure read (l : inout line;
value : out std_ulogic; good : out boolean);
procedure read (l : inout line; value : out std_ulogic);
procedure read (l : inout line;
value : out std_ulogic_vector; good : out boolean);
procedure read (l : inout line; value : out std_ulogic_vector);
alias bread is read [line, std_ulogic_vector, boolean];
alias bread is read [line, std_ulogic_vector];
alias binary_read is read [line, std_ulogic_vector, boolean];
alias binary_read is read [line, std_ulogic_vector];
procedure hread (l : inout line;
value : out std_ulogic_vector; good : out boolean);
procedure hread (l : inout line; value : out std_ulogic_vector);
alias hex_read is read [line, std_ulogic_vector, boolean];
alias hex_read is read [line, std_ulogic_vector];
procedure oread (l : inout line;
value : out std_ulogic_vector; good : out boolean);
procedure oread (l : inout line; value : out std_ulogic_vector);
alias octal_read is read [line, std_ulogic_vector, boolean];
alias octal_read is read [line, std_ulogic_vector];
end std_logic_1164;
| gpl-2.0 | 52c9f7fac8c13f912a8d98e43f9c47e4 | 0.663096 | 3.421992 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/tb_asgn07.vhdl | 1 | 940 | entity tb_asgn07 is
end tb_asgn07;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn07 is
signal s0 : std_logic;
signal clk : std_logic;
signal r : std_logic_vector (65 downto 0);
begin
dut: entity work.asgn07
port map (clk => clk, s0 => s0, r => r);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
s0 <= '0';
pulse;
assert r (0) = '0' severity failure;
assert r (65) = '0' severity failure;
s0 <= '1';
pulse;
assert r (0) = '1' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cccc" severity failure;
assert r (65) = '1' severity failure;
s0 <= '0';
pulse;
assert r (0) = '0' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cc7c" severity failure;
assert r (65) = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 841ea720c38e4314adcba1c874162448 | 0.588298 | 3.092105 | false | false | false | false |
mistryalok/FPGA | Xilinx/ISE/Basics/dEMUX8x1/demux1x8.vhd | 1 | 1,252 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:23 04/04/2013
-- Design Name:
-- Module Name: demux1x8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity demux1x8 is
Port ( i : in STD_LOGIC;
o : out std_logic_VECTOR (7 downto 0);
s : in bit_VECTOR (2 downto 0));
end demux1x8;
architecture Behavioral of demux1x8 is
begin
process(S)
begin
case s is
when "000" => o(0) <= i;
when "001" => o(1) <= i;
when "010" => o(2) <= i;
when "011" => o(3) <= i;
when "100" => o(4) <= i;
when "101" => o(5) <= i;
when "110" => o(6) <= i;
when "111" => o(7) <= i;
end case;
end process;
end Behavioral;
| gpl-3.0 | e55c40009cb84aed064a5752aed01bd5 | 0.51278 | 3.226804 | false | false | false | false |
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