repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_cntrl_strm.vhd | 7 | 25,041 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_fifo_v1_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
| gpl-3.0 | 22cb06941e36f0d717ca2c138efff75a | 0.441835 | 4.114525 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/bd/design_1/hdl/design_1.vhd | 1 | 376,192 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016
--Date : Wed Jun 22 01:41:53 2016
--Host : darkin-UX303LN running 64-bit elementary OS Freya
--Command : generate_target design_1.bd
--Design : design_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1R706YB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1R706YB;
architecture STRUCTURE of m00_couplers_imp_1R706YB is
component design_1_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= auto_pc_to_m00_couplers_ARID(0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= auto_pc_to_m00_couplers_AWID(0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(63 downto 0) <= auto_pc_to_m00_couplers_WDATA(63 downto 0);
M_AXI_wid(0) <= auto_pc_to_m00_couplers_WID(0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_pc_to_m00_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(0) <= m00_couplers_to_auto_pc_BID(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(63 downto 0) <= m00_couplers_to_auto_pc_RDATA(63 downto 0);
S_AXI_rid(0) <= m00_couplers_to_auto_pc_RID(0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(63 downto 0) <= S_AXI_wdata(63 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(7 downto 0) <= S_AXI_wstrb(7 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_1_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => auto_pc_to_m00_couplers_ARID(0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => auto_pc_to_m00_couplers_AWID(0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(0) => auto_pc_to_m00_couplers_BID(0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => auto_pc_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(0) => auto_pc_to_m00_couplers_RID(0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => auto_pc_to_m00_couplers_WDATA(63 downto 0),
m_axi_wid(0) => auto_pc_to_m00_couplers_WID(0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_pc_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(0) => m00_couplers_to_auto_pc_ARID(0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(0) => m00_couplers_to_auto_pc_AWID(0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(0) => m00_couplers_to_auto_pc_BID(0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(63 downto 0) => m00_couplers_to_auto_pc_RDATA(63 downto 0),
s_axi_rid(0) => m00_couplers_to_auto_pc_RID(0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(63 downto 0) => m00_couplers_to_auto_pc_WDATA(63 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(7 downto 0) => m00_couplers_to_auto_pc_WSTRB(7 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_OBU1DD is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_OBU1DD;
architecture STRUCTURE of m00_couplers_imp_OBU1DD is
component design_1_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= m00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= m00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_1_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => NLW_auto_pc_m_axi_wstrb_UNCONNECTED(3 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => m00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => m00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => m00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => m00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1FBREZ4 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1FBREZ4;
architecture STRUCTURE of m01_couplers_imp_1FBREZ4 is
component design_1_auto_pc_2 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_pc_2;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m01_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m01_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m01_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m01_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m01_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m01_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m01_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m01_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m01_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m01_couplers_WVALID : STD_LOGIC;
signal m01_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m01_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m01_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m01_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m01_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m01_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m01_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m01_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m01_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m01_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m01_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m01_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m01_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m01_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m01_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m01_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_m01_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m01_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m01_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m01_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m01_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= m01_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= m01_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= m01_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m01_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m01_couplers_to_auto_pc_WREADY;
auto_pc_to_m01_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m01_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m01_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m01_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m01_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m01_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
m01_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m01_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m01_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m01_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m01_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m01_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m01_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m01_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m01_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
m01_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m01_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m01_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m01_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m01_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m01_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m01_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m01_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m01_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m01_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_1_auto_pc_2
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m01_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_m01_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_m01_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m01_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_m01_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_m01_couplers_AWVALID,
m_axi_bready => auto_pc_to_m01_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m01_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m01_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m01_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_m01_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m01_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m01_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m01_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_m01_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m01_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m01_couplers_WVALID,
s_axi_araddr(31 downto 0) => m01_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m01_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m01_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => m01_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(7 downto 0) => m01_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m01_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m01_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m01_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m01_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m01_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m01_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m01_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m01_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m01_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m01_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => m01_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(7 downto 0) => m01_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m01_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m01_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m01_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m01_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m01_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m01_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m01_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => m01_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => m01_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m01_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m01_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m01_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => m01_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => m01_couplers_to_auto_pc_RLAST,
s_axi_rready => m01_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m01_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m01_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m01_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m01_couplers_to_auto_pc_WLAST,
s_axi_wready => m01_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m01_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m01_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_MVV5YQ is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_MVV5YQ;
architecture STRUCTURE of m02_couplers_imp_MVV5YQ is
component design_1_auto_pc_3 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_pc_3;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m02_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m02_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m02_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m02_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m02_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m02_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m02_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m02_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m02_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m02_couplers_WVALID : STD_LOGIC;
signal m02_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m02_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m02_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m02_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m02_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m02_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m02_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m02_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m02_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m02_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m02_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m02_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m02_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m02_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m02_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m02_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m02_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m02_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_m02_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m02_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m02_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m02_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m02_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= m02_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= m02_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= m02_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= m02_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m02_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m02_couplers_to_auto_pc_WREADY;
auto_pc_to_m02_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m02_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m02_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m02_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m02_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m02_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
m02_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m02_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m02_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m02_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m02_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m02_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m02_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m02_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m02_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m02_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
m02_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m02_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m02_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m02_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m02_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m02_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m02_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m02_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m02_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m02_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m02_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_1_auto_pc_3
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m02_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_m02_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_m02_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m02_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_m02_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_m02_couplers_AWVALID,
m_axi_bready => auto_pc_to_m02_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m02_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m02_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m02_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_m02_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m02_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m02_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m02_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_m02_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m02_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m02_couplers_WVALID,
s_axi_araddr(31 downto 0) => m02_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m02_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m02_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => m02_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(7 downto 0) => m02_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m02_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m02_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m02_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m02_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m02_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m02_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m02_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m02_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m02_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m02_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => m02_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(7 downto 0) => m02_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m02_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m02_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m02_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m02_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m02_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m02_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m02_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => m02_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => m02_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m02_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m02_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m02_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => m02_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => m02_couplers_to_auto_pc_RLAST,
s_axi_rready => m02_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m02_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m02_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m02_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m02_couplers_to_auto_pc_WLAST,
s_axi_wready => m02_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m02_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m02_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1GHG26R is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC;
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC;
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC;
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1GHG26R;
architecture STRUCTURE of m03_couplers_imp_1GHG26R is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m03_couplers_to_m03_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m03_couplers_to_m03_couplers_ARLOCK : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m03_couplers_to_m03_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m03_couplers_to_m03_couplers_AWLOCK : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m03_couplers_to_m03_couplers_RLAST : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WLAST : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= m03_couplers_to_m03_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= m03_couplers_to_m03_couplers_ARCACHE(3 downto 0);
M_AXI_arid(11 downto 0) <= m03_couplers_to_m03_couplers_ARID(11 downto 0);
M_AXI_arlen(7 downto 0) <= m03_couplers_to_m03_couplers_ARLEN(7 downto 0);
M_AXI_arlock <= m03_couplers_to_m03_couplers_ARLOCK;
M_AXI_arprot(2 downto 0) <= m03_couplers_to_m03_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= m03_couplers_to_m03_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= m03_couplers_to_m03_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= m03_couplers_to_m03_couplers_AWCACHE(3 downto 0);
M_AXI_awid(11 downto 0) <= m03_couplers_to_m03_couplers_AWID(11 downto 0);
M_AXI_awlen(7 downto 0) <= m03_couplers_to_m03_couplers_AWLEN(7 downto 0);
M_AXI_awlock <= m03_couplers_to_m03_couplers_AWLOCK;
M_AXI_awprot(2 downto 0) <= m03_couplers_to_m03_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= m03_couplers_to_m03_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wlast <= m03_couplers_to_m03_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bid(11 downto 0) <= m03_couplers_to_m03_couplers_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= m03_couplers_to_m03_couplers_RID(11 downto 0);
S_AXI_rlast <= m03_couplers_to_m03_couplers_RLAST;
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m03_couplers_to_m03_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m03_couplers_to_m03_couplers_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
m03_couplers_to_m03_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m03_couplers_to_m03_couplers_ARLOCK <= S_AXI_arlock;
m03_couplers_to_m03_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m03_couplers_to_m03_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m03_couplers_to_m03_couplers_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
m03_couplers_to_m03_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m03_couplers_to_m03_couplers_AWLOCK <= S_AXI_awlock;
m03_couplers_to_m03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BID(11 downto 0) <= M_AXI_bid(11 downto 0);
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RID(11 downto 0) <= M_AXI_rid(11 downto 0);
m03_couplers_to_m03_couplers_RLAST <= M_AXI_rlast;
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WLAST <= S_AXI_wlast;
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_PJ7QT3 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_PJ7QT3;
architecture STRUCTURE of m04_couplers_imp_PJ7QT3 is
component design_1_auto_pc_4 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_pc_4;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m04_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m04_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m04_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m04_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m04_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m04_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m04_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m04_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m04_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m04_couplers_WVALID : STD_LOGIC;
signal m04_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m04_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m04_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m04_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m04_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m04_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m04_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m04_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m04_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m04_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m04_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m04_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m04_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m04_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m04_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m04_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m04_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m04_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_m04_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m04_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m04_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m04_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m04_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= m04_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= m04_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= m04_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= m04_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m04_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m04_couplers_to_auto_pc_WREADY;
auto_pc_to_m04_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m04_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m04_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m04_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m04_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m04_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
m04_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m04_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m04_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m04_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m04_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m04_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m04_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m04_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m04_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m04_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
m04_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m04_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m04_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m04_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m04_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m04_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m04_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m04_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m04_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m04_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m04_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_1_auto_pc_4
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m04_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_m04_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_m04_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m04_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_m04_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_m04_couplers_AWVALID,
m_axi_bready => auto_pc_to_m04_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m04_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m04_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m04_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_m04_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m04_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m04_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m04_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_m04_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m04_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m04_couplers_WVALID,
s_axi_araddr(31 downto 0) => m04_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m04_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m04_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => m04_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(7 downto 0) => m04_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m04_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m04_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m04_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m04_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m04_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m04_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m04_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m04_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m04_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m04_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => m04_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(7 downto 0) => m04_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m04_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m04_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m04_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m04_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m04_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m04_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m04_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => m04_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => m04_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m04_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m04_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m04_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => m04_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => m04_couplers_to_auto_pc_RLAST,
s_axi_rready => m04_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m04_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m04_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m04_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m04_couplers_to_auto_pc_WLAST,
s_axi_wready => m04_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m04_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m04_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1CFO1MB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1CFO1MB;
architecture STRUCTURE of s00_couplers_imp_1CFO1MB is
component design_1_auto_pc_5 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_pc_5;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_pc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(11 downto 0) <= auto_pc_to_s00_couplers_ARID(11 downto 0);
M_AXI_arlen(7 downto 0) <= auto_pc_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_pc_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(11 downto 0) <= auto_pc_to_s00_couplers_AWID(11 downto 0);
M_AXI_awlen(7 downto 0) <= auto_pc_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_pc_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wlast <= auto_pc_to_s00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BID(11 downto 0) <= M_AXI_bid(11 downto 0);
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RID(11 downto 0) <= M_AXI_rid(11 downto 0);
auto_pc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_1_auto_pc_5
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arid(11 downto 0) => auto_pc_to_s00_couplers_ARID(11 downto 0),
m_axi_arlen(7 downto 0) => auto_pc_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_pc_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_pc_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_pc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awid(11 downto 0) => auto_pc_to_s00_couplers_AWID(11 downto 0),
m_axi_awlen(7 downto 0) => auto_pc_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_pc_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_s00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_pc_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_pc_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bid(11 downto 0) => auto_pc_to_s00_couplers_BID(11 downto 0),
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rid(11 downto 0) => auto_pc_to_s00_couplers_RID(11 downto 0),
m_axi_rlast => auto_pc_to_s00_couplers_RLAST,
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wlast => auto_pc_to_s00_couplers_WLAST,
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_7HNO1D is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s00_couplers_imp_7HNO1D;
architecture STRUCTURE of s00_couplers_imp_7HNO1D is
component design_1_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_us_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_RVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID;
M_AXI_rready <= auto_us_to_s00_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_us_ARREADY;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID;
auto_us_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_us_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_us_RREADY <= S_AXI_rready;
auto_us: component design_1_auto_us_0
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s00_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_us_to_s00_couplers_RLAST,
m_axi_rready => auto_us_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s00_couplers_RVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1(0),
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s00_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_us_ARVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s00_couplers_to_auto_us_RLAST,
s_axi_rready => s00_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_us_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1W60HW0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1W60HW0;
architecture STRUCTURE of s01_couplers_imp_1W60HW0 is
component design_1_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC
);
end component design_1_auto_us_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s01_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s01_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_WVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s01_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_awaddr(31 downto 0) <= auto_us_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s01_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s01_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s01_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s01_couplers_BREADY;
M_AXI_wdata(63 downto 0) <= auto_us_to_s01_couplers_WDATA(63 downto 0);
M_AXI_wlast <= auto_us_to_s01_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_us_to_s01_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_us_to_s01_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_awready <= s01_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_auto_us_BVALID;
S_AXI_wready <= s01_couplers_to_auto_us_WREADY;
auto_us_to_s01_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s01_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s01_couplers_to_auto_us_BREADY <= S_AXI_bready;
s01_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s01_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
auto_us: component design_1_auto_us_1
port map (
m_axi_awaddr(31 downto 0) => auto_us_to_s01_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s01_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s01_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s01_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s01_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s01_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s01_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s01_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s01_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s01_couplers_AWVALID,
m_axi_bready => auto_us_to_s01_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s01_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s01_couplers_BVALID,
m_axi_wdata(63 downto 0) => auto_us_to_s01_couplers_WDATA(63 downto 0),
m_axi_wlast => auto_us_to_s01_couplers_WLAST,
m_axi_wready => auto_us_to_s01_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_us_to_s01_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_us_to_s01_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_aresetn => S_ARESETN_1(0),
s_axi_awaddr(31 downto 0) => s01_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s01_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s01_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s01_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s01_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => s01_couplers_to_auto_us_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s01_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s01_couplers_to_auto_us_AWVALID,
s_axi_bready => s01_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s01_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s01_couplers_to_auto_us_BVALID,
s_axi_wdata(31 downto 0) => s01_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s01_couplers_to_auto_us_WLAST,
s_axi_wready => s01_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s01_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s01_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC
);
end design_1_axi_mem_intercon_0;
architecture STRUCTURE of design_1_axi_mem_intercon_0 is
component design_1_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC;
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 64 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(63 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0);
M00_AXI_wid(0) <= m00_couplers_to_axi_mem_intercon_WID(0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(7 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_awready <= axi_mem_intercon_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= axi_mem_intercon_to_s01_couplers_BVALID;
S01_AXI_wready <= axi_mem_intercon_to_s01_couplers_WREADY;
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
axi_mem_intercon_to_s01_couplers_BREADY <= S01_AXI_bready;
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST <= S01_AXI_wlast;
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID <= S01_AXI_wvalid;
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0);
m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1R706YB
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0),
M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0),
M_AXI_wid(0) => m00_couplers_to_axi_mem_intercon_WID(0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(7 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(0) => xbar_to_m00_couplers_BID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
S_AXI_rid(0) => xbar_to_m00_couplers_RID(0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_7HNO1D
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID
);
s01_couplers: entity work.s01_couplers_imp_1W60HW0
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s01_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s01_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_wdata(63 downto 0) => s01_couplers_to_xbar_WDATA(63 downto 0),
M_AXI_wlast => s01_couplers_to_xbar_WLAST,
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(7 downto 0) => s01_couplers_to_xbar_WSTRB(7 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s01_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s01_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s01_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s01_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s01_couplers_WVALID
);
xbar: component design_1_xbar_1
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => xbar_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => xbar_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(0) => xbar_to_m00_couplers_BID(0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(0) => xbar_to_m00_couplers_RID(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(3 downto 2) => B"00",
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(7 downto 4) => B"0000",
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(1 downto 0) => B"00",
s_axi_arlen(15 downto 8) => B"00000000",
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(1) => '0',
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(5 downto 3) => B"000",
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(7 downto 4) => B"0000",
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(5 downto 3) => B"000",
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(1) => '0',
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(1 downto 0) => B"00",
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1) => s01_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(0) => '0',
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(7 downto 4) => s01_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0),
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => '0',
s_axi_bid(1 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(1 downto 0),
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => '0',
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0),
s_axi_rdata(127 downto 64) => NLW_xbar_s_axi_rdata_UNCONNECTED(127 downto 64),
s_axi_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
s_axi_rid(1 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(1 downto 0),
s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(1) => '0',
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(127 downto 64) => s01_couplers_to_xbar_WDATA(63 downto 0),
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST,
s_axi_wlast(0) => '1',
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0),
s_axi_wstrb(15 downto 8) => s01_couplers_to_xbar_WSTRB(7 downto 0),
s_axi_wstrb(7 downto 0) => B"11111111",
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M03_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M03_AXI_arlock : out STD_LOGIC;
M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M03_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M03_AXI_awlock : out STD_LOGIC;
M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M03_AXI_rlast : in STD_LOGIC;
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wlast : out STD_LOGIC;
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_1_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_1_processing_system7_0_axi_periph_0 is
component design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 59 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 14 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 9 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 59 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 59 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 14 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 9 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 59 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component design_1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARLOCK : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWLOCK : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RLAST : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WLAST : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WLAST : STD_LOGIC;
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARBURST : STD_LOGIC_VECTOR ( 3 downto 2 );
signal xbar_to_m01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_ARID : STD_LOGIC_VECTOR ( 23 downto 12 );
signal xbar_to_m01_couplers_ARLEN : STD_LOGIC_VECTOR ( 15 downto 8 );
signal xbar_to_m01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARQOS : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARREGION : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWBURST : STD_LOGIC_VECTOR ( 3 downto 2 );
signal xbar_to_m01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_AWID : STD_LOGIC_VECTOR ( 23 downto 12 );
signal xbar_to_m01_couplers_AWLEN : STD_LOGIC_VECTOR ( 15 downto 8 );
signal xbar_to_m01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWQOS : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWREGION : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m01_couplers_RLAST : STD_LOGIC;
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WLAST : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARBURST : STD_LOGIC_VECTOR ( 5 downto 4 );
signal xbar_to_m02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_ARID : STD_LOGIC_VECTOR ( 35 downto 24 );
signal xbar_to_m02_couplers_ARLEN : STD_LOGIC_VECTOR ( 23 downto 16 );
signal xbar_to_m02_couplers_ARLOCK : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_ARQOS : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARREGION : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWBURST : STD_LOGIC_VECTOR ( 5 downto 4 );
signal xbar_to_m02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_AWID : STD_LOGIC_VECTOR ( 35 downto 24 );
signal xbar_to_m02_couplers_AWLEN : STD_LOGIC_VECTOR ( 23 downto 16 );
signal xbar_to_m02_couplers_AWLOCK : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_AWQOS : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWREGION : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m02_couplers_RLAST : STD_LOGIC;
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WLAST : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARBURST : STD_LOGIC_VECTOR ( 7 downto 6 );
signal xbar_to_m03_couplers_ARCACHE : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_ARID : STD_LOGIC_VECTOR ( 47 downto 36 );
signal xbar_to_m03_couplers_ARLEN : STD_LOGIC_VECTOR ( 31 downto 24 );
signal xbar_to_m03_couplers_ARLOCK : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARSIZE : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWBURST : STD_LOGIC_VECTOR ( 7 downto 6 );
signal xbar_to_m03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_AWID : STD_LOGIC_VECTOR ( 47 downto 36 );
signal xbar_to_m03_couplers_AWLEN : STD_LOGIC_VECTOR ( 31 downto 24 );
signal xbar_to_m03_couplers_AWLOCK : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m03_couplers_RLAST : STD_LOGIC;
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WLAST : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARBURST : STD_LOGIC_VECTOR ( 9 downto 8 );
signal xbar_to_m04_couplers_ARCACHE : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_ARID : STD_LOGIC_VECTOR ( 59 downto 48 );
signal xbar_to_m04_couplers_ARLEN : STD_LOGIC_VECTOR ( 39 downto 32 );
signal xbar_to_m04_couplers_ARLOCK : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_ARPROT : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_ARQOS : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARREGION : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_ARSIZE : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWBURST : STD_LOGIC_VECTOR ( 9 downto 8 );
signal xbar_to_m04_couplers_AWCACHE : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_AWID : STD_LOGIC_VECTOR ( 59 downto 48 );
signal xbar_to_m04_couplers_AWLEN : STD_LOGIC_VECTOR ( 39 downto 32 );
signal xbar_to_m04_couplers_AWLOCK : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWPROT : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_AWQOS : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWREGION : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_AWSIZE : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal xbar_to_m04_couplers_RLAST : STD_LOGIC;
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WLAST : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal NLW_xbar_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 );
signal NLW_xbar_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 );
signal NLW_xbar_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 );
signal NLW_xbar_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
M00_AXI_bready <= m00_couplers_to_processing_system7_0_axi_periph_BREADY;
M00_AXI_rready <= m00_couplers_to_processing_system7_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wvalid <= m00_couplers_to_processing_system7_0_axi_periph_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_processing_system7_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_processing_system7_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_processing_system7_0_axi_periph_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1(0) <= M03_ARESETN(0);
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arburst(1 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARBURST(1 downto 0);
M03_AXI_arcache(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARCACHE(3 downto 0);
M03_AXI_arid(11 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARID(11 downto 0);
M03_AXI_arlen(7 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARLEN(7 downto 0);
M03_AXI_arlock <= m03_couplers_to_processing_system7_0_axi_periph_ARLOCK;
M03_AXI_arprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M03_AXI_arsize(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARSIZE(2 downto 0);
M03_AXI_arvalid <= m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awburst(1 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWBURST(1 downto 0);
M03_AXI_awcache(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWCACHE(3 downto 0);
M03_AXI_awid(11 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWID(11 downto 0);
M03_AXI_awlen(7 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWLEN(7 downto 0);
M03_AXI_awlock <= m03_couplers_to_processing_system7_0_axi_periph_AWLOCK;
M03_AXI_awprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M03_AXI_awsize(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWSIZE(2 downto 0);
M03_AXI_awvalid <= m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_processing_system7_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_processing_system7_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wlast <= m03_couplers_to_processing_system7_0_axi_periph_WLAST;
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_processing_system7_0_axi_periph_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1(0) <= M04_ARESETN(0);
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_processing_system7_0_axi_periph_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_processing_system7_0_axi_periph_AWVALID;
M04_AXI_bready <= m04_couplers_to_processing_system7_0_axi_periph_BREADY;
M04_AXI_rready <= m04_couplers_to_processing_system7_0_axi_periph_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY <= M00_AXI_arready;
m00_couplers_to_processing_system7_0_axi_periph_AWREADY <= M00_AXI_awready;
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID <= M00_AXI_bvalid;
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID <= M00_AXI_rvalid;
m00_couplers_to_processing_system7_0_axi_periph_WREADY <= M00_AXI_wready;
m01_couplers_to_processing_system7_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_processing_system7_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_processing_system7_0_axi_periph_WREADY <= M01_AXI_wready;
m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready;
m03_couplers_to_processing_system7_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_processing_system7_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_processing_system7_0_axi_periph_BID(11 downto 0) <= M03_AXI_bid(11 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RID(11 downto 0) <= M03_AXI_rid(11 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RLAST <= M03_AXI_rlast;
m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_processing_system7_0_axi_periph_WREADY <= M03_AXI_wready;
m04_couplers_to_processing_system7_0_axi_periph_ARREADY <= M04_AXI_arready;
m04_couplers_to_processing_system7_0_axi_periph_AWREADY <= M04_AXI_awready;
m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_BVALID <= M04_AXI_bvalid;
m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RVALID <= M04_AXI_rvalid;
m04_couplers_to_processing_system7_0_axi_periph_WREADY <= M04_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_OBU1DD
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m00_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m00_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m00_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m00_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m00_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m00_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => xbar_to_m00_couplers_ARID(11 downto 0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => xbar_to_m00_couplers_AWID(11 downto 0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(11 downto 0) => xbar_to_m00_couplers_BID(11 downto 0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => xbar_to_m00_couplers_RID(11 downto 0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1FBREZ4
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m01_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m01_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arburst(1 downto 0) => xbar_to_m01_couplers_ARBURST(3 downto 2),
S_AXI_arcache(3 downto 0) => xbar_to_m01_couplers_ARCACHE(7 downto 4),
S_AXI_arid(11 downto 0) => xbar_to_m01_couplers_ARID(23 downto 12),
S_AXI_arlen(7 downto 0) => xbar_to_m01_couplers_ARLEN(15 downto 8),
S_AXI_arlock(0) => xbar_to_m01_couplers_ARLOCK(1),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arqos(3 downto 0) => xbar_to_m01_couplers_ARQOS(7 downto 4),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m01_couplers_ARREGION(7 downto 4),
S_AXI_arsize(2 downto 0) => xbar_to_m01_couplers_ARSIZE(5 downto 3),
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awburst(1 downto 0) => xbar_to_m01_couplers_AWBURST(3 downto 2),
S_AXI_awcache(3 downto 0) => xbar_to_m01_couplers_AWCACHE(7 downto 4),
S_AXI_awid(11 downto 0) => xbar_to_m01_couplers_AWID(23 downto 12),
S_AXI_awlen(7 downto 0) => xbar_to_m01_couplers_AWLEN(15 downto 8),
S_AXI_awlock(0) => xbar_to_m01_couplers_AWLOCK(1),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awqos(3 downto 0) => xbar_to_m01_couplers_AWQOS(7 downto 4),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m01_couplers_AWREGION(7 downto 4),
S_AXI_awsize(2 downto 0) => xbar_to_m01_couplers_AWSIZE(5 downto 3),
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bid(11 downto 0) => xbar_to_m01_couplers_BID(11 downto 0),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => xbar_to_m01_couplers_RID(11 downto 0),
S_AXI_rlast => xbar_to_m01_couplers_RLAST,
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wlast => xbar_to_m01_couplers_WLAST(1),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_MVV5YQ
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arburst(1 downto 0) => xbar_to_m02_couplers_ARBURST(5 downto 4),
S_AXI_arcache(3 downto 0) => xbar_to_m02_couplers_ARCACHE(11 downto 8),
S_AXI_arid(11 downto 0) => xbar_to_m02_couplers_ARID(35 downto 24),
S_AXI_arlen(7 downto 0) => xbar_to_m02_couplers_ARLEN(23 downto 16),
S_AXI_arlock(0) => xbar_to_m02_couplers_ARLOCK(2),
S_AXI_arprot(2 downto 0) => xbar_to_m02_couplers_ARPROT(8 downto 6),
S_AXI_arqos(3 downto 0) => xbar_to_m02_couplers_ARQOS(11 downto 8),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m02_couplers_ARREGION(11 downto 8),
S_AXI_arsize(2 downto 0) => xbar_to_m02_couplers_ARSIZE(8 downto 6),
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awburst(1 downto 0) => xbar_to_m02_couplers_AWBURST(5 downto 4),
S_AXI_awcache(3 downto 0) => xbar_to_m02_couplers_AWCACHE(11 downto 8),
S_AXI_awid(11 downto 0) => xbar_to_m02_couplers_AWID(35 downto 24),
S_AXI_awlen(7 downto 0) => xbar_to_m02_couplers_AWLEN(23 downto 16),
S_AXI_awlock(0) => xbar_to_m02_couplers_AWLOCK(2),
S_AXI_awprot(2 downto 0) => xbar_to_m02_couplers_AWPROT(8 downto 6),
S_AXI_awqos(3 downto 0) => xbar_to_m02_couplers_AWQOS(11 downto 8),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m02_couplers_AWREGION(11 downto 8),
S_AXI_awsize(2 downto 0) => xbar_to_m02_couplers_AWSIZE(8 downto 6),
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bid(11 downto 0) => xbar_to_m02_couplers_BID(11 downto 0),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => xbar_to_m02_couplers_RID(11 downto 0),
S_AXI_rlast => xbar_to_m02_couplers_RLAST,
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wlast => xbar_to_m02_couplers_WLAST(2),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1GHG26R
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN(0) => M03_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARCACHE(3 downto 0),
M_AXI_arid(11 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARID(11 downto 0),
M_AXI_arlen(7 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARLEN(7 downto 0),
M_AXI_arlock => m03_couplers_to_processing_system7_0_axi_periph_ARLOCK,
M_AXI_arprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m03_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arsize(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARSIZE(2 downto 0),
M_AXI_arvalid => m03_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWCACHE(3 downto 0),
M_AXI_awid(11 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWID(11 downto 0),
M_AXI_awlen(7 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWLEN(7 downto 0),
M_AXI_awlock => m03_couplers_to_processing_system7_0_axi_periph_AWLOCK,
M_AXI_awprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m03_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awsize(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWSIZE(2 downto 0),
M_AXI_awvalid => m03_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bid(11 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BID(11 downto 0),
M_AXI_bready => m03_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rid(11 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RID(11 downto 0),
M_AXI_rlast => m03_couplers_to_processing_system7_0_axi_periph_RLAST,
M_AXI_rready => m03_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wlast => m03_couplers_to_processing_system7_0_axi_periph_WLAST,
M_AXI_wready => m03_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arburst(1 downto 0) => xbar_to_m03_couplers_ARBURST(7 downto 6),
S_AXI_arcache(3 downto 0) => xbar_to_m03_couplers_ARCACHE(15 downto 12),
S_AXI_arid(11 downto 0) => xbar_to_m03_couplers_ARID(47 downto 36),
S_AXI_arlen(7 downto 0) => xbar_to_m03_couplers_ARLEN(31 downto 24),
S_AXI_arlock => xbar_to_m03_couplers_ARLOCK(3),
S_AXI_arprot(2 downto 0) => xbar_to_m03_couplers_ARPROT(11 downto 9),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => xbar_to_m03_couplers_ARSIZE(11 downto 9),
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awburst(1 downto 0) => xbar_to_m03_couplers_AWBURST(7 downto 6),
S_AXI_awcache(3 downto 0) => xbar_to_m03_couplers_AWCACHE(15 downto 12),
S_AXI_awid(11 downto 0) => xbar_to_m03_couplers_AWID(47 downto 36),
S_AXI_awlen(7 downto 0) => xbar_to_m03_couplers_AWLEN(31 downto 24),
S_AXI_awlock => xbar_to_m03_couplers_AWLOCK(3),
S_AXI_awprot(2 downto 0) => xbar_to_m03_couplers_AWPROT(11 downto 9),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => xbar_to_m03_couplers_AWSIZE(11 downto 9),
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bid(11 downto 0) => xbar_to_m03_couplers_BID(11 downto 0),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => xbar_to_m03_couplers_RID(11 downto 0),
S_AXI_rlast => xbar_to_m03_couplers_RLAST,
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wlast => xbar_to_m03_couplers_WLAST(3),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_PJ7QT3
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN(0) => M04_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m04_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m04_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m04_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arburst(1 downto 0) => xbar_to_m04_couplers_ARBURST(9 downto 8),
S_AXI_arcache(3 downto 0) => xbar_to_m04_couplers_ARCACHE(19 downto 16),
S_AXI_arid(11 downto 0) => xbar_to_m04_couplers_ARID(59 downto 48),
S_AXI_arlen(7 downto 0) => xbar_to_m04_couplers_ARLEN(39 downto 32),
S_AXI_arlock(0) => xbar_to_m04_couplers_ARLOCK(4),
S_AXI_arprot(2 downto 0) => xbar_to_m04_couplers_ARPROT(14 downto 12),
S_AXI_arqos(3 downto 0) => xbar_to_m04_couplers_ARQOS(19 downto 16),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m04_couplers_ARREGION(19 downto 16),
S_AXI_arsize(2 downto 0) => xbar_to_m04_couplers_ARSIZE(14 downto 12),
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awburst(1 downto 0) => xbar_to_m04_couplers_AWBURST(9 downto 8),
S_AXI_awcache(3 downto 0) => xbar_to_m04_couplers_AWCACHE(19 downto 16),
S_AXI_awid(11 downto 0) => xbar_to_m04_couplers_AWID(59 downto 48),
S_AXI_awlen(7 downto 0) => xbar_to_m04_couplers_AWLEN(39 downto 32),
S_AXI_awlock(0) => xbar_to_m04_couplers_AWLOCK(4),
S_AXI_awprot(2 downto 0) => xbar_to_m04_couplers_AWPROT(14 downto 12),
S_AXI_awqos(3 downto 0) => xbar_to_m04_couplers_AWQOS(19 downto 16),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m04_couplers_AWREGION(19 downto 16),
S_AXI_awsize(2 downto 0) => xbar_to_m04_couplers_AWSIZE(14 downto 12),
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bid(11 downto 0) => xbar_to_m04_couplers_BID(11 downto 0),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => xbar_to_m04_couplers_RID(11 downto 0),
S_AXI_rlast => xbar_to_m04_couplers_RLAST,
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wlast => xbar_to_m04_couplers_WLAST(4),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
s00_couplers: entity work.s00_couplers_imp_1CFO1MB
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arid(11 downto 0) => s00_couplers_to_xbar_ARID(11 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awid(11 downto 0) => s00_couplers_to_xbar_AWID(11 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bid(11 downto 0) => s00_couplers_to_xbar_BID(11 downto 0),
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rid(11 downto 0) => s00_couplers_to_xbar_RID(11 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast => s00_couplers_to_xbar_WLAST,
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component design_1_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(9 downto 8) => xbar_to_m04_couplers_ARBURST(9 downto 8),
m_axi_arburst(7 downto 6) => xbar_to_m03_couplers_ARBURST(7 downto 6),
m_axi_arburst(5 downto 4) => xbar_to_m02_couplers_ARBURST(5 downto 4),
m_axi_arburst(3 downto 2) => xbar_to_m01_couplers_ARBURST(3 downto 2),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(19 downto 16) => xbar_to_m04_couplers_ARCACHE(19 downto 16),
m_axi_arcache(15 downto 12) => xbar_to_m03_couplers_ARCACHE(15 downto 12),
m_axi_arcache(11 downto 8) => xbar_to_m02_couplers_ARCACHE(11 downto 8),
m_axi_arcache(7 downto 4) => xbar_to_m01_couplers_ARCACHE(7 downto 4),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(59 downto 48) => xbar_to_m04_couplers_ARID(59 downto 48),
m_axi_arid(47 downto 36) => xbar_to_m03_couplers_ARID(47 downto 36),
m_axi_arid(35 downto 24) => xbar_to_m02_couplers_ARID(35 downto 24),
m_axi_arid(23 downto 12) => xbar_to_m01_couplers_ARID(23 downto 12),
m_axi_arid(11 downto 0) => xbar_to_m00_couplers_ARID(11 downto 0),
m_axi_arlen(39 downto 32) => xbar_to_m04_couplers_ARLEN(39 downto 32),
m_axi_arlen(31 downto 24) => xbar_to_m03_couplers_ARLEN(31 downto 24),
m_axi_arlen(23 downto 16) => xbar_to_m02_couplers_ARLEN(23 downto 16),
m_axi_arlen(15 downto 8) => xbar_to_m01_couplers_ARLEN(15 downto 8),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(4) => xbar_to_m04_couplers_ARLOCK(4),
m_axi_arlock(3) => xbar_to_m03_couplers_ARLOCK(3),
m_axi_arlock(2) => xbar_to_m02_couplers_ARLOCK(2),
m_axi_arlock(1) => xbar_to_m01_couplers_ARLOCK(1),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(14 downto 12) => xbar_to_m04_couplers_ARPROT(14 downto 12),
m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
m_axi_arprot(8 downto 6) => xbar_to_m02_couplers_ARPROT(8 downto 6),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(19 downto 16) => xbar_to_m04_couplers_ARQOS(19 downto 16),
m_axi_arqos(15 downto 12) => NLW_xbar_m_axi_arqos_UNCONNECTED(15 downto 12),
m_axi_arqos(11 downto 8) => xbar_to_m02_couplers_ARQOS(11 downto 8),
m_axi_arqos(7 downto 4) => xbar_to_m01_couplers_ARQOS(7 downto 4),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(19 downto 16) => xbar_to_m04_couplers_ARREGION(19 downto 16),
m_axi_arregion(15 downto 12) => NLW_xbar_m_axi_arregion_UNCONNECTED(15 downto 12),
m_axi_arregion(11 downto 8) => xbar_to_m02_couplers_ARREGION(11 downto 8),
m_axi_arregion(7 downto 4) => xbar_to_m01_couplers_ARREGION(7 downto 4),
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(14 downto 12) => xbar_to_m04_couplers_ARSIZE(14 downto 12),
m_axi_arsize(11 downto 9) => xbar_to_m03_couplers_ARSIZE(11 downto 9),
m_axi_arsize(8 downto 6) => xbar_to_m02_couplers_ARSIZE(8 downto 6),
m_axi_arsize(5 downto 3) => xbar_to_m01_couplers_ARSIZE(5 downto 3),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(9 downto 8) => xbar_to_m04_couplers_AWBURST(9 downto 8),
m_axi_awburst(7 downto 6) => xbar_to_m03_couplers_AWBURST(7 downto 6),
m_axi_awburst(5 downto 4) => xbar_to_m02_couplers_AWBURST(5 downto 4),
m_axi_awburst(3 downto 2) => xbar_to_m01_couplers_AWBURST(3 downto 2),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(19 downto 16) => xbar_to_m04_couplers_AWCACHE(19 downto 16),
m_axi_awcache(15 downto 12) => xbar_to_m03_couplers_AWCACHE(15 downto 12),
m_axi_awcache(11 downto 8) => xbar_to_m02_couplers_AWCACHE(11 downto 8),
m_axi_awcache(7 downto 4) => xbar_to_m01_couplers_AWCACHE(7 downto 4),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(59 downto 48) => xbar_to_m04_couplers_AWID(59 downto 48),
m_axi_awid(47 downto 36) => xbar_to_m03_couplers_AWID(47 downto 36),
m_axi_awid(35 downto 24) => xbar_to_m02_couplers_AWID(35 downto 24),
m_axi_awid(23 downto 12) => xbar_to_m01_couplers_AWID(23 downto 12),
m_axi_awid(11 downto 0) => xbar_to_m00_couplers_AWID(11 downto 0),
m_axi_awlen(39 downto 32) => xbar_to_m04_couplers_AWLEN(39 downto 32),
m_axi_awlen(31 downto 24) => xbar_to_m03_couplers_AWLEN(31 downto 24),
m_axi_awlen(23 downto 16) => xbar_to_m02_couplers_AWLEN(23 downto 16),
m_axi_awlen(15 downto 8) => xbar_to_m01_couplers_AWLEN(15 downto 8),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(4) => xbar_to_m04_couplers_AWLOCK(4),
m_axi_awlock(3) => xbar_to_m03_couplers_AWLOCK(3),
m_axi_awlock(2) => xbar_to_m02_couplers_AWLOCK(2),
m_axi_awlock(1) => xbar_to_m01_couplers_AWLOCK(1),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(14 downto 12) => xbar_to_m04_couplers_AWPROT(14 downto 12),
m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
m_axi_awprot(8 downto 6) => xbar_to_m02_couplers_AWPROT(8 downto 6),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(19 downto 16) => xbar_to_m04_couplers_AWQOS(19 downto 16),
m_axi_awqos(15 downto 12) => NLW_xbar_m_axi_awqos_UNCONNECTED(15 downto 12),
m_axi_awqos(11 downto 8) => xbar_to_m02_couplers_AWQOS(11 downto 8),
m_axi_awqos(7 downto 4) => xbar_to_m01_couplers_AWQOS(7 downto 4),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(19 downto 16) => xbar_to_m04_couplers_AWREGION(19 downto 16),
m_axi_awregion(15 downto 12) => NLW_xbar_m_axi_awregion_UNCONNECTED(15 downto 12),
m_axi_awregion(11 downto 8) => xbar_to_m02_couplers_AWREGION(11 downto 8),
m_axi_awregion(7 downto 4) => xbar_to_m01_couplers_AWREGION(7 downto 4),
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(14 downto 12) => xbar_to_m04_couplers_AWSIZE(14 downto 12),
m_axi_awsize(11 downto 9) => xbar_to_m03_couplers_AWSIZE(11 downto 9),
m_axi_awsize(8 downto 6) => xbar_to_m02_couplers_AWSIZE(8 downto 6),
m_axi_awsize(5 downto 3) => xbar_to_m01_couplers_AWSIZE(5 downto 3),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(59 downto 48) => xbar_to_m04_couplers_BID(11 downto 0),
m_axi_bid(47 downto 36) => xbar_to_m03_couplers_BID(11 downto 0),
m_axi_bid(35 downto 24) => xbar_to_m02_couplers_BID(11 downto 0),
m_axi_bid(23 downto 12) => xbar_to_m01_couplers_BID(11 downto 0),
m_axi_bid(11 downto 0) => xbar_to_m00_couplers_BID(11 downto 0),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(59 downto 48) => xbar_to_m04_couplers_RID(11 downto 0),
m_axi_rid(47 downto 36) => xbar_to_m03_couplers_RID(11 downto 0),
m_axi_rid(35 downto 24) => xbar_to_m02_couplers_RID(11 downto 0),
m_axi_rid(23 downto 12) => xbar_to_m01_couplers_RID(11 downto 0),
m_axi_rid(11 downto 0) => xbar_to_m00_couplers_RID(11 downto 0),
m_axi_rlast(4) => xbar_to_m04_couplers_RLAST,
m_axi_rlast(3) => xbar_to_m03_couplers_RLAST,
m_axi_rlast(2) => xbar_to_m02_couplers_RLAST,
m_axi_rlast(1) => xbar_to_m01_couplers_RLAST,
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(4) => xbar_to_m04_couplers_WLAST(4),
m_axi_wlast(3) => xbar_to_m03_couplers_WLAST(3),
m_axi_wlast(2) => xbar_to_m02_couplers_WLAST(2),
m_axi_wlast(1) => xbar_to_m01_couplers_WLAST(1),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_xbar_ARID(11 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_xbar_AWID(11 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_xbar_BID(11 downto 0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_xbar_RID(11 downto 0),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wlast(0) => s00_couplers_to_xbar_WLAST,
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1 is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=30,numReposBlks=19,numNonXlnxBlks=2,numHierBlks=11,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=2,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=7,da_board_cnt=1,da_bram_cntlr_cnt=1,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
end design_1;
architecture STRUCTURE of design_1 is
component design_1_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_1_processing_system7_0_0;
component design_1_axi_dma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
mm2s_introut : out STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component design_1_axi_dma_0_0;
component design_1_rst_processing_system7_0_50M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_rst_processing_system7_0_50M_0;
component design_1_doHist_0_1 is
port (
s_axi_CTRL_BUS_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_CTRL_BUS_AWVALID : in STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : out STD_LOGIC;
s_axi_CTRL_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_CTRL_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_CTRL_BUS_WVALID : in STD_LOGIC;
s_axi_CTRL_BUS_WREADY : out STD_LOGIC;
s_axi_CTRL_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_CTRL_BUS_BVALID : out STD_LOGIC;
s_axi_CTRL_BUS_BREADY : in STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_CTRL_BUS_ARVALID : in STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : out STD_LOGIC;
s_axi_CTRL_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_CTRL_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_CTRL_BUS_RVALID : out STD_LOGIC;
s_axi_CTRL_BUS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC;
inStream_TVALID : in STD_LOGIC;
inStream_TREADY : out STD_LOGIC;
inStream_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 );
inStream_TDEST : in STD_LOGIC_VECTOR ( 5 downto 0 );
inStream_TKEEP : in STD_LOGIC_VECTOR ( 0 to 0 );
inStream_TSTRB : in STD_LOGIC_VECTOR ( 0 to 0 );
inStream_TUSER : in STD_LOGIC_VECTOR ( 1 downto 0 );
inStream_TLAST : in STD_LOGIC_VECTOR ( 0 to 0 );
inStream_TID : in STD_LOGIC_VECTOR ( 4 downto 0 );
histo_Clk_A : out STD_LOGIC;
histo_Rst_A : out STD_LOGIC;
histo_EN_A : out STD_LOGIC;
histo_WEN_A : out STD_LOGIC_VECTOR ( 3 downto 0 );
histo_Addr_A : out STD_LOGIC_VECTOR ( 31 downto 0 );
histo_Din_A : out STD_LOGIC_VECTOR ( 31 downto 0 );
histo_Dout_A : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_1_doHist_0_1;
component design_1_axis_broadcaster_0_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axis_tready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axis_tlast : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component design_1_axis_broadcaster_0_0;
component design_1_doHist_0_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_1_doHist_0_bram_0;
component design_1_axi_bram_ctrl_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_1_axi_bram_ctrl_0_0;
component design_1_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end component design_1_axi_timer_0_0;
component design_1_doHistStretch_0_0 is
port (
s_axi_CTRL_BUS_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_CTRL_BUS_AWVALID : in STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : out STD_LOGIC;
s_axi_CTRL_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_CTRL_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_CTRL_BUS_WVALID : in STD_LOGIC;
s_axi_CTRL_BUS_WREADY : out STD_LOGIC;
s_axi_CTRL_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_CTRL_BUS_BVALID : out STD_LOGIC;
s_axi_CTRL_BUS_BREADY : in STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_CTRL_BUS_ARVALID : in STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : out STD_LOGIC;
s_axi_CTRL_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_CTRL_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_CTRL_BUS_RVALID : out STD_LOGIC;
s_axi_CTRL_BUS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC;
inStream_TVALID : in STD_LOGIC;
inStream_TREADY : out STD_LOGIC;
inStream_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 );
inStream_TDEST : in STD_LOGIC_VECTOR ( 5 downto 0 );
inStream_TKEEP : in STD_LOGIC_VECTOR ( 0 to 0 );
inStream_TSTRB : in STD_LOGIC_VECTOR ( 0 to 0 );
inStream_TUSER : in STD_LOGIC_VECTOR ( 1 downto 0 );
inStream_TLAST : in STD_LOGIC_VECTOR ( 0 to 0 );
inStream_TID : in STD_LOGIC_VECTOR ( 4 downto 0 );
outStream_TVALID : out STD_LOGIC;
outStream_TREADY : in STD_LOGIC;
outStream_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 );
outStream_TDEST : out STD_LOGIC_VECTOR ( 5 downto 0 );
outStream_TKEEP : out STD_LOGIC_VECTOR ( 0 to 0 );
outStream_TSTRB : out STD_LOGIC_VECTOR ( 0 to 0 );
outStream_TUSER : out STD_LOGIC_VECTOR ( 1 downto 0 );
outStream_TLAST : out STD_LOGIC_VECTOR ( 0 to 0 );
outStream_TID : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component design_1_doHistStretch_0_0;
signal axi_bram_ctrl_0_BRAM_PORTA_ADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_CLK : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_DIN : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_EN : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_RST : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_WE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal axis_broadcaster_0_M00_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axis_broadcaster_0_M00_AXIS_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 );
signal axis_broadcaster_0_M00_AXIS_TLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axis_broadcaster_0_M00_AXIS_TREADY : STD_LOGIC;
signal axis_broadcaster_0_M00_AXIS_TVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axis_broadcaster_0_M01_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 8 );
signal axis_broadcaster_0_M01_AXIS_TKEEP : STD_LOGIC_VECTOR ( 1 to 1 );
signal axis_broadcaster_0_M01_AXIS_TLAST : STD_LOGIC_VECTOR ( 1 to 1 );
signal axis_broadcaster_0_M01_AXIS_TREADY : STD_LOGIC;
signal axis_broadcaster_0_M01_AXIS_TVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal doHistStretch_0_outStream_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
signal doHistStretch_0_outStream_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 );
signal doHistStretch_0_outStream_TLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal doHistStretch_0_outStream_TREADY : STD_LOGIC;
signal doHistStretch_0_outStream_TVALID : STD_LOGIC;
signal doHist_0_histo_PORTA_ADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal doHist_0_histo_PORTA_CLK : STD_LOGIC;
signal doHist_0_histo_PORTA_DIN : STD_LOGIC_VECTOR ( 31 downto 0 );
signal doHist_0_histo_PORTA_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal doHist_0_histo_PORTA_EN : STD_LOGIC;
signal doHist_0_histo_PORTA_RST : STD_LOGIC;
signal doHist_0_histo_PORTA_WE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARLOCK : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWLOCK : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_50M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_50M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_dma_0_mm2s_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_s2mm_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
signal NLW_doHistStretch_0_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_doHistStretch_0_outStream_TDEST_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_doHistStretch_0_outStream_TID_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_doHistStretch_0_outStream_TSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_doHistStretch_0_outStream_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_doHist_0_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_50M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_50M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_50M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of axi_bram_ctrl_0 : label is "byte 0x40000000 32 > design_1 doHist_0_bram";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of axi_bram_ctrl_0 : label is "yes";
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of processing_system7_0 : label is "arm > design_1 axi_bram_ctrl_0";
attribute KEEP_HIERARCHY of processing_system7_0 : label is "yes";
begin
axi_bram_ctrl_0: component design_1_axi_bram_ctrl_0_0
port map (
bram_addr_a(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0),
bram_clk_a => axi_bram_ctrl_0_BRAM_PORTA_CLK,
bram_en_a => axi_bram_ctrl_0_BRAM_PORTA_EN,
bram_rddata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0),
bram_rst_a => axi_bram_ctrl_0_BRAM_PORTA_RST,
bram_we_a(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0),
bram_wrdata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(12 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(12 downto 0),
s_axi_arburst(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARCACHE(3 downto 0),
s_axi_aresetn => rst_processing_system7_0_50M_peripheral_aresetn(0),
s_axi_arid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARID(11 downto 0),
s_axi_arlen(7 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARLEN(7 downto 0),
s_axi_arlock => processing_system7_0_axi_periph_M03_AXI_ARLOCK,
s_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0),
s_axi_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
s_axi_arsize(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARSIZE(2 downto 0),
s_axi_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
s_axi_awaddr(12 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(12 downto 0),
s_axi_awburst(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWID(11 downto 0),
s_axi_awlen(7 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWLEN(7 downto 0),
s_axi_awlock => processing_system7_0_axi_periph_M03_AXI_AWLOCK,
s_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
s_axi_awsize(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWSIZE(2 downto 0),
s_axi_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
s_axi_bid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_BID(11 downto 0),
s_axi_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_RID(11 downto 0),
s_axi_rlast => processing_system7_0_axi_periph_M03_AXI_RLAST,
s_axi_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s_axi_wlast => processing_system7_0_axi_periph_M03_AXI_WLAST,
s_axi_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID
);
axi_dma_0: component design_1_axi_dma_0_0
port map (
axi_resetn => rst_processing_system7_0_50M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_0_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_0_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_0_M_AXI_S2MM_WVALID,
m_axis_mm2s_tdata(7 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(7 downto 0),
m_axis_mm2s_tkeep(0) => axi_dma_0_M_AXIS_MM2S_TKEEP(0),
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
mm2s_introut => NLW_axi_dma_0_mm2s_introut_UNCONNECTED,
mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED,
s2mm_introut => NLW_axi_dma_0_s2mm_introut_UNCONNECTED,
s2mm_prmry_reset_out_n => NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID,
s_axis_s2mm_tdata(7 downto 0) => doHistStretch_0_outStream_TDATA(7 downto 0),
s_axis_s2mm_tkeep(0) => doHistStretch_0_outStream_TKEEP(0),
s_axis_s2mm_tlast => doHistStretch_0_outStream_TLAST(0),
s_axis_s2mm_tready => doHistStretch_0_outStream_TREADY,
s_axis_s2mm_tvalid => doHistStretch_0_outStream_TVALID
);
axi_mem_intercon: entity work.design_1_axi_mem_intercon_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_50M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
M00_AXI_wid(0) => axi_mem_intercon_M00_AXI_WID(0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
S00_AXI_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
S00_AXI_rready => axi_dma_0_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
S01_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
S01_AXI_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
S01_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
S01_AXI_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
S01_AXI_bready => axi_dma_0_M_AXI_S2MM_BREADY,
S01_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
S01_AXI_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
S01_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
S01_AXI_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
S01_AXI_wready => axi_dma_0_M_AXI_S2MM_WREADY,
S01_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
S01_AXI_wvalid => axi_dma_0_M_AXI_S2MM_WVALID
);
axi_timer_0: component design_1_axi_timer_0_0
port map (
capturetrig0 => '0',
capturetrig1 => '0',
freeze => '0',
generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
interrupt => NLW_axi_timer_0_interrupt_UNCONNECTED,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(4 downto 0),
s_axi_aresetn => rst_processing_system7_0_50M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
s_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(4 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID
);
axis_broadcaster_0: component design_1_axis_broadcaster_0_0
port map (
aclk => processing_system7_0_FCLK_CLK0,
aresetn => rst_processing_system7_0_50M_peripheral_aresetn(0),
m_axis_tdata(15 downto 8) => axis_broadcaster_0_M01_AXIS_TDATA(15 downto 8),
m_axis_tdata(7 downto 0) => axis_broadcaster_0_M00_AXIS_TDATA(7 downto 0),
m_axis_tkeep(1) => axis_broadcaster_0_M01_AXIS_TKEEP(1),
m_axis_tkeep(0) => axis_broadcaster_0_M00_AXIS_TKEEP(0),
m_axis_tlast(1) => axis_broadcaster_0_M01_AXIS_TLAST(1),
m_axis_tlast(0) => axis_broadcaster_0_M00_AXIS_TLAST(0),
m_axis_tready(1) => axis_broadcaster_0_M01_AXIS_TREADY,
m_axis_tready(0) => axis_broadcaster_0_M00_AXIS_TREADY,
m_axis_tvalid(1) => axis_broadcaster_0_M01_AXIS_TVALID(1),
m_axis_tvalid(0) => axis_broadcaster_0_M00_AXIS_TVALID(0),
s_axis_tdata(7 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(7 downto 0),
s_axis_tkeep(0) => axi_dma_0_M_AXIS_MM2S_TKEEP(0),
s_axis_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
s_axis_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
s_axis_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID
);
doHistStretch_0: component design_1_doHistStretch_0_0
port map (
ap_clk => processing_system7_0_FCLK_CLK0,
ap_rst_n => rst_processing_system7_0_50M_peripheral_aresetn(0),
inStream_TDATA(7 downto 0) => axis_broadcaster_0_M01_AXIS_TDATA(15 downto 8),
inStream_TDEST(5 downto 0) => B"000000",
inStream_TID(4 downto 0) => B"00000",
inStream_TKEEP(0) => axis_broadcaster_0_M01_AXIS_TKEEP(1),
inStream_TLAST(0) => axis_broadcaster_0_M01_AXIS_TLAST(1),
inStream_TREADY => axis_broadcaster_0_M01_AXIS_TREADY,
inStream_TSTRB(0) => '1',
inStream_TUSER(1 downto 0) => B"00",
inStream_TVALID => axis_broadcaster_0_M01_AXIS_TVALID(1),
interrupt => NLW_doHistStretch_0_interrupt_UNCONNECTED,
outStream_TDATA(7 downto 0) => doHistStretch_0_outStream_TDATA(7 downto 0),
outStream_TDEST(5 downto 0) => NLW_doHistStretch_0_outStream_TDEST_UNCONNECTED(5 downto 0),
outStream_TID(4 downto 0) => NLW_doHistStretch_0_outStream_TID_UNCONNECTED(4 downto 0),
outStream_TKEEP(0) => doHistStretch_0_outStream_TKEEP(0),
outStream_TLAST(0) => doHistStretch_0_outStream_TLAST(0),
outStream_TREADY => doHistStretch_0_outStream_TREADY,
outStream_TSTRB(0) => NLW_doHistStretch_0_outStream_TSTRB_UNCONNECTED(0),
outStream_TUSER(1 downto 0) => NLW_doHistStretch_0_outStream_TUSER_UNCONNECTED(1 downto 0),
outStream_TVALID => doHistStretch_0_outStream_TVALID,
s_axi_CTRL_BUS_ARADDR(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(4 downto 0),
s_axi_CTRL_BUS_ARREADY => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_CTRL_BUS_ARVALID => processing_system7_0_axi_periph_M01_AXI_ARVALID,
s_axi_CTRL_BUS_AWADDR(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(4 downto 0),
s_axi_CTRL_BUS_AWREADY => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_CTRL_BUS_AWVALID => processing_system7_0_axi_periph_M01_AXI_AWVALID,
s_axi_CTRL_BUS_BREADY => processing_system7_0_axi_periph_M01_AXI_BREADY,
s_axi_CTRL_BUS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_CTRL_BUS_BVALID => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_CTRL_BUS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_CTRL_BUS_RREADY => processing_system7_0_axi_periph_M01_AXI_RREADY,
s_axi_CTRL_BUS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_CTRL_BUS_RVALID => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_CTRL_BUS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_CTRL_BUS_WREADY => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_CTRL_BUS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_CTRL_BUS_WVALID => processing_system7_0_axi_periph_M01_AXI_WVALID
);
doHist_0: component design_1_doHist_0_1
port map (
ap_clk => processing_system7_0_FCLK_CLK0,
ap_rst_n => rst_processing_system7_0_50M_peripheral_aresetn(0),
histo_Addr_A(31 downto 0) => doHist_0_histo_PORTA_ADDR(31 downto 0),
histo_Clk_A => doHist_0_histo_PORTA_CLK,
histo_Din_A(31 downto 0) => doHist_0_histo_PORTA_DIN(31 downto 0),
histo_Dout_A(31 downto 0) => doHist_0_histo_PORTA_DOUT(31 downto 0),
histo_EN_A => doHist_0_histo_PORTA_EN,
histo_Rst_A => doHist_0_histo_PORTA_RST,
histo_WEN_A(3 downto 0) => doHist_0_histo_PORTA_WE(3 downto 0),
inStream_TDATA(7 downto 0) => axis_broadcaster_0_M00_AXIS_TDATA(7 downto 0),
inStream_TDEST(5 downto 0) => B"000000",
inStream_TID(4 downto 0) => B"00000",
inStream_TKEEP(0) => axis_broadcaster_0_M00_AXIS_TKEEP(0),
inStream_TLAST(0) => axis_broadcaster_0_M00_AXIS_TLAST(0),
inStream_TREADY => axis_broadcaster_0_M00_AXIS_TREADY,
inStream_TSTRB(0) => '1',
inStream_TUSER(1 downto 0) => B"00",
inStream_TVALID => axis_broadcaster_0_M00_AXIS_TVALID(0),
interrupt => NLW_doHist_0_interrupt_UNCONNECTED,
s_axi_CTRL_BUS_ARADDR(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(3 downto 0),
s_axi_CTRL_BUS_ARREADY => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s_axi_CTRL_BUS_ARVALID => processing_system7_0_axi_periph_M02_AXI_ARVALID,
s_axi_CTRL_BUS_AWADDR(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(3 downto 0),
s_axi_CTRL_BUS_AWREADY => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s_axi_CTRL_BUS_AWVALID => processing_system7_0_axi_periph_M02_AXI_AWVALID,
s_axi_CTRL_BUS_BREADY => processing_system7_0_axi_periph_M02_AXI_BREADY,
s_axi_CTRL_BUS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_CTRL_BUS_BVALID => processing_system7_0_axi_periph_M02_AXI_BVALID,
s_axi_CTRL_BUS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_CTRL_BUS_RREADY => processing_system7_0_axi_periph_M02_AXI_RREADY,
s_axi_CTRL_BUS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_CTRL_BUS_RVALID => processing_system7_0_axi_periph_M02_AXI_RVALID,
s_axi_CTRL_BUS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_CTRL_BUS_WREADY => processing_system7_0_axi_periph_M02_AXI_WREADY,
s_axi_CTRL_BUS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_CTRL_BUS_WVALID => processing_system7_0_axi_periph_M02_AXI_WVALID
);
doHist_0_bram: component design_1_doHist_0_bram_0
port map (
addra(31 downto 0) => doHist_0_histo_PORTA_ADDR(31 downto 0),
addrb(31 downto 13) => B"0000000000000000000",
addrb(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0),
clka => doHist_0_histo_PORTA_CLK,
clkb => axi_bram_ctrl_0_BRAM_PORTA_CLK,
dina(31 downto 0) => doHist_0_histo_PORTA_DIN(31 downto 0),
dinb(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0),
douta(31 downto 0) => doHist_0_histo_PORTA_DOUT(31 downto 0),
doutb(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0),
ena => doHist_0_histo_PORTA_EN,
enb => axi_bram_ctrl_0_BRAM_PORTA_EN,
rsta => doHist_0_histo_PORTA_RST,
rstb => axi_bram_ctrl_0_BRAM_PORTA_RST,
wea(3 downto 0) => doHist_0_histo_PORTA_WE(3 downto 0),
web(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0)
);
processing_system7_0: component design_1_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 1) => B"00000",
S_AXI_HP0_ARID(0) => axi_mem_intercon_M00_AXI_ARID(0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 1) => B"00000",
S_AXI_HP0_AWID(0) => axi_mem_intercon_M00_AXI_AWID(0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
S_AXI_HP0_WID(5 downto 1) => B"00000",
S_AXI_HP0_WID(0) => axi_mem_intercon_M00_AXI_WID(0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_1_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_50M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
M00_AXI_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID,
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID,
M01_AXI_bready => processing_system7_0_axi_periph_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => processing_system7_0_axi_periph_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID,
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
M03_ACLK => processing_system7_0_FCLK_CLK0,
M03_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARBURST(1 downto 0),
M03_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARCACHE(3 downto 0),
M03_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARID(11 downto 0),
M03_AXI_arlen(7 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARLEN(7 downto 0),
M03_AXI_arlock => processing_system7_0_axi_periph_M03_AXI_ARLOCK,
M03_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0),
M03_AXI_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARSIZE(2 downto 0),
M03_AXI_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWBURST(1 downto 0),
M03_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWCACHE(3 downto 0),
M03_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWID(11 downto 0),
M03_AXI_awlen(7 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWLEN(7 downto 0),
M03_AXI_awlock => processing_system7_0_axi_periph_M03_AXI_AWLOCK,
M03_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0),
M03_AXI_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWSIZE(2 downto 0),
M03_AXI_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_BID(11 downto 0),
M03_AXI_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_M03_AXI_RID(11 downto 0),
M03_AXI_rlast => processing_system7_0_axi_periph_M03_AXI_RLAST,
M03_AXI_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wlast => processing_system7_0_axi_periph_M03_AXI_WLAST,
M03_AXI_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID,
M04_ACLK => processing_system7_0_FCLK_CLK0,
M04_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
M04_AXI_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_50M: component design_1_rst_processing_system7_0_50M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_50M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_50M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_50M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_50M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_50M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
| gpl-3.0 | 4fcd483c59702b37bd1d4fd945c90578 | 0.675328 | 2.816525 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/my_project.vhdl | 1 | 1,805 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This is a template file.
--
-- TODO
--
-- USAGE:
-- 1) Copy this file into your project's source directory and rename it to
-- "my_project.vhdl".
-- 2) Add file to library "poc" in your synthesis tool.
-- 3) Change setup appropriately.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := "prjdir"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "LINUX"; -- e.g. "WINDOWS", "LINUX"
end package;
| gpl-2.0 | 103e6975f56ae1fd8d9ab69d5537d5bf | 0.58338 | 4.065315 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/asgn07.vhdl | 1 | 525 | library ieee;
use ieee.std_logic_1164.all;
entity asgn07 is
port (clk : std_logic;
s0 : std_logic;
r : out std_logic_vector (65 downto 0));
end asgn07;
architecture behav of asgn07 is
begin
process (clk) is
begin
if rising_edge(clk) then
if s0 = '1' then
r (0) <= '1';
r (64 downto 1) <= x"ffff_eeee_dddd_cccc";
r (65) <= '1';
else
r (0) <= '0';
r (8 downto 5) <= x"7";
r (65) <= '0';
end if;
end if;
end process;
end behav;
| gpl-2.0 | d69523d435a4360eb80314512871c1f3 | 0.512381 | 2.949438 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_05.vhd | 4 | 2,097 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_05.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_05 is
end entity ch_03_05;
architecture test of ch_03_05 is
type phase_type is (wash, other_phase);
signal phase : phase_type := other_phase;
type cycle_type is (delicate_cycle, other_cycle);
signal cycle_select : cycle_type := delicate_cycle;
type speed_type is (slow, fast);
signal agitator_speed : speed_type := slow;
signal agitator_on : boolean := false;
begin
process_3_1_e : process (phase, cycle_select) is
begin
-- code from book:
if phase = wash then
if cycle_select = delicate_cycle then
agitator_speed <= slow;
else
agitator_speed <= fast;
end if;
agitator_on <= true;
end if;
-- end of code from book
end process process_3_1_e;
stimulus : process is
begin
cycle_select <= other_cycle; wait for 100 ns;
phase <= wash; wait for 100 ns;
cycle_select <= delicate_cycle; wait for 100 ns;
cycle_select <= other_cycle; wait for 100 ns;
phase <= other_phase; wait for 100 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 88180b1605fba3ee9e14ffc57e845ad6 | 0.632809 | 3.847706 | false | false | false | false |
nickg/nvc | test/regress/conv3.vhd | 1 | 808 | entity sub is
port ( o1 : out integer;
i1 : in real );
end entity;
architecture test of sub is
begin
p1: process is
begin
o1 <= 1;
wait for 1 ns;
o1 <= 2;
assert i1 = real(5);
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity conv3 is
end entity;
architecture test of conv3 is
signal x : real;
signal y : integer;
begin
uut: entity work.sub
port map ( real(o1) => x,
i1 => real(y) );
p2: process is
begin
assert x = real(integer'left);
wait for 0 ns;
assert x = real(1);
y <= 5;
wait for 2 ns;
assert x = real(2);
wait;
end process;
end architecture;
| gpl-3.0 | fa6a87124efb23df3b6fcd78adbd0711 | 0.461634 | 3.92233 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue522/shifter_tb.vhdl | 1 | 6,080 | library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity Shifter_tb is
end Shifter_tb;
architecture simu of Shifter_tb is
signal shift_lsl, shift_lsr, shift_asr, shift_ror, shift_rrx, cin : std_logic;
signal shift_val :std_logic_vector (4 downto 0);
signal din :std_logic_vector (31 downto 0);
signal dout :std_logic_vector (31 downto 0);
signal cout :std_logic;
signal vdd :bit;
signal vss :bit;
begin
L0: entity work.Shifter
port map (shift_lsl, shift_lsr, shift_asr, shift_ror, shift_rrx, cin, shift_val, din, dout,cout, vdd, vss);
process
variable test : std_logic_vector (31 downto 0);
constant exttest : std_logic_vector (31 downto 0) := X"FFFFFFFF";
begin
cin <= '0';
shift_val <= "00000";
din <= X"0FF00000";
shift_asr <= '0';
shift_ror <= '0';
shift_rrx <= '0';
shift_lsl <= '0';
shift_lsr <= '0';
assert dout = din report "Variable Test = Initial Defaut"severity error;
wait for 1 ns;
--*************************************ASR**************************************************
din <= X"A5A50000";
shift_asr <= '0';
shift_ror <= '1';
shift_rrx <= '0';
shift_lsl <= '0';
shift_lsr <= '0';
for shift in 0 to 30 looP
shift_val <= std_logic_vector(to_unsigned(shift,5 ));
test := din;
wait for 1 ns;
if shift /= 0 then
--"asr" équivaut à une division signé par "2^shift"
--l'operateur exposant n'étant pas disponible on fais une boucle qui divise par 2^shift à chaque tour de boucle
for i in 0 to (shift-1) loop
test := std_logic_vector (shift_right(signed(test),1));
assert dout = test report "Expected Test Result = " & integer'image(to_integer(signed(test))) & " || Dout = " &
integer'image(to_integer(signed(dout))) & " || ASR shift = " & integer'image(to_integer(unsigned(shift_val))) severity error;
end loop;
else
test := std_logic_vector(signed(din));
assert dout = test report "Expected Test Result = " & integer'image(to_integer(signed(test))) &
" || Dout = " & integer'image(to_integer(signed(dout))) & " ||ASR shift = " & integer'image(shift) severity error;
end if;
wait for 2 ns;
end loop;
--Test de l'extention de signe
din <= X"80000000";
shift_val <= "11111";
wait for 1 ns;
assert dout (31 downto 0) = exttest (31 downto 0) report "Bit de Signe = " & integer'image ( to_integer (unsigned(din(31 downto 31)))) & " || Dout =" & integer'image(to_integer(unsigned(dout (31 downto (31-(to_integer(unsigned(shift_val)))))))) & " || ASR shift = " & integer'image(to_integer(unsigned(shift_val))) severity error;
--*************************************LSR**************************************************
cin <= '0';
shift_lsr <= '1';
shift_asr <= '0';
shift_ror <= '0';
shift_rrx <= '0';
shift_lsl <= '0';
for shift in 0 to 30 looP
shift_val <= std_logic_vector(to_unsigned(shift, 5 ));
test := din;
wait for 1 ns;
if shift /= 0 then
for i in 0 to (shift-1) loop
test := std_logic_vector (shift_right(unsigned(test),1));
assert dout = test report "Expected Test Result = " & integer'image(to_integer(unsigned(test))) & " || Dout = " &
integer'image(to_integer(unsigned(dout))) & " || LSR shift = " & integer'image(to_integer(unsigned(shift_val))) severity error;
end loop;
else
test := std_logic_vector(signed(din));
assert dout = test report "Expected Test Result = " & integer'image(to_integer(unsigned(test))) &
" || Dout = " & integer'image(to_integer(unsigned(dout))) & " || LSR shift = " & integer'image(shift) severity error;
end if;
wait for 2 ns;
end loop;
--*************************************LSL**************************************************
din <= X"F000A5A5";
shift_asr <= '0';
shift_ror <= '0';
shift_rrx <= '0';
shift_lsl <= '1';
shift_lsr <= '0';
for z in 0 to 256 loop
for shift in 0 to 30 loop
shift_val <= std_logic_vector(to_unsigned(shift,5));
test := din;
wait for 1 ns;
if shift /= 0 then
for i in 0 to (shift-1) loop
test := std_logic_vector (shift_left(unsigned(test),1));
assert dout = test report "Expected Test Result = " & integer'image(to_integer(unsigned(test))) & " || Dout = " &
integer'image(to_integer(unsigned(dout))) & " ||LSL shift = " & integer'image(to_integer(unsigned(shift_val))) severity error;
end loop;
else
test := std_logic_vector(unsigned(din));
assert dout = test report "Expected Test Result = " & integer'image(to_integer(unsigned(test))) &
" || Dout = " & integer'image(to_integer(unsigned(dout))) & " || LSR shift = " & integer'image(shift) severity error;
end if;
wait for 2 ns;
end loop;
end loop;
--**********************************************************************************************
report "end of TB";
wait for 4 ns;
wait;
end process;
end simu;
| gpl-2.0 | 6a6ebda09e81dcf3348baa440d508418 | 0.466447 | 4.122034 | false | true | false | false |
nickg/nvc | test/sem/gensub2.vhd | 1 | 1,398 | package generic_ff_pack is
procedure FF
generic (
type T)
parameter (
signal q : out T;
constant d : in T;
constant INIT_VAL : in T;
constant rst : in bit;
signal clk : in bit;
constant en : in bit := '1');
end package generic_ff_pack;
package body generic_ff_pack is
procedure FF
generic (
type T)
parameter (
signal q : out T;
constant d : in T;
constant INIT_VAL : in T;
constant rst : in bit;
signal clk : in bit;
constant en : in bit := '1') is
begin
if (clk'event and clk = '1') then
if (rst /= '0') then
q <= INIT_VAL;
elsif (en = '1') then
q <= d;
end if;
end if;
end procedure FF;
end package body;
use work.generic_ff_pack.all;
entity generic_ff_tb is
port (
clkIn : in bit;
rstIn : in bit;
enIn : in bit;
valIn : in bit_vector(7 downto 0);
valOut : out bit_vector(7 downto 0));
end entity generic_ff_tb;
architecture behav of generic_ff_tb is
procedure ff_byte is new FF generic map (T => bit_vector(7 downto 0));
constant INIT_VAL : bit_vector(7 downto 0) := (others=>'0');
begin
ff_byte(valOut, valIn, INIT_VAL, rstIn, clkIn, enIn);
end architecture behav;
| gpl-3.0 | 8ed8291c80f0c02ea6414e5482418966 | 0.526466 | 3.44335 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff02/dff08c.vhdl | 1 | 576 | library ieee;
use ieee.std_logic_1164.all;
entity dff08c is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic;
en : std_logic;
rst : std_logic);
end dff08c;
architecture behav of dff08c is
constant c : std_logic_vector(7 downto 0) := x"aa";
signal p : std_logic_vector(7 downto 0) := c;
begin
process (clk, rst) is
begin
if en = '0' then
null;
elsif rst = '1' then
p <= c;
elsif rising_edge (clk) then
p <= d;
end if;
end process;
q <= p;
end behav;
| gpl-2.0 | 37fb565e0d8e6093466f98b9801ae43f | 0.579861 | 3.015707 | false | false | false | false |
lfmunoz/vhdl | templates/sip_cmd/ip_fblock_ctrl.vhd | 2 | 12,795 | -------------------------------------------------------------------------------------
-- FILE NAME : ip_fblock_ctrl.vhd
-- AUTHOR : Luis Munoz
-- COMPANY : 4DSP
-- UNITS : Entity - ip_block_ctrl
-- architecture - ip_block_ctrl
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity ip_fblock_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
adc_phy_clk : in std_logic;
fifo_valid : in std_logic_vector(3 downto 0);
fifo_wr_en : out std_logic_vector(3 downto 0);
reg6 : out std_logic_vector(31 downto 0);
reg7 : in std_logic_vector(31 downto 0);
reg8 : in std_logic_vector(31 downto 0);
reg9 : in std_logic_vector(31 downto 0);
reg10 : in std_logic_vector(31 downto 0)
);
end ip_fblock_ctrl;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of ip_fblock_ctrl is
----------------------------------------------------------------------------------------------------
-- Components
----------------------------------------------------------------------------------------------------
component stellar_generic_cmd is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component stellar_generic_cmd;
component pulse2pulse is
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component pulse2pulse;
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_COMMAND : std_logic_vector(31 downto 0) := x"00000000";
constant ADDR_CONTROL : std_logic_vector(31 downto 0) := x"00000001";
constant ADDR_NB_BURSTS : std_logic_vector(31 downto 0) := x"00000002";
constant ADDR_BURST_SIZE : std_logic_vector(31 downto 0) := x"00000003";
constant ADDR_FMC_INFO : std_logic_vector(31 downto 0) := x"00000004";
constant ADDR_REG5 : std_logic_vector(31 downto 0) := x"00000005";
constant ADDR_REG6 : std_logic_vector(31 downto 0) := x"00000006";
constant ADDR_REG7 : std_logic_vector(31 downto 0) := x"00000007";
constant ADDR_REG8 : std_logic_vector(31 downto 0) := x"00000008";
constant ADDR_REG9 : std_logic_vector(31 downto 0) := x"00000009";
constant ADDR_REG10 : std_logic_vector(31 downto 0) := x"0000000A";
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal adc_en_reg : std_logic_vector(3 downto 0);
signal trigger_sel_reg : std_logic_vector(1 downto 0);
signal nb_bursts_reg : std_logic_vector(31 downto 0);
signal burst_size_reg : std_logic_vector(31 downto 0);
signal cmd_reg : std_logic_vector(31 downto 0);
signal adc_cmd : std_logic_vector(31 downto 0);
signal arm : std_logic;
signal disarm : std_logic;
signal sw_trigger : std_logic;
signal clk_to_fpga : std_logic;
signal ext_trigger : std_logic;
signal register5 : std_logic_vector(31 downto 0);
signal register6 : std_logic_vector(31 downto 0);
signal register7 : std_logic_vector(31 downto 0);
signal register8 : std_logic_vector(31 downto 0);
signal register9 : std_logic_vector(31 downto 0);
signal register10 : std_logic_vector(31 downto 0);
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
stellar_cmd_inst : stellar_generic_cmd
generic map (
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map (
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk_cmd,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd)
begin
if (rst = '1') then
cmd_reg <= (others => '0');
adc_en_reg <= (others=>'0');
trigger_sel_reg <= (others => '0');
nb_bursts_reg <= (others => '0');
burst_size_reg <= (others => '0');
in_reg_val <= '0';
in_reg <= (others => '0');
register5 <= (others =>'0');
register6 <= (others =>'0');
register7 <= (others =>'0');
register8 <= (others =>'0');
elsif (rising_edge(clk_cmd)) then
-----------------------------------------------------------------
-- Write
-----------------------------------------------------------------
if (out_reg_val = '1' and out_reg_addr = ADDR_COMMAND) then
cmd_reg <= out_reg;
else
cmd_reg <= (others => '0');
end if;
if (out_reg_val = '1' and out_reg_addr = ADDR_CONTROL) then
adc_en_reg(0) <= out_reg(0);
adc_en_reg(1) <= out_reg(1);
adc_en_reg(2) <= out_reg(2);
adc_en_reg(3) <= out_reg(3);
trigger_sel_reg <= out_reg(7 downto 6);
end if;
if (out_reg_val = '1' and out_reg_addr = ADDR_NB_BURSTS) then
nb_bursts_reg <= out_reg;
end if;
if (out_reg_val = '1' and out_reg_addr = ADDR_BURST_SIZE) then
burst_size_reg <= out_reg;
end if;
if (out_reg_val = '1' and out_reg_addr = ADDR_REG5) then
register5 <= out_reg;
end if;
if (out_reg_val = '1' and out_reg_addr = ADDR_REG6) then
register6 <= out_reg;
end if;
-----------------------------------------------------------------
-- Read
-----------------------------------------------------------------
if (in_reg_req = '1' and in_reg_addr = ADDR_COMMAND) then
in_reg_val <= '1';
in_reg <= cmd_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_CONTROL) then
in_reg_val <= '1';
in_reg <= x"A5A5" & x"A5A5";
elsif (in_reg_req = '1' and in_reg_addr = ADDR_NB_BURSTS) then
in_reg_val <= '1';
in_reg <= nb_bursts_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_BURST_SIZE) then
in_reg_val <= '1';
in_reg <= burst_size_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_FMC_INFO) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 32);
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG5) then
in_reg_val <= '1';
in_reg <= register5;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG6) then
in_reg_val <= '1';
in_reg <= register6;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG7) then
in_reg_val <= '1';
in_reg <= reg7;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
end if;
end process;
-- register mapping
reg6 <= register6;
----------------------------------------------------------------------------------------------------
-- Transfer command pulses to other ADC0 clock domain
----------------------------------------------------------------------------------------------------
adc_cmd_pls: for i in 0 to 31 generate
pulse2pulse_inst : pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => adc_phy_clk,
rst => rst,
pulsein => cmd_reg(i),
inbusy => open,
pulseout => adc_cmd(i)
);
end generate;
----------------------------------------------------------------------------------------------------
-- Map pulses
----------------------------------------------------------------------------------------------------
arm <= adc_cmd(0);
disarm <= adc_cmd(1);
sw_trigger <= adc_cmd(2);
ext_trigger <= '0';
----------------------------------------------------------------------------------------------------
-- LVDS Trigger Input
----------------------------------------------------------------------------------------------------
generate_fifo_ctrl0:
for I in 0 to 3 generate
fifo_ctrl_inst0:
entity work.fifo_ctrl
port map (
rst => rst,
clk => adc_phy_clk,
arm => arm,
disarm => disarm,
adc0_en_reg => adc_en_reg(0),
sw_trigger => sw_trigger,
trigger_sel_reg => trigger_sel_reg,
fifo_valid => fifo_valid(I),
ext_trigger => ext_trigger,
nb_bursts_reg => nb_bursts_reg,
burst_size_reg => burst_size_reg,
fifo0_wr_en => fifo_wr_en(I)
);
end generate;
--****************************************************************************************************
end Behavioral;
--****************************************************************************************************
| mit | d7355a38835ddd07abb8649a0a1da682 | 0.419695 | 4.04521 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_fifo.vhd | 3 | 25,002 | -------------------------------------------------------------------------------
-- axi_datamover_fifo.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_10.axi_datamover_afifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 )))
or
(C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 0 )
generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_datamover_v5_1_10.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_datamover_v5_1_10.axi_datamover_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Ainit_Rd_clk => fifo_async_rd_reset ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
| gpl-3.0 | f5d93ba03bee2349b7425e688ab361a3 | 0.417447 | 4.483055 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug090/hang7.vhdl | 1 | 1,300 | library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
t_n : in std_logic;
d : c_vector (len - 1 downto 0);
q : out stdector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process p;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : s;
signal rst_n : std_logic;
signal din, dout, dout2 : std_loor (7 downto 0);
component dff is
generic (len : natural := 8);
port (clk : in std_logic;
st_n : in std_logic;
d : std_logic_vector (len - 1 downto 0);
q : out std_logic_vector (len - 1 downto 0));
end component;
begin
mydff : entity work.dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout);
dff2 : dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
rst_n <= '0' after 0 ns, '1' after 4 ns;
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1case
end process;
chkr: process (clk)
begin
if!rst_n = '0' then
null;
elsif rising_edge (av;
| gpl-2.0 | 75749557750ce72092903b5384d5d618 | 0.558462 | 3.073286 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1321/issue.vhdl | 1 | 2,025 | library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
data <= to_bit(seq(index));
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port (
clk : in std_logic
);
end entity issue;
architecture psl of issue is
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
signal req, busy, done : std_logic;
begin
-- 0123456789
SEQ_REQ : sequencer generic map ("_-________") port map (clk, req);
SEQ_BUSY : sequencer generic map ("__-_-_-___") port map (clk, busy);
SEQ_DONE : sequencer generic map ("________-_") port map (clk, done);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- Non consecutive repetition of 3 cycles with possible padding
-- busy has to hold on 3 cycles between req & done
-- This assertion holds
-- Not yet supported
SERE_0_a : assert always {req} |=> {busy[=3]; done};
-- Non consecutive repetition of 2 to 4 cycles with possible padding
-- busy has to hold on 2 to 4 cycles between req & done
-- This assertion holds
-- Not yet supported
SERE_1_a : assert always {req} |=> {busy[=2 to 4]; done};
end architecture psl;
| gpl-2.0 | 807407e13decc2564306691755a9156d | 0.600988 | 3.629032 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff02/dff08d.vhdl | 1 | 540 | library ieee;
use ieee.std_logic_1164.all;
entity dff08d is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic;
en : std_logic;
rst : std_logic);
end dff08d;
architecture behav of dff08d is
constant c : std_logic_vector(7 downto 0) := x"aa";
signal p : std_logic_vector(7 downto 0) := c;
begin
process (clk, rst) is
begin
if rst = '1' then
p <= c;
elsif rising_edge (clk) then
p <= d;
end if;
end process;
q <= p;
end behav;
| gpl-2.0 | 2a5823803951c325209f6fa6f554ad54 | 0.588889 | 3 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd | 4 | 2,058 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
-- code from book:
type small_int is range 1 to 4;
type small_array is array (small_int range <>) of -- . . . ;
-- not in book
MVL4_ulogic;
-- end not in book
-- end of code from book
type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
variable result : MVL4_ulogic := 'Z';
begin
for index in contribution'range loop
result := resolution_table(result, contribution(index));
end loop;
return result;
end function resolve_MVL4;
subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
signal s : MVL4_logic;
begin
driver_1 : s <= 'Z';
driver_2 : s <= 'Z';
driver_3 : s <= 'Z';
driver_4 : s <= 'Z';
driver_5 : s <= 'Z';
end architecture test;
| gpl-2.0 | d1a87130223cee6b96e07c3231aab465 | 0.602041 | 3.523973 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2259.vhd | 4 | 6,739 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2259.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p05n01i02259ent IS
END c07s02b06x00p05n01i02259ent;
ARCHITECTURE c07s02b06x00p05n01i02259arch OF c07s02b06x00p05n01i02259ent IS
BEGIN
TESTING: PROCESS
constant mod11 : integer := (1 - 4) mod (1 - 4);
constant mod12 : integer := (1 - 4) mod (2 - 4);
constant mod13 : integer := (1 - 4) mod (3 - 4);
constant mod15 : integer := (1 - 4) mod (5 - 4);
constant mod16 : integer := (1 - 4) mod (6 - 4);
constant mod17 : integer := (1 - 4) mod (7 - 4);
constant mod18 : integer := (1 - 4) mod (8 - 4);
constant mod19 : integer := (1 - 4) mod (9 - 4);
constant mod41 : integer := (4 - 4) mod (1 - 4);
constant mod42 : integer := (4 - 4) mod (2 - 4);
constant mod43 : integer := (4 - 4) mod (3 - 4);
constant mod45 : integer := (4 - 4) mod (5 - 4);
constant mod46 : integer := (4 - 4) mod (6 - 4);
constant mod47 : integer := (4 - 4) mod (7 - 4);
constant mod48 : integer := (4 - 4) mod (8 - 4);
constant mod49 : integer := (4 - 4) mod (9 - 4);
constant mod61 : integer := (6 - 4) mod (1 - 4);
constant mod62 : integer := (6 - 4) mod (2 - 4);
constant mod63 : integer := (6 - 4) mod (3 - 4);
constant mod65 : integer := (6 - 4) mod (5 - 4);
constant mod66 : integer := (6 - 4) mod (6 - 4);
constant mod67 : integer := (6 - 4) mod (7 - 4);
constant mod68 : integer := (6 - 4) mod (8 - 4);
constant mod69 : integer := (6 - 4) mod (9 - 4);
variable four : integer := 4;
BEGIN
assert mod11 = (1 - four) mod (1 - four);
assert mod12 = (1 - four) mod (2 - four);
assert mod13 = (1 - four) mod (3 - four);
assert mod15 = (1 - four) mod (5 - four);
assert mod16 = (1 - four) mod (6 - four);
assert mod17 = (1 - four) mod (7 - four);
assert mod18 = (1 - four) mod (8 - four);
assert mod19 = (1 - four) mod (9 - four);
assert mod41 = (4 - four) mod (1 - four);
assert mod42 = (4 - four) mod (2 - four);
assert mod43 = (4 - four) mod (3 - four);
assert mod45 = (4 - four) mod (5 - four);
assert mod46 = (4 - four) mod (6 - four);
assert mod47 = (4 - four) mod (7 - four);
assert mod48 = (4 - four) mod (8 - four);
assert mod49 = (4 - four) mod (9 - four);
assert mod61 = (6 - four) mod (1 - four);
assert mod62 = (6 - four) mod (2 - four);
assert mod63 = (6 - four) mod (3 - four);
assert mod65 = (6 - four) mod (5 - four);
assert mod66 = (6 - four) mod (6 - four);
assert mod67 = (6 - four) mod (7 - four);
assert mod68 = (6 - four) mod (8 - four);
assert mod69 = (6 - four) mod (9 - four);
assert NOT((mod11 = (1 - four) mod (1 - four)) and
( mod12 = (1 - four) mod (2 - four)) and
( mod13 = (1 - four) mod (3 - four)) and
( mod15 = (1 - four) mod (5 - four)) and
( mod16 = (1 - four) mod (6 - four)) and
( mod17 = (1 - four) mod (7 - four)) and
( mod18 = (1 - four) mod (8 - four)) and
( mod19 = (1 - four) mod (9 - four)) and
( mod41 = (4 - four) mod (1 - four)) and
( mod42 = (4 - four) mod (2 - four)) and
( mod43 = (4 - four) mod (3 - four)) and
( mod45 = (4 - four) mod (5 - four)) and
( mod46 = (4 - four) mod (6 - four)) and
( mod47 = (4 - four) mod (7 - four)) and
( mod48 = (4 - four) mod (8 - four)) and
( mod49 = (4 - four) mod (9 - four)) and
( mod61 = (6 - four) mod (1 - four)) and
( mod62 = (6 - four) mod (2 - four)) and
( mod63 = (6 - four) mod (3 - four)) and
( mod65 = (6 - four) mod (5 - four)) and
( mod66 = (6 - four) mod (6 - four)) and
( mod67 = (6 - four) mod (7 - four)) and
( mod68 = (6 - four) mod (8 - four)) and
( mod69 = (6 - four) mod (9 - four)) )
report "***PASSED TEST: c07s02b06x00p05n01i02259"
severity NOTE;
assert (( mod11 = (1 - four) mod (1 - four)) and
( mod12 = (1 - four) mod (2 - four)) and
( mod13 = (1 - four) mod (3 - four)) and
( mod15 = (1 - four) mod (5 - four)) and
( mod16 = (1 - four) mod (6 - four)) and
( mod17 = (1 - four) mod (7 - four)) and
( mod18 = (1 - four) mod (8 - four)) and
( mod19 = (1 - four) mod (9 - four)) and
( mod41 = (4 - four) mod (1 - four)) and
( mod42 = (4 - four) mod (2 - four)) and
( mod43 = (4 - four) mod (3 - four)) and
( mod45 = (4 - four) mod (5 - four)) and
( mod46 = (4 - four) mod (6 - four)) and
( mod47 = (4 - four) mod (7 - four)) and
( mod48 = (4 - four) mod (8 - four)) and
( mod49 = (4 - four) mod (9 - four)) and
( mod61 = (6 - four) mod (1 - four)) and
( mod62 = (6 - four) mod (2 - four)) and
( mod63 = (6 - four) mod (3 - four)) and
( mod65 = (6 - four) mod (5 - four)) and
( mod66 = (6 - four) mod (6 - four)) and
( mod67 = (6 - four) mod (7 - four)) and
( mod68 = (6 - four) mod (8 - four)) and
( mod69 = (6 - four) mod (9 - four)) )
report "***FAILED TEST: c07s02b06x00p05n01i02259 - Constant integer type mod test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p05n01i02259arch;
| gpl-2.0 | 8c1284e2c5de5f9107492d5bb9478ba6 | 0.49859 | 3.165336 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_pkg.vhd | 8 | 23,668 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
package axi_dma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Find minimum required btt width
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer;
-- Return correct hertz paramter value
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer;
-- Return SnF enable or disable
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
--constant NUM_REG_TOTAL : integer := 18;
--constant NUM_REG_TOTAL : integer := 23;
constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers
--constant NUM_REG_PER_CHANNEL : integer := 6;
constant NUM_REG_PER_CHANNEL : integer := 12;
constant NUM_REG_PER_S2MM : integer := 120;
--constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
constant CMD_BASE_WIDTH : integer := 40;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Lite AXI DMA Register Offsets
-------------------------------------------------------------------------------
constant MM2S_DMACR_INDEX : integer := 0;
constant MM2S_DMASR_INDEX : integer := 1;
constant MM2S_CURDESC_LSB_INDEX : integer := 2;
constant MM2S_CURDESC_MSB_INDEX : integer := 3;
constant MM2S_TAILDESC_LSB_INDEX : integer := 4;
constant MM2S_TAILDESC_MSB_INDEX : integer := 5;
constant MM2S_SA_INDEX : integer := 6;
constant MM2S_SA2_INDEX : integer := 7;
constant RESERVED_20_INDEX : integer := 8;
constant RESERVED_24_INDEX : integer := 9;
constant MM2S_LENGTH_INDEX : integer := 10;
constant RESERVED_2C_INDEX : integer := 11;
constant S2MM_DMACR_INDEX : integer := 12;
constant S2MM_DMASR_INDEX : integer := 13;
constant S2MM_CURDESC_LSB_INDEX : integer := 14;
constant S2MM_CURDESC_MSB_INDEX : integer := 15;
constant S2MM_TAILDESC_LSB_INDEX : integer := 16;
constant S2MM_TAILDESC_MSB_INDEX : integer := 17;
constant S2MM_DA_INDEX : integer := 18;
constant S2MM_DA2_INDEX : integer := 19;
constant RESERVED_50_INDEX : integer := 20;
constant RESERVED_54_INDEX : integer := 21;
--constant S2MM_LENGTH_INDEX : integer := 22;
constant S2MM_LENGTH_INDEX : integer := 142;
constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00
constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04
constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08
constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C
constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10
constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14
constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18
constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C
constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20
constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24
constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28
-- Following was reserved, now is used for SG xCache and xUser
constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C
constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30
constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34
constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38
constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C
constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40
constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44
constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034
constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C
constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50
constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54
constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58
-- New registers for S2MM channels
constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70
constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74
constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78
constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C
constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90
constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94
constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98
constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C
constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0
constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4
constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8
constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC
constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0
constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4
constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8
constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC
constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0
constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4
constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8
constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC
constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110
constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114
constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118
constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C
constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130
constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134
constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138
constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C
constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150
constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154
constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158
constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C
constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170
constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174
constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178
constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C
constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190
constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194
constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198
constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C
constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0
constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4
constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8
constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC
constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0
constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4
constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8
constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC
constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0
constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4
constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8
constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC
constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210
constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214
constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218
constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C
constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230
constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234
constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238
constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RS_BIT : integer := 0;
constant DMACR_TAILPEN_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_KH_BIT : integer := 3;
constant CYCLIC_BIT : integer := 4;
--constant DMACR_RESERVED3_BIT : integer := 3;
--constant DMACR_RESERVED4_BIT : integer := 4;
constant DMACR_RESERVED5_BIT : integer := 5;
constant DMACR_RESERVED6_BIT : integer := 6;
constant DMACR_RESERVED7_BIT : integer := 7;
constant DMACR_RESERVED8_BIT : integer := 8;
constant DMACR_RESERVED9_BIT : integer := 9;
constant DMACR_RESERVED10_BIT : integer := 10;
constant DMACR_RESERVED11_BIT : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_CMPLT_BIT : integer := 2;
constant DMASR_ERROR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_RESERVED7_BIT : integer := 7;
constant DMASR_SGINTERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_RESERVED15_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 6;
constant CURDESC_RESERVED_BIT5 : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
constant CURDESC_RESERVED_BIT3 : integer := 3;
constant CURDESC_RESERVED_BIT2 : integer := 2;
constant CURDESC_RESERVED_BIT1 : integer := 1;
constant CURDESC_RESERVED_BIT0 : integer := 0;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 6;
constant TAILDESC_RESERVED_BIT5 : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Control Bits
constant DESC_BLENGTH_LSB_BIT : integer := 0;
constant DESC_BLENGTH_MSB_BIT : integer := 22;
constant DESC_RSVD23_BIT : integer := 23;
constant DESC_RSVD24_BIT : integer := 24;
constant DESC_RSVD25_BIT : integer := 25;
constant DESC_EOF_BIT : integer := 26;
constant DESC_SOF_BIT : integer := 27;
constant DESC_RSVD28_BIT : integer := 28;
constant DESC_RSVD29_BIT : integer := 29;
constant DESC_RSVD30_BIT : integer := 30;
constant DESC_IOC_BIT : integer := 31;
-- Descriptor Status Bits
constant DESC_STS_CMPLTD_BIT : integer := 31;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_RXSOF_BIT : integer := 27;
constant DESC_STS_RXEOF_BIT : integer := 26;
constant DESC_STS_RSVD25_BIT : integer := 25;
constant DESC_STS_RSVD24_BIT : integer := 24;
constant DESC_STS_RSVD23_BIT : integer := 23;
constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22;
constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
end axi_dma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_dma_pkg is
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width ( dwidth : integer;
burst_size: integer;
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width;
-------------------------------------------------------------------------------
-- function to return Frequency Hertz parameter based on inclusion of sg engine
-------------------------------------------------------------------------------
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer is
begin
-- 1 = Scatter Gather Included
-- 0 = Scatter Gather Excluded
if(included = 1)then
return sg_frequency;
else
return lite_frequency;
end if;
end;
-------------------------------------------------------------------------------
-- function to enable store and forward based on data width mismatch
-- or directly enabled
-------------------------------------------------------------------------------
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer is
begin
-- If store and forward enable or data widths do not
-- match then return 1 to enable snf
if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then
return 1;
else
-- coverage off
return 0;
-- coverage on
end if;
end;
end package body axi_dma_pkg;
| gpl-3.0 | 3e3509c4fffce09bb100e78df4a3dab0 | 0.600389 | 3.73548 | false | false | false | false |
nickg/nvc | test/lower/cond1.vhd | 1 | 397 | entity cond1 is
end entity;
architecture test of cond1 is
signal x : integer := 5;
begin
p1: process is
variable y : integer;
begin
if x = y then
y := 2;
end if;
if x = y + 1 then
y := 1;
else
y := 3;
null;
end if;
report "doo";
wait;
end process;
end architecture;
| gpl-3.0 | ceee4b52f3c2d95198797b2d147ff74d | 0.448363 | 3.97 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_quant_tbl_quantval.vhd | 2 | 1,454 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_quant_tbl_quantval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_quant_tbl_quantval;
architecture augh of p_jinfo_quant_tbl_quantval is
-- Embedded RAM
type ram_type is array (0 to 255) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 5991ab079aede9919e2dc853b5d31ac5 | 0.677442 | 2.879208 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth109/ram3.vhdl | 1 | 1,816 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ram2 is
generic (
WIDTH : integer := 32;
SIZE : integer := 64;
ADDRWIDTH : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end ram2;
architecture behavioral of ram2 is
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal regA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal regB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
regA <= readA;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
readB <= ram(conv_integer(addrB));
end if;
regB <= readB;
end if;
end process;
doA <= regA;
doB <= regB;
end behavioral;
| gpl-2.0 | ec22caba03f1ae451a19887cce940e2b | 0.575991 | 3.248658 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth109/asymmetric_ram_2a.vhd | 1 | 3,507 | --
-- Asymmetric port RAM
-- Port A is 256x8-bit read-and-write (write-first synchronization)
-- Port B is 64x32-bit read-and-write (write-first synchronization)
--
-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
-- File: HDL_Coding_Techniques/rams/asymmetric_ram_2a.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity asymmetric_ram_2a is
generic (
WIDTHA : integer := 8;
SIZEA : integer := 256;
ADDRWIDTHA : integer := 8;
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
diA : in std_logic_vector(WIDTHA-1 downto 0);
diB : in std_logic_vector(WIDTHB-1 downto 0);
doA : out std_logic_vector(WIDTHA-1 downto 0);
doB : out std_logic_vector(WIDTHB-1 downto 0)
);
end asymmetric_ram_2a;
architecture behavioral of asymmetric_ram_2a is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant minWIDTH : integer := min(WIDTHA,WIDTHB);
constant maxWIDTH : integer := max(WIDTHA,WIDTHB);
constant maxSIZE : integer := max(SIZEA,SIZEB);
constant RATIO : integer := maxWIDTH / minWIDTH;
type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
signal regA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0');
signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
regA <= readA;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB&conv_std_logic_vector(0,2))) := diB(minWIDTH-1 downto 0);
ram(conv_integer(addrB&conv_std_logic_vector(1,2))) := diB(2*minWIDTH-1 downto minWIDTH);
ram(conv_integer(addrB&conv_std_logic_vector(2,2))) := diB(3*minWIDTH-1 downto 2*minWIDTH);
ram(conv_integer(addrB&conv_std_logic_vector(3,2))) := diB(4*minWIDTH-1 downto 3*minWIDTH);
end if;
readB(minWIDTH-1 downto 0) <= ram(conv_integer(addrB&conv_std_logic_vector(0,2)));
readB(2*minWIDTH-1 downto minWIDTH) <= ram(conv_integer(addrB&conv_std_logic_vector(1,2)));
readB(3*minWIDTH-1 downto 2*minWIDTH) <= ram(conv_integer(addrB&conv_std_logic_vector(2,2)));
readB(4*minWIDTH-1 downto 3*minWIDTH) <= ram(conv_integer(addrB&conv_std_logic_vector(3,2)));
end if;
regB <= readB;
end if;
end process;
doA <= regA;
doB <= regB;
end behavioral;
| gpl-2.0 | 9a62bf1b912218646d9bf45a4a819c80 | 0.611064 | 3.271455 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd | 4 | 24,794 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : VCOAnalog.vhd
-- Author : Mentor Graphics
-- Created : 2001/07/11
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Analog Voltage Controlled Oscillator
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/07/11 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity VCOAnalog is
generic (
Kv : real := 100.0e3; -- VCO Gain [Hz/Volt]
Fc : real := 1.0e6; -- center freq [Hz]
Vc : voltage := 2.5; -- input voltage that gives fc [Volts]
Vcmin : voltage := 0.0; -- control voltage mininum [Volts]
Vcmax : voltage := 5.0; -- control voltage maximum [Volts]
Vout_ampl : voltage := 1.0; -- amplitude of output [Volts]
Vout_offset : voltage := 0.0 -- offset voltage of output [Volts]
);
port (
terminal v_inp, v_inm, output : electrical);
end entity VCOAnalog;
-------------------------------------------------------------------------------
-- VCO Equation:
-- Fout = Fc + Kv*Vin
-------------------------------------------------------------------------------
architecture behavioral of VCOAnalog is
quantity vout across iout through output to electrical_ref;
quantity vctrl across v_inp to v_inm;
quantity phi : real;
quantity vtmp : real;
constant Kv_w : real := math_2_pi*Kv; -- convert to (Rad/s)/Volt
constant wc : real := math_2_pi*Fc; -- convert freq to Rad/s
begin -- ARCHITECTURE behavioral
if vctrl > Vcmax use -- test control voltage for limits
vtmp == Vcmax;
elsif vctrl < Vcmin use
vtmp == Vcmin;
else
vtmp == vctrl;
end use;
if domain = quiescent_domain use
phi == 0.0;
else
-- use one of the following equations depending on preference
-- phi'dot == Fc + Kv*(vtmp-Vc); -- Calculate output Freq in Rad/s
phi'dot == wc + Kv_w*(vtmp-Vc); -- Calculate output Freq in Hz
end use;
-- Use one of the following equations depending on phi'dot equation above
--vout == Vout_offset + Vout_ampl*cos(math_2_pi*phi);
vout == Vout_offset + Vout_ampl*cos(phi);
end architecture behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : vLeadLag.vhd
-- Author : Mentor Graphics
-- Created : 2001/11/09
-- Last update: 2001/11/27
-------------------------------------------------------------------------------
-- Description: Lead-Lag filter with electrical connections
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/11/09 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity vLeadLag is
generic (
K : real := 1.0; -- gain
Fp : real := 20.0e3; -- pole frequency
Fz : real := 1.0e6); -- zero frequency
port (
terminal input, output : electrical);
end entity vLeadLag;
-------------------------------------------------------------------------------
-- Transfer Fucntion:
--
-- 1 + (s/wz)
-- H(s) = K * ------------
-- 1 + (s/wp)
--
-------------------------------------------------------------------------------
architecture behavioral of vLeadLag is
quantity vin across input to electrical_ref;
quantity vout across iout through output to electrical_ref;
constant wp : real := math_2_pi*Fp; -- Pole freq (in radians)
constant wz : real := math_2_pi*Fz; -- Zero freq (in radians)
constant num : real_vector := (1.0, 1.0/wz);
constant den : real_vector := (1.0, 1.0/wp);
begin
vout == K * vin'ltf(num, den); -- Laplace transform of input
end architecture behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : vMult.vhd
-- Author : Mentor Graphics
-- Created : 2001/11/09
-- Last update: 2001/11/09
-------------------------------------------------------------------------------
-- Description: Two input Multiplier with electrical connections
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/11/09 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity vMult is
generic (K : real := 1.0); -- Gain
port (
terminal in1, in2 : electrical;
terminal output : electrical);
end entity vMult;
architecture behavioral of vMult is
quantity vin1 across in1 to electrical_ref;
quantity vin2 across in2 to electrical_ref;
quantity vout across iout through output to electrical_ref;
begin
vout == k * vin1 * vin2;
end architecture behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity PLL is
port(
terminal lf_out : electrical;
terminal input : electrical;
terminal vco_out : electrical
);
end PLL;
architecture PLL of PLL is
-- Component declarations
-- Signal declarations
terminal pd_out : electrical;
begin
-- Signal assignments
-- Component instances
vco2 : entity work.VCOAnalog(behavioral)
generic map(
Fc => 455.0e3,
Vcmax => 5.0,
Vcmin => -5.0,
Vc => 0.0
)
port map(
v_inp => lf_out,
output => vco_out,
v_inm => ELECTRICAL_REF
);
vLeadLag1 : entity work.vLeadLag(behavioral)
generic map(
Fz => 500.0e3
)
port map(
input => pd_out,
output => lf_out
);
vmult1 : entity work.vMult(behavioral)
port map(
in1 => input,
in2 => vco_out,
output => pd_out
);
end PLL;
--
-- Model of Binary Frequency Shift Keying (BFSK) modulator
-- with digital input and analog output
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.MATH_REAL.all;
entity bfsk is
generic (
fc : real := 455.0e3; -- Mean carrier frequency
delta_f : real := 5.0e3; -- Difference between low and high carrier frequency
amp : voltage := 1.0; -- Amplitude of modulated signal
offset : voltage := 0.0 -- output offset voltage
);
port (
d_in : in std_logic; -- digital input
terminal a_out : electrical -- output terminal
);
end entity bfsk;
architecture behavioral of bfsk is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity for angle in radians
constant wc : real := math_2_pi*fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi*delta_f; -- convert delta_f to rad/s
begin
if (d_in = '0') use
phi'dot == wc; -- set to carrier frequency
elsif (d_in = '1') use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
vout == offset + amp*sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : vLPF_2nd.vhd
-- Author : Mentor Graphics
-- Created : 2001/11/27
-- Last update: 2001/11/27
-------------------------------------------------------------------------------
-- Description: 2nd order Lowpass Filter with Electrical connections
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/11/27 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity vLPF_2nd is
generic ( K : real := 1.0; -- Filter Gain
Fp : real; -- Double Pole Frequency [Hz]
Q : real := 0.707 -- Quality factor
);
port ( terminal input : electrical;
terminal output : electrical
);
end entity vLPF_2nd;
-------------------------------------------------------------------------------
-- Transfer Function:
--
-- wp^2
-- Vo(s) = K * --------------------- Vin(s)
-- S^2 + (wp/Q)*s + wp^2
-------------------------------------------------------------------------------
architecture behavioral of vLPF_2nd is
quantity vin across input;
quantity vout across iout through output;
constant wp : real := math_2_pi*Fp; -- Frequency in Radians
constant num : real_vector := (wp*wp, 0.0, 0.0); -- Numerator array
constant den : real_vector := (wp*wp, wp/Q, 1.0); -- Denominator array
begin
vout == K * vin'ltf(num, den); -- Laplace Transform of input
end architecture behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
entity MeasFreq is
generic ( thres : real := 0.0 ); -- threshold crossing
port ( terminal input : electrical;
signal f_out : out real := 0.0);
end entity MeasFreq;
architecture ThresDetect of MeasFreq is
quantity vin across input;
-- signal freq : real := 0.0;
begin
-- f_out <= freq;
detect : process (vin'above(thres)) is
variable t_old : real := real'low;
begin
if vin'above(thres) then
f_out <= 1.0 / (now - t_old);
t_old := now;
end if;
end process detect;
end ThresDetect;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : a2d_bit.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Ideal one bit A/D converter
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity a2d_bit is
generic (
thres : real := 2.5); -- Threshold to determine logic output
port (
terminal a : electrical; -- analog input
signal d : out std_logic); -- digital (std_logic) output
end entity a2d_bit;
-------------------------------------------------------------------------------
-- Ideal architecture
-- Uses 'above operator to detect threshold crossing
-------------------------------------------------------------------------------
architecture ideal of a2d_bit is
quantity vin across a;
begin
-- purpose: Detect threshold crossing and assign event on output (d)
-- type : combinational
-- inputs : vin'above(thres)
-- outputs: pulse_signal
process (vin'above(thres)) is
begin -- PROCESS
if vin'above(thres) then
d <= '1';
else
d <= '0';
end if;
end process;
end ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity tb_CS4_CommSys_PLL is
end tb_CS4_CommSys_PLL;
architecture TB_CS4_CommSys_PLL of tb_CS4_CommSys_PLL is
-- Component declarations
-- Signal declarations
terminal a_out : electrical;
signal baseband : std_logic;
terminal fsk_out : electrical;
signal fsk_out_f : real;
terminal lpf_pll_out : electrical;
terminal vco_out : electrical;
signal bitstream : std_logic;
signal vco_out_f : real;
begin
-- Signal assignments
-- Component instances
pll3 : entity work.PLL
port map(
vco_out => vco_out,
input => fsk_out,
lf_out => lpf_pll_out
);
BFSK4 : entity work.bfsk(behavioral)
port map(
d_in => bitstream,
a_out => fsk_out
);
vLPF1 : entity work.vLPF_2nd(behavioral)
generic map(
K => 200.0,
Fp => 50.0e3
)
port map(
input => lpf_pll_out,
output => a_out
);
MeasFreq8 : entity work.MeasFreq(ThresDetect)
port map(
input => fsk_out,
f_out => fsk_out_f
);
MeasFreq9 : entity work.MeasFreq(ThresDetect)
port map(
input => vco_out,
f_out => vco_out_f
);
a4 : entity work.a2d_bit(ideal)
port map(
D => baseband,
A => a_out
);
-- bitstream
P_bitstream :
process
begin
-- 0.000
wait for 0.000 ns; bitstream <= '0';
-- 50000.000
wait for 50000.000 ns; bitstream <= '1';
-- 100000.000
wait for 50000.000 ns; bitstream <= '0';
-- 150000.000
wait for 50000.000 ns; bitstream <= '1';
-- 200000.000
wait for 50000.000 ns; bitstream <= '0';
-- 300000.000
wait for 100000.000 ns; bitstream <= '1';
-- 501000.000
wait for 201000.000 ns; bitstream <= '0';
-- 550000.000
wait for 49000.000 ns; bitstream <= '1';
-- 600000.000
wait for 50000.000 ns; bitstream <= '0';
wait;
end process;
end TB_CS4_CommSys_PLL;
| gpl-2.0 | d9f75bea4da0df1faa288fb6844757d5 | 0.569493 | 4.594034 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_11.vhd | 4 | 4,493 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package body bounded_buffer_adt is
function new_bounded_buffer ( size : in positive ) return bounded_buffer is
begin
return new bounded_buffer_object'(
byte_count => 0, head_index => 0, tail_index => 0,
store => new store_array(0 to size - 1) );
end function new_bounded_buffer;
procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
is_empty : out boolean ) is
begin
is_empty := the_bounded_buffer.byte_count = 0;
end procedure test_empty;
procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
is_full : out boolean ) is
begin
is_full := the_bounded_buffer.byte_count = the_bounded_buffer.store'length;
end procedure test_full;
procedure write ( the_bounded_buffer : inout bounded_buffer; data : in byte ) is
variable buffer_full : boolean;
begin
test_full(the_bounded_buffer, buffer_full);
if buffer_full then
report "write to full bounded buffer" severity failure;
else
the_bounded_buffer.store(the_bounded_buffer.tail_index) := data;
the_bounded_buffer.tail_index := (the_bounded_buffer.tail_index + 1)
mod the_bounded_buffer.store'length;
the_bounded_buffer.byte_count := the_bounded_buffer.byte_count + 1;
end if;
end procedure write;
procedure read ( the_bounded_buffer : inout bounded_buffer; data : out byte ) is
variable buffer_empty : boolean;
begin
test_empty(the_bounded_buffer, buffer_empty);
if buffer_empty then
report "read from empty bounded buffer" severity failure;
else
data := the_bounded_buffer.store(the_bounded_buffer.head_index);
the_bounded_buffer.head_index := (the_bounded_buffer.head_index + 1)
mod the_bounded_buffer.store'length;
the_bounded_buffer.byte_count := the_bounded_buffer.byte_count - 1;
end if;
end procedure read;
end package body bounded_buffer_adt;
-- not in book
entity fg_17_11 is
end entity fg_17_11;
architecture test of fg_17_11 is
begin
process is
use work.bounded_buffer_adt.all;
variable buf : bounded_buffer := new_bounded_buffer(4);
variable empty, full : boolean;
variable d : byte;
begin
test_empty(buf, empty);
assert empty;
test_full(buf, full);
assert not full;
write(buf, X"01");
write(buf, X"02");
test_empty(buf, empty);
assert not empty;
test_full(buf, full);
assert not full;
write(buf, X"03");
write(buf, X"04");
test_empty(buf, empty);
assert not empty;
test_full(buf, full);
assert full;
write(buf, X"05");
read(buf, d);
read(buf, d);
test_empty(buf, empty);
assert not empty;
test_full(buf, full);
assert not full;
read(buf, d);
read(buf, d);
test_empty(buf, empty);
assert empty;
test_full(buf, full);
assert not full;
read(buf, d);
write(buf, X"06");
write(buf, X"07");
write(buf, X"08");
read(buf, d);
read(buf, d);
write(buf, X"09");
read(buf, d);
write(buf, X"0A");
read(buf, d);
write(buf, X"0B");
read(buf, d);
write(buf, X"0C");
read(buf, d);
write(buf, X"0D");
read(buf, d);
write(buf, X"0E");
read(buf, d);
write(buf, X"0F");
read(buf, d);
wait;
end process;
end architecture test;
-- end not in book
| gpl-2.0 | 0f48352eee4220dd33496efd4c75917d | 0.612286 | 3.626312 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1021/test.vhdl | 1 | 1,525 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity test is
generic(
ROW_BITS : integer := 4;
WIDTH : integer := 64
);
port(
clk : in std_logic;
rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
rd_data : out std_logic_vector(WIDTH - 1 downto 0);
wr_en : in std_logic;
wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
wr_data : in std_logic_vector(WIDTH - 1 downto 0)
);
end test;
architecture rtl of test is
constant SIZE : integer := 2**ROW_BITS;
type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
signal ram : ram_type;
begin
process(clk)
variable lbit : integer range 0 to WIDTH - 1;
variable mbit : integer range 0 to WIDTH - 1;
variable widx : integer range 0 to SIZE - 1;
begin
if rising_edge(clk) then
if wr_en = '1' then
for i in 0 to WIDTH/8-1 loop
lbit := i * 8;
mbit := lbit + 7;
widx := to_integer(unsigned(wr_addr));
if wr_sel(i) = '1' then
ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
end if;
end loop;
end if;
rd_data <= ram(to_integer(unsigned(rd_addr)));
end if;
end process;
end;
| gpl-2.0 | 765d909f2c7fc9261ab3a51bbcbfc012 | 0.517377 | 3.571429 | false | true | false | false |
tgingold/ghdl | testsuite/synth/dff01/tb_dff10.vhdl | 1 | 774 | entity tb_dff10 is
end tb_dff10;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff10 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
signal en : std_logic;
begin
dut: entity work.dff10
port map (
q => dout,
d => din,
clk => clk,
rst => rst,
en => en);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
en <= '1';
wait for 1 ns;
assert dout = x"55" severity failure;
rst <= '0';
din <= x"7e";
pulse;
assert dout = x"7e" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 49a461f53780f6dc25531b838c3ecdcd | 0.559432 | 3.238494 | false | false | false | false |
nickg/nvc | test/parse/conc.vhd | 1 | 722 | entity ee is end entity;
architecture aa of ee is
signal x, a, b, c : bit;
signal foo, bar : boolean;
signal y : integer;
signal v : bit_vector(1 to 2);
procedure pcall(x : in bit; y : in integer);
procedure xxx;
begin
x <= a or b;
postponed x <= '1' when foo
else '1' when bar
else '0';
with y select x <=
'0' when 6,
'1' when 5,
'1' when others;
pcall(x, y);
assert y = 5;
(a, b) <= v;
xxx;
b1: block is
generic ( g1 : integer; g2 : bit := '1' );
generic map ( g1 => 5 );
port ( p1 : integer );
port map ( p1 => y );
begin
end block;
end architecture;
| gpl-3.0 | a5497f5426790b31db6d1417a82b715f | 0.475069 | 3.373832 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc503.vhd | 4 | 2,114 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc503.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p03n01i00503ent IS
END c03s02b02x00p03n01i00503ent;
ARCHITECTURE c03s02b02x00p03n01i00503arch OF c03s02b02x00p03n01i00503ent IS
type R2 is record
R11,R12 : INTEGER;
R21,R22,R23 : BOOLEAN;
end record;
BEGIN
TESTING: PROCESS
variable k : R2;
BEGIN
k.R11 := 1;
k.R12 := 2;
k.R21 := true;
k.R22 := false;
k.R23 := true;
wait for 2 ns;
assert NOT(k.R11=1 and k.R12=2 and k.R21=true and k.R22=false and k.R23=true)
report "***PASSED TEST: c03s02b02x00p03n01i00503"
severity NOTE;
assert (k.R11=1 and k.R12=2 and k.R21=true and k.R22=false and k.R23=true)
report "***FAILED TEST: c03s02b02x00p03n01i00503 - A multiple object declaration is equivalent to a sequence of the corresponding number of single object declarations."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p03n01i00503arch;
| gpl-2.0 | 7a90ff8d8c1a42b24b2732f0dea0df6b | 0.653737 | 3.437398 | false | true | false | false |
nickg/nvc | test/regress/vests35.vhd | 1 | 20,408 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc31.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests35 IS
END vests35;
ARCHITECTURE c04s03b01x01p01n01i00031arch OF vests35 IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; -- unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; -- constrained array type
SUBTYPE ust_subchary IS ut_chary; -- unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); -- constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); -- constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 1 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
BEGIN
TESTING: PROCESS
--
-- Constant declarations - without range constraint
--
CONSTANT STRING_con_1 : STRING := "sailing";
CONSTANT STRING_con_2 : STRING := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
CONSTANT BIT_VECTOR_con_1 : BIT_VECTOR := B"10101110";
CONSTANT BIT_VECTOR_con_2 : BIT_VECTOR := ( '1', '0', '1', '0', '1', '1', '1', '0');
CONSTANT ut_chary_con : ut_chary := ( 1, 2, 3, 9, 8, 7);
CONSTANT ct_word_con : ct_word := ( '0', '0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0', '0');
CONSTANT cst_str10_con_1 : cst_str10 := "abcdefghij";
CONSTANT cst_str10_con_2 : cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');
CONSTANT cst_digit_con : cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
CONSTANT rt_date_con : rt_date := (1, Jan, 1989);
CONSTANT rst_date_con : rst_date := (1, Apr, 2000);
----------------------------------------------------------------------------------------------------------
BEGIN
ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(NUL) = 1 REPORT "ut_chary_con('a') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(SOH) = 2 REPORT "ut_chary_con('b') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(STX) = 3 REPORT "ut_chary_con('c') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(ETX) = 9 REPORT "ut_chary_con('d') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(EOT) = 8 REPORT "ut_chary_con('e') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(ENQ) = 7 REPORT "ut_chary_con('f') not properly intialized" SEVERITY FAILURE;
FOR I IN 0 TO 15
LOOP
ASSERT ct_word_con(I) = '0' REPORT "ct_word_con(I) not properly intialized" SEVERITY FAILURE;
END LOOP;
ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('0') = 0 REPORT "cst_digit_con('0') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('1') = 1 REPORT "cst_digit_con('1') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('2') = 2 REPORT "cst_digit_con('2') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('3') = 3 REPORT "cst_digit_con('3') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('4') = 4 REPORT "cst_digit_con('4') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('5') = 5 REPORT "cst_digit_con('5') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('6') = 6 REPORT "cst_digit_con('6') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('7') = 7 REPORT "cst_digit_con('7') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('8') = 8 REPORT "cst_digit_con('8') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('9') = 9 REPORT "cst_digit_con('9') not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con.day = 1 REPORT "rt_date_con.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con.month = Jan REPORT "rt_date_con.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con.year = 1989 REPORT "rt_date_con.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con.day = 1 REPORT "rst_date_con.day not properly intialized" SEVERITY
FAILURE;
ASSERT rst_date_con.month = Apr REPORT "rst_date_con.month not properly intialized" SEVERITY
FAILURE;
ASSERT rst_date_con.year = 2000 REPORT "rst_date_con.year not properly intialized" SEVERITY
FAILURE;
---------------------------------------------------------------------------------------------
assert NOT( STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con(NUL) = 1 and
ut_chary_con(SOH) = 2 and
ut_chary_con(STX) = 3 and
ut_chary_con(ETX) = 9 and
ut_chary_con(EOT) = 8 and
ut_chary_con(ENQ) = 7 and
ct_word_con(0) = '0' and
ct_word_con(1) = '0' and
ct_word_con(2) = '0' and
ct_word_con(3) = '0' and
ct_word_con(4) = '0' and
ct_word_con(5) = '0' and
ct_word_con(6) = '0' and
ct_word_con(7) = '0' and
ct_word_con(8) = '0' and
ct_word_con(9) = '0' and
ct_word_con(10) = '0' and
ct_word_con(11) = '0' and
ct_word_con(12) = '0' and
ct_word_con(13) = '0' and
ct_word_con(14) = '0' and
ct_word_con(15) = '0' and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con('0') = 0 and
cst_digit_con('1') = 1 and
cst_digit_con('2') = 2 and
cst_digit_con('3') = 3 and
cst_digit_con('4') = 4 and
cst_digit_con('5') = 5 and
cst_digit_con('6') = 6 and
cst_digit_con('7') = 7 and
cst_digit_con('8') = 8 and
cst_digit_con('9') = 9 and
rt_date_con.day = 1 and
rt_date_con.month = Jan and
rt_date_con.year = 1989 and
rst_date_con.day = 1 and
rst_date_con.month = Apr and
rst_date_con.year = 2000 )
report "***PASSED TEST: /src/ch04/sc03/sb01/ss01/p001/s010101.vhd"
severity NOTE;
assert ( STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con(NUL) = 1 and
ut_chary_con(SOH) = 2 and
ut_chary_con(STX) = 3 and
ut_chary_con(ETX) = 9 and
ut_chary_con(EOT) = 8 and
ut_chary_con(ENQ) = 7 and
ct_word_con(0) = '0' and
ct_word_con(1) = '0' and
ct_word_con(2) = '0' and
ct_word_con(3) = '0' and
ct_word_con(4) = '0' and
ct_word_con(5) = '0' and
ct_word_con(6) = '0' and
ct_word_con(7) = '0' and
ct_word_con(8) = '0' and
ct_word_con(9) = '0' and
ct_word_con(10) = '0' and
ct_word_con(11) = '0' and
ct_word_con(12) = '0' and
ct_word_con(13) = '0' and
ct_word_con(14) = '0' and
ct_word_con(15) = '0' and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con('0') = 0 and
cst_digit_con('1') = 1 and
cst_digit_con('2') = 2 and
cst_digit_con('3') = 3 and
cst_digit_con('4') = 4 and
cst_digit_con('5') = 5 and
cst_digit_con('6') = 6 and
cst_digit_con('7') = 7 and
cst_digit_con('8') = 8 and
cst_digit_con('9') = 9 and
rt_date_con.day = 1 and
rt_date_con.month = Jan and
rt_date_con.year = 1989 and
rst_date_con.day = 1 and
rst_date_con.month = Apr and
rst_date_con.year = 2000 )
report "***FAILED TEST: c04s03b01x01p01n01i00031 - A constant declares a constant of the specified type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p01n01i00031arch;
| gpl-3.0 | afd96c6dd45868197665fbb2e21606a7 | 0.507791 | 3.316756 | false | false | false | false |
nickg/nvc | test/regress/bounds23.vhd | 1 | 1,046 | package pack is
type int_vector is array (natural range <>) of natural;
function spread_ints (x : integer) return int_vector;
end package;
package body pack is
function spread_ints (x : integer) return int_vector is
variable r : int_vector(1 to 5);
begin
for i in r'range loop
r(i) := x;
end loop;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( o : out integer := 0 );
end entity;
architecture test of sub is
begin
p1: process is
begin
o <= 1;
wait for 1 ns;
o <= 2;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity bounds23 is
end entity;
use work.pack.all;
architecture test of bounds23 is
signal x : int_vector(1 to 3);
begin
uut: entity work.sub
port map ( spread_ints(o) => x ); -- Error
end architecture;
| gpl-3.0 | 10e6cd19e5ee95079e597be42a2779d3 | 0.510516 | 4.11811 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1489.vhd | 4 | 1,792 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1489.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p05n01i01489ent IS
END c08s08b00x00p05n01i01489ent;
ARCHITECTURE c08s08b00x00p05n01i01489arch OF c08s08b00x00p05n01i01489ent IS
BEGIN
TESTING: PROCESS
type x is (Jan,Feb,Mar);
variable y:x;
BEGIN
case y is
when Jan => NULL;
when Feb => NULL;
when Mar => NULL;
when Jan => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p05n01i01489 - Each choice in a case statement may only be represented once"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p05n01i01489arch;
| gpl-2.0 | 5135630272a2aa70ffb737a713f16434 | 0.655134 | 3.725572 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug048/leftof2.vhdl | 2 | 539 | entity leftofrightof is
end entity;
architecture subclass_variable of leftofrightof is
begin
process
variable i: integer := 1;
begin
report "variable i = " & integer'image(i);
report "integer'leftof(i) = " & integer'image(integer'leftof(i));
wait;
end process;
process
variable j: integer := 1;
begin
report "variable j = " & integer'image(j);
report "integer'rightof(j) = " & integer'image(integer'rightof(j));
wait;
end process;
end architecture;
| gpl-2.0 | 3396d582bd7b1622db5010c1f9ce295b | 0.6141 | 3.822695 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/axi_utils_v2_0_2/axi_utils_v2_0_vh_rfs.vhd | 9 | 292,074 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ehpxA86vBUi/FmDVEerA6tSWWyhbNZEErHjkDvrA5hEcv101gIisNr6PDmR35dLLxDjY0abTbuBw
3ZAJ7IlKPg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
BomXbsOrdGVM0fvXbkkztfZLxSYQcIOi3a5d4FMKr+Ji4K1o4zTd+YQMcP1x8i7gJOg10iQ3HJoI
JaR4DWBUno2CbKecaGykQSgnzel1IkvHUIOHPFs3zfJT7i2J4YPduJ+RJx2f0+mn7QyTkJ/VmOh9
zxdggtPxxq8ZRKdSWXw=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
tAYuOM8O4SG4+r+qE2T10Lzy8Np5SsSlWE46xFj0h8PvgL8xnK/Dd9KA/loItwmYg64KEcplB9w6
PIuOkNDjErjCgMvMsFFu09Qvzkq+gNztFn4bC7UCjLnN+FREE4n2UVMe2OArhYBbWoVHTcA+O58P
jhzpcgR8qKXVcnoPRQI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
1pr5jCKpAd9n1GGHsSrOV8hgy4lh9hh5yTt/TRSvrmd60MLhHcF3heU0zPCSTlviMs8M7AjK/VMn
6FYi7jJCXaWAOUWbIeOjBdpvCiAy41m8k63F3u5mejeEprQtADPrWjbCql8XzeI9iijXofK+MkBx
OlDy3WhP6q8fmRYMo5QajiZ/a2krpb/u5DKamZN36krw9A9ioNvDkWj01YO4Jlsy8dU5l/Bx39nx
Gl4miFV3NjqRHKQ27Yvz57TViyRxDxptOdd1xr3Z9hyZUqDLMvRhqbFmN295R33Xbmgir/xsCGpQ
AapagS5pon04myJHnbGCR4TNdpcmM7qSTavLgA==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Tn6CuojiT6JxjXLKoFYPsk3fy5A3VvtXM1c92BjP+tci+s1aSSdcuKSkNEId0SjhuhjkRGTXUDEV
VN/L0SX6wjRyYVxR90qi/sr6bilB6QpN17Th2XDTDQyRgCU1yMH1HwyUhHSqZvQOD8M3kTbKJkOi
LgfVN+gI7vvBxmYjnM0I2TpDCAZNQIF8zLh212snNnBNK5xspJ6xzPdnTsn4OUb9xCJeuq92riSu
BZuM3MecfO3heIanidyHURs0hXGk4kvUpDozAwnwUn7Wb2+ApZ09UPFK8rVhVZ6v8O2iPz4ToHLj
fDvsoVPmmohgORjIAnL40ysoohWI4WFSDRNyjA==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gyRkut+R6ccSLKdfkdfEcGWIFIPtP/U++5UwS7oTxAh6ARBZ3jOmR/z25wJYNPAMRyRuEtUdi4MG
fuwc15IzNXMS/UBg+VKRo1Ma4gMy8e4A0oe5+LLsFAVtP8Is/I8bUbfEtdAfBNMkFPJa4Bgq0Rca
/sq7wPKrWDsgkg1JrmZtc7uFH815b769CRHmIU4P/HCp0QJGOvrKztzmBSQmE9ax3bd9d27Q8GKr
WHEPfTm9gyHPAjUSiLg5OU5lZcTnC5dXIMfj5Vm0XPCQCV8wrpILle9+QrLXhEyrdqufcgGwpCC0
ESHP9b8fc2Jd4wOojOjaC04TD+McDiCtR55TVA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214080)
`protect data_block
3pcvTVdnZtuD1iNCS8oQaOJStV6NP+WVpIP3bi4R3PLuJBSibvQPEhZUOzKyIHg3OyLcZv1pceIp
zJFpI+eWar4IFUxH/Vz9sWESwEfDb0jWvAD0HpkMc+2fsAbzkv/n5yonCA2El2Bf+3FkZRuRM4Gb
FvC6Fy9pUiaeuze+M/eG1l5sEZiKc2WK7PMYFgrrPmG0x/ShGbFgtUSkvp9JvNZF0Xw52WbAkkAg
Jy6O3Q5WL08zMADmYymHZZs9PlJ7Ss1YRHblLlEzAZSNpw5N5KWvY4RcCgt1rLRJ8qM6s7hgHT56
JPdKRhGKcP4MrvLy3T0otoK/EXs1J5n7uue/mRxZ12IjAZdjyEsswaVnW9B8zqkug5l0bE0NzCkz
6mCiVNgJamLYYeNBwIsTnPF/miEq04NaInb+M/NCuQYSB/Cxnjs8dcsCrkUxZjFWo0xSrsg591AO
sPq9UMZyvd7LKAidcjIN+UMLJykkhyFS9YwLCSHmLqcXEqwRfVOj81nztbNJmj6GLTW1NyosrXbQ
rM6270Dai65vK3AKp9mUPQuF7tPkvRz4OUT9lask0LIfQh6yquHxuugxh5X7niXT1OXin/cbKzKw
l8gw4sdzmsWPDhiqAtw/aA+9PX3t30UUnUlNUi0/V8fULYdbsRIv4S9a/D+jYKktPJvXxN4rR9au
6zyPWyolF/v8Mnn+etjQfIRvJ6UbqzBAoIgwPqEWLm6dI7UFOXsrQsCciwLi9UjJP0okn1XlLbMg
z/74eHrKg0bNITPjlm1Ok4Ru7Z0W/9slfDFJR67MGE1169L1uoYb9hupdD1MTEkltT4SH1puRjQy
WeKWxh4HgrQ13TMqAxN7MwAHWe85Vruimqz4BZRpg8yQjuLFaMJAbaZ8QSZ6F/dLqiMghHJFmt/d
zxUhlzgDoPTP4RbX+Kt3JNJOnGeBDyZiQK3DJjHEYjSB7PqrcXaU+QZK70IFF6SkojxI/ed9lijj
/o6+rjzq8DdWlAQMsPdWYX7lbadPFeizOY63Wjefv+ZN0v2zVtaqjKATbEPHGihYm8tobScp9KCS
E6rEGH6EGFJYEN+vvCykcMleVj9+GjugC06tWCNQBeoV7ak1t8GeW90k2fCloF9DpcGP3mgusGFw
tSvXd1j/9TNQM0P1BEFGDtoZ7dqi32WiEwBapZK8WcAm00aEekYFCEFWe7kNCj2lHq4RDlUXMxAz
37WQrU3mcsjGgnAz4MVT2wSuZVOGpK6N+HPa4m3BaIweFWv9wDtjxeZi97KWj6EC7exFCK/oLflc
nrPKANJVWYkEZdwstDNC+rvVJeW8+X0GY6uxtc4unSJqLUW6aPq7bpETt2s4FXRE4Dx3sKQ+UKQk
EyAG1r8Gm3m+P2qk3bJ5wYIOI7W81qF+qLttoOwmNtz5l/He0YD+c1XSODVjWewlMDchMkcVRFim
hO5mvjfiVx/OEPYMf3Rv3PfNmOmw7KGWYtbgy9mP8uQFLwPW5jDfDobJ3errm7tso/LiZhHY0bLq
PEnGkjIyTMk6V4yhYOD0sd1+vddW+pirvzkDzadg1GpSM+fvYUUBAOv4kLrc8Pj0OeAi4mUTay8i
bbOweISkLUbI8G0isE4cSpAgiPiwd4FKKVyx6uUMyUJyYMGDzM2ApN3iQ85E/AAuy/TaKGyKiREc
XYUoYbU9gYWyZQzFrrlvCnogkzXqqLZbwZk36iU2cq1WOWLfFNh5jb395KxIZeuR/PKaSPGgtei+
vjqD3is5xnTafhIAItkFZ9CcsprXEG1ZTkx0nPWbHRpfgYYNkjP3oIg3IoEWpSfwuqrhfuqlVjKE
749ivrKnuH+ZGCrLFCgpJTqAnyeU7v6HEVzDWoLpQ26tIkie3YwYoi7EXTKZo1dFQ+/oMiOskGXc
j0enY1OHpyTO2w/pGxMn711h2Aq/sCDsk2Qe+2cl2TdQhg7QH/Jc9wFYcUUsO+r7p15JMewZUFD3
qGbTqI6XGJp7wEqcURkOKjvL74STBunhGaJmKg1B8fh5niUaJ8ef0hNWS9GO3PQ/Ct5EJ7KlZMpD
93gnAPpTXV6T2zvcsiBGl50c7XeBrjzCth/nbI6NuLSQTVjpvORDHocOjPjFWMcyejvy9q/nLtYq
jwY8z1cWml3a+T768Moy2UYCN2N95tNOJek+WiKTzEQAfOGJRwtmhQeUUMI3ifSqUAREV5izN4MZ
Svz3GAb4ygoSbwxV1W+arTYt3w+JpweV1XYPifG3B9mfWtnBfXN7OhwjDGEiXc1YqSHae6tmEjv4
R6wm5AlqAyiP+ksmh2VVcFR4Qt73+kl6DUStKOWVo2Fspe8D1SNaIebekTGNlT0O+RgF2BoL/HaR
1ai17KBXxlxZtZy0ljA9q3s+fX1bvYpM5b5JJeft3+gi+ryFmq/DU6yLlZEGhDQtGwiPyVcXGqOB
xYwptkjVG3f2WQtW/w7TnrCknMyxIqH5f0iyWmk4RRkKFzZMVkbtzAxA0/oCU66Z085Lo0C8Dhm3
lAxSRqLyMXKb2ElBsVfEzfngLo94NZlZYfLfhNHIDJzsZHapBUfBG1S/a7emPh2Y4xY2Gfpyilvo
hh5zQt9Hl0EY6HuC4xoMYtGd8OKkLVjQucirriSKwY4cfKQ5NAqEUVbRzLr5Vn/LOAd1q/7uFcDX
UwocaxjtlFJos8ZBIeNh2cv6oJ7FvzkjPuPR1NJjpKhlgzVNC7J1JwG/f0WtCu0ycqMFBksnNLm6
odU6T5XgD3dWfY7a1PhYcOpEHgavvne9I83G2fBBsLTHLF63DjNDtYwsPlt6UTnQCItCWv38+Yd4
xBHW8vx1rH02365MRv2fXgr/089KSQ/FRveeNv5dJpraLX9jmQopB9rKZfrxKqd6IkI/JMRn0vxv
y/tOQPWV+Ili0d6oGe8ZROaHeO9PJqSOSDFeVHnqx/be1LgciommCTLm3acP6oEURMOCq+lnJl2i
jacPUvQsDxJ6WljtS7LpXnEgQkKn6RZKnkkad3ao8PUlKZ1xzfTwi9yyJW/ao5HCbp/w8NkUAkhr
eb/+ITtt8XdPx0mxd9kr2OrX44mcIFG3TEignOaGoFKKwi7V911ASoQYYyHy5TitkjVNL804RLw8
5LINEH/plyIqD6KNd9puA6BOoC4RfkIAsQFdRdHb0r1QPht2nhgV0mSHkhJcCSOmqopQO/IwpNRP
V8L5voZ5xjhmVgP6gy5O8MmNkWesVJM6lvmeUSKqggPZx2x8XQZq8pjy8YOcm4HXAvRC86i4VDlt
6tHn6JVv8VWM7cHHK9T8OEP8cP0zkrR5Ne8UzWFwIauY5IuxSOmJRjWlFJj7TSbm56TRcAqWlBWa
DHtMUzaqbJXLFVVOGcMmyf0FsMgxV3N3OKET90mROqXj0sTwlVz1tcD0K5ZACak+kyvk64fpJsSl
6N4c1lgEY7oe6QCE0Ijp+WKKNDvRf75uzH52De3XZ46KiHwWUtMpmnw5aRVAse7fQYshrfFPrG2i
tWfG/aajPtJzWWRc6gE5RXHfPzh4bWToHmLai/jxV4YP7F6n15faUnB5Ls4kuXe5owQ05A2ixRYZ
IY/Uvihl0zVEBKrBMAJSfaaXg5xviYxmqAr8XLqz77gU8AVAU4WbM0zQkKrWqruNp64i45axbB+4
2eT/BB6ZU3pTE4HxBTp9P+cbtPN5RQw7vkxLRmXfGgngTx07f7wb3fA4CoYDvnThiun8+y1sO6My
mIXbsscay0JvZljgF4Ltscxxw+ibxRzCBgdDjjZ1IVYkpK8NTK+aN+zrRpW5GvJuRzzaPKaSaL/s
kO+p1ojnDIEslGO0fLnQtlBDt7b9qPV0ipPYKS/qUUoT6SNsPLVf3favB85idp+WAXUM6WRfez+f
CLSXrA3LdA+1Dcy7oDWSzLDYBxcmsaRE6Gy6+/1gJ7Xj8kx0StP3XcX5RbQFEATPa1kjKtX9AJ8I
zq2J20zdyAK4Fsld4eTTqtV1Pt7tiUIKGjzbR/hps28qQ0lEXjDAJ7hYuNJX/I9N/zr2oojxLIlV
J0Aoq5DndXbTufrWC55s8MrumkEuwZVbBeTIu7nkRBDOyJTBXYj/mnPJ4vVQoduwzczJcBcmFCKU
rIdd3Jz7X3EJ/0eWU6HMN+uC6Xy9IkLprLMtTBiVN/18x6vWreLG6xhjz72ZRBaOX7x722U7+pn8
vw8lZc5ZfrZDOZOD372LuvcHqCZb61+lPyH81Sj53pdGt1LMqF9ugyzGR+N1WW+HL7uVJpS5j8zP
W0AD+KD3SxPH7Sw59AuQYEKG1xpGo8XsXse5pLr6uuETx5bJ/08Byp0iAs96KFIP2FmYdVOk17ID
OU4J+q79JhZ7QDMvK0iioeN/1I0hmLy5iDvTksRCQxA5JQk/ps9Oct1cgjpo82D9XD1qu7ChWK+H
fHfeG88DpoigPOl8qXvjlafJ5mdp3QRUhmklRifTkcWvR0k9pVK6j40OVPcOIocnkYaL5EwW22I4
hpkISBU/HT750HqLnXX8okIMrq1+mwMDxEtopJaWGtA/F3VOdIVriphxVgZhkIVCowoh078mCGH5
9PqS9t5VtfskSDUvYxr2xBs5ZuLHnYu2saTjNHga5YXzOOM0G+QYBNVVPhV+QGnAlq6e5MZV2KjH
B/iELs3LEblwNW7oBN/XuwT7z+4G8mWFwZRzlxCMJLEpn2F7m/J9ax6/EOX2ygA8VJuu7t4Djz2S
wDh/Agr+7Ncx2ZmYw4094EBERIPDeCDqq3PxvGxsBYwrqBU6tRn92pTZQquomApB2AJp9B8djKoO
8051Aj3lt5P1e9ISAe5uJyb0uq4qaBqMchvJGZCwnM9mN46qRGhdZq6hbdKtBwsM6MP346M+LHha
JpN7+wVI4jdefNcgj1BOOewpr4D9evdXCBLlPiYMBSu9vGdpklV77n9TeivZPjzFzlv6xp/bwHO8
Lpk12kj1E1cpv02oohhCXfPu7Gc3bBh3zr3luqJZcuuamDSxv0GHEIE0vKYg7P4lcUE2JDtxgX4+
DZpI4frU24CRtAWn85ojDHhvqb+/kcAvBbYwCOggZ4Z+D6nPlk4jJzpjY6HbuU0WXALbtPvg5Sll
6+U7R2Sf5OlwFiqGpq4w113Zbnmgry/KHC8Hn0lwBR9DK80zm3SZdFaKzmodU1fWxEEUyFEk2O3O
g/QIs0GgAAWPN/LJuOX+ps45MiLscQQCD0d8HHo9CYlauox2OOluf6l/E+WYTrG/EwlPUS9CIC+r
o7r0hU4rawhMRGxbgYyD8LJmieniRpzhsktlWTPl4TjOmn5LxWarqYV3vlNpB3qahC8+rVTHLIHh
B2LD4RwB17lyhPdXUCjVJbu4+Lk5ckaNfqyEsDJIeJ4S9EyLdPdRdkPw2yGqx0P7q06gcnVzC49k
/xyoOPp4a06O+njkrlbbj8t1BvdV+hxfPVKedK+zTbaTG6XZrVh1ZaZW3yr8M0ARMSTbEkCd6HNC
AX8KWLEvdDFk0WSxCL/ilc0XZqsIDqRc31dabpgY1VAQ9G3KpO50DGtDgYx+kzQJb+mc8tOHQQtp
anhf26nG00l9NKQVPrX7+86l+WT+CouwTfrcMe3iYC0OEBnNHYlH7bOZtA/LsQ/CMYX0RlwpmWze
3Q3MB2kgluOk5ZyNSpq1NUGIkFIy3rm5n9u8xLf5enaJKdAJ6W04CAt6nFj1KQAeYVeZNCqfKT8F
Ksehh6pBqA4wdwzMytYgmHSxT1iDM+3SdO/M3dviyD1H8QCdrtt1osiqEQUqGtKOq0+IYlvx0aw5
KcFGMZyqCwvzdTYsYFVvreeQF9J41GapX3Dh8o1UUUVVEIBeHtXeKRpiV08asGiAGR2+2T2eNvBb
VV5wd3ii9TRhFbuL0AQ6sbw/RJbTQl1NaPqb9Lp+Ij3v8KA9TI9o9QEOByFSVpTtqFjhLiDIr6Yz
ASe70BCGydPy5Iy1cYQX712NPlfBE5EnigOoFVOAqJZq6l5gHwm6e/mV3ArjdflYg8pEszMLHI+z
dCJyJYUF3YtPKwJKUeJc8ty+qhHTzaERO4Z1iqc3KOMRjgObvGOQj2pWdHHW0DipWpGNStFr6Dix
m9TPX4l4cmqLApUYnViQHpZ3b/WZeLHs+s5jhrCQy0w2OvHUe8vILQTubffu/kbjTO0ReXIayP9a
Hta6ZJI3OyJJPwp9WqaK3z+MVMudHpNqPPrRbKoxplI9HfRZ2w89jGeDWQ72MOsLSvKzt+GXUhef
Ut/dW92+eJeBILJl/0cjabYPxrol/e40P/6X5U2RI5d3w2LQcJz0qpYDEKzBrMu5cv7HYiy0qTg3
GzQCGaZPtWgW9mpExdWj7FzP2/lkOVoObRSUj9LhoogkM/jx66FoaonJW+e5dICyKey4QuPxGRfE
C/cmwO0p5oiHHgKVYlT+c7sS8ZdVAz4jSjmMWC9l6DG6rrqv/U1YwbEYoltfBdQs4c4z9SNKPoWF
jyFo/c3npOu9ZiTsjk2m4H36WjepDA/Fu+0vk9P2rBfjK6QmeCZMt0DdiAx6YECYDp3iRjn5RNCg
LhGlNXnnnPFVHefvsehQG+/O3uiKqZVSFPK6mpgg+idZvHo95K0vqyPEN+imNL3Nf+1CmLB2HHIp
dk4y9VgjsbFeTpvtxLGXfM0dAjAm0a5UyWl5dl/GnU9ShR/WPdw9M3hErhfurICYWXXF+ShN4oHM
JHQ/YIQVg6aDpdWrpygfAUXZPpPHvotGoVDulTmw1hrVXX0zNYAzN0U6NPtuXmY3r335/oGLV4+X
YX8i3nNWhwY3Ei8/JSFNnZEuVd2R4f7oyzn17BRkh36cDGlmzL3xmrp55vQtl0qgUo66t7izKCua
MRUJrUnrwD1hHzSNBtTJ3vOCKN0QOUX/FJt6fKLcZQk9fwpLbyk/RPpwfCV9PZSCKbzCq/RYTYDW
gMnTftnmhDwocpSZtup6Pjwqp4Pn+2JXC2tDOR37MQfWYbmky9LwYSdti0j0DaUmvu8Q6iSQXfhi
G0k1LuuJ8acwZLTt15to/ihYFgAgu2pI77xjpp3wGIEdkKF7ItrPKqx3wJLkuAcQ6kCKTbzxO8Ie
mSscps42eDxaIEUKwCHeCHK6sAvM+v/MivYdTWabq71lJBzZjxnC1m/ezaB5jCLgM05AdpmY6vys
Aw/denBKMkrIduDIirE+m0pHcFzDHaDyb68/G53wcXJsq5XLFjfJYVBOrqWr/o4Rl/nI+jfEC9+G
Rk6dtFG8p/2qHfGqE/40V0oyYrSnS4w0/q66pObBkmR8eXDKwSXQKD9md/uWmWDG5LPweFdqDJZX
HU4NtAnnVeDCt3ufkPFXRg5dQATH8MoURJlb8WgyuwCVKJhnkfKMfhFyWrOdyOJN1t6d3r1zxIhb
VKOntbVyVFFVLzMCmWbz0LO+tyDL5Jo2Ta4pbYxZv2kK++TIGboB5MdG51QM0LVIh6W8U3iGbm7i
RisA8QrTqI7wO48+EQATunkM8H2aivQiHT65aJF+oJcv+Mox9e1h0Gdn6d7Bu5e+YHLZ+aqiGqmC
qgimSKum/9BPTJrlE4JXA9nEcZSOGcSS+LyvBsr1hnp+AKCo8lIG+XL7jPoxgdPYkA6Wu76MTfsX
pSWKP2JEd26ZDeUaG3xRtBKFh1nXfEyjPfuLoqxJnX1wQwfQGeoGUdgPliTWaHS1gzGQYyB77SRS
TrioMKYYivMreREk6ETH94SG0xSfYwMri9LGIof+7TEEFcNRCm4lAvyJqJkUGi1cVZuqfdzkh2v/
jqZEa3TS4ozFTPn60gvG9TLAeSFzuBHbe4uh3tSPQ+1IMk5d8jT8Q0NsPfsKf8N9HqCeAS5retTK
mNS5nPbeADK26/+Vn593BYmV6plJA9P9GNaH+3xEGRkvVABEw3Wzk2dR7f/qM3ynWAWvETG1lzg4
oy118YBd6ZwCT00kFCOPTON+V0DsM9odzIOr0+b1ynwGIm5TBP92B/VPQrfl/Kiwr3wTlXAwf0nq
iw15ghScAbGKt6c6JbEBd6LjRCNmIEQczAySVU/vtPirQjQmG2m71h97zd/VpsN6+vQWVYmaO0Bf
pnVjDbd+B4A/DQVui16E9IILrjognhnQQUW2FUxk4RgKhk3jSXYj0fFXyODfGmcPU4whms0Z9NjQ
pp2kTN4DpySS/dqsparSMYE7Lw5vgOQ7Qv+lWsCFD+ijEOohWQvXT+J7wjYIC11y0ef82t594BGd
PW6jahdHVF9GDYj2sI7rEMXUabqXu6wjXm8sCvjPxq068WBzKJMsJswvhqKyadEdg+aV5u+UdJbg
a2xdkYkeoMmPgM1mYznATsSpCdXFDRdExIjeBDf3e6iKd+rOzu5sWwe+qoUr4dtLrzn6BsiDVBaZ
I8qt8N7X0Exy1Vm0sdO8Y92wYd20N0w2YDcJ41BUIBqPeDhYFfeMWd0MCgrhejjLL1AJfEkGIDH5
dxueOSZ1UjnxFgdc3A1mmB0SD+xTqNMSaSb0su4ZEYZFmk7ownVe3Frbq3QeTMcbpTqw3PwtxOOx
EwTbewV9aRgUQcJUrg1cXkc3QWNwcQ5z6PXF/5X5WxTtu9GzPW3zIcS1UhABvo/aDOGT5lb/OUIs
+PLaI9YqV9IPvXK2wYHrW73IILLxsQIaFbix1NZwcugCcBCaylg5rJMiMYyJAbRXGrMQqS5H0Czt
MTbSTFl+WOMIdS8lwPA33zUp1/pncoxaFrK4K/HLGh9TW/eUVqzyLycnGhJ+9c1BuAEDRS9XKlc2
LiNrf7C7P6g54mPkYyZhfGeqiYFGIH11iYhk1OOqMMP+k+xBs1hnbZSXcb592DyJJsAtVHDwNZa5
4kvhMRRZAKNNrGllP2iHSwwCyabZkplW3IBdoluP17P0x3BV6ULqYYiQh/ZRpogYeeqp5OBhjxAm
0eZCuYq3LmBoH6CL+Q43iQpHeNUr7lGZ7gAxGfSv9QlFpuMxjPZ0m4z96LhOxLasxzlrfiRHFpvv
5+n5gFl2KByXsndov33HqefFLE/X+VwDZqN7C6iaQVjF+ke8xhRIbq33oJK1tSVpE0I0abLm+xRI
5lVRunqC9ZtV0PON7MqrlAuNz+G6MaWbn7tF+3HIeYdUaJKXLidx9F1zL5/2jMRN8zAs7CX442aX
Qoidl2fKEbiTuInJ49rJysbC4CHYNcogt6TmUPztuhrrET3Mc/h+l6nNkjfXqp6S/FGerFvipK10
RG+0BOoHYA7wV78EWZKhU69SZJlP85jDR6lBes40Ctes+w7gYqQln8sDABEIZpqjoB9Jy5wMkF95
xrQ9I+ZLvYnIq4IVAftRND4jmmbRYuMMW0brXxrBy3/XTord3XhP9CKoJ7E1r/AqtMRQ96x4MJyd
ZbH6Y+s5yHagkQfT1vLIyYHm5i82vN3mX5b4iTkvVg9xeTIbFaQtpOHrq9pCUsppFRmE5CntV/nZ
yB7AywVLo1kp5pVQD3LrZpHS8Ww33rOcwaJLbMPJp30K6ep3VxunwZsTHQFW5/g1RXh9PFCMTinW
wIn8Eb++TEKNT/Dd/bEg8Uzt4pAroGCiP1iFLfMyBqDXS4XrbYDbCaGcb1WlRiLVJ8M30kaO8+Lv
9RhZreklatgbbHPIBFKy+kbtlXh1YaW/2BzJoVl3K3ImbRajyR4hqRHlbPWhbPsGqXhmi6WjZzI5
CHAVyqOCY+vb1/aSqZ2ONN74/pb6jkxXQCbXDVleULP227E02lX57sJOVuzggur0T/hUgyB765h1
+IstmS9pg5hqhHLuW2vvEpnvzyzNtgVbZjW4q5QARaW1WF7urJXo2NJ7MbzAXq8KJfx261RBCbTH
QG7QC7R47GWcNAzsde0SomixDaOCayrvj3S2XM1H0jeuSP15J9Cm10xyRga5gmUWE1u94e6frX6h
LGN/16RRBBWo6GHYryx0VlSzQTR6egvcGl2mwXW0QjrWREjX7XKjdxCW5C5Fpdf3EtcaFiiEiO0e
LfGmRKz3sSVHkLdbi7+tIgUs+mjSW6G90SbnJ0yifoav+5ZYgy1/YsdW+Cze4NqU8dE3ROBVfV8S
jfv8MHfXNfrg3/uS8DnaWkabM7xfHUYAt974aqm34co7GEZXTVYIURH2uZxVgWv9sJjhdFxrEUSv
gAc/6smKLWAGmkdHI+yjTQ02MFLO7+VmatqF+tf91+Y34WJK8D5vxVuX8JZC1QdJpJWo8tjGMYoX
VxqqXejQ+VNRqvilvqNsXDcfR8aLbD38fhomtyV//26fB7UPAoJFd2Bz6j4yzwFd9zwVoY/awMd7
lk9aXPYQXZTo/0OTn7Qu9v4UqRFR+48Mr2wvtN32hgxLrTzWXcC2i0tSMdawJazVFEL75dZ6U2fK
KaCo7ytwix6tbpG3q7d0qLSAnD9aeKPaoRPFN0mM/A/9c9P2TsOXjNrAOioJ+wLDe01mQvYTQWcu
8Om75z5y6uk+AcXifEZUpHeGlJ+ESEpGmzVVxmyU4PgvL4ABT9GmGOHx6MmhEhNU9y7Lugvi7baG
kEkqMbRESHH8YUpenlJUz6A1JaYIWscphYPrEUsh2G1VIOHt0iXeD6/51EbRe1pjf0sDGEhARHYs
R4u9urUnWLUVuzBV5af6YbzlBNa8iXiiuqILMfmeY7+kXR5cPlow4sx8dN7jeKPwa4wgRSjdGLZy
H7WL/q636AWleb2HV/+QNA2NvMj/1uYtrMzHiQBFUSdMCd7rIIawe/bQeUOZkS3yFjttLIxa2wj4
KDu3EYzJ66JYTHHeI4J+nEnIozT00z+CoB83QL1lky3lFVeDKAbLSW2qYRI3xjAEN6cT/4WOfzUd
pCrHaMJf0mFG81Fy6YRJB1N2MhARH23vsgcat7t9TZP3ui306fgKujrK3Z2DSEFYeA4rywsl9VPs
9XKSkgO5/N/ZyJ1NAPEx9PmIM/QLsrzDC68OHWj/+Kf6NaO9FuAmLEhdhL2drkCS4haYutN7RwHd
lJET9RFruaQuaGpKy3FJL/EhnIGru52x5hrmIptCsgLh16TlMTghLEIj8+VBdd4jHJ5Qi5ADlGpU
IEm23ehHxnVEv0YYhzqRG+1/VUbMEAvY0GA/i/wxmaXZxZp6GZWhVf4Js6V5JYP9abfBcAo3o8gR
JMK8UCoqZbL7dhefukZ7pXhvo78TvAYO4FoO0xpl5SHByymTWlGejXPh7W5NhogXC+Ym0yXZMWvf
SkV6dNJFDzjQmTY9TtUlxAvjB5PtSjSbqCpe9q6cfGSwnhxfD3nFOoLlx33mpOYhZzAI1koGm6mJ
FsiXuPd+FjsUlRd6Q382Xi6VW+eMeUMSgFVtXgDFNptSPqxDKtaR5EI3VsrXaqaZXdKVzCjjy0kN
oe7yL9uMN0LEt6VHx0kGmTJXvgYeAJQgnnvPo1GbIBaNlOLZIwBXJ9UOZS01ohEHZPdManFSHZ2x
S/HoFU4dS9j/mBG+BrF0uTyEHHphw5+RarJ7qtA6RmfnAo28UWDqXGdIJBWQACnFpzbius/SqaAN
fdhxP6ZszOv/NBl9nFosmQnkT78QIkpHzmZdsioMu10G8k4Rz7LxjL2ghPNyhg26MON0CsNikzQF
aB2U1Hw9ekUK1TiNhi/jY7ZBpNaRtaJZPyJY6R8g0BNiEytaiydy6b6oEWTS2R7XWxwOAhitnfz7
+EzHs3aOJ0di4uRTfjLn3kIIvwh0CRJiNJ/3PRmLWj+dgjfuGcosX7mCWsil2jQBs4V3bvEzfTq7
gOERdeaRyWgHNop3I1e7DGu9qH4oauOILd3P4ZRdfkn8mikkBlZngpFAJS/76BOzg1YwExJHzGoO
rJ9wGzTr1/iAm24S/AMS6kwOC8t3MFid5V7ZeCmArgqzV27VMYVXaJJ1HLO2j51TSZeVwKXv/d2A
Btoq9C5AIXWMAIoUbjGvBIDh6T0TzP+CnrzTPxV92sJPa6R8O3bIPOg21xcT84ZMlIFZEu9SzYcs
0VVct/hU8oG6N4sjt3aJC9IDMigNKJd2NqEG7jhsyYmQeuCKJrfT6+hGtaQVUNJrhl3zsqVrWi3R
i2jqRgm2ahBJxDuG/zmjNpMIJLNR0OmD/5VNdmCk2xNYC/y1+PPsalwePb9FonsEKEI+OAXNZNZb
2jOPp7I3aQnWlgz98tzyjG3f4ioeWBMQE3A6J3AAQH3zvI/1VXhgiZCKWnm89+6vCBU35R1c5VY1
KJOL5xsU2B2ULG4dQ3JvCEGU2DFNjcumUUpjC2Km7qodk9o7Or55pWdhMqsPI/ry9BaWUyzvGmqs
5yhoZTFxD46MDiOensJkVh3lZ5BYMbzCNlVMuYYzjnUDhneoPu5tFvUGJMvJ5JwmZorELyKgoQRM
+xzxADOU74L0U556CcfJpqLn9/8TA61pT+wfN5qLrEOf1hD/fgmKLkMUabpT7VtEG/mkHYQ8o8od
5o9Y07u/SjCt2/LP49Bjw9lPOvole3zZ6q+vOU+Vs7lBuGytgAE2NZrp1jkwUidsHTsvaOISNSp1
0c+78PuSfAL3MjH3pXqCFu3YOSGtfqn/MK63mxn/cnO5268Th1mG2WruyqaPX+pC+kLnVYIzqvoV
CfQDgQFZqgEYrjuUP3Pw9QtBVnRd44rkN2Yp4wsn/iIhrtxpvIQNJheEAQgiHkfu614oFkj5ri1U
zlKZ12WiafT+fNp201CJmlrqpHxbHxN4Sy0C5sU9d2IRivfaGg6vdx6HfCjMZq4wa4Som1CsrbWx
dpaXMrSDxOxS+iwcln7CKXq6heWGxr6Q29UNGGI8RKnmN0cYUiaDQzTWtr/fkw0sd3F+a6EktoP/
JM7OQ2XDQ6ofsxiWbNcKRbHk84q0vdH/4psa2s8qNDtIbRYdtPLYNEwH0/glSA8AgsdwxNCQ1foH
wDkzn8ama5GfOwDmf5lClXktZuVqmJ4RhYBeL4sqktTCfye9ukRMt82nJxcab4JdBWpcSAn9J6Jp
hl/Y7uXzQZpkX281xV5wGOMd/cRdA63kO3ecsNzYf64dhAvgT7iVMud4fSj42Rt948i2O5RSfM4g
y7tXPg9/ooxi36Ft9aijHxLAugts2uFLrW18nIBH7fNOgNO8dn6XfloP/cMogE0t8anaXM60yt2t
xVbQPUIwRyKIXDRBio18e0vEUlh9t+1F/IYIer8P5y++sFluydi3xiE8MBJCvG3Oea67MtyGsLzY
86KAUuaEBpwN4Bpd7zskTr8A/dgpeaSly80PWesHIkRwGGUaxt/iyqtTMl3SEw+rS49mG5ZkrBYR
WbdFH+0ynz7dLA85MdwWrDTdBkfbeUZ/er/GUGpEXXpBylpZMrERa1PLS3rAbfNjznHKcI1hc19n
vpz//OPTsPYy26yMgT/huhxevSZu7CgoQq0jLTmfn7bRFEfp7escjAxkB2+jmpdDbv7u5Ipi+FFg
LnuMpEhffaX+w4ah6wme1AQVFoL3T7KvpcVRxgo3EuC0wxo/Q0GFbyXWbG/tn1DCcKbS7lfMVFdS
OJRjMpF3azxV76wjDmU+fsWg8/ZrsDyLTeCtmbuH3u/Bvqir0i/BU0ewy/ovX6eeAbwHVmN2xVxx
WfqXdqCyJ0LLw/NUtCBz6ydMw8up4WL1e9W4en9D/zetmLyAtBfmwFCTG9MvluY8MRzeODkTlY9s
tKZ5Ho9Nd6zubHsFFI99xj8lvn4QmcltE/VvSu1s1DbYlwb4ml3/mdKHwQKRkqtbe/n+2HnN75Vo
KkF+AmwpJFKmA5bmxG+vylqBi+BeT7eaYY3qM3utUum5lFAC3IJJO8VToUuJTpiPn4WQrwjP8Nc6
MQHXW5+HoA4ploLLaO4qb7r3nkXmDb1llCNvW3lh/hXT7fxkHBVjcpe0kdx7LofZmoIOjbiljAM+
CpMa9DSeo8GWJ+xfzlulqN1ckSdAwj7XjCI1WcbkeB3haBzHbuiPbozLLJcGiD5xUTe8OzO2AkV/
js6tzf71hekt+tLZ6NMa0oOySGas3aHbTNARVjjrZXPjU1/d4T/bgC1VgdY+R1H53TX3qbpgeqIu
U30SrOPR9I/EoyH2G18RN+8vUqxAt7FRQYbjyZQW1gXlzjmsliPpwqS7p66G4r8JXqayqOETbzXK
HXEwICQ002rEBWH8XUiduXpO817Qwk2tW+hVygyMZ1ASjKXs+gVj3ZFnQLZXx4OuBP7FI+rgiodJ
qIANql4Aw/l4ey6AbLi/mUIzigWR5s6CmBegjAefvUZTTf78cykb2Dqd1efUK2Kn0iUYS2RUsgpU
F6HL3jZat087JyjoOlgW9nBA3EGEAgyNNFfEeClreAc2aDejOD1jzVzd3zfAE6p1B6Ss7jMXQw+R
A46pvMD1+HqA6u5onwmNZ+I01z5uzs6VZm3s3vrYmetr7Sl7QcA5Y0+D+wiy3r0lpZw9H5hDhfGI
BOJHXp5w+0hzSiPvrylTWVj50gYDEbJteMw046gwElLTOMln3T5oQf8k8yeWLyUJ8uqcmxvS3Rg5
QWEGXakSYKFwP246g6fhLL4ENCSlD3YQ/T06lfZc9/3QN0pFjIGNsgZt4TZet0MVPp8I4Sj5ZR5T
CfcjOMXz6wHhZ1KOplykyiu5piXN1djHlJS5iIMMke5dRUyMtMjS5aqtP1gS9cwvAwz51iF1Lks4
CqXbgeOOq5gmEKBfXgPF73WMrADDeDk6Dg2kXa+etWxtzveDOBfopn7QBX+HNAzgx3KBb+IzG2ag
IOLb8RNLQZUqOR4CGS8Q8WYs2WQmnQjKPopvpBrdnXnSW2x1i5nca1CMhTx3opGFJPHfP6yvZi/e
YJwa34Sq9hkqcwxlCI6TXaYQaKheNYXcoT1zRgHb3af8LQZM95QPG4Ksneiew3A/stLH3pZP3TsJ
H5/aQRMTZL16OjuU2RuT/R6MC+6OLNJSo7BATODT9EYNXwsUWmYvSIZa0IgfOhz2W0Myfbwn9hHq
3k2GFFAv1Fhys6cXXHjja3fvnMQG9UUxSHS8BXTOa4gfy+1RRzMrsVD0UcSS0pM6QHnppExmvl6Q
2ekaDN5+r3V/T90NH1SLhoeUHmupxPm1gwVTC2UZMqwI78q+If9IlfnHprLa7Vi5M094hhyw8dDO
C8T01qoPqS+0Ovn7S9jlrzx3PkY/qPo4kw5OTOookGbqZg6WCU720jjlgAPFY1nENiVFH0cP6diI
zWsws/mrcLLBJkpUHw3MHCy8aK40eFE9+mzdqvK5jLm1qblwmYEJNMlpFBewW89pBo04OxxMk8fj
9jb3Ql8I8pkNxwXcF6WhKP6AXSgG8aRL48bGsDIoA5+C/66hqnOO41hwGyY7IRqZTallQTt+cC3v
8V6RO+Y+DuKPaK2gj0cbS0uxQrX+ptSPejXi8PrdcKQamFj+xUEOCoZy+E8Ii7Sr7XdAr7qydXgj
w/m64hJ1qwecJ+MyT2mXyYRpQc0lx8dajdTzNgChlsVGiYbExvrb5Ggpm7tZMvtKKwlcSOc7zgIw
s6r8gbO5trH+WI7qnJ/tXqzjA+caCAI3/I3Vrj2TqfpdgMlC3sBT11a7II2+YN6xgl0gQetXddgN
sj0Cn9qOydi1lQ5wyECPdqjK89ilDXQ+qr8asPU5/QxuZoBFXZ6cytI7JZW8uaKQrG46uQ4njttP
Zcve9YhrbwZ7838PmL9KzVxQPF3e0FIDwqYqbC2LcCvcF7woXLBn9hf+cTqTiHLAKjjmv9xKJ0bV
MQimhbv8sGwBOCvIO2mw5mtK7j/cA6DqqPeFa1yIxPL9MulapIl4eIpOVE56td3HnMyRYEiFIubc
DLyx8OkYM1N6H0s2c7IvoP9/QHLYM4TXWfJzbEGr4bZFGO9XX8iGqqAN07J1OsPmr4GD8Qjp4rcA
9M2T7mwiEVNotWscnuRz6XrXYXGd38SnpOTajVsO0irP+p6Cm5i0nXmwVizM5/9z0mDq2JYF2wR0
+l3b7a/dIh1GkrSp66dS7J09D/dFbuVOEfwOyYQPJvDVwlqFWyECG3BtQ8oN0LVuB2kAYtICKV0G
4/R3O4RL9iAUxPKMna/kF0OERDVTNBs5CqbgCHOm0fcIKpXbX/w3XWE77TpLFvDEkX8t8YVurVo5
1cVNRL6imFxdjGx01j4Xbrhs1akPIVdQu+9rqVD5CLRElLDKuD6gBpUTfL1GeXh66Tp7A82qc/RN
PgavWhAIpBqo/0oEIhCYhgHnzXeSv+HpUNhr/+si3752flBc7dA+B32lktzHB2mhaPUmr/O/K6aT
jNalufls113jDYzDiyql4roK/KxFVDwCJqC1ohOxBNqJScS5gwtaeJqTpdzK0txQC3IoDsFipEV3
zDC5bL8hpzYBsodqdOUT8euJEy/aZVAuHTbZj8ASzf3aXvNLhy43H4NHh+AzjZU1r6nQDpKyP+EO
ctV3MCN6E66Z/rj+ICM2j+66Ibuh6LF98wV8N89BtaHll88lGdDDXG5O+txkC6oWTxeN3J228d4G
iaaXuiMffOHeJ5LuJ9p5KPpUYEMjIvghGkP6DwMxlqhT4Skw15kQSI3ufO8EjWfb5T/PNOPFPdtc
SGg79iMqqN5YKoDaAg55aCYP4wod45aT6BRVLyAbyJnKq2qDI1h32hlLvgbhiLOe1Y63lY1YL4Gs
rmzt+QcCczmnPlasvDoB9zXSOwReAqzivn44QxOhXSJknbc+wQfezbElA/8JRroVS6w2qS4VZqEp
Qwblh37BPyDzZ+apYRmUuKKHYnwY6DPrlxX69cs0CxZa/specEWPkr2VSueRrOMPlP+OFvdrADEJ
BE/HlRYxsjHiJ/gAvR3pOL3aJeS8ofL857i0H2uhB4rtQZw3mfX5kyIXsX9WS/vayPtqlZGRHVPr
7cp0Wurhg0iwYxGIRNxewgOB6w7bI+pF5HD/lDdPqkLgamnGvAZ8QuoAu6m5r0qRciEcuIhXZw42
6lNVoDtixLlqlYddz4/pM8+Bybl++YZpYrneTCDhkDFSULzgUJaK5XOxsp7iofL9lJjDJOCtO01W
6GRqHIH+mGaY4Nf4sLUdTsIJhKq/mgeMWmShggRLUcK7hH/HaYmwFFnp/lmRJKorhOFINU36vK2V
KILrPRtS30ouoPkb2r882ryjosA6WWJGvoZUbqeceHN+qLwYjqOrechplslxjmJ9XoEeJOlI2GGj
K5M7y3okaIg/Y8sABWamWghQ37vsjpIRJIUTySge+WMgC7CHxX15y+++IKZPuzKmK4Ypgn9PGndw
QtlZwZQGdesvI9gXb9WulKGePi33VTo+qHZepuWAJniqozFMHv6QMvha18sk4zMcm+/vYb/Kd8WM
f5D3vfzCPLGiShc/7KoAxH5Z1sbSauCLGR4JqcJixH63l848dqXAgn8ZgusyRg4cOWgm9PXDUUWo
RX2+62goAxEKzdmCU2pFnZqlfn954Sci927qtCRNp0oQiyyLJbUo3eRIpDjBn66p7HMC4mw1y9uV
z9FrGdufLF6MIeH2MQPtixUlMYW7ZE7LTYX9awsCtvR6evvnbZBoF9WMChfuihBGPbf40PsYB129
63Ztli7RcPiY8ZJ1ZS8d0uaCv0Rk8mL4nfTuUdFxU8GNDaK921CBsrLJNM3ltHMrwQpVmTzWJh5M
DVm9O9gJqImXa3cP6JndIfpowQ4T0UeTl6uJEmRDQh3rilwgycbRwU6kinpilk5ENIus+eVQDvKk
NzPJKqCrQMbQsg7hNolbq9XDtEtHoaliw0PptmPyB510ihJXTHz/VD2au9zsKl1uM2NpLE6p4zy/
eVUX5CDwd1gQMRsDmo9Y3tb10qGPRg6OfUFo/fAPQjnKA4bp9WblILY2aOszbmiivz+3DOJTASWW
ETXZ7tX3eWjr+opFtKMEfJw7WlGTiHunS01Vz7D+KzpMc11McJzWqpfCa6uBHezXYPbDnfcWvHGy
3O7xGvL/X4JV/cSW8fg6PZWBdOOuaNC18+SL/LJG5WdhFxxkko5o35ItxmWlKREGXbeotoDRj1RA
Ap1G6oHVVgzcW8SXe7VeJ8cNPs+dzXqmHNkNopgzJtbxha3+VXiMxBwgtKDbf7ajYpJQ+JZJOii+
g3jlTk5NBDjcAhlaK44ZNG67mOEkJ6PjPFFFBd3ZcIza9CH87bj3NCBaQKXgjJ7/OwzS7aDpQpY6
1sBRJwlBeqkSCxNC56XTTLSY3Bx/IoguXEq5i4dZjMI8JRqs2CqOOEmFeBgzZDp6L317efbUANwP
Pm7pjqLnF6+qx92ahwC2hSBa/CAJ95+20tdkviwHD8Ou0jQF6q0r33+7qTouGljKxy6dBWRGl6H0
s6xLNHsoFO7Fl+wrMXGekQYOfOWetMf7WYdhUFCtQhoNtBvKl0cB81EmP0Q7zneMRujRLeuFXwqB
RmZYHzGNHk3ZoRRh7ZeykoPyHf0rUBQbKPKUrO/0E3a268C//eoadrrz8ecxGqig/9TZJ1mSREQW
bQeRWbsA0c5f+X8eRUwSFWASNTSXOBKlWMiq38nOFYoPzaqc6r246kYvvgp6ecBLrikxCwlfMKEn
aZiR2DHb9t/Qve6UHoqVV/mkRJKjtj8AySZY4t+L9zBU6MMzLeABICfguY9qtPoLSVDDN0EUZ5EE
62QgkWMiTEbgInCNDcEMCCTdIcglz4bihJPS/LGLEHxAMy7KOW7E+gBXo/ljx2uHsJb5SAU6zUCY
EwD34dmZDwaxvtVnCb8JdaMLVohZtMe2t1g0uSRtMh9fjsEc2BRfnIdUnxKLATTBq4c53f8UKZVy
WJkee8RuptBBwMtThOKymcyz4pFBsjuO78Qz2Ezo/zRJoB7fnGpTvY5bF2C8qz8O2vM3mRB2piDD
EyzSUAya4aWsMHU2p9I4dSH+XcdVqSIy7O+FvLxfXZhzlsM4cLvAeDq3PStqqHX1ePFcwecleIZ+
PTCat0b4gEdgo8Mmn33KyVb2Bct/KfDBw4NRDRwJggVea2HcJZiihKdY+bxxPUQRKQoPbyr2CjFd
osSXjJjV6LqaYFPDo6T7QtGm140hu7amhEEQeeUem1m0valphnRIQJZSQMxoxN552cCwbF9c/lwf
2u25fUdvjI0FQswCl+fYWugJea3CE923blhiTQ9+tbbs4xEBrdJOlm0guqfCHhH0gfpadexIcNlN
ioWFdwRLsJZd4q9YnYseTtI0vC5GFphHwWsO7rS7cWyg1TWM8p1Vk3bYdIqTGaABL+zIJHkMPXct
YxQhTgvReeJy+hhvFW/gWaf3bwUZCg8CCzzE6P43nd9pLBgVUiTEkEe+4591E+s2zb/QPQQ+0Qvb
fK2RUXpE4kMs9lfHOvS3RceF3w3jdUYjnWAA8TiWrxsCZhr8LL1YIAYGU5reQNqK76kBQou7CNcK
RNpYg8IvshIS5vmWuQfv5OluK02qDsB7CXRqQsB0kY4DT/stQweGB7nCVxN7p3HLbTPIyIWMROVn
GTU2c0ZL7qtvwA6tPdezmyICFIBD5TJLHUlCTmNMB7EKZvfjmQYQEAyHyIS31W4qvqgVLuEFVq+2
PoEEUg4XXDUf+1w6n9BIHQ5ZHMTBvGo8V/tEUfaMhOJ4Tu5rCeRw6WyxYHazTALWex4SnQBEG3ph
XihLXEysVWd9Q4VIe7ktJUc8gfbsHpLiZZgvj1wNpbY+Scrf5GxAQukmSmQLS47PD+sXnGxfaEjt
DhISpA2+m6Sqgx67mEwvSKa8QWiuTLweIGlkUofvBNh//uKIuRtpLD6qlL7P6Q6opkwebg2MSEJE
tum6heHsawtgMey2Tp5besAFms7obJe7hbE/G4ONk6xNZBehPo4DGOoe5nbtC2ENgyp9gdZA4I5Y
jD/JvUtJe+QCz+fRZL3TPWxIv2DjAjeA1t9Wr4i8erP50knmuwu2yBBTqzFWGhIu+jVOOjUSBCKR
LRIbNKdx+6TZV7v8IUKEv0+yBfQWVnrmDhr+casvgbF9wQeLUjHytC3LZWsHTVsEkx36/ZbsjtTz
TeN3OT0nynD/u5oBgsVdBi6watusSrkN+ZXV2WMdKuvcvo+vOZvTVQnCdsZQcPH1H1GWGFoCimby
Z5lfjs4kKOacx4dxuA2b1ztddJfeCJTHZO5m6XLdtcZUOgq8SoqFF8bsCMjj2Z0nZxcp5ZEWhkQd
4idueTgfV+xvBzoc855vuV7yMeHpbRnasK5AJDu4k03MG/d0kDCjOOs0rRbfCJ24rDzfXgky3ih1
47pNw0hJp5uaLL9RDdjoEn0PX549OeMW81RC88HyUf0b4ijw36BuN2o5Spkabka9lm/3IkG0s5R4
dkFWrQY6yPb8tDAa2BFJAUZ8KIAZxU+qcUH9HDjcvpMZ7h9qjkF3N3O6LRCtrbd+TnpLkvpTO89J
0MwjtWlHzUjFcyOS7VHPbB72Wsp0lL/oHzBA3a48E9GsS/Ofp/5JhtVT3WkDUSUlAdfRvNT3zuuX
CGn2X3yyyvm4/BOcUromLgtMNlZ4uB+9j3u8HFuTdHQgM67epWk8SRbmdwLRYnMcOeM+eJmBD1By
ejlKfRr54Nm0VOSWFO5hKjhuXn/XspQ13MkQf9Bdkva7uYAMne2/TSYh/Xb/7l/truTmn6LkVhNr
PIoJe2PHx9+9rVOKVVLJdLP3DO5fmz3ydMJYIYMQACtOlYCZyTYGzuo80NIz9ltlMMa1s2ODiBzi
T1AHX5MVTy8hxpp58EofIEpc20ujqhPRJLIWKDG/u4SLqSLDBhaUe0smMBW6v+EJb46xAMRRPPH7
nJuCtuJcHn08kgKkWUWwJcBLjmyJcDn0bnBE5joZqp7utm7fknAwyR3JrZhKqDGfrMmnWlRa2BmE
BkW0bIZ1k/sNztlwv9PEuWcIaTS43JzpakxxPhyzl8Pen+bDFtwY0LHXEuGRb4HcVB+zGtUzc1jr
yHvJv5VbSV0lrCJD8n7edx7PjSWbHyzeAKmmQWfubXKuIfnpEklLeyFRhXls5leckw8+KezLYxcN
szTlqRb4IOTOPMPr4cqb3+vQ7pz0r+yu+wUXHedBADX1ifnsuqCvmzQ9wHlhfd39ERhbSPiy6ewM
raZ7eKGERsXlQbby3FiIBpTG773r1RGDZ2UGH1HNlvNCmien4b5li5U0x1S+0ZUmKNTcqltPhZ89
k7Mgdf7ybVEzJLsQD+MhU2PV2RSppLauNX7AuB4JwYlgrrObn/aT3wGvWnNU7ueH7uahEH1Bi9he
GpdAgpzgITvr/3OLPeM3EMJGtIoTT9FPo3hM4DV9fZjPpPpawewro06S+Z2oRoL9Xaqb5C8yta6h
ECDZbNSCzFSvoG6SrGEpJAmIU3JsEqRoc1vQPwJkP7CwvSjNYjU6qXvZd9MR+HT4NIPwjsnpLLUK
5iU4sSKEo6XDt89jTRYFAZbCeNfINK4Ym/AKim7VexlkAa1xZUG8gqYnzqXsmKyt79/SjjNlphAI
gH2s05bFFCKApDPKBTHVZenUQ0+CUelBkyg4ng3dGtaKAAbsyevB1Zgenrw9byeljq8cknU6PxOb
u5aGh9/FjJ+PTfORrdrcK0Q9BvD6nw95nisztJbcTpbh//XNA1uEGfYnn7+bD6YC7SFgRNMa5dTw
onAqENo7HFVPZMsIvDgv/NLa4L90tlUkjti06LF6eCyPVilU4cwyz5rf/Daxv6H6IMqxxXVMU6hd
CSoc/OyYsA4chfqfpDyGdDQbTO2C1MI3JJyCegraQ6C1It9au9t4kEJrslSnrGT3HrHnkBg27JMY
y7EWDUMu8WiSPcBWI0QXcEnMGUzUc8WM+qXiGUbdY63fLkC1CETRLqQ4LYa1q1nbSL3lkFDbSIV7
f4SybEq3qSYlzfKdoAvXTtD7h9OlquFxu3Yi9GJjl8nP+JOcA7DMRQFKGDso1UW3K8lyTvu8CKc8
p+9ZoNGSyzIpo+Ih7pyJIKe1TBu9NHqd1KB8UFQY3dHNZKE9gMLq4Fz/WOMPUbICdAvBRl5JPSkB
XfF7T4WDlOb6KzOuOoqOOD+gGgTTeYurEs6Ap2kcJbzJEBCpFtpNxKvNUljIdxYkf6qPXmldHqiX
gMX36/PENNSYve3LqzvUzr9MgsdZ7kZ/V1h7gJCllu1uIAVkb6v6hbAVPQ5cprWhcF+DD/16v0cj
/hIFB3fYkeU4PlH+1cUEC53hcaKrXN0ZLNxNrFNNDt/DuQ9gb4qHHTQ+1PycPLuQXslpl90xb93s
6xV6/3qeogbECakpSq98jin1cAKSrgxF92mBlLqqUeaHuG1c4yu1etZ6xKUkt8sQ0P+gDcVMah8E
78cNzjvNX+hHQvoecXuEhaNtX2Ygpm73JRJZnuVycdN882XIoBNE3d6dl1IXkXQvhSJKrILr0PBJ
i+CfQyRGL8H/o+O1uu6LZUnlsIknzoaape3ND9BCgZCm3xFaFFkBgAFyB+b31rZyQiUhwKWS36A3
WFRnO5Aa39KsxmlU9Yvz8rQSCo4BjocdBwJLGkT8XrVZKOlGnFHV6qvp7b9tMdVsoQzcZQfQPPOO
xiyQEdI33JVMuuCV1bR1VRFM5lXJYwfpFFRLucXdwba0Ih33Ij+VrDIzpSTaWWyM92hp+tBVV+Hz
D4mIliFTmA7lloJTBCeo5Dn7R0YuLyz04QTgNrsVsMXC0Bch+yHub/JmD3yGbPBf0ljv4Od8Stwr
uSU7rv9WDua8BIRpn+BpV1ec4NP6D2X6V6a+t8PHY13pOeu5DSus8lPEyl6C2IGzrVikdcs+5Ws9
TjEkfRU5HgS7pZMT7p1j13cFVwrqwzAZ1au6NSwTIYm6T8GlzXTNg80ElFSGD6IbqdbhzijtgBqV
g1vKvMFQ16qBAYIrMrrNiOyYopflWktIf2DU93z277ygwiw32qiYKIcMA381xkdOXEgFIWxRo5MB
wSmJrjujSteMC+96P7tWwHVpvy/KnoQU0c72+CvEnQgbzEOY4F8FG3wNn19oRjmE2pbpGOY8bfk5
fQmIN36uWqVb0mBT7okhqGp3LhHCaq8ngoLW1hVSmT9zNmzBIMbUKErK9cGxNxz1PjlaF4jR/cj6
Yeri26rWvk3qv7GSO/Od1RVMjH37cpRezK9suh36SJIDafDpn5lo6VmRFkgMGKPAsDw3aoL40kXp
ZVTfnoA76NheII3FFh7lclxRQ1Stv3TJXslnWNaWXgFUjP0Otjih/3/t3W7b60sGS0ekN9ypTnV1
HdvMCOi3fJOW/5AhZ2T8skZiFw2+TmL6a1EmvDc9fivAb/F/TDKAfuOYG1/7nXGmfWcyRSs+xz7H
wpr0n8tayPdICgqbPh3VkJRcgyZSpLnup0UlgpJJ3LA/RnSrxlq6XeNXUnqpMvnuvkbcCxApJBkb
qjOyUXrglXUV5P+YCaxNdB/viIGE8doswmE4gp87Cb4RAVzsPkqxy4Vh0HcSgRK3PUi6cUIf3kql
EKvizbaCkeKku3kBZXHKTtfddaUyj3ce7UYa4uLNpQob+USjA6cSquPSNbW71OadYkYjrxsK+lNl
VPZ32onboY8zXGIAaaErZCmzoqExY67555URllH4KHZDv0plRnj41wA8pZNNrBnxsbdDxeqH59RF
PIO9kRCFkDe92/jBoqR0TzTSKvastASuMpfjxX3mFd+HADO5l8ETFr/KhdGhG+QgQfrVTQAHfeHM
t9oOcdg+HY4fMs7k2pTCwc8R96xMKSt+hXpiThy6T8JVR0DxqyVO3hwaoWELpJgZuFrIyejqkDcO
zMIV6MxPSPjpz0V3476IurDt1EK/1tUonyh+46gW5Gdxbe8/f5b2WH4ztBK+IFUvNcGE3Tify/WJ
nkjyNc6WMu6NouVTK1WH1LN81Iuu5H5/5BOxtpZo2CBm5/77D1SqPO4Hyz6gcQKBfzi44akXLOX4
qr9X24FV/3cA6AZL7IucyYEPLzYVO3mxEqQmoQ/ajjMskDpP7qOH/8yQQz1/Np5A86MQNql25Mu6
k9CeMzOquNZMxmdj3YiL8oUjYi1Hrem+v2y3G9hjtjz821xYhfI/9nRiDJDfL5lGJWsscOdlm0dA
sfH3SscsP4JNK7NEzfgFAcVs0woCskSlrcfG8geUcDHr7ZTOJ8hXtKeiGl7zT5f3li9ri75s4XnH
Bn/gVfqw6eq5tlhpl4Di8KQ3XPYXrVX5pIauiJj07eDnS4BETa9s0CjuzxkqH8b0Ozyjx+q+7oKN
+XvqeVZEWJ2VPDc4aR2FsaZN+pT+Ud3mXpAzImkih6tGcEZTKjoJoPwm1zX7Nj7IrfZBS1nRn/Ol
q2mxkVyEs5ooTvhTT725QiV9A4xP6B3fXRYSUJAYrxPa8K9s9AySgChl6Mxh88FtWlbIb2huDAK6
vfwOivdzEaxCyO6mQ10pL9V1WvxLs3XAxwIxFt3wsegBglnu4B27F+6+3Bh+1mjefUEtiTc6OON9
UVlcs1fx80rSKo/8c8Yq/3fC7OjqPZZZXo0365EwaV7xW0jis4KC6m07tGIx6sNB3rbfoLM1RQ2s
LYW6iJwgDEw/WfFA0AQJ8Xy4YBPfXyFkCpovO+VS6GCpum2jtc3vJcQnvpi77KweWBCgKqO6Zq/Y
P46ulCU/aYtj9YTk6PbmdYFfKSY3/oS4K0S40eVuobxHF96t4uYTVNiAhyIxCuScLRMaf/hIXOEf
YJ2sHin4geGefHqi9O9o28AG2g6ImKLC18ZDZtLVK+8Rl6nW9GSM22nQ7ujeR8NczvEFluyJh8ii
jxY4s2+8A/lXznAb/Bf4sqpMJ3hWEi3KdSmKt+bmfTS7Hj6fAA2v2MFTkJeysYtNN4cDaobKqhOR
QE+RzGQudDy5mBhVJsuNEAUWO2G2krLzj+/N07TL6KPmHavNgKTdKHP/dOV6NbzOinX2I/BC7RHk
G1O95RfG70UvLTyqOH6rTxGkG3y7eI3ZzjLD0+hccurcisARHRKeLrJu7v3lUIl4USTOeJqmmxbN
MKb31ZdUlhVg3KM+hq6IjDrtrE5eqyNeKqdS5iU5stlJr8GdgcLZ2tBukbw3IY180UW24SJpSrzT
V3MfBrRe8eGJfDveA41A/K3FaR7DBep2jKwtT3e6JoSjTmY0SzmoPJAekUXxNHEAZymKqmFAPRde
umHr5hI3EecyB1hbjgQ13O1X31kCe8p7PDjWhS7X4L2BgxgBzfaF3rJnStI2dsyH04jppEK+673+
7kbKL31z5VlzMz9W+xn7qpafSam0r/DIBdLtPQG2ZlQ71jyEHO0F81JHAkem6MGEcWwvjuVihRXs
41X/VvWGqplsEB+21ae3i72VHLA1WeCVCr/KCggs79ohCC56TY5hwj9HIqONVc748QIjtn+OzVke
NK1TJR4N8jkkaUZYQKFQyBAUMFVGUE3YCo2kIxwoiCxpfrUoNSyvZhHrdFP5eLKvrMNlV+7rsu0r
X1CCjY55kwer2JShs4Rero0VPvnEyLYLrH6AKCfBv1DADj3pNxerg1laaxsCmb6HXUd+fxZDh4aB
ADBqyGD0bBf2XDW7mRltiPSCoXnbxJVxeLGChUqtN7b9r0GsTbc3Vdq03I5MsPZF4lX9KoBElD9J
e5cpJlNPcdoxtWVW9ETCrKA/bxHFFqx2AjnFiJIT+delc/Jq9Mvs6HgQ05uoPMioENcHq6zO7Qld
nLZtwVoZhsPvABvaDZdjarMEYwKsSxFW8B27SsKPzzo7SEK61b6A6XbYtGaeSjRE4Hv3YbJgGPfn
V/xMQpSNJvWlm0UXR+rSaBLjsBL2jozZV2T7til00dqsDS4WlfaLF/o/97+GFg0Fy4MQPKrJ/SPX
SDI8KOgKOi+/huaR73q05f4SOo5lPuQdwysDVJeQC3a265tdVgE1893w1jMZS4NwPAVBmkg7BJ3X
iPjUlvWW6HkCQykKww/sX20jgL0DRHjL7vjT3+WemwYAcSK2+z6W2i044ZAUHrqXG/OBzyNooGyC
LuhgwRlR6N5Rm0mKbZx72xfxmF9tddOUreNbHyiV9eTudvWy2N2dSTk+gCZ2JfyDIo/o1YKMQpu+
wtFJ03zMdO4q1wkkkvrPOac1gkH4Dm4vzz1AQqM6dNnwcbuWPMdcKdV56+Dn/qJ6JdCb2lsBzZGH
JEdlgRw85oZbmzN1/5ZVqXpTH2HnbO+lA19EbYJhRwhUEiTrDyQQ4RWi3E1aRz9aPytfiEoZAE/J
/0IDgCwHNpVmADsNzJ8glZdVbp5/DWH+J5gnY7jZ9GWuOp+X6GUdHkVm7KINYxpAYwnERv0/C2Eq
vGklknf151+2YyzceR5hGA4MDE+q+SKFK2xFyV5E86QxPIdUatyn96FN6J6MH76Wg3xgVHcHarrW
4yyPu1UQJWRPT8eiBqDdnOjMZg9eqZLohk9WsafM/ajH5cRZNGE6D1d2N3dATvSHhdLLx2m/l0nH
2rxTobG/Jc4D7Si40vKIqNOBnCOJ4Qt6DyC1wURsderelYRUvrXptp9uYVHpsPdYTLlCJYrYiJDY
w8f2RHqj/IloaqrP96ccKthFkSUSdkLT0E0y50S7+NPpnq+PtmirsYysLkNUrYeHUAwJU6IIcxwr
6SKivi9N4e4/fTmzIpxvaMMIQAk7/MWu74+BcWTCuH810UJWH4wHaWYE8yM9eLhtHjNEoAC8yvON
c4aQ70bEmbhya14vGa7ltjMYLwXBtk592v/cSHTsCQ1JUMN6OpyWplsnWllIox7FmfPcCJybyP0Q
kfnSKM6drdfpMFIsngbSMlJ+cGHkA85aEpn+nTuOrRN2k4dSSlPL3VU+hIBsG0Pf9/ISsVAxdzIc
vTNZzuQ/FLKmHY5VSVx9fXXbhO/cwXf6nfuU6JsN96Br5qcrw+eNsE9tepY+aEHIQWPBclbpKYoI
uq0crly9PI1p9QiNPIF+t5rutdD79G5n/YK5eKpQB8LlU4UNQSBG7SQBig8jDuO9Yictnq7lTVcD
B2EHcBGkzq1I8NIsE1eXKVwsnYS1qVp5tKgRd+we6El08rirq15D6yUu5ksRWpqjHZnoaMm2avPz
qtQLTovJqwPBTLIsOyq2q5SJ8A3BtA4kbm2S3es+eXqSFp5jHItUsdBWuKH+piuYHe96DhjMuXKm
T+PvDHoodhuxp51hUghDauUUNpO5hgjFLiv8cfJ8IXvcRw69mb1Eg6wrCqzYwQ8DcUoGlXTfl6W2
jiefWVyK8OV/36Vfks4xgEx+67rhr/Py6Fdqte3MerioWuj/iAUZPwicF0FfbtzbAtMyF636yBaY
DGTogfduPKFcRn5tEbL+cusdN3Kq9T8tfaZpDSaEN3tawGJ4Qa6UKQ3DCkDQhtmDIlOXMt6BfWwS
eNYIQN0t/asJ3BRL/O/OLPyzNfdln3ld3PLoxISJjwypqirZbfGzDKoBlyuguYmq/QPnW0nkS+ZA
ggWzcNXfkhRmqY4FlPtMrbGlGZS5CDE4EC9cpi5aybKO63rXVWyrPVLVxkNh3qAGEtpesnq4LCzs
0wDCT3D00G/87sBeTelXUhDkzPuFBfEfBSg++3L2nr9hNPPxhSJDB5W6eR3Gn4zBl2zpZKAMA/n5
3dyUs62QqUIX1zcSO3uDn7owzFWXCvcOEuFTKxxgHxCnY3eanUIqcDU/RHfy5ycxksSnqEElicqD
d26RLuc5GggV98cWEkAaARP7ChXkBrOVCoVRUiebzMcJ55VOq7mTopTU6yuTpcdm/MPp6qu4fw8o
LsJupwP3/GsDVCXRhibb9sNf1Jfj6iKkdlXqZkH5qxEku7uicIBgQNIWH5BKYvyvz2fTl7dLLJYV
YUoJO5iqh37ZuE+/AYsFiM1Hd9VerMzzeUOwtasgLM3z2L8ada2uTuF7YbEPCMminLDW+tgNzqHW
l4LuuQrN4oBmQoNsRdtmawBqqROr2xKLIdpKw344G969uPyVZmol3y4TMgUeABjguHu6/0GlKCw3
XK2xxjhyPiAnA6+iw/ii4d3ay7O6AUbO4anB2Hc1fIkGXRwXRrOayO0lnZA/tF9u2jjvhU//0yOL
R06dx2vqzMPPiSFLl6EesArWERC1PELmZkUKutc8+x0DnCi8pOwm+0i6dt3b9mfgYjpjClXa70Xv
xnLedxxf/TDhWllQDkqYH5eOqLF5+/EsIObznzyaJgrtwUTnzDLUeEcjvENaf6vE/YcoETsXbOle
4GQfd270xTWg/x6kYuFM6HJexUtvYws/sOKB6BzDwbN5yONY720fz2VFx+sqBfbJB8OXdkMk5lyV
pqI4LpA3b90zG3MlfxImgniGdUk+y182RI2XVG3Vo1C7r7QVfs4Yjr0B2iXhCtcW/0aGHQ8DbVQP
r8GkE+tmsri8e6uoI667Ev+7sE0r4vodThXMKJ1Jp/qCbhuq2Y3jZCOWHKJGW5WeJBxlSxeHSkZw
dNlqwfrVaT2gTpQ/t4Dxoh40AHdi0vY9AQiDbZ+6jEXikFvaEZ45cR9OpkFSPd7GHmEndzSFPwkV
hDs+cUB2nPLzKs6iqthZKf/croFostwxe86s6eVBjzunpp2WLWZeFHr03VKtBDa022Ef/GPE5R22
eym43pwz283Pyt4YGDHquJMdAUlhRk1xlxpjiez/ZH7Fx0RxrnHO1Q7/dWLT5LUrWZm5KeL1vbcc
KxASmraBLkXZFov8BpqHTOkSZFgU5dcp7AXAux/D/CxpBNn+hLaXC3VYM2hv7O7ou6p6BK50Si+v
e7TAR/klIdyP9+0tem3oWkBHuPTUQXrdOwyOKcT1tj+TJZrnVOSFWUaCZZnwgrNqN0fc1r71EQQb
NL2XukXh5V15YZkyzvfQr3V8/IhTcXERZEib5FRXukkvRcex063v7BKTkbBPYrWL74+0RjtYEaIh
ZOsTg5T8JHXYqVG8zRIvuJ5L8AXJ/Yp/lnm+zubax4LQUzJSd0mbypPlJLzebXC4tYDRijYXnQ91
dZH78OXsqB6F4zXMyT/gDZ9FWzATot7sfTTFh5fDB6hu0BKHI78fiSFnuJoVmYk4GkL1LNuycal6
YaY3KA91+rSABYCKLwZ8PFJnegdG5lO1WjVCOdBLaUHqT8rpjC/NZ9XiD6VoQOhR6SVyL7e5mkem
ey0fmwG/ftG49LpzQhHYStkvyz+ID9tFBtx/qFHP5pX+569gxYI4nffRQdh8DJec5MwcXH4FJhmM
sHlhT8BjZjXdaKVfp2fXjhdgWqzqPysPn9YEDRAdG6l78mgbK+MK/aPrinRropasYdl6njzauDYl
e7RLOlyKH1WRZmghMVhG5xryy2JHds6XeGh0ExGGvU+G5KlfY3EDiHIIRo2nZVbsFcE0J3V2KUy6
3XW58E1euWU9ZJJZVdc76JxEnBzwhMIBXepSw4indFItFWhB6oR1trK5oFz4tGZelgd62zAEd7DP
A7A09qOTYN1On2e0jspDEWsqpDxEA/eeXu6umBQDhWCvPuuGVLR10Hr3B0Ve2FWjIqZgWWHrDC+l
79nCSub14wf/tV+MdchZbhIjmhKsjCkJXS0KxOS9uD8cJJoGDXHlRrWHb1VmzuShVy/phy9dF3tt
eoTT/n1i1OzGXtvyffCHOg6SMYpYi70t3/AzMWE6dIoy9iB9bkCuUh5xxwG5G0khfOyXVgkyqJii
p10RQ4jwWwYuWAW2pbFLJEatLhFOV8+hdTmGw6B1pQFLJ3M1ZTrNUHJ1NTseToL9GS8b+qZC2kX8
7VD9PV/J+XoYbxuzFh90ABrx/eVIF1bTXaea8J2tLHE/bnhP++WgEaR4Q+v0BHS725PNGXAoAT6u
RuyN/UYGv3m6AyKlUr/L/NCg6sWpl52V7wo4X9ULbtQoqMzUum1luY8ZM9sPqs2jYeXXlqHNQk60
VtwHlYqQMo4jrR8glK0RsctICRfPdl5e/PJWuQtBfahcdJM0rVgknc33vo8MKkPJFjZyzB84Qwx8
m+W8dPWK8o8LTtyj5rCWIQ6/oE+lSrnj82KotOrfLaFi/TdzFZaLqDEYkc3IrhOP+OC4oi6cjcnK
8VPiuQt72MSYIrh/NtNUFDcH+VoQHaUXaFmFAjVHdbOd2UPEFwWC4g2cv8EoW+RuwJns7HQQ1hPp
IXZy8S+5jj7lKrcwlkxc2s/H49ozgpbihucs9v7abR+kVCL6Gc6INP/4Dczkn5BIpdQqF/QL+2UA
FJQ07BwoybyTV5v4Lcv1pO293sR/FQKnX0YS5BHlhLsLT7QFxxrbphg6dCqP1BFHvlC31c/m5+DR
KxXnP8VFZxz97OQUrog3r2KpLzJ5P4gplL8XEENSJs0hZEYWQuVTV21C5MVg3IBjMaB+dHhzPfw7
6wCGv6Ton6gQHU9LYHYfI803Kj74lU0FQ3RmweJi5WAR3lmw5nzJe8oBehzoO0z0yylMoj50tKl8
/WRTPPgtme49A4+LVsryletK11GFt+vZm/F12UAxIAv37B3/BQOhUJra8Qh4saqX2QfhTMr4dXaP
w3somhZenGJhqQ32H5wE3wFhZ+rn/xZggovaFmclXEywK5cko+jfS+wWIEPy3H3t7Y76RAFhCJyJ
UCK+z+wqdXqKwAncOPCBX/Su+p8Nr+HqTpuKsl49ssO4d/85n/Tct/ZGIbCuIHSPDZ9ekGaCRpq+
YC7fzVpbauN+tmUQW/Hb/Z3PbjGFYTF/o6tNlayw3bYhyCUeTRPGv8khQfOznAamrkCY3ejvlVNx
WxGpYGLGaOwin5RHnh6I6kC1u4+bLYXl5rLCPWiFveO66N2nAoNCzHpEpdjTUH79cB2uRdof8mw1
wE2hiKn/Zfx4Dwi81XB6H/6wiM6+pqTBPLmCnKNdIPA1z8HLNMeuzw6IPeycHQF3Q9JzVRLRmBFV
G390bCr8MtL14Xcvh8s8ikP3NVAeZo+eqxyrezoi6QAcpBikLV+b7cK4YnFaumWTTl+E0snDGdhO
jr3iPWqZa5lcXrJHgqnhNQkFxksoyBo2ztbWoi4UjneDhCjuwpmMCtOZ6jgkc1lEp63XhB7MQYiF
efQ4Xo1odfl6UDW7OB4A10nrNuVzyMFLKO9lhu13628RCcNkF7TTpfRzh2YQj6LCcraaLYmoDC3G
cS5QS8pTmuzaRS9g/G4A5ov2ZNxERr+UMKAHibEDtw7b7/Ce+GmbnWCZe5m8aax9D71Pz9+fXWJD
IuMfFRxaPAiEmLahqAa+Hm9TIIphsgtCLk9mHRGCIuw4a/549BhBBqui+S/mQq/EYg/QYk9NP4LA
rKKQfZQnMw5lWcdtcoqpe5pulDX1KS10CYbd+9Wsm0pqz4O2m7kxcDcmJb5hNNh9Cy9EV4XiPRiL
SRVp1qMMSb74suAI3YjnsSNAXEFvcBLYOOEUdwC2y2sWT6DTXljhQiyAI2GZJ7CYwSkMFsZsy7qt
WC0i7AMuMv7myxqhoD4jKP2MswH0q3BzzFRfUwHxb9AExSNToidCSXsrRYjjNleszI1itCtUKElp
FKPLXdOpzAvHxaf8RbID47HaZqmEXLCICBChOdvY5yPpjrFGNlX+JBNveWi++RNLkX7K0gP03yuY
hTmB2ITW7ICgExR8S+UIMQiPYdCmcbnrnKBs77NhnDv3vdsuS0Gul7VKDWV/Z9KLh+5OWO1sAp+M
y7e6QUi+42rHQrZyVcMxWkYw+q/4wCmFMrmWOgrRFP5AOkyoLtoQBsEQRosfIRirXigtGeEUcUiA
WfqMMtiWEOPw7VORBz1WvYMR3XiJLHrse+if6X5bW3dQhEST0kVfrcNsueyqAN4icS7S+BTJc4w5
bSUcGTMLttmAdWlhl/2/zaDOjSMG9yAirgo464g47Uy7ng4Z8bvqx8OsPFp5Kz7vlK3/T1jB/fmh
K0ZorfXAdr0K1OJ1O6MWatUG4Tx2KyRKk+5Wicy9U9CSLGAav5UjRpgcLIeU27WksXSR9gc+B5N8
lH2yEGNKzAO8bANSgynnJ5+wzTC8Vm45TxszYXwguPU7OG0xFsxg7egnGvtIQdTMD4MA4F6KWNhR
SYe1LMEmmW0NjU63XLZHkZGxs6jZlrXJa7FFh7IHW0cFNPkzDI/zAfOLLUjKyNQaZ6+0LYf5Apox
T1Njvd2q79WFHYY9Pqjw1eKNSlRG2/jJgZ7AIYxhMC9S03xG8ub+HdImQrHeCTSjS0wzw0G8obrr
PY265GEcVKc8UZJduxnrAHrovkvd9xtV5ag5iYScFI3ZmqSvU1ChXG2itMj8Usqt6ytGLfKfh0Qm
5jeY248FrBAmwxKSwzzJ/76zxnXHJdF2+A7g3Q+dKIbec4dtlsw0s3HNK7TWfTPRxB5iHfseRNCN
1HzHwb9NjHerNpr0qwzZtpkXa7v3qDdziWVGdBK4oo/fB69PfGsf+cEXdvZAS1/0hMgUFEuc/RTG
eScecFB/CKGdvXkO8rj9Krxt3jfm/s1790dF+lRYJhQQTEF2PTgzQVMqfhi2KMxXWX1wtIiplhN/
pPjrkOdrWTUVBNHrX8UidtueAyH83yvAasT3Vox/Sr5oMm9LS6EWlJUY4c3Czc08b6fVTew/2KdK
zSbVnoi+EgyPhCyL9oj3pvwMCIixFSBJncgJsENpBMp0B5pUlwK2oEkeaiojFq79SkotdITWUuBX
+Ilb2OaH3vZjjo1btc5dcWO6XA75b5ybgjaTO7dZjCPCbU/Kbvzl3kSUdkNHDDoE1dwDm8FKS5A+
NIXe3ERNKhRzgZwahmridSz1J5A8C6dYEUb52cbI/Id5Z1eDXpWXR1JMhcG2LzPY3BuMjcYl+G4C
4rpbpQzTPk9jU+fkIu8v6bncUrSVKwyfkqC5wm0b3JXjOdC8mim1cr+ufJXc0oVmXqxEKZE2oDHf
85LJQEkNWXoiHLAe5Vh4aIRRUUPTiby0kMBKrCxKWM+kFIJCIDljP4oUv7qMaxcqryuW/HUjM1GY
u9QI8n46M6JA16jMTS6Ur1z8EddsMcpAEE8w9zcjZ9MZwwrDVJdT74vE3IdA8g2SliGsPzPS5Rie
Rnl2Uq+cLb7um7LI4yIoYT46Q4apMd5ENQQQeuTCOtZCr9p6gyUJF56nI59u+T7miJx5dh1hN6ME
/8Am7w6F9F+PH5gVujep8ulr8CJxkt9uPGlyQemtPH+cmOlD9Euk75OdUjk9j9ffkqLSI3ZKURzg
oWVumncYelux7cC0hEMHkhbGtkdTXS1m3UpsxJtRiH+dN82gLc334zGlZIkZKEcuA8p3EefFv/B0
zuQuO/k7DEvQmovfy1j+U28pa9EVcuzN0Br+Adh4HlySD+1/BlL6xZps75vgx/lGT+A2cdAfsUsa
9m5ewxbNutB1CkEcanCl9DTAVY/cT5Lzn8mho1ZC/z3SMIMUsAKCsu85KOBMZPXc1SSN6Y0zSaTJ
zDu301/XFF7dyaUS2WdIfG4cu1I+I0noV+XnVQlgoQPzj0UH8q39CkvJkxbXBPd+2TWvylI4ER8o
BgrWa0AXrBzphzAEfO2Q6hUhAKegC282bsb7godtRBBjbOCat6aEgeMRaUV1Zl1TTyjF9jwpYZPA
9OmY075JV5HSZiZb1WDopK1xc+LYYxB9KFwqXhnEO2cB6AIYFe7jUD1lck6H6ZB11zlEoL6ffRKS
vDLBo+fBQxkrXe6mQ3aKlG/absaAXDdnqCmcdwL2ggEAy0SxvmnVF8C+oZMaoakKkpjboj6oXzls
wvqErrlrY5uEjKh64A93G0W1Vok4br/jdHERKd30wvXXdsTk+YQCwdm2mGiRtTEMA9w2p253730o
rZbwhUGbK88PtJJr+7nowJxGst1b73OkasLCO/a9u5NkYa/B8rZbIrzB2I+knVFdkaVPspbvHLRL
DRh16W/l1Wzckxri77drY+Mx6c3CVUew/G92HqGIHTcznDbnQM+2FEg5naGkg8Mspxs0ATADTuXY
uG2GQEJ/ZQOWJqatbbGzRuBlsbqPsp/Hltr8Fxvt405W+GVMRuPW/L83glnblJeP5uOtqula48XP
SGUVhdmeo5AgHIcih0CRRkCpwt6iiy+q1Ic/n9LM1ZFbg/fJyOKWpXHDxPAR75YEM+LAbJzGlZoe
q2AviUw6/DI5cMnMD6Wq9kR8h9QlWGigZ5EZxEptKaRZTbE2lzL93IKLIutvteS7+AkCSonhc7lI
5RTfGA3ybUHXMZGFyAj0P60JUHRXrhWoZEbLD/7y/RaZOdSYbaYOvg4h5yC31eoIQTmiGT7tc52v
vpribpLrh5mza5strwOeFBF1A2nLrCTPxNSwHIIfdoAfOydPuw5U13wslGTZFQvkK5VaboYgmAzW
ZAlUCPNA7vWQaqZSot+ALq371NsbTYz/FdQEr/HrFm//L4gQSHRmZ+aZXkcvQuKRkhe7J6ou0W2/
TZkKS4Hck6zLBYYs3WzC/WsSSDtClc1IAkxPAQp0e5iWvQoESTre4I13pHE8shH8i7KF1kR+/gEd
ORQByiKgwsQ8ZoW7baYc2TIw8ngcS+Gbu+YJ6uiwSYaRZ0ww3FDV0gpr+TOuwc1qdaHCmTXKU038
KFNuA0/feVAN0K6h1UD+R3kKATo/pm8SctKibRWPH4ge7Xck7xqEGlTdRSxHg/Gdc+8vIM+9JGsR
CleSbpZA8/7PyOXufhJHvyuuF8Ya5ZH5LVL640qHJfczZixTiufA9BbmhV1b7LLADPDsNgqE/RuI
Bls6fq+iE7YZsGvQY7Q2FUQRw3ja7Vy64jjBR9QYYytc4xi1zQm+02Kr6EKK9PkPEsZ5xvGXWvs7
sbJ28yLDRZio7YTXgATn3ZfCgs2Bfb/7SeoRzOJvYEepb+4ja00kS68e+bKk3oVDTxV4pui/wYV5
tV2wBcePGEWspfr7hSXJ/qTxZlOIDENeMX699OCEQHnh9ejJKP3MeSPnEWtW+XXJVk/Js8LRtfPv
MX41WPBOAT5mxMy1Ki4JmUn1TYMPHdY45Z4cCjcGBqBnyUBWfu1BjDm0jKTpgK7gvQcVoLqQ32GJ
btjkc4P/yqiWJ1yuSfFQl8RCjWD0jDEksA7xe66HBnLhitP+MxMAmkUdArlqHIqMVg1ietnJFKvr
aw+c79ehEXaHC1xj3yiClP/bMbEnkP/eNqO9s0qSHKYulyWTfaaByZIKGeHYi/vKdI4qwHUMq/7b
pKhHnTMX6oMuYL+rEZCZrCsgwFME123rf0+2LUgpGNLvJW6bE6FapgwVQMxygTTV1rVAVXt7djeZ
yKUYlKASgG00LUGMg+w6UpVxRWZgYtDtb6FrDpEVWNecoLb15LNxikl20IQCN1QTz84mvoqcz2uC
yRdpxFdix3rqVJMEZxIVCLN+W5hZ429pXOuAQtnpvrDmLAu00YsBgpyq2dQHWVy66eoO5d6IjEJt
QppLUpNWoGBQZY36BAn1vpebymBIpVF+t3F69jbT2FuFqcnvpZfVpqsETOps/cWbZ+GYMu8O9yOr
8uHTCDtluCoMsgznoabnxO4Kg/66q0I6P9BnMwQpdgnDcokATWnzi/WlA02p8JJ02rmDozanZFvW
8axic6sNNXpdlbuP+dEYTTOM9GSc9IddAHRaDwa07heWSkZ6ABlPfFw87C8uGlxxQ9PfTscOtQu0
zeUaFXA9kRXs0fY0LsWVnZA00dcEKo27hVV6nXkUECUUYxMMkVzHOXsGXaNMJCO8P5ROQiDk339t
zw37cfaxe9opOeSPFfluLThATD7uJ9ZKpVRCtlAnifqbHSGr3uNPZQyx4juAZrxsuDj2wXrzHJUC
BKVjoIMyIXXuixdb25AHRl3szJ4z7btYivGQvKKoKIdgwRslhY/JyBP3lwYP5Guh/LlBs1SK5w+m
LxJyDHIvYQ1UFnDozKtcTdRrF0srsCtxdZgfnw7FqC0LMDd5Q6+T+9bWIdo81vliAzTuNSouWNTH
6N/mOkzP/9MBzxG/1TyfgwdggORJsajyV+/0utCkUIDs7HQRg4B9yVbM801RykCxNzkwzWM8TeF1
wjwc8efE1NY0KCSVA6L4p+Smq5s8x6iCRqBdRtqqxwSB0M80NgHC00XuzQK+ONaxOnkMgG89+CiC
yiTHk90pXatrg2H+J7iomSC3mYECOa4qfYgdS+o2/SYzeg/1OUkmjE50HqubpDnT/xHvvZaO2VbJ
iRRJR68fEygNyGmcmjimz/QFpVWCcmUUdJM8OMRBfYU0CzhyAqJ+i2Jlwq/O12/I6pHw+IPwPr+L
gJ3KU1CFh6b2nv3M43k2depQwH87zZu/vvjmYPIAfQp956u724q+WjJG6xRfylCmkmcHahLmzmrW
y/itCP9kirxay5ZTW3qvAkDBIOlbEy3FtLRiKHqDIe9CfsuD3mJiap4ZHCt6uVYYOcJUF3DZysT4
2NvoEawcqvf2QNt1rvlXi+H1ccFDIpn+cCxYWVLXvmRhICSd4EuLcRPo+EF/Hd0Uuva2kTDitrvb
JlnbdM7zwv0CNFIbwBJfOm2tyML/woIhCfBWmnrjYc5nusshMtMBfzGuY2ek/rYKM6DOPcqWRfdq
7375IBUpnG5lDt18MsiokOaXznjad09+loONAzhdunmV+pwEqKn4ruBOyHO5aSw0jlqVBRDijzcM
xHJV5fjx/JDgnXO1gawloIux+vz9AYlZYgp9VUYTZAo4IApm3DApKqEMpnYpcfm2sfLYfEJs/ksH
XqnFWw62RHDx+7OafC3NQGGP6CH6m6xnrKwKOQQSiqTCVZuLN/ovMM6SEY5ITmOakQ5KrH4VHVye
i6IdJwvnL4p/bpMokaA7dSWyeTKjwKcX2UI6KfKMUvkWU/fGRB2cbp1CNy/YGB6ok81obpMmpMMA
KsLPGK8qMLU6hixCmzzR61mmz7HC+RP573+tNnbtT/ffx4F1N6/XLirC98ERODSdWfhchi2Egjaa
pLJNMQUUPj2DD6HvGtmlukWMsXwVloThpndylNdOZvH4m3RZJXfGqwGB5bl2/iAEnwsuaFWJc0wc
rEmvhimS50a62KsqpR5xqQFYcS2WlBt0+ZB2Jcw8srXMT3vCJ3WUIBKS8PqnxzgzL9ftpEPRzgsF
PHPgLhC9fT24T+6ei8dj8Wi8bdL7xorFjooXJutQUKkw8FaNhDsluBDmTzR2JNAKfQLCl73aESP2
ja7sQmhXtu8WqJGks4s1/Za+eJ78RGUtJsty0Mfpx27UqoZ6JtZ8J2evwNCM/XFyl6T46xq83eZb
eZiFQa703Tx6LLTGoSjUd8x0cBvBslScHfipTXMh6hJuAeasMEFJJC/xHc+PB+UhOSp8x9k6uzqI
3tu/uadCf8lKaxdI5UY/pg5b26NWVBYe/Z1CilXKo5goVNfdivck9mPpKsejnDjS16O+K9Ij5oPi
+EVmEiThbo6blbSAWu3kjqN/VSWqzJXGvfS+eF6LOF810X71SSvx2J64mb/fU5Bliu6AVv3YkP8+
W7s9VTPRRHUj1GG+Jl55yjRi53iy6bA1bElc3kwuBcj5fJp5bBOuMpoTFUmRQXFgv1AhanVu0crx
7ud+wrxM57nykbPIlnbXtCqUKLwiXl7qfKXlTywvyh/zsTJuAVOy0hA62NkbIBq9xW36rzqZa06M
nKetkLOAipTBOAgvhs7Rg/2T0iesnnP61vqIf3hSXM9MIVAJZqDXDrGMXehmgAzAu0eQq0WmDr9+
2NnLL+HtKIdw1jsF3svQ1onUXAzpkRry8U3g412TIpjNxUglzrOUooQuTSyU3J7ntBpn47FuuwUn
7XZRJ9HEQgIz00xHTlOrzMmQ82uogHLyblXXyNHWQPGO1XASzKi1FHY9TBBp6eUfOLZ/wrjsAkhu
NAbvjiYf3gHIHhiDXL9kb2QXsVX8/MegqkIp4cVof0pD0zx0K/Xs7frwGSMJ8gDUJraNk8yNWpeu
IVzAK6NkjvqodbzIn3oa/J6RFimR2auTMsSwRTrBMT65bq9L3wdGteDcAVVVOI69O+t4Dq3wZOxS
EuasygREzgS8/9EZLwa5PELZeGr/Aw80PVFQAX0J0KhgffBnle1SY1EbZae9Ij6HhLLB0CDwIBva
VqKSmzjbxesVs3iPk+2I5To4e4D2MIMxMbi6yT5XFQs3iR7J9JSQKTRNRk13fketB/WTvEdbRens
5Z0jp8ht6lm89nkvboI0mR/dGFouxPVLvr2wi/20mHQrRlf0d3KTTaWwBCIfLaDqG1EoBwbcwW08
nX6ZllKG+5JtGdAoVMsZreCSb+NEdzDncmQurLq6/Lp3ybIfsc6LjijDK97RCkmF2mrqIBTTIGAR
3RWVxmcntWfG02XvKpHBMFUZK0e1Y7fcHtVNKlAza7ag9a73sS55BWi5j9KxGGsNmYZgE7KFhWnn
iuf4QJ1Dt3DXBjO4zogiTVks6nNvcU6JrGlw93YXD4i5e5x5xcTpCyMZ7arSD1djqDDFsTUcRKVL
ZI4G+x08lqfrA6oPQRQAEsgsxC+607uY3NTu+yM0RQx7YSxW2uyZTw2w3KcTB5/lMhtIkSV2rL5X
NNOlBMxeWC4TK2d6hZkNra0v8wNG/t/huHANqMxtiHme6w0fqpzTGBaFczeqROL87PaSbFfWqSyq
1JpaSk3lcBr1blptDSbYcazi5tIeiwnT/IMQkVFUNV5Xki0gDAKhzvlhonQVIEnLohQPT+W0wnO7
NKClUUHeIOj2GSq0Danlo8PwzsOm+nTIjKmVRuUEtrMO89gFPPQTcFnlTcjhxMkK5hXZwAKYhnhO
UMGZkGQBGeJT2fU1W3SlFnZKXjiO+GHl5zBgXt+re8UXs4l7+ayCHAwikpvJ0kLhVwZ23g5taOi/
v1HrypnkgjMxCbJMnL7NyQ64/s18aWhRcH7MJ8f+F+H5v3CTH/EbUhteY60CbZb7migt1DqMm559
eGE/MVHPED7aLsiaC6pphAMCMo810V8l6v+PTYIKHtXCzvO5oKT9gWZWf5I1mz5iSx4apSrH7zCi
H5W4oxHZS+f/Mxkdg+n708J/xOFZ1LPdxJK7iz/fBgfEbsWXVXLkQ267ubkCDYBoH2ncoEryXsD+
LMzjnFXbs1FYQudyKO9CqBPtRpRRXKWFjTUrMSnKvHMpA+2rnfACHx6ACNDTBAZoy+oOW0LdvQA0
9I/OzR4IDTmnlFsgtqoJibFdQF9ocnquiMhufwp11pac8CHx0+drQdSdhl+ShP7KQUHRp3CNokZQ
hK3e53KNLNsPBar+lJ9+LN27sszotjuA8cfhh/xAPatAQCjnj0QgRK0A47tM2VMptgZWAkTSY7iD
PQabhwfPGZkUD3P84ptMN2C3IldPZ6knDIUD3ipf8X84smHQjWsMAY6fx+scsEvLdLE1fgsVZyRQ
W2Rm9/tQB1dFQDnIJbbcXqLX912VvTv42vhv/EH+cH/ijH1EO1l1Zb5gTer9gS9viEXejvPaZVze
+p8EM869rz19X5hNfB7UqFW3pTPHFf4LrdDaBCdDbGBjtO1d0z3svC6FvoSjamHI9WXEKxdPZd2c
bqno580c40CSWidDnpdQuiadsg94/232qlYEdVfUE5lRKP4kuqjThRZfw7bztJx+OyRSV59eoVtW
+7MpXttwVh3bjE+8DMxJd5F9FFNU1FBq0ubkFq9bqLEUH4PNrL0p26QuBQTerUOO/b6EAEmupZ9l
47RXaerT/1y2GTn4Ndtq9hls4X9BLEhJfA0fuvArrMQJGjjcsyJFpHFnKd7KWALVbozpM8MHoRGH
S5cbIqOFZaKGCcwjx2kXGZbmLbyhtuA2bYaIQpesE+TPzzmv98eVE85xooUDnRtWLd5oUyQFJjW3
ngBglig9TifNATNk9sHRNQxoLlDCjNKAhUPEPnEFcjlQ8tNVt6T+Xmydo0wBVjJQEim2y2AHwNs5
E3JErtfLrbWgzGOV3ZfWmx07JLJ5uK0Epelhh/Vzccr9fWE/3IKsX8xUHOMgBP6I02bhaNkEaOHi
p2YxDSZBO+6sdJRNs8jfoITiImtRxjVVd8jbvdbIFrE396NU9Cb8NxfMOOqtYKOqw9WeyXRWW1IH
MHk8HlwGm+RCN0Z8zqb8Ra9nj+fJtoKQH3XClErwUO8m+MwVhJITmpemUDY62zFE0nd74LBaIu0J
F/TaLVQv+Ea8yvlV757O7M+lAil3remyt79nN9au5e2YARbRkdKKGSNzxhsGhzGCbNuUC5QqtK8Q
ylYX21IAc2tCuHtORG5cvjEVpuY12qCoLTpngpthLY1/S8E4KFOfGs4x2K7x/JlQbBm81ou1/mIn
sQ9rIWZZGPc2GMD5P+NM7g9eMzTo4EB5O0guy/DFCRHwNziX7X6UZHlc8wujWKKPw3jKqhEHjbPN
mwl8yiumROe5Bq25xR9wP6X2lTyOS0YH+vDcl4dNfhOGwyTromEP/7X7KwdJIKgjpV0O+32ZFzbN
bUvJGrsY/zZN6I0fzNC+ax0PE8koaDXYEQZ5kQMxeQBrUx+sQioO8IrC6l0+qpXPak5joYF6Oeh+
cn6e66S4QLgOyO/aBYOTCtMN3GZXlKvi7PXqJzOcMaP/lXV7IyLigf22SLTMo9umeIoybhZduHsR
bbs59EhXLujD8IILqbsgg/KYD+6To76SFILFmcZHtwkjiXGT7aq1FC2cxbltUo21LvqX62Jpa++t
WW4j6gB9GlYr7x8Xp9zJRG9p7TcbSTmc8pMKCezPCaotQFGYftkgWk85L5h/njCAKePVUG9Xivkr
MAzqZfQ+D7kTIuJeTiXjCIWkESnPdnttK25vdRViv5HBgVRqQTxI6p3vT2VrEQkxxwVzHruqs2rC
HuYn/m31LfZjK1yT8miGusDQoLidQ+TOBTO8ssTRUCwiVJSwSUVDYH1d3kFv7BOngVbsG7h1JJfB
NrMc3si33X5y4sO9U6ImN0eSvwCceoBABDOWAmmAW1DSyBJmeLoxNFiU5BeTeLCnKMK1i1b5IyTg
5ow6NBnm6m8t7XTSlZJt0XFL4WtRrf6x8Jr4AqllE4by42IWmka5V9Py/NmWkqwn0xsWV9zmoqsC
PJw5Qn9Amv+vg2mTdsl4VdKUwkLB6Lxm9NXJkbuvaaZZylD5rZirWx0qKHRQTRbDyuFPpuwkq8cD
cA//wOCqrLAdK6GBEX+zp+gE/Vt1QwvG2n2kVip+BKjw2slE314NEKYwQ5xWnXBiY2Fc9MS6sjHP
aUQCCwuNrlardSUcc1c8BM39fp3dEmlTvmtMoo+kNyh9imH6mn90ncOq5Ilf3ldQHnoBLpP29lvo
3g7F7o8DIeijC9Ae1zTdxGrx+WzHr67baTVLPzzg5Ay5GxoZg7Z7odeTwnQHu0dHGesltKD9v3Bt
hx5bGoI5lN9LHVbAvn6hDrhMIvB8kLtOGhFQX60vBXPWZy3l53ixOJ2d7ZfrUvI/ItO1rAD6YQAF
DB/pjAxL107MblwIdkqI4pXgDc6w/WwsXjjgQt33eeqSJE57/I9hnB7cxe19MA1O44W4XgceArrh
697CUt9RAfmNoWNhVT92nB+qxzwFBaBMD15UjhwSPUllRLVv85/34KCASKS9XwA8pSnzmIsH9EwR
DKEcVfqPG1KYH0q9WFkjTwfCfLJX34JeSVLHILwlPHDdq/Myge0GGSzZR+CU4YWOsF5+Kbjro/LP
dE109BY1lDW2d6y3erie5BzfSVb00neODbbvW6YzHP/4E5UNZJT7GFqpH+8YZpooP+4HidgnwzhY
gk7EdxwPI5zZhhpUb9XbRid+jMosL9v7poNvYa4GlaF38RnJnw8VKBCk4z7b+zTL2duuRY95CE9i
IwZC/7vvWIHTH84DB0KeqQZW1hnQeVQgGl7JUv5UI0F3IXnTo3SFAj+Gvi8tzddhrLXnYlBIoHtt
nmskdIi8Ys7yu3CyYdTfwou+yWKmmiRJhkq2FiPaw1cooh1OPfjBfB23YIkWKYYhySBMuqJ3y4XI
SE8JqimQpjS9nDiTDIEVfyCk1paChd2IAQPuttaB/MkjeQ2uXrFsq+SPO/aL2dB4jiOqjtDsqipr
QrmDec0+316nxriCklCsE63jOFZqG4/pOkVB1lWyoEFeqpvyV5FEhXUPjrpW0TOI1sVrZIe0r2Z+
HCZgA+tJZpxPjz650lv7epRfSKV7Wf6/LUla3+dXl1krjFElUcXjiJ7Dg8vqRayNmcnnex9ZvBmW
k7B5RMKAkiPGa7SXf441AqGgcG7vROCZND95xfqIQCicUoVxTlJYt082cZmf2k3iwjSCJjlugHj3
MorQ4VKEdinZsgJX6u77QC+q9N2R4Yt12Qo/lL5ssHafoMU4VwtFMSXfYGkZ8ftGI99MXDLxozen
tZlETpujFow1BjgG7AbmQXz8mgdH+bgg0zXGc6RurBS/o6RDaG78q4kF7jGD7QWp6KQ2cCS4FrY1
2Jadts34TeVTuJMVwUpURhSlUtdr7OX/lTqSjbdpmP2FaCEPOuYJqkY0l3133vm5RX7xOXcEI++v
tCM10xYrkSeaW0dHeTPy7ZzCkWyM+MfITk+0jUlQuesMncVTcW9lnHBP9dtdimPOU04GTIt4GZ3g
REe9Q5qJscawWI7UYErRZ6eQIVI25LVdjFkH1iKoimtHC1PpWMdXGcAwLLvPp6y9PXVG61whC/gG
W1Kv0DAN2war8aBK9x/x2cPwPeWyzaGtLlIx2sfikNtDKOdVdxGQ7+tRlMWXAmOHaT0wDjmYd5ah
o76pQ9OSNB+ZHIHu9WJHrxmvADcnH+MvpG1ifk2qxIVKFIfdHmh3nWCjROwenL6jZA+FM6b3fNvJ
Tz1EWRyoCdKc6MkIbytwyc3cUVWHulRtmWBTxXPSS1njBEJ9ZTbjBd9qe2fdZ8Esokunll/OAuuH
7+L6jYwnvAR70WVa6tNz1bJuPBe/KiCFNXbWcjdIgGx0txivx3xNyUfCbtqDDWmMHl8n50ubrZKC
lpoYcWDGp7M6+kTTMi0ZWMBdyzZY+JEKu728MLCNNQ5yMP3Bn8TzeEtof028ssn+pyAXAGE0uzM+
IjNBsAQgM6/LSFxZlqwTJw3N/eW7Gl9XD3kof67Y89Ex/JMD/ITVI5wGP5503lcvtd/MXGEF1ga+
w/wXy6lzZq8s5N5+PSn0HkmVR7rXBl2qATqfEE70GgUDFzGmmCv4GDk10WDykmJe4jscXf6Ye5/S
mwm0NFCIsCWx1IwZc6yqPBgJfu9K9zFB3bSh1hGTFWg+W9IlHzF8oXkiiXyvWSGXlj+esogFETkP
o28JpupVa43qq+QzdT4ZY2sXMqqK2sEzxrVRViaikZ5ckzcth/zhMk5D/i2DX8KM3YfZVRKUqMqT
MBsCA95sIl2ctn9oe8x/OJlV5wSUnAnA6oM3KaoC0bZlVcmHBkfNt6lbvTkjohaohk/ii21irQM1
7Wonesz4cjAsMtsP0xP8XFv+ssMSsn78hNFS2hvkThOyAuMhoaWW0Xx+l5PXZQx3sH4fIlobjby7
lSF8VcDIUxjC2tzKtiT5i8ya0YXk5aIAwMKIMXrSIQo7li7v5lgCHcE9N2U8hFRnW9GjGlLURodO
AIhkB8zLIce9bNCpQRDR5Du+6+fz5L1a0kZU5DQiE29OMOi7N3Lb5ZeLpZ6JOO6fuG2phJV/G8rt
erg7PnFRfWewq5lloNRgjzaTL+cJ3m9gXYevP4j3rv7XGtMoT8Ys2k2Vv9mR2TnE5RjowjHKFs2k
tJoZz/ixbzHIkgSfPKzDX0t4WSSFEpkR0H6J2G+7d/dAiah+ENOyU3+LH3BfPCNGNon3EkXCO0dN
Ksl4dGk4Btzz6yvCA2IkygeJjeBzNEC/KP4sifL0PQ5GN/xCWkjYkfdp67sIvusZ1x7XhTMnjf2j
664lcm1T9uBopWL+xzzTm74/5VJIggLJAxzU1nIV/XI9aGXVcxBlWW691HZV5nLqFOalV77UdHzh
FE65+OIdLjH7BKotJTqAWiPhwhmCXDQmTuVabF/a3Utv8B63CA3iLywp6DrALPyTZcZEgIIYcx8y
QtO4FHztHOgpx8vyozaEYYSdrqKkQ2ExZoxq8jvdpqvz3MGoQR4CTpzF/om0D9FxE31pFJNTkcsv
+P316yDvfctTNFF/G6Xw5KE+sHzXwC74MM02B0B6D7nJx4Hbtp36jpkzJas8/uJ/FyPIdG6N1/6Z
WXq/F81GbjP+8vFy8953Hq7suVtmyq9Rc3khFBvUAtOB3cMH6gtwpcac3Qv9iCOyj6k8BvhIXlSf
2DnUhIDxOfCEqTrybjmBIDnJG9gg8n1iJUFl5SnBHswFwYS67kLhiWnY/kaPVoRO1JyaDgAiyVPN
evOH8qJotC4rYpVIm0ZhwWhno0oMEkMiGSqoMkKj8BqFC7z8gqd99rwuxv9fN4yKhJ3ke7kNGp3G
7s8mGKFmEsgU6lNIop/6KsROgqWfTPbfPwnqtUSvDxlGASxUWggYR8SwXwL2ANYm9ai5XnoMfOZU
PtTQnR6eoHdGigKVmsjOaWTCvKRh6TG7SNoUVpkoDhj1IGxiPJwX2LaOXWOIXm7BhVthaf+rCUa8
KsTmRVb9spEKMXYL+hJ0+CG+8gfAPgU0TTK/nP5wym2ajO3eCFcyJ11RWas7/uyErPMsGCZnrUei
aDtRorLkmJyyd1dS8yiQ1vCL/fmAwMUAB6Rro/j6g6LLaSkzPEPPEGnfPFDgxxtjLnVaiTAW+/M3
tHdpOCsRanen/Ylq3rHMSUW7TucdQ7aTx0X8jVCV+TbQzWnbUrqB2YADGIzxBYadGd+duLiWuuKh
8XVluHSmK/z9dOHCrVNTL1rMEjwOYDvHWIkghj+WtEZqoDmWVUSDYuWPI1V0wPwT4j2KmRWsKfhI
f5TzAU3ILzmz8gFCEu+mY8O69B9Jt2ex0ysi+G3NoV8OxpQoS8LZ4fJepXrgxxXh2qC2/yrqu92V
/FemjeSMrz0u7KipZ3YOSJG3DqxqBv3BxK9MUgccy9qXaLr1oc2fSqAEEmyoUJy92HEpJnGWnt0q
wl78IBqUqLfqU/HzGHtoHRJm+32eYt9shS5D4TYU3lWY69y38jd6x/EzGzRn7t0Lgg0mNpclIORU
khWT+6NkAmI8h3KyXGBEP3S37KWIWvJyuEz6N8vCLhy5GGitYxdnjL2aRRsnhCTubrYIxJSUjwkT
+aEV408C84dc89K+xlL+E7WtnOgZ27XbfX50O2yhwLPJJFhHlL0EqxuoEVWB6/gph5Cjkwce+Lys
c5892CyZ34ZWq+O9A+xfTgKjev6b+DfroSoHLJP84rbKeDE+RjTiH35pJ9BXfiny/Fa+ppNtBAMI
KF8tesQnHoQtHL7dVaZy10p4SFUZiMf8j6cFx1NXVELpYs6pK0PO1cKDAeQq3XN/ggXyz9/Sa0Ue
00CtB8n3Wn1F1zBwKIaNzP7d820gEUGqP8P+Uc7sGWSeUHQax3S1Qihls4N6TO+TqW58hTUJe53k
lxan01ZsDNwqG0TuPpVnoKHXvmNKi3dG1w4G9VAvtvuujIJb/ch5VBBFNX8OWmFD947GjOK8P0ut
23pHmr1vuCHzME1etGaNZntr/bbI7QdwXmoYwMpuhiz4MGwHWrS4gQO7iaRM8IF7IHyEngZ0Fzyg
RnLEfnncUTt3SdCSdZZ5lbn6Wdj8qRBEPlJDnHatAxCm3ekcZhW9Y4KDB/szPEtUNnreC/4TThzs
RCsRN/afrb25bHSZ4vO1raG7yFSo2Qy8tP3RXObFlhteKWQhoHf4jr7EhOZPINtYoW0Fp7/Dckrs
7OCyhD1muhmqIl7500E77rpFqiQf3So8Qk2D+2PfdC23u6A0RVAJtt2TNiBLZD8b6iai7EA1na54
iJOAu0m2LiqYt1TxlMbfoLHUQ8cWv9sjQAyb0nSMoeIF4SPnSYRIaiIBXIHUuaC8EbbvKEgAdi2r
lXxM/zc96J0rNxQQE8hxGqeauNm+TXHZkmJpK+ioGSKb8u5UqvLrjMDeq/+7iLNnSetNDrtgasRs
gRROV3zNIKmTJLiHl9zpHcZmq88fB8melJlKKEzaadOazRuqyragHZy5OK9XzxSWMnSzBEW+CzBe
HUwl/mY3XqgbvwjIRQMRt0xT0ifa2Vwaz+I3+MPD7gg9pVqmtjoduelV+DXVu/EA6SgFKlbNIO1P
xB3nRPCLdesxhyWOTQh7RyHG6rhKHyYwROBak9Vr64hqvxnCkzlml8yN3F2/u5wbQnO2jbFeh08t
OXBwYBczKFk66Bc1ouKTKcFovJqcwXEt8SX+SoswwCWQ0dVGA7qFiTzH0wgDZIm084XkiOFt7XqN
Y8/RDrNSTyQGelJr6SKZ0BQWI22d6Q+EoWLgUK4cBAcpMqYZeqVRV0Q9XPxhvOSVBEC7zFYYbVTv
vFGdk0kFLninfMc17DkazpNniq/bAq4BlzL8udeWGqytmm0u9P9PS89undjiUTsZbQDUy/cjBj8Z
08xv2xqYSe3r+PQfax9eUfhlQL1O4rY94QtdU0DgRMk/pssUUOMnJoY3PGwiKMp3E+/Nw9hkRnzD
11CmepEmZg4t9EPOAUiUJHqjJEc5hKzfv9LLwfDxuU5fiKW9AmopK9CTdBXcjXNHrqJfIlSLPSAU
Syp2JvRn7hU8OZycLWLKudEE3+Kp/D+piPiyOJiHDDNyHKLFKV4GLDyavw5hhGyS6hZm9LD8J6lo
fT1La8B53QxZvU+AWumzgn9dZGts62VQuhudE5allmMLQf5OYuPaeJDnviv98xcBOXY2moGAocxp
wdVmA/KcVYN8LOfLNZ5aRrsdsy/cfEaiXXqUqrZxlosnW5mHIy7jsitb8d9dZH0EhqX4+aNIuNkM
QYGrRuX2nqQfk88+imnym7WDOSdE2Rtmob2q4JwV9Q9vQ9lZWUKJKZQGzsY9i4D7DGP/8jZ9T7B+
AnZKBvdRK9YCip9TlJxWu3TAHyK2yx7dkWhXBd91wlb/ISv6tR/f+ngUrdZkBMDROOVAhBX9nFO/
CjaChQIfNZ+pOMmoLeFBIOyN0hznYELovuOgrZf4htYbfG6FfWpbhjCeTUP0eBfOEhrxDjwrx45B
UOvvhV0J6MvkKWjjfwuhSUEo5jsQQyLhamv70gRLIVgidmbHiAEaiOsApENdjYkWwf0I2ZfsjDkQ
QXoogjZ3qaeYXi2+G4bhv0Xn1p6JCeigvaKjcgpWvSjg9CU5Ri9BpF4MgIfHX7J3UBavipY2cUoe
C1JT40fvOLqE26o8q3bs2jXCS9dk5+UeYoh9B8+soLye8hr3W84nPnd0/FwA5slls6/3i5XYPLOs
FEqt3kVlYuTF3SIGkWuW19gSeG5Hn6zmRJOeKgVEQwmgo8N9NYod60fuGg3kvOc3b9wQjy/SpDYD
hK0OGU16M//DC2x7C3HnN/7mGU4uYqzhS+a03s1+t/kRO2fZ71JP3fMVy+5DRgiJ1fow6MGSHAa/
zRy1NPTcM27YiOrM3RNtdKzzmRDRJdCyckd63PJWyYcncWXPebn1nTVsapOThxYeBnXEBKVus2Re
bPl0+K0l8OxtYYq8oJ23xHRnV1svR2a38ufXGCdzJIZ3aWEr5Mbu/WFXgC51B+zQ3lR+9whWPb6p
DC6AJHMX0tdFHYp5jA1IhUhfECxLy35Rls0wLlbD6Jr+67betgkmM1RDu9oZam6/0cCtDXDXIOaC
bpdXb7dW6lsSsJ9HbfFmb0oLRWZd7FOLCEhnjGGuIobcjp+HaDnz9LplvHFUZlFIQ0uqS3/gOtqj
YC99FhDwgChBK/9DVtG856isF1wU3rGd8Day2lM093Nm4L+p7iazTmIYUf0wdohMe4/E8tk0jF/l
kYHq7edWb3JUSyelMkWDnpJB3+HqsYPuBrNO90ERM0ZgQ1Mhnl+lbtwATZ+jn4h7MvJ+qros14u7
5wxW2M3GehwUMTsAesnZY+eOqfzuo0HF49q0E6/Sq/5PcA8/Js1NyXp0+Qd2B1gpd0G7GFbXfXF1
+/S4/gm+M01lnNyuwP+WP26wHnS4PIzk9Z4tJfVH+xQczjMltjsvcoJksPQB7TUVCc0qLFAuUAsk
MPjlsRnygpn8sA21fSo2vgCwNjZyO30pxS6r2B5gzPWdK9jN2tifwwOXN9NAmTY6zuwb/ErwJ5d1
ZsDjxMItW1hYy99qG9eWKbrgRkaQOG4JTwI+KTBxClnhtUXNX8olAI3y/aFCGwsHQmZi65Bj3Si9
p++kIIxmQb0m9iRYYjx3re3ozfz2ved64g2VI+5C2lAHEOIDu+UYUgxMmf4t2zFRAZRXwOw1fRfD
pkuUlC8aghTisBn8IiPu2g+WssWAz8QDTrR380fqy9BMnrneLXR9RIHffasE948GA9S5a4xC6iOx
9ebKU/bNKctM633iafiLhTZdiags3f5zB2Ivn6oIo7Orj83IQHC+xERYEQHJ9PgxNUKa7dj/BPmB
pjFATFkbA/VPD4OUsmyYSnQAwehGYCF+yHGeoZk97CHgFwAkegXuPVper3Wy9xxbuAT9Hs025OY2
ZrfRGQtf1rQqKM7bD44+si5HgGYFOEJNCV+SF5g8j/Ttj4YBtL/WNz2vpvcF8rjDNunwBpNxQ0cS
KWNTeI1242Oq7puTXJAzwiBKW6JYGRyfFQcKKbB14cbk0ig6gblkpi9zdKRDH8jBAMVyjHObVu+p
XG8gZcBWIEKMcaNtyUGPXhwL6HtnUgvq3W9bB2KA1+GPQoVd/JdPoc7hikInYiYg2c1xIj68tA9R
U5I9howTv9GtEn3ZN3D9R4HSNzCEYAveLp9B2u0ew+xC3wrfJctRQDNhlZxsgfaozIZl3rOfNyQb
hXZ+Gonr8uy2QFFDr/CRSFBxoR72cv25sUt9NweM6y7dMiKTArDzFK3BivLBNosqV0pzHmx4aRRa
XmjOhDpwaF2QCP45Sue5UPvGotOGQfL6f/w4nGUapbALzFtwI99aSt/ClJ5f13bMZe3QsLWomxPV
+s7AkEXJK+4Knt2TlUV5nfUDCacDlS9AJinWZVBzpvUTqMSHSxcx/yZJ/OH5p06KmaCsXh9TROOJ
av33ZrU3o75hbQfe2SWvNubLyKAnaA0XRMjGm3iwM6SFbK9kO/tHgaJzLXD29a9ib4Qo7cF3Evbx
3z+Q7kNCo52INQ2JYuDIB5jr+FWTHebrgYHYoSB2MaFsUQCpD4iS7iIbth2LSLCjGYqonz8T9i12
zgmRNPbVsxJN3ue3OItlTm9ifixOcWK+ktf/lqu3KzWJgU8a1H0iqWsId+rDZ7L9jdrV5pFvoX4E
YLjJj4DehOcryEPyMuC5FVynnTuzzVx9qViNErcOWlDvuAVoOjuUbfGcVQ6TtwPLGcUUGjP54Hxd
c+PgU2ik9DqCGhP9fZit6/VHenma+aHQErUeSTcuKaM533e3pbMbP9CdRDJ/bQ8L8lodrb0fHRX+
olv+W/qsLMva7Yg/qLLCbY+DH6y6K5yZqppbRyHFcXnhQyE/6ZI7wYMx3ojnsag19247MsfWWsCV
Ij8zFlPmzMLUWp8nz32oL9xvwOoabPYc23o4Py9Y1GvTReTCRuFwJoEuXF9PbEoDhqVX9HQp70NF
ll/VUSN+IHXIb+/b38c+UMKmSRMTSoBuj8+Mxa8xmNMmblNSqHsCiCFW2gtgW8P8T1d3RAKn9faI
KrNWdxnCfNxVpf4MdKt7oTkQgJwRdmaIuA34rwtZW/4I4WFl1bm/hQuPn2zpHR6APF2OuK6j/Xcl
mZwgHStpkwRFn8dHcyo2shTWhLOyf/Ultho0j6zMleQfeTBQc4ACBFitcTHUFD1pJ1PQqWmFTcKh
U5OBGHDD/HmLSXp6QhKAtoJZzwZo+VdFAJmZGH7MKt51Yzs1/qvYnZvrHu74+O7597h5tyk+7Y0P
fKJ4LgJojKgOrj4xcEe6cqpHvO7cj4JUfV72O5lfU3QjRthv2Wp3XH5p2kxcN6M21AHlqJdNrz1E
8qg7L/EG5cBQMv9M8WBUpDNEZE8lpxV3zu3Er2rfA5rvsHrCP1GzYKTiSM8p9Z9p8IjFP4N3gWi1
ZRyKg6h2jbb5HmiOKK8VnAPl4vy+RJrY1p8C/6wO5YXYtP8KgJATPzXOAumWSq01NScG+Z6MVbMT
yGAPDIVIkJ0hl/5vTkHkOADWqgI9EU8sF82/Q8laKDMsGxr6vKuxEoz6QXvkwomJYa95nfod4Mvb
eoW9r6raqeYkCGckwPtkjo0WJKUb82Df+e6z63Z7l907ituiS5WrroGT90L6eDNq8hbcNGdkaiQQ
98VRvNycal/S7Pp6p/HiCqcFmZOSQPfHW8zeAWYrXzCBMwSMtH3Tp08oleMYY/K77/uJiRJQ9Acm
7iDA8mTrmHan+65DysLdcU0phFYV+EE1iyG8C4Ed4QLODE12dV0+8ml1HoxjU6ajCmrjcL1BABED
bv1h5Xhb/U5ZAaFRmmheiFzO3xkd9Lgt5eB2N8XR0V7EIBIz8OAuKvinrVkaD16NMuB2s6UdiAcO
6Vqqn/koUSLMtiDEBpcdQuN1wub1MEw9Ne0Y0dMe/pucTk5LfmnfuCMun2TtCw+O15wuVmNZGEoG
C+1OMGV9Re327dv5aevCnsARDG6jyrNiLagmshucotFxhadjrhKKSwQgcD62qPqrh22ztl+SVg2X
fYeonWxeAx/n6Q5DPVA3LqH93NWEpE4jJvUwPX/El98rQddSAkgWmjdJEDyOsy0bmDlODi6ct6LI
Dov7hS3oUZXq0F0FDCekjfSI92goTkovS7LhUEcw13lYcAMgFPkIpn0tTeceP4WyOu9NRuPx0fSv
RMgu73RSAfJVsj4/X35Qrxy/zSPLwstIqmA/kmq1iKFLWElaqVcT1sw0bEzBnMExiffrsH/X7myr
ogUoTksuYORSUAyQdOyvXljuqGRIaNLlJ4/y4uaG6yugDmHQe05DSxssjHd7w+zR5duA1VcLZLEn
MhYeAc92OLUHg3PIfhRs4ilOB4GD8Wgq0rwy6P3d3L5YUk8uZOD+RSQw8ofM2Xww25kjiByCVsFb
GD0UBEFG9Syb1mLxqMk9ia2rYfKvyKtyUKChkMG7QVeseRb09JDZKhp8dpuiLHSdE2EsFrl+/L1I
cV0kwx67mw6sZDwOLO11OLoxPTz8mLGf3MxxSdg7vehLV+mgvlKKvOkt9PWCG/qDVXqBkY7bwfV4
Qvn+Sz9Q/2U6yayPDpOeKAiwwriYjdZRXn3+UVvVHY6x6iWsEzee2P5mRaVRBTgDPCDNGxsFD7wa
D8sKp0UH1Yd7g++r/OsimWKuJxGsKQKvkPjVEQLHnS4GqjXEWYoJJB1mqD+XyfmiQBVc6OB0ruVD
12Kz86+oN57hKLZ9MsytJrm75V3avbRmyzzpWEWKK/DDhNd39IZ1eeICLk0vma2QQ7CRN7tsLT9R
IoH+6J/cj/oPIDnDlnhxPpFGBLHMkDiafN6dhIMgcYR59VwcLWrNpn0CT7c3VtJCyobR45wXrNzc
qGbsPR4vJ3Rrha+tA1LT+lMTy1OvXoIKf+S7AYAa7XN3LL07TbAZxhEqLyi4F8XuMYRb5QjIONhn
xi4/DZhvGUcHLV9IStMpg+go1SKIcV/gyl3R1JiZFHEC/Wr0lwFnC710sw5cYQAdnxAQ2K9ckTC7
TlM7QDMgC7J8b+ajbFJCDDW+K3JpyaACXA9uYfHD8ZnyaQmlJJXbnGDSczu0DddsYmulZNPKwzPQ
FjvoLL6j/VvEoaHSDJDg5QzZK/IU4bBhyhBeQc2kw+cRhB9FcKbSSZABqoun9QlNZlIlMFOraSY4
g/ZWH2tWKFKYQ4+VNHE3LH4uRnUJuepZtxfhYEyrGuK2gxlOoekwHmMjHPZfTSzCO0eKHXDVrY5f
sS3bKIihhHB5WvY6pZIqk2gS77bTNmfbOlCux3jHz8tKzf+q+l3+MFuRBP9Wv3aJr8F9Rkb47kOc
tIRBAENGh18bSFliFf8uVZEY0E21cQY67KJJyP75jL7o9Q08bpgnHIFFPZdiku1w5Yneejk3Im+a
UoNg5eHMt1RALLvN4tvHCKnKsOMQxwPM/Rqgw1KZXCN3/drU6xWOR4QBTyYOR66pX1qHDu/WLcHJ
21uTclFFsP+KQkWDrPuvLEVLVVow0rXGf0V7KtzQQAAomytzBfm/zhVeiuwT5VjnVrzbQuudskY9
pu0RIcD1PgkUhGlMfe3KFye5XqMkzWtfk25oDx2IsPASeD6zST4Of8gmm0RynY6fcNlwOe8yO9Bw
l4SisvGMM6vecEZ45Yj0u4bn7co7bSxeG/+58ESl//BwsvAU9XuDJVnrRpR6m54Oft/da3EwQovG
0vOHAjJX2TGCTdkqWMW0EzpMV5HtgOBJW80yBHwZuDMfvGI0WzYU0c9DcCzD+wYcj0qPpTqn+BSm
lO8OasfXDs5WpyeOAngC2KMmEUTweZTvTLoBXwz09ZCtp6IehBw8pXml26Q4JTSCiJNbGflhZt7S
KlJpOvfjASd+F27bd2h7I+0rdNObXqM8iDN0b6a35l1q7dp17R8duI6CPZc41ZXfoURFEHxc1cx2
3RJoTmXz6QldT2/+lUZZRvj/FRrFyv+GMpdDC0hOMrjNOnQmcz/khozqvjg7IlOphlj/kyj3ra8U
TZ7NDu0ZNJ+3HwewQ8Ml1SdcDhUyq6HBjOfdHlCZb3O4ncZyuoTSpsm/gacWFroK0imwrS5Qxilx
08j7lDe5mksLGOH+aQdNI2Y1uvljc7P83yIm/OYMTSe4FqOh02YQl9L2cJO+hW8ckc4rlqgY67qk
gm3TDAvao01PAcssz1YbjA62YWEQeu9M49DLFRZRmnOPV6FkFAVQD9DiiPzGqxwFSaYkYnZB3x+Z
F59wfG5/bRgIGxBYQnEepcdWDqU1G2rR3ERvnwZZWpduGBo73cOnGi1mnwnjjlaJDu2q1vf3+Dqr
QetRoBMglviL8M4d668RfmauZXJIEhnBWWPRkZdsVqbxS++ccN6LsOaWmemZobVLFOZlYajwYlEt
C6s66npq/TQXsDl60kPpz94/0UcOhBLWaNxM8m2CVMYDQuFr1jMMVe39HJHfeKMw0DwRU+5JaHxS
ixSokHC8r9J2Glq8ys++0JQLRjscxvJTrgPzJW9XzIA898aSA0JZjcopLCIMfkywgYjAeaz8lbeC
jWR/N/r+HIPILkXzUDzKQUrR3u0o1kkgR57iWeXCW681LnvhYSciBuwWFOFFNb0KE2Jyq9LAXu2R
U8SeSdizLP4xMfvKTqWeKwbPNiydtDHUu3UVPPtNjBP6pljXFCFpBKBqCvPBlcdGJDwFYvrm3A/R
fFdVTZnp/s8GWCfSynpMhCqC2VvtbqXSY54xhngzs9TkxZC0DusjGFBj1QGLALclrnBdyfXrNZw0
8RhTli1o7NLEDurXHfgDhNNyn7q06EAR1JJjS6/yj2xnfDdukikJvFE7hDgRMAf6c1v4nJSOMaAI
6iSNPqZrgFL0ryzzdliA2araSZ/7UwHo7wUezPJLRBipQEBTt/SsIjk9EvU7OR2FJYwm3zxo5jV9
yJl4xIDpf0nhWRhQ51xoKQLqREEye/UAy3vFPoWdnDNgrYPo6q+NwYAsdbzxM6gGHRJYB3YJVmoY
NCM7A+x3F9L6HD3Z9SejAlpri8MOqoLoX1xVDChzH7S+6nSOPf29TsB3hcZJ/bNLJcLZrvYR5ztf
NhZKgCARW/aMdnKW9VweT1JUKeEVnLfd/WcvYXqCV5tyJVaq9HUnMDadVn98ekI5tSVGOmqDv0c+
XvJ82sOYxnIhCHlN5zVMqswn1/4TBLaZryJ6x3M6ditoS3rIfZnZo/84Q3pq7KFBTIQtQ93Bm29j
E+4MMOmJxkYwU5Q5nopPSZQ4Te8QGATho5vHfiVIXklBOIg1EgMvua10cVYQzS5SifOgi1hpYPAy
bB2FTPlBtt1vv7wed+SndkIuxPuQPOvqeRqLeO00KiZzhDM+g4BDfxE9zWI9jTygR+kEKr+XIuRG
36x/0RqdEm7VYROxJoQ0Yx/tjhq6aT+SJgOu5nmMal6o1ApHWMjKGwzvwnKus4ZyYGHYD3zBrzI6
nDFjLNIqPK7FzZrAVnocJj9FxTy39MVRQHjXHQWx16PIvC2mp4vG0gEYMpm8vE8MiGbXHMAATWB6
ZYoZqgzVPmLMHBn3mbh69erosJTc1qIKZ4d93tQBnDLXRj4ar24JaNXtzNhA2yvG1stvvySvZflN
+pqM5z8H0KoqJNaYbZRzyAtq8Y9Fa4Dln7rC1jw1ebVs9JunHeRsOEJA+TTM6wGvze8470c/q1cc
cVePePeUZbkXZiGDUAA/8lkirTyuh7UcxHnyHsDGf8XLvmPtC2GA5MSrz1N6gIh2VdrG97JCH6nj
LK3qQC/uzdfMFcDeNNpQc57enq6Q4+pyDNzkvhzWpAKu2uKKVwt1Tc9ymVUtYc9Ei/H63q6STItY
4icHWp5xEINjpKbJMfiXaFzzqYmjZLomDGmrYinMHXMgL2kf/9/K/wUmycKoZY60oiBaqyTyj4Qj
fq0EIuNrl3cEeLIMh3D2+tH5FAkfGLr3jW5ZOEcfA7A6MUm0rYx1uCQCoJsi9ZeoQ9SU00zZd6Zp
OkpetyvyqgGXpDdxuZV48Mnd1ASSQH8RCKfzRCpd1Dg+hm9Ca/7FJpQ73aIyQ/HJaTqOhYzlvrm3
63RgaS9fNA/sdWmiW8utk91W8fjJ6RWVnC8Qmhfs1Srwk30p+ZAQaSa6T+iiwuENyLum53kvwXtV
r9t0Sz7iXGx7vMZvcrukjFwvqiWnZk285o3X5Laae1I9LVYGErm4pHvwtLYuWKrW60vfTwsieXUN
T4+ohKBvI6tIkD0SvecYsC4zjySw2wb0HjJ/R/OaA56j+c1RB051MqfO5SKXuADQlfHRmajQNYiR
Qh7ysy6T9QAf00i0+zWFN2Z5o8/CfcH9sxb87Di5D3uuPZWQzL/DgORQHip48H7ek1/sBS23G9eq
E6XPuyp23/ZTGMhprGY9j8ajOidoA2HQjSjytXxJVh3mto3BZSO7ItW6ygWJ+cWF2f7Gzi44iyQu
IFuaXmwnbBBHfkt5g92c+kcKQMZZv5TWwM37BYQ7QKGSAJTysSTqvw+9tFNNtqjJT24/N8DFCqAF
xrBMrjXGtgQfkj3c+KDzS8pp0TNAelBZoEPy+B4F1901XmbxmZxGxvVe4HQ5IX/IUnADmkZ//0ZA
rp1TlQPZyKmzZrjbkIEPBsm99bJt+FfiPHwCeIc9iqiHq7ogTJVzFP+UVkSVBYXxSIcRieD+DfQq
7sAS5GyYmcDBUKd7z5IM1o50FC53PaPmVsB21DI7Do/mdLq83NH/gM7+wpzNDmiJojgXiwnS5KCJ
D/TjG3If6s0RG9osWkhU64OIN2A5lmXj4T0cEJxKTkv80NljUO1XqbqmYHzPNGpKgYk/Zu4SlcDj
DiGXsNhT1OkNekdpLTKaM2dHZt/8mU+VAXSO0UMRNiwqUZHJ2RG5iAaxgT7GdXKGq0N8UkwM6OsC
CU8FZdtsTVbw354aPQVBnrbE2dklikikTCom9ihZmIfclEC8YEn4JtvewwaKv2CWhKNLwKkSUEtS
kKa3lN5/STLcFX0fZDOwd0sj4nA+sFAUk3ujjPBsbzZ+TuOOweQ4nMAkPcCyyxkpuGk8OWE/SCkC
vyjie7F30WfIc5eP2DMneiFjG5uw1o7/3GJMSJFSFq64M6R+EW7RKCQC6F1IFmsqKpY21kJm9tAz
tkddy+Tgj1gxOQ60anQKpd/C02wy4BxnZ9jsUfgtllF/YGbLBHxvw/eEa/CzZOEC/d0r2zn/Hy2Q
La4tsNpPmP7MySLHI271NisQhgVpHVkizn2AKSyYAQMr89bhi5r24dhzhaF8WDn9LiDM5gxGUAgL
Elz0xC2HvDajROTjePrTaNcFIuN1zm5fVhVYx0OxE2P/LI9+Us2QsaH6nxtK35GsFkh/AtD6yQno
mVtzl6Cw7tb/RlswNFrFw+MPF5efUOf3l1VWtX34J/886JePRFlSkoke6XxhfWVmpwb1exbXdE+Z
lO5CkHlilSMRFF+pDyuTfKks0QPETBdx8ex2eLtTu15QmRgUL93VNMYM6WmaUoeNIJt1d2Xx/8qE
CkkWVp+0GOeYbF7IVUhWi7bebZ52rmToQ3dzv+PfqGEmO4wXcom/qSwvLrNFDTM7LnSYyqQDDRBj
0XfoJNF5avlV4IX8xdpXcfnuvHQPvXOADAlm6eLqym7yQPcL91VEMvsALL9Utuhs0q4zEI4RH92b
UjLk0xg5WFdrhAzXqk5fUQEtiMcZftxc4QcMakmuM73SkOclwuZ3C8S5ImLejbXUtdvUREosOBFn
JCxeXyFjlX7nW5UcHTL3l8+z1ek898zhJtoKEGrtKduel3oubenaN1eu8DGhZltBwOCzHdyTJNkl
iLcd2V1AtlH4Z6CJRMnzItPep38x53ubPd2PS3p8ceyduxyA/tOvUsr/g39G99cE7sp32f/zA4FS
Kh+6BY1iN0uILeVu7Lg5mZ9fqbO4EY5iYiraET79M2shQjjXV4inMf6y5Zti7Fbu0iCu+SA2WAoo
zuuHDDAou4Ksx222PszNCwzdrFtFR+2eM8+EyQdzPlpCSqlVoMOuJINVj3H5feSdKzEDpwxK7S91
wQre+Tbq/yIsEfnOgiVn3glKYduio7dmT4aLboc9NbSQ0WUK/wfAPECZlJ3Au0iHp5RDSfmkvsax
Ko7wAJzEHdYVwxuK0Lu7/vdZb2Khk7LT8mzO15tGIg22AhAbuzE2ewc8+7QBKCGQEt5g+/3/nU+G
xIRc2ff+x193x7Fi3bnRxqZVM2DkZyP7NHzzqk+20m/34u36dmN7uZSDUNv8NP6eq+0vg9n7olCh
+xATSb/weOghQRcSHEiH0n5iiCQAPZt76N5Q8EIq5H8PfUbaXXjhlYB8CHYApYNkJcPaZSMfrAHh
egyyLIkmzSpHxBwkv4q6VnkAxepT1ZuhGhlW6U9SlxwmyaWqfERwqdVBY70xgTkDLup7NbIM6rlS
2dOg6NwHxPV/kMXlGWXzzmhFhNRdGysR6ta/Coj42OY4G5h/I2Az2pi1r+ft3nswQUiIFnfjlUi2
pWI4AP2MPN/vjAbI1SKJ60MJkD4TLVg9+3E+Qr5e7KT60R8j9q1AEVU0ALWMR21imk4Hvp1fFAlx
0admN/UHpm5v12x5xy6FAuBXsHEJKyErciuo57YoRr6dzTwWogT1w+gXCL0auzR1sZDWB4XLd+O/
gE9PsF6aG38FbgyfAr/EsM3hUqmQgzVuPJQY9tmDj5SOTTlgaXXRQO02bBLlzQTeKap7Vy1u9CHo
2EOg2XBVdZZcmvRH3UrlB4/Dn8P4WYnahrdD5r+v+0BD46CqCJRueCQ3XMHh4f1Eycql0SyT9Wmz
/3mcUm/NiOqKLLBCdZNFbcIpfaPsFGiOu2prH95IL6Srs5ytj0tRGrAGwRySun8QTN1Q2XMNzmfI
hx/x3vpxGBnaKlEeeoxrbUXqdXxtzpraMdHv7J2Vb55AYRmN5LSmunXIyK7XNhZc4wN1RCtAb9YA
KcnLf6dKY994jtzG7zMaTquOdiDOkttPf8opzy1jyGLkUmyOk2YiBta5tx3fAmz/06K48qVYl+QE
WXHPQtHsP/Fif5kT/YJs7pFGunLcWb1iO+cEB7Y2L909H2/dWaFSQsUIuFBg973L2JLD5ysHm7pj
oiUAi5nWtEoG34L1hpEi2/Kh98eeq1tvNlXdOQvRvETVXr4GPi8l9pZWYgmKxVg+AnFkofeyEzeK
iR6Y6WQjpTjDGLwGQHcGtXxgXRoOQZgJrW/rkXzNLupa2OiRAihhzeZhIFhwYYwgkJlxtyVwoe0N
S9vt5VzPsmXTpwEe1Eh0aqbPP7o5P4grANd68LXOUNQpfdeKfiHp+zn7SqroG+71znNkFoFZfCOj
QOWP7HD0rja1ShC2+w4NLVlaRXcSEDzpOtHSiVYNbJoWZ96zOqLv0uxrwVfSN8Jq2dK016Ya8phB
medureExdBRRi41frNY1O9XpW5CdQPKofCcAUADzJ/nqz3OUzRNegqVoSfN8u7wWQEIWSzm98/7D
gXiHJEQ6xvfE5Okwp+VzFQcS60QTX0k59tkBGCNg29tdRn0Zaj3u6HeUknq8M19ymMvOwLgs+XwY
utJ4scVPtzz6Nt65+TRNWOqr/oEb5uzDe1Cn70F9Vp9abRBAX7lFet39AoHyeMjGiU0ihZ0mv4Fq
5dc7se8b7Lz6nx8OX/kGrIam4AJRFf+pTHV5HDDG/Dm5o4Yj3c4GQzrqAOXnL3HwSaho3VtfUmKI
5rVxR7qiux7Wt9undD/3D0dg7eGMM5mrwerZCNuPo7tRikP0qYBuCDHJR0Jo4Nsehmg0/YWZXgKD
W5WYpQWjvF6BvBneajNwIFxkqatO+xEWpAKXFVlHeujLUa2YkjhCv6FiR0gdSvi9otiJe8yDaKIH
+Fzrp5CT67p2iTMQ+9u6hSmu17IUgKzBJRoKrYOcVeMkqrOk3rThdeL74txm412Yac8I4fpNsoV2
bbUM4A+sKFD5VSTD+JTw0pkYdRqIbYyjM+dz/Pojbh0HDlmbnT+ZAzYz/KfM8EE8YwP78J92HaqE
0u9eWS5WeyN9QMsplf10sX/I7TPdcfpZcTRKvatoVmmZA0tTmNZALp29d8121Q6b52b9YbBhXOss
e8RyIzpoADPhSLvIeSnh23FajDCKlUBmN2075AXGpVh989b52gEBVUpvjUMhCC5xNiIebt4Va1VR
BPGizowpsgWjdKcUPM4pA8AWq+mmumnd7iuFJBfJgF6U5ROpUqz7u+dU4S23K47RBnBKcNXVVA3C
snCd4wb3Iavq1ouZsgqoOsFwf0+T2y2WjnW6yee3Ozt4WDOlnUh7utvoPJFqajyosEyabttt21X+
In8ZTtNvEHD3uBkwEXfpnPbSEAM8gPpqwB3KpmvHLWxnmDMq8mwpRxifXT6N6DQNQIJxE+dADqzX
/FA1MEMqlzHYqvb6ulugp5Q86mAlxmkwMuyCh5Gp9H4ZP/VVflmnltMe9XeNjKrF5QgI3deliZEf
oNKo6Rhwm0oiu8pB2brN5T1vMVJsCgPbwPfWQVjAqxC7B9+hGW6okOfHIG4mlJDZ1H5waM+kiir6
RSg6txUAqW/nFg9V927aoI1N3SOVKlUCuOBQSbR5vfH1gsEFYpO4IBfhE17uQh3dzK6EGL4EIpWe
X9xErc9O5EDuAFnvbIMfHTJ8+AS3GRps1zw7A5z6SdQ1cVnwpsBxEb3Q8ryZAV0F3bI+CZ5V+WcR
ib34Dk4YY0woOOV4c57spFoa5dHxvRrYf1gb6IPQBxhaOkTESQJS2ft8rViMgPpD19pYeutIwqdI
R4ifZ/BM1L31YGzPi8HNNQEkXDZvp0lT7EPHHhCvlJW4hBl6k0uX1bTwJ+P2KDOZXFepkD2sDYXZ
5qBA5choQPm47CSEq67pXe/kevfhzQQmcy0ijPU2zSw+g6OSTQfDywHm7TfVvrM1inD8QFk9RYTL
Qgi7q4G+zjdwUKu5DyOjB266v1n5vT47ZOtXzyjV6T0CLKElt0C3FfiMZSCBZlwp+tiLAMiuTtgM
ae8J3q8HEGpmfmKcspX1sknGEMIExxhGbOdZFrmtyQczwanlZpjm3IjX7/bG8E/xFL5iuXRZ3nRE
CP67kRVw7E3j+vNfzZhwfmn0x+s4kBXoTyG27wIz+kSZULeDqkd26l/+7nFSSn0Cskdo2deAVZCx
JrgOqfwl7+4/g+uio5B90iR8FWlwbbNY8Vp5PRuIzMoowfUYoGCAbvgK4sR/KQUg5HXwqmeDFbaL
LgQQFwln4poNKizjH9k3xr5aKO3bmZ+puqSerPbiKA3udNiOIusvWbxCxRetlGvG87I9QYdsl29J
86fDjB5zDYISs0ELSz0NGCupRKmh91bmsRHf4vBQBF9YZ4zAyp0pcsl3NA2NUNcv9p+CGaXNX3LW
raX8EsTkjChCAyEbjeq0+KHUEZsJLr3cjcOXh+GM6fiN6PvKA42F420c3BPc1sdsWS01YxQoZufV
JjAvlACN4YKeI0CgmYgOKlAesw7p5v1Xim43MSqUsgiklLCi3jwDhVEqZ3lLRkEEFJf/1ssEj3Un
wb0e+aoLsM2bv9YFzfpHj6Tx0QPR58bkslYZ+cgO96SW64+dFtDBH0NwvkhZl2uqyC6bGuNS04iP
XVno2OeLG6bTOe4QDFJAEBfZHUTHTrZYvbOdDnvd+SX2RMGGykyuSzDKnJB79AGpmQ+nxSSr4R+v
cNMaDUjotnyGNb6ADPYAHq8xtAY1SUW1xlNT3LDZw0sCKs24fLFXejHaLBVSEvHqFQ4loaKg0bK9
MW/jb8dHLFJkMOpk294gcCAbp1m0nBQBRfsDoifBbWBJgljDmKAdscov+1eXWKx5U/GsE6B0cDUv
SMTyc0jG1hCPKrDzepcHyYAESFRjwKW7pekbX7JKtU8ujOBbe5U4FrsCHmgOai2MxKxbE0El+Cu6
QrhHIqi2QvsCvKZCB4Ug2fI5qFIF7N3P+dMOjZNPe3l17yHi7hdGh1t02nSOIYpsLTKqBAXi+raj
Boqg8TzdWT5uIu0vMW/tKMG2frKzqdU15aeYUBJDDHOJ0NAn+c21wKoesqvKPl8ff4s7SyfNPVpY
PZWovKSJ10oAFGyAnCZB5yk4I9kvCAjNLMmrAFVVH547DhxNEeFKvA8ZXHf9SVEZ2HoupjQXiHy5
ptYvUl1OK2QBPlFYXEQdh7kqQkhksWcM9by3PIMLjFlh9qSZQMDvXmXZ74IY6AGmbgb9OyX5d4ll
6VRTWj/X80OBs/grePNyqYH6DEPElTK8ngji9p5CSj8kbhfImVxlWDV40KwZxqYqHl6Wr/9y6g7P
6P+3InucE37KGeUThii6klbsaWpBFxeKjOCzCVcacvFvtDU7ENjJZCO9TO1FdTn3WvO3HfsLLIz0
ZlBDrim3FyGMWle7y3C8EtqvAxAi7e80vjlXLNLTtYAbz+EM+9cWdyWu8B3uh1f1X/PKU5Dmeeqz
qMkoYEBE6191h4Kt0R9S8i0/HvicgwBTnvfgGfAKKIwIaTwyUDQ82qmN8+SmjuxM5sU1klW0kBoV
ArMSt0iW/GNx+gF1LPu5iqcC8FB3zpop9vuEXISJk3LrVy2rby3DOzbWdVFfoM8u3wOW1BWHDaXh
ijYf5DsD8/kzmOckg6wqemEzl1+l8UK8Whelth4eQzr4ceQroZ7c8h3QxjPo/2PPnlyIRjG9aZ+K
45YAEYvt+Wa+ftwuRt6aVjCY4Ws1RHmmcp+XkuEleMM7trwRNMMD+feusaV8T9rcgeTVRrVIk/7I
riaTt/6XSbRWbHwMQcMO/CKaEOBiw1W+FVyYb10dqIKz+ByHB1OjsBAEBZ50k19tkqTdHg7GvbgV
v9hyzelm0RhyxcIxg5+DPKXiI7XPA4y90OBRNTJWzgbhCuNJ/qoYfLEmIKQAz//aqTiIn4eNeobD
4Ywkl64SUnGn5tZFUXlGmELq8xVhcVNK2N+eeofq9rhHKxDHe0H3yEasecZkTwPPUyfJuo9H+UDK
rwQ+JN6DwwpsopztE2Hr9jlbgJRE4ZTijKeOBtFbgQV91zv8dF275xfEgA2ui99hnWjTqbVmoRGd
HwP3p0MUWGx1C+bV9u/trQ3aBzYRPND52LWJxvQdTijOd1/F8rLcC1dYB5iINX5qQJpAr9HymSfa
3NKiq85jgq5QlaBW4yudjeJI3sRojxevuEsUsJ3j0i+/6Nbv7tPG4DoF+EY0PcIAJbjEYKGVNN8f
ilGm8a68AdfDm8etbkCRF0myxG1w9n6Q4fjackniK2QiosQvjmmo4KstcAg6Pv2QzX7lIr6xV3/e
cyVbPeG07onz4tIRHKD+3x9qbiIwniN7nv2cOW1voUUxztUgjc078H9VLiw5ZOsQPVNyEg0WCxuf
A2c3E5AH+L7+NrmVzrg7XWYxteiuZZ5Xh7KhCx/tPEc65OSAeaHLj710QA8hdV32n4/SqUhhJNyX
dZFC5SNWgZ+7c30V3dJiNPkG8vD40GsR4nPbenvn2A4pHjTFEzwKtCjleLC3DPS7JD5Gv3983reR
t2hHlCSLRptKM/iHv5G147ZHoTs6KQMpeFDZgMPvLPLsmAZxPsImDoudT47qtOu/5gPMsgo10OHq
KJ46pbyxYgO/ZAamz0qJk06fw6DB9C6EKV8JrX8kQ1bpIFnLPN21W/aSKy/C1SkOzmy+514paeh8
BGcK2Q0M6l/8Flg+/HLYPC2QXyrXOHJMF8uz02H6X5XxYlx4YV0jU+D2UP0cxbjbiyuP0/sV39Lb
6f1NYOPsEufsimaY1cIFL2vakYbtfbJovboQDQHNQnSM9bqy1JnNONugvzIA9+GsFyXW2mZloY9Y
5hBDEqZL2B08BWM432VBsmfZmXtFddrb/UaV6a9U0kMwfKJPEalcnJO/6xxVzorTsht6yQo4uyiP
zgcZdNqj9so4d5ZEx57BLfLzBVn6rIILGjacYSl3PWsyARwvv+HfnvnZPTrSTgiA0ZKIu/Oy5Ulk
CUwyuZGdTZguB5fWUcxmhZNJlfju1hxKwAHaaW7pjPa2Uwt5uhAG6iTHoldyaJubFVx/Mw7/wDpm
eSSmRLidgY7Au+5twlORANYjMoDO9KAqhWZAwVRcZ1acnklKKGwiQrcAf8jLChj1s8MQf9sU3eq1
jE4r0sG2fk3T7SB3wqPpP7Hcsn/aWU2gqNunXHefr2jZPHqXI+vVSKlpO0AoY1X4D6LOTN6c2Aul
Hod4XL9pwRyCfgHJ/oGaQRa0ur4RNP2SYjocWNCFTAhOBCdZFd6al9N3UDUM3VRLNUUauJLR0oMg
J0zRE5+ukKehMjEFvylJPpk6imY4IbugrkMLCmHwYxj+YPggNmsFygY8K/0nqvfpndyGTZOkfb0m
IPITLLh/jlrGTNz9skCFxtzLrdwfwfURZV6spEtAmLkYw0v8Ly12gdo7DQFHPLUsLM6noSAF7fex
o6DIzwUCezmOdjUPrYGHYJQZgZq8cjiF6rHddMbF7dshAD/ImDaPHJHIwVI00kxaKdAr+C1WwWfD
EoDayvsigJr7cEQofZ4ktoUk5+bM+t5JtrQ9D9pFy8jiuC4znSTp163AzPnPAE9NyIDYEjCNVtVY
yarRfOHvcbBamqRURM36NvlZ2SGfD39wSGRuPAHGd59tsEfYrCWiYhpfhE8wWeAtO/6NHgRB6FLc
AMtkBUmNASFVO0wsTYKHEZjtTYk3stnvMsbVP2KSBhSxOQA0pHnoLph72AJEMVd6vEhYig/SjgKX
xSLkVqBnPDEGzoCLLeTwbyIxXI5VxZIJHYrGDATPRHQCPwCFLLvzCmspMwHToyNXt6scezx4jOhu
lwFu1G14Ys4JrR387mOTCYzJJCB1UvR1QehDU63n3uohXyXmjvCrhCtWrEuGRFz8KLsK9r1vd7U0
gbdycoDGjfW635pOW1XGRCqahVmXGwav2yg0u4SZwnOvttc7fy7WCQZYqzxxSzWfo4LL4Qn39wp8
MjqYpj6J0nHvlw5/381qugFyjxD/KLurCi6Xc8nYz7rOvmraAuuRsG4EfqCXF82jl+PVSDTPAEuH
Md6xayw4MqaJQv/30qbzYEE/ot7BmfP0/HVmlCPJDtmyuw2NUdRpSEelSAPpVQu2j9owvLjvrK0d
BFLO9a8HZZq1ZkdYJPUv1jMaY+1Rww4KZiW7OfmwQ2HqH0eGkPM2q4p4VqfGBodJlp6iZNVwKM0V
m8+xMhpZvDpJxe094K9gCTjk23f5nkf1cHzJJLuFKAEQ6k6RgCqD0Ew04Gywj1VHNQuWKNadT2Za
keKBEDSbyai9eCVifvVfLzsVUV1RJ7gBUAxji87+Kqb297ZCsipH+EfDtuOAaqgK340KYUhu7J1/
dUmioYxbId60zWSQuEhu9N0sBIYmOihcIS5d9vy3nXxN+sZ7J/7euHmSg7g+Ho5u538zou+FX8dt
qILc6LWSZyINUaA/84GvS0m7UhxFHEca9/4nGiDT7w/tbsLuZS3dzy8a4AZTeV48j8MYEVjG2TWv
H0lsd4QBMsSCgoVsswypbRTtJhzgbsHh6bQ2kXV4cjRAaw3OoPHknRdvXV5bVEpmjUrKqvDn6XVv
C40ka8eC4Es2Z9J6Phh0qJpxxaEQDqW+F/75BoOGo8UfQ2xg6KZPlC8AI9wwym8fkQIEzVOlQP/n
1xTjqDs4HdoKYAuC3/7MHKXMebboeQNW4CD11iveZoVxjiB7SoVkQYYIsZDpWrGnOXaXH14Fy/tL
wD0XY0Ktij9N4rqGhGZwF56sCjEMFnaBqeLFScuFozrJwv6oAJ+mVqnsOapLUgsXRL5JNNMgAwkg
LZSYSsm3pzEbQFfW24MP0NLhYcuVJfYaUByNNBQsVlv2eFfipOdwkqgpxl2JsfkSYJoYffSJq4Rc
9GX2oSHJV16RXdhaX+tpMF1yDDKdlS45VV9ZNQx0LR9Bl7fAeT377oyEyg7ncr42jpF54n4nKJqt
MTE/FUeHH0Ultcw6c3E5LFOaIzGbhk1Zi9giYd1ZiVgv176byiPG368o3qFWmkm7RSp5oAS46znJ
cWyUGz7vlySV/zJoWvZbsSYpUJvbr8hKEyPUPa4EomUZzk/HCui/tCEFaEeJoza71yYmWhdPB8vG
+TKrUZQWQwenpGMJnT1WRpllu77A5KrEUmh85BLw96KflsMJg10Wo5wd1UqMl1cGqKfiaD/08CyO
mCZCxXWgttaH2hULauZ6uUIURZCitIppVhzL0VHFCBq7eA82kn8g/9Ba00ed9vBjI2zNhWXEzHpC
uKfJqB+d0On48+jAelRVkDa7fyTNo9Z87NvZqRAJmgRoqi+yFPhKilfz/Nw4PfXkMdk12oX/qBen
bqOgQaQzgcvevJPLWl9FSFZB9ys/gjsAcheQDgEwddCiqGmRcErXrtPc/uY2yHuYY1Qn+hAxAvl4
iu290J9qH42yPlQgiWBtLt5ArZGZH42Ete65cXS3tiZAdnKmfoc7BTHGPKN3+k5IRs9HV44Q0ku5
MBBy9ajlF2jbfjcU2vbMifDJ9J82HqTh0CoDFy8V+EfAb4y01n82/IEhxSO2AalXsG0LJDS1txxT
CNjehKYwld3qZQ6Me6rOlI3FCQpdXAJpxF9KN1dolD+eJsdCzpb7ElBkzQxy4dPW99ydTW9z3cy8
W2fNlQA950DtJMB0kEnpiE6uCllqvkLLDNYXweoEGnL/miC3weUNfXwGZ3u5pqRH+puDUhyIHJB1
lEAF4Rc1HSZ76fSXSp+3bLRC4yUngMTGclGnWKe4mYntUIgDd1ln5Ecpbs2I/V9Qivk7NPHq9gnZ
e0diNQH/ru692FgYsyEzVPalw3D+ZirzaZ6RMD8VmiL3e0bqK+dK6eU1MFo+/XHDqtFCcwgP37fG
XeYb9+Y6S6wJQFYxPWemyEarzlJ9DaHrT3MjUAW/+qIhxVmrW8uI9IK7WSoy53sPbEXd9KFqQAFE
8jFP1fQy1+wRbfNHDFRqs7PefczRTspEGPJx9rhGJuoJWi3G1HeIERmpasxKA9gTPrrv0sg20sD7
LL/4imqZPlDUY94owD1h0wYLmLPOMJxIyuKlP6zj0CQM4PgxrPktRWJ9pOfmmgicM0i1UlHou6Gm
+fKJSCKpysbswI2a5hqpJoMGeGqv7m4bGNjiVh3a9z4pGeRRdv/Cobn8GoNU3tmcsf9SASCTXKdu
6xpemc2bJJFU9K0GuGWqhdU1ubBrNr8sahA5jTATFC5NyyMffyoGvgFfLr2A7VGwHaVDsMgc2bCr
TPhoo6HwGT1+fsAoGFp7Y43rdmLDebsKYmkVOrxnVfCStTwpkOTbsJjqCmqADGu6iRcO1MVvw6AJ
ebZX6eCmT2yZS6JQ/SHfrQds74dhHKeNfm5/JsycH4GptDP9Tf/RVdfDpGAaxMx9nq+FAlETgXay
IkYuBn/DLJ3z/LwH2iaRPlCNxSsZszPLY7NzYFwI5kZNJFCuA2Z8VIK2nrfID7XeV3aYUL91xor5
STKjCFCGeXEoitvcXZ/2lxwVPOjdQPT9WmqjKq2y5IlyVUxl2aKyvKDijOMUqpDjkZ1PLsq+YNVk
B5/vmG3dLu9x5d0XP1STViCaF5L9rsMI6zZfDPaPF0qPKMb/GOXGsGUf8CR/PXjEy9LJ8Xt035MW
opbevee9ue1+Tr/gz+WjCQMJ8hcXI5QxTwlkiLoyhM6l1bc7NmFwHmk43fSjYCK6R7OFqJw5Kby0
vP4AL0n9tbj0iyh+OPha9SyonWWsT/0dKAPSjTCos835NYYtCEah6Tg8K6IMRIENvhNsaTEqd8Kb
nptgE1tjwphAqJ/Lbco9MXOSuCMEIunXSRIB5UghUNHM5hJeiQ/grgTsDmg1czko8GirchKCg3aO
58y972E/9++O7JjU0FAQt/dY8sLeG6ny0t+TensBkQvHtWQKw5pPXdpgPT+8I+o9Y65oN/GuaY1E
hRW/vTIbFRwq5h77xCPmLZ3E5028r0clSY8TAoxuWoKqp2mMttDK8irX9ke5SJJjxT+EeyjiJKO7
/SnWx7aSfHXIOhLVzN4Frb32r9VqVZmJ8yuM8wtQ3jFqCY27pAQ70k8GSAd1LH+ZPm8BSuEFPcR+
pKtP5ozJ6euVy79q9BCe+QSNWydQm0OtieNPiBogKlmtNOJcrr8lJ6OGn+Lj4N4MhZaH74BkPuF2
XV3yOxBiuAdG/N3dszeKvLOm06bLIlxmtcxw4PXN32pSuVySYbfGVsAeDUSkbxTU6FEK3R4XS9zs
/rIkQLbmJe0EwdeQegDqVe/Y2sgqhSkOJLcOAk6uhCPfkQq5KFdHs38WnbJCw3iknDHvhI3jr/OC
yxaoelHgmdGmLTz9zGoSIZVM779g48iEHIJBY9DLGNUnjb6GwQpv0YzbKBHFzCWOb82WZh9Hove9
Fasgo3o9GPE2d5karjEeCq26wLTf70H9E7gzuQhvZBbUG9qUJ63fNs8luKLaE6qvmWINgSsBk+u4
XSVQsbX2tmM8aiF4FeK0hgkjqIz1286BI2Cyl9IhSSHEGmP7A6qlEG5Y6iHTlqjIvStJyvH3DGjg
EeWCO0yFxhBQMBEUnXfQMBpwFf8twWpraAR6VtjV5Qh2x0a0/COdGeJsjclGDY+aq/Fn46CPtqXn
l//GFMAgmyBl0p/oBJw74UqyzmV93oR8hDznzvJ7DpdV96aHKkITB4s78N2+DEtEd45w3kayTXyd
X2iU/JTAjmHsdyYoP9Ke+04EjbsXWBYIgXVxb4qKRL51RAD8Q3JX59viF06C93yCeNnokJ5AYoEB
zcklOowNkP4ptNscBkf10Vat8/cXKRz/lAD1cRkRILLe/wfJR5Bz2UNRLJ04a+prjQ5BOGuMa+KC
1Z2RB2pyojsFuJ/5Z9L0d/Qp6BKcqkvqFRBGQSL8ybruVYsBamDAIsHGz02+YBY7GNvsWHGUxcsh
HXmQflZrihUJiNkEG8d4De6zfSJcq0iubA6VwpLZZrZJBLD7FDrKxTq0TIo4Jkp75O9v1yrKq/dz
IVM0pQGtTVkh413Yxd1mBnRdEszwL3Z9bll86uqahmVsJVlHDybxGI6IAwCvRKOukB/ShILH80hI
UsOkC9W42E61wmAlFxMI/r3rS08vLR6dtpzlEPQPxaXiBMtinQ6xmjBdHcLN0sMeXE8Ap7UBNM4b
zEKzdq//4ZcsQRswXNdRbmDrnohtzVGTx5SBktkl/NlY5dLfNdfJi4Z0ggSE0dYjxl7hGuExvLgr
xJOAryNnJrXcvQpwmkD7+FSueq/NqbrGWp1Hj7UtNckE1hWv0YkEXrVW3u40ETnasqq2aSM5mj1l
QvHBqxvDwGZT3Gnn2dy8L8nHzelNLWZEPYbzm1O4KhPrChTFEy5R4K1gjDErVZFVuaxZUz29UZV/
luh2Eua7Q7hLvsfLBhRDJSYWg9AxyBnJhG+kODng2xXpJ/f8mP8djh2eUz4fnOFBjko7pqjpilWt
bRGImitp5iqQI32p8/bkzeM//BCkQqL4MxClWFW7mPkQrE/1YURtpCAY/7W6Hzb0fBjJG3Aj+npU
wJH2BFlwYUVZ54COVSz5WHXv8mDHhzxoN8zYMVWP0NQFXPpPALfQKzEnPwjcndOfmix7FqF2bnLL
JBQW15jHgaa+f+gpeLJtJ115YSB/jQ2oVOltll8nR9ad/95hdy243DKOBQMvn+OvE9e7/bi+MXPr
iz8x2enM/z+b8SvW+FMI+inDRmK4k2KoJdaLoYbbo5NVDgxen56a4h0zVOUtUMC/+rKfSxevTf5V
hzZzjGqF7O9tXIH/Bz61vOC7WCNFzLeCjOGe8T7jZtk9K+lRqt0K8bDzCrMFKZQEEueu4QGrE33S
yNRS2eOwOTi6jEDSdkuO8sQtYdxCPVZIyFaaMjcwAx4oWZRiHGCkQykHK1p+MpHkKEUkITsowTqs
6Ft4mapfNsRvsOObvLQ1k3umng3VE3m8Yrj15LaT2OTf8YLNLpupFJF18GSKlYidD68TCXFLoPeP
lJBo3PfhVbzsPjap+I9i5rkSbV9rYKO8Ls/JwctIHWNypPqDJo+rg3+RSYqYVIBsMVG60+3IHSU2
iMJ8kpiYB3//PseBj6Yi74m8P6BaXP2Y3wXqWLrc0/VpVW9YjmjOVQ96OiRyyT9dLtTZ1aJ1efWm
5uZqYBN5mwpMpq39GLvx4+pBGOfn7iuOC+/lqJV5jO0tQhUrGFuusCADl5IUWNoC/g9NaQdIqx5U
U4gEOhWfRg3lWuJLTgW/LLBS8u4qsAfjj+x8nDz6/muTurAffCL6jvZvs1FzWOcAzdV4mZ3I+Vd1
XzR+z8aI+H9XRKtkeo+vFas94JYW2SU4FzC1+LUJAfdvDEqx7zpm8eJwNrCR5A3x3R7jUFt96O30
xfrZJwl0X7v7mhMZZsDGC0cxBlfJ6vDVTOtRRLJxJwUV/2ciJRCH7lXz1o1K7EQoXOd1QzTHDFR6
pqjA6wy5qhqs1YMSJ98zyvRNhMpxIPxF1QvYz4/C1M4gUMyR+hH2hizGWYvVwinusNnHd13jsIHo
x1wQz2Ye2RsZnsAb3aBn+uM7UkQY5Kayga3DKS9Ir4hxNFUhbmnrAlcYA5A7STK035Ny2UUMk78W
7XdzOgMZ2z20YRmcciDX+V4Ix4mEX2QNt0pYkR4nK2hEizLS59+0zZi8FFS4bPCC5BQZiPUMQUMS
XB3bZwDI6If+hF5aLtkhGRTrQiVFAtOtMKONhXuQAdDnvHma4ASRyEBltO7FeIbAZ+GlhhVXB5Ln
zLw7Br8FxvrBbVU2fNf9BAjhYIs1znU+xN+EywVi2QE6lGYFh2puvNopW80Akm6ZYCG42aXikpI3
sUCoTqWNQoZQhlrYPiWpaYLG379mFuBc3UMYKWIp70p/3ARauqHBcRJLamv4g7sTpSAEorfP1XE5
GyfVY4WFTXdJmvVvPc7bnCtpZburbWFtc4a9Vs/0x9N77wAXzHBzg3ImK56XgMt3VT4KuHdka1aU
oAQ8UQQEZ4WUmC0d7F/gr1ydxE8FCEbx635D7dZZVZqsCyl2R7euonHUgA3sc8BxRSTj9mj7XcxZ
7I8XUCKJtlOOJpauMJw4upVLaQKW2LexG8nBm/Gm3BlS+HQiQ/AYfAOkdi6Oe3hnfgLgmdRUln7o
NCOw0pMK2ZTrw02dRklLkHG4LANtdBFmdu+GgxoNRLoQwEDmOSGyZa9Po2HbIC/6xoLXQlx08Knr
nkGhWPykInbETj0lf9RWizFerDjaBBCZX0VxAEHaNbrCBgABist8YNgZRp5TyffB+6PZk4StOl5X
///++b618tTvsvYCxBo+OE4BFMDHY3dEKMUS0391pJ1ceuO/Bds1V77I7T4FCSFzCuh9vytNJyDz
glda8g1vZJKwhiF2xyB6TLoCAQKAVfNQN5PnlrDbbGtsLakTN6RbbtOi7UVCa482gDrIPlKbukKw
DkmZ0gnl/c+ZjJefbUcvanqpoZHUvSLtSIOabLf5p5wIQWnXi3dw7L8cSmu/ji4kaCV20iRXPWf0
dt9wyHIa6Goutx3FYzWBzZ3YjgC/d30tTbeVj65k7SQoAFNwte5EGKJeLtB8QEHyBmGowfyL7FxC
jcZkpKaE9i38SqBfIukjwR1p5wOlaDYtggtezpoZw0GHBuKHazblHmhfh13sQVSG7RwEE/i3H6WA
EM8JFUhE04tOGSf/MNsIoeY6tkDEdzmKQ86tVQhf81o5ib2rc3AER3EKaSn06k7AIw1aDxcblZ7l
8FKrhb2iVUZu2WDU5E4dGkGkAyD+M0hAkxvcE/SyzRLJYSa0Q3Et74sj2LVH1hQwBoMKCZdL/Ro1
rU0M7N746cxk9jti+Hruk+7vf0jQCWwq48nsV/gsqP5YsS99PwReD6i6fJij35X5PpsMhtARdIf3
aaltrSIB0fHNM1G/w1fXKeUI5ZIM9y+O3+KJqD7Pei/qzamAWNkwQsYlSg9lAeIlHxuteeYWi1xc
Z5EkMY7GOdGbuH+wolintZLBXdnCuIzoWLYYm9U07Q42E1vJvNEyOIi9UPY9IbsnffkQ1yVdofWz
t1OoRG61AsmmnuLEeeVV7rmLMNNKovodc4ok/Pgpx+PGjWSg5PBi5B9ZiPUw/suUmEZ9yeXKAKWH
UayZd+5+WbIUfFvcFZR1TPX/qjSGb0J4UNXU63ww5Ze5FNW0p3Bm+jAmtwjAHRLBSZzkfWDWFkM+
sxMHJrbjGzLwU5t9vIiUDsEyT+eRVsaiiSQWbwft4ZAFBWuAnurFql5m/K8MwMeU4gVpi5G3b5cI
Lwj6PX/RwUeCbJJTDcGwgklIDGMCgoCewItGONJBtgtq8HK3KA94/iO/gGh0ikF8PWy648fPNm77
jht99dakArBFr9pG42rbzBq78MEE8h4BPbNrcv1KBZ7gAH+/GUpF7oFiYBdNVxL8zXwEksC7bYCG
mN8mULDeyIaNPYeeHHTuiK90i5rRul5UiNKwToAKB2tI5EwTMB3ZRSdCvXFTtIVVyrxHlBAqvm0X
v0PFiKFArSPXOWw9YCOnSN9/gFCETT6VFAN4zYBtm7jt4EslhwgaxCfzu7wjM0jw94PvWruRjdJ8
agv2fCNLpHNLk7BpfSntGQ+TJAtOwdqqgOyVgYQPf2ZCqsEGNp4tmpr4PCQkaQ7wBb7bUlRYh6q5
U/nVIEAtAF5nopLdQlU1fmA2kh2Cwd92TUx9AQ5Z2XJps1ZenNqIFzzSJQ/8z/Kix/WT1JocSk72
Qd7lrgvYdfuAW0X5b1HIFPOM1PfxnvZ+a0wVH83RPmXT1AiThdDWqDk40spmhQsM4o/dTc3csBOh
EnDRr598r3O2eoZsSqlW7A422godtPxiBcPw7ar7B7xzLwvqaHoOeU1zMbtOO1DYtWWn9FyUpTyf
HdOWt2Z0u2aTsZppwh8TH6xVbax2tS7zGUQTFMrRbpacjHXOgsU/LiwMoK8ppnQkbNzkarAdtzvt
js4tNiclQHiORycwMW3G++WMbafgdKWoRbEokkkFgwkg/U4E0ld1yAdKe0CJY/Xl8veO4RWhDS30
jYF/i+Vh7tlg249JmZVyWPy9f7W06tpAaNrAwEMFZW9CDy92Ui5i1VbUVLXbN+JKe/Xo5yasUO1H
vc8/R2LMfRGeze7g8byQJ6GRX1YuAb9VIHsFPLvXF0Nuo0tnbiy0cbXorlqmlEIfVimRQMgBrjEv
q8WNGl/4op1hbqLfzpadurjV4IsOMVm0EUH1v9qplexSHKQpFO4lBQ6qLP2WotZAkGkTE7Gx3E3p
132CEYa+H3XxX6tJaaIwBVRzTXQVTRm1FcFnhkle9dlO6PiOTXImDVRwfb67G3liwmYAmIBFhowJ
IfmCrogHnaFeXh5dx6fCrPhqK5ktM9WgdWyIhTycpdbF4EuStYi9BrE4nwpwFmlVQd+lG2KKH9Zl
ygIUCPcN7dwzs39atDs4xL5X6j5WAhmJCxEcxrZX0YYMx68RYoldFxx28hUvw6VO6RmcJeDBLr+8
xPfaYisp70xk6x/xn4/RhalHzGO1UDYszf7xym22KWZcUYwZu0NqDSJmbevt2VKyx0ZywU+MaCZo
GEVRZbJpqw1F/HJRhJ99JN60PIIuc+0+c+fqYMjD5kZ9KZHBElNPaUwbHkEPK05mumZP213yaS2A
rubcfs11RPqAvPp+j77dUOtbnc8G6JwIGmXR9o60pf5PJGktOkBxV5/xDQG8eIyQCL+KeoZeTteI
f+Te2UWrCLAwihwlIQN5ZM/RK3D0soKvqLGFI9tElrUe2m71BMDmratX2N2oJ7fgW2QDyYZwm3n2
MQrbfsBZrdpV1TppS4Dn8Q0x2PIgM9xd8nMcBiq5+PXv8L0K6IeDh+cI/xbvX3/EVmz4pth3m232
P5xqa3wFWkr5IVIFodI0JbH1r7fSS28oNOc/vwqIVLQidRusDyDJua9RZq26RIkkaIvzQbxng89z
B7/oLa6fQkroSzw6XIrSnws7R0ViD0t24DH0X257lcwTk1a5u4C2I7WTuhbHzwwM0qYyUO5TPgxe
BARhkD9iwzf9JlcWBHl3FJbxCPPCitY5+l57CHx993uqcjw1QQ2MuWsjinCYbpHlBZVTZL/A6+hM
OWHtFmyvntmLzGmF6oZZYYct+k9R6pJ4L+MNPknzWsn9fOE77HriFoKJq4KQu/Acl1n5mctrJJcO
b4MsbE8Dlp7DxgV972m+N8wEB6d48OkRIzNbrBOXVQ/ashw4UX+KqeEnPxA6JkL+mlcZ05/EhUWM
6yHHyD+FoHazVfq8yFn6GV7ox+VU3agLVZhhiEML5OH4fqNDpdUZHIhvwV9SjRLd1pMlqNCa7EmG
8l5YD6VFBbVZJHHy5AwrVe10C29gpf8zTIh6ZU2TLWT5Gs6MGbyf0ALACneGxhb+LQz8w7e/Hu1t
R1n1EkqVCLBzO9TufAkJJ/HnR6+DzZoh8svqbkybgoCvXMC0dxZdOjb1lXpDuJkUj7/n1/3Wg++I
S/vGK100U+1s2PCbv3TFn7VetalwI07wQjUiYD+Hl1adO7o5cBYSEd5D5Qn4ipLM80G+BM8fdn+A
469qf8k0eZYPPSi28Hpvu9wzlMzqwy+oe7sf6r2/19/2pwgXyeH456xwLSkcsY9Psy6/HdGLad+r
UsG3B0reokeIWYC537li8yfwKPV6vh+IwLWeeG8BhIMkaGJExOAtANk/ZNzHmm8vREDLpWDBz2PF
A5zR6WcKU3aP4f41B+/2xftN6F6rWk5yaEwnNLyxSURezc49vz4lhz2HFt2DdLWhkukUWdB//Af3
6swbQlwWbOVQ9yVne6qgR3M2KQSTutqHZrO6BimUZ3VBAQmaNQLoANP4Hj3Aoj7n9vXZgSejANT6
KJcC92w1HnhyC68ueG8klGNw8DjdHZQurvcv4eynqQ+rL2hCQ6Awsepswhd9e7MKKxrAE/BZ62rd
kYztEDt5iACbhCdxbNbO4y0elavBX5h3OSGmhxYetzWsOnifcNi8GwkJIx/Qmm6EpNTcA0bCokdM
VzZSbdPISB1Q6PTR/01/y9SRNnDdpoa2rOV1hChx2UEkFj2yqewgvHvnHJ4lhZdgjtKpTjzDclbD
dWuwsusVqbfuUjN/lwvW3H70F6bxbd8P2q7zdu/Pmn3gWhniO7cOKY1wLMi+e5gFBtPIg2yZsfZc
VMxMtY6vaS2w1/27ScifRW9IzXr7K5F+yoRhHO0ZNVdZiejfeKDn8aeIwLgzp7NRM9iFb/ST8MrJ
mjbW12knwmUkDhlFUjLuX0CNrOcy96lrJs4CPlpYgCLdoEfMtEplDXxI6PYySN1oj/BYCcZ3DXf+
aVD5lLfqOtUDjg1m8OIZRODHQsRPhewRusbGFl08xF44UVczPv5PEMap/MRdxriwjmBCbNsdodAp
+DwJf0K1KQgmKgaiy4vjkNsLNxLln4Hkue7JXWhM2kUkHpkpT9phUdYyMB4zJySIOUHBb5lHhu2Y
9StIpv8Db4ypDEhIGZghGAtVeGlYFdU8P8tioGrf0WgUN0csmy8JTDtMdAGbTEvPcqcdBKacPnUN
Ysr9R2lha3zuNFlm5PtbQO9pa2MPS8bc1HvqWTz6WsMdpc8KQb8gdcjgkg9n6Gp9Gnrnrk79BG0D
56J26qQd8b13l77hIv79nNK8Drl2EKAYQuf1GNfgk9EanHImkZo09itVY1H9eqABAB4wtuh1uzau
4mELaRAQi5Lla4y6rr+EKSN2VzYWcRej44L/jfKlN+ZjuH+UyDScS509SJkCKK+IpKGOB8/4g5rt
I7/1lm0KIJIGZ3O+gtjx9S1t9B0OnhW/cVseKWpvVKIUzkGbOIGND8kIwRANdl3e6n38hBal4cqa
Ec59zhwT/a2R47wwZtzSSonHzEnPpAtM3MBB4hhMpZGJMtXaYjzj0xnkMmGhBN4EoL4QKDZ4nfYo
A26b78RmXHLksB3Pe7OmeA369DlTz6mLwDFUpvjjqAA3u2+zW5AnE491jfg9B20VlFqlzqIXcFZy
gqIIpnDOF6x2Da+pvKioVqZK3aYSR1XAA15Q6WBL7mDXXQeqFaXghKDcz1Ciz1BprOphedHB7W+e
pGO+ZkDa3yhDxXcZQ5S+zu4JzL2XFbQx+yPx8ujWs/TyGZ9qy9RoXbYZPh1qwYvb/aTjFH0NNhpx
DLMDXrNT44TzbofTRx/acvw8SKS2SeYTyYAn8XaQV2fAhhbd8S/Sn5ELQtrt6t/DgWKvbkeBC1fx
iyoApUP18z3GvcjQndMhCbHhE0+fqD8wKNV9M1OqZKRUxra6qsq/LtaVVVlxunkJq+rvJfMqHZTc
yXpiqJTVD6b5MggL9wmGNzuPeJsWNmapBJ9cbdFwPqaDrOSlwJkEUsN9waI4xC4r1jc7z/MBg5J0
CmhfoMWot5eCwc2CeXHw0aBCZ4pAeMPENpc/inh/7+YXFvDZ8zb0twMVmhVnN88X/TQYfTu2UeIG
DeWVSXXM2CXriUVAogmo4bgiBdV1viWkGu3XiYPCmue9e0g6i9d/ogymOY3RnDnT6MjxyOGqV3nM
0TfgCpBf8fGYq9eOdgzFYVMKAAvhXwmX/1r2iyI50Xm4eJILuO2hxvK94Mw8F66QV9DgeEz7LiJ6
i6k/gMmMhn8NFMad6O06G8u2UZTf+cPU+zjJRQx75IKpLEBHZQYdeICePa5g288vLujId/8Uv/qE
7+7mpbzPavvmH3DBupYxRnDju0ay5V0thoULeAw6cKDtWOvX5bWluQUOtCwP5TgXf0+hSKag9Aya
eiBFlW/YZHCtkoWgsN+s7AfEFC/7C2JwZsDbMmuzB3X6fQLcsIevEqRZHyHPiIDLpFVrWDGmPvXb
yZSLPldz3J1U94OnV15QtmPQoejMzxvHipvNqiPlH69Ss4UTrGb80A5dz7TCpfBw3uipNQNGmxV3
JShd4vaTGFCTNzkQM4CT2lbKyo+JzvFgm97G97em2PzP0PK7Rt2TroGON/CSuL3VLXyW+mLswHqy
vBeAwM3/Cz9rH7lT/nzIVWKGDYcZzEoT10F2fy3/2nIT90NEj0uQkELlQzeRAgi3NLnOGJNFSVA7
JNs/ije/ex3MWjqX+Cp+hOkUIamTDM+PGcWbRU+rE9j4UCGiT0s1cFI//b7nAX3xmORiL2hqYvs3
2AQM6/ajHkqfa+6iy/E0vn2xd8qITXLiQsZUZmdeVKMA+hV7IYwTe5J11+x0FHIMWp6yzMDzM9uk
yesP28PabkMRRMRRrj5kLHKrUktdO/XAiHIIf/tgEIz9YKQjI8SmmN4M2QRuDtzPHIKkJ4HVtrgA
E+YQoGadTApGI9POSL6CEZ1/7+c+AmQRio/q1b0eg16YwZ2mbV9/1qIKfP0HyoCo/QGhxZX5iG4B
eXv8mv1LPXKe4cHxwGClLy28tFh0f4WYbTMwfBabGg+eZqnR1sTUg7BzV1Zp5XpzZBclrmbcwO+I
GFQbxGcvArrmmZr5nrM1YKADNUmDJqazI3cPxRTogoXW+nR9oahXZ5ed9GBBYDO5PYzILSFqr+0w
SBZgiLtuUNddVmh0bvw5Aewp3RpNRZtDpXdedBoRaudByQcakRQ0E/yobd5BfPqE0vYK8LVMv6X4
1ms8WzgQeeQ5L+Bq/a9ShMjrGQpI/PtABmpxiWRuMFcAFQY7T9gw8bPlkGaWzOx2dr7dzOk0ziQm
0ULq7AQqWPW3z49nrA6p98RZ3rp4b0W0/1lihMWSpElgn8Tbg4s0ArGJsOwqE/He/dpiuW6AcqP2
daJb5xJX8vRTrJ/LH2g1hysV8NmRprXLVDXy+aIcyBeuWVi8tKRPZ9ANxlmLeDMV8kgfISk7AZIs
Jphk3PeqYf2nFmL8HNezIYykPn+Gk16662Wqx83WhuhCa2dBKbKvfH2bA4elXVluW3ddWEQ9EB6C
6oWaSgaMk5+7pj9Yi2sfsOtANgq8o7JYV7WbW/BxxRuQZ5/FIttr/RJL9baZudHcR0mvYbsH8n0N
yaFi//57N8P5bHDxOMCEfD3+RastslPtWrgWpdDYOWrUHOygBemjhFLntZlkC97M5obUapablNi9
YGOCxpxjfUsujYwg6Zxsw4dna6hc8lUnCftoFodxlWAXp5keqhrTz8TMnzDNsirkymi1jzogFfL9
cjsdeJrGzIdezWXh0w0W1ZTvYTNJv6U+uLsMYe4Tvx5owyaeh6KruNfQfRTE3/MEx3h6MqqML/sc
SpoUbz9uI9v0HkX3R3/RINRVpD4b3Mx0Utixm6F+HuX92mzcaEknuPBShU9I4OGHAYt0tudWY538
qu+6Fug5HugcZTy/4aRum2CbhPSSVyeCrDGy0BbXZwmRp9UWJKblAGfQ7bsd5I4ek02jR0xoauWD
oK5csuNShPFvv1ffdd1WwafClDMeM2C+Tk4xOIy8nyh+8lv3T73PgN4dN5/g/gmJz9so9gFsM4q+
LCTV7C8+VzW2umz480Mt9pm2HOE3gPMIC8IPCLXx+VW3y+PtJKj1Ns/hSNXIWEoJyxb7jEDMl+nA
VjIxHbxQ9qpp/iqoF7js2vQO6cOrFATsjZSgWdQODVs22RpsLL5tmlFuMUZ2i5i1c4GGWj8vkc8O
B7UXB8ZXHTnLmSx0w3GB4e9c96EePxQqASyXQe7LI0XyMzWi7LHTnMapcPsco5WVJqxpHc1u2T9W
hbjhvlQvU5BbDe638BHWM/aoJQYoyoGA9TnKaJEIHVICFjsyGGAz2eyZB0YVRV8Yoac3TDlwL2Uk
9zBgw+MC8CAX1d1sN0B+avgqLYkNNXEkpyLq/9BW60ppNSHWNf6ynp0WWAyaCWdxEB3U8DzyIKa5
m92ni9m2zh43a94MpzRXlFASn7TkLx07D1kSoUwUK9+pBGWPW+eNcaIagcJ2xatVgSr52010uCF3
OKuhGyQU7WZblPTsEz1py01R+tkJctqD5tyzXHmfgVW1gy35HRqofRtF8lGadHm/0lGVgG5OvUdd
tIUAjAkz1lhIEkNnQbuH51bCOybE66tnE8Iav0TCZWadFkORzzfrXaZKTGUnXshP5mq7K0VobcFn
OXjFQ4JdqP0XRC7eHKFLc1DXj26zSbuu6HKJukEN5I+aHdD2v2uSPxxPX9LXJD/GG7V8k5kIL/tY
tDd0oFIrl6TRnNxZiyYfTJjaWAc3ENA7nvPALM4x1f8aRH/EI0MOvt4Ou5Si3dp40v69Ab1sr3Ep
VPLgOSCmY1LWcfEW0Dnvnq4hjk8FmUk5ya1TPNKva9kqlHBeCZUV+s30vWbUQva52IGTCKBYaWQr
MufIe3oGnDnCLEOBiC1JkSILS1ru/VbtKGBwhCUeLXenizn0+IJW5MFYzGO/DiWawqC1bQyCVmU3
sRZhPvCIm8cXCx812KVffBwoVtcN+KOSmdaxZH80tb/DGpOvL0AlSLtpTwoCyt7Aso941Cl5UZO4
p/CHECtQeAQm8VBdYBU/Z+auP/GnwAlg4NQiqIAhnyiIIqiuwjKpV6o1J2zr/+VF/1SNkM85Ygwo
OuB/Ejk/05zOeCn1Wn/ftjwbkHhhkvOzNWAcSyNZf6mpf0+1UWQyuNl3pyWEN0hQ9K81scrH6XpA
+FQMbtl0RXxibWgheQOqvm2sRko9h/LVMvdRNyWvA9G0DiPTiG9hlEuCYXsbvWireWP6dow6kN6r
uWr6J/bSPBKvny6ukYVPzDyb3jDtuf3p6HrDrrGn9bwhToLkiPUCCaTDcJo82qhuRn6H/SUTFaRH
L6Y1BJkxXa8ovxCwFQLtJJRBFQKrN6qrK79LdO2d9v65BxA92d60QAIGuzBldPOJkCa7EuvqGwFM
USS7PvdA+SyRu9wDzhrurKQLJ1jDgvz/uxhe0KH9XZ2YJyt66sHT0CqM7d6nR6X5ZGsX5GwyF4XB
SWQJUfZmQGbn07jJr2HTXFGjCEwKkyqLE24AdHCXy/f7HqkCFLoLqeAV4aAJWTfOvUBPBfYihu25
awQZhS2Sa6hA+iRkvXpg2Q3nODurA3/tnL21BGrWAIc6lNuth2/Hzu+6uAYGHJucj6NkZg29CmVb
961zxLBvcw/1nrbicIx2d6q/3ZC2fCU0C5jeYrDs0zK0W/4stz15EgVK4AQqpbuuISX8e0mh0FT8
eF01a8fkhOVtn92mbIPK/B92W+PE5ag7nljT9M2ncn6Y8Zc2RadTxkfN/Ra7HHQ9HUU04mC/pEiL
qRTxXi0jf/uRAWKAlEo88e3M7T6OPPvOAHIICVJIQD1Yj9+YIYNMJQ/iHw+uhe3clUD1vATaa2u9
PJc6Fg95eTgXksrPzNy1hoEiuJDvQDGGv33ynsUyQr3etsK6wFFKZJDBKu5oHK3cOtR/v9IE49OK
3c6pSnuvB4banmOUnRAIqhvj8+cylc3rRhY+jeoKNyW19iPY8xwLwHgBg65cex/8FQujdf9kp0VK
rOkth1lAcxCFlEBWzEXaY4A1zGyBKhTa14o7i2vbZWhMiG6xWJNIduclvB/lJI5qxsoCvjwg1Suw
i6Z//wagvLcyex5WyyQTD8ZFYUwEmIANr3MhYBtw5nhku9j8eY+AqqNgkgRD5O/mFcg6WfSpjiwo
YAwnopQhHNMt0rOAo4+I2PIPInvW6f+tbrum8Oj/nc10FbbiLo8mbgrdGlrGQdU8KMksQIs1SSei
6W0/NEXzbpzJioVnxZ2By26TgmBNKbA8umJbCBG4QTy3ttmG1P8PZf6U4Zze1Eqh5LllnDXQFBw9
OT/JrwW97zBJ87mGhMi7qhZ3pyJ5Q+OzdIHehNWvA6yBn94lwKANfSuwz8F7AQOtKjXsS/RN33oH
aYZ+byOsxnP16V0q5SA1ocYxXz2cALfC1zI+Gj2sWsOCjuFv40u2VP+lK2FQcDPLMxO57fN5I4Fp
NGU4AewAzEtbKL56wnsuFq9eGIhZeMQtAWJDtgm8ToqiUZPaSl9n4NoU6A66/XiGAxqFvT4eR9vv
MXmHaGi1O3zJjn65UwWlJt8BA0qEfVPKyT9ibAQ1De3ny0AXicKRWciWvQRAQdBYNW4rXIOWJhKj
Y8vtH8od9A2K6zUNoWR3q/7O0yXmFHqQ3qX1HA8Aj6emmQXMz83kVdBwHmoTBveBH0QmvbzTPqgP
SSJjPUmjLdfyN5mkCtRTC9zV9C1g4rWBURc1h/Glbuyno7DMFiY+IJOBUDwZIsn39sMEhbbxugfq
grktuD7uNYC/SIO8uVADGOIwU0cSYPZybd6kIUwQJ11nVdHXxUK1ozZD0w3GwpGzs4YTYuQXKQNx
+eCEY7WUrPbxng8XFfi1vlH/1zhqIA77RdBzHpFmGPLlfooFlOQlL+ewyBdRFzmA4yNdFich4K7Z
3dV4Jv0PCtUEXIq+dyQHLwwFZsl1wY8C/F1qyLR58TZeCR9xGhzRrgmU57UsyFmpQqSOgq436rVW
3vbINJ4+3sGbOHdDPlEIoSxFMMdgK+t3V3GIfE9O9mOP27O7siZW2JmgWRZ2/fb8Tnumlqjomhvo
ulWcPowKAdqM7fGXC5F5Ua3lyhfuRyrbfY3r8UghgYyU7GbwLIiDIMoLYNeEf6lFjvywRiGvJn/x
yzK4cNGOanlUlpvqjUcXtDTssGNv4KKjOa0W9K4dNdF5vprXrr8Ai7rZstniisPFgI5OTrtYLl8/
w8A8HmiLT/uHtX1qALHzCiyfC6LOCIeLSsZzjBLwGDL91BktncTbx5kb+82uy7pAzau+XoKZE5gq
+UnjaMzi2H+6s/Dh6OJmwVtlEWLPjmqgISD5KCNahB/AD5XYxoOPvBItefCVQjmqS9QcuUrUmskp
nsb9EfWcWSe6BLA8AFnYfdRAy2dvguZoPn9VTrdkEe0d0onveDQNB/8wSaw5zYWQvd1Kk/5xFYYM
7scZPfVI/s5rOeaSLfkFsWu9ovtoB69/Vb49EpSYotMcUpeMwDRBLbg6yVq5AkBWZQQcdOoDZbId
9hpToO2OCIezq41YmmIVNkco/Z0+6eb0ca427r/riTBFZy7Vz/Ud5E/RfGNtRpKa9J4300yacSNQ
dSy2LG3cvyZ6SBRm76UB5m2SCi1SfkdQPZynGAYt6YA3WtOBU0lPlFANrCfH/qab6uW5RPtfxZ01
i+7k+s7Y7CcrwR7WSisV14ZZZkCutdsc4IWwxqyQJtiAwn7yfi7ZQ+mfwl4ePTbtIpNVG8TkHRPB
Dm2voEsuEKECSaCd3CXBMd/qL2uKsgjy2oKgiNe9yzwJupBOCMO9kmb8j4kInlAFyaAJ6QcEB2wE
DXUn+8cm/UU7qs3HS79LS2Vs44rusDtpzkmnb8V77T6+g2dVA+JgdqrKeUlScmeF8XcsBEf9Vd35
nbzh6lysJPnA1Y+4eg6vUXA6I5YyEP7zAvi+CeR34ggwepTWcvuEc06smzbNgrUaNaTMRZVH7RLz
cZjfc/cielCG0R7yPtYx0bef6b13/YiB0kn5Nx84KRvGIOaiqWAoC1PhhpOhv9ysEUBsMyrlq2cs
5xRnX+Qi89xzQjJeAhIWLv6TOGfRrH2WMchqxk6LITibF1iFXAinJ9AQMH4W0221XwzqF9Xl6onM
YmixM4BgGanAcK7jSYHkRRhpkRoleMs41tMw7s+yV73to+6WGLrgcfW8hxYfRjm+84KY3L2tt7lM
6isiI/KqYlhQui/P7QvsQO5wld/43XN9uIcsNOh6b0v8fM3IAsKLDCrF6oKLz0xIW2zYsJNJLSER
wKEC3Mec/WWr9iia7rTNR7gjWxufrTqBWVBdblEIC/ZWlXiH4fKX9zsrvVCOcd75WqxnSvWGeg1Q
VP2oy74xowxmfOROCIPcdKaQ05eVJ1tBhGxeZ4NNLjbn/oiAYhNLXa3I73C1DD5EqgrDcItlM1as
PJ5iVpZtE13XLhJpFl3fMpjPnDvlTWXOvjXnFjRihwJ1ZGLfKLeRNxzCEV9FuySFGzGycAVj+ESc
y3sjLV6xkwABu6er93K6a6+JN3kLD+nPkxm6FgudVNiJ0b755fSJs4I7IdxJJUqD6Up6xnAH+gmi
FlAduHKaRZKF+T8DBbLMYXja3t2XNEC0l5/4LNBx7xYds4yLFgQ6Bj1nfqBM3B5Da9fYV4ohIO61
j/J+amZP8lXlNi6RPPRHOEXlBL0yj7MMGxAmpnky3PmSQrKRoh9cZn4FUiWurPOLvfMevfhgMsDj
A3/Gbj6FxOO0xxRkD6kv+e4qrZyORgAISEhzQ6OId583j1LK/rID4D9L8FyBBZTWyL5Uo3LCITH0
REKViheZ2huVY0E13nC8u4r/uYNqKpdkGIYn2cFI28yxg3UkiTA9tK3UK7faqlP7CLKQvT5k1blD
9jYQdri5L7rAPjzgcmFusyNdGG2wlU6b7cSbTdzLZU68ljruio9/GngZxs78XkmMA+tD+l0B4Wli
htRyIvyZHiYXk7v3qd+qQs/MExEPuCnuiKVZX02VoD1rcKUAoDQ8QBOMUqzCzDLXnfWgT4gbkCFC
LX6eoluovz5QbOoaqpxr2bzFELwE5CL6nP9+QP9/1eyzwQo5LTuQEaUo2NqFxkfH5/zH68+9tK8u
BKY2GhkBl82oj4cGKPtGj2W23vfNv4YbEJXgzsArYMEdEDRLDe0PkX9VNpvPhzo7byFABbzTCHiv
0YaUVT6DNg+EbXLLERtF0vOp7ncJ/Eqyn/6PbnFuarAAIfDd2085hbWVazddNxfVd8dhIGJ3eLJb
yebce+7WptP3usout5rbP6xYQaYExPxPVcIu2wYilxlWM94X4eT1yTHipieOqOI+7XOjau2qokuB
UiZNn4pBKuK3HedqYj5Xwdrzmu1HpWjsDZwDWHxP5PA9w0ETBpw+QZUMYmHZpofsTMgPVgvZUHT8
QjLuuACDaLhIs19oLxIiCMKYp9CmxK8D2nF8SYgcvVCp2X5hMQ36/BWiwTI466j2801xb1RBcQ3A
CIEgn8o6oYN7q5aLTdHI/gTlhtanBOx48NoFctEbL/nPZa0evQ4xFnDoYImaewldiHxKj8CH+X7b
0gImHV72Dv3aYJ0C4AbHMq6dRGoBXsvtGnRoSXZEGSGx0L8m3g3Lo17oMRcVAb8RkCuaZx68hIbf
lhp8J8AYh/Sc+p/502dpF96n0wFX7f5W+LAOUC/0PpfJdUtvsWduK5iiRsE8G1M9aZURWahz9Q5T
nE9gOUs0IcQM3OJno/jtXD6Vk8oyqCqY9OZZ7a65uRc3MMvpGn4d7Om23ebW8OZzv4hkpttHbvgq
C5FOcBfBxvya5zrKj1XMgtD12IND4hentkE/sH5t1AYVRZSMxQ9hxQ6fK6DAVQLXaPJdYuREqw1t
55Jql3l8zdhAJg6O5brtOUQcZhQ7on8qiD8UhM+qRPlJ11alGXI9mkaTav6oCXBBJBx2ms7FRLNK
fulZNA3NVUAzENapSbgiOlyYDdBy/odsa63Sz5Ab4Tt6Glged2TUfHzQRZzSK5sKBxAW/PAX7jAd
BSaGzQmSAfjxYpjxOgngLWZXbyFkSFx4KmDqsGXmL7exC5fDDRxXz3lfrtuxPDCOVi+U+jpbRvaD
7ahgSIF9zoPW+Cq4dmnNd1BjdTmrjOoTntxBPwLNt8xQBwUN7BKHFauX2DXUAyt0zgwvvSWuoYBi
oxFv4YiRt82uxkilverkyJbnEdPmqQe/jgAt7yU5F+UZq4qaTH8OC44PUtP9OODcxPX3ziahPMyH
HSXrD1oX360TFM2uj1tskYHQP7KAKTN7MEYcsFlOhKtPUgth1tqIvoWXOpbmftqvXI3D91n5ZAOU
LlAiVYHLqVfM6tghchZNXEazMX9vu7YRSAug5oPObU9zi+Z0W4FAOfiTdgUBYRGXVJVIbaoGpTNw
s+fF1fu7jOuOkfJKVF8mPFrh1Ed9QLwU1K6yjLQuqKY5shR22FAqdqdcFeJThd3nU8d/3+asT28O
3dYvqiaZcLPMNTOADSlAkEe4w6KwvQX6wYwLs/Z8wjvBvdIussjj85Re1XOIekC94Yvs1ZWhJl+v
1bsQnNsgATIEg8LgGkxSXYVumkjZXw+u2Q2j15nuQzAfKfA/O5RLvVCIbg/ii1SajSmqXRp4vAYa
hsswNmizBMm8b5LF/9/q57Uebe8GupRhEhDl2Gq4kTBkx26m/c6AZEOGGBbPMO5dqYJdmRcFuPzQ
UXGrBRMqvCTnUYr8p5CZbWBuSc66tLZfDbmwkY3ZHXyinEHMXDOHVoCJtVfjhUO6YMVoXR+r5BHk
m4gibJE9vxrt50mScLvOd9jugbxOdS57W9UDoEGcxkyAdyL7gG6szvQUHimxtu3MHWV3sNdT1TKG
GuVszbA/B2pSi/Iu3XVEr+dJDJOrg1I+1VhygT7ihz6CmaQQNaOfsx0pVgvDVzzhDIm+NmaygZiI
rVacoEwHhnCdThiol0y/VADxlswtgD/5axoCIh5jTXVmg4ilopbrqbB13+LCUeGSoDb1lhDRSuJZ
JMatLteEFZ5yQdSk39Luufj5xLVufO+pRGqG8mU+x6+/b2BOBbvsPNnbIW99yFOGTxoQUFt6EUSu
/OgiVZu5lIvvMJKl9IFrcu5OBQiOskkFG6dRaxrDXVGdSG0B+NvovzQuRWgyOocQv6W9DxA/vT2L
qPp7QKGGFJLv8+rb3kVRwwhW1h+ToiqM0kzE8HFsb9XFuYYirWDpNvwAp7ac9EaURkjj8MLiV9Sr
r+o2UIEoVTho7sqkASKiQ+gur0sUg9gT8Azu/8adpifjXqUKUySUJIIo44UHh0SF/sl/9N5JjWoj
eQryhyIFcaGBMp0z90EkDBo+WI03qqLkACX9XgwHastSw6ZikjWC7LsZkG1N4ElzMHST5LoINs4I
P1X+mvDl6H897ckavaDjgt6/NLw/k+Z6TMI18ZO2seJb+FOF7Ibv5mOp4l00wEe53FOKqdOupW6W
Bt0l8UBJbXR0FkKF877mzrlcxhRHwMlHooKdjwPfuXjDTep7DelpRRQsfNmU+Hv70GF0fm3x6DxB
/DwmFDWBDRJfTcuq3eEsWwqJkUaQYaXzdnijCjEbuP0tcUMEZdKw9Evw6IOvVYr/a0KPLhGmu0bN
ik9FND9PA/MFpHbMX/3xBD/sUOdumRUsPI6LOu/wfQIacHmkMmtyQueEF9xuV6xt155vfSGlG5JT
r9oUI9xquGgVCHBr/bu12DIpsCri9Qo5BOZvyDJDYrlIO/7GUbIVuuixYRk1WOsG+zhu2uTe4mtx
z2KHg4Ep4s7jHKEo8u2VCtK+ozytBBffvTJbdB48bKStDGrCryRF4YRbGZJpcnewM0f5AXDekME5
b32HpQVfAf7Jzv0jG1goYmRI0Fd80wZxkxdl1wc69Yh2rNvml5oFT5n+8hFWtwJajoziCp0MKTAN
DTdve8wCdA8D+jlDwIijc9TLSwZVboJV5Yd1Fh7zk6WX4vLaaDPMR++yvWtVZkdZ2WdG5mb8l55i
jc7fKmgKiwlS1VgkkwfmDwsQYtJj0epv6UYaCoWzkZYyfSjyOuBC/E2IKUsrptKsahGu58adsY9p
klx8bR/LjahwY5QwCPL6kOho0S64zFsR9caoATju5qpxPqd9W1J/n/A1UleMW2ZsbXCI5+KmG777
SD3QfaNeuKAM6qVR8CGvvgUoFIBNUg/TXdXFH+HAh4nAkmLAEOGercxnHJC5oEsEEbsXFdfcjQDq
9I/XXS5CVFGylc3OyT6nYPNNAqYn1plQRKIS9Js4drkEdNoJIb7kG9Kw+8Ii7ZgIkAfVyAT66/qS
OxGvnx1hgRCsfYBXaBETu2fo8ZKFBOTcOAbBwzB0kLObEr8N00H1pKAi1sBJFA3GMsK1bUjzA8z3
KxSLNlPp1f2rl+plkERv0S5LSEhF/3KWoa19VDhy2sbWKHhHBpfm8shNsjPTOKzDtZPsgUnMz5cj
bgPh/cGnEY5qM/fFq8ySKYjvxJnQg+JF4FSs3Xv68S/cpa9y7rSzGLMf129YUmCgUJg5b0ffY/7D
7mgkoJwfhi8fu2PmCzFVEcgaQd7XcwxkBgGYtVipHYYg5AfpuaNkZrp7fRpniTFfgwkrpOWa+MOc
5W1QQg7G0q83TUH3ZjkFHiS547uE6VSahTUwealZ++NZ5HZkdbJfcgjwRRqBdF9XYqvJThHcEUSa
nFuO83YsDWNM7c9w2TGeMDRbqgEnW6qG6HZ/1Wb6JkC26tu477YUT29rFdN5P6p31Mb+X7mM4o9c
jRmmAZfxLkOqEk444KfOe1ohSAaMNm27rnOpgkp49fTMLaB8dYqaiAJm8jTRUNh84/nbJ/2EYhTq
zmtmGAggLIVciYXp72T4HIvU3QAIl3DLN6OOp3R3h3am+Lgioxk2ehy83SbLdf5krfUiSe49Uy/s
5hwKn3TxuNC245EaBP3NW77ItqhQYFxS6OzOlsxoZny6Vjmb/5aL3SNA2FCbN/DCG7bPbfN4mYGx
jxEZtbM9bP9pAoAse9l8eg644rSNSLDmQ2/ygl0KLvplWWmYE3faOoTEFNks7AAoGFea0fAowJYe
Ca6F30fU7H+ohpPdlnKlg299cpmdcPEOAY6lJS3NNiNTGfJOZ3wVgRq4q/a1Clo075Osb4U1dls5
t4wbQ9uDA5q6YnajrVEbpPqg1/Y0Bcj1ZgWN6tJJqk3/Ea9Smg9oKESzKolr22hwVgJBBMxJujL9
tUgpwl+g6eXAsfvVxjXj+KicCsNKsOfjGC5RZBfNx1Bh+3Qh9i5Ob4p43N10g8IayUv2dnmiwZtl
7XE0QF/RV0mFDT1NqblBxxdFLi9DNVRZAfdkGHEu2XID1xgi6iLVvodjADoelG10YQwwksrY9v2a
fN5SGCfW2/gDMWkM0GehwhnJRdaBjTCw/h27G8Tvm4OjSJh4OeydELreQp+2OrLLhcmEN7IjSxEu
sCRDKB0fYRJSp7QHHE2Eeu6Sgarmq9Dv6fHBgpZPyp8pFIiLDlIhm6vt8FM+ycLkYZPlSFtyCSD9
BP/glJpv7Y47arIYjYoTYOwufts3yq05vpsEQav95NUE7r27b1cxbs7bpkxfcq/ioBPTl+nNJYbn
ObExp8ND+gp1g9UmpI20+ifeDspDMmRmTKQQKkUNQhPuAqY93SpqGqfwz5tJG8db/6mc0KFaHL86
KnRaPYGd+8QVxrT3xcHziGnaCWssnhVT81ca9KYPcvmBG2PvSKl8cEHzQe5pHpP4Pk+MLwgR03pU
ClrnpgcThRU7hoAKxQK9idZWMRQTJAZK9kNQMhSxVsCFl74iYtDgi/iEVOe0oKJqRXCxj3mscCIL
c/Hw3COMLa1/3A4Se4kWKh3c6D3VOQ6feZgxEREpGmjyjRQPSL1DoC7PNnMiGWK9klR57zzOrj69
HP49a/3b0fAU5nW1GrWiV36KKbhl1buE9F3kScUv8L6xKvm2BgF08iyyc7vtkMMVhm6w8ivjxVfu
v/LMaW+nyQrLoDipnapJPDvgRuLUSX+emV396bLrU/D8f5fNSqSfadel2cmRMtxJO0Nz8k0pqXqc
dt0cf9dgoa+koLwAuoZdl6WgpZA/5uQfkVELIXdMmV/AfNzZL3wj/sTNNOXRJjeSUvXuM8092/RN
KoXJi/Vj7rSj3w/gkQ0Q+Zn2kCTAW7sMNt5TaVS3PatY9WGsSYzQudLZ1aDQZn0Q4wavgWFBI8za
ouItM4HXqqztNjbc5dfU4NmJQcFsN0yU889eELIDiWAsJ1XufcUI6EPCJr1+KsomQFoVSDY9oRUL
et+Kc3EbNWoXpSU/Rc1poML67IIeu9x8I6hNVNcwxpEHz5V5TzS5DJeDUOSaTEskfHH+bQVvF+KF
kPnFfIyhGJz5E3qjMMvGU9IFQ7/JjS30ZRY0ox6bTGUL+hTcwTqgUKHpe1o6FHwq9Ve4AH6p7gXe
RJXm8/HnhoTzrYins2ZWS5vpAgJx9chCfVZ/VOhOGsGYYwyxdruIRf1L8882ktlUbo1if6SJ42tW
fXS2SWPWBtKwaZ1G2E2KDpGLNA6AgmzZcJuIuGW/t261FXaW9issapGBYjdt32t4aLNUfjdB9lAh
Mdfkk/Fz5588L2Y210uMdggyBdXaGsXq7aza7cRaIu1OIlZatWlMkcQLXc+ZRL78lkRY3675ed17
2+H+hCOPfdUKjZa3eDme2MC+e9rWgIO3C12ciOPJLbRu86eblNNOaDC5NwiLqCCBeFbY08gy4fys
LKUc9doejmsQwR64kCnbqhOOSqcKTMVXswrfligKH+mliAcCa+AROMRATys4TlPCP39Gssn2A9he
9kOxLHs5ciF/6zAO10x0synIj/uECQTa9FDb/MS6lKVG1Dv1bcpHFa91xPyjH315noHco6pNfaIt
DAh2mGWsjDCk6rnik/zUnfHb5tkbv2pj8OXl2UUPxiKwaXBfCDK4/d+sEmcJ05+BhqVSHF0A01g8
YvYWV0q+5LQNv1MvLhPp2Ofp40C1BrcE7pnODuSBe+fDXZNh9Tsqk4MBME6i2QBa7IXdpDEpudcQ
LC3jRV5ujBL3Fdmk0vSVw0x4RBhIr0RTIPV8+8Za/t5jsxk6s9rjRhtDIuYYbvh2DVgz7KHl6dCA
t0G8XYYdVBlHJ2ZuTNGDUv6573RFkC7BGDI+Mia+0syT/6ew/X/lDEl3aSYsJfg7thadz0dH6d/z
/HVmwA7z1cutlsi+IX6b0PET8iDIT6ACGvgT1oo6F+p3CB1CEUWasomfz6aT715KqZ126oABBv54
c50qJSYmNFC64g/lYQKXPm41hHzBbEfIR5z2QnuLKsDS8R+6Up8BpKFr7mHdRr1pIt1ZiD5JkCZO
K7xG5gVtgxT4xpsVD1l3zEzvmwaJFTrMZU26pShYInxjBAMMgfc72YuxO7r3G7OoFWyjFvqT02gK
6dsC9CxakH/RvZ/+JTE/1dKVGXoFU4DuotSWiUn6i9TvehREcYxiGE67gjoMWL/7KoRGkJ67vP5+
J9YyFu7mPJaDdwTwkYUB927LH6l677dta6yF6xjpRVwu8UgBqZX/pL5XJ2jbviomv087u7vIQiVC
+mJZvVgtkJ/F/alDj5qM1Nk3XlzVtwyK9GIXdAHdfXmop1ZAguaru8qbx3cPFJc/k625FA7j5uKv
GaOv4lwuWvVlTWfHqcPQt/H134CMcEWR40bNJCEESjwm8TBgAPWyAE3iVwGXybNx9tbVc6zZOKWW
Dyg8DrR+gED9rCSjIi9MyKy6HGRjP5f15XxQpRXPVJjdv52EzZTV7/DpSqkfx4iUA5dFDoscgpl7
A7k9scGCQj04EwvF1sFekCDgxfDoXrU4UGXVjPUwAzT/t5+uPSntiKWZPYSy0s8llBBH/MbJoUiP
qQ5jjHyQ/4lLWqd57BQqC8yVcJKPE3WswKp7xfRvR5GeB2qOpmyu9Q1tJYeyiGtwyBHc7bchmABS
Ouwgx2euDuZ435Rkx4ckXfo6ezJGyTS4xVluTTWe2EGWfr+y8TcCsFlstRWr0jAc3Uv81RkVWThq
egflX11unpkKbGtXHQ+r5/Ig7sXFdDkpW13lMZl5fODBNRsZikBkNrIUDzw+BhvnYtxxTvbj7g5T
xrnsEmrQiePFhLTm+1z6+Uhn/i5RVoSiFNXevMTTIMHkL/f5YoZMtTaCz9bNOzHUkTHAAe55g8V2
Sz4Lfl4+4As+/667r6ukKNswD8l6nTF0ZgTPtaRMBouqVnNohmTkpFVV9T/XRV4Fv1BTNyOR6MOE
65gp4lSeKBYWDmJIsYjBqM+fzyGLaGiwx8u6PQ70hm68w4AWagQZGwD3DUyqezvUdMhePxZfvwpB
6l4B/wtZ6Iw/jNeSOLKjQqFg8wxzpt9RltS6Qe8Xii3XiswM3vCrCzB6wPvvV8mgX+XL53bhCAYb
Hu60qZ2fSKZs3/zRLmomZaZFaegPtxGZ4vJOOZjORsEw9EMlIvgzDrpD2R2BT3a407tBhQ3iXMV1
lOUWKomXDqUs+ZfzJEBpG0Pv4cDCtcuF/q7BKCX07UtEnAIozpyrEic2F9JiXlHz6nhbzlr/R65A
XWsjC7IX8XWFgd0ssP6o75zHRDwWe35EL3PQbXFX1B3qymiCSF7NncJ9zGDwNmN4KrSXCHYbXzjW
NMUzcTgXEpBPZUSCzZgQsT/xG9RUjHyVi2bhqGsgrHq0aCL7tnhCwhBlAOyjjp0XIVpl3sefN+Oc
D0v+sV+Co1QXowFI4XeH1G7n/jJRDebVFw4JJEkNMEJj7wx/AV21UzeBmJrqhEoqgV5SvBg710zC
JENvDN17jBEeSEOnUD7nt3VBQESFzgwzFv1ccBqFEPxJCnR1+eb59c21uE01LemWCyW84Ck226Mi
77KydQHwIcAhgoMzJHfpLxEy7nh/iWKVPTLe9Q1h6TZezQ2xb3+L9UE+nNN9RVrfogK0Dg6UwuCn
u/E9/71p5D/g2j86o/qwakrfMTMhIqRONS+GYCvHjN9O1rIFXQAlft/X3HWUVeboSZMRhPwQCPjY
PDLE2qC888DEOowxlnX1d3GshJgxWRNGb4efGcLRThpy/RqXD31iUvhzg2KF2P+EhLEg+Kp6yJIC
5YqGi4K38qW+Lb79loSIr08X2haM82Wke4XF78rPoMJn/2iGAgSlzsl/2oH7pmVFQCBNuLmDWS4L
f+VDlh3/gbH8AkaG6dGiuayojIdvCIOh53MHyE4Vl0l19UZktG+vxe2qRMdZa+KVEYpwI+Mi3lds
9m+Ou2F8LQofP+hq/aXIMg7Pq36dmwX/puS//RJIbJXBwgxKcYGdwuVYiww4ngSFwO2GOoAJfmRA
pw9HuAA2hAEpxU37DC/Iz1YtFr/NoRJdWo7mLBYK9z7BmCKQFJq+HSFHEUTUgnzfjPKE3gBA3Hys
/t8wah4b0WxgGEcOSMqteQpcTtX2XnKxPLe0+x3aWP10rAdzxSNQBxjRVzjz3otUdbYYcwjUjJL+
gbHdaCreczTE1NCWaFLw4YO6Gze1DG+kmFjWtgfBE3zKHjthAAfI0rEW2mxHTowVnYpzCrS521zY
CWqjy8QugMuj+brFO6HwNF1k29jmsWcJa+orTIUmNfIjkW8G/R4ydm67bwxSs3ucnE9oYLWIx+Ot
3PsiALzD+I5L+OHLGGyalF129GajWRCVHcM3r0vkbQPVz83cyVD/0BKoNhVegWFavCbiD7fC5tcY
UgKDFAGSVC/CW6DI4Yx0KkLpwGYpbR8bzkjBcrpkQLd9T7Aqls8QJ5efGSIc7nZl3xhaCXjzX/k7
inDUaj/7VzpHDmZ9hE9K4nfQNy96ELftvqoghbB+GYGwJ7/lnpSJdqbdi4HDb0mFA4DsAEhvMjOb
GFqeKHWcAQ2wh0PM5fKISHtvQtticgi7BrnQWRDxRU07aQt42RqLAbrBp2d1GKTO0zZuMOQoytfb
uWoA+qNaVc7qEvNh15Q5YphXjcbzI5IVXiPa/a1W0BBPCjYEBJR2p5SarwGSoyw+aCr1yre8TNFU
og3lWtcbNLXmnvsNtmep3UCSIoJaHGQhRU6z4dK6NBPTEvT4E19YNXMJabq4mnjA+cUM3fNtKkOB
PGeiH6HHGsRyNkQeB5t0QZ7pb+lHc2JaRJbyWrxpBUkleRH1ZDn5TMvQ9HaBxvkuJhOAIExpdKJX
6wwD2zcUu+m+HX4+B4LnPFvECYO9sNn6f6m9gcQuGQ0gmynqrqspLHNagdgSF6viiCGOm0zlDt34
kaiqfdOLNZL9yejVdsB+CTjkMAOuaN4KppmOe2kwL+fEb2DgQXb5UPdzqLXoRWvC81EfXd++RU1x
hMdTB7RcFCOOY+RHJSTNJq3aRUbsBZBEPiFbgLgJfNeJr97cdiqNhm/ggDF8mz8f43dekMiHq/Hi
YOrAcHG32Z8LC8JoChdE91EbsM5QBe/lNrkhFbOEEMeogHutonTirlRa8id5qptzFmnNUlJmPhXa
fZL9OJQfOWXDEJOKLiy+tuMGO+EvPmUIyD4QDH55E14eM5BgH1iwMyqjP7FbMprB1/auTkZvISu2
3ipUcpgUJwCQyn1Brzl/yw92D1FTdyoLnkGWXa49KW7Ev6PJuGtDWGAtEz54E+GZBtWSO0UKO+us
a6MlUgDW8BjGmuJwMaF8jTbt6g+9yWQlQYnD7bAL7zYwCYBtMdU6woUFnmYTF8mR+IrvFzsEf/BH
Giia0SZgSaYmyRA8uSVYZsMqo0rM/VUdQjWWa71bWnQ/jORqlZsDYXALt6anRP6vc07IgmZpVIe/
FimTqLZq6QGFMoThtFaZf7+jiFc55VPb+G66wwG8Dmu8/goT0ZBEKZrag1PejOPXzXYNYYSUMyPG
B98DSNcwt1ujlIFNfASblZAtA20P9WaHL6ED0B7Jvdxqd5shY/MThbBYWGDuxb74tSyHRGj6pfH7
dr7FDQPeAvCQHmagNplfGv6QH5m6s+yQqQI1TxcaxCXuXiBJuUSFaq0qG0EqGbBwGMV6Nu9hnir6
FG/CB2CcqGLZYmaqDPTYBwyyg31V36aX5D8FsoPeJr3ytw8JU2XxKSFrK/Hog+yMiYjTuK0Jw0DI
kMX2OtoQweqkVDsvG2LCAPwgJfwg859gW7fs7Lw/V5GV0MvP2/JbPx0DiAPCLwRCFDJsVtWTFF8j
lYK8cZpQzSox7gVjSZTJ8OnQ4h4O76RYIVpUmTfRdFnqN4WKUkna3691JlLkp/xgGvt264LH1IsS
BC6TRtCZiSQgXWgXHDYIhh5D8xcsaTJA/+GEn2WeRZw8xqKr3GYBV9qPL1RZk8THSGl1LOE8XD7F
sC6Os/ddbQqRTuNIuZUq19Iak2VmpQ52wV4PIeyhpJvx8ldbIIAHu6dI9gQkAvGxKaasumhkAA6j
kGgCXhc7j4em5H1kND4jBMngLz8ci50ZCWcLpJRUWz6jLQV/3yJjSgNwfBdxTwsIqhhLsIRqGqDV
UQH10JodMyI0MqbuL54HJJF93Gsuw2Dqm5RZqmwXfHFPV5croSCjGds47gNNgmaKabfc3yIptu/W
LLZg+NcdmQa0cuVZmi7R7Ga6cjeoA4wdX+PhofRyGAwqxPnRRMuxjL60mO8terAAREhknH8g4Xq3
XJLusbkVVM3RW47l7koX6cbslysiQsOt3GVhRla7Riuh721I3sgimkC5ywQLsalsMr4OmKRU/cUA
xJ/JXJee1GrBtBLrMX3Fk0uf4KbaSeYsCYXaL4Cpw8omoAdc/Icy4UGSnKmtrEw6uy75EUWgL7uH
ncdgJ0zDNUgJrnWbKaC6tU3Pqjw5BCxtgA8kleHg1xb6TZqf2jsnaZGe8grHEquioLZzZdZMBOAo
yNDqtnmPr5kC570BMwYIcRAGsyHMCnbYkKlfwBaDBElBPV9Y9lwqMJ0TCuXlqYFEdiS1bqV2gEu0
nAFjCEyRT+k9A+kdjaKVXS3ghYdz9V/77fTJKJkOF5iYjb4dT7/xntmLNTO3in0XBkCS47YgQizJ
AD3wV4vsuf3q5tdOpFwJCN5zr3kCmTLtmLc4Alsk4c8Qxlxkv0+6hw4JB7SaLPQIgGcpAgaB6JuJ
1zoixB+iyzoBBDx+jzZ7TYrw74FHpyiZIve1QR8goqbe+eSS+VMLRd9Hxa8YKYd7yZfoFoW8xv1q
YvivlyN7G8QgpVcD6Fnfpd1G42l1l/RTH55B6kwI8j5F5n1RIdM1382Jx37qu/6e2fMIVoShfL9j
h5xCuphkthohAeMztvTxdP5uaDtxUTECsFrgL0XmXDiGPbn7NHSIJVHD+5gNxRs+75qLHf1fE/v5
MygoYNaqV8sVMyj9o825RYpnPU+jx1II8rQNJ5pL6MKscaGbGzVHZ3sGKBYyw1fcakLODZMlJ3gV
r5irYePE5mmGpkQ1L9n8T9aHT8lu+yF6cgYzKIvlPMMtdmYFTAgHAab4eVAa7eFhh6c7CIvpAPCF
MepHvCBJjkb0jajrCXoSbbAWRO1zu/WmxIrnRq+Y8q2JbT2Nfv6/lLUV7X2vEDDEYoSbhMVlU4JG
biHeockagNIhZJ+oEPdtae5gLJg8rV0iZUZxjJarTGxwYvnX4FwLthvGLxlPIU0Fv0LufIjGrbuv
3JtE24FfYBa4pctAEnbdfYCmEreQW3Wwm1e+KC7pDrDWF+J99wIom+hMlS4QH9+CuVhekJJsmO+G
udnmoRxdhy1WGLrMO9lnGFeWUSafY8TUyew/EaND2NDUztckABfPLBQBqZbv6OhcEMHuJcTWeGEc
sTgkAfAL6b/4137dFZ7+gu91KitajBvDCMIZZCMzkkJPd4f4wslHVxa8ScnjlqSppcUDkJdA/vH+
TF9eDvqF6isKngwsZbioluXQT6r4zMkJgV+Pkw0lLfVBa/Xt2bqFSZcye5u9p6WYvL9q2YZpSa2/
YWM5iMARoKJnoddcdBK2k3YDm7YkB6zEkBG+8iWfEoAkhSMgQDtreOXjJR+KZYwIzm8uMZqkevQ3
ESPFyfjgm1T7MdsmAO7PA8CDZ3e0f6uJ7zdxyVv/aFlvx9E333OqoYZg7gzbH1hvdFSeGgF/OeGG
cyB74l9QI4iNNQvp/VBe8zgKTBF1cmBTwq3apd114yyAknkjvCYXBH5QcPF338OCCj8qexlUrfNS
9zY9vH1KNMEpVWkBpzVooQpBchszKijJNLeqtstD5uW06vXODtoij6chiA7uSIbEG5hANWXYgmfl
imnSGXvBJbLTuUF7SHzyxLw8MWeH/YZdU68q3l1G9X25HRg4ua67jK9rVnZHzVldvvRt4lp8/sdD
fszcGlCska/Y1UzBmWYf+Qde83UTBBhsH/WU5QK9TwB4qwtTS3r8QSctbP94ipeAlj3Q8tp3iUw+
rOsNHA+r8NJnu22YjQsgZtc3QvKN9cJ9amqsbIhccW7q+o68OkEbCl5J8yr8y0TC+0Q7u3TThQ1r
u9w0PKO4k7WGYW73epauEB5nQhNi7bcSAwrERZEjkdP3mn22fL0fAc5gaDadDxq9rHsKbKvyxAMI
HLOixe1LyBwzSBd8XtVb7cOTpcocF3mum5SHRXDURm11V69Ko2ATHrk00f9owzxuPeFQoZeuDblq
eEpavpPMTbNGypYiwrSoShAS71nr8jF/qG91JqZ7q4+0qgg77lw1n2zdVjwtjvlNF2gwTQSIjaE2
fI/ot6KEv3S8ouhY8+FVeDA5uI2vrYRdNsi+p41bHcFzfuUmoFxRzKfpeD0jRulD7OxGNiI5LAef
XpG5exM/V0la4dDnDV0XjnFyHC9z+d0jnxdByQWu8i3vlpeVPYJg/BnQiLoPV3a8wMdKsYlGDWwK
ljA7aCC4vITOtodC3GZCoCjj+6lYXvXle/SjjvBWB2qOk7syI1dW55woaQ5gfHHRghf+xBCJmUNV
/fiyqlmudJm2Pm2xLSDRVyCP19ETQJHJfr9ITIyLIdUvhfsD9XwQARrKckNAnn6f7rM8ELMQcihn
TlIJZSl9ohSDNmYZdPAWC5t7+HwttPeUJgkPUQapQIGs+vPe8PD/armazZqW8XUgU6m01CsCAAib
v4FwuB82oMBwbWudps/E2jFa+ANSFfVhBqwA48gWvRRT92Wms0/QT+KNrn8Y4nOPSETWfrGXW+i5
luEsQQUYtYwk+OacuuSyJLol1J6kWUGsBsty4xbGNrCf7UaG7kHOEmd28Ti+1qTaPeITWH0sWbeC
RIY6udSS6SumTh9TASodLPhWUeLDMBIdkT7av7g1Vm1IXr2xsxFNiIvqrC//KV6OWEJD97WhElO/
LdWYbpUaCwX79z5uMO1tGc8n2qT2RA/Y0gH+KhI+gh6f91q7PFrcXuqmqMRiZnbVxVVMIsYDS25J
xG90uLhXaqsWE7RTuK4gypqu4EtubcrWJUmxq0mOmZ4Lu9z/1iV4z3b7jxI5jZ/K/wHweVs5Unzb
3wBPM8+7wjumQbndUGp+Yojrfrh4Fcw1gGu6Cow//YZAAzchQziL5DDWw8XF/cADnembdfmMJGRE
rTrALlR66TUxPJTHo8SiJlpXbElSrN/THelnz7WYXiYzPJbs+I2asNzPvLT6ZTbz8tiUmK9SEEZz
7qK5HfD3eNw9CGTvVprDQFHBXvoog0eEBvOlTewF4V/6OQkrz0PxHaogrbEtEwRcE2xi5Ay1ttQG
NKzQjvErWFjHRuuYoLPghRigI8jLsKLiYJ+Z+rD9PwuJXpXA6fkA89FhElihq2PgSWV0kwDxAycV
cF3puQ07SY7zzAPVAdRUI8YT/37nVsnhT6428OC+6IceXIYlEnW+/u6uPKczPbVXQfcO9SS89wzT
b482we56q+EgL7m0gMi90o/nclGSC7PiWVEpTgdY8eGG8Vlc/eucANwxrLOiQ9xNfnNISQZnrsSt
6l12wooYi/8rGzbuuZeHCCvIAEAmwFYxvB+ioNQt3I39bDetq2MoCFttpzUPVFtZHzUzBX2FUHkz
UTpg60nd5HWuJ1a8w5Ni0qe5ip7boxaeo/AtuAbMtbnZ9Zs7CgPSsUeXM8hqSX2dUmL38otS+hvA
WgCZov8sS1l41zGRsezEse1gQhjCr86boUcHQn8KpVlK1rVMG4d9+ymdbIVE5th6/oMnfDU/OtM4
7laVCFxlNpU1YpJT//gpMPinJmXUXlTeGYYBdpuUmdRJ6fSJHq7We16r9jdSVIUGm++sfKz4jOtK
2fnJrV9jIRI8Q/UnSxVI/L6RviDpnT8a52tcp0Zrs4MTDgwUK98vZczX6cV01gg39ZJRjgh0Hs/5
nsTQxFAixWzRdMiXUllccan26fAocGpGGtOv1k3x9BcjmHthpnn+PM92i2Rxa+NFVJy13vw3KY+a
cSjXDUuf9azd7ztvvb9TlA63WpanTp8Cc6AEupXXVJSemz1YZ7tizLx6QUAWFyCyuLTv6h3irC6L
AU3eIx1NDWYkazWamVfvmjNGXd2g9b8JEG02qKz2LAQz7NLYoP0tExa4Jux0xduDxsAX5ko0X6XB
B/UNPfSEmeEbXi1sNHNhageEi9v4qSFY399Nhw7Taileap6D+qU3o6E+W00Pgn3cbTAUDpF3acYv
YAevb9KB5e5QoltA7s/0VRedBv0SoPGW8RhwfBj/DWyUgvb2V+LC/kNV/NCPxaYzfOLt80Pi1WOu
RjWQsm065Xry9qe2gcw4UMDgIfnFgRPPDGPokmfDTTIw94Is6ERc2IThTCeXKGt3RIzd4mok+9ow
2VT/AqkAnw2YLSbRZ0bfZms0H9WJ4xlu6ycPbwF9P1Lm1HSG/ukhC6pugnrFz/mFZAn9B/n+3V1q
CYrbzy4UaDdC4E+iV+fOy/IwR8Nx3hNqzp6YfpWvo45Cy6PrE952FsMSfNwLFehu3xJ0V2oAzBke
2fTEjn77BxithiBYGdBm0jYWZnofRfcPVubB5tHO1MtkYuB1GX5bK2aK+fVjFsmi1/IpurTLieW7
vPDn7YN3FhCHMutlmjj13dDNR7THvHUEnx5nJYnDBKz1Z1I3oHiEjS9ilOuqdL9Y2ZIrKpY8skcn
ytUjtzoPJjDS2JxTskZKe4vQUyH2+Q1blWI6kMIHnOZ7RmKIteNmUY6zZhKdbaWjqLJOql15CGEC
chQMsKuCwZr6BZEFt9stWBvbGaQGh080RP2vW7I/yzrg/sH23Ge9oOFeCXGhZHR+UGj91RdddD2U
TwdBO5nGiR/IwGW//suXGZNiRP79XC4j7tOHJAmvs8+zdAAF8RqV2K3hVqoej2eSf6E1X8QelTPO
QWpVi4GWvuNm7MCkys1LOAdL9EgaJQyqWOBd+8R+hqdC4kEgFmSEw2IhAnU9Go2usV7Y4vFYVrx4
VgWbO6L0Awfuultog2aJWf0TVlqFf6TDBIqGR6EdxQ6H7aaE81ldnYsbRLjpdLR0VbQQWxHAXYP6
EY47K/16N2pyJwwRa9qMiRYPESwKAcLilr5/x6zHScFzABRwmx3N0ElLD47jAHrbRHxuYU6mF9gh
LQDZfNMd7X9m8eQYP4aL+3DQvCbV0LIhDIYpDGnCFhmOUZ3fbymtDbcsy6y/0/OADqif4mmyRNL2
nlkGvnZcZXGKwHzMubdJY6p7is2f6SQg/Rb26ZJHIP0OQv6ipb2LWT2pYdy+KSaVgzKY+iOpWGfJ
nHu9133dp4tl/cjBnFVju8+dY+leULbNxq0/DgmeBpqZZflF58sSedI9KZsju9MdeAa9TpONCqh8
rZfb+X/AXMKdN43jTaZxho7wkV4RnBivBwgTrNjxptmbmUNnrzQNkfGRqO8Wn6fsULTx92gjEAEt
++J1U3wCkTCox3x1TaYteAr+NDUVFuaZvP7APodhWxyfrFVC9rfAAEHYQlfv5YidtGvFzqyOEjK8
aw2K8FU3ltvqczEqEa+Oc8TmEUaJiWiRZn6XotM8pUGlRryaikczOjhNuGlWn2/6j4IzKpm/amZ1
7wr7xaCZeKocJTcY6cYDLXsmUs6uWdO9oz/frmgJzM20eaubG3EcZOMrzODR2k6i6hlG6Rcrz10p
CpAKOroUsC3BJAM9IuoEc3pu/RPb5C4WkuZ3/aTNv5b1NTkbzxCAReUZUoalkezD81dI5x/3iWpB
CJX4/dppazsH8x7CXvviN2rNxNiZumvYcbv+r9Ln/TRtFaa62OOWwbrqX54D3XKyOx/hwhQ/QQ1M
8xGRqZVC6jX+4CzNlapG5kX1CMDZ+AsRJSNQubLnwAWKTqOtcfAHwL7Vt/9n3UqM99tsr7is5+Mi
PrsElfqdtcWEtMJXpGjgFpEjBGaDeZy5QWNykmlTuijLxqhiGnqTc54URm1yVe5e+eWtmKPUD6gB
tybVbv/300Q38FAp1+J7vd9E5pq6WnszG8DBE/uGsTtkk3N7854dYvAcB/SqcT/Tf7+sAJ3NXgYF
FHFdChJ7SENbmbPvurmb1nqzLGw5va9GMPNafdZdjPBnoGPvRmzG18/5zFwFNF2BmmvheoCDocTM
kDnNlWMh2j9LSH5ZUoxHD9XceAYmWd8/tBBkCkMtl8hM09gYCen4iRO6r+y7QfAmLWfwC8FkYgVq
FWaPzihJ8jJ9fjMs3VMGPQsmNrJFW2GzvRKMPiDcuHi8YawtBiBP+39kEDw4ZlO39Yfekg+UAk66
1X0CFBLwjboSqeaU93exnEoYNPrlr2gnrNN9dIRFWVIxfdE1CDX/P1bcvS/0CMwU/IVKJfXfxun8
4bi2CT6wTnkskLM8uIqvnPaa7wpAoPC9lDJotY3QzwyGDhk7Y+z47cUcesUDGxVWz39+D98NX+pD
aJ8iyyvHaitnmKkywDCpUPBWjOvNWXt07Lq+wz+CMAWwRZZ+XEfgdrU2XbPGAfbuVyoD7NB8llqb
sLLUnB8zdVV7enOoEgM0Cdi9VF9eP4lo2aGXz9yd8uJDuCOOuIUvrunNUnsJma4LHheCAwU7b8Ix
w8ZmlC1cc2PzdZRtZWQUS2BeT8/5tEl5fl69b1vfgFqCms/6bDa5PV13Uyq7pifC/hpseyazW+yc
cybN83e/8BuwmHgJDypuHPtDsNZmkpp4kLouiBLtWOovsmxdwuawBa2pBIFyohWBhR9sxmGvf+ie
njeKarNBDRAZhs+Yj7bqJFCHaGc6TbEso311z5AXpQugApAxRhbx/tosHoJN6AybyHr0Fm5hHfJ2
PxTJFgRDxiSariMl5g7AOqlK87LGN/ILLg3nmex3Vd+kejDTt7F5XI5YEcLPz9Dv3qPvne7GcH/h
hT8nxiWNXWp25thgjk3EVyinCaIZ/9guZHclVD7i/R6jnvBo4lErsIS6xiq83WOCEBJpco1RuNwN
vGwiPQ5KLs81vRncee39Rbss3d6LoZaFj1OsQWik5iun5gHmlZJtWzw8w8+Y6XjCVypWhX7Zhmti
j9wd7aONcDj9QkgMJ58TbiDwU8amrXPH6MdnYg/zTNXRpj2RVYYS2xEb3SeQUUsT3Otws4y0W1Zl
XBzySwv+JAey3Ovq4dJ2sPiSlvRdOo0CXZUOuPu8DtJdNz0HCLH/ItzZRFrxbs+CF22vAkEhcslH
G1QmQZ6GWqP+LEkYVAfb8DiudWC4EArmTMOhtDn+HO35vVZt9Ecad3MSUTzF7Dn6FJFL2eAA1Wyk
RRYiu0+VyCLJUdNmbMGWHNQsNsWTTympOfRFvy81B+o3YkmRcYzon87YbnKgosMs2uMu/sx14o5E
LoVR0nNnFpnNCtGcT+TXBljTlRYJNxwKvs9rlhTd2LfxcJ4No1nK97ZrJcuEtyipoQ8ddORj9OJL
+XH6yHjRJ+uOAf+hSJQQ/O1bmB/sALRFdL7ZB6eW4l5jYUlppZPdEt3qt7pwZoz6uk2+jPS0zk+h
5flAPpJeiJeY3+3uY+cQP0BcSg7P4wn3hdCoytqQkcQVU8LYgQ8TeBZwoHcUOcWxtZrvVdZwMlK8
RJiE4+lO9DNAnfZa5zNct1yxopuAOoinY2S0dpHBZOXYPsElDmgRZ9d0RiSMiFhmovSwQQtv/eug
WSHfVvmHExWRTob9oPnkRwwII4qcrgxqYMflM5AqoM1q+XUhCStT3F9nk5xyvhzvPj9uik06Ajgl
hXkgQVWbdcM/uU+rkiAH1vJbXDi/YXuN3KwwAbjb2PCrnQlczIgEPTe0c8NNLcWKMMGc/lJxIFGk
Ze7+NQJ0Gl8FKZr+pEBFUbWY62NG04M0oHB5/ATnBDVtHd5vQucAoM3S88F3s1KxtxcsheHBAOEr
en4PsR13QFKLl+0RBw47N2vlnh7N4ay11Dk0E10TiSCGcTFDtOArbzhJ/gUwmgSw3y+m3HkUWhis
pb1knNPGgCrGCCUn57ZXuk1tx/QXO3n3zlcBjuMBHiIyjPN+2m+hvR2xz0+8FpVTxA8PXRR7n3Jb
eC1JBKdFN14GrrLnBR/7DaP8j6S6BnPxQdKXBs0DE3IpYlRjYmPXo3+InshYNhzIt+jAmFN604Xq
WIfVA5M0V4DBLErAqKdO7uC3BMZUDmc+47C+unKGuKUX48VKJQx5bY8HjQvJS4nImSxInXiScs2w
aAjNjByF4E/SDXV6YSun2MQW3JqaP/3bDT40MNhJlhyRes6rCGNTOhkc0zJvUmQsRliTyQC9/xkX
F4DhDIUew6QCdv0rvKDCgu28vgGiZ3JU65IpDgMbS02HZjNV7aqXdiocaorGi0RPeASWnCpJ1a8t
9bOzBElYJEg6R837DQq+X+GlBCU0uPEJw4qATWZYBXpkjnTGXwQEQKze3wCB9LD+Ckbx7IlM6XFK
UdIJD8VI2+mrlbIUCVNdUx1WU9wZS2n/kZG6Tbpk0gTOVEez7DGOLJeEbGhjUyHUQmi9amvJLyN5
B9TUxFRCr8b0BKY/Ld9VXWSZcthXoQfggdk/q7RC/aSNJQ7HewFxy8TJisAzcfmOSlh8PQht5xkS
lAsZJPFE0P3nR4hiV7KQ5C/0vCV0EJiUM3RytFS+Ct2dEi34CsRi1BvShi1inJufI61xOC2ucxVv
LaL5PE6zybqKzBIWejTxBp7LBDNWr9Rh1kxGp+/8vgPRtw8Rg9lF+ZpjUtG5x0Q4IQwq9tNV/lQT
+rxRoX5SMhDxWkSOppaQuKwjs/vaJ6ys7VlIfCo1oHdYQkBNA4HI9BWorIpSrTEAuEjlfH7D4pPJ
+M0zSbWWm+cedk+3EgG3opyB5BYGyCH4nGnL69h6RbS8ZZL7NDZ1fbSuW3aHR8bWBqqT8cLvseLu
YkT3TMLpNoxi8ZrqMfOF35RFac4oJTnBSl9LrwPJ1tB/IYw6jZRgLjXh1J9HY6XD09d98d8PcGqT
Xpl1pwGkxtScP0x121OhrNkfQkMDySOsW3DJ3K/8N0rJC27mmqY4RxnlE7DlZT4QgM5SsQ7UCdSS
crzzPFGO+Xb17kIQV7ufZBEiW1sP0R2gdsnAr6JDpPWMlhORQK+dr7doU4112Afb7N1wBs0aM1BA
8Eg4xof88nGyBDk1PRxTxt8XudISPHki+2zbfXCDa3HmClDtfSLs8Ru4453YIJGla5aJCHPHDuFn
u3kWHujzCPwv8y61PYfJw8yUXN3oXYrSFAn6L5z0Cj/JssSi9BrDefY3RpEhB1tSrUjzFbInKX4y
eJQQYbrMSJy/sMohakNn4av1QZGkkJFp0k9Dkm85BqKRw433Eeeej80aG8ruJkCseOts8w8w2mdq
kS6anLZRByTVQj0ukQAHWYvh+II2ESAtSjAip/4JacwA6G00GWL7yBAxh+WGP2nV7neRSoEMH8np
sVjuxSXyNtNs27sdCPXnAVh3HK72NxVIH+d+WCQ7WxGtoKQE9XpUQxVnoeM8ti9BzRlxeAxrxv/u
Ge96PZm3YuXsqhwHLy/akpXfqrEqQVbM6IFRBb8XjN5ppEDFcaIEjYLMmXolL6YUkkF8QpdjpxH/
2LBY054ebmEhTu3pv8Z2aQ8tAB5eZ1BJlICCZwHqrQgPx6Ck+YJ2Y7hc4MANUWUCMOPmLPwX3EdC
WBBU6dcJMLxX6pne8L79k5wYpV0Iz2zC8c/Q8qsbsvFwLHFps6qnJ74yfSnIbRobuRhFsZgk0vWl
Sv8wRbPeaI007FV+2R48LfUttJU4RciM2f6UduZ4bgYZ/KZfnCx1LOL/N5AB4UOJrbw4vuTADeo/
oRY+2UEqxvGvOXywmUHWvS7HgcwaLoXkLlk6pWZ6t1RKiYyk9BMyOGzukat1mb5OKhzHiwvrplWu
+d0COoAzTDi0pHi6H83ZRyuI5owuIoYvcX5qOfrbuR+THPG00Tg66RAOCKhtAO8q5ui9POE1PQ0z
oaEk/UYaYIT0oIPQZyBlhxEGabSI0Yi1ThfAWXlBEK34d281XCG1UsqKd88sUtZXckN9g+NzgzI8
m7BNU1konExfY9eEa4EGBdIt0QAhe4k5iJc+0/P8/pYxwiHt9yoTLTfD3kEXAv2CnCdVFqvIcbBt
jsKrgprqo1nrWep9d9pUXk89t6w01zRJpCbQCBs0UvOKG1UVvsz0p1nHU61VzGPP80s1pgMR+tYA
BO8gURavODtH2NA3qYd0Ol3msMWvbvMcfvJloHdwGJLdtlc8QIasBVjKAOBjo2LnKHEBucyObBWl
OntnHPuLkTCCmK4JPFTYeueUXnNpLMDnfJuCaG7bM0A7rpC0w2uCuTScNwJQuAZvMWSa0Q1nobfQ
D+7WkU+5z0qSUdC0POc64Wjzul5XrYl4SUdtbMz3EIKCpfVqAdK7z0Q/BG8QNT4U5Pv7elrrAL5A
Ao8h6+spj132f3MyffmR84g90oz+Y+RMR0gdUDotmEte/JDJWikAHZqcpVTOyBOMwnSJ8AIAgh3l
u2A5CnWqbC8W76HveJhItEdOolFTAoKUknc5u4Lxy+DXwT7N+FrlES9lDcndUGqk5b2eYFTRxExU
W3fMQkSPdl88FqMQjaNYgqaGXLb5XGQ09PL7AGsm5ROiksLjF5q3OPINSIaBIxOawPXVC1sJSEED
yyqFuNNqTpp6ojIl6PZuPsxXoynlCCd32ZXyBZulJy87JHT17pLCGws9jiiI05eH6/RdgaVJPb4U
iyjgRjG14Nz7dQN+ZlO7HTdgCGzzqj8NdQ4SJLnE2vNT0m+iMeH/Bi23/zkGAHAuxcJxmBjGV/z5
n/CbSOjdxLBT6P0i84Z99o8q0Hb+T37tBPP8Y2KgCfwo2il5kjEEaMkpTAyWK2OAK0SdGLkykTgm
imDUDN58uIqesnUzwg/2GWH7MWuRi5NKXATPbYzjTVEwV2n9z8RAPYAfEmWz4L3Y2qx09l7ihvKf
ku7fNlj84+4FQcJecD0VkbSIJhbcL01g0hbOGe1mrbMM8s9I2Xmx9H5xxI0RgHSSr+b/uNOHjx28
yoN3HcaV8+bfDa8z7fbOf5BMWd7UgYoBz7Dq77KhcuH+8eV7L1aImYPHzaF0TfEbHHFZDzevHEdH
6eREGiEuIjPssNVOy42PMI8fcrhQCG93knIkjfZJXFM3Wn6HWcsbOFU9kxajecI443y0xCmtLZti
XpZ/qO0vl+Y8O43iFblTNJonBIEM7UBXsGcbQATpF1bJL2ynNfCCp8KaV4rMa+Zc+c7hPB+e8UEM
/IyWPhMuCzu1SpIJfUWcKPByeOGKqa5Y9NQG8ctu0HUgYRIsJqg4w4dnW0j453yqMNBFqDoOsOMM
AlLn3iTC7yT4j7xN4b8/nS41XxJtIeOODkJOD7NPdPwaSZ3seglARhmkzIynP7tsDHFevfrntdIy
/51sQjBmaILc4eDfZspZteP99HcyRVlEXKmaAkH/jdzciPMNqZKYReOMfRRYXQvsh+TXR/QoUPH6
ASLDHmIc7QFt6QBVfdBhHFc16/mGV0SQvJddb0C4QE+Fw0e5N86UzzP+dtWiyA+qrZourdGnW+PX
6d4rgsyQIjyUTTD4sHHEBISLvxs8BBeHqM/SYsOdenkGKv1blNDOerqNjr3+Ocq1+9JD8LZBWBQV
2Agk27AFXtJfwutDYu3WDEr6U5fYp2LFEUS6+e0DRNgwVQhmtPP0HU7yEL/SvVRzCDuhjorLDXuS
3boPcmM6cqi8ODnzLbQC83OEqxISgFXyrlb799ZSxEksC+7FCSDE4/JDGdsGH6Z4/gSZBBvRlSr5
4JO5ENSNtuWrdL5nygcHHSQaHRK9bqCvw8de2FdgvYzZd8cX1ztppL8C6ats5So8DeU6xhcjhyEn
yUMBUlY2vkV/gmBNb+oQ9K4Mz/TFLzYS/2+PH1Ftfovx1kPAx4E1nHCWv89iFAQMCFrZXE9OHUUQ
m7ejrRcpKfNXYd5cYEY2RtT8w8bpTiOkefphGpmdpuEHJLEeDlknbB/JX4Sn4J6bLe27hjDFgLOO
yAXQaibHFZDM81ycHr2c8LI6oSm9k54jSY8K6KhQrECibpJXmFrPshC5SkiSe8eD/90VyxyNaAjS
ydFehoGBl1EWp1kJHfRyx6IDpSYDZ4OmtE1+H8tJr9JcXRvJ3hGa7/oVjFeXFM5pwTqeV0L27lx7
G+Kmcjew+HiQC8oe3Az837+63J8eyqAjrs02ELcJtK+NZgwfXayQXUiF9HraJ4zuWir+/YCqNLi0
UZ14YOnWv+uEpc5uTnOH7yXMZa/Ppf1ZEEdj5jt35W3IVoX0VxwemeALaa08KfH/3XwYwNn0Mb5n
JKT8WW42pzxySw2b2vBKJm6nMqopX/kIcWVzVX/M+pAvWtJjnW/g8BeuOXErIVt85+YHAR0KxEuF
+7+RWQ2optS5pS0hDjaS2bIb9RnXN1E8jBbGoyjJ21el2FR0ssYkI//RKvTqqGe9dbpBkWOaSALf
tUq6nhUdE/S3A1OA2ySNsO3U8BNcy3xBO7CENw6r7/UY0M/nVS01xlipDsYmK9Zn2FiOUbcaIk9y
J3nmKI7KVYuTUnajVVRzCK37MXwaSCholkxkEJz1XIpd3I21NCKPD9/5I5KbXBFGPMzxHJBlB4AV
sog1Z1v3Cw/JItfQl2jamgKtI2hKoc+Ueaii+LajhBC7pw7Nkc0SQUxGz+z5FpYVCFURW477kEYi
az5WKAXr7NLeM3C4WiAm83Lns+b6hB82b1mK9z5CSisnnHYVN2eS7H8BCdyDQEwQEtQomZM9Ju8Y
JXzvybC8hG4OvyiJ92bQtCtS9F3GIPmB7RI8WHSSCk8AC1GxQMT5rAxBkmJutZYj+AvvB3lvspNG
ggcYrlPMmODS4OHBQViHq+1IptfAKlkS3PBZFzo3QlapOZkUdO4PeO6p4SKp0srWQ4uhNQmr0lPp
ISxXObw62hvzkvRTRVCwAegi4JAo8fl64rFSZKxzYD3ql5h9KCh4AzCIqL/a+hTYh4We5eRndUyi
FKcF1aSmci2AFYD6iu/u3wRdV7iRL/dn803OyECOdpfuA4AVQgUyzoIhBbh0RRQTTCUXlq5A0Aq6
EAjc/s10ejXdVLVBTaw44BA4zBdwfN4Zalfft7s+DheIqXoBtfEJEvnIKr7noIryHRCus8FI+7/A
9+rJd04ayelLDU0puslPP60LVcTb/a7dRh2AbV+OiKk7Pb1FSXxv/r7NYfdCLBX9GYlg9H21KZH7
kq6+tGNo+EK13SD0HoRLJ89PRxB8bwj3ykmkdSk8vbMMubC7wZ7ftQR+YREJDS/fFdSoGyh/5uFR
+rjjco8mu4Vd0Z8JfHk7OR9pe7EmJiYcgHwvqda+hPnPwSfCUIxZ8H7NC1haT1tjw7zBHYAxUaqg
is6Qu3jbjKcN9ZzP5Khm3H+yKoIwJ4sNqz7FkiVv7nTt6odjSKYtbdBF+eDp2MqBj/8DWNBfVJ+C
g0mSJs/+IW9Hz6xqSxhWsKKdg2AG3taImcAu6hFye1j0+h+3Ad4dB0tPpoTGghUm4m5Sj7esxJhu
x3Ys/r6lgX404vsybw2Atqwt5IalnhRUMx5C2i9WKzpWE0zGgLtSmi6kLHnT3WdM6/Toe/bH/P+Z
tcYhvLU/IgbIJ86X7Rl77EByLMnVx7DEQDmW8jApd2DiH6d/meMAEEctO4NdCHhH68Yk1oyvRKYf
7hepXSSDd3lsfQtU/BR5dX/T0DxBp1aRBmrgzOgFeJ/sXZRiNFKIw7SEmiATSujlJUcCTV93Ff3s
Bd9EGaYxAcRWAbC2qcsFBfx9YkOJBsZmvxiAOIqWXdp05B1f7GoQcTwQaUcZjCsc+QBFlD7DXI+t
+rbV23NDyyZKfCa9e0gYMzlimxh0EDBMn9TWbcYNjNVILz5nZxYIjzgcsxz3m2OFs67GX6/r+Ag5
qgWc8Bs7eX2D5mEN+lBS4Noayc05hsSm8MIE67/EPxZ1SVO88br5V/i2qSAz5op+NdC2hHLac9Xq
+aFr3DcvTQWuss+JSDxaHUvjefQPhOUn+krdhBzqAw8TmiJuLQq9q0KliBOAR7BVMYiRREiTj5Dl
CfCtmBXnRwGUv+Utda+uK9MWV8o9zoGYfCcqwhwNv4jp5Fvkkar7zbDBAg4MQ6HvRQSHw3w9xAOe
kB9VUkrwCpvqAS9h1NHh5D5wgOpzxCaEktTxqgKwp/H4vtYxmh7AMj+hZYjGrwXf3IdijOapWUAI
+QXjSMW6Lrj7va9lo3Xpz1WrAfASpRjUJ+2zBKq1RRe55vIG5QwU4U/I62cJMANP3YcKSoFvmh70
3vmFCLhmnsq2oaKncP+YQF/JcX7DPNpCC6JmNbJe+bkMS2hsOQRABhGZeWM1wGoyoZZiKodQ0Zzc
YLK4gPS4/tdlYNrd37NFpBQz+z80SqjeQt1EsfhToiimrkLe3YP1dIsaTnpqPCQaYpR5lpejixcd
JwTKTVuo6jrbgmlelvmedK53f1bI3LfIb3TiYRzVwyqGqP4jrhRUuQG2bVyjczEiit+6Ftt+OCCt
fb/X8F3fnp3mz7HhvXQt/07k6WkldtqCdNWlT7SdLiR1jSGS/Q23Ta9OgqqP7VtXus97O3VATGdJ
0jUk9IJ/Zm3UZ1vFli522+xZrRYf5dcqTkJ0ofGL2liyRUGebB4TG+oT5bKO2vg2//brOf5SCgYX
oWbK12vsfzttTyzT5bR+dcThUKEqxSZT2GO69cnSDt9kj21q5nqZ6QbBpB0JWPr8fs9QitAl+FIM
2XR7kFyC2qvHZd844q7ZZki/GdJygbtfkbQ6QLgWp3bit+53LK1N6CErChCWkM4JI2Yi6EHBVkCV
nXO1ZxqszWf+u3CaqTMw6nLCGu6IC3bjEje0F8KCZ6/jdRHBLcka6GvZc4cDTCH0XpgLgXjfom+h
lFFsFpaf5rIEyDOMZz7swkaZ2FiMpegC4pADClyBs4UIPrVnUvV33Q5u5xZ4Y2neWAG1o5h6+BEB
8Fb+5VC8yB7BZZHj7wlvz+JdYh1vviOFq61LdsfQVXeUTnDXAxdfvBdZra8JfmahmsU2dhQrAkJW
WZMNqJAJTNjdy4QrhJuQsvPTjsMGDwtjkl3SG4K2O4+gEyZs5//WVz8/oIYIjFgdTNC8fqPJ2/ML
ZaOgbqjlrJqc6jDrKwHJpX1QDnwGRM1DzLQWoaCimVu21dGbI9yuPOntf6VbAhhLBydl5A2lIHMy
ERpFObbCjtUhzZGnmYtHMNMk6PqVnQwuL5jsNEVmWbkOYKZ/bI0AH5ZtU0VDlp0cQBHwWMNKVoxW
Tq05ynwDiAzgK3xZKESClWmboTMfe425RaOaVycyNEeEDoT9+1g6UF3MpZis8xBqp5NXzkMjQ72x
rktegbLSi4e4t3bpOVTWALjtg5uA+GNZgmb/Z+M6D20jvwk6eA/NKXIDDE0BhT1sU566i729TbFu
xFN7s34mnPgIVrjXUc04tX2xCza1iCYaMNZIqHVgKAW4FaeKEqYB+6F1QCJbr9JiXVUIomI7YdjC
Wln4KNnPIyj7N01nVIiUBvaWI3LVmL2gMiMmu7E6sXNSMRKjFv67Cmb1wiGK8tu2BccAy+PhvBe8
USUWazJ1QM23/7azH8VvYGX8AOu3lEHn+tC6J9LOHMlx9nYDR6n67iMEge5nEnIbsAIQ6lV092xi
lP/eRA2FHb4Rg6yypg7Ku9pxpVUNeROPxkXWICOHK37gfPx3Pbj+IVGeFkUPoa4ZS9ZRgrox0FJz
eYr+/LC5Y1UKNmm7Z8F9bjLitk21j+yBHjX9yIPFaesziXvrCq9tOV7bl3KWjD9WLgWnanl/WCX6
fOFaQuaYJ8Ntrg2VGMxpz/VxhSfXKuVNohGy2M4fe4hTTf36XfppPLi5su+vtEKocuLsgEJ/x/aj
LW5z9zi28RMX/Smqxw8mUppt4NRo98+1ZCoKOi9oCzDHE5r+9WZz57c40zaXXeHTKcy15CefDjri
F+ubpt40FNQXPWFNPrMSRMYuurRoa5Q6Ti3u/YVuBGMLMIgTaz4c4sRuRsMqVEe3e6IH0AsaxDZH
VWis5M2xDIj6dcejclYN7D+MBSUBhLZOwEU11aA8vAQ7QqmMFg0SVC82TNKfbWtHicc35X1IPpwo
tfcUJ9yvSJ9+Sc8LSPJEmf5jaes5SL2AupcwQONVI/4o7y/YbMAczaGZRl41d/8loBwhlyVI7eaq
wz7eED9CKBmxIRGZSo3/zahBGJg16FWiGfR0+MWX5SSutp1JlhekWV1xiKizxUNtzOhb1SWSSd5K
QK0hhBC3AnuTUYKmCC8k8xnAMhRWiYECmuagSufhWyJrb9u28wBqGenI2wgAFBFmq52UsgACOvvg
sORlTPpD78FGmuw9PV7LRSmlldnSBHioI6cmPTjXSdl9w4UG5rbI5ceOepEVVBqKdfGJPSfqM81r
seOUx6XBucLh7ZEm0zVhzlai/1U3LDJEPZIgsNkw3O/6f+3FN/BepkPsLUfM6x9yXVOiDeIvKrqM
xG60nFmOUccEyE4AVSpNsuiAy4UDhPxWO3XyGE4GVw/YSiuO+TzvULR5KfViXPm+Z34MChSorFXU
qRDrJswKNOvV45bzN696Siym7UKVhsBm+8cKbJ1LOd4AeWbtCawr0LtjyPMnBqAzQIkRamuLesMS
dmT0xEd1sP4bsPdxIDp6GF6yUm68ePpEJHZfo8HrQR/z+zEcQEmJxVDclU3CuGTkolvGDuTW5PZP
WXMSAI7McOhvgqd1lxLF5Kg054Tpix3oOuj1lwwH+wJYF0D/mE13lMQkdY+1flWaDI3WZ+7Y6Fsr
312Vz8UFNLz/b4mHsLMX+ixwOhjbvcMZDFxH0WpSwDX/TfuRkMmxCseQSrLKa+r+Dx7TwOnKsxsV
xQ8neuIQOLdkdZPC1TEOjY+mALu4sDysH3xZFLloXKuArnZ+PVj7sd97Io+0Tx0NY7+uXqjS/+q+
MaVocM6dDr0BdBwsM9RVfEdbrzKpSwwNYBGy6l6UTfhp7rvWtWP33dAeDQFMg1OiBPuTxozPAPrQ
8j5/DCz9KpdqoWiaLaJQHp0duvrj1VqLXm4Fun9pWoDwK/m51Vke9nOjLjy01hB8+TsYMLS/nto8
2dJ4XSAaiUE1wjNtVLfZLLpgA9exDTSgwtLipdLdFFTeYsIQ9Fch800s5wJ8MDM6JlLRI9rh+VpE
wKXT591/6rfok6ACRpDEozhN4+sIIUpp1HwtmTL0w92JSoq1c4yNtWxBqgzoPJ1dZI7QRJz2DLor
UReEcpEvmWmY+czg8FtcJ0vUKINR8oR8mddLWk0Aavfp7Aw9j98tbatzZ0sqXl4ICH1+CbEK4qJN
KgXynbs4aVJtASFoOWMps7asxLjd56R0XbiZ8iRYvfHp9lolnhF8EitNrSesM3U2WA76QR1BOd81
IyriOooSYvq4vkoDoabyJLhU0WaIoIxQiA6Gi5jH5Q1ixilGbXaB8mKgHNLNNEn+Hf8I8wf8Om5O
s5MyxjrxTQ02Imun7SzDd7CjDab1XwFJbTFUaEkpjMxTJro7dBK0uBqzlgW3HV5xl+nvjsKzdZEB
OiSvAva8O2RJ4aaGglqsNP7uSgud+vtssoa5gG8Olis5u/FqcTOr2M9KQTQPZ/S8TcvQTxOVwtSy
ynjSixORpWLFz0LdBbMHFo+iVyzgyzEiGwEGC3KT6Xc34IStWCHaFbjx1sRc1O+Zfb1wSBc8YjWD
Xj68EB+YkzNfL6KogcND2uuhvVaRX3/YdYAAC3/hk8i0petSMCRXMT9Bv6JMG8lLpYv2Fuml2J59
PeBVs8zZusuUsHlhgygUJVUjX85eXBUM982SpUI+PI5rjOuDorE1CKANd9NbapFydyyrP5PevyZY
yEl01ZT0QjUYdw3N1OMKlwZcrc16meCtvggEAvTjolHLgsi3ysyFa0HLLzKLM6LaQpCeALNalHLM
EQDr6AnCSyrbvTNL1Mhrr0Xs566wax6QmssHJgmz7LGGFZZzlz6mXcU3EVS1KEnNb6HKUsR/dN8G
1N5kZCn8zDcLAzBmRNKsdfH1VCtIUU/uOgbC2fFbvIpplvFVHFnxaIE1JuB1RAlxIKTLOUm9Xs1m
KSI24RgTB12HMrN2lG+bikhwdWQp7GTpL1jeyXHW7NvLWRBN1z2HF1rMQMbVIjDUNEVIuCJ5dJ9z
ajGXNfg4lwmDpc5qNQd8V1epS48HSWtID+85sYq4iBNiPDLA2zxXcrMfw1nx/BHukBo8TEmEcHMt
5/DI97d13oYAFtTznE3hHxJ89AcUVZmxNXGlwFuVqh6KIR98SV9fdoUkWg3bwp4Y2tMX0b5hSRK/
KDP0A49nmv6ODjbtuP5eomZmDSifnotfsBb4Mjn3d1HjKXLSyYcdT7Qib7swAk9waxMWAnXedZ3c
flSunlOZVhjlL91+9tGhPPb/KAEQo+7XaG9TdzlFKJggvAV5W+cSupZoUdepnDz3d4DxO44LiKFr
wjXT3NzIC9TPY4/m8tN5+O7eyEIc7IKMOK8Ih8Jt1fpq4mHHNqc7eHuHBnQtlmwCXzb4b6fbSqh/
rQ7ajdHeByDS1FOy/AhfYO9nMup1GhQ54mo1VeYqFZr7+Z7X3VCJ956o99Tc5u5rf/yQj83urV//
HBCAzxAQJio4Y1B/Cnco/zOO8ucDwtP83sViRGZZTK9Zti3PeslEINyu7AIU+26P5YqDpLf1ebMR
6v4wFsaMmojpAl83rDMoDEviS33wZQIietI/kuhJG2/bF6lX+/oEFAOXrkl7ewQE/L5mMWyUhqO8
uAwdFiW2bCUlIeN4JSrIrnKgjgRomxAXSPYzQ89dv4Li47UsgoDErYajISIjv9jZIW6zv71sAFzX
W2PyWLv2UH7sGt54wZjyHgxjYtjytEsY3h6AdpThRAJyvsY87/uvdWtaA5+8tmRAtmKEXlxtEdSP
ITLa3Jw2U0bx8H8GVgvQvWnuSJKn9aIVemn/fP32jQKJ8NjaLX3QvUWe5z0OMXLTHkx+uypLTf8X
GicSDkxR8msIdHxHgm24k64gdPAmfnOgBtQC1Rmw2ckPAdGlSSZFJEohkA97oz6Cxlkb5O2USN7s
HmC71EjJcJ5cjbngBKnCqRMvgBl2tq+mfvhpMw7cq4W9OxisrDB8VsnL0pwiOqMLVeMnX1+ZvIsU
epY4NXh165MmO7jcNM8KZpM1Bit2L7qQjcGaHLRO3D6grRvMtn1G/YfDnaBzJ7P912B/vPE3xj5K
cqyVzh/lSpOjAu0UxOuzg1hZTxnSSYp51Hwyq6pJXt79x//orcD7PCq/7GPc2AnB4vZpv6qrevSS
dtrVqrAODLxJ0e12TWb408Cx4PcdynY/icM3J/8myGeLiOAt9GvwGPENWBPa6VAUjIdpfpFdArdA
e2S3T4m99ZSWNIul8AIrWgOPsiojoN7VREpGUdVaPWu1vqsG0A36247zzPH2EkJYvnYTcNxzI8eu
hwTOPybf4rqehcnPRAtoH4vVBJI7VzOujLUvKkmyVFzvk6ye2Mv+NqD6vJe8B362CZUZ46m7jaaL
pSS0aXmfsWwW9PP+/nZOTC9I10h1P8NxX65Lvli4+8KDGcYzzYCglSEt1PyJsT5ruuCU58SwuP7Q
NxhHr7F4mvQsjfmOc/VREip6ED0wK9K67n6rFYOqmuXkYTi0mjuG1SUgqd+wfR7fa/h5jyffB3+l
g9Qc4NWY0oh/3cCRjvRSAXesda7joJxpylAgzgL2OGitxp+RCfnJ3UUPP5FmiHlcPlCj+JlslXmY
UFrTuBEw7Dh0bp74ldpXljiF+7v/MgYBSCNUwpRnYexcs02/ijeERKHGG/uzUmE2NMf/p+aO3v2e
Vb1usI2dExeO537gUnq2/K9dDl94O+3maUHT1QvOB1lIOqb1M9HXmnEPFzctHEgApx0Mk6sGplpM
uK0UsX3ypPQpD8m+JYhjIXm4HcGM9p62bnG9v4dI4iXK1/nKVVc77b5umDFxxsbKySWT5pG2H1ZH
9pOBvSl293LaB8njEt1XAsGeKXCenWByBFewSGxWBmVrnWbX9CyPQjzKQmXqARlaCcFl5jr8CUqb
kM/OCq/16/q52/kc6BgZNqWhyOGIicippOrnqEzXA1baM7ArvMWEcx/+sFfxHL7iqkoBHu8gjMV8
XlKoS1OADd71Fl72B+2y2yFc9VEZNPKFToq4Y8IDcmziDEv1kdb0edLYkjXq+lrGfOEIcNYB7ppI
vpVhif3zcWrHSM3YlpXyoNqipvKTwRvPvJ95+1O6fK4AfYjY0NnDG2TjVkHXgXAR/raJYUmbvz83
s4/3awJem93kW9pNaz8hEHNWbxvmsRzRpEkklAcJXCbl67R5sdNzsuuvtrBpZPzsg2m6bf6mo9gd
RdJy2xD3r92l2BZGVpV0qHIwTvT/KY1zmpltWWK6OdaNN4w1ktNBvMCctMO0F4iXSt2c+tJWnWsY
dSSHOecqiRQ2BY9ZkcIqVNPNfjPd3xSd6/tzDKoqxOsfo6FFsiqbhSgi1yreehOlV9Bs3vUcYREH
Ob+0CTYDCOwRlBYZwQCdRfkkTq3j5V+oJ2lBkqCu6Y0VsszJYNxWAORT+ZjpW/6RALNqZt3QSKHe
qm0iznFQuUSKlYjzMdhIASCDc+zGCZ2xoe/nLTzH5nLbYWB3gkO9dgzASk8yrJlYGFv0A3DQt2Qm
SxCjENgLC/bkegJhH1o/NTQ4A7JKyS13xXiU5uiXkX5R5pGWnlPHD4i2KpoJkUhsIzrP/5lp7xww
fC/VQaezrta9Gr2o52konGz8YpFthrhsmKA8citwYAk/H8+7nYjkWo3PbcLN8QuadjG7ZWPoUpvn
+S2Cwd0iP16KVsVWyI8oJ8FLY20x0P6RuXyth3S3DNIqZbCEMB5dW/O7YO2Ik2Wxp9HlKdBYIXRM
yLJQOcfq6F0dU+5EgE1ewXmTCKkBTrik0RX73ajp11Pc6kRAu/VRkpSgC1dIIGe4XKW2k8gaMSdE
ys06SbMxolHafWFwI3P7hRhTPNyMJgJzMDEr7gHFZRIsT2El/i1ZJqhZSMEeHNCw84+yF0LmwjWR
qiszNDatPN/4iuZE8iy+PJxowjseyLEvUo8V3oR4TW3DgC1BF0B4iFlcMjt++sezPW+K2Jkzonot
P/FmuUgt6iH5ofq2kLTOZoTo3ZZ/6MYNx3AcFw3ru1sTdhizJjBMokcMaPzZhvbXIbfs5r4RHtn5
buiAwN6IDIqIx94toHS5QG5jwvA8uJ4gCkyjHdtodWdJYZ1awyY3z9oH2R7p7EQTDhyJVAylqN1x
AFvFRpdeh8bc7WKpN7UzBaLboSaMn+MQzwZ4MKMhOZYODWwAWHNiQFGBSnhz58nQokcIUHzNUkgq
2rF3IwPTCpGq10FEylQBsiErmYO0HZOT7fnuR/62oa81S3Jk+5yPMAdVu/soGeocGUFAxG5Kccq0
cyQiJlasbUb4gk0LGEsADrv7YgAtRHLsGWvLkvEL/UhVFVVTflEmNmL0Lrj/bk85JP91zXnd8uve
FrZxHcWe3XFM0M7hxKnLI9mdOy3jA5LFKdSuO69NNWRqAw0U1BcuQ+ah65Ptdx3bRx8U1AydnnTN
F5an0FB8Pg6HTgY3qepyhY2/cdwSvXe7zEuNz6r2lEuhs8pzeCrK+LgXq81qrnKwZevCZw1xXpfn
/5DWllM6gK523IvMgcRcXq1+pkdMuUtZxrpxaNNAr0hleV8tFn171OP36E3F3A7X0cAoFqzA3q1o
QHTOzc8VVqK6P4VeM9nFDU5d6wBo9hzeD4MtgDBczsWIcuwhR0TpwXY8GYliO2YLj0D2qm8F8Fgl
hojBMw8osVQP7uT8G3nNAoi7exKIwqePUI3/MsHWlYmpBEOUhtx8pnIWTOUJcqt0kg37fiIfBXhX
ZIpGsxy0hi16mIa8ThUjwdi2u7kZ+O0h2IY84cCLK4PxryfDDnZQTvaOJMUy4nhQGH6tY7PolkkY
vV0nWy4KbZ7/Nn1KafRHDMGXMENj6yNUOH4NB6xgvPquLpUDZZKjlVpIBoV57926PrtAvzQiYHO3
Zc44NEwPhp4NqnNoIl68cx/Y7opFtOAHFPJYEx9ivTFbzGf+qZI9xTGPm25s9yqwd4x+HoernPfn
kHzyIowAzYJEexe6+9xHtOzXVvU57gib5HBZt3MOyMX4LEZ8ro6V4Ly1cQU5Hh1zJQe8U9qoaDUe
TVDstj2J8OfEsaIGZOrpTTl7gtquH+pADpF+yfpKe8MxSN7UjnRnTeeLtuBUNzy1k628Pamq0IqD
i21fBO7ivF6mKN6kBvgbGqOv2nwkZACcdwzBiu/S+glGxmI21VrI0TrTvnvYbb7H2/I2bfcettM+
wgQZXeyjcJjh4OwS6uOVNlcCM2FG23/f/phAvsyKaX+WAdAxbXE5vGolSYwAGfgZGo2rQbiiEXDW
vZSTCJBXwAMgUTAPf3NirqPENma/t8J03Zlr71N3BQjJprx2Wc5886xUmydH7F5qmkRj9bfRIQGC
TWu7U2l/9Fk2FtZcH0uI//YzLXd2Z2n4FwdeObjCwDCRN7UJPEYKn5dMTaB26sBzA74+WkAY3QMh
bu6FMu0j50vJFG1xsyt0XFW21cQSRffNjZvwJ5Z/0TTqq/RtqkUFaB/EfEKDBndRULL+z+FQxtED
HDGjRoi4iMHRwhPMvR5ko6mMQqzlrO0WDIa5LbwNudSqVRCDlkZFR48sa+8WLjtHrQ2SZfJGS4Xm
zWnO0KPazYqeKPdnCg+PgE6cASDLJXxub/oo9jEgvYSlbnVVxY+ibdfoloi9u0VnPcLwb6/V3AS4
nrDsfNiYz30sFawAcwPCq0MesjkZLVFmRORW5Nc5/VoDqa0cy++9+jiTQ9YUzFQTSTh5Tk1ighCb
HczkfCpd2Q9wIf7fktN4NyqYV2FBGxZgQF/qZ5XVgxahmqJSgrTK87cVE6LwfbueuH6JevchTX6h
sxGoBb5g+1cP2e7cr0GYDn3VsNz2iQ4FkjCj3FlyXhUWGQHWmF8SnmlOoMT9fWmY393RYe51L/fW
TES+k8qholVVaxxxJgJOaVGUFHxYrFSzrb+dcOFE/k0q+qREBmrPeAHwvouGP66C8WJ5iJDFgp7u
dffUdUjSsimDCjo5Atym61srA2+HLIz3DtHa1jbijHuVj+GqjXm8yZAR6OaK08J4QtnTSQHIbUxS
YmsGM5T58fvLOrLTBhaWi2UiI1zAdOeDLl5mR7i6zxSeUHsliUxX8C3x7zJ7n1SEPoUAHFsDAU3E
W7F1TQ8X/LDBbs62NKXWkvq2ORLVV3TkmjbnE5ceSCEriCTPWLyS8J8nUkoxIwp4Ug6Zav033PZ9
dNw6b5zY19g6IgKppLFBOXoMjtBluffgin5Oe3XUcZzVTLCNGuvVSWHtv9zje3S40NzN5ebdPlIc
6usmW+BZQlxuKvaQivAIwx3HGL49df0cxXOAGHNi/V760HF0JPtd+VytSKPQh90kbTGxF6Pcyt8o
GFyvgAtodWU60SKNLwbWh+yJoOrKInlXytTWfr1HyjAq22UPZHEHmUQ5T1Cw7i1pJG/GvazjP920
QFTq4tLwC9RztQa6d19FygDzzEU4kMugAbU8BcXT52cbZIljzDtRYSQk7s7XNsdvnxAFu15a8OfF
JpkdwVBIj2odJvIyO6j9R8F2KiIUyBX5c857gB+OasKknSsg2yvYW7r7kEe4g0uU2acv+0nxvl5U
paeBdtNUCKlU3qcPidj9IIcrhytBUIYGATlE0+C+pyjeBCq7Ep4vANsUs7G1Sm71UOuucYzIZXiX
HmlYStSWfOHzpC2dYE76Lhk6Rk34DGBaPAbw+tNT3I4IOYrBGx6PkYt1Nwcs2DFDjvEWvz5TiYI1
KP/7T1ydwImZDvrFi4bJEfH9HOJilvsXNAJ7JSS1mY6sZ7WoR40coMJb8U8sbXzTa3xCDPAyXHdK
cKJ4nrJ/l5OjRLCVkkXp4kVzO6+ihfvuq7iW8gUfEYH785+vUlMxcGzYwnvxeOdd+ILI1UbjnizT
y5t/HuUDrukuUar6Yic2RkVAXgwejhTm0sLZcL3C/58Wvoc4ys8MjWRkiQ8bVM2m50FTwhuFh8Ck
9s1+MZDeXmVe8IYbzb/grE4GZ9SVNT3DTMyteq+m0ARe7NrndQjH7NVwmvYUGsCu29+RRhLMfns8
pDWaeTYya4QveUluCCfWn1uNII2kRMpLOYl0NwcpdjjLtWgk+UqhdSH9Bx3ozayrIutiAIZrPpUX
m/4z/DsNy58hSx9craIIrvQUTExTQHkR/gRd6EUb0Asq3IcdhFVWwGcoMOw/pIcF5lobtCRjmdZ1
QJhTSyQc/5052KcYyEbfTQgFKMGPbl9ogWjHXM/86OREWcm/9P83l99VsuxlY/cx23QqWT8fOagI
kG55LENyBL2l9Z4iLydjhBu/PnC5uH93rmwn5bS7VKfXPCuG2pFmfZBjGSPfxB0YKH5pW0tMmd7q
t5rD6hlZPSfhk0RJSGZReE4StFpmGuwafJQzByUHcwwCD2xTglkbrZY7iWSYiACuAdbfcd1UUDmo
db5mQlTiNIv/z3W4eH/nFmrS7pr1t0ix+9VugDGniIIUgEgpELjpqFin9zdu8RR36Hj8iSSQ6oJD
g8TAQ9tJvHRPwQ4XaTlzgWN0e0s7ZEoAMCq7MFPlm8voHqeQpudiaEqOtIs/0G6Ts4DIdKqIY5C8
r9hGAQJdT4oE5/0LFPOtgAYLDyXmuUALzfncbq48Em/1iQrXI1FsvVvT1znqPy6NykOQ2BwyVDj+
ziKPmWFNkPsmrBci5bXRS5taBAVp0B/c3Ij3b52ZhdUtHZcXDO+8JYrksYvO5uSxyDYEGayaGvJt
dSzUxtgeAeTM9AwPDGIfNEiGSiUWdE1E92kDeH7ZrOmbkJs+ReOMA2grnD5f3ycLe/3327jK1TnM
9EWxH+DA1P6oDxhaAIG9Yb15s0XlnaBtFcfB//m6i5y3Z7yXbLrfctrjFNFSebWzmHpi3Wc8mIMV
qCv9/USIctIlVXaFbMVePaIr6NjTtIDHqyI1o3svavJE5B7YTul2BzD5ZJ/3QX2coFe3OO0M68np
WkEIVCzdP/tc6CJXnWn/zZdzUcfg5S3pNIDS7d3wz64rXF4WoKL9+ULCEWWcIKTVqY24ssPOsksK
aiJ3Me1UaU+YGxEda2flR+cEXRPgWkhPmMntsDbKmn8/aBF2dP5byXETgENHUAhYTNUjWPjPXvAM
cCUAm5hAMbKH0AxhWkoqDB03VuKnHw12KXFHjnJJ2kopwSxLYuaK98eEG84CNbnsE1ETVCb0l9m5
/gCqlIeBrprdhScZoUO6JnXX8GvuRev2e008CgV1YCF8jS/4mX86g4SO+lEnhOFqBRIA5d+ych2I
k4/xu3rM5razC2WScVKr3YGt3Q+GSPyPwsHPMW9QjPFhrjig90sCSig38FvBqI19w1NK1CCQrvt/
qJJ1WoaRfl47XtCruhdvtcxH4JaATd5/ceFGwySMyhJGmRaTHPoBw0EAs2SFlNwR0aSZPLPy1D8o
HUK9tzVTeLUL+nILo2P2GKW32zk1S4l06qXsXf9nkBa4aWuBd6dVfbMgvV7SdAQBags+nK2IIJrY
AOXDA4fSc8iyvQTltafVzbNjsQaSacAqPIZ8bRvzuNlDberWD54kxv5ICrZkDuyBSlKJt/GIa4lA
Hf+C7X7R3znbRiKDtBXiY4qY59BudgkInBAt6HW+HzrhP68BEbTFowZmnCHQRghA7hw0brvtHLWW
vgB/bDMPL1ebflNMVyHZcfmQOp0Mjbkg5ZlqBcZYAKA3m4qlHRupy9p9ZL65cl4aIl6W2JdX0AFE
eY0VYK++VrVTQA7kTxlqFFfzQOA0KJwpooLolUWWDhbAoDN/Sv+CEXPgNcG5H22kGFv5nachO9QE
hCiB6tTL7a52KQPtLZpWb/h76VWtRN8mt+KdUe93dSSUNS4OF03Hj93+S4IZO7kPmL3wH5v6/8M6
LzExaUOS3TXOsCJ88ZBzB+ZU7RgkjHVOna2yaZGcXLb7PZhGs11RKbYyU92vZUaPMkfI9AkaymDc
EmE02h2efGrF497P83bGQHRhxeAuQDSgUe83SoycVD1gqPwPnMVXwEV6QPuc1Wi5bmVIEBplA4gl
gPmvSrByqgwKkFVZ6+1enIoiD+cHFrARXuWqzIUR/ipIAxCUF+IkBzcM7/XJHPhcgPhxWiEXbkl6
M8u+NYK0UACLPxE0JidLevDTrCxhl1UtoHUr3T62zyNcucxIS3a6tPg5CxhnZ8C6f0POXx/ZeZfa
dHUhqXZknC64YuPyvnNy+BXzPant4T1lMRPBqow+We/gd/aJwWTYuKjcWiTI2ih7B+yWggOI54JK
piJukMSMDHT5oln0BtQjf3ih+axG8JbwJgTpiGBWyfNb3CrUqkkyjN40KwzCF0Ri4+jB7xB4X87G
TQlMSdUtaG3KHXjVmoKLX5/VKL1B99yp1gxDoezrrrJo6aQrWD2lJiIBLBwDEyr5r96r/xjighEB
/Y2gLV/0fWV6at8VZgTtaK9tQTESngrMDBobuEVAglkgM7u2x+h4R6W3g8ExkBQdXYLXiit26eGT
R9PfXagKqk43n06M8f59JjUkNwJGnG8OaGxX0lLVzzraMdCDWdrZI77mfRdxqEOFcBXikCRGeGEI
leCaNlvuglS6AA8Nk1p34GENjtF+u/IIkaBoStZgowFmvv0Ms9vEpu74OSrH3eZKJ+B5zrFvNRzr
O6SCRvjzQfX5MbkZqdIH2AT1D7icrlE6fnC1cckvMHXc2jzFDhmy1tv99bcQI2ZISZyrJMWTMjdh
BHqWRPOeEHifY96NXMlcUu949X8cp4i3P3Iwx5ZyyW8KICOkENJpFRa2WhlHP/lDSnFaOq0+/Bhq
8w3NBDCAnIjZg0sxKo8xNNVmMY2mOmZLwIjiCexwn7bQw4hTGH9wHbWbCuO2ZYJFCkwgVVbGf6L2
EU+l9hKLMYyIdtBmoP1+mVFwZKpwwlEBIlW7mVNLFKEyfy0ncePaC7gtoihx7rt0LiSCDhK4Hm86
aWMzmV62valDuvP79VtwZpOFCtQi5jj6Jd8Dmv0zonYwHkLI9qkNmLMbwXeJWq7rKBM3kE/Zonff
kihKHeWjwc4nhpXf21/6kMk1/poF8eim0KdonDsTymBcGi5wamaEXO+ytKVgRMAxxYqaWOZbxQUg
FyvFozoitnuPaI6wly03HbSkfFPeHU0DLgQyqslK+SnutTN8DmgzDyd6l9/Srq3yQplCBYuvXtU+
WZCULtPndimJwdq/FXZSw97hT270JI7hPOKzzLmzrROGNYNuuI1lvYqYvFQAtynV/271X0n5spR8
vlED0RsOnvB1oro0YBr1l1/bC4nK1wKGv7P4Cu9wPNzuTVxU7psY1JPzpRJJ0thdp+/5JB2mmxGh
PgMWnq9xiGGtSrs6UNCkVRsNZrzEQmMnDDQlYNes4m8oMRWwDhlwjPSFpDMpGINI2l7xMEjHHy9F
0Yf50gQoN2ypJw6Mb4Seuf1LM0NAoP4TMR0lliyXGvA44C5ONz5RiN4WGvW20oax2h42RVh8aDNv
HGXijEf5I39jN6IuhNjZKFDHohuZMOOSbCyvZbSnft7QyGKILXMY0ZHkc+LRf6+ugmsel5F78B72
gS+MUZEQIrCEiuZ80P1MDiMQmiWIYU/lnXLT0dUB39Duij0QE8A9/ekvpF3NME6O/ZvhJzeEABoE
68PWwQ7JYeN+v9YJQa+1uDcl1+9dQB7OHhH+PBjMlo3roGUSswVKWnQBAB2CgdUIqz28fWaAhYz9
PAT2LnSJp1XhdkFclrp5ZE1anlO26o3mA1euAOS+Ap82zXJDPQDBNQQRGXy7d4WCpOt0KiT1o+iF
1IjG7yub5jW+kvmrFY0KgIfEB00EqeBEgLbCBFG2GNYH63MXWl9ChWRAwj1AxI9aM8W8nhUCvTpW
9p1h71jL02wBoNslDg8Z+oV193KyGVyB/Bb1mByZCJe3ltzDQP6kRJ49kInhcJUAUjDxNr7/tF8M
zwDxkFrOhjAWqmgy+ne2QXKNOh4qpWLj9c1WKOg/xRO5QW9VYQFzuW91G7UXwMSl+VclwedJj+y5
4Mu6+JbJIuxB6HWZM5ySPIFQw2ZOj/hUKC7EzZ8Mj9p87VWReo5y3/Gc4/ZRcxKcv9KTKwl1jcji
hM/d+uLLDTtb7ppddwA05FVuojd61sSWgP+R+BUVStPpZXtjq+RkatsqtDB2TDKE3wpbDxGvXsuk
VQy6v2yCUtvtkrAhxBe+84XJHGS9i8nBkMTWKFJORocItfS0oIINjtQO+bKgb21dVrHnAMA9VMuo
Rl+O2FYtqbZm4xbqbFZF6QMV5xEHaZ9xLvyEscHrUHcAutHx1C1IGwaSEwAyIuwRBEUe76Ywnbyj
U85kUQPyrnUx2f1ZqipYgxCmixEZQumjf6nlDzHFKB0Xt0Aq/8HK1H+jgCnC/H/CTsI+uciFUe6d
qK7P7BPguo30d3ROmusYv8P6JV2nr7eUxTQSUiH7KzETLuuZeUGngZrq4IJ/Nqrl1MnF+eWx+fv7
laboFJyYnUD+vdNZhwYtCmFQpcxekeiwrawJHEfmJ8sSKbebyY4vsfgxngLVNph61Ypgba1MebxS
kLLTuaPuuCcPQH5T2hOUSOSVu1dcCbV1wi7yWLg8yLGmvDdKdT4mNsNWgNXn8bQO+971Xy++MwOp
J+QOjP4JZDtdzYMrNtOf0G7bSOEygV9INr5UIdF2J+cjw+lIRyE8dvUzPyMaVB0vgyvQqkSnnmqC
PUOX2kY/r6OeG9fpoPAkYZh/AAuZikcnao9Z605APkLsB5VCnbUVpdZ3mXI3lxyaydZYtXk9h2+e
iB8YvhL/KJyTy7CACOm/5TYrFbFoVLN7k+gn2hNZNKdDh05TL3/sCE/OrMpyx5xvH7/4BK5HePmL
nIXXak9pzhS9jl8FD7YJjOKnWj5h7Rmm27T5fLoKZKC5YJxY79YJqu49xEYJ3dE0tjoJl5YnIymW
jm+nzYhpCtsO66tQeF3yDYrai9c2vZhpDSi3hvJx/wfh3XKP8TGp34YVfoluhFLbDWt44KwDxanq
gS/bmdiPDEOvktfuH5w4bywzF9AIWRGRnYm69aYGhXaRnIOMAA1zFc6Y7zXuxodpJB06u0KtneB6
nKZSkQWkjWL5/jTtXw0b8E+pzZggqnm2WhOKFAIO/VuiXQDrRtswslJmSZw7tasLPGZxDwSGROUa
VoyauWM2CXjCfxZDGKeYiFgB/ZQ/sjbqlmWUTyqCzEFHRG9jAQ2pWs76ZU9AYMP1Av01fstKcYDB
LR2G5tjVZQZlJbB4jv6RAAR4ElslYTRYDVtbN98WIBTw8VjroNB3yH03WMg13umAyaFB0oJGvCwj
sMrmQcCM38r8NpAHU93mw9HKMSkUFzvGq425QFgfIcLLNohyJm44SWVDgwmbueHhh++/4Lev2cPY
lrJGEJHbj9Q1j+ytr9ohIyc9I2A7kfops6I3F74ylRe/23sSmgf5bBF4l1hS1X9FF/Nu9iMke2MR
2s8n6zxQQgYVETxocu73GkPIFUxumvVi8YpkqbYopD7delaj5Gdr9Esj30csZcvSOr1rDoX2JGwP
UUJCC7sIzFpsIsVJf9Rr1lNWm77PL+whlRobqQPHVu6JvJ02q+AK8hVOs6M5P1fwFJzQMw2/9TZU
Dlfi68tjVg+c4Uxqaas85bj1Hjx1qURNetNbyyQMYfHZuRYldxulVTp5arzF9ftEX0bxIpPyf0DY
T/PsDPl7+WSqOCY/moV7aWky/2NWHXPu/Rm1TDqTjx/IVvY2EkXGQYGfCepB7sqU0XcoFnWUrBp2
BQqyPvQTUyTRjRMkrcGsxhMZHg95LS2eqx4S75sl+TGgs6GxVm8HeKrvegwP8M1b7Fwy5oWTMQKD
gudBsbtYEKb+uW1Z1JQfjGcupl0j3qB7AdObR0F1SkE1UN8Ih04ZiMZL8Fdh3B2Rxt8WzCa/n6ko
ibwzoDGwWTM0jPp3iT2mss00HOX/eQX54bJZfR7WGPZ7t9uC6JT7k6uHEFSW97J0jiZ3k/LkysgI
Ej5GEKek3WgpI+Oiflvv0hU6oAw3Q4rsZ6WQPND9YRUZRPQ21yNmQjVjjlB7Jtscc9A6h04tfjaT
v84DS6q7JmOBhppuJ1l4I/u1u3aglodyPiIi4ePBFpzMUpXn0s/AEqoemyt+9d0xq8XgBdmHbvy9
usRX1hE+bdnOQ25OznelFzevEhuRI7JWMj/o/5qW2gnAv8lLe9B/tkaed6i0dtK6MB+LV3ntkcoY
v5MDEAfzuAyjOJnTzKGg6pE0BVEhwfWcgRkry7ibHTQn12DegVhKf7ebt2Fa8K1YEpxVXk7QlSOk
WMjik7Fdl8WfPLuVZYBiazW+OqiCir77vTlyJv3aXTVjNWZrDnQ/gzJw32GYyPfdsIbNrKTsd4hw
IZxkLnvpMSdQ+5pOyKi7oUGckw+1PizJCMY9lDN8tacgqkkyVKganszEqHxcizVX8vcyBcst3vk1
EJ+bSrVuTEoFB6yZTcg92JEXx9/mawv2n5Z+saUCL5+h3VrBB5QCSMrSpH/Ye2LlWQ6QBJ4eZhHG
7P0SvUrxrCGlbTHhaRXRUmqP+o2Di8pT7YRNtV2972sc8v14/3qLemXKBqbruCn2VJzRoUXqjkwf
ooS4fj4p2jwJ4Vz9cT9q5uAr9OKOqxvR9t02bzLIYD55ymJskVKerJHqW4rSo0EZzlD6lgmp0nXa
CzHv3jmZg4f3rvfhXZBm6+rRhXVWCKhV6CifjcV1qmm9R3/TUuSHOCBRF0MrwttK+GXpCd0uMyCG
4TsFP6cEpIjbdQatsUyCSrNHRHDdsaluIJBuHyYy34vCw7oHa5fMZsxkc5f2qEd73z9A1uWA5H1V
rGTb79lgF+ozQJ1veH2Gf8HB7o9NRfF/e3+OHsdRCzcdqAlOZnVsZbQeITyM6j/Uh4fvZfSAljM9
rhE0aqF/RO/0jQV0wVTQPIDQi4OXFSoTVc6MFGiGh0RF8II6lozMLahsFngoOpwRs7wvfKz2Dudm
sD5XUPv4u/eJyQBh2Ta9WEVubKQ5d+KY5ALjv/q82RhwXqJpGUewx9PTfBt6BSi9i4OgxfvvGWfg
pY1/4YU/JCnJzxy9LjsgfckBZTAS7CH1+0kBx91FOBGuHpN89QmmnhlxShzDo5RHhYrgh4tM6PO+
oI5kbzT4+/3DyMLAtH/KNQnv6fpsoGhFO2OnZiyNv00xSLr5V6RAV1UPrWmYUubcHJvME2i+O4WY
uK+QqrTclJH77iR5PblnsLBPmUL3HaYpvTAA8lCfXE44CoUTKamcix1K6CC0TRrCaf0ca49YWS5t
90qdgWU4Xz/86d0XzR2rJv9kRQQ+FXiUOwRlPSw4ONnvXp6xr2p/pEuqVfMhUpv0gfLIeadIuYgT
OdHGcPu64kRTrHvyjv+V8xaxajG+Iuybh8awsQbO8g0mZsNqMGxIRObT+Rf+4ZP9U3VMp4/srhqD
NsdJLigaSaS5D5eGiEgUYQSEhLVqMZXcyF1LffWE6aWHOcJLV5WddboWrsGglNYGPU1dj+OTSZRU
2Jc5F/gTazzeyPyYdTsV69kiVl8TelraUd8wq48o1N4oU5UK9anwBd132gS0elDdXXW7nLw3rBnr
T5oTmD7DZj8duA3MAksdaJ1fCkhMjSr6jGijpoJ1yo5FikoPJVS3Ba/GQioQs0Xk/rzSkIMgNtBy
7mgnYfCRRcjdLYNFfs5LOWrQkZ5R6UOFR3xmtSs14alsIgmxc9C13M9JUE7/1czUmUArCMBSq+Bj
gqWYqUvgnI9xXnn/3xtk/k8+wOkT84k6L8LG+zZDOAW6obvo4vd4kqY3gOeq6Itx5I05yGlx/tJK
5Ihydmev/7ktBzPG8/5JnLHV6M0iS22XgZMUfqVp8+bOSGBuU/PL5L/D7l2NtMVjbzIaAHiRKHBX
YCefDXIF6HTwNeNe7BS/wWh4Ffz97SHogRAxjfodzsr90bLufeRXbg54dMKq5u4YC9EEZ2Ck2OD3
TOvS5K3JFTkmTeRitODsBnUBnPBvbQ9uoIuExN8Zovx09ZATyrmgTGLdvDigO6ZWO9lxrQFx8Jlu
gVOEuDRpQHzrA5YeF3kFoDhoSPkyUykfqsOzath4+0HYIr01tYgYHQFBaOtG22tvX5h3Iyu5wDsZ
XHI7feA7XrbscOT5Skfv04wB3iWbIvhNu9p+PkR88kWBmEZ+eK4adPmPoIfp5DaSImVuFo+fSiNj
Fx2CtGSwedggVbwFL+TBzNlPTfAkLfBsCoEjL6/yOIei2plPGeo5vkmMpYIOmQPCKiGjhHozYxbj
osY3KnehcagYS5K9kHGtWXFOsL1eqDJ6sXQDkWdLx5iR0om+Hi7MFnaLPW9owg+fxvc3Y26eHXzI
Me4i8wfReygY2QFNqJm9uzBEGipWcEqcXb9T24Y2Y0dt2YjxrJe+YmSzvP/t1uQhcnlipl5iTXVG
NCHUC8dtiJ7TfYECk8SHE47oCIkq9GmjC3eu+frAPu3P89wYqWPBQ49Or2G8oKA1JgXOiDi/zPF1
7UIbSJ8IzhIRtqtRrG9idRoqAQtR1nBvLNy5oHKuBw1ENiEUG1o6rmtwPGvUcowDF4E9SIAcNh6V
sbsbFDv7CBAKkuAG3L5a1qxiMigGu290CiLNNXTtbssBIPbj4/k+2G5zF5d6uWf3otCPf4GBzmI5
JneZqamYRZqRJXkGbetfU8/6ObuSm8g1C/kv/cqINenqAIK1igYrNKkIMS2ZXbGnJVHNpDJ6s/v1
UngoNuAmhU+sljOChFv/oal3oNudefkDaap2eqpanaD/l88mrAtk3EYSgogwAYdl9Vwv2icIdDq0
JvHWxCOASe5BKlPxfbMsj+Utq0IrTp2qAFzrucckXSV39s9B5hiVyeQUKphIMk+aB+3Wh3wIe3Vb
AaElmyQuys0L1wTLZHLAVpbEYVTFYLQAQUc0+eGr9JS0SqdwsR8iXZJ6zWpY+Yo0v4RpJ5KSBAnN
Yzp+15g5jMHd/JAIH197NY8GLRY368CBuExOjlR+h00Q97WdJi0rxsiuVM5ZLlp9V3HBoic5O8X8
1cqbd3g6VW5B2yhx5Fj/c0bJWpqWP1vjiE0DQ2HE1Uis47P4a/2imYZn70DS1A8C6222gpdNBqdd
YyzkASf78cmOIJLYUHJ4x2WW4qUcOqYx3xckKIfLoLP6Dn4p8pTD5KL1h/mCQhGtH1IuOmWm9pr/
MDcds+Fb+aTnPXWBVKssJeMDBIMXkRPPY8x6GEPuOBxibQDXcLdT92tP9IrneMVElRYHNwiPzaSV
t3Ld2I4K5ODc9WB8HYKgPtwj5uotq732RMKexqHpq0LCOOrvOSnVmdNDA/wCNfGbYkcWATQngVrV
UqNdklzHq23Nsvy+vBW2CEY68kzigKtTHADcxmf83mTyFr5sjuXNVUqE7I3E2lmGJQ0UprJyAwMX
l7RCFquPj2mrQ38Bkaxs0JaNuSEFmSd80O7V2ttQARCWZ2qtvpGegb91pGzjP0IfLfYAfG2IC9Im
X1WhMg3jOU/bvnRe75pj+wP8lhkYaamKv5bbKkseve6mSySLthAG7vDrW4q3lO4/Tvxds80WB/FG
2FzCpGIxTtep/jM9Cd+ewJlONInsdMNCLvefTctMYyJKL/7TSnZzQoOGgzFluy/PnmlFpPgIK19N
ybYP7DXRbcVM63UUZpjCqTs5K9MKf7coJAbrtptJVzfVGlXRL/DzsJF1XuWhO1rWZ/ouUb63rcry
wHFFQVjBVu+ju2IX9S9/2Pl6Z1qe9atyQR0+h34LmyV3N7TvmnwGRvmxKzgXrVLX2r8TDVCCgDr6
J+MArXL7cyrp/4dSfr13Op4jtxFHxDW6rGgSJ+2WmcVAJfjgGsPyvcgiX45+Yb2BtGbs++g58Fn2
50kpofwLQ9KIndW7ft4YQvnGgYGcJm7lcCe6WIegRO7AGs3T2Sg4K/UsoMVMXwOwa0h2R9YrSeNM
7YwwdQgbZ2hRwTVHADghezDct1RN+wOGwExMTxhZadArcxSyAzEtOiHB734rcPvhNMsx84pXFOht
JbBgqk7wVFsdJb8hXF+3ZFhoyfes1ORJLYvTVTL/7rMyRzVwCuOWWbSfS+R6BqthWvL9cMxH/xjL
FYvYZqVOfpQhH5PjT6zlhm8CNdAlI/JzTEXXtNzn1GyKM/d9n43y5F9lARUhnc4zh0PFY1a9awRw
laLUeNpuGEC/Lraz2H1EMwGVVA1LIL0odrqiNu7wwbtbCtkCNaotpt7onvVqXCOZe5ghw4pJdhb+
86xIqELB7C2TwzFDcnFWmqfS0Yd7CJaEHkaiMlrK7owkON/i1bRKkR9yc9QE7dUC6NoCDUFdY40w
0d0oz9qYg+69an9PL5cNrX+lLJzSo0cAShA4b9r1oOc9e1DPGpQ/vcRbukUIhOkOgShXlMJAN2KR
w/J4lqxz6me7XlwUDKRCfioaqenVb2cLZnbFJKjILFhwsSJCXCEdT0PdhxTaISGbGY/Dd714gxFE
CmAODS5y0B6DGbKZBrnC/WOj186KcmYXlX40qE3pB045Rz2kzORX//LQU+fbksDQxS7S0myDspHh
WXlZU66dV/hNCor/Lnn90wSj1uxaFBT7fr1BhK2w14MVD0a6ifMKVXu+C0XsZDDFElrimPLrVQzL
MEd3unr3XQI35S2DXUs0oE9CdBBptDBHw0rMZrAVJWFSpkHzIMm/pIHq3Uzp0nj7gmCl7z8J7Hhv
jcQONIlMIbv7tkmYcmjie6Qg1KF0U0J7MegptC8sqArf5ytLdh48w0AsGneK7QkAsagPgF/wuzmk
zS1gucHDL+PAKm6NZ0Zt1AtPPNLDFjWMIYfs4B9VKe/pDqdZOu6cQ74i/8ZF+d50rcgpREiX18pt
mzV6ro6V8lYpg4GWOOSkVkwy3gERP0rTAIHHc1NOFQzG8+dJlgvcUq8TM4e/ovNbA6G01DT4QA9r
G1O9uoOgN7QYEgmYOHuIg2dtBNfGY7oKZpAW7aq+TwCLCJj+OafCgtKSmczmrDBXVaXNCWWaLc7X
zcmNxiaugJrZGpw+kY5xyyRsER3GxRkpwVmLvB9o1AOwBMJHKG5PLkQT5KrYMbRAk6o8UO6CYk/q
zFHYKOMh9ckIHbCmb+8wwIiy+UbWSk4C3BrbRpUtcqFQpE+9UqN+Bim81+u7xkdGN9mQirLad9pM
ZfkfvdB9JGoA/GJfDFs51Y8i7FvJzP4lXACdN+7TiZ31PTkrJlZdU+1NVD/dvfJJe0eNL3mMiTtE
4fThqLm/IYjHPU++nDfZBF7d8pEXwmjjRSuha4Vv3WYtWUflb+qQI0IzR7HAUGC84WmNRu1HOna/
tcI7fYAO9tBsaQPWGwQoc29BBm/sWZDdXpptUOgXOH9Htr0t0SnxUxp94P5SmbSnezo1xzcyVl+h
hZsTx6TrlCJF2BQ9FagZsCVnHdVCpAqR3GfCp/y3eRYx7yqro7Ljsp7Mi7v+owsuhpkz8vb+wHbp
6rLX3igAAahO/GeB+CsLVW7KEzTBtdT5Sc7+2nXpS0nP5H+PLDaJzAtCJEzbVi3U015bd3LapF78
lib0bCOExUA70Ppx0huPReqpCmhYSUokJEgDtyWiUJC90Y7uNhHHQShm4Etqca8VdzhXz6EdhlNa
V4ICVKz+JbiIXPzdkXf82DS8ssTW1vGR3RXYw9Is4dAd9MUKnUE1nRjeAy53zSk62N9tm5EBEEiE
AsR+60XWAe93luwxkmXlYoMrHdaDe6A9nGf4xyWgn5D+A12d0mHahZo55hyqYKbY/nK1e1y+Fzjf
7Oa3h3YyIx65zoVMHTtLohapkqqpbKrNCdZA+NdxrnKfxmNfMbbVlQDb8FJzqhtTzQxwRRttGQgC
E0tLJRztf8EbrYTItLCRfelcR0pMY1j2JgBmeZsSuvBr3+CRwfKwSSVWCyn0xNJlsMZtvxamiMLG
YQDwgX5fwWo684gzSZ5HAAy7bsfwHn4N9HAotz2SpOrc2kbJU2CHxptm4oeDEKfhFh8d9tuyjK3u
QxA+MiF1Za/Avk4PE7n574U2pcCIaA1RXtJ925XojjJoJsMjuHAn7bJnOzu3d99GyZSOZ8ymUbdq
8iiZJYrPglOVmPHzFEw9+kBdfCOnztVucsPdMdA9z2+Dv2bALQTnmVwpvOS9QF8/7UASJ/NVX7WJ
MachhPS9N4PHEQ9YqXncJ9qP891pdNqRmpO6KGycphPb5Iv2ZF+NIKHh1a39UrhAnrw/4bnAoqkM
Lnf5vpVYzp2GHByqPnaMzbOW7uY3Q0+H0KguqCAP1MiMqxsjHSOdGvHKNCn0h8x7ngdhtYQoC4sh
uPtZ4Z51RovTN0BsQRXtjTdSL8iycoKBlb6ta5jMeyPwziirn8S3nBzauitB4idFBJyLJdk8+GsM
3djKOaBThsOm2thr1J19rC6wPjtmFVZzQQjjyRyE5qamUqDBnzaHOPUNUhmrP6ZP0Ikfn9e/5suU
LiBYl3f6waFl/emDCqshrUVq0hXTkGY/LQ8HcpELBV04dDzZxSHrAKmwqXyj76W4M7wzUvCqfL4w
AyZo2FXMZizgYnbwlMSJ2r9sJucBvdI6QiCRdGQVNUaSbphU41noyR7ePLlMQlwW6rApxg/7x4Ay
l/bO5qoECUMWUWnmg69wlPWEouopd8wiO2IHFUDCrp0e9EMtZnXfQ16FF4ZeUFVQCgmqp+iN2qEg
IYIrK/uhNe/+wF03UrMNO2G7p2bRuAQxfRJ+AmoAh3k7nmaq8w7pjsQ9uj9Ifb+MegW+3Ymb1MUa
APPFi6kGUHF/z3Vcx/jHLjNOTywEUr1dqZbXtENyhhIOPBRNiTc2yX6ciSJ4s12oxtbQ6uH1cqBb
H3FivQoFL75EnBmna8okyPrDLFpiOl/BMPfnTkgji6lh1F/zT7wzpFY2wXwjrE4I7H2Z6cmKVEnE
ZKCkK5B4VyG2AOVgnXUZCiKIvve/1x/fViTNQPGA+6CvsAepiAa/QojX9fg1qmo9uxlAL0nkFC9b
c6kXnkojgX6Zg1evLGy/NAUiJe0mJFFjF9Y1Y5O2YMg/L4XoW37WkFCPo9Up+nPjhHJcvnbuj21A
6Us1gPomVEBgIJmBmq1hJ3K+xYYpcBbxIs+Bh9pV/PMKg4s00Kh3bIPpYj9lCnBQtKf/SBfIhXE0
rlq3xQjI7v9TpLgA9Lfn6TcBxyQvB+MT5dWpiGc6Wx0jHdjF76yP1DVq5qXpBeUETw+/k7kiF1fa
cKQo8JPMqZ88LUhj0Bx2ynh6iPr81ygHWA//b3Nug+2hMkIz1DUlA9I87ivhpDsiQCt+IhVY8N6U
3Kg80KWh/iHR5mIDDsIuAVp/lXE7fSpDtz0A15KAs/glsyVZA9GpL1rlSIkRXuRH04F7G279qVZz
QxFC978gTzZa95boBbswHUUJc+/G3g+IsVNo4HzJ6gCj6a0+OB/CSOb6+K7MhTb3IC7sr9aJ8XM4
jJdRqcP3RL98OcI4EZNYZA12uN+3AhGdviAQRt9/c0v3CCzeTrqNn+URsAxD1GvoILYNmKFq2KZ9
zt4GB2AAYQ9qEsYBqwvcZtC/Q4AY+/a9cVOku4sg2TD+vDtxVCK5w8RLnT+p2scKrVTbq/wBmdD3
wc34oAPkLhgXOtIvxxYGOBoZKijrmJ6ZAnfXeJ/pmR2BRMmqyrH4jif6XQVqsqeGDw01d/pH7MrE
dc+y03e+MxU7gVNjFvF5JKx1tG8n6Yz5xs1P95GCnwHxOaaWZ0gdwY0K2j8lmj2m3+QAf6d5zaMW
sm2AoXAO0v6s/RBdTHp3z/e9S8jvsym7x6rEmbWFFDoDSpMta8hd/AeBJLAoojkHeM5Avl5jbii2
92gu967PsIKPva09JiVoqMzaQGNeqsZsFbpcJ5Up/lALJjS8SzO1tKG2dltQKtUAhC26eUjkhRlF
DjmC0lcu1zeW+NgS7kwdA+GA/fBtvgxacqzlA3PUcbsOohPb9i9+YMucYo9ZnyER2AvdrTLIaapO
4h3NKWTmp+xuEIC5hoa/1qdCgTLx3JTv7y6u0mu+4pxf+hnquX9Uv6AI+2iBYJ/NqBZk3q/HPb6z
sl36y9QhVamp2PvRWn0tkuiqVBSDRQXa6/QnS/nIA9lI1tSGpIXVv5xMS6HFn72ijrieZc7Gy9tr
4NAqVVgt19z2ChQmAxrJFtUM6y9jf1KkSLRG684VbkIuFVhoeOHDRJD7nGyTGhnu/QG9ZFdlfgdi
DRgrgNUtGnjf2x2r3Ek/CgjGIt30K1Q6o+jtEdb57scSwqzK3fU9ac4/Ge0YhQQLpCNsFqn76n3g
XavndHSY1LDWDEFDT218pdrWIfyXt1n5pd+VMf24et/dcRJhZmbLOBFHumTzMtuqsCv1I+cIr1nd
xlJRn7PZszpClRMWu6N4ZAlfLLM2ODzPvNflrSQsUcrYDKH8CUHf/I2xvKFrYogKaCAsUPRmMFSo
mkD4YvIeZHjKUtAJyFHA83ij9G/QFI8GRNrPru0oY3bRBKrR4Xf5H9NUAvkKMz2Z6HqZcnvjIgwj
dJmT6UVvjG8bNDf6oOE+ngJ7yMLNKiMjJbgtY+Sm81yNYaXsf1EDi65fV/LrZviSBK0EGfJikA+h
ElhyvrKnMUkLjGHBWhB/omlg1tEZ9+KIzGPenJlUgqhDjHKgTaWM0L1hoI5hhQZoWBE+EVIsm84D
kcpnkS6pf1/VXmSYgivISX37iRFjuz0CzDA5pxnS8Q4hPuorehWRo8vc1Iyr00SgkHaVfN+bXLSg
CHDA+XgX0P7rOgYaVbmnAIpVtUebvwm3mddlGhuSaqD4hfxYFToDnmtRGqHhMYV45VJm7Z9gV5A5
jVrMUHsR+lRdBcq3/aUGU++8UZse1Ik+3vomf9+UZxPwgI7AJxNna5L/tJRtXCdJT5RmvVqreFhI
lfE9fgVoFs8xe40VSML5h6MXqND6NEitJPB9VdYsL/Z1xR+rTZSVVBa+DtpoXrJ7H9Z7FqLl43k2
RVUSsLgQfXpdhJAI5PB6Rl6baSKmDfDgTAvWWH/2x9JFScfYYUuFxs4uuLJeTZQ09r8mUY5sK+Eo
zUlmTG9VfZ1CJ4iI1ODkIjm2D2D8+dluMWcWll2GR0WNUqDulq26Ixs+yTKHusSQ59oJOpZNi3G6
GQGXt0oGRPxBNJhTpfS0E8A5MABCRtkpq1ILzLM6HXPwlGSRBR9n2+mTdJgeSW155NyOhV3yXXUG
G6LTFlYnhJtv0YDFT2YIQwzx/5KJqOyvdaWKylq7CNRdbBF1MQtrXuSkqN/t6nbIVdULIe61mCko
jfmxgPk7r0rVBTi/Y8koHPVU7pPlatcKHOMisTTzYgPj2OUzJ1U7Fu8t2Bc/383pNTP+6oOEMXCw
2v28dmpZ/X/guUY1EJDJP7PWVdS53HLCXxp/DIEc1O8ri8/Y6dS0Jr8q/jKLScT6pKn78+NefCZH
RIl7piDZWvj/vPobZ8PG96ZS4Ee2qWQev6+AnShNAEK+SdSnphZ8MQ508DWlLgH3rJE0lR3kh6AV
scI0fRXsk7X5JO+efBxwqsoGauL9mA930OqJJlcjE/VAdqz8WxXg/EzDsmZaD6C2pOcEfPBorves
5Wowx1xHjpQxyq2KVZxXvQhHhoPYe4vPxOtNcy780mtVaBqK5RnbWfO2OEIP9/U3g5AnRaVWXVyH
GTxK2ssuknJIXVIECS5VItnL4Ql17wQQr1ukaQVDyCXm3heV363UE7BpPOD1wJQ6Yeq8ck7TlBQv
uHxKwbwdnwkLXrr7U+xcBEnqaaCsjLYV2HRjwbHOus3bnUXobv9R7tOKkKV47Z9KAv5Vs+DVugWs
RcZ8pO3MTYP2kPs9afaNz/CrEsxO1GK49OIjAoEuVU1sY4AoLhppt3J+YBw/mT+oanSYEX1aorSK
Em131A087HeUyA6QSpRAlqsMP0W5k2T6rAJVpBrmLfmm//XWIQ1Kq/sQpYQASZDAWS/T4Dpsr5g8
RCdh5BU5UP8cHao2yvKaB9stj3+lk7sYsAk8z019yaVa6fy9lR9nom2d2sPEz10/XzBjhZv+ttrZ
hP4w6MY36h4BdY2IXau1EDEyjrvmvCTdBxwmIkbDZXMMV9ALsqj7zYXz97nBd9PcLB3HC9AFROIF
fb6hMVpHv5mh8G4UlmfpI+fzZNraMx6iJicU+Breimdfgigtl6zBfGjsElCj3xNlaK+Qeqdjg5l4
WzUhIEtSCuYxzf5yGl4jPPrO0duJk416vTB5SUCT/Nyfwk6UjTdIitkyasFc8EkQzc2mA+R8qCAU
cekb8MgVGmvNjARiVBY2dhZtytLSExFRwVRDTiAP6vu+Wf1wbxTspKzF6BgLwiGSSd1HTndFvtKd
4TqxcLMD/mcCCxWzOMfaGW16pONihl1RZCg9M3KOVUEYODIFCltCksFfFc/jUin6r+emJOFSnLa4
ikY82dVzYBJByQTcuWa5U9v6jN6UCARlhouR4fZYTx8rlQ3Vnc3U3sruaVT2z1EVjm6n6H0ZBXW9
TdZqL+VY6zy+vWY8SIWZy97GYRS8DyjOJVeeh7J8ITe0f/4Hc/aTqBWqNQsXOfizVeGB5ZVlATEV
wcjdUxyAuDZnu6Oqa4FtOjrmcjVm929OuB6AQBpua0Wfey7ipFd3qgxncnc+GPchhg3kbD7Hr99o
gMGTP52d15DUPLu4CezyRsFBJj6AsZ/xEuiK11rv0GSELrTKYhHUQ4yb5M7O6Ua7LdySlqp1iiQK
w8euAkYFL28EwhlVg96BYqXCsTVEYuPxwiVeS3su0J4/xdplfyZeIPwcMTr10kqyYsGovz19e6zm
ys2bhNQ05poFZb9RfXT7+V4iKinxtn7ZQpvgVh+kSv7Yukjhtdpt87b8UAD0mz7ZVr8OWhaV6U63
ZZQIgfJXd0m/SlUiR249iHC6tUduq7ScS8EGbxGIryQ/MS+lEfjPNMuT9RRgc+dnVcsBXlTRfsZ7
e0/yGdbSQvf/1DswPUDqqFEXlOxLGM12tPVJbZ7YSHCoHFaKAL7y8Ec4Er5Mo7gYINUvf3dl5arv
2IGAEEmbvccHPADBEY7Bi0PWW+S33vUU5PabwNwNJdsHyy4lLmm0kUWYOdsU+dgPklmDq8bVL3P2
4FZe37SJ7jdUvathHq/A01b8HfCe41U+tSjLPDQZg3duJvzHS7hMwigiM0pohjiiFPDCD/pIeE4w
mDJsX0PjVbNtJ/Rh+PRwZj/vHdm29a5ZORGXgnf7uiymY8Mm/ZclZOQ1J19Ou2iLASgYu+7M6Knm
HfnGl3YxpbQfoyf+qr62wNzyPQ+SxcqkzBqghMqxRBm3mK5h0Dhk7pQREUtqy7auD0nDcx7zYc6e
rW9eVjPq/VfVpSpP10nsirOc7PCS1I/wP67R2olJpee0HZbhWcvEMU96VWI0SseNoudCpRFfT62d
zKe67x5IBWwZIKGffBw6esdLA8mhzZGn96uF8Qbl/NlhJZBeAFj7ZGOHpszjxHTG6027QkrkBhT4
5FZTFimqfsUpBialpeKMZG9V3hq3VSKC/NxpvAabJVSTh++T1vfEu/l6qnazZEdt81wTRrhfAbG1
ZcDiD1oYwj9KBdaV1BNQ7svs2GPmhk6D0jAwVph0FXRsqVrAYKA9xxa0GZrPA5Wh6ZiHY8+emy/Q
XTdHoHspabIbCXN/sRJ5zbS2YbI34prLkge4Nsoyv3sIOgnqyC8BGRPNnbaA8+H782r+sTxLXHf/
OZ2e98+DHRwDSHSTuLEKsiuox3tfbqklc203FY2nnl/Iw9oY71iE4hywmW9PYvQ9nqnUFAOL5cmo
PtXwH1+oyZPg2If93d43FPPy1J+SkbtTZDr/O79ebqDbhywpuMmr8u1KTHLkGSqoZGaP7p93zoxZ
2HI8zMDR2JEO0GO4rSRIZ62+JFHalWyn31xdBhoD5eXXgPb73fX2Iz+XvfoH6tEAkKvrj7CpRN4E
3ION0v8l1LljJalFs9SuWRjxldvBAJo1VSs5eJtiDTmuIIy2pUewKr0YntAmhidc4IwJz02ZD721
w/tF3hkY3rN/kOomXoVD1kc3XeIZfIAyT254e20SdV3pZYIawFnvPMrleTOx9HqB+fGeCccufhHT
Owng4gKZwtEMVeaMR9R+D30jbD05lsogoY+uBdsenB6VrYHiT16R5sy3JxCd64RZyXrHw7I5Mtju
iI+s+Hq214B9BiN6+vRLW9PAKGBqWQXyFm7SYh7/kF5tcG93LnuWVKEADBk+KAqa5QXYbccp9ODj
9OFNdbYkzo22uIBBjOYuROe1mIRDAAs6qeAf96x8uaS+EtI70h4Z5bBiD16kC9o10KSKVzqoiRdX
DExqu8zNRuGTeySmK/zg6Pq1PETw3ZbAMefetmVjJ4s9NYbjpcZM3RocVLbJOU528BLWP/GqLJxC
x8Kgm2khBPF8rF1l2eDwFsptLB2Aa/TKUpV2VEBucRdoBmHnfYJSkbflJeRDV1gbbRKByY9FmJbF
MThf8IfmQBEWWxY0o+1v+fPH1yQLIS3OmqyIDChno3OsMqLZ04hG4D9rEf5bBt7gfbpmfz3BKnH7
JF8uRDI8lKVUb+b5vV40sb6bCp9cC5F7uKfMuFGcbWbVhB9g4M/DExD3fIT6EzrKfBkJtQhLLCIw
DN8HlVdg87BdbPzwCq3YPGMCJxmEMV7gbNAO62747pDCLqFyiWqhY998nE4ZEUvGdqO9/FbtQE+n
2b5e2WkCKYvXevEPmXFXl1SFq3n0DdBiAnFGZ6Z5OIG5PtavhbmOKRJiy9/0CKdbBcrqkRQwqZF1
BUavfLRTEFr+K+CEvRhjNpKshET+vvLP5o5j6mZ4mKhfSTAj3MRK1aB9lgm/dRTMBOe6144hQJB1
AGxJ5n5RdP/7lXw/uKttU/WLVzoiSs60S8pgk8IRPXLfYRpX07zUh62tignV5ZDrwdU3VEhO/8Pd
g6cPQY0sFj8uAO9esPZjTrsitjyJpkGEqZ9qzlJwvr1sebHs2/hrCjJZRMQ4vcc5jhKpoqAWhrjg
M1mc8+BJY7sExSvYZEa6oXyfh0ky+AJDph6PU7QDZqW9nNkbu+Dir0Qk/YDLMuPkoWdK38g46sZz
iGa15Vl1nncO0X34K7iyVCVNpXmWRZngFgfPXArULW26fl24fO9JtgQSKReXktBGag2HubwebVOR
ZyNPrUpAslumNqPV22wNB/GbZ/x8PH//ArNV1Yt+OHUoev/YKTT7kA0q9d5PQyFpMty4ZmR8fTXS
VOhYdtgCGkikSG2uJAi93to/yvA1a8hafVBJqZEUAw4PKz5TWwWe+0OeZkx5aleYjbo5O0ma/jOf
o/GtfcaZ3oinph7a677JfWfcCbCsm4fJnsXlCAOHEh3sS3kp21CJp3cs+qpgtfkRetdPgj9DLQle
TXdbNAZe878hmQxnwkajSuvv1pLyGsbevuC/t9thh2idKIyeB9VXYrW/kH9mSkedUJnEEUv8oSLc
ZlG7+xWWqOsu3dRtz07rctRjaTNyYNLBEewELIVk6LK263Ibw/dLgH5OvPDADxp7rm8p6GsBkuwD
gG1Q+wpvVhJ32c2FLUkOsUVKrndPqsRUmPNDibcYjDAjr1sf+qu9gdBtQ22I8jQI14eDl7oHboGq
6R2RJXIG6tFDp6K9zpHsTeDaebXZG75M/iOr1ntpQbrukxOD99gGdOfmuv01LVhOdx8rH6Tfr/lA
wBg57Tf2AIaqBjexe0HiFRiI5y+kQeG8r28r1AMxOYAUy2RwuXI4ZSS/NvGQyXxodt8c5g4AMXyH
1FbSIb2H9ONuixhsqGJxa593pFFedmUzVfmXJ2usNFG7ze9u8EJ27gChOS9s3Z1fCf1eiPqwAKo7
dh/JWsE4p2+/2kK8bTwnDUs8OL21LiT9NrVzs8pX83xbpSmt6SVm13WpShfAU7IztNq5kgbjbr+j
azF+HuV1dvcSnUXqcgyAJsyxWX3i/oyIuAIZy/W28FZAezDeq1r5bH3Lnh71b2bUEEnlKy+fsyNF
PLtvISYXZRcc9UpA5X8rhCYrr770fwsro+6NHhJetIAZg66YQGKG/X+D7wcZ7t0ncgMqOlnYo3Dg
FgCp87J4ax4JT+tCXkYQ3WFoSA1IQ7/eMOesy+bq7eHK654/l2ZZAnJmZ5VC3lNcR/3zufvzOpKX
vbQi7Sl598TdxCeNT7cbuWuHswSgR36uAFVlvfmU/UPbbt1RcAc8AgwYtJw7FrXt0IETZqYvuUiI
+4woPw7iQmGoNtm5NO4QbNHbCsvL9PFxGZXEZM3VvMIoak9YC/xD+k8kI8tlA7Oc2TYkVwpQT0wj
Bf5z8UFFoCST6GTfoWsmyUs9Kewp8JDb6a8b7dZo+BlIplQpue0YVSbQ8niWQmun7VGU2beZC05p
pZiU9ZzbbIbB5dkkW9ysRo92VGMDl9vzX077o/4SzaTSPb6F9sIKyWpU+OP1A4+ntWc0mPB0RXWV
nkOkjHh5tF/0S/NXzbCgYCbP/epxDNBOormkxqM5dOZUji4K2F/IBhBgjNqJ1XVTgzUsMDbed0tC
SwZWspIDlOox6x4MnRAf/RyzThfwQP9E/LTeDyRqttLdlz4RcfgMlV92SSaiZZXYLAqKXHtlZh4B
wavh520tazqefmKwH8k/c1zWLwDkRGeGHs4GGfb2bxiOL30bZhUcsHekP3aFlhyikjvjW2GtodJo
UQvSpBa/99ffCXlSLWa/J/44DKJ358/EcOwg/CKbp5iZA2ZZheTtFrWu5j88Fz8K5JGxnRk7YQ7a
o27vX04YLnGef+ZFYflu66S35WJMid+DxvaqNQsf7YpnDtpT0JRRoS4uyUDGpHZbGZCNCFeUqLti
vj9pk2kp9BB+DwGgWQ+x+uvewZ7lCJBK/8HPUJKIYPMsYtiNhxQmU86uKriwUptr3OV+g/2TkwZ0
x9R2iHq5BZIJxLBtBphhr+Wqcwm+UtgIUVTe3deo+glVM7ydeD7NoqGXyWfL6GbfsP7+SU606Q7m
1aWxKvd908y7TiAaiswEFyBTr3Cfcn+D3DIQJGTJKyI7A8Yhon7/pVopTX6izpB1mAriKQKXRvpQ
+cRmyCNvDPL3IgTtK3x+BNnRjNbVvnmy4qnnfPfJRXBdsqQp8XMflKyY7l1vBw/9n6Wr/QOBJgmI
nqplMGzSh/hhVmiJbZMcyphmjVbO+Q6bzMBii4Q5Cp7UGxyiLjpntSkG8C3tWkSh1e2+EkG1RiKJ
D4INq7xzqpYiIPXF4m9UvOYKhwX3j2WftlFoUndUPbvGU+4h1DyPk+0IjaZWRYqGogOLM/P16S3E
6FeIvG0oQtrv0AW6BvzrsEUCPUZB9INLsAFIbYE+gjJ2fVXAHDvGwtFVAzi/tlNhiLKITStFGVQp
wDVHMueuu1SY78fXfRIeLcsZGeRQTjk4VPzCkQ6dc6KiTxE90ilQTmu9r8bm6udKeQxbq6Doftrr
Mlb+LfKuPszTOEH6kjdh7h7zeIfbS0+NgXIwO+km/7SkGhml6djWSlV1kVmd0UBiskKcvmDhuXii
qOJp+hRAeVb8ELOjfFLaxxUZnvy9A+JZO3qR9fP3DF99LztKW3hkaJolW1dgvVsnwUSyooZuyzBA
xb43ZkKZ4Riye0V/G3wrpk/uX+Nf1cNOaBIUA9nZABN1uYYay2yuECMiWxxZBj+hCXFhlXjnwXMt
9O0gR1z1lnO2L7glQNIZSmzUmpwZod0ASyLuV5cs/RvFWd9sRmGVChTsEDcTuHu9MqtZ9CbYNddd
UfdHYd0rJ1G1JORO4w+Jw/VpfPOO5E9wKeiDlPjhmt63beVNymfb5va1yx2nnZJLnD3PUMAXPYCw
4L1bmgdXInbDADvxRSZFEkyLpfATbAX1HFN/uRlrsKZBkMjGTu6c5OIOYDEoRdCA4cAM0Iscddmy
+RAPkqWdNkm9oqif+017kSQzubGsc16mwVAmT7gmx3SZdyzUH3/XrLUgJkSrVv9693cv/ytj27Qm
kW0aRfRA25fg4YrYECoxjpWhsZq3Zq1gcjg1lV4mZpTeDYZe6JKTnG6MkShF1sTz2FUL7IOeLxPg
wizksgj5x+qgIMJq98y1DaNvJ9ddWQoZ1u6rBmBfsV4i17DiP+iC2UEqlMalQgq4qmawkB94wDJS
C1nY49owCr9s2I8U8HVi3R1Q0EzW2qTxLRKbyOtUWMMLSZJRnExsZXfn3a64eHDqsfXuIVLkSylz
DRnsM9rLjIlqoEqLnzDbrgA7SJOKPJBSqPNUNhPyAL8kMIuF2NVnb1RenQyaOzd8xwndvqpqcYVM
dmN9lH2v4A8IacOFSpkEj1zzMXlvozSub+/oj3QiBnx4AmPYRyoJs1AqIprZSQThcKkJW0QO86KI
Z58OGllFDMOXItgR+zsYgqVJoyrhUUowq0VdztG3M1OOX9X4kKZEa1tlGVw1RWdZZw2PmmXTGhue
QZJGpoGlGUy/KPbdrbLfFR4FJC1/gwh1j1gm+I/0eFrYEAOq70SCsNghF6bOMSWjxQPK2x4ZAdNW
V8lGAp/PO/HYtU9RRrgvv0kiEntd8QBKbvEtn7EpAmKunCEYTfPTIp9n+RaliiNx5S5xq3JUmKPg
Uo1ObyX18/h2ZQFEb1yG0DWanGXgR6Y4A/hYe3PvqDyLOLklc2h6EXed3nWUxUnRm+6q8PMb/hS/
NjdCrHJSMFt6FK7kI1t5FK3q5j4gqPd3TBvpzJsDixJDQfOUa8K4bhRT3I7LS8Sux+7mxkT1sJ71
Yy8sP2AeUukKn5JucE0R5nbqo6EYOd3R56VvpaJwwljcPjVkolsNwrPh9temHDcU//5ann+vC7oC
oDQTI9Khwj8W1QgC+S3wwQfVoIXjpCCFRt4ifEOIijLPLzI/GezxdDxS8YO2SQpkhjQKulGCzMMq
2rSeaRH8YY8qgPn9mDh1teDJmFqvoNRwYg+U+QK70Uol+aYpV4GiUETU65Ki4XQU6T3qoaycNtLU
sjeBw2XwQgNeri4B05JSGc81mVBodFa07dKq4S+iyRMmWPJuZ1MuLj1FYErQNew9KvP0Q8kl3VBr
y7tmSRe2FAaz7CHj7zmdEkOMulZElEH5OtWpgLOf0wj6VME1WtzYfK+KlIUm16tK9vkwColjoXwk
uA1es+C+k0dyWw7YyIref7ZZKL8KUEVYdQ9T7CUUiGL87VwP0mZ26fvk2n78C14gPEcGyBE/BGf9
38MNK3vCQSMUlsOFxrQuqBDG8TTz4T3XxkaTqAoPgM3MiekVXJDNlOLn6MC20EyaceuvRcMSBvdO
8UrG2z9FhbELZNWYv4pHow+fHJEnYeR7sBwjpCQAPhTMGOf2fWfvQdM9TmDsrf1fHLhAlD7tkVNa
tjDM2t7ucOmpqw94VG4thEZfV4DSOVqsqaGvjMEQF5ZBrEKCFiorRus8zpHY5eMwUrx3UeRdiu0w
p6U/BvLoTFbU/F5+jHJz3QQjcUE+igbUazv58/mdXzuASeW99XK1qCOSTKz0mVH7zm/ka92Bul5w
49Hty29e0oRGBbKL8CGgjgHusFzoPsm4QUbio6GZaLhngaZI4/Lim56/rFe46H2Sf/bZm0CSecQk
+xFVGt+NnixoMFCkitUkyzdKPb9YTpXStN/pefsRHK2tgfMPb3/MP5rJ7fTLq1zWpj0+gBgxatfO
a+0GPD1EgvOiy2mscUAx1HxhdwrjCABpC9doMPGNROjCwsgMiyaX0vTNsnQYquZ91fOGZT169It2
pBmyrANoYftgQpNdTxzhhQ7WnuSRH+LsvBaUAuv49pUK+ONkxYGC64lXT9RqA4XZKP9eqy5yJcY5
1hGWxRRqm5p1GOiibrLwyhg0yqfAYwEdta0lvUBZg3uu8+Sdhm55vpKCB+57GKPsObSN5WRhvLmv
cyeYxCeV0HGF0kkY68PIr3vo+GP1NRX77htFlugALl34fjF0w9+AndNaxb8MLeexdJzV5uxyguc5
gNq0fvLoG0FZAiwaeuBq5VZHi4aKiv4AJRYgEKgf59UVGO2Ry3//jLyfhQd4sD2kLKARSswdxuWO
543X4jwBue1slMSRwNyCoOK+bc29VZzgWTsnO/wmFRmI3Yks+od974D9SxSNuYWGUz5BJmFXRQ+z
rvv5lrGWB57OUW282fjnzLv9rE22mYbuvdpVSyWKHxA60vSENRzsVjAcRiV3X7GrUQs9J1sJPfoL
Q562ik+oECGDyEjqkqJC71seELPIyHQRlRDtFcJWylhxrYjIfFvn9lwv0ZhZt1wZw2qoylEqOdHl
cEyNy45+OQan+5YvEH5KznddqkSx0WOYl37qqunQ3Hl7CkimsWfJ5OA6/13VJl0kIlyh9+AVHY77
/bI9J3/UC4hMvpi0UsUxkPx55mrMgwrDMgPQkHiZqwWA30O9YxQoEbdY7i4JbikHPD9tF4HLfSpa
Ko41psWaNqMHf0FYgtPCvCFcmNZJh0b4u/r5Sj5EvXyiT4qg8d+cpWxGNryn4vBlWfP5ugXL1bC4
LISs5G05xm4X9Nqb+ko1nPb6MejFQG86o8m1NYfB7mKzX3Tb8dcO9XDYG/r+Qqev4VWb1dVhQ5h2
ioaYhoFFoMyZF7cmwVTsiv9FWUd1bCCjL3GLPhcu8wBDpF+ofTJ0xScNEEIPo9MBXhFv+cF20Z7d
a+fsZFQ6IWURTn+EtHduHMwBsn1JX991l8AnEcOgLUdOBqsh5TOPAnkuxPnnjnvPzZby5JsdknMf
F2XQxyF9iRpcnnQkZzAZmFamRANyveJ+9CkoiBf0MruXC6FPHnwDv4SJGPTTelU2ycutKR4aIWpP
mnD/Tej2wOK/6TnlWqby7wC0/dbxe1pRrVSwYAziS0baP08tlbFh1hwgzX9fSO9prbsUdR9w27VO
lkTlYZAnPZceoJDIB4IuFu7PotFlSJzB+9bc5xAt0HmGZZqQlidJdBy2f4zazlIl0ohoFrGEXNlz
pXyv9enirz/ln01FvCaBJA6sZ8ta0YCpHaXvMPS6NOzIsTWtQ5AgzHP6U7pYoiSGpCYSQoLPZFKX
rwte4hMkNbInynXVC7Wk0RaEXUE3uBM/0sJQGNj0t+eFk1h3vc+MsI0IRY/GAOGKJ76xJUpP/aGe
yNnO6d+kTDoKHh13lmksJGm8sLbkQ+x5zM4t2iqPyUMfPYAlB6iPMR+cc3jXcz3RSpF36+jea05t
RpGOLm5WdDvoAmAmNDm1CNO5CN6gSCY5UUB/XXSqVKm5t95TjSoa2v86mntt2oXnu1EuYsbx6uBU
yC2WVcCZs5hPpXKhfbUxgR0hho4ancy8U/eobofMkjGf6MY1Go6yO2EradOkMYskSAaYYVvI+R/n
TJHBgURzd59Xhav089fWO9yABc63AjX3XzGsC4KfGMXmYvrl4tEtMBSrxdUTxkEEj3twWhBsMBhz
KEZDHckqCyhQTcGbMpO71B+H1S2b35/LX299n9gJ/d/2pVByovGaMRZ1vbx7Fx+4jpHojvfiaylg
LvOpduOF5z0UWjPnrLsmpI4GmBMN9OAZgXsERqRSmsvrgaLvjPsYAe0ZWuS6zr/KmUpTRENtJjlm
x9exg1SKeRowlLtK7Ti20T/Rp98q//HTURp7lWOXiUlehsHqXNpAjuaXT/V6pmsHKv3aawQmxkoz
kkM3t7Yf1NUudkneVk+nCRtFu8T8YQ3R7VrxW0ij+HDrlYv1B/11XG6tF4t1xtwIEmYmboOgr6Dr
Nwt3kV2/eEdgwjSSRR/g/N5u7yV3JLx+bXo6aaCQgB9UUMM7MEupfdVMwqIm86drNDCbFQ6vnF+G
Afn2EPXMKTGfo8Tb0eI6TVgKtSasc1mfeRDjRhreh9WitAxogDyzZJCQzohOcIHvQVvFd2uxfkU2
8L5Jv6JvqFDvCVLWIasHxJOyRohWzf9HsnePUXDu3wBZzQnjp9TD69CUBou07FF1ZkGjc5xMuHSO
WrzDNWcBmSo/iA9XqMTxo5QHlTIQxOpOgWfYp7QIk+5RvBep5Sg73Vla+NKLPJdkYIEQlHdGNc5x
EFuJOunpAAkT8Ltg1V/QcAIr8DpjD1c2dnra3IJMUCQqFRrOt2oeZno+CyxiOLLb//WpvsXu9yNd
eBXirciZso6nLlnTtxURLnn74vGwObg7iCYv0gx3Mw7Yb25IpIldvPJ2Y05Glw/zqE/ASOE7giov
hmj8C6zd5mMNK8cgGQajvJsZQ1X7pd5PeZAEf5NzNND/MS1ox2RRm6fFt3lyKWjCP/c8RDzHxDxs
Gg+7naM6SjWWWRFXAu/7IPfvHy+7rcIEMw3zZSaKfVqMTcTVaou9C44+kl2DgZjO4yGgvhq+OydW
sw+Vj5xDmff+Qvn3/XQYsBArak1+DGr3P42eZ/LNTe3p/XJvKKrBofIfnnJWzeNFfhYMD8TI/dhg
pD+FnPnhCiVY8RGdfjDUtwdKsD3yNsXHAvl9HY9g9Qj0QvB+S6OvvmmdXJK1LfCC7j3l3lR7B8F9
b6c6+DGA0KOgvOYKko7i8luoTwu0ymKXrJ31Eh3sIyy8npkqMuV9nFoqMmf1vYfQKacYd89Ai4x4
T9V3hQv6tEhwbXk3uuSCF0uhkiaEI6AD+hJxVOfu9W0hDMI/kmZbgPa0WxbxrNdjLAX21zK0LF3w
ZqJE+HlqtqeaSVWFJsxItceqn6RPxY/jEjcFpQK/RIm65APqI0/ikShXkcGmoKvW0uGTNOSTRGiA
X/euO/aBm+n7clV3fmct7bGVSfqc+TBYCiTwt1qMzIPibMhVlkpr3L1W1uyx7pk8OW4lAldrqsF6
zPEUupR0q5IBR/xOalnTBeDf6Mu505Npw2ibtqHCaYYAks3cF3YG0LXbYRprUXCZxoVTS5itZ15j
KnFoxGS8I7k40Hv50LIYa1OX1GtRi18W6Za0DJr1VlwLLHTFG3Ut4xhpQoeaUzMYPJLNo2d16jg8
CE9tGMaXpexpGv5ALsVqxMeTIGMyA+KLstNojXUdcY4OhO9v+TlvCojU7KxPYx5EVZXnD74HCXQC
svwPnTPRDPSTq3gjWFahgTC/JBJdX5K2BM3lJCcOGCIhJxIvdOXfDwbwP5UgPf6YtvEvLoP09vSP
/kpzVld+r4Sp/C85qZFiN8HF3LeuGDuUu88yO9rieHu0HN4J0bFTHN3jmNVTPT8qLqb21zniijco
VBf+2xyZQDB2x6/eCE0xNExKXLg0Cv3kEQoOAjEjRFQ5MhobNaJhhTJVPq8h82iQHyiUSixLvLvY
ZOtmrbBG8F9DS0UbHkwoM6XOhTYiCTu364sMe5TCg+Ce5e0dEWbIas0Drkm+jESD066gUBbDVOZA
SoOU9XFO8kwYbVB4WDqTPMfLFJahZhJ5Hqf6g6+bjLiT9cbXmGySSGTvdr3oUe9TKiHEEokdzLjY
6gma9PFPWHnPrwSWd2SOAj/UoIOrIbVbftsMjEPcX1RUGbHZP8rePZYZgNhQH0eAMfY9rYWdLyzq
r512Ggxacy2tGqtjErBLX6XqBsJJw7EBvF93PqVWu18qO/CoYP/AQpEhrwsgj1ij/5U+gujp5ymc
QM6AARLtcmdqAd5PQikWj3/Qt4OslwTX7OnQD20VOxrIPXxC5KLQ+7EhyRmY+LAJI4+MuVrfaRg4
r7o625idYcIXXa2PIcLgNHZPTqzP4OstZhYTpPKIpH1B6ekcHcNUdIZTWN2ylYNe4aNoueQsaYVx
d2Uv8J2AUCtH8APFvSnLCGEjyrmVoz0Kz/naHhdh86LLuYqX7t/WAiXJ20sJRFnJ3zJ6Djjo74t9
rDEM25bepN2uFc1yGcRG/ncV232WfD/C+d9SA7D5pUi3g85oevc0Ev/r00DXo8kzMZtSC1+PtwhY
lJ6sQafsegFsubtPcLPiZaQn0cXuemTbHwYHF14+z3mnTr8KAh/hpKW454Zn6IUDbtIon4uVGYV+
nZQSQ+HGjZ1rLWhc7ODGlX2BJNFuMpCulEEmmtV7D68yyQmYEEDQzTSstJn/sui9RXIabvbal83Y
Aq/KxoDrnuR3CGaMyPryRZ6RUm1yOhvLazLtia7cVvw/KXFgogRlsYGJ/HZoSICGwNhP/rUIxjl9
efAYdicjBphFEvnGR0FS3cDpyK0PPAm/bSskAAWv7taX12SUrsdqEo0yVFZNClppuZ1AcZ92wmdG
s8QfkVHrmHkbi6ADbCpYNJ9dqaCGgtaWzTp03lyne+M7m4ts3qEPk02U1+VXkw7TeW43nNcyUNAr
YBSe1f0Pnp2EuVodYpg3IyYAv8bxmeocNKQlsClu/NurKK4cTxO+JuYoxxJmBDfRhpwcw5dsk0Lq
ui1kY7XuWCBiYYx0VJAlQ9VyvGrtmf4DC+E45LksbnSTEc9qlssr5IozN6vGdTtJYQnY1kCVETs9
zSrgAgkx070I2K3RbVS6RlgQi3+DI1MhDg0v29PfBGYs5XF+GYs5w+G3a9FBEMfLWiB7As//o1tv
Qx8tzvDtHK495XGN8twhxIfLXFPUeHDhaxEqpfR5gBz+nWcLdHQ5xprQban116PdzgIWrwQFCcSG
sS/TK8vyjTogiLkO3+A9gjbgCUFHCV6SmDnYR6MwzzZHe6DLkiCqrcjLo/l8qZbEGJxhLh7DHCho
Z7snbuGtaTJ4mGUNyu5ZxVzVIlYS57YVmkfbT1I44xeCkA/lUHEGGz9tsdWQr+BY/w3JeDKZW5Bn
bioi4+YmftMHlGI1gJgGVjZdSv2V/aSsQa0ImSrme0GXSY1gfE+Qkznnv4QqaE+4+my2Ny7Qb2e+
WYHHQJ4kZO4ASgd3hQldxov+6LHXUB0WKpkStWd4xzXfZnx12A+7ombtLdDEwp9oNd2vEfwvj22g
qibFShwjbpakEuwEc3TNq6dotbGYUtXQnAcIOl0YTb1KtMn52VshWH8sFZnrpOHYpoRU2yqkW6tB
ODgC5eYCEjVXiUJRxokXmwuBIJO9XBs8xR4XVD2s8R1AJcsx5tCasy8NZpBHF2bwrCaqwEcJ3pq6
lxGz2F6gtTUXsahzW78HnHT3pSNqM66GNP7fmvXcU2WfcKuftOIkRRFLJGWOPM2SAS4LOjtlDeT9
bdCj6kWdfnGkTCkvl2HcBLQhGK8sF5jYN1NJXxxfDEldMRCI/Y51aX4+cJJwNVTNB7a8v4Lh1aUs
kQmURjLl1NrFtHTsxseXeZ2eND0v7gGTEAW6zvN+jNfOcjzCY13QoAbSU8u0JQnJcIRo0nZ4n3bj
K+f6Txe5ek63xkTnAnSj0rcqs3/f5AzBAhG9ASf91km3YVnibRMDbA1LjU1nYBFibYNhvGkxPT2y
vyaqA1reA/xSASyo2YowJn0FN/U/jHnh+AupSwgxjFDDJHCiVe3YWI7fmdijrYJxgPfYnrb5Y7CL
AXCx4Kxt5hmQw5+vuly8wtRJPs3P3dmGg+qpfGqgAbjq+2Hgctp6QWIMbNal0vvk++Rzgr3HqlkL
3LQ4hieqDOcxv71wWuqOk9WOQE994bcf9lrw900E8yrZEaMpTZiXUxf9Hs7Zzs9ejifGrSDEyhhV
VkT9B1aB6s4HtRyBHz+GmFJgd3lyrqfIU4hzOKqQnuj+rhyYqHTGjlPuTk+clxx8p1Vq+V1TRXr0
iizv9vTUWG1SI3sDZDoabWCPyyvRmUXSjWAFowK3uVpzvYUpAk2JJESnXb8pT4MzyqrKyIbXkKXV
sbjqMcUQFLpH9dBm6J13D8k8ehvpMdDQHMcIaRprwN0dYrgU8OhgHF1+3NMupYrHZB2EimGzfvXY
yuLJ6SexVfRrYROQuxocOTMw2HPo2doBss+vr44R9qbFnE8NuTQXZao2xVEf82f+lxQ6wXUPOi6d
OlJ9SQX/CG3tA8JAzmCkzsuzDXUR24rg40ale7j/eDvxZSdACv/C0+7CSy6VeHbtC/6c+bStwCcK
rvwBsuoXxddTW+pQK0HEVT7sB3TX2ZGZM9+CpvorGlW2WAROnmkv+r2qfIWH98l/6JkAB9M2jO7t
MHSIlYvdr6WHXXUE6l4plS/RvojkhwICoh7X5ul8HIc3yO6RSefLMcHAsPZT01x+0+KXD/DReNUa
0S5inrTb2TsCRipDuQPHbDNc6jIgTLWZw+QWeZPeNjZi7u1uIvomCKubin4fosbDkOrA2ddQMnp8
q37S8lOaXptmOVOzmlO9i3kMijPz85qjGCXIBYpfDTmoC45DB0nOCD1JWWx3I3Nxgz7Usv+1hs6W
Q1t9TRdKxP+cPYGI6zuPLo7g2/5W2JvCHrpmN8l0XbbdYEuJ34S75EgwWx+txHeLWXlK2lFB26Er
EjrfaKjlu6nbM7TUzG9SbJ7wIXRbkyhX61HhNkGhlFX/JxwGzzZc9FCbOQLZqmTUCdDcfpydREZt
wuEScsbl+ApUDQ2DZip41uBJTRZDeXybmNpUCvmTe9A2+O7s9sHNTpNrjEuyguvfFkSMUtdDDGRN
vIHoAxnGNi3lAml+i7zX/Jx/XVDMeGrkbEGfdOTV25Ygi5kXnmtwomBFB7MPnjWz03m+UxtPMnet
rcbbAzojEnMbbJdPkw2L+EmDEGVc/2Qwz8x+MJkgAqC3oLu++ebZAQ2vrmRQSqH/aIp6mmJJyknX
Az0syUEcE1doiNXdGqGtTUz1JE3gYTU/E1A9yiDLdhRGU+y16AjT1L94Vz4cwZYi/L1TZu1AuBOq
BlDZmfKnRT2MG4rxzojBSvPnajcL+YAthv0Eoo+e/QUpXQYeTCNr2xMGw6sSep+bkUtRR3WLkDTH
gZZQD1v9i4pGOX4FUb+7C8V9/ps3+aH5OKws5opiddtqdFpUUDU1A+h8DsazvXoIw4fFAogvCrNh
hV/s3rn28jHGE0p6Dl7pat1Z+/vrLNbqLdSPVkebMGY2GSb+BTooxtxPhj9QinFP6mh05QMJ+A/b
5pv2/X2yRlxWqVAjZ1pY8NBlunX+Vt1SYAVM0wz4VSOYFjCQkaYyJWw5cMDqYceQQfDm2c9AOdJn
v7cw57BC+djXPOCRt+Vpb1PatqUpMnkDqM0vZIpt6MzfsZtASa4FrLfT6FTO/dV7DRmMPO9DTZWE
EnN6v53ypeJeR7bwps8JcgjhqFMHVT1jFVyU6u9phfG7CkuYtIJD3QMjphUVULxSxixuqTq2MDYL
8qV6vlFlnTtzuu+pFAIvOAGL4bDAwEUj87AH5efvW57sdDWFI8tFevsoNLyeVHYBAsWqmPn3uPNv
sLddo79/7gJ9mlHmH9dm+pO1JBv9DEqkv7ps4DiSFzvAW59NKfWuLQjHFdtwENmSiCP51tuolSOw
x32ORlxx03b25l65rODHsRgfdEYeIn5h+0ulDQCcK7DddhElw7qA39kLLYIk28dAj3IFwFLj/39i
8EDwhBzFiINLa1Nlbe/D0IY5vlgPTQrM2lK85tk9fjIE0xMcSnyKYbGNpY/E3DC6rTnoHCNX+fbd
sGIS/8r6errAnn03+VLcJpnORr3OMbF5z8uwz9TUlqeWCSHzRcaw8HanQfD52jYW3Sv1hppk0QQV
XYhC/j3WRcAsaKcoyZUGlMDhmSW0Fg/VUoNKflrPDZQ8Q9W/EsfEM2eHrGtsFbMQHW41TKdyWkDK
O3OUuyQn6ZfPeNm7KNg34LL9nfGUoDgPzzkriUBcwxwkq/SmyiFBe1ngy1GgGL3MoGANUucE1PAl
SurQa92uizP3ausv8925Z2uLrOQzmx4mP5eX66KxVH3D3gi1nbfm7iaO5YcM6G4QDu9ACKEkqFDY
fftReEzRzKbxAla6aeFX6ucRldlU4a5KfufPPgA+p0FupBob0BWeUTpdcztc+LlZX2a5ASv/4Azr
4WFYMsWWsbANdRgiykylSD6LlWQ2zqAgJW5TNtyFSAQgKryR1utId3BLVXvZTGXh1a8ZFzwXb5Bj
XRwZz4OxLFadDDLTpjUf5BV7laMuz586/p0ywkisHTDHU6ddrW6XgXvf+Jmq4uLdDC+/DcsuUh5S
bILB2YlBAfTQUkFCavLgFgxwnGKh3MFTG3cvw58/lzFLFpfOLXAsMKIfkjV1HNIS1HOFiAzwz5vx
sSQZLTMC8icYHdAeJ1ruUtIXKG76K0R7yehovJhnj5GO9X3aD0Hnp4ofGmsWMqfA6yU0yveUp1X4
/2hvH6Mzpi+Czt0e8lebMDH0+Yfie3fz8uW1kDKMT3uMWQAmZvDB0Hfryj7ccfS2NHAdfCIlJ1CA
ojIY0IuzB6/ovqpM64zfAC76lPt0hruB7RU+vAGxo/TnQ/gTILhF39jBFDlgYavXhgFKZYpPfsu0
A7ihnZCTF0sLtM2Gj4mokC8CgikhfwwpUiLjZmlGJ8sAyF3pSwBrKIoGUSWhitfMQyLURfDmpugI
T37kZSl0z3CT2epqnfe+1no2mL30RxGBTshDCKnDKQfy3/RCvN3WIAwXdH+3/5jLu7nYmhndfbLl
Z07eyza4vkRpzsGfMsm8dSGkTEd3uNUf65yHkRUmlSnmS7bqE4y+OEqA/GwToAGKgCJQ1u/6zPyM
/H6cORJfHuGsqbs31aKRcJu8uLlGQ6flOS4IjiuPUgSctMAhtdsOMwAuApnLIo1P9fTjyn1OvSb2
7nSJwwcRQeFTFsUrGLWSD5ossv7AbtdQmPChVFYDbUAZYJEdQAKYIzw2KJiHX9CzDvc3NrpGuqTF
UEYu/PMkUM2Ko1J2tnhDRKGLNTqovGHeHMKzws85SPnwZdOazaPHxNcklDNyzxPIZtUYL6RUze+l
KyZ1rQf6q74s+YjpHHAPARErbg0uCnKH9nC6F36Y1WN59COxdOVH4DIzXX/dctBT8jWGfAhW+gAF
8s1/PgXwFUxiKug9HiG3/rQmiZqFTvWKtxGMiIarnfIG/iViXfdAx7pwSh0yBqvYZei6MLJFgduw
jJsl72Os2rdHkSsFpGXPF9svVCYJQnzkvDZraRSym4jgnuP249+sW+uOvOPTqpNk6yco5BxfGCKY
OIaHZ7yeDNEKY3yqTgyojlTfLk4yEwQPyBpQHfTcFvfS6whl+ERthwqrhyt0szy5MDaLycF2d+rS
KCcOOLDL3fHAWtMQq/qcrONfovHOOOHnWw9LDwJZVuFqsiDNP0OEKHVV31ydwev04uXpxUzZwwGe
fF3fMuoU/5OcJkm+/W2hAszOuZmf7rVYGdZZJHNiNUIO8gE67xyHDnEfKUN0+7HX+rwbC6fO1Rzw
bddF02vtnuaMs81KT7MS0nTn7SE8sFC/sdRpeds/qdlnvb2xigeBd+lK9kVKZHjEOW4TFFitnE1L
Ouys5OxXkqDMy/C8Ny3zpZ6LWGxNv3m8LJpQT2w912ZWOptsfqjifnCDoE7S5ZCNgjgHdJFfOPaF
hArlB8DA8SpJGm4U3rInLT/dmjnYX0NN13YxMB9o5ikjBKskfg4xB02mj4MR9zYgHI0TEC9vKj90
r4lz26H93eKngwgvk2GPGB4/3mryyig6ASCaw4WwVxvKQEZGEbaJrze9JrnrMxHNlxb01HAc1Wo6
W3gtGmwa+LPKEP7kxC7eFIUHhUw22xY4iGrvDas9FGab33FNWZALwPrMBkhR80OsTLKafA8va4BC
rdxMDPJZdzscnisUpWyg4Z/5jb2UipsTt32fbfE6us/iKA93x69E+NZDNW+X62JTL9AGlNBgO6yh
3s37m+qLBuoygZ05BBzGx5+AGoutaP6u/+cY1iyg7lq1yy/3qvF8a/vdz+3r+ayaj8BzXIm9Tnlq
YAsb4MgZg8qpP7OteLO4pfHJkhhxDJTNVtrM3wcKVqnqm14lQinw2VVC8pr8OOZomfkxBXyh1CL8
oXUYZJpRAqYTpbPMARTFPlvSRmXhdrf06M1EnaFobksZwq7cy8ACaz0+r+RybygD70IpBB9GP95B
h/JZVEoyNny2Z/9spazdqTtZLxmyK6W6Da4yIucZ/num6OSjua5LstSQm0tsBo6A1P3MfYqG6eYr
pzZ9EJlUqnlkholZ4wJgniW4uX087RKNDR/7yWmCf9mZQsRc/sBTL38eRtIJWNVejEVYFIWXxbM2
ko54Qajz1PUVcKn6QcutmgVV+Xxaln4e78Gzif5YItzfJui3cP3iP+lKS8qxpTo4Gd1Ht61mFCdr
918r00GAOb4156UsLcExosvL15hTLaAKnHn9rTNgsGqwOPLthLycLdL/9OwUOc9l8LH3muGbknYV
JtzMmpJ1tiQWOkP4kmlP9oxR5moIhct6U7NLlisC8FrqpD94xwT1BdE8xFpj3L/j9RtW8mj9NqTI
zruI3jn/ufgoMr5hkezSmKQbdMxnZPnxZ+CGrcGtonSN7zErnNxcxOEi4sr4p6oo5AlhIRXMpIP6
y1+Ms14scqI4nPY7BBuQXYCzQGc60chKi+lJVoj6WqlT/EhMMmPElBer2ZZywPuioQBkJyap0Mo9
MOe7HGEaAi4BO+0SeL8wOo0PRQ4oTnbsiu7lq9bN/eRp33YGar2viQHi1Aah/ZEhZS9LL7mWGOO1
V2TNzdiWGZNdAn2dWiOmpaQ4K/3oUueDVIFMasECAKQbLa4ILO6mQGW+YWnEV/fVmWt2uJa+7Rbm
wEmBZ09KwXrlbYD3cZm+ruHd7vBICMDCN9GPiSQAh+hJ6QaXf0ZqzunFr9sE71DlO1LDVtQCvepr
mlr9eUKjx9neSj0DS8/XBJlkjD4KPOiVHvjQRfARCJne/G3wPMKc4vSaCPoCgjLEjxZyVe4fY/mb
jqa1U2tm9fJWyOqpKgu4dC/wGQqlifznWhAhee1wQ08a91fLlzkoEbWGvzRuD2VqdP55M37Lc/I+
sTHs5n20rTrNxjH+fgLnGwTkH9jW3lUEFIOKV/DjVw6hQZoge8RKJNB85mBPtepYmtPhYIyIjsLE
GLIn5NHq4cKMjvCSTrbqkIE3OMqnXOJ3jXcFTp9YUzBr1R0aEWUtXyMOdTbzCtcrapyXxMkMwBvq
9rE9PJcAny0RGwXPIwMrvrLjGIm/aeZky7CbQor77/MqbRJeBwnOKvFmkRXO5OUSbNUVXsGoe5Qj
3LKCnVQhcExAb5O0HOGgJF9NAvV7FXPZp1lhhp4VriwsDBtGfQmPJkFjMogLWClNNjWgjQlZ1j0+
lpxYuFrRM622xedD+ICg0vEjrylUjCbIwp9pvvA7lu/YyIuYHvIEA6Z2Ei/pYXgOZSe0sTrYzpBT
zT1bBQ5Ru+fb1oHhg7Xbg1VH49cIl/PnKWayOr4Q8Qb0inz/qgD1Dmr0wCOmwmj4U0rq0gizMgCK
U5nQCxpJULnzVYq369ZfqzqvwFJt/p8svXQsNyX5tX3uKBPwPo0nil1wO427lRd6HM6H2FGz5BUe
p/yGnJFxGKnAPalXy+IKooxXpcP+wRD/lgSL8dP5jc600jjrLoMbpvtTJCoVtsTMdy+AYfrsPUvH
zHDeOCYP24G6VCw65Q4aHLTfOReQldFXsRg6amUdtDjcDNXGd05cU61928dBYguUCeMKEXo6krZ4
DHuMgrzj9VoYe5JsPi4qLGj3GW0kLnYoVNiBl3nCWuUjRhm/bFod9SJbFdoM/S8gmXC1TI8rQDG7
OVIfCiaRcf1URVWI1If2xbFpBnxMNHHU7vRStMTgVPLhpQAD6HB0aNtc6DHqntXqgakC8KU/M3g4
dnRifw4zVPA3i2rryJi/FsTypLWbCBtGJ92JzkIShon4V3ubXFP1zSgLn8y9kRVuMhiW4sREJc3n
7X8Gc3mxLc1wLLVTkSmXp73nq2x4BNWV/TbUmKutCx//yRZMUbkKPYQgkUUBT2q8Fhi4MEyhlw9F
z0ktRqQVBJmbQwGuFn0wdnUWCkXPz2x2ZpHD1txUG6lS08oYaMG5Ak5sdzzRTRaJHntGCLvUeLVC
UQXdhi6B9WSst2ff3Z0SkJANyGTJStAom4PeeCcfw28+tU1fFtc0j7fxShMhFvKv6RXcv8+x33eV
Omu0jtyt9g9C9ZosEAYa4yK14hyWg+p1/18RveKftze6qbULpzOp8+93wyIwNfv0u9UIru4TRNGk
ji7zmr6BgWydZF0o9a8o/viZzUP/+nQF0RLmMzl8s9Fie62C9vXLJanG5bgATaT+zsFqJ1nJjJBy
BV9tOcGofm+6gVVA9IBdOUKjzBHPuj6XllL7WKyPdjBDqiEM/mQI4K+o8AKaR+2C2kQxSn0TOYKg
mACFOjn175rXnIU1+L6nSHJ5GpWU5NJqcJtD2ohGnEIOCJhLLPYYEgtnDA+5IudTsfcN4LL83yr1
ksvoSqwzIHVAB+skJTwGu6Apkj4axm5gPc0/n4giIrLpEnzSsbBNzyx+ohDQTryU1S9EYmh1boVf
RLWgUPaarcoqVM3USIVSEG+SEI4HeF9YUnk71Mur3l+z3VvGHD97tpMlT3wm0GyLyYI7gH971dlN
nCkt/aUT8VR9VUbxAJCAUGGCgXQnRH7bWYxi6NtxPjS0lfXEgwuSFjHClqS2a9sTFKMnq1RTdlZ9
iNhdb+SNZb1KbiRamcElfiALmOros2Yl6lpV44pqZVnja1JoTirJ11BjsJHhAxHSR5VT1WCfv2a/
3d1mNst83sjqm0Nec/ZuWXw1dNMZ55kQw1UKI5ciTdJ5U4fUmWIQe8vboK00U5qtMUTzLcXySko+
k9zmvyft9rod7sX39sXYPRpmWIb/22TvCK002cpBLn80CUrIXLIKtZBJBDBNajadNKx2JEazzLe8
5iPuQUkL5bPghdkn27tBrBAcN44NppRY0lrIgS86SPWF5JhYXT4e+RlSC8qL4PiqDFT3mpDfcqcd
fVYmBId+q5j3MqOZj3uDRcc8iGjOyWoHAITm7vwDdkTpSgsTwb8tKwcuP2qJWumbPQc2jiGxOraS
lLG85S3RmhsioL2zXe2F3XYOlx9svKdsML0nFnM8sz/UuBHtQ7h0soIg43p2M1szQ5XUUveUise8
YQBzD+aYJJAOXiQHWHp3zXL314lxfBIxK9e+fs7DwETmkq6tKtVwPzc0p99+Xi9LFAH8jbmJheHp
07nfrBh+LyYkHBcatqxKOaCGLP7VAOdk1K45uP+40bjFws6ou5wovquTTGfkdnEKbavJd/9rLcjc
Iea86VsX3RawOf6uZEn58ZJ5I/LyT8sZK04v1+Gdf9FplojoQ36FoVZU3DiqZRUr8Ls+V1oz5Caf
DzspRGkwYDw1fkCAq2fW5Up9PqUNlABT/Y/o5aS1Bh+yVPdU4jn2OahVOuramAvYFfqCEfxT41GP
KZmtybKFyVoQCD5r9RN2swEGE3bUbT6+cxtKvyM7Rhy61VSw9/3OZeQnntiUCtIKtIvwce5pR8dc
cr67RT8UOXm597aKjieY7w8fQouxar1QEtII+fiPLzrq5RNmCXz3K/z+vU/BC/QdOarJwQFgPHUE
xIZo3T6Jvv93q+PGpuLo20LHLkKwYQ8cpgPObC1GwzA5BbaAe9EskNmLM1S9XlrvLPLFhZiLASkx
opgXPnJntK+BSbVl7i9zaee1VV9YJNFwTqn7tqmZKiPeTRosGWxQHS7p1HuAT4mu3NMdYbPfID8X
QP6h4BNrfOlkx9lvrj0queKcg1rNJ2OCeVhw4faNqjeiyzETY+ol70vL0t6kKbgGhnCAjqik42d9
wpDhndynMMuk2HgrW/Dg/53lmcllxqIq77eA276L9lM/SyXJreXoJoHWv/X1aqhz+Hr3VFGHtLqN
CHgfYQ9cp0qifHXwo+bJaOaioymkHBOweiWTqGQQpcccYYOhsLDwBm+d7WH501BmZrtVNJszrqvh
A+jBMpBDeAbrnbT/MyLMp2cRUjYzjhNDRNhwZJToqJaggLUgGiDIbK7T2nN9t5lVECn16tZDffKJ
gRgHOUhlXhdI9gwFgTBjltI0mIT6dQkZUQq1sot9UOp190n5mMm8DHoEtkGB/V543CDaKDGLpMZY
BLUhy7Bl7yWx4FG98R4Xez96SsZJGtPY7aPQxVvnDm6Xemm3B+NGAlvKjZCmAzrB60SqqCiwyb8e
d6DZXJpny1WtgFD+c2weiRH9S8T8Mo4IsfCYNDPhy/bwCrIxy3p2iAwz4idyfEsWS6OS8QU94L5e
RqWyqqfQdZh12xc2XdhURu/lWwQrIhxw32ORsEyHjYW69vKEkCUDpGmfFnjqdGVXPXngY6Wp6guK
y+MWlHC/hy85+AjYnPlBojEvPc4POqZXpyl0pGqLNgG/O6N58H+ji+P6YmZJMgN/ID7UU1EL1jjf
luAmouJ287WTyavl9zeYHdB42MYb6bKsPDmO6CoSTDwTygJEAtlbniROrzJlzt4c21BTU0mv5bGq
395dyx1eJeS0Rn39cE1mm5GLnr/fxhQXwLB3fQxtRLHFgWQi/NiFqftoC1+09JAYZoqZ2la6pHZ+
NxnCIfftTzi1zWAxUDb1mlnJrj9hYudQfDKwQtezMe/Ys/F3hto2p96kEWe+SnO7WaVowG2CByVh
XFoYoCxGjuin75j5w6lU4hi5XHVb1wbnuIBfYWPotdrwQyTpEFNYYUMuwVT8QKWpL0dXdswiB7b/
/R/bjRfkzs6N0ggdqKDNr9E2+et2pNIzE2d+CDwqNCzdjtLNJjLalujBe3C3PdUjC65vL2KcZ8f7
BfJmi5PaMcJ6jroekTUOKd9ltQeggd+L5cnb4Amaa4A2QCIoz8StIhLgjJSJMcJ7ee9LNGak19nn
Z9/HK9H5L/MBDK8RIq5BhoaYZOLb4s6Eo9JiQk5PwACzueDl0rBBAf6mPphki2iV6ZHnhXZF+n16
VJoX16FsGCLcASy1vmPAa9BBfd4CBqYw1vkPcm/MRolLVDsWf+AQJfCzQrYYv9Ve5R8zc7Ff49IN
A0535/lYNtpyUdCfIaQpY9qUczpC+lac/W/0slEi6kOf9F9pnI1InwRvwTV8G+i+vpIqHJ2m1YZM
fnU+0eE6QQLrsNQ0M5nT/u//jwJhDMyXYs/W6g3z701mKXvQ0nhV+ayt2OdcUjVz7BN9LBLegKzN
68YZKrxb8jJaUWryyhun+n3fQjJdsu/ok08sgHRamVNamtSGrMIPOFCEm3NV91ls51Btc+kgEivG
8d7kYDKWIvfTsixKWecpPf37uijkTa+8EXpKQPd9Yjz4U+egxhA86no5hJnZse82FbPxDBPyjquR
vJyha0MFSgV7kFzz7kOdfqqzQgrmxF9wWQfmIKd99gNWw/biU4nxgU/92ybnggb5N1LI8t+YgDxU
VajsXEJ0A4hjkzY8ku7Qvez+zx3/tGGV54YRw1eTCcyPGhTl8LRuuBIqfgr1B62SeXCzZ+h1yQn9
Axw96xI7NzYWDPm2ipvk1ODdN9N/yJhmxAw6By+5mX1msCR6akLDZdy63xOKU9T3LC+/+qw+Zy1O
9hMpfg5MZLT+hxtHGnHfJTcEoc07DGZ2QBLSc+SeIFbVrPGfmtq1nBJMatVEDZDRR/e9CYvkzoog
GxIC2rpl3CHApkykxHC1ISr3Tkw7LAIEKgNwddZiOzFgrrN4+C60exHHKoK3gSRPKrWXf05cqZ27
gwb7qM1H3wYmGrzWccfsvpiVQr2P88NYPNi4qv8+AP3y2utu2NeOtedjzDdbbPlRIra1O+YU7qIg
KqaPmzhF8VIQy4cFmn3ld8h5YoAhUFpBoGxhMgRGRYRK3rwRAY1AG4Wxx8ktR+JcVrHINx+G0o4s
ISqsyQyBCa76vTM9FrjndhSsDObZURGzoAiGQE++qcU36AKDmr0R96wDC+VXYW14fWiBKh3lQ15B
mwi4lTIkSBCnWfWXzSxdXY0MQjP71fifPpvqWy8cuYryeL3kzSSU4nqCpjpR+8z88W4P5UWiqdDy
IyTpW3SA1vYZzymCLJT7EhuIgtdnFUwqW8j72f6JQO2yYnwGCeUP1xy7YVleH+h99iBc5ITAdCq+
LpQevSFewci5kwJWN3NE2ZXvi7zCPFGiZQsfkZb/i90fxFqSAx05AtdX9HYIiKoHpJ95zdwAxHQQ
v/XynKTpngg/VJBFzG4XqXQAfRVHn5C17hME/1E8kDJe3Rmguf/ufq1c19f+Nk4ZsxkwVQLCRUAd
ibCiXV9++Mac65x2qF6wD1yzhIUIfFPMy0eEgHHlMDw33apntsbPi5uWu7243Tq7aBJ4jVCdiS/k
b7x1C8qzamCkH9qAcwSltm58zjMmNGXmMS7n4Jd+3Cg9L+HAhX4wvm8cOkvUNFmvBFQMZ4NAnDG/
8cLK57I82aimjRouMtWDFNAOcwySMQWMN9ZNfRcruC5lODJRYpkPawLPOdCr9lhA5KfvejHgQD6s
8CAtzO+pdkp+n8zrYQYmOQxyzcUMA6sOIbePVlf6vHfx0w6fSl+0ivxKqxt4+ghCVHVzyyygL14C
r/qq/LGqyjE3awu1ZQDL3sFU4n4T30yU2juf6WWLoPi8wNzLqsXXYKhUhbNqhq5Vpxuk8a/fxS2K
F37OUGBSOxdZR6fYHIrG/HwPIsqVkOgmm2EjrMNaDetws7+84oxRfUky/avXRw7ArdbqhD+gK5qW
B4XfxPP1KLKOq0oD/yjrDQPNeMl7htVzhzuw9f2x57yopIHaYJ0wv0ONzQNqret6l5rO7N5msltK
C9eXrlMq/5HEwQfE+777h7As0yvCPzLgOgjO0G8T62wmbALsiRSg0IUqBPIvEJ3RlVjbHzcD2it3
I5Lxkzd6e6tDXGXSRrcs+IsbMi3BzAxIeuH3yev7WArYGZLlEuvzpJbyqUjAVIyRPcm/3jcHI7+4
++JsnAms/4tmcHQWjVPUi14jrrMbYr+7sZirpETqb6nLSJW7a6qjUEmNt4LbuNBKIqxtCS9j8nPB
wd5gTis8zeXwsqbwxcjtBByylwMCoSk0tWg2rjvVV7hfvgR4hD8Z/G9pTideSbyqO8IZWUEqmt/G
Q9pQmvB1OB++NwpBZnou3E2sPKr37sfGFmGJdIFUj6P5m91zlhWbHWdGe/6Ha9bohxBwpEbqIUR9
qfhlctO1oHBuVz3Q+eUiDeKHh6rVHLzWj06Yw4Yl8fvWQKl/I416OI12GdXgSG6ZqQP6PHbt/cI+
ZUAb1RagbJ/p3Mqxi9rD4/MQ+Xpb3etdchFZ53uxkqNz4PzjHT+cMYbw8UzQNHtsjSG6UpIN68TA
5MrUUk5ccq7CyBdLzvQ0HEnJEKPn2tzAQ0818x8bgLh7al1I4MJHlgUSJ2qPFHZMUHVSLEryUQ27
lglI3iod/Vttrapt4RAqBmXHNsW302WPL++a3UUcfuKaon1/Eb9ZFHpRnKFORRGn55Y1NPDnHkJ1
xe+cUep8jr+NG6XkOMp3YyBWL97fR3ssv84iyNeTCsHGz8dNnKnktn/MysGlDf+5wgGwJVxAQLLl
e/55bbZRFQpYhy7CjfWMOvrQr1SG29evV0qUhx2fL6yLgNqfLVJxv+a8ltSLE5Wy+awpDkcp5qY1
Sexz51ydtNvtMRc+Sf1no5ZUGz4rSTxm3aG+zs0sDU4kCbrixiStED0GFjzYBDez7Fa4zNdLa6xQ
XsALFCrPvVotiUD9/azrHS4Y4Xbo5G5gKNvq9Gp2qCt1pyTJmUZNP5oJKiWlApPMEIyP4ot/zvEA
RQgJ80SlFs6dsppOpVP9oc5lxxRMSnS9xhuOc45lxohKr9jCwjmGKahBaiga31pjoyd7xzE8nv4G
Wy/PjxqG4EW5k7qTW2Ou6i8NgOkKeVJQOM7MArkO3MwPSdizIp3sVtFG4VvmsUPQJwcYFY0o60Fv
mY6bW3B05O7x+vU4+++IwB8NoyJB+rOMBEAMtG6WXMXmvdGPFZS81dQIJBHakeUt++5pmGr5IUT4
zicI/rHHuByBYCUdYzkoE5iwxEk1T/JPNF5+ZfZqqw8aUWCGdLGW60WdZ6Zye7H0WBhBKMM0fCsK
3fg/bPoVgAmmhTxFJ8QXXBN6MTSwUuYOlQGClVtcU/T3+6p50nTNvCbU+D7TJbUhZ/NRqWbM08dy
5Zenzdh0ajTpfSSDAZyLvt43SGmc+04UescQSVP1PKjSuUeCv+MbSd7pDTNyWv78u0x3TzdlddTH
ivceJK6yKIc2h+S9JovEnmxt9yrigK4Z+BzWf7Ch05vlBxYmu4y1md3Dtn5+LEq5YyiE2g7J4+yK
23ixhidJGc8pZNQvmLG5I/Bcqe0yaiT/bP5TBt0Npb997hlfdVDpyGpaJrlfW7Q5XpRLHw0pJ279
coXh9Jpu4fGCBJPYUrTtz+P0cK7HSnj+g5q7XIYi1EAiWUAg8ea+sSFycRRFjZnNo7DD91KvAqQU
i7ifJailjvckEGgKMwlwdNv94kV1aYIBDKZ8r7OKPmutD9e2xpzoj0Nbu4QiQFpbrJYmFjyKLoqu
yxxsYkzQu8/nCG9lQgbVBoh4ltN4jljDgAan9kxRCRog4H2E/7Jnc3ADq5YXiUm2GyvUQnIl5TcZ
2aNohXRMv887rUQrWi/6LGjOYkQq4/Md5/7jSe0yXHna/KuhuF4cy0/5sZc1hN/BagSYuKZmzGaU
J/4dK9s9WhcQIJPWpW+MoGVdQeKbf8B8qDe/8/KbwVnPrmKiq/vAt4EXZo3jV3Ky5tOvllJFmRYA
yTbMxTFwTzEPwtWb7/XQjuy9zk2+XCsDACE7Wi+WgQv4kpXMkOgfPtfCF2ZbX3IQXHYEIjasodo/
QCL8+EwaU0xaW5vPKGGeBdGuCnNwI7XhCaw+20DSMCxFuc0+6DAPn514Y3tCdP/qmOohKnhW0/lr
/aM7Wo6U+rOUBrALurYdXIaUi5Dte+zHdIIcMv0duUfkDX8gtbS30fXDgdkna3bZRRO2aYuXtLVc
9hbu/2wHmkhHXX22gom/SM9kKwyJGgxDVah5YVuYyp2z5W7lbWBfsF4TDMnUVsoqn9QkIFQk9YZH
wF9h4UaMreJOXRf0boQQvTqoFgl9HOIi4Hdwo3esy5d4gVeA6/Db9uC5sqMN+yhZvzEWYJpr0bnO
RQfUSG7JpKl6UdnB4Bit+FlrWCUKZ2YLZiaRPNHiqhfIDvZR5sUPndf39aKzjy71Jgej0fDgAGoc
t5PIzCYxkevbanx+54KpRSD2Xdm9mPr34Lbmp1/RW6FXJW4NPIpIHGHRkwVgsm8GPuZ6OtJvCU86
RtYpSTEnQaLyo8TjJaC2fr1wZMHHWHewJ4YDRYT+PYTOyWduEc88jKenwolQbwo/bG5FM53B2nPp
e6AUgEoxPJpXlGq6Is+MuvgOs6xsm3Mkn0Pj+NZ6dpMRHZGutFviMcPVg1Iyx8U3KUh+SGeewOYb
5afyC2/Bg4uT7B46zPEYk5CongixlIzOf5fVGGxrvBYPHB5M5EtOhZWULxiOLg0dNz3zJdZwWjw9
xopuJYANeGl49dO7Hzw0jmQWZW6jmNRT+damyA1DyirfYWZjGD/jLAdPN5GWbNPHK4emyupK19EH
qS+w0O5B/Fo5JBQFCmRdzd1WuQZpqTnApJGMGhIO9Fxs43iwvurjhP3GMnq5wIoMkkVFECWHLPRR
7PU1E18XK81z81D4NrYxH4H7JxokOnc9MEl919tnJqx5y9r/SFibXNLBh3pMsIUYH5eusO8+Az/5
SAkJILPJklu/jYzAxvIZWMA+dnsxUGMsyUWjPkbqCQIJfcikIz8lAAwjLSi3OyFiLaEP+mPhqohZ
nDHyMfLws7MeiQujTYw0pNemDvcNeXJYHVQW5rdURN18ftBncW0jZ16IN1o5OoVGeyEIe5YtylyI
vRwCrCGla8JuA5xf/2995xF0ZmY8DLjWgffsrtEV67VsiWAh7IqwFZVoJ6tCm+2hyK6RoqnC+Eqj
VNaiYPzuHFOD7nH0ZyBD33ClpMr0HLr4X5HztWrg/SD0L1m2VLIJhH6AgVJfwFjwlPx4OtktdDZk
m4LFccCNdhbP8s9SQblqOc7Lt3oM6whonSTsBExiQI7QOkyf8p6ZU3bRApoK5mGfyy1JSVxinmyp
Fnhd5bL6J7S5V6m5ryotY44ftuSPz7vo9GTY+vxMRSETM+wpzR1t8scprUqmQk2Smpy0w6OnlJmO
RhvWC9bElQ83oXZoc9nfJDIkrr8v5EMsA3GHHs+L00ESTI8fACn/MTtzro6w2U4lM0C9Ksj09Xeh
SFfScrp7h6GMnCQYeKe2IPK6HmI9QphviJQD4oYum5KMu24+nzDU0D25SiNlqGqamcBhNxnvEupc
CjYJKstnpieuq1qo78FNPvvm/F2nqDkUILOG01zVVN82JpvfLF5371pszF5dCyPiOQ4FU+9bgjms
++RSlE/V/7wGRNLYt3Jup+IWrTizlwYn5OPNcLW4JGG07hd/ke00SRFUi42ANsEI05aFLL0iGGdN
LWaWT/MGDMm4UDdSWakxjHFhcP72Ru4G57hir9wwmKd7ItsotMm7h/VfWVvZfpacjN4bw//BVS/L
rujHT2f6T/50j33iffCKC+/sgcGU/Ku2o/W/gPvUtciZKsjAANlDul7Elkso7Ql+MnrY1cDtSuY8
2vkmlm8Oq9P4KSm0nwg8gGwK7C44pDzZIfAIo1fjQrPPl8uYAwRvVbgxtiuodhuodav1M9zluQKm
NTuhtNLiVrrrleHcltqZ5YV989piVTLA+oQNL3SXKKNN6OUhDjHawv9TNWENQ4I2iKfPb9oL1kiP
3/sBXflz1+8LOhGRZzgfqJE2/wP7GEm6WbbHbwVkrJeIBS5huFPTuzRPh/T5iOl106kaqrjD5Zzz
44Syffzhuf11+AgilKwRTJg0zh2prGCImeDsAn3Ekw1uy/ZvG0yH+Pqv+UVWwpaoAy6YuqiGwkih
MPkhnvHo2bRaF7vFL+wazj2oGK8UMqMU84WjeDyhGryS6conSilQ0hMqSom+9j9pVOCRheHQXkvx
q0ZtZEwzwnPaMvTDubRuGyJfW5rGSodxmc8qNhzHz/9w8TRxchnf9YyrsWJebEIgJPw2azQ51R2w
e/qTLZGXmhZlt9jKX4IBcQ6zZJ2PjHDrktzr6vwwa4OJ4GTh/uPIQ9wpHYgIZiHjcA++ezCYIJDp
htP78qQldCrHEGqLj5mLQUXnfHCMOd1S5QUwc0RIAgih2ZCAJq/3G4nhf9Y58JZIY01r2aJhqx1X
QhKc7bJe7YQ6lyRTk+vaDtBombWZ6o4J4qHjJZCf2FLgxl/QhspE8MGOid97wOdo+qA1fm2NIfal
4ilHLUzrQFvZJQzMvflloLpsOgbamAZ3Iys+kEBEOB0Iiq9yZYyFwSxc+WsgYUpHH2newK7FBdtm
MDdRB47twzVcK06Ej6gFXTE1nvwmO89aqXNmy/2Jnb/Iqf0L3NTP05g+3UX6vkSGff7v8d/Ez2FE
Ll0tMfOVKOqfAV519IsBP6+mqB1aSC6M1E0VkLhZ6VPDhJ+2gLxWPNgSQSSkE7R7UmJqN7Vbp4+M
4eT88y1hNa4XDmVhHX7WhnviA0ZaidtFaOgDSmWjsiEZF8M/QZV22WnXncuywU07dm3NkYpN1fNT
sRVTIRrnTkfG6O41OtQe9nDBJ0pV56utrdZOiklUGMwUrO6U6Ux0OPzNuyAgIxsi6pN1a+bh2sRf
RBXBoDX/4bBO3iR8CD4kOGxj4hGWt3MJD1+wo0WCgyYkF+YZw6/4TyMBJRAn4/t+ApVSlgJqaal5
fEUEh0W44d65L58sQIEHER+xf5x6tdJSZvsHQcyA6lMAibVHEl/Wq72OVNTGBB6OamfTgXNbwCq5
xbf7Wctc2nRDwNvSXZsBN1J1+n8UUMdJcpVvtzMyW55LCGXd95W2UVaHKxJIa/GezoC5qsptBB+k
2Gm5f3Wdk8KtD3aeGkCabSkkW3nteTG8nRGkzEzxY9cM1sXYJurrjkaVRUDbXwN4xZvExAfZQYDq
bIjJO2frvmYBQdNwdK3hJ0kx3S+vpEGfDDgjX2HpEnOdBu+TkBraVuH9GLH9oxBjD93s82c5Xmxf
ju8XJjBgNJXmyJww0XVytPu1b/fn8s4uB9U2uafwvdecknTuXKXeZn5YLGwVUSnDPB7UMiF09Yv4
lUffvJm+q7ERHjGalpmgFw3a2f1teq1dKK61dG3zwc0z5DO+97pSDFrIsQyjwRXgjGuC07s/ZuAk
6ImD8ITdYj/acgh1Xy7S7kRzizxXMj+lZp1uBn4NS3vqJyteK9lSy6VosE3mSPHGowU/6udemjYv
UzPkSuhtP77t4ZZPDQsEGWqn/x3JgVjZu27Z1a62OgbA/bkXuq8+FAywQUf0MMlNADKMbma9+5cI
2T0ohYP/DJgAeaYJK4xuh+R9CTLAlCb2mzUi8Fr1O6KtgKzIDWsYx52wVKEO75izLn8n2fZBCLzd
LM2qggUkm6ZQ3dJ2iUyph6s2pgxW8y6erHyOblomk1HBUGDaskQfFhyE2SIhq4Lf+oNmovB9uxzE
QkFaLoh0fBbCuE7aDcNeP1kEdNGZ3RFgm42GQfQxRNeEbCYr1gPbybh51+4cYFMwMXIe/ftwWQxB
HU9dGgCuFnbQVC0YFvy8HfYfeykjzqihiEm6TIdm1PivK5lAhfZm2cnK/1Yfph9RKxU0rI1gD1wz
eBlbKwKjQICpWL+wtuKwUciV7UmbxS2x02gJeNAu7h/3Zq2HG/C/AYXaPin9DwzwHyOZ9CJlUZNs
5lBA7XXxmKbNowahGng7MdIp2cKiSPK/sMc8srV77z3IKgULRUt5jtbHngkMxh+hpYXYyztaPX0D
xe0sqtV6cRWI9irtyN03oAZwkY2xnQDEGy3XxvdRjE/kvzK2XmsHwkKm/+sRF5EWbbe4GofiFJ+h
XMZiby+BNjxb6cuWLKK4tc/B6tsR+MSVnTjgeXrhDlkEYzyp/iTPIVydz1UbVpk4iR8LsMjlplys
Foju8AWQOmtwweNDtLSb6zTK9jmKQpuWdVp785Kj8va+Fi9jrCVzgyMj7qa9lX25aB5Sk5p+ice6
P2jxiXnSfgwowarJ8PvRro429DBawLdgZUro3Up6DCXUh1+WY4oOOigkeOqq1T0lUirLFlGi0App
F5+jtzJll+idTXu1K1idg+V4FxHEgAelvKf4gAlxQrNhu9NrwfOcU0dhgPqIgVihkoS2vUAN3RjX
ee7L1Sgv+T5yUHUMmFl7iK0ptO4QPawan1CBSSLbXmu/cU95fxz3JQUA60PWtL03HUJA2d4c8Mz4
gF/QBemv7hgrqStAKuHeY8XGGgY3ioCXsoMhcfM+X7rqrLYi7DxC4nv1h4nnLENDloQKaVEYDi9R
KK1uN0/VW0MR3LtWiwlitx1WhpdWoDsefSFQcGzRRlOrBA2q4pzngMr2hP99sqtDCq9x1vabuMFS
yaTroh7vRx1k9ghUtmBiZztKak2pRn7+SWK69t3myZnHUxdazgeVudnEukEiUvypafEAMt0vtS5f
xKF2coug0xI8rZJI5AV2sJrDnFLxDWRkl4PM9YyDYQIg8/xVwq6silUsv9tfbrbhY5xm1AzST9D1
Sj1sJ7xF1Uths99w8Rfsc2/SrLZsr17+xLT6YbA97DeNQzQ8owIYSN8VGB9V1PifZP7kJlzfDsUT
iLZ0KCSyeLAbhfOhXujki6ZW6GMsmlE2/R+fHeqU8mtkZvwD9zOSA/6AQEEZKMbQl3Tpc1RiC91y
QdFx3W9exe/1OoY3tQjHzMNCyzkjOqSHhg+zSKKcKpLiJYUyeF5V14jkq0mT74BomA1NYUf1dJcE
+/6xY07ln1qvAH6e4TRDUcxYEUdUFEfRqe/JmWB/BR1s2iwTnPVBKnnK10kjz4bDcrIbtmj1ZhxD
tn+glRb9nqyDxIlXfCrfh+l+k9ShItkJuq1KyL3aYw9mqohpyf5U6StDjGsvRx2Ve+3sU/bkGl+j
vxcxH8cRKwt8ornAO/wobCkj6oM4U+wH2e6QmXaGXySXmnScql0VdBFjmmf1F2QAQy9SiJKXGTWh
4yceHiwvfm4Elb8stVxHHAgSvjbyf/JoRU9xy63DG0+5k+XxjE6xqhc2KOa/LfFkb968NsBeEKsv
omtyfZrNBDSNOqLFAJoWWlDULzHTuzaefbg4D+9u62FBhXa0FuEQMyyOfy3gYWkNaWzr4VGEiyl2
b9TnQ8anuhDW1OkeBN8/o0od0GPgksZnIhiSS+6Me/l2jEUpr5TzNRB8n1PD5K0u8IuSLAxtO9vD
AUeo3TdT7QFJ0jAiOoQ9pRzvvkZNoeVRExL5u0JSE0BJoi0QJgd4rUvql0ztChOo70qObndecE/d
mhyo2rDmkLjVwc4oVGVyKB268g+qLWnwrJuYhNQeuuQgMwPzyl/GXsX8kNY6uUVH/WnflGxdvbI/
/ezUePJrIPuGiRJhQe+PEM/WIKN+YhGGbwk/N7qdYFNEnJT7j8G70MsxnRztssHXhiurptwqRAvH
7GfxlUJ6rL8aDqI6lt+uD1e8+itn1/F6XP7jLQ8saPOR4UrRQsPddw6MoHeqv9/jYyRJRqt2kDge
+CIbNDG3EiJrGMtdk6U4Yv9js/zDXnDiLMuiTD8U//0fCSaSaH8ReSy5t87xLm8mjxtuHDj1cNRp
YAvyywpnTQz2RzyXTczEWh5Yy/j7Ugsxn2lLyH0gFAHftL6Mbl+/3A8+H9nDmibKajY3wLTmw9Ns
fEfAtQ3yZXCO7YCsl62egiabw+3n7SaM6vOqkVvk97L5nuyMIvf4TByxQnHNAUCTl7e1wiOidO3r
mmMCuzl113u7EeTVP+Bv27K9tkNLjIV50AURbRMntwDKeUIREzQexGLeKiOl4YJ1IKMKwy4px04H
AFnSbjpoFZ2BKBP8mTchK+Z16lUGSFhgHqkiz+6YmUZJHGLWuQCjIgELIKHSzwpqJHQaQ3OCOqW3
qq2Ne2PUfkom35om9Bint23FvtGmIpIq3TzKLy+O7H8uW5hpldU3G9hvxRsDIief/pSyfGQ/RjBb
y34pB2FmzqcQMKBnT8CLvsAo+Gq6Kg+6ejBfvdGVhMieX10FEf1hGq8vC5lDElXnqsy2/zxZuSeq
rNZ4ADq1P7foqP9DOhgKdTOX3XkpKr0JHjn9/2e59T+aFCtYLKrYHk7FyUaIvcszAAzgAFqhlZku
LG1a5VUEH80cRzV1ebO2oBL48fyeHGxx70dyotNVSmFFjF0PnrFfBfV9lc9rMypW+PMsMT1ue5u/
ZYnlAz69Po+0i2TYDO99/+Kr7Hk1jAPirjG4n7pv5IB2CShCbwMxmtvxOEGzkNPbFgCa+Pbk/CKI
QQ8ngl5R3Gm65Obq0zV2jQnZF5Z5n+gEEJgUo5SsQVCBzB2H5v6ZaoL2iyyrmccGhm32zogaP0Yz
UPB4A+Uvgz8zMNKRzaPWYi8/OtMFLl/JWjnILv0ge9peBz7qOIX/J3saMewgBqX5UwqaLXeS4mas
aR/9Lgmnb7YSfARpyIxSxvX2sRB2lE3/q/ecidb/lef691waqmQ/v7acY1oa1k67idnkS50y4Q6T
gwXYDHepf2JBOasI9WdqkjD9DuLe+XbblhiMH0G1Bj7u1j1iGzdDx+qh7pMJmNmElYG8OjC9Kbdn
sdNB5soGDplWVtvwcuPOC8XAF919+d6JQZ3sIss0lvg8elKkRMD1COrJgueg4XuoqJKULJ91akyk
SU73lguhRM3OrtS3meyajhlKOe5i4ItSgfe0TjJBHRQmhdHiC9COyqxW7m6O9Txo5ulKLZRHBpMM
SEkgyM+VpL/Q53PqjT6927ALn9oDhsvnO2hT5PdAQL0JVhV23Y/iTQwQUMKU3nq2IoiccwwaqbOM
ETZJVjrrKyUHxfy0zzyxJmK2zlGfdE4JJEWTOoYsTMcOWa7X9Ow4WQBUZletjrsUp4xm24ysZ+ie
NNnyR3SO2I6bdlLWraV0Azkah/Jji2yrRzCCWfCVhRZDN4wQa8h18qzrPu/BXAhzy9oi3b228qNh
dQhv9hSJXY9OUyk7jJBf68mgINNQSG71Ayz19VVuXlWfzzx7XaF0j5OP3V7fzgkeRfcY5Y51HYv+
O5/V142k8ijOzrF/mRSc3cmhBS8+MCBUjIOPZpBzGr54ZrIIvEa0I0LerQ8pUOvzqDReLiM8My8W
cKFJDqYF1JPBvjJUibEZZy8u7EPFWUjBVlpdDWJA1XbBcTft0F3V3Ppbl1mDfENqrx1Vs89wOeMg
/cmJjXOX41H8MZZX81bfki5vOYuYvRyLyELWj6h+gyb6Vbo7UVvWc7PedvkGCZuF7DrsO5Qm+hna
Ou6KEUu5h4HKddZ2n5x7TbuaZz67z2jnDL+lbhffS5Rj8UsiazJDDqZJmxSGW880bCj+i1RJDnTC
M9JT4XHHxp64TXY6gsgmPCa2oCH/lV2KaNT/EogWl0W9xth1d7cMqEYecVsgMXgolZ/dqaM3my/r
INTTut8BMWJkcGEIjPj6jgO42jtXWocrb580ZElGHjrPjas5e5Yz8OcThx6OWDo8XLEUMs7wCRUR
PvfY4IBfn8okkyfvEkQm+7xIDgWLNWhUf9WNJ0vb+bnSL5cJZwnIJUMB69gE39sOkjz+COIAXyGk
YW4gfFD3eNmWDT9ZBitxmRr+QkMXwJfEHpB2VPSvIzO25R09iWrgTAS4pKclzALF2hSGrSK/3cSY
+FfL880mbQYbIJi9AwDIYk6TMsoEDZs1WkpS/lszZ+h1ZbgVRkaGufqq1N3V2qacgkbxjJr3wlSx
ba+GAt2Gx63DdqHF3ozeDPceZWIjLpqG2pKbrj/VDM7qzsPM2rn+Brh9hmO0G/dz7CzI/lmVky/l
MFi7fRobQ2L+HmN/HMxcMueFYzMatVPNt7EnJEMK72Fa7ycZ6JofqB3PzYmQOKF45HsWlX+LQUiL
fLykc4TA3fDESD95ZQV1MbOHyaNNrwpR98AI1QP8Eko6Ta2KQkL+1RC7+vwsoM95ulkuvx4Tc6b8
LMyy+zPMN/igwQ9KQFIx67ZNgmhddPG0iw4IQrnwb2a5PRk1R2h75lRrgYU1sgqx+0quxQXiZ/Rx
uSgCfNVvyILQJTXdeuOXCIyamMFOPtmxx9DtE0DDiiBedoLWvp6Vp/Q2o/4papNycnunMp3IC9Dq
jAk1rUxobAA0mX60l1Rad2UNuKq+NwpK37AGec4Dc8lyLt0AbSAKRd0P3khAcedIpSlhadnpWxqL
pWJ/A2qzf5hKCA77ZHCjgkGCikDYevCfBG0YJjSNv62QRUCj7kFKkdwFenZTSHo3/YMo87x0EYe0
TzLb2z3ouLnzHSF+j3dzyNQfhRsuXK3tI9c46eQASHTDcIQecZIlfPL10XvAZ5gt+w95pNFXunFo
VUFa3qTqx1GV7IPmqYFWbTzNmCXqSvD3bKyBOnlsmxo/nevnJ2leiSBtnFEQYbCSmJdmFY6AUK3f
Ro0/NLM2Z828BaARsovyM53AvnXN8Trf2gaCumYB6MmddiGoT+vn9M1LG4as6k43Elc5yqU6uyPt
MdD9UUtIwpSuOeI1JOOrQzj5VwvA9yNzepGEM9IupL3uT4960klJ6zdpwHrQ2EXUZtAxcuDwK+Ky
pIMXDKpf+K4XEeZf8g6//mbE4atuCis0mk38WiOYCfv9AS+MyAogkOYImkGNcA+HB0CSWJ+1+jmr
eXVTlK2gQ8UECkiS0c689W8xtQinhT7A5kkIr76hST2YN+Ventn9HfTyprvwt+ofKTrhF9TfffP/
pBvON9BxMrZkc3RLH6lW+HhRYv2VxpVQ6SHD0R8YQMhVCAzNRAbjH9YJbeRjHcVR7pgK8A7AuQrh
caags1w1J13oNydBE1vGi7fm80kynxCtUf58cvgtNo3A+uwJEEctIakRqEmi9dx9qYy8YpuZOAeE
21kU3ZO0i+unrqWaKKf6IjeR8eGR4YrRfyf3iHKT7NQPWQ+rkqNhX+nrCAI3mnCpvrO7s8VGGnSP
0RU8RVLfQv5PvKAlqU4PBlOUAn4yf3J2Ng+WQOGEEsQO2lauBx/d/WN5GUV4sXoSAWxUMnYp6Y8o
VHsGjrXx6qcxOHO0HSzUrjGdfSo43J29KF7DkJGxINPzlNOITTsIe6a/J3zPUAdzkLDGyVuLsnuk
Zbv19bB9c6Lx+96Dz/OZelj4h7Y82BVT6rtH5AipjIZDd4+PR1zFK2nm9BHVlDMGFLcGRekDPkHD
sj55X600X8rCoq3QZXXghvhvRwpjgCIIg2O7A7JjC9o5LgANQtX+GJMzazj3xoFfRbWu8+yW3Q82
I5iDEo8lHFBPKydwrh7LX8w+3kGhC+e5k+Y4f6mwYExLbQmGv6WgLUl3pBMfc2bSRagbo68OLZbs
jBJaEnYG8aHE4LZnQ2M86V4LjXyzBFP6w+VH80HbagnFGfSA6abXJHWRUHOlQdlsw7ySxFL3UaBe
NbHUe3AhXxzzaO/1ynxskN4FmESqrsUF5oVqgfjUQSLjdLhIf9trTYRv1J2alkcfbzyTGPqDxgio
d/yg471+iNwgwhYzowRCZSsIa51QtfNH/bb1AlWQyV8e39KSubZyrQVprer8b8Zt97pjDkn2dQlt
1bD2pmLkdd8E3VToQ+s9ezk0Nph1dOYs+gZaAdsPEd+bp/gcu2xWrOL2BSBzL6YT8TTNzj2tO7Xv
QsxolO5qMI717+H0dctSZYt32PHIV3mH5xRzC7PYqfanoQfYUrUzKbgOVEgI1jncEkF8qWs0V5vb
kq3BDQD//DgXbTC9TrlMFNY40gTDJI55o3nF3WieKUXv9RzqAeDLklaUMcJD6n2wVlgVI2mYfHqF
QUMQzfA7lFY2tGe1UcgsAh9BjztXbiuXNTtYABrXdcvNHLoiB6lYKTn7XrdrkMhLtc1bseI168mP
rO5EA+DzBy6u+hitaM8a+qZImKHCr/u4hgI60SfTnsUinaXvJGCL5qBJQTPUpilQlHBmd1oaaVAS
OVkRZZYdkPDDadqBql5cmvG3LpX3+wPva6tAuaCZandzT4ib97PdDC2BlRV4nCIfDAzT69hE1vo0
3VyGvmRJu8D/UcQNwvA3w1SPRyPD+HZKlRt0Ii4oUlCjZDK4cvw+DiuolJhQTgKN041ZDdSwP9UZ
FxTupAQg8yW2nqk5tD1FWNvGhe3y80wVyH0d+T8xuxxaGs+c/RtW65akIWiGj+ClPSW8jTnN1txW
B85feDvriN+3HO+n2QX6+TWRwBIGpQ1C4L9Xf/bJHxiEoFhpmpvJlyWXnzc0vW9bCWMmRI2iMAQg
0CpvVuizGHOe4OeqLkN3ZzBjbef1ymGNqi2XxXEHi1F51N7ZsFkOuJSkjlSlxw/0zVyENZe8ZgzJ
xu7B0AOMa/K5hM4Akdv9t+q8USLDHwku/2MfK7edXHiFKjfwxkbcrQ2Ioh6OcnPZPGFVUrFYcmLC
J8J5X75k/9ubx4j2n/7eiN4s/TVWWSMpu42Ponw7JvzbQianNblEb8B9JZBa78V9sBMG2B3MpS1i
G5bCZ+i/vjbER1ZZV5FxV8tUqH1LA+R3Eur8lp/ztLxbRA368Gzwjqivbzg3YlrLwdDeGipY17wb
fm9i+jz169oIUWMT7Ss+W0E7uQpLsJ3t5W67oslvEBKT5parMdQTcd6Y9tlj89Q+HtzxIBtvcgHX
L6292qlAf+EfFBwrPo+V0jZyQf0Brr4909TY0e0Z/EXMklhIRT9wH+dEaflcWdkv2HXKEc81OczI
hPkmt9NYayOF8LYF2apO3gL1L3hb9EBnoTzuWhCvtm31oxUvv7GvcIysQBswyhO2U/rU5n9ck1qV
VgosORzivGRpEtT37QCCYikuPLUtXwc1Vxuo54HA01+jb7opt1fBskJPEjIw15ZMqQt3i6oLsgGf
igbrbnbMFox+WyzUOXwDC7Iaf7r2WC1iqc2t3FbA5dlr7O5OyazO1XRmyKMuGABfls8iZy6bJGOO
D6ZlxBwMoKGKLaM5UCzQ1vAtxr/FTAwiWChpbH9s07heOxqRfUL+Sh+Ohd0xHJoK2WiU1fpia+Q4
2UgJtzrXhNnj/jvH3+c0hWsjo8Hc36lOnkIOHHLrp97v87VOlTOPvVtmnl9UKIcqE1E/AYOjSPjz
KXDhSejGC5RJlaiWC2wrp2i4hQGyg0T5lNxd1wBxpPpoOsQ+nRnvriGpS7pTdKuiLWL5ci65fYlV
fgM5I9x3CoSNzUCAzLvkkOw66+SvvHwpGnAj2VOJE6NkRMfWgWG9HtBpfKrc/Yas3LXpaZupjrbI
WTNlpf3xeZm3lDWW+8vTwhUXWb1pd9pU9+Vaae0nt7ANiDNPKqpP74i4RccPTwBpMw3lexdpUP+O
5J8auYFOsBiNoksqjFPAM+xWRd5tORrFf9h2YKx3lbymJ9yHew6C3vP+yigjz9Ydy3nN8PndME88
gT4NcxBeJrHmTfaLgC7cl6mLnZi9TdW/OSqff0vBz2UhZBCms2IZ+S6/2Uz/599CUoMeoErbzRJ8
BPDI0L+BwNSBUL5PAmN+YYZen4a7JvuwTlVgRUTarlzrNoVEmzBMASIhPDO23mDsF2JvBQhOgnBo
DdhveseXbxKAHIs/nyYG3InFMrqfiZnhWlbukFxeJBJyDbC9nXJph2HYW4SiwzyO0GQsNEAyN8bo
5gBpE7BcENFbniGFoicVE+QkzYIRARjJ2u9rgO420frZ7KN2OwguT5QjkXega43z8sJrUnEIBUNQ
9hxRdw6RNMHoEPUKvdl241LOAUZjIaZJd3TadP4lTaCdI829O/vCjjN2BAJyQW3r4IdWznnkzyXT
bbLEhOzmF+Uc4M5cuVhOnZqObBkzjRaQ2LzAR4B9nI7rpPjgNqsSzNgrC6wOnILIMehq5OtOtVXK
QgBz7y6mHgy0d+d4l84ti8bEblCCvOIAVZyYBYzuBBc5P12k5xNyQ9pZjiUBQ/Mi/iCiXAIzspWo
WgdjDAcL9LDDo3yK48fp9N982FZIeFjCDLPdYa/AJmF4KPUuhJW1bna0MtOSvVSQ2IvlDZcW52rQ
vXc965MxbS4ZtgEDgcjWLcGFLtKN48Wb0NT5+6qOQviFfxRu8HIiBdLS7LbJi4F2HeGtTi+/UX9T
/1Crc8/ndpqvdmVNobLAdutFGfPVq1cnEXc6mL49+ePN1f8QJU/nO2YFqke68DWKw5YxEjdiYPjD
2wSK/PILegXV00ye6OUB2CSAqbfBDAJbYzW/dE+EV1EQx6Vv9TOQThKFSdMShilRmoTTusgLFnTR
CVTzXLHNvcv1ceke0N5nhFw43F8eOsz064X2bLjITlysg9fvLEsIddHUDszm4zUqCmkitq2EhbUj
RAkvxHY33BpEUONc9qjaSW7UkidN4uMq8MhPBLdsPoMAZWWDk1oIauWUlpMlTjSQfYeRHOgJLuHr
danRccMTG6zEgCItHyr+32b3Pfbnkpag+rkgJrNNiGkaVkSP6f2sRDSQ/lPjwfqzEnSZKXuW54zi
9+8Za1XNQv6bUQbi0nCUTkCiix+n+Usn5SxozY6shXTm1AXQvBwmztePljM6tL3fVRw2JDvyelVt
ivhujB9XXqhytfOqSGBtXHNchA2jSXfb77Id0k7ugP0WruD2ateMg7nK/NQRtOIELf+OQBSP+NVb
xYjbv7uHZfpYhAMZoN7JylgFgmi1N+9dcJc4X5UN3mVxbC/Q7CmbyqvOOsA2bQCVct5+s6H1m1yq
K9TWT93qy5v9T0KwoN0whdhE1ieAnc64Yvz2k7DgmiLoPHbvvX7wcIcNjTPX6Jy+YmOVDVFlZnXJ
j5jvVyl+LWWre29EMAkto7KUfpcA318tNXu9gRtkITWNNGbYjQSnn1VnkNk0URXzIKEjUikidHfj
X2E1g7ngn8DDHO38QsdB51+WwOBxVsu3zKyov3cS+TuIOXPrcDvmzpMpx4qhkqvfrCa4M1MdZ+qc
+ilGyYuKHQzOATsV3QqcSH6WD6Xh4g+Qk1LHge6edgjI+UxlU1BSe/cDdSgqANfZhk0Yr5y5GWp9
WzaHBh4iOtB0RW6UzX3tdNEr9GM78GyQ0S0t8QOcLex6eAUjcRoq5YaZ8nIOXe80myczdZcRN1LV
5KM3aB5O10ArO1x/ktvgGzoENL+WxdYL0x/TqYbb+gdsxdkYFhdieaUsR1IpjTn3bGzqErUMLlo6
FF45h9rjWBk44d5OP67TB+gHSpV1WEBSpHjcc/htmCXeqQA1LO8I8Xl5KYWRU6GNPeN9ra1JWZcr
J6Wd4xLKYFPQQbNlyj+grwWB3z29+lbVt+SLUvDG4x6p84HnduyLIJ9ERRTzpy2+1cTWpnZfK6zm
Hd9CefQV2E61xgPdTiC4x0uXgAPznoYmNTRdsdjkKUgEssSvr3ozPKuxtcfYEuXLzebuYLI92RGH
BjdaYOtI82Od6kLydHw0QQSD0vu6VxJebpHFdGAnAbhH1nltmYWLlGqPLzMOvxxqH2WHpQ0L5MyE
mV1RgBpcNto4SQNsz9d7u1J1V5S2FYdE4vbgE63LjzP2v3hw71dqOdrpV1G6PHX/jVam/WQVpsLa
SugMuShsv1zFIu3nrdGz6B+qnbfAxSAnI4WR6bZ2jk9n8wSPmZRS2At0qktoLtBgu+ii4j+urRzO
zunpEP0BsNJ+YNulTv7sSNWm4YVWleAH3C9SC2sl1VHvTC7Q5BiY/xmiT30SAz9xGJTszT3WusI3
E6t0tGHSVn9uTMv+Ek0cDOAfAdOn3kimBZDMQQFk2PdIrUuCaX19HMEMo4RpoI7cJmmaun43TdfZ
UiraN8TcGPHtpiU6CRs5TQ/MjXQ2CnMchwJZhrBaLIaKKm4CxlUUFLkFTkTc/SEH8pmugPbqZlCF
D2iPl5Lk+xMfYDLwofNQg9ZIJEggL527+Sjsgm2vhs/5HjAyad6xUS3rS8cc1C9Qq/vycryX6Uxh
qsqjd+xwSy5eqpMY4kM/GUVYW3z184xPiQQbWeiKN9HRMwPceXlCH9P1ajqdXTZiWTtDiE5zBFfH
3Dzjj5+TiVcKCSJ9519eDhYOiy16mUFV4TtmGmuI4bCm28lPT1XTdvGBP0hW4NnYBs6KcEObhSmT
MIhuULoH/ojDPfL7tQaqdrwHNU/btyv47JRiV/ceToqW7auet9DIUKd2FRn/r7osLVGKZuxeKZro
wjzdmYMymWnjMoem8tb6UIXcSvfcFjcpHBMD1Nk9tK2ipuCOdm96AWBGQ7REVi7fdrjU/CKVmmY7
su88OBMludGjtqSG3aeHRaA7DRIt11PEz4i6FXq5bPrQPrKLiN8GGn/8uwr1EWXdotclA0DhoXEb
J6Cd0EgPKxLzvvp9KIOQdaqwqv4e9TBOAeTt6yYy6j9n/iS/E1YwQTY4ctUrH+eJYy0Ks+UTfxt2
g9dMDub1gt2Xw3cPeNO3357kvYkJn1B32ZqN0abl1eDjdsrmHxlLnivu/rK+zpbGsEOfFVoIBksn
Etl3CXY5AafHiXeLP0PyNVmXLGV4NqLTso/nsuAeayrSOrBhkQksJlSAjgyjv/PFDfpt6JSfkGQd
4mscLCZmpLXWoUVF+q+HY8jDgqzFhYv5YD/UBuQYDVhsri+TyI2D+QVV4OgA9X2Zghjs7P3GVGHj
hC8K18l1iJiB6zj88S1FkHVEY4WtbaEIrMG1utaj5DsJ06HXaAsCZl6bF+tuZQLgmoN6T9EiMBqw
pjTOqh1a26qZePW/oGgE6596m38vSu0EbSDP8+6wJIZjD9OyH2+aen2fxx+Z/fZzoGeluAu5Lr4E
SSm8UDTvPXzMSMP0kf3dxv9llKogSoRzZD++brUUWop2zoVn31qmk/AMLv/sYEQy3Lw4FnRwq+27
f1WpF/WkA55tSDOCFf07XKMxoOUdGf46pCatEoXk2UooKn/ZnnDctuBkUBbd734KZeHiNYXP8Q8S
y+qXsYnRHSEYnKHmAzZwTi+EaqQ4HOLUGfAMEELdnYep3hVkxeAe8CxiWLxPzZC2g8ETqUGiy2EV
fDbNcWJ7c+BCsWJR6K+fK1imwBHDeVK60ErjPCwiB+bK+LtLrIz5AIlrz7xAa1dBnegK3Y+3aBec
w92E3awblaN7slR6mB7is2FtNQG1xMRAC3/kcKZnXl2/FxQCpFX3sfliMSsE0DN/vMK3gdPlQmy7
VsXyxbVCWT1F7iK3um5kktsownTMOpW1tj0KtPtK+rLWozXbChta3hGczhMGUNpd4ODc6NfqMt0I
v2u9gDt47pHya7RvsQVRgDzgYdsNwzm24PownY2cC0rw0FlaZvF/0x3cS9A3q+7SwY0DoSLK4CJ+
e3w2BHHSpKQ7bcJYtI4XkgwWBrzX0su21ChysA6TTYePbvtm4Xu1ecLjH6hoDbdB1wDvIBZoCfo5
8UvJjweCYvhgWVjyWxB1h8cS8rr6V/znr0gKfbFmbaXDn1tdQ9kCxssiJZJT0NKoTn8ycMDDPGhQ
D45Ay6uTdA7kh90z0Hwn6T2bMovvpnrZU53ey2cJUZ2RKzZGcS7q15UrDGjd4UVlkcavLCJKEokG
vmHpTw8igVcd4QpSWFOVdLa50GY3dz3qSXm9QUKLe/w7gxXuOjVxZM5SrQLF+tCt6uRgSWhb9MkX
PLlutPU/qN/JHB/+2LRtk9VS1c3RjRE4TyM8fv9/k8LnB0isHTI7IuJOoQF0qtM9ek3f/XZAu0NL
JSTjJliz66tzfnKeXyqmuolIgteMI4uxo/hifNUeoElj+O3EhkHbOThcd6Jz0cXVi+MkUb1944IO
tLf9Ur1Z3XArR783fM9Suj5dr4BfZsL4a0JrPS7kvExQ6IspjoQ+CwRLHIlVURRG7pkMzIMuC5UF
E5Eo4vVtRyRuJ3++v98Wb/wfERsfR3rItYWOJQsyRQ4hFj0HL0r+362MKL+s37x3alIPd7q1Sl4f
5mig+tPgMG+jr3d6VZdbz3eUNeypH52JgJ5ZDKeBjAFyowcrUcIXXTaNT7cJPoenfTQiahbpV+y6
TwHMEbcMP6NdKJvgJkp5cDVQQEzN31OB9pBBBruVn1DZzWqjNKCdqc1iI0m3Nv1uoAX3IPqEWwjk
gzgpkkxPCCJyufhK9/UjeDksa46DChAh/cbeCndXPd19HIhh9o0mPXONk+pFUxmyuQBZmT24ZO9p
7X2Fet3PYFokqdUfD4GF0Pg8Hu+CGWEDm2rsGmuLconGYlZ0NR4iMcxuPnFP3FWzUnug0Crg4q7A
tAwRTiUgJu3iG2VuyWfxbhxNhvLCZPGBzpHnDcThtNerOAWGuL9nMwXJPJ41edUqTC7NFrtFpqco
pH+kq54T8EoFXkYds0Cdm9BX0DeuUVutFC7Itr5O4+hFbgypgQg2reqOGqw+8FuCtGPSTRWXBZvd
04Rops/1CzmKFUZm9Do9bq/+P216myHpCTS9kG/EepyL690BdERYDPM0dpIYkfcfoca1/oPH7RPD
dbmyAg79ZMHw+TyViPKFgt0bxrTJXefV+x6OBm1f29g4SJ6lj5YILQvVlOQ9035i3tHzg0Xnjowi
0Ygv/zlye1yQkFNkAelVDHpVDj3JRgSdfuMK6SI/T/316VUyvxX++QhRqPxS5XyjbMUwnkS+kexC
W77r4XxYEJJJKeBiPPOQGcC+kzxN+Q7j2/G2VUBYsXyrSPdEiKGnKLJpknTJinWDxyXIScBIbTXm
m7PXBl0iFGynehOyGDsX6Wk3/lRTlRTWBvHQ5uNfqh+p6SEXmRLuNZiaxc/gnajO7A/oW9fbcKiE
ZQq58mj4VI5flS9lnRStAisCO7Jh6f/JiogWOeR0d2aT6bvE3c7PEaUkM9xcswInSywnlr+8QpSl
2aQ3gCFczEwIrpjlxgGAcaFRu3iJOjWG2z7MomUi5u+Aj+8/Jv189Qb694iJ1BfyGdp4EVgegndu
ZXtnn3wHBRJ1mdhpPPxfGm559IgMhg0Q00w9QtrKX6h+8gi0B703rL6udthD9uQ8Ze5x3XhiOtdD
P8Z9XNowXKDWFyJCcLPGxr3HspGkhp/31AuAJ2C8tSKVw//0+dfi4cdvZSeYQwxTD12XySOPa3RF
PrGTaTwMQRFXX7WnfdinpiSeXt4qjc7RfRowl8IqApxxU0sW/NyJR1uIGW9L7OwM2aCNpKT4xpAk
xvU6RJNLvrIFBjyy5Qy9AAWT9hMFQDeec7mwYlU+L+cjAFDsSMAJD/MJ11nV1G+g07bRBXAiQyUy
lNtqzofd/sOkQ09VxsBPG2Z1FGeAFoaN9SNlJGcmZ3j5+e+GbLLGageptEqpZO6SWCASW3ZK7ULh
o5Fm/BeJ6JKBZgDqBcz9zY61fQjAri1PbOLf/7c+DcPyos1KWhMosd1ccAtc6noIqPQqH9OoR3o9
D1d8UYxZ29/v9vX/klHdLrc7brgllCYRnxDwmp76Sd5NHB6qauJ+CGNM9atqIyhu9Jx2NdpWXuv9
BDAkgnS8Taz4jQR0ZJdVVnbq1QJXa4bTgVNg4hUSTiwFpqlVnYDVzjoQR+Kbg0xLIIJRr5F70DSU
A7hAH55V/TgsL8/kfRig15fWUWph+g3TcvvD6+zHz0cH9yQBsun0qhMgq2gQWD1xW18fEpFxWSur
1Jj4c9ybMzBi3ogrIvIl8uuRFhwESxqahp17LASeSTcPoWErgxqkL/f4E7W3ZW3Xoa3Rxng1iUqM
xgWFOjuyXap7pBW7MLdOSThjp9KCuNqJwo9wf7w3RnE2mGxOlPKdVBez/Lb2QjX6ZBg8fZVCKeLi
UTJNPOATZBBkTHfvJltzytxFBZUhEb9iNuC/0LG60uvV2ZNyG7j4swHrrIIai+xjOis514qgNtPk
th9KTB9s43BAtdIEzJP6lTl4qob2sjuOtuqlwSf5EkV3HieaPq4pps1oKf0tb9BOoY/L4+YbCZUI
XTGSrhLgBqCJlFBeKfisLl1jSGjxx0e0cIjmCxVLMOiPL/9NinrAtSPJFWXFvSTd4HU6QR7JK4RA
Yp31VyWM/yoS9IVMDkUO+Vvpo8K7xN6CH/0/swnSjLqBeyaFZJBJaaP365ibI1l210zlZcWOyp5B
eyp7wJ7fO7gvtcOQBlYB5DO60uwdT0iLNyJ8FRZ0XUjRxvU9/qdybR9j+GFh1AWHs1Aqheg1MygE
yToHg7SLphVDzwKuH6TQe5GlbyuDkLAU0M77ILZBJAQ/81AuLyLyiTfjCUFlSpnkGgrMdGifBvpi
JeGeAigyCvZkcZwNeYiWZjhedl+TMYSOznehO35iuvZ7ZaE6zQqvz01zIlXXn6YD5EMIw2Npui6E
9kjAvPUM3TU0PDMAbBc6cPWPmEvCotfIIspOjkJ/A9ejW3231CbVSPaBvFYyrSwAyxUDThGY2X3t
6m1HJFWB7sPQSXvaeWLPtNgwLRIo3wGDAUDOLMN6rvEBBUFHv57Y7jsJ8BBMiglmrYOod/Fv+jWe
ztyM2jdfuxnU+EtmZmz9XQftwWgtpddsJNn8P7UF3tbSeXjz2bp1HXhuJvsDtIJhDVXbtk7ZWHmY
5VhLlbHSwKjDZBYQjybOTynMUirYegXRnrVWd0TtDJoBICYqFntmmSZjPA+CTOIEXc5kzq97sYor
IFko5jgHo4xC4kccLHBJXKel12gxWKDncgWEzAWh1EpBADok5jR7+WhiN4t2fYXwWfJK8GxerOOQ
q+HIYSRaHanR5VVytnEJlSEBs0EE3KoBtt0tKNKbf89wjpfereoBK7ipmFLXrll5oi3KGJG+b5Jn
bocrFhuU0/rpEJaYJKkMfVg92odb33o5hkaQuSD4WDYUUc1H9TCmWwjVgXM6LwlQ2CFbqJ3kDRg6
jByhcMxTe+L+14ZvtiYquV2qnua1FomsN8MCwFtsosbr243H0QtP1iSCmOLWrSzvm4Owr1vP0jQX
JaPykuSsAN4ExtB+szo8wBkRIQQYZW9TlW7bjZNRSmcxb9Tn6UV5n9v/dXJDDi66keKsXk83gnRl
Z/KXi9y8TMPi3tuWm4ZL5gHaFMH9P6cS2XhIzokQUeAB+GdNHNgkQsK80x1dVF6bL/Vd/ZULxma3
pa8nKOjdNxauertnK7ArXBsvZYG7okkv8Kx4HFwT8Fa9pcWH5WXJpP3DvZsAttzMUNgXOSIgx96r
p+xupICePkxntI/Z+MWKCalhBdeuWYq9MQUVKA/l9MkLwtZ2cktQtCCDDzmb/isB+8S8hWe1gp9F
cW7I5nPboAd8QGAl1GIMiUMiPeG3YnGU55a99Y7WhVmllc/isR5fquNaUr/PwueE1iWm1ntsG2f0
c56Mb+qtsp7pN9zwyS8gm/cogef2g9S/G6AdwQlkB41bMY1zQQ0tRMjRCr/rKqSZyYclout90WJx
j+YGvqoqCOw6wtF9JsmC0Q8BcsEAvzFiEa5LtTixZmDO7YEbA9W9xePzSghoRt5FCWYAKzpd6jaK
XdsKub3JgWafCx2C5Gg29bcOE6wLdCu8RnOcoYUcz/S2/smfVAiXYfroUbldn7smUrYlRWH34v/9
4Qhfm6XQLCGmUs6wQxJ5Afb/GMu1yURs7drpz2qKRT7TUJrQY7ZwlCRWltfnMewipe5Tfdzvb7HI
kSVxNFYMvaEb7vT8fR3pkd1V1lRXUA9JBS33Q1WylZX5ixTw55rL8kJ7aMcbKeuhG5Yn+JKj+5Bu
LEOq2n8fxOkn7H6qIozc9nr20l+j3XdfSnPDwVNToOdwTgTxh9uYucWkzFxxhP/9fSGlHTFb0c3R
fsm9C4FqDYb//rDXTFPxNqamjg6rFr+2d+9dpzvf5PYIbAfOa0vhu5q1cABUqkBVCrTpp1a+jACx
PCVcA92T5cur2LL1gdg0DVx8dPO3DtIAAqvREIKx+rGg9ynnQWkSsMLiIlmRz3PIonPBWtoMTC4Q
oDfPPhNsJJZinmrF1Gqb76QxZZK4fhrSfY3r7h68Zq/QsfWt2MQ4o6iMpeU7vocxKrfQGV9axSWU
FPV8J1/8tHeT337Q4WNMDYSi4DuetWhIui14APlV7Oqg3AikClh2NEVy5KE+ddTFfI6Yqajw/wc3
rFXQOtKHkQs7ud3vsidQ/FjngTG1/0b7X4myYBhqCoNlKgMsGoIhRFgTAwA+fInJ3V2t8DaCYPte
kQQ3RFCuLB40O1fOcKyC4YN0ELBVzdzOmC82BvRGr30108Wr2FDIi0ocTwiU3xNYNG3Tc7jH9+gD
59aAZ+84Po2N+ZnkArC5cJEfm3kAmQR8ihCB2cu+4TZ2HlvguVNA7TeFq2Z3R8Hllkh5uxsazdpk
uCfaNy/qHWIgJu6rDdibblYlnKw/srwCnBa7Ri+qOZ1wciDakJSgQDCkcDbH3pp9ozrdF3BxJhlp
e0PiHoumedSkbxKQs/dl7Kj7RSIRX319S/gOwKzH2WZayBGyroQ28eh6Gjli11D/xZ48OCftZxzI
NomWSO4N27DaVB6i8jrF15bG8TryVtAl8lSXbCK2v7EaKNw1mRcASXceqH+3TPWDOa3+FDRQu0DR
OFgQEHSNy/EcphoSqaFvl1tpSmH8Dp9pk23AQG6B1fOTsdzGdRcbZ7b2n+0kJxx687ij2um4yS9G
HYhip3PcXdBsIr/heM7gGdAWhii26euZMDHHxtcVmPqmea/2UEBOSLRWLQltP134J5OgEySTZbD/
lGlWjNgxHVAKShW5KIUNpc7QW7VdjohIjG6Sx1qKiVkW9+BmP3u//sL1H4Eu/fcZcGTeG0JTFOPh
+KlFUG6PdY+DEfIRTV9w3g7jeBWZcqr+6hI3ur2AjHJw/7BZIgKCoSKQT9qg7Fbg2ku+WcNshyyS
NXych94IesRkNdpOD9qSlGVOhsZrvEpTdquVmwhaEe80u08wfyS+uvo/E7pJIP1gziTqFkMXzOQw
QEqW6ITEW6kKcZVbKJUkLKx/8G2Qklbpspug7Ic+3JWI79P0K8zWDOsFtuhw6VjVm7WdvILMeXQf
nnqszwSAN/eZlyH1PRpykrcc14Mhob8KOhRKP6NHeAIs20tSipEuVFwaeFiiPjx390v/hNqmY74M
/KEVwA98k8HzMTVmNjTIWyfEQkM4bMX3xoYiBf9PKp7p8XNxTA7YLFMNW/BWLTrnh4xkgLRsk1cM
5t+xTNfy5AN9SmiK5dEQu1fJ3TkY+RWFzoNg9ABOz+fUtUxH066ETpY3DnIiatDfvmTJtUBB4D0i
VdagkTh5njijSPT/V32OfCm7torjvM4wDNXcQ5Atiq0gFbvy7231E9qQkPV3SQw6bJj/myHTbkhP
9xZkI0PjYmAyn4IU8kMbGO2kUCh6aoaOyNCRNNcb+1HP9HT1OGiDGO5ocTzGkeXQFz3C8wnsIeta
BrPbC9DyrkcqFU/kVDXBzamJXlJ3bevAiZ2F0LImtJ9p4BYiAVXh5nAFjl0qOjvYB1EJAZtVFXqx
9N0VccKVFzm/D7gKmCFwr9rqAUxE6Snso/jzSciYqhDmhwx/ZvPZ+54T6KeZKW/GMXP4AEYTy94A
Vt0Xrilhn+8dje43tNqlD2HiZkyxiVTvXFPdp8+37qPkp7DLG07gozj9xXgv1VyBCfu2WolqnVxD
pP3/BQD5lXm7ewO+LPwrF+e65gWBf1mk0hEu0n3JJq7uir44TlVfqrjN5xNp6ceS6gDqoeVrR5ns
1fetyYbpz8hWn86nHVHj1EtUafjPsK4UScfhdKfD5A8ys9n81Lg9jUfxfqHDw2kgGbkekLnpQLFo
LDuf+WpNhKB2S75ReBacWnpvSfOnSwEkEo5xMdL7GhcHN6zXmpG0nvfOYp97/SWtrpHqkTl4ak7q
n/K7jx+v3kJXUNaO1Qza4uhpCQJan0/xJ79tptMHRhEDrNX4Bsv3WWjAp2Wk6QSt5huVB2NyzwkP
Tzi9IkjrqUwyZ1TITzSBStPJBHdP5vyjfNpmqjQZJmXz6UAqCq2XO3LQI1EWIKvx1x1lwaxuEU4L
Ao/4Z5hLfFOkrDCbWhhIiTZpRIp/W8DaWB/nZGvQEFpJ90X+FwBvL58ES2eCIQc58rtrRg//cY2i
KczyH/W++nfnZX5egJ/Wg02L0OZi27tfMS2Phf4hE47I+RbNa/X2ugWf3dtZM4DoHPssuYGV9D4D
iVBd5BnLaEzFCkkUbXsTk1VhPxKfWSPtFDEvvBIRjcAj3yV2r7ZFyEdrfqZDYHTSk71mJkwJnNlO
B8GvqN1HF/yed9Z4tEaqGKUHkgE4vH9R2hM9KuQR1zzqg4R5kx/hfy5i3EThQ27GmhnSjFfopSB0
UP668by3ctobRJtvT8xNs4IyQ/Z96zH6mczO4fZPdH43XJ6mKpuczxn+HfqstqJu4k9Cz9CtjvG2
DIF8uum9cvcyR8i/kWspCRchwXdIyjjIbWTThPTetYwEDBVjAnfRKlrBvCsoAE0a4P5+lRDsmfnd
6T15aofuDgdwFc6w911006XuNK2oKIMZ5ehKul9WsO4FZTFqC5ag8yHlUt4CRqq0E2FWXpd+BlaW
uXadAEwJ7wYUI/yH6dRpTxMDcT2HJUsDEty7WnOFl9XvUwre7nLOM88c1uAsCZcuRMGwpCe5yWgu
L/o4uxTeZmY5SwrRKdkdUciHlXR6dYraTooaAjw6flxo7DNU3wmMDbFEso4QkknVgC2cpEOs8vF6
HDvobFcg7XGZL4MX0uEYzT0X2KR/TA9knunpYilyPa7f4QVY4LVxV7TmSTAGRKAZYVvyCBncKwCx
BaGpMV4LmtpEARbj0q1H/2/rfQ2QAYNmJq/IThtBYrF+R/C2ZUrhYD7OKQV4seixTYq3ycH6vl7s
LO4yGBKnF2nsQ8iFrq9F94bTvqfesiDCq7d2LAcajXPFwTjfxFN1XSM5coL5GxG3eVkudYYy6Nfw
seMwrFXqUpLhlKVC8AzIg15eYdLmELQMG0xes7f/nWVoBkPEANR8+3mb1NQZI2d+peBJ3laqRQKE
PBKTR37HrP2KHhRCmqv/l0THQQ0D4KQMf65Fc6MHl7+chQHx6OE/qDUBNjY7jJWEijxuAp5Wv9JJ
scrzehi5OsgAHafORV/AdZK97qtgC5/pxZwmf0akboGXIpIhPvDZJ+yVM3AOTxNT1VPxF6uOyGnV
ieTP9XkgIh4GjkqJlBr8QiwIWQqMT771MQRLhGnKR0Fjcd7HggOKytWCghAhd+bYchd/Sz+jLGXV
4W+w5RjBZ15va+jZnfz7HjX+VvuFgYE8aFUXdelCRWkwoREkNCsRN73mzQ+JuMzdXcVzYjvO+BXE
n/Q7NZ12o1iXZbCcB7dOn0NadYyOvjgObO4riSVNZSXPITdfY9uL8mSXeaj0yIAdRms8d2PfL5id
O5Jb3d1RS+xRFwnxvkjbdLke6bDsID5xqUkpTgwiBqeHIhdPWewcvcxkEkU7lRfj8ofugD633TWp
iNyePWrIcB/5lQek+AdMJUC88A6HiTSrO56g0/eOFuUp+4sO3GXAprSnVictIzo/uGb+1/tfRlaQ
ahBeDWEQkxP0tOcbXoXKLyPckOM0Z3c8bVypheNONN5fJlaYAcy5vvpkV9mJkQJImmh2mxik/Ypi
D2yyroraIq0uzKwopqNB8rybX5ryPSPmcg3m2ytK2MpRHGq1sSaaqfSkt4TdH2hVovpDiPhEEOhb
qHRBPP7BHJfBGlSfElWlhvNXIFrFFwcagTvRbQEWRkAFyQ7x3HLAMTck7MDkaSm4Otq+oNugGUit
5I1htDyNOByIMLYwqtMIgSBRtnT0J4gPJ7UXmsmYWwr9LeorMkxUgG2jCTEu/TYoHlsfmDDdJvbb
N1RcamIntXfuajk52wvU3O+va8+h44RTvr8/v2AU9xD9Lz02laO9EGmvdbyESV0T4GRkIvaxCa7O
PviPvRtZl48bRbGoFniQiEcJC7WiShN4bY0iOHpx3rfPF0kxaO3AMwYM9MDWpJavSxSNhcqLgXwn
QTUCGM5TiEuPEQa7XgVPVbAJNhBLB/svrmLnbgHNebhabZLm4dWg2f+zi/WB+cdKZO6COr+JkjYh
Lfi+VMHpPYVgVuF/E9H5Sa2Pkca5YXb/lw5pNkgdT3XuRDJhfppNglLFOKu0DGXQTL5K92IMoIVT
PG1LLDCtBApmp2rgmzlOumBz6HKgwuZ8gTdhUWYIpqrYa7SLX1NIrOSwnpJLUUrkWZ5dkKPmkYcR
rRSmtntaa1mzmk953rIrvchO/HBrvNEEtsoPcKgvmSYU+9Mb+5k4WcyLZx14BFMQ+IuQZ4nnOlpI
SIPawDBobtxdqE70DcaESCR4EXb1CFBuNuGoI4MhnSCtnZACvG2cXoXL2t8o7Xdja+/aIyMIv/i2
+vapTJrPpYNtju5PqMKj7IyAFia768idB9D54C3FeKOD9FERVa71TB1IgZQ/MCycn5p5v5Go/+ka
jfrrqjGXDp4cq06mlhkV2nL34IxCzsq20FkSoZ0Nv46hlzMcVNT0upY5vx33dtKETPbjwnK7vNLA
QMDF5RG0bOUxjhKMKor22ODlCJvjPCXNA9uVCni5+HivvnntA/QaX2kUoUnF+81wSZJjvN4xScys
deri883BRcmbZXTLwKhYCISXUhMNDeszi16r2ZdPIN+9VhdPhGcFwN3kJ2MT9w9GcmbmjD4tD89r
FvowzphXJv5FKCkI8W7tnZZmkko9/8GxWooQUzKh6LxEm8/XFKuh/2pRgp/0liNlG1oHgjJpX47e
Kfa/UzIhnGaL4SYf8mciBlkSIdndtVa4dHMPBY6CXer+nTb0e8QqBcUeqhxEfeVHpkH60Mo8ZubU
nDY2TPDuVnS5XoiB2UhU9+lSvu0M4x9rT00tnm2OKVJJ6mctx8sp5hZx9vt5nx9ZGwHwBIRKKpI5
sHn/1APXgBkqv8tzmfCjwpRQ0/CwbrdwRqK4qRQXc8mglS6BeQAgHKn9p4Q16mNgHjraYW1XtB1J
RkFUe/PN46Pm5k+KMjZNC4JoRSsDTI6tuJJIDZ7aojrA93/kwVVaE30AxDm0Qr59HMs76B7P9+Bi
gh8IRVumAleWXqCU5VKs3dFAOBiiW+LKcC1W4/jFqo/FEq6RCX71rRnwZbYvEHtqJl8Z/faqNZmg
VwgSj48o6iNQqSF3VcmAJxWxcoDDWCTd9t3X19HI2JA+WVAFlBLAAF8mVIBqUBQjEzmI5qVkKPH3
RNp17wX/tyB7mksmeY50CMhyGgC7IRPt+Qt3XV5N1EP+JWbIFwCJNoCCLuwWdqm3V0MWsk1z3M3c
RGaCQidXVnLUpiCVgGqIgdHfQ2qSJQYU7ZUaOy4RVMuZHxwM+UcztrQNwHQRRnl/7kFrapjapYun
lvK0gG14yzFFAXgsjKJgcGgXfmNaANBoJxnk94OrLis+C7nzg6+n3Xh8KZGvMDOwgTPN853IovPl
AUMmQH1BgQ44hppKOQVR9D8u82LyZFuCqEKKcJWisaFxcwTlzQgDkY22BGJ1bMrEfqxfqgjflC1J
zXDo1iLYqqi8sSU4ZzRcD7uK/h5jHw3Nt4xg6DqB1CToskNgZmMsRPOO+1TsFIenjhFDFq9cTnIk
b4ptx3iUd1dodTHg61v2Qz+oViwF7ZmIpl1BOm+U6bX3dFZqtMlIcwrru6f8ykj4rifRbTtBcOR8
sTtVEAJgyTbwz/snfNMuhCNKTcNoREvG4J9/U24huDRmXrcqJlkO0Oa/pMzdNMcoWBZ09VV2C8MJ
mo+IgZ/wVNN8q4qK99urYM4IvcS1NMSXMEytPh3tmly8cJ5mZX2pVXI4jpBdKgONq3FhadTPBCiA
gdxYBIun6UaRghlZxcCMKb0M9ZY17CpwmRU7+cOn/IaxrsBOe0laykNWTfYFpXcKY6BEp4emhUKE
GNjAhBSyLwr7To4rwzye/tJQPJWr7Qg8tGmngoCacz9+ppJcyE28qZJ1Lt79T5kKxsuj73z39AGo
6YtRGDWY76Qc2xorcw7Mwa1DZ0Yc9zSMxzzrisbHKATzXMi5G0J27jjQs7bv7fDQhS5gKpXj/X94
2PAbnj8Cl4C9m/M2GjjwsDiPRx2dmzuw0Xa1tOpfVzLNh5m63GPqb+V73VgTZBY8fJkJUMqfp3zV
7uC8EEqJGZlc1hW9+i9cEGf2hzZMBxg/XykDALnntZ+J8rcBArBlihD46vtHK1mVl61LxTqvgOvF
nAc7WzWrGqYQew9FU2iWXXZ6+cOpv+lBcxnzv5b08K9o9RDTdjpshQ2kjiOLB/X0QM7t42pkmtD5
30rq2fF9zylNHF9F7SiXIF3MeLVqj5CD8nYQz42o37vHgg9kHm3OAunHbLolxbHNY54inYKT4mSL
z7PqQTdsilprCLGM2WmY/SNvfSwS9QKUp+WlxfsTI8wyh8RTJfW87CzoGSnapwtmJbm5OVNrYJlc
eANlBi6bB2P32z03cJgKgHu6LmZiSB/cZ8pfCWuoE46k7CqKq1D/KRHzcn8/SS4Brm9hZOEJxdod
pwd92CXA54qsbexaIR8yxcbOfkTZb+KO7U4QNK4waQyFnBGrCAcYhY/3dpNi900I5CT9gG6nOQOU
owThH2E58phMgzP8mhatpvZI2LP+pVynkIpcv1sXmk8VvWuJQ4Xqkj8r/ghyXTJf1genhWfp6OIB
1plNmv2mU9bbZOd7tm7X6ZrP+xoNI+eHLD6gA6In/ocnunKXSL9LUg1XHF3h17kNjBeVdnFjVtwK
iOwritOp/A8Vz3y70hqyEzr53brQRPi75KLsShfol3mTllZgan91F541SKVJs8F5/zxKSilinzlG
eYKFxWRiFzGKzvshjMITA74Lg9zvu5+gGpXqB53QRR0xSjmduXIuBOgNndpMlL2kgnR8KSiDhLmD
fcDEOY/NaiP2VvNA/GVoW56abNMBqxr8fDhagS+tNi6fPRttLBQ4pNaeExZ+l0u1yJenbeK1VhUI
/2KaM/0Fj/qE2qWIy4IolBPY6pK3VNq2Qm5PSqxYQSZRzE0nYs+PtOxdwwzYPoX8+xkM6GtN5vvL
E3jMgCFHQ0M4nfKLvkRt7ylGS1Fy9yG+J2OQl05UiMNb5IlH5Ag1Qz7cwr9nyrgxmiV931nszVly
bZxZanoX1Yx8oDBQACzbLKA60EktFlVK8p1Gslhy0w7PcQv4loMxuN37RTByol7Cah4M2JTzyur7
k3jpLlvHAlbRiZ3tMk3I92oVPqBmG+3VvjiQZRg2ZE2BugDH2IP33uBk49ZQcEJcOYQQH5VXP2+x
cf9sq5S54SHadhfpM+bCU/Od/iFGBrDSobJ5Ccr1wOjEpAVppOsg0ptrBh+ZrIJP5KcNydQXckdV
CgzQvdaRgfM7WRw/6qLB5kovMg503aT3TmpMeefLnBC3wIhF1PVC680jKzYML9eJULwxJ0FDEYBP
J8evqiOTqBr6VIx+uJTYu1vuZ5+l0ZfpZl3pbP9KyPWyX2uRWPXpZ7+BqU/QeI2BdHx4yh+Fc3na
868MXHCyb+WrVw9h/Q+CuD4V3BOEvWsjgzGJh5vz+RhGt5EAWPlGzLSf0oVb1oQYylsqNhaXdKOg
UVbSlFGJV7gU93qUkBbgTOLfAqKOZM5q4SQmM0iSe+rvzs5A3z/WVS2rwxFm9YLjhHs/yg9+8zQ+
9Crvfe96aWyQyxcIyb8opcnTsGQgbOhA4ejfWRQvMqEfsegXzMS0ELlZ/iqppuHaa42uiwPK2CTM
gB63fe8A8wSPhSmwddZ/uBeZDvNAqyBr13cpgpE+XMbTc8J29kVfIWHRLtDBQhfMCXv379BZRpWp
FdK0HS0qVKugSRL5quFjF1hX/GmkNMEK/r24LvyqccLYY2ax1qtDC2R+9Hh+NdLYr0gtoGBdZZ0Q
6ol4U4JaUMLoAt9mOqTe8xh+dTiBvOzOfjxboUSxSw6S2P0zUUbcH+wMHlctELB4O+kKgWbqMZJd
M/1LitoxZ3Gi8EBonIAox/yx+/D91uM3Gm4Ar2u4QIcXN4P+sI1ZL421PyxWiO211tdb/rEQVNW9
MCvhJU2bL9lFo9wUsUUjzjX+4UqO8R8iJdbE9qi+QKz+Ef0bPa98jqDyTbybW90uPYptxY2JYfHs
7cA26LgBMnD/ivLEqm9Wl3EamSiwsk0TrbCpd2ORpzeApQ4DQQ5RlZMuuhnptHuBY0FRQyIKrtQM
l7BQ9v0POkD86GbbqvS/sIrNtbE3I5i3FoyurEwyaIoapXbJTC3sIRnP/iCLp0FTpuZCivujP05T
zeyiT9OiB6L3mUUb16ZxRLJOjBNv3k9yazzMqVrG5YX7/xrpw3omkAQ54DVomoE/5VQkCIMceKJc
+XBZ6Geq7mJAkwUdE8axPluet5xUG6IUd+rB4Pnihb3Cqpj1h2o6W5EauK86QtYslZtuPC6Sh9SM
k1lqdLnOVCoj6YiyfYyZDKuuQfJdGVjA/Zc5Y+Hi/f+D1tLFAlEtm1ENia/tLa++6N/IHKWwZqoF
ecCRHFpMwi/gx1ANvlX+kb0DkB8Ss4z/NsZtNaySrNzj7FiBU8mpqfZtgqbK/pzn32fxfr/6FcQx
t5QIgSmFd02wnrgtztdiOXJr5nF1viSfVUv6eBddvfvV/+s/3oViqXxnQqS0xOovQhvkK98uQMY7
tQQ/TatOWsS2IOshKW4sr8J55iROiw0g+D6S6g4c6aeBTV9JbcVBbWrTjcRiwCrEKKu18kwRfoua
6+lYevRKay92pAfzCwVTcmY0p+pB8CpxWPgRxvMMZy43GxLy3GZciUQamtgpSnpctaBxodUj7j8s
D9E6iTi9zgST9KQmwnfKT9iuyKtESib5cp8up7udqU5OxsGC3AWqJMQl914DX+dgLQHFR/+3p7b9
t7OOoQxn3kvp4/BAg65rlldDOAOkbs8jXoivz1TUlLaA4UlEU0lohCaEXCp2FUqLhknc0htSSJWA
jl4ZucO+yixsm2SfYkmLY+vBsxN7Xah5ZX+RPu6tHDOC7zUgfWV+/FctNFn1oGeUiKGko3HTZtdt
9dmum31OWaHDF3MjYQ2R6t3WZlzjAIMMISl+mx70udI0xXwIqbDKlngbefnNF99EiqBBUx4n10Mq
oGyYgLHrqjZ68yUwY2k+y+lR3wL/gQK9K5SR5AeWeDD07S5EOy2ZhJnI/RBeXfsOVw5lqjlGF8aR
v0TGRhxt84odbzwQFXRTwdc1+9urHkxnBZIThGc/vnUr1ua58IOyxUF6ErNGpA4nhU7pZQgXagEA
jWCS5H1g3i6ipCSX/+QXqo3Xj8/dm9GoCKi32qmskur6/mP2+KtaLzuhgDHDQ6hfDXUu95Ie+lV8
ftVOpkVxGPcck+T5EZT3iJ3ti1jR819eCCN7YOhUfnGnBBS0SvmxmPJhi63sfxnzstIxzPOAyvdS
n/H4vvtqmfSfHZzn4DCcBq/3flRcamYrRAuMJSn5LPI3OEXIK62rXwjBHHzsrmnfZG+Gnpomudcu
W6b/JDIWDVVkW6DyBSwyunn3/UlXr6SBucSl2EhzPx2kg9khyQjK7iUU7OKD0qBIZdPKg7sc4/++
WiYT9LfKnQZ6bsuORjECoDlfuYt4KGLeV+ktvKKq03bTjjxIE9HGywqq/qgGQuTDFo8W6MKffYYz
CeP73ZnS4gCTK1zlkju5DYpONNuJ97f3bCCaDEj6FuCXIAAerkq9GUhnuXte4R8AruSFY7uQFUhM
auBxOSQ25CH36+Ur+U7pFIcUToJRSSrgNA0ocL2Sv+hRk3lvxOHINvrK3q4DibpzBQ8wjEZET1hD
xoCUl4WTtwBeW9v/01X9z4L6OFYiT1Ch+PRAI5shroBv7x7Ne+/AEsgRenyJGBE4RuoEN4Nks542
V3L0Ds2g2IZXXBIDPPot6xdDa/VN3ITmtPsJ7rWQDPpd4JYR40cz32HdVoUkKZ2B2+Vb6/80Lk74
dz9bNiRt88jsYDa3eNFMzbg0XLbMoWzu7tE/3uY65v9PzWc6mci/XvEFtIDnHLllxMmxJQ8IDS6o
wIvH67FNKNNjiT1/Pt91p4aS2cqwKhNcDJ4eBoFPiAQZ/DVMGk+Wg8Jm5pG+DUICKcV4EU4y/1Rc
+3n0YCmW9v98vQktHrrsxtTHp3/ncFsIapGW9U930EcRwfM/TowQ+v+ySXL5ntAROlAFuHaGd7Qx
aZeFmJmS3WMf629MLnxYF2JHn6uC4Cbk4LQc8eVncU7nhr+sxB5d5qUOhxTyj3oUBGUUdforamJb
Wq/npgykIJh2XnAmTCyljyilg9BefwJEMe64+Ps6zhDvHH7Z1e/nRilR6+ufZrcCWKw/59lY/+ct
iO3GSVpx3txTa8ZPLn3tdVFbFZ8ZAJpL3mkCFb0wo1w3g0X0gfPEziJbCaGEKQUz8WDooMovD3b8
UC2nhPghVyLjpf/APK+fUB+YM4hz4kbI5HgE6UrukoDyx4swHVzERAffllb5MpYpfQ0x6GExkofI
bvVccuVCGZl7GSazJeNf4d8caEAuQhr3+EUSuoaSZHBgijZiKKdUzNo05tkV1xupzGZmZQB3NVn5
YhiETnkper3Q2xAsITs9wkdIcTVa1I3FVDGoRs4YaUYnDQJFT4z58kHo9Ss8JTm7qtnH4CzFCqhp
MXpnUzM3jLNxIRjFi5UF3+VKluMuPb6ls50vNp9kJeHMNhH9cmvKA1rmsbn/t5H8ypwYAnMxMYM7
RlqUuTdpOVm/V6ow1V3D+5ctzEMKvatISvAZbEcKd+dHf3tpIOej3Mb1mAtotrQRsXoiffo1Ha2N
HNElZ93rcmT1bD96GnpHUwZjuSuI09E7xghuHkGCFJvnfKKLE1u2p8OnVwkw7HgP5CrbWq7IGCTf
hwSvNyftHnnSbCqM74W5PZwF+pFv7NTM3lYOLU8jW6UNscyn6AnTU6fhIDc1CnEVMarJkWwx47bs
IbWTqB4sn9qf8vVK+/6LGYSK0IS9fGDvNixNUzl7RI3Nepv0B8AYElscCTNBzInUgd0Z4sbarYpA
+DdEiEpKQzKlxKyFk6kbFVWLIItFz/hmMupFx3rzlrYGzrOOvsDN11wqMFpVMvNrPBAg4MMgBB8P
yaNE4IX9K6PSzRsuUSFgqnu3YIQiOezntWFso7aNrm7qyqHc+eRvfXWbVtC0ELNOlGuasxiMJGXi
xJ0v1B8iLN44YnS9GcNnfdy2iex4hwH1o6i/AFIeJ0prC9DSCsaZ8ZM7g/Th1WBSX3K2MawzFjBv
kc76QE8cNM2bXrawzxwUTc4Dwlqh9SomlepEL3+OQgbR9YZNvhlozM0n3PLjVwnBke9tO9qyOy+5
Rk3Rx+IPjkawCtpPA/QNUEr2/enO1cFju+8I+WWY2t0Pq4qmA+fgoh7vfKyHZ1hqfvj1sb8goe+A
tgdFkAYoAKnePTArAaBf3utM4PecXJ5A3415+3FsLFnKkvE+KEPK5ivMxmQuItbKETZEN7UrOfuU
4uChy4MTnbG1Ln0IIPiJuoPj2iXniq4Nbvxe3dVyh/0a4th8B18nAj8ZMjGrswjH/bBQMgb+BfLM
usaspSNXvtZWj7IlnU3MRZwJIIMUDPRDG7aRCeRYYD7SehAarrLlGvI1Jf30AxbLXEV9ge46W5Ph
l57g7sLKLdSHEq8RptDkPe9DktUe4MAUMftAI4cg0b8KqPHzR9S6XIh6G2pDdyC8ITWBwEuVlwxn
y8sZUmaQYqEskrEEJsa1kCobOp/lW3TAhqknskdi9xD0J0yeXDQiItAkFlykbWoCCdye0771Ieqg
9aC5RfZ9yY4+Xeg326/+KHjHt0Og24KsIJAPGFSzgINGc9rUX8wDpBVuU+8NDt8WMLV7VjcIoUeg
F4a2mTPoJAnIHHnlcm26bo353BeydZTxfW9ncjgUBD3inJuY+B4KImcUUY8yMZExO2ldCtfNS1F3
0pre/liNNr2u2JNrfN70CpEF9EFeM8ucey97S8Loyd+8pmaVS+02gLG0Icye6Ivkc0sai8rrtCH8
31/e1H9Iuw2lB8WJGg+AiLcl9AFbgd3sUtIY1tpQShovsMPy+mJ++AJ9uLP4oa5mllczPZKnBGkO
bCZ/hyTc/RdJp5LQMKUgSRum5oRsuUaKXjJkMzt5v5L61eK1YNqHDZOfM1hU7hW9oknjfsM1UlxI
QRugWGYXQWFhkwiGiJ86OY3E3ddJk4PzGI8f39eXtPM6r5VMpMyEIjtrc7KEP7+3M0MrkZK98tqY
Z9WJcTYuhRpYDBHrigowzBZXeoTeekDivpsF8YewWwXc+mm/1IrSMZUy19A/gB2nNZ0i0V+3UcWt
rjaaj6kBDYrJ+cmyCeJts+oJmYbUTuVpXemoC022xpzM3WF4TIyl64NPENPrKQmHFhbfGfiTsv9W
Q8N82CtsePLa8lR2lHkD7Z5G/CNZEf0/+2amPVI0AUg9XbaJ/8m9jV4mBdi0e5Esv6J1vAT3pcWe
EnNVnV4+9IkzdjaKIxYtMaIT4euj8Z5gPJBt9LukPKPUEgAr+EzDA4k0FU2C+dE+87FzyWgVsgpf
tDf5hhhizl5IuSO/V63fT7js7SLpaSQCRPqWbgUWy1VK0cshrskDXY+9J0IqoCzA43aiH7P5fBHh
dmTa/osR64shHRLHBL0TX7tASWt4dHN/G336lNZtdM69Ta64R/GBJzuPerukRX6uM/qQi7JLq4Tj
PecnVbUPrn4M+0E5sE0Ukvo2cKrfnP5IngyXuV6b5nsGORc9UQgL39q9HJ/WmBHbgZVlG12F8s9n
ELUu5tGODGEHEX7vdkMUloLpswb7iiXolc7to9Xp5uG2B/m4xmQBwe1XISugkn7ImbyRc/or8FUB
LBuR4iggzi99fahBI3gFSsMAAun+Ip6qY8020AsJfcrqvU98DTC15Z7jWntQTOp1en/LoHcFz9oh
bSnYt5fdvn5gocPvGl9BHkAAdU09BXZM7urQSZEMrBzmJyOCv84K+xuyUPejgnLogII/bC1FdHq6
AX6MQgkyohqusmWlI3hvzuJTJqpeHobe9paaTRb6PHf5HA7aUnFWrUtmtwTLmg7RxGTi1Se2lrZh
ZyCxSep2SqF72uooXYf/hA76wly77vEwgm9szzABRWu+qML0NzF8+mzqyhZW7MvYaTOFRQslhuiV
PJYV7573C0/Y70DQNv2AE/EoBfio378N24TJqmg3fhYBMmBNNxoRk/DoD9Y4dp+e7Dr3DJUdSO+y
/A1aNpRr779QPwfU49sSDhaKhjNL7/C5Al1VhNtMgtRDg83ZfKmPm4PTL53LX6FZCwcJMZ5PCeRQ
8QATiR1X3h37Kf/Pd53GV+FDatGczon17aRVuYHOF2hkj9/I+QXK4tcp++LDyyUkotjxPowhndt2
xnJrOOeWqVbgqXpPkoLip4owP80K7fXmNKkez6WqkkSGt+x30/BjfAcejrj8QnZmQuiAKFGHdn3b
p3pTMM2sZnUbdeBmzDM+sPPR4RRrKWnp5n8zXFmO61vw+7411na0BAw0iQZxYjthFHxxGSfa+/iV
s8IvU/RA9+yuyGDnjvdJNq0cDG7I2VNsMpYC52To3arqgLua4Iw5t5Y0W3Q40TCnuljPk1YMAE+v
ppGO56/p0US5l5xfsWGon+A5VMetfVw5kknETbYkDNoK3iQaMCb/OwaL6QRbz5PW4CHMR/O8ekIG
bziePZT0yB+dPZS6egPm0OxPdfYYZzyCw8cidkFljm5y3UnPbWisNw4zKFrttyS8fXgf7q3SBuIf
uSz2KC+tDjkb1yGOeXrAR97YRI1wRxO23q0MaW088L7CM8pJCJFOQ6vgB49azSrME3lmgcw16X8P
q2fKtGzN7xopWEsYPxUPye4Lh1g27xCX+BzVRId8twOBE3USBz0GH8zH0KuAeV4PxD7L0GLqgIxk
6M9UdW1fzMBN5V0VWB3L1h84pp8WktD7VuRiAXaA+YRPP7+zBnHiaThDlObS0iqfinxqd8ZspG/o
AqEFdJKLItQATKc6/Nvhousqmc4NH/ZoErmp/drsrdJexz/gjsgDRdY3jKUPugbVRL13rJh+l5D+
3AhWBcR3QBFQs0oKuJ1bg9R5Z9PUTNCHo5XS2C48Gy0MQhSblE99777dfAzdKY/xgqm/6/4fAmhi
8UTyNCJtRE7aQRRZgaVNPizp3WT6YRok0SfCtbtKVcDFhIZprW2KZ37NndwcEyVXtDfSfkNKBrah
lMnzZQCSc2HP/2UDpWViR72FEWeqUyhRPVQivXg1knE0g7cYj1JaTsTRR+SexCIVnREWKEDL0U/j
CKWrquB6AVV7jEzfS6X41GqfcrS9qJbvxEfhwmwiyQofKy2HgBANbLcw7FQ2FmKt0oDNQpVorXIw
eW7uUiqEXgNvbsUF6j2HXuqJ3Lv58sZPEtS5DX28eh23ehx+XLYM7YjV7jvesCe1sqlDS72V/1i2
uB3qDKiEQL14guZHr4PeaqNJkgTLLgfEmQYQtm/CgeOfXoZipiIkCIRkZ70NQYNJoTRkgtiv4Iqb
+sFWI9/vVcU7jcVYwPy3SubN8jVksnbvseriVElqvFSfZbl9j6ZB6LYI0B81oseKcqQMCpr8oUCN
112UgduvjojBkfhLBrNblx44ofPRZJTi9d9s0C3moDjS5mGs5Le2I5lZ7tOxi85ec7zYzMWu2BA2
Zs9jkpIu9uvG2AYiABEf8c/XWBmr0Fkd3x5rTA4mbQk36cKa4uoDyFxY8395NG45bsF1YfMmXhiF
wQwo6x2BxHkvJ0i3c1xC0ICOx8QxtiFkAM/b9PDkdWg2hCjkSyI5MzJ0XMOJl9BAUj7b28xfsf5j
ph3NHP+FoaIAJTFL70XD1ZfholM/BookcV02w/J8ZlMJYE2tgGbTBrxJBs0Jwkg6/BwZjMQ49khz
ufqjZRQ76sXzTpC7DH8IXuhK0Zd3YB+IIagjU6wipORzBmSvxgh0waZzBJGFdHNC1vQCxptWohl6
uiXOuA9sWQ3JQ3v8Z2voqAWVHeW8xbH8LoKbQcSkOnd+0h2o23othNUyXz2FGf1x4185ZPc4Dn5K
TcuNK0TyqFoST5GLBOwWp0hU9euJd6LNNs8ZJoT9FPcABeEPMecXZOYqKryXw2aCY2aCfbf4DEHI
HeUEHKukfppRtmd+AsGm0T3YNENiDR0LAVj2RQCSKtmd/4ojuvqaNB2jwQX6g/MW5KqEtWA9fu78
E/VTkCnFgPvjGdQ2p8MJy6KMi0zFxr8xHsDN6Yt1v2nI27ptgEhq6VywibY6eol3CRdZhihxPNBf
JCP0BbFOXPzgXAQCmJ++mxw7FOh802NjyYvUfvT1uhjm6lhRl3IK4xr303/sBn2RY4Xv+wd2HHw5
kOQxF933YLYY9/jUi6R1l1kJPVH9hxqP1RnfxH1bkUyxrJ+yTiKTL5IAT0TQeFXDUxJYNAwNWTBD
AtdtysxJAycQaJLh5L4BstzRpwbYLwjz8Z8VTqPfOPP1PJNSDxvnaFBkh8SQiAaqhI1tfOA/ZNSr
ZaFRlFpBYsiv4ZUW7UmevM9OoDozN5F8gTTOLV3qTB1mDjxCtviZxbhXgWAKLcmMOY13BGMbw75l
FLg1lHLWfTBnBIykS8w1nvK2JmHHI9ka/vDTDdjNBOFlcV7OlIxROw5Bqlqswg050J6dIcPTF8c8
u2oPKlPStIDdfxVk0anOZOkeS69Kc6pItIwryw2r+aff1ekvfpDwvHexIsllOIJaoSgC/eFPQJJp
2ADRL3zzy5tEdZQUHbR8IAQgDyixBUB3Cqst+P/4vvL9C4KqKpROYS+aqKLLV5d10aGrjeRKkQMR
SMcuafRMeZsVqxzrL8RY9OOs6MI736kYYPQ+yV6i17NpxbabVmXsRkDTZRikZSxR9dAhcvIzTfHA
keNLFYZkDHCpYy15R065gVzFAzYXF8XvRIJJYQt9x39G4qsP2VUwWvYux9AmWNK5psS9E3NN2eaS
xu6Dr6LUS9p5wUgrQkE+InPEO3soIuzZba8m+PJgmNXf1G8+QAvSU2RgTnfikjXRLNT0jN8aknmZ
ss/DWvHqGI87VK1cB+AV+823Vt36cXtKxZrlWbuHY7V+8/gVuo8BXSX3LqcZfetRMWKo+glh6Ubw
feDnGIOHIf6HTXMFSBzvSjeF8N0VNYmMJ3mY5nH/b2RNNPVjtEz1oVcVfF9FJCPyHkCHDjGtGN6/
v31PkPEBSzYKI8qsmwmKjmbQxAOGi3iF5SZ29xj7z6O+WNT52BuDum/UUSXlscB3XNKxMfNgW47z
+8qF3L0dk/OoiLyTMOLx8g/KtCcpm9ktf57x4nrzRjXdygnwBnOadg+NTl8I5sMMGkcfMH0VhCJQ
wRyce9ZdWVbwmrLm9d5/KBRGtAUo91oli2otcdg3IHTTSrVWQHY4fFVuaEkm91fRARadrr5jlQ3P
KRDfrfJYFzS99RizZ0jt+bdTZ7dZ7zMtQbvFv7YV5PNjvgv45khi06wf0Ar8DU8y/aJWaQyC7n56
Jx4V0iLUgY1V6X9AG2eiBYTUvSOicCeJ5HEqw0ZFbBY4+ciAq3dHBaeNRdlr8NQ6BcUVsjWtQi7h
p6h2mQ37MWqSLKFuM8N6KofpUV0GouPK/LYBRsmYEZRZxjjrVQ22tymdzzPLKnP9xpKdpMbwMIIG
h4qGs8VC+YVsi3Q8HVZvU8KsJ0LNWVdN8OrtG5ag9iVyDpZoOhJlgcK3THN/IxeVSJWdvD2fPiX/
hxnXeqfM19m2UXMQ+jCxuoO1oxADuovZaHQ0xa5vwWISTYsdyZrO0cR7C8RCWdmoqHkwq693jdJL
PWQTBXPTupV3+2AXcPPP8/WGC1ZidqgrULzo+rsy0P61nAb3Te5azY0pC6saigfNGKOlEu6Tsmxm
lBtWlS2ueQXRZyFwYPJdoqtPol+DBpsnyySpGEmE3LvpVRrAheNfTAYpmo8CmIRLqiXHG8ZJh3hU
FESCm0l3pG//qzI3NFIgybee2tLf7kU+YHqN/ktoqNmLU94Agdqi6lfz1jlBUf1j2hegEHTGNVfy
AOscrX8qSEc1gI4Je5l5fiE63jwIyyeeTxjsG0CUIKfaVx+x5q38MKWRNwnGGWyYm36TJrn6ZYR6
8yRhYGe8WRZiBcg8gqem3TED1m2cepYP2zXY5psMS4zrW+jnFXsxyi80cTmUoS6ex8tqHnf7ZAd+
9JoaMFQ8IjZ8txZUtebH+qdeLE7OAuE6VJkxOu+VUCy2IOTFQD3sNUUIUL4gdE0eQxcj89hPafFA
GmPk6Qnd6bnzLBGnEMkKZyKezkeoFaR0VjfmRMJR878Xpg5Mfhvd9kqm5EukaM/37dWYS5FTJPkc
jGFNE+We1pFA+D0RFzmK6Web00pGfpNbC67y4qpN+JA3p7bXqFEx9Fq+I83eeEySCpPfNJ1HE7KA
cYZ9efNMnS3pDwvy6N/r+Zd6y2USIg5++cPuoxtCnuqvcJUgxTENNZ3DtCBYULSv8HJzKLX6as9m
9Sfa61HTy0IHlzZOgLopCfDcX4smsdDcK930gn46P+6Gwa7lEsMpiGoUDmzdgtfKuIdRS3rKW24N
wQrY7k1NBGZtA61EIC4LjqcT7QGJJ2ZqjCFyhe+rLLkoe2D0xmkYyeuTJ9M6iO5DdHQbn+zSsUE9
2rRqfBUTl2KUv326pRr6YOx6pbHWd9wh9nOEq8iaNQm9wWyp2mkUDDJFJxqXCXiYSZMzpfXNdAua
vJ0CPPMhyAxunh4GSGMG6/ocvYrS1pRquontluHdagxRVv9f7G8chr4dWElbLizE69jUL8Efbhwt
H7xIzmBXJ+SJXrtnzE8KVYHt+VttvytAcp262HaFD648lnywc69R73aVSBDZfRerRTCyzodw4I57
fREaEu79agQThiwiPnw4IM02hBWSE0DyNX45DGGkTE9+iZ4mkI/hCY0s/n0ie/AeyhnDouIy9ZIN
RACJPkzf+8BHgV2S20Imh/0AI/Cw1KczTrLW5PtAgtroq0zCF4gdZlcHQaRBogcSzPKG39Pp8cOr
c5QZNW7POsSfbkYJrJSo5Ln7w33stgaQZdbrdvvMNJAA5cHDvPKVD7bPQ7Om65WjUD4aMp8zq2+Y
kx2VKVizk1UV1XiFyTz+2vKUnt8q2114YXWz1lPO3dtHWGErlKxBQwdR7q9lHUun51wElmjyECI2
hdqxGHzeK8wttvyN1sVfXeV1vl3PIsj2wNzUWJCiYRapOawNF5UKH0+wEAeamtdiNMqW2ziz/zgZ
5CsWHTPfUZAbLYix9RPZX8Mvv4Th49EQ0oJpYNVYI18eriYS2Xa415QFr/DePqT23LVFFDfCINFG
3a55xFkxjY9Ko1FqZsVROjsniEEBVDF4p+vx5rFF4J+n7INs8cGggWWtezEzhL6+0kOWdReGG0/c
F1cXIEE/iCbfGw6e2smnikDsDvMeCBMhUftXciUZCurMb7DQhFFiz3CxlQr5bi2AptCxiclGRW9I
e37nfXQLWbSPXTKacUv0QaTAJcKGYcsS8vRLCb2mXUNbQFQ/P7YQoIo3jWUg6zYIG5TCyrnMd737
SMmOXRQ/5J8VzJtHI5cHLa2/DTFGBGRaNC8K0kdz+6Ik8i7zI4fLMulhWE0CyGIQ/qtwSqqgS7Mj
pPSQW/N96QBfwyKQ8lXGRsQ5fcStQdQDPkdvBHxLbmNvsLM3mMCHmw8KxwY+cx9y2VmNXVa56tK5
ICtfH3YTnSIFVeya6txG0qtoAfI2C89St3kOj28oda931MFEoy3QvlbnJey/K+kgbSie4zLAZwo/
rX4J/vEf5393dQIzuSn6mm80V3GKtak/u+SgaIqmjFblWZoNAEXQCtwgQ+3fbxKKZypJzdaJJnch
hAe+XFcamHKTwmFLEkns7chSokcZP8lje9iEOxphi6ACKmUnDRtqN/tHSjUkra4qq2y4ptgpSJG7
Ld0plPL1/FyUeWxk/L8pBaC/P1JoxRyDlpLyfg4lx4TtxW4/QoMVcLLjXqCFFu/FsmP60lJ1eC1D
3UFe8NyrGQvNjO72D9xhB5UgJSbelrVi7TrYqxfX22VPMx4O5wSKd8M5yae/zSB/lvhVnnzvDJ8W
F9ROjWkbEwPKEij3r5mP++AJnwah/VmzarJYI11on2KkOZMNIvKlz27K2hGBDUBZU3KraRyN5s3L
HdS6TawxSlCbzc1lQWbPFfi9CJP0Ry+LwNU0ZmRXccJMfRsD/3YzJBnxR34xwpVQNt0SWj+TvlLK
iuJorWYzet5dXvf4AGieNMGKIpMiKWf44ig+783+RK/4P8areokzi/E5JPTcPiarhfr8MggT8mAF
q4BDRDvsaamo+Anx4DrkMlcf/EZS5fjD9e85a6PB5BI435+JwaKZX92vlBxtHU9d1ARz6zpGCRcy
l+rq5yXcx8uJxYSzorfsEZjKLWOR9J+ZfGgmQJaCH+Qp6Oos7qBs98qBTDRxeQEbGFFWH7qeZyMw
yyQrjwZtXAlS5o6znkrwhhc5pqhHeYM82o/mE2BVt5CTSd+5+O2MSnQP9DlqH/C0oscx3lgLz9QO
IOKDxD53Twv3pJ2tUbYepvYX1Re5O8fhaHSM+YVhWFrhUdVU2FkCHUsqGLOxUQs/f4/xnWsBq2ab
I5DipycF5T2guNi+5QBz42GaJCgnDjgxaOTfkF3F9uOeAb3wOAyqCrtXrvi18k/CnGpCz3BdpTZG
vsNVxOtMTRiVVTXdl0Fi09jWJ/kFWwwjSn3IdCxUtnHdWkqVnqDMjf5yKo/d4pMIinWxN1iwFERM
Uv9WmrlvrIY6Ppa6pQlm6SqdQXCr5KjhAut8DEaBrBaxKTPvxLvLvMk30+CcKAXx4AbSAKhEk/Cc
ozxh6urwE+decnPTrZA0JMKUrRrMoeh/K6oVv1EA2MCQhDTSWmlJKYP+4O8A+kAdML+URltKwqRb
l+pNomDg8PF/Y5/N5jtQSIKc5NjTmbkN06/HEyQTagnRS/Y43bv/VKiwk1HpWBWNPTsnDlRPfcVH
eFQF+tXYHkgljRrDsJur5NR/15oLa8RjsgyOEqznspPYWTUXGehylDAHtoBIDYQf9QCS5lm2oPY2
G9HiwMJD4CnXI953ZU1uEvCdj482rVvWcYLemBlVOqV5YRxzQAygkAb+AzSg8Ox6DV/zlDGSvWVM
b6zPSBl6Z3Z3XWQ1UpT2D5YrcFZTISAEVli1nYBBQOsco88FGpqb/833MEd2LdXjCwuRMQU1TnOn
g7D76cXR55J9rBJ50+E+Ci3wgygi0Gxqk34qg5ATgYVDYyW8aaYDoeolO0SvSyD7fBU2g5TPwP87
gSQhmskZpUVwxf+j7i5heA1/AlPBH63kO84A5uMuxRMyi7WlWGd8ns0xAqMtrrNhFiu1Z4lz+rSG
6RvAtxMpyg5ht5UB0DhHozVxBD10WdAExfKIZdWmwiLnysAVmBm65VAkm8J/AlbhGjWovTZ9gJns
X95RGm0hvvE8A38npPGLZfDuNacx2hyp/iCIxduStIuA9tOrURKpKdFZKcn0F2AcSsxqzSaBuObv
rO+jeJTAKH2Ls5KnNHpRBYMVSeZXRZTJahKewyYJJfPRO4u5J9VtmhyRXy7BdcbvKGdt/yWSD1oV
snUulDZ1wPClOUwBgKlEiDD2rUS4Br3M11P1xCkriyWExGBGrlgnLKSFOG7YViKVNbJnTeNPN1gC
xC0XZ2h0cbJcS9IqyP/eYa+IR5C8BLO5R70PDXDCNOCNINoLZBeizymRGcmVnboChxFtb4hWmVKX
1gYiyynrLeA087NnWF4SgxcPUOqFK/8+1OiqzpV96+xJsssJiSGa4jTAngLVwuh9jsB1PLdxyQtO
p1l4BWxlysIUpCD7+0TEsEkOCviYMDPGJXE5M7qvhpTe0MdIZXvqYWbnce89sQ6hBsvpi7tx4Ofy
U5r4I3yC0bJBxUowbTNAPFJxvv3XLyGqJgY8EaHBjsZ8K6vGkfuzHF6gHPIqRQJ9/2UNkQKnAWM8
0paZqcnPVOHpPuANCj2p2AgmIimj7OptSzdZOGoSdl3MSe/yev1u2/ssXAMVSCg6HFdzrwDOAfCs
wvgB44EvCg7kATNvxYTbDkP1nXjsSS2mj/yWoPB74Y69EbIn/Y5b0BpyCPlDX4Q62/K2VtaqKVhY
+oJFL690s3R0JwYBs330nt1T+u+jCYlVXBGT05av4/Plz4DuzMUgKjBkMyGhz5ZNZGu4beFqaTDw
P/HzY4LVxdy6eJ5M87ephHCxp8bDowws0dwcdYSG+KleoejM696jfq/P1s5DLXkDM1F3D07yUFz7
hkFsc29qDC3uTIHB2UKANeZ1t7mfj1avCY5/4v1E54NIDL7eDwiDm1GqbbxaI6EH9ilddce9GXvp
2rzKocLVz2CCBwKDH7gZWHp9ki404vC8dMfq3fpEhcP/XOxUB7GZwXClRnqZ9P8huKfCdA7/Dpo8
mbQYuQHvpndHUOFQDC/5Oo613ErR7q+PIafe+2dBre58roEH92PULmcmzILGmzYbF1EfBQgaWMS9
EZDLb+WzGw/lQH087mmpxWHRhR65KM+GU8uBIf1ZnIwXFkzd3u+TP9sP26oJdawu0an1Q7COo/Xi
Mlv2TyztnyF5Ipjw8+ZXyYxsTCg2osDvMZI7e6yyvC6MdSTBevBHLC0xQmWByEwZLE1x5z3QPf3Y
Hnn4GN3qlZtYiUYf5uq1XyQLwEOKZ7WaQ77PS6faQnRh66zYK44EN5/IR8yFoBh6cB2MYNXwfAyk
1gPUwZ8s27oGa/0bCtl4CWuOj5brQyAZ712nlsLlxyBVAwa/o5ZPVue8IxQ67BF+DjTL1rVC+Jh4
VvjX60HO4hQfJVtdcK/0leX5J6vwCMywVMzZ5fYP3TwY5EXwm6AXTZewL1XJqGWDkg3vHkrrpF1b
ujePJEHHIHPza5EUW+vwH9G4j347Fx8kZIvFVUTwWUs5yhcssRjVcJC+bdCtOw7vd+T+D5aOHoNI
6e8+cxzooYT8EAXAPxTPHovuMP8s5QAEe+jdRe7JNH3608M9wbd5sEY5TMNQzZ6pigXE5wI94D70
9BOCP+/JF3zjTtqtNKJ7hHwVN4XoulOMRAax21KXrdDjxw/fqaCcsonjW4nU1DMrx//FGNakWKo2
dgIPASyaqW/yOKoheS+j5NwI+fsxR/jejodxmpNI3U7wbbbrxN+I59e76A2mNK4ZEYzqzAAS67+b
WPNNnxjltWupYBhaRu+zXJox+JvKXecxM2tXWV7++Dlsnp+RiG30IZZj2NfswDQvZLA3ZMUh8M3e
xqnp+g3paDBjDisDz4MNIOx/qp39pWXjm/yWpXF4ZXo/k/F8JzHg/YnuQEziTW2GX0wV8dzuNK4e
I6erbU53o3FXNCpoZCwygFm2ctR1gDNlaBhz9+29QFXWejfi80RiU9zjxr7F7QOQpEXzpSwANQ8J
D73tpf/SKng2uu/hPQPeHVN/LWcMwgDXiv213p/fxIKEVa/o8j2E72l/vtjXo5fhAiI/jhYMp21K
I5h1IIvQoSOFXP5J7yPWJVe/BxZ3Ogc4qGSz4gRZ5ivLN0TnwYl1qp1RzGuJ4vJXOWHLFTLn4vWj
QPv7BJwTjwHKIE6bkAZDpvDFn4Cp+1tUD1DLtC/9OBi2mRpdgvpBFnQAVmsejkC2WA4g3pV4NLwX
kVcal6FqRC1KRyh4knp7NaiVJkvKIYZt6RIlgtVurkxZ2A1f43XlpWqpnvMuNPCavn4m4i7tC1JG
kg7fI1f4NvkgUK5KVtK5sO44hVsi5qmoj937dlei/fcVmoNxcfULJ3rt2v2YVY3sFIzkndZJF5ob
zrV+lABdbzChFuXCGZdVW2Z/Ho1Owu/aEAqJWwSKv9y4hPWbU+YDwhIVnQtaQx9T9sIqu/EFmLhZ
Id5IsjT4sQM89N5Z5IjIklhFzBXpMgQXlFzXGim0R3Ol0FnYmIX9l5O589X40o0ZI8ksHGKzWsgJ
ByYkVc1xEhQXdrD6GhylX0qqhUsXIqcCQxUIeJctiOoSrtgO/F2emj2KDzjC5GO2YD+uonaDWVos
/MjRK4Zj0ZqMP+WDzoWeCn2aFWw3XOC37eZizSTg0l8+iXnbQ+AByaDqMI86mdMDVB3hamYLvEyN
MQSgiZLg6L1JhBNogTN1/kQbKIhasDeoM/UzZ1qhUCLxHZXplL15RS9qDjOfzBOBPbjtgjxZoEbO
k7DmHBR+m/G/TR+poDkzMos431m+oqw/c7a0pTQBR30KafoXZYPtKzNlRIJmiOyZweJ5kd6CbW92
/GJ/8sxmB74el6QwV6vTHOKRFxDabjFMGY4FR3uwMuuYgfQqAGPH2ZEkNTb47o8881O5bAF47Mth
j4Hrnt6OdyJTh+I96fWtNhlXEyO+aeJIqfBDW/VhrUEJLbHeVJZq4tIgAZCh/xT7SrX+AKyqEaom
v/JWuYqopT+TqWPRO+2cOhJ/cbXjf0HjYL+HUQltDh69nk8sNjHOAnfwPcIqg+fgitgpX+rbjbuj
fmxCI1gllWrPe/33ZYIgFNqBQaVifH/JuSxfHA0Q5p6ul6+hpwblo/mJY8F6qxXo8kKjX629fp5m
sTHuprStPDNAI+055aaPTwv1qKeRJb6RqFB0GU48yFPm6XTIubmf6xUOAmCqsm3Y5d27kVGFtKG4
TKYELxuidnTzyGkkBLNdMsCfkVquv6Y1dsXsPIdQraMnwnsDr47dl94OwXYfpELmKbiISSeSoP6I
gcrQ/fbW464Ots9/imal4RzVaUMNItDrziCmpELfzzlrtNtD+pdSdk1a7qQnAz9vfEb5Bo4/82Dd
5Xkv093mDa4dPpx35qpSsTWJ21tjm1M9/t1709Kyl0xqG7BjZq9GyY5uT3Q8jjWFyVMgC/hfSM2n
V0/ei6mi/kW60qSuZd2kYW2Fih16Hn5l1K2g86LDnpzsvxOIGbZe6rt4NKldG7UO9JZcM2GO9yvb
povPR5hkcfxjp4WPVb/nPQwSafwOyUphwOCoALu9VgutAvBcRcMlfg5FvJhRQyEW9oGxeLw660B+
nagAE+48TUMjRwbDNSPsH5atNWu3WvucWHVPTr95HmkFIASco4zElubl94tAU1MX5m/gwFZmm3FC
K0RLa+UyIpRUvb2/VyJr1CPcDkPfe54ahDeRW/UoZ8/ViI13pCvCa/mJ2u4Iqo+AnIxyfI/As/F5
Ld73O+DV9d3/Ge3X7Rz6X3WnyRjpjGTVgbYQDN4D5iFZIw5Ejvc9m3mQ1admWf5aJsM9s9JMVTUo
B1w2lBca+seUp8ixVexh64D5JRK/co+etWhHTvHP6kmG0KrGvN72Ph2FGOxZhB2F79FeYoffuvFx
peKQjUr8/WGivYQyY695RXHUmM9VaVGtg6glH+1JKF6yeW9l2+WeXONasoxNCjUQ8b3xLrQZO/uu
ft05p6+lgP10hg+Ln+QdGL3VLh5o8f4DIedM+HVQrPAWLdcBkX9dVEF0mpa4V33/0EaN3Uag1EXi
02Vm2XFVt1M2Coi4JcQEwbgN2suY4vJpr9m+uWn1+gHAr7ktg8hqUJNNTd9UOw6ga/Loe3nmBIn3
BKm7Uhidc1wDiC0UlhGZw6oK2Irym9QdLawMcRoO+mE4C00nE5oRBblcl1M7jkYvF4RF9Q5FeG4A
kmL4gi4lhd8bKCEmqzeW0SealJxpskfRCyQB6w9kZ9qgAQyTzSaAJM61ALyu6oHyouqnOWFIHOdz
RK++KyCEsrO1gr7wBZe2Uid3xUqhLNgHwxHRwoTVL9L82Mfxtr3N+ZTTHTds427ShW4zU/Z9Go1Y
Y7j3pLkV6DObvWzseBXGwNylKmCzZcHH0u8/2yBSXXQxpgugIc3JgG+2VTCntmlBf+bHdkgdgCo5
M6wVhSGpRjDKiJiBibvO2VHzmXsorPd9StehDOlEuk2pebRzEVNpmrTB2JbMGlipsPOWUld1ajYr
FYD6SFzbG+PanhFfvW+PaOyBejvTt74Rr5eOKvGve+ycfdSxNLkVgBx0n7Av8P9PIc211gUG6elf
u6eKgbCvgusJfZ6c1xqryUa6Imoh2NCiKJHfFUb+49GV8mFsplofjluyYsFAhORQtcopSBC5GtiQ
SsCf5Z8jdz53/rWtb/EypNo7rMzxmnCkYWz7W0QK/Z10Mde/7AE2j0KcrIFowa9XxtKx0FLitQru
KDkDK8psLEkXlklaRiYcao1mR8V2eQw2BoegAoxAnEJwDE/49Vf5Z9VlelRQ7X5Q16rZMgbYAmLD
hWeqXZ0TYdBg7Uv1Rv9iHr3KiJCkRURLFqtPNjfLZIaFXKTT1Xm41GUgOrfhTz2/layRCIlBOYSI
WFjfegVYPWkWLEgMts1WJgUhB0KBirusiD0IrCloVxsoIz1dH29D8zBskd6EvzZoPLxyA5Q3dEUJ
O6InF3uOhNXVJkvA1SwvBF7qLRwB/h/OQ/ejNRw/mtfGXXwC0uhP6GMj3uUklqzVyVcK1lea2CW1
L8sYTEHLDkfW/7AKZDrLR3kLGHKW4nM4w1S5kSSRcX9TmMY8aGY9nlXPINEoieVUK7VLX24Uavoh
CsqLP0clT8r6m5zG6FGjG4XrrihDlU/hWw3ccc4iwvcLl5++NuxEU4v2r4yreWJxOjqV9FJO78Sv
Cz4E3upwKuh6vECKZxCNLDDq8kcpdROhXJbA5Q1VVZsmtflHxEPMa6SHMfz4rJTojD+r0wkPrUvx
Wmw0nqxjj8OY671fmZbh6142K4EGrdx0WQcG67RIzF26HnjawuZwMbp/pXHFHCbV+O3ZANFRixYQ
Cc9bUB13A2qhfIR7EuUv6kRZKIiaRQdhCw0vo/bIClVkcNyps+OaRulMnYsDP0UX/1m8lK+RC1Xw
THGWK9eqfORyxa9NBv/U56L8TSUWd7ZQj+Zef3P5oK5rPDQV2LSfNwJY2A0HCrpsi1w6U1S3Y1To
r5o/AGVouIE96aNaRfbJ9uf1I+fPyYVQr/lAEcRD5dm1f84HxoR1WEnIDbF53tOU7OzBF45X3UKi
XXfCHIPDN5QCGDyFXiOqKt6xR79Y70ZqMaBpq16kidyVgXn42996AmwjsT/RhBLxiIcEHfGBAwzO
i3GWeeIladkbt47Rtkjl5sg3m7PpK5cdVf4Oodyf3l3SybwEssgaA1VsSjHObIf0O8gknCgD9Ow4
zvtP0qsXwGOEgdNF5ataI3mafynLTB/2T6BTWIcKlr3SkIYbbMtgVmCi9xwNH3pdq7e0wvb5RRno
S4oFR1QgfBTQVSKgKVwp0ZnfCdPCJ1YGYSUSk/GOsk3ELziF7GxfRiUjuWmwKiDhhZemlLLx2JGX
/zD1cabSjdFPlBelnh4fI2IDjb2Vh52KZNwBVBGP1Pa6qA3sfSwQLqiHGvS/4Eye1GJ0xWPXUthG
5z19+taZmUc8Q7J+q0XPxu3a9MygUia+HTfcURX6y7Oaakc9aOd7RDrZaXR7i+tLtSLhfd41KUoW
i0uQhduKsWlrgoI0mEtyG+MNQw7600WsU+SnxzCbRyMadzVYYCo6Rsu9z9XZ4yoOcju6KRwX6VrC
XaO6nXzf6W3orfzXmpJ4rTzQPd8TqPgyDl3MjOF5RbBWC/bDk9F55z48S+UEU+4a8GKBEs2aGctG
DVxHk3aOw+qChq0n/ELzLiktURajruz45kWJ79h+oTpLeEk2AKj4IBYGEebi3Q8/sImRCmZMPHoy
2dkj6wGAWwdC6YKedsNDlljPUaFCm9ZEkqHWIVAYLjsgl8FhE8FxvKgm2E7ZLd1YEKOhokfqCbHb
yCmxNHh3e1UWrpOwkANmhIyeBTMwSdzhEkoWXSYP8ZiWVLb9pgsazF7VeoLYZ/J+AQsvYmbN5Atv
U4EuuyGWVGaBtOQ2j5yEnjHX5LgzrozPgmDV+noFvUEVyFEOERUvl6/PWCaATzcJh2fLHyH2hIYR
4Y67aIzB5RUCEX4oLk0baUgHZRY372XejvQ7lJk8BA4Sx+8HgkqbXKfStWWZ6F7Xw1cDExp1BSI4
3M7hOFu9d1/1ORNDqg/nhgRZo5m5lg0Nx+mm0K7LWHWB8PNg++HFoji3hIrphUSBX/jB06WR5H3b
kC+HP8apPjxZMKrixcPML6tSnNPkO6JQG0AEblK7v1UbrzMl6R6jHclA3OH9C5tQ+pY8T6Z/ocTo
6iJN+lEbLCgtGyaox65oDj0iqu0cV6D7iQAswE0442z5ocGic5dYIPPTJnWn6Ub9SNThfyFCmykn
Qggj6sBzn0aPwxyGFgTIWt/IYIshIMTCsp9v5sy1Tca1UQvX8NVoO49jb0WhgrXVJ1n/WTujmO0W
bIMS1kERwh3DeL/koXuv+bB1koDmsRrGnW8i0WE0WPssucSngPzVxd4TS9LteZqhZSFK0/73G43n
0Rtk30/mE6zQP/rjFRrtAV0UCG7eSmoewGln62dwW7qwLT/2hbtA//J6QBBQNKZnEixLSbZbArbd
E9w6PvNRBF0z5KR99BKZZnUwB1Q3dvJ8rBUAtBRxRZvdv/Rzvam0E6zY3XXEALqd3Ie7cf+vzu+H
n/3AevvbT8InYgwPBFcIBdwrRvVLWJPmcEJtG9U2qn4wTKGTNhPM6mYGpYJVA1TDZcDaTtcm1PNO
whBnfN/Zw4xL9ewsQVXrDAE3DY9AhOYN+PXf+AE0SiRiBOkbWDFy5TvPVB+ittx2XsDNlPQqfZdo
XD4OHGK1SpsbmlBXIbVRPgFPR/87pZcsoMi80ihxewHcmYbAaw3esMinz5XCSCTGl21qcdruR+7m
sMlavc+VwjXvP6XJzBwpVayb2kWk1q9e/FXquL4D8bo6jOouPpdSkqg2WdPW0RWgJb7qnGBlqKuE
UnOB/UL0e8R1tnzg608XJj7kdTC7nb1Svx+dnrpPGjgAiH4w9xfx92ZimxN/tEv619hFqoAq9Szr
b3A8Y4NLftB3hwCaxDvz7+hn11M0cu5NhgjQEjeY5qB/kZ3UJ/PynhUcjxLWWfyJUaa8qz9jQ/+f
jvISMDiOIJKbPoRflTPoe9CWNHs3pHmp0sVuHUlCaT7BIL57kVLF+GG/JE+qzpG9yoJR7C0zLTck
cMqe4Cat3X8WmzEVvcrED+gPBeR6vHXKgLTyANnbp7fhQivlZ6Q/2C3XA1JCdoyFXKZ2OQAgNaH5
APOCUZ775oAikEQR0Yv87eDtnXO0fFgYAP1PTtAnrcg+3XdKBEbPGxicZzlTJLUunRJeCW06B50X
goU5a4fsr24mNF426yty4qlyEVctmWo4M1RyK/UM0CfIvFrC0XEcSH/pDuJweMOS7MER+Sc/19aK
jW7MfWF2L15JWS9Pa5nFXNFyMH/reOGJA3a2qHc9LVcU5SqGayI7o5oUVN+Ae2AiAhWIEK+NVNhZ
KDqgDTXmgauPowrO1BMVfLTk3ICNx1kwQx+IHWd0loqpEIm6DLWVoExTAADuqWzhvk9qYb4UG51M
kIRKQhU6tGZRu6qr9fJ1jzS1HZ39pdtlxn0WtSr6MHUL04TzQnXgrVNx5418FwgtsPY09oeoysJz
qJyKStZGdSri1XjUDsveCSQwovd3+MlUzhN6vcSZHWA8A/Oz9gEcF4eUkEM0NqR62c0AxoDNZx7f
HENpPEmWfeYBzPqJ8EpGATbgxVapEGUI/rLq1rFnYgmwg6NPIXfLzdPN8t+OL0H7/iTZ7czuJ2HQ
VQazrmX9gEihQHPJktlLh7I2HuwCVNSvJ2Huqv/Oo8cZZlI96AtucnmiaM1RGKDOj7J2ya0O19fO
An/i/ckzkFFo3gvHg57s8AChcZyBCBoFi4zRdvo6qAJA0pAVsECC5m8PqhJYdWgQctr5l6qyVNY7
Ej+cIYCRAUa5a6f7WQiuuXCAF++vQB58eTYYCUlxm57JXTwHcrt+v5410+E+wamFcTZJ2OYCqerD
gm083QAEsAJrL2XnnLAjlvAHq1qufrHtqcRWKZwODkY4vI63u4u3p4isreRGf/Rx7lV9mE3iSRQ9
Gwybnq5ziycGAcKavQoUU0LizXSwlh2IsidpA5i4hiCfeSR3KDDBGAMGPIIPXPtRlF7/Y2nKdxIM
cpJ3FrNn3Pxt+B05vC+Gsplo7ifn9C/feaYqwkD63zhthNal/RW33CqtA/8ys14m4BVNEaExHL5t
1rvQ58gsoszMuC3buF1bg3biIXoU1TbfAPRezln0djHI4TJp3Nx4mDsKfsZbTdU1KNn4JC18c+2V
Iq0FACZc3DKWWPDR2ptLzRbme0n+SgNIurOskL7E7F6Xkvi83sQh2rmtsHTBlDcoL4VRLpGYmLyz
vu8VQ6qE1vtFU/KZA8djY4HQo1u4mt7KghMeTzRt6shq3y0s54eSHvzSDJn4hNIypRJjKf7HKVnC
zkkN7+8lDJETsXHhr+yKtPaL0kVj9lM4Qw1z54y99hKNbf7tjqSPr5ej1A2h5BRp0nOw6cNmjPHr
aPloCrjAZgRvVEUT1/FVSCFsL3cqssjJuo7wg/3P1zcl/MUrqKEJ2o0De3ueXePL/2C47YW3LrvZ
3/ESJmFDZAFyL7WGDYmqugnwrtRY/cIocZPtn60FebqZNYGOE+oWZmPOWWuR8AlLpWo1PtXA4Hn8
HM1COPNF+/ha6pQ6QaW+leLCeIDspl/n50YOQpPLthTsk0SxHzszOcEbSzpHGQhj3oN4tS62h0Bu
qbDX5keUf4UKP19HTtH2zCx8RJr87Ck3Uq+hI055JP010nieU0OWUom5lJkpD/UNDwsyCjWuy5lW
S6+pV9sEW0B+cDWvzfUi4Js5ddf07ibYJr2DjyLMNn/r2dSAO0cBEtPGA2/mDahJNTsw0PEf7MyX
J9MQEhL1OHrYQa9Hm4o/lMHCTU9c93j5AL8LC7WQc4NNlkGSgz4DS7EdIufKET286xEF3ftZzO5A
2MJRt2EuiZxZ7Wp58s8Ct3k+0auaRmxQ9kuv5zUGcsz+bE8VP6vjRkGBSiaXJjclfj50qoTRv6G+
nUe1WKGhyeQw2hg+GNjedX/Pza4iBia2MA6blAMOZM+8zNsmVT08dST8LyNSZ/E1JbkpDXja0m8s
KwWB8uX9RH4FMU+UD0cakYrWd3AGSX1NxOVP9sFPANsi4v+ibOm9AtapBuF4OZEBWw/cTo5pea4I
JCGs/nnMJ0M+ks1bmcjOOuiTxiZFtXNr9CCI8ntrxguPw0VLYcXAImZLmFg3owIOq8sHMD/svW4a
XkzoYFDSv/A9yWWYMXTrxC5Pn8fifhRNlvlq8DfEMwHwaLwz8amSvX7idc/6DEPgzKc9pqPNCZ87
ykAYcPsn6N4YC/YN+AdMmCU8wL/Z+IXGBHFS2C03jhxsbwBqrFFDyNVB0oVJXMdzALCVN4d/xtGh
NtQQ7oJHo3UB0lzVb6yzBVKAdWHIrg4fjyBAgt1IIf6JKEIAz0Tf66OlsS+LlFuv90J84wG78ny3
/i8EVK+OnInaVbSgQRCYXgUIfsK6okc7gKGJC+/S4VpBB7myqk4rT879uRySImiI9K8SlJf5oKhb
QCIHfPpP55KjALLziQOkMCB16zN0SCPPeRUrwFFKaX4Jso7/GrsLwwCxxnquo7ODu5JXSX/x6ZnI
WXqrycztw4+GJqx/Taln7I++mHyoeIICjMkxGr0/OOcLcqTGq6zo7uFDYB/aPseQbHfADt0Tqdyb
TiJZ1HwVF3Y7HLROZfuB9PDup612PNmEhF+++LfRtPRVgNLyg0/ddp1jZfGkN05wIf/E31Dc9Pqa
yQ9F1jkp5Z8+9+Vb5TwfE0izUIiFh6tENb8KgdXldf6y9zPmunwFDpr2nyyRsjSIkKd144stDLjr
LwOcG0Ruofths2BVNmuxAH3Cnx7CcL9v7WhhWEHHFwxF/1Tc7stef04KSZiXFVmhiIu3LC0kzbUv
NyJy1k53YniROMbw/XYNhWcFOby2ZQMTbG+cKlMqhlCfktSBolMxmKHhMnCXYsdEo6EDI1yhtcHJ
JfHSF4S/M/X/kszIIB/LFg7fwPpwm4yJZlXd/L3hYywSjjCXY1wlrScoDF0hKHk3Fl2m/0oS94pg
3+CJBicEmUoHRlfgzbVeDzfSoYBBihMYoNcRZpECLX6Numdkp7pHknc+hptpSX7uwZ2/2EOMKU8c
GEaIxhjlNgHsm5tLpcaEH4j0eCX6O1d+LrA//OSH/s/kpsOmObjNTvAkDb5NfoxThlG1A4Uof5CV
lTSaQFmfdSeJ+chRiwJ3TJMljJ8YMvjF3vvlh66G12dGNterdq171Q7SNujKbFFSPI4waXF/aQfn
VJ0oF8nV2nF+Un7o+Tli5d31sjH50CvzVZPDuwWdn+8E0vGEaUKnjkZ9wgdz6aI71hHHeIShc49d
F3SRXbi8gTJ6iAtgapV/x5e85sa008aJwSCflZQCWgV86v5BhwOAWVL7tOZixcVy2LSl1WmMTcX6
ZBwbASZ5O91x7xpaU0C7dPjHeispNAooQgAXzwUmQvOvdxplVka5sMi7V6XAIR0UmprVrG0BRRaH
Gh76yQZ1HolDrvZAvIfO49PLpUouXe8eOg1UahsaoDkIeA5qHtFsVd3NvKB6P/fhL2HF3J+lKhVH
trDUAv/fUQvav+zbnjhqgPJyM/NZqlvWP6UwUrjdzdJffah+5GzTs8LbkdGBV7EP7oZAKv60uL4f
h2CsqI3LfuHRczUqXmXy+0R4CpRv9E/7qxw1HXuvNAUS1FFHG75rxRA2AkExxPicnB0CxrnE++fr
nbaGVEVg0NSXU5PTb5u0QO79xgeWc+/IB7J9YJEbV+fSR15fKLXvTocbabGro9X9cy9jEoiHhf9L
fOqaxff3b9yF6KUByPa7qJ8x7h094Ud9HQ0e69Qa6N8gjgMcPiZebid3Hs0y68IXZTwMmfMdKFan
JBfkX5wZYrBT6pcP4T7HeHilWjgliLy76H5pZ0cwGi8rGKPQ7PN/nt1hFgeQxmtOzh0n0EhiapFw
gkv8AYv8wTmsMYVu+UE6NdypvAK2ZZ1w6rD2xgQifO4s7pH1Gaag/XGfPBZMFMSzqwBW1wyqpxrE
tcepR9RfDr5rWNPMB0oNq/sHlSj3e0as/h1kA6j9OS1fKhE4b9isnOgTN19fZ1Pi+8Vnkm1kXBqx
R7QK2QXWzrCJlHQla2yIFtBK467ZSJVkTKgH7XjklpEWZH7Lj+MB8b1j6L4maZEJXfT4wdOsJ+kP
MpJ8ee6jeZYjwGUjEwItK8ZFAqf/wYLLa/R5VBgMDsD1iV++Johh4ZOrx4+OpmiXZQ79ZSzLwRUC
kAEfeuh3/OV1VSeXS/CSe7l5RnPAY08cX+DpzAFMNtWrYlY7oyBfAp0PMslErzbp+zp529LkqCXt
g+Wk2ZRBGXcI/ZVxYTOTjh6KFwOsLwT11YF2ETegngvuZTfKvHqRIjK5b7GqFDCyyIxvsF6J3llB
eEhvYnFm2gP1Rq+F2igzqTVmOCGcqAglAd2H8lt5iLAc2mGShKqx5LSrUI4ri8bhWOgt9Q4rj9u7
WW9dr3ULIt+BaFpgUDL2ZPm9UjccCa8GUzzblBeJ5Q4COzmOuqjFbW8UjsLqFX+jvvncVUoVKC8R
XUEUFGTwRCuCVeJZCYy/jQji/2l1SGKm5ne4q9Fe0Z9TV8zc4mAPhTqWmS7AmdFGByH+ITE72Wbg
HS4W1XpYwzsO8f44DuudHCfRuFKqArxVDdfLYyFX0WbtNP2qaGPYsF7EwDui9laS4ijH2EbDQu3F
YhNxv/aVchy/VCGD2onWx3iD8/ikARGSYVZfk+ejG20R4vugxVlEYkZsFkHyiqtVmnim+XE8921T
hbMOgPcF9OVzg5OTeKHchPcu36iRzwR1mf4kpcb9vSf23oJXPpL8fMYyISEqM1qrLnopGDuhQyHK
uNJFLTJkZqQL6EgUVQm4AV/rWRRz2dqFGy2lNCSuYzqePjRp/i0kiqkv5i7HMj0faj2wZ6s/F77V
1YmEPjG5xzNGYMwB7iFAppMr+bZrMZnxEPdoX3p21f866JqX6+aLA6wMppaYqumpzvRMT+lRJk3S
UIpOM3/2+g/ERAwy5QX5ZErKtjUokfcNI1D9ZXNE+8rfB0EhDt5N9HOUzYv8lcxyhtNhgYxsOAkn
7CLZmjCXmByS+O358fEJlS+wWUN1LHLqtZIpH2Fc5Ro5at1GnznGNuj10IRMsfZSn5Ek6vnfES/U
dAhA33jaosJ28atri4JCqW34N2gocMSS0KLZ6ZSvm/ktWqgl49sXV0gaeqpGjFN6D04eOzeYDxvH
jH0RAh794A+GPNa8q+TQLXPITFZIJYY7oXcc//4ybV7cPRV38F9Trbp5oS1RQwT1o0QAGa8esWXe
kRnI2Xia3makaSQ3Zhq4Gdl6URWHHFNKz4IJF6jWAc+U2CsJjl1KFsyxvci7GJR21A+Parb987+O
JAmsxUYJA/ms8GzpM62EMx6LcY+x3W6O/HEDKpPjvxz24fCsKledjWKKTZ7pbf4HyzMttuXc0CfJ
AzYF57iTgZWCgL7758pDlO7KR/wF5vpTOhI9OKrIo9tqfJRLP7qB1DbaVhoGcFB8fRA8MRqpBmJa
CF3N4qwi3hd6wcE6ZB1euCPVWVYI0EhxE2w8TASSA0EMEz71w3fNOzYtDuuYWwLm4MOXr3nz0sQp
yZKvCebqlC+OhWr8ClcEymcGDTtqMAEs9WsS+jglXyONkcK5BPFFcirex5Wi/NGV8ZebuFGUz4F9
y9PvIOX8BpY1ewHngf7V8nReibBGeVr00LaBYsQUuQbPO87zVDc1e5YjsfRtvv4m70ERqOPT1Van
yr3TTiPu12mWsevgRKjJpSmBHJ9X7KUS1KykuvqEjIq+ehGfnDbMPsXAljLVhR7xPlTOqW+7NRhM
9DFMtami5PtS1uDATVchQIJ0GmQkbebJFdGPbzgq+Cxsk+pNt7YQZNNEOMYjy3vPFm85qnqCvKOd
sw+SLncsVd6DpcI4hjHfeQ8jFz4I+KQZR/jXxG90D1Q3YYiXYRd/YpDb6Z75Ekood4T/Zz2DSWoI
BHzs07CrWWZCDVOK+qlzy7wgYTOCdU2UTEQXlhA3Cn0tNndGH2PF1FavZRqHTyjq2rbIcAlwohMa
9Didg0ZM04JyY9SUd0DZ0JKBLPOt3jBNLM2JSxRtN+W4KjPc9OqW5cqBofluCaQmTnd06Cv8rLUi
/Qsgeu3ldRlrWwdxifXSp1dJjZkKW2x+U3vmidUJxxdhy5TxSaFuM1ccsYizMwKP+lGRIIrjresi
yattnGOGsD3uE9F3xcVewChkG1UAlHcy2G1CtBC3AUwlHGb1PYa3HOZOq5xozwujMlZg9hzzpQjd
hn4oEmmHha6Gm1f6lA9Bjztkf0rqMLkI3Yu1xJ3gbCmcY0Fr5Ga6PR5Ra1LLGmHJjBFn/J0zajN7
0XxtGYyugTAUsNyTK0nKtmfIN17nNha9mXStY+0V0G0HjY5ih6iqP8O9o3Hxg4AV5ghvvcZifrws
fQoTHCCUaKS78P9W54YPOrJxfvurKpzF0O36pSckqDtXFU9ociy+v7snwi+Nlr/eEl9DSxZKL5+o
wOcSzCs13opCVhrHwSzgRcpXF6q5pUKWUMkTU3h8WLKwgyJ7NvUPR9Yi3AeziSTZ3pcC6cbI3lPH
2bja9WU2ii9q9VsTiHxYVi/VhF3P53FphbeA2U22UQ4OQWEAYlGfnSdwW07SxGXLt76/tiCNF1KQ
Zz0H31oPGSrELcsIxExbXtVM/MeK7owrbe6KpM+07YUs/Wg1/39dywIXe9ZCwKjaY9tFVFXYSkIk
BEnXHpGVX27gM84IhUFsOw1+KotSzr9MDXj7KDR1+pUkv7wNK3zinoS/AFtV52l0q86uMCE2DB6N
JZUKnTTXM/B+1Gxrl0iN7+Ar/C9bWIF77DNcTFwqNf0BjjXfF6PgBPnMGH4ujOrWbASfym2Rryxu
SDibP0WJund/KZQQr5NL9Tm0kH7tTFe1mSIbfEU5RJZpqDSbdmx4oxoeDUYDlaHw+yBKmtC84tjX
I2EuyApCLJFwmy+XpH+Kkc664HoFHMIIAMDG20L01Mo7DhfkMHOF5jcm1D2eQvkm804AZL9G3X88
5glm5xY7VIqB001Ovc1AqdoI04OBXFgJuY83IGo6yNmvrFcPLlAHGf9k9fFRRNO1QRLEffk2Oa6K
C5CpR6aaUAeyjwPc8uYV7C2d1JEcIu+w+1L+lYg2J/X7AZgtudHdv3UzVd7dxF45lf6IaysRMBxD
tl60gOoa1dP9jOpRkCpNxl/x3JMhEYtQZH2PHSk6Hh9eJjytljSE96VwgH8JkWOtjZ0kMXd4t17g
pR40Vgpq6tY8wrRu8xYnBWZHjm4mMLdCz0IuRivmoLjYKq6ohzZ9V0nLv7qGxSebOp2gA2C27qnK
t4KosNJBkBFLgF8riEi7EztodV8zsnYowZFVArgubekcVBYeP1qFzOeF7XiV+nVLL16XXp3yvvxS
WZzasK/HFoJNjZH21G6mQYCUSvP+sHbxQkPhhVotbZB34cNttZn06Mg//GGDLC/DmeeJ2isp3f8X
/o4Bkqdd/tglw2LO+2WaFdYNo/EUN7Y76+likM/0+g3PE52s+5nX0VXYSZQ+qWG7a4Xp+pt0+PZI
CBSdbl8G3/dqjdHmUncyZF0PH3v0X7GgEsR1W5bCnWAheU9SZPQxRMuWrVr/Ix8ayRDArOetXXxm
GdJ4tmf0o2PlKQz/DN4wsAofThQOK5ytznL92RNSpL3hhRDcQRVo1pZuvpZ2Nlg9ppBLXkX6ikFL
APPrV6RvUNb+H4o4tv2nwnXn/WS5I/pO0pJJnhDYBMpJpw/dtapjcXQgtEuOuuWQ+hgWuU56qdh5
RxDmR4HlSJQriXuPEtA7Bfco1n1kvqvX5Z3kY1G2Z7/1FQfluUBp/mcV+97KSRNof8QO5sB2Rn73
CYBI1CTDSn7s1hZVynhsPDqdDPz1S4QvaSOGHYGVs7o/0lbqwCZ345CEbJnwdTZIwGvlMfuXkGXd
Q9i88RG0oGHfO2C9cX1IR8D+58tsPFFRGKgAOTn1+9APCW2CaATOc+r15slpkFIKPecndqEBOsk0
IV/lzNySzmpkuu9eBWJRomDHCB0c0e7BkJ13wVS3KgZ5FzHhPWTbaXAFuT/cTOvSBhduArOOM7JA
FVYzCWhT+LEEhbZ24u1LUl1QO0Sa0XMy7ob6JIh95EvCeJAHkffbTEUzqHDP2x6RStXo0J2NTTiP
fTn3IyhBoP+e8PUYQLQvJV4UPorjcgjzHtnEcOn5KVXnx4YOebCQvINUlFYGjkOJo5f79VEpXqwn
GFEr4fmlDE3sJ7Gpe6ZELoZF/ypYiaP8tGEsjzavdnTgfdXb8UrAIQLYrr/BHWdqwEO+zEbQ7bYv
BdH72rbmSMtouEigcD1JkMXIyLjz+BFYn2aUDfZVHv5PHM9GPGdHOuXFFPKH9PZrCA6gYUTIkd1G
gowfATnGQw6VkTN0ZoKhpLXfUKCdQ+SX90GN9ZYNUUAEQ/aUm0Eykg7OM0eal7TaE7e2q1e7vidR
vrN7Sy1jW9Nc9mzDkBwv263mt369vEuTcN2jw4JjOFcDKWLZXIgu4Ys0fwOqJi0DziDeMCH2wHsE
suf4MKvmTBUg9GZsVaevsYh9PLEFVF/KlSJ7+EIv2gX5kr/jC6G4R3kRKUTSMQRIWCBNO2zlCu3G
SdsMzjlfnRmhVvU/YHWs4Dw/YMwsPK4BRC9Hqjw2O5TmO9IIzYbP8ta/nALncjh7YCiqqc98lbkj
sio1Io3YJB7uvGJeXJZbtC/7Nirkt3mY71gmMame/tNCr+pfrp+P1EhY5YQ/oCttiHcPpVEbDi94
IX6F59OLwb9XkeqXCqQwd52yqjO6ElvouRlzZCkJ0bBxGXjsdJfblf/x6H6tPOLijcSbDVMjlLRE
/aMnSVoZs6Iv+xAtyfn85xvu1VtG0X4nZyALCjVQxWDmTql+e9e3jcmIGwgzAtEmEctgagrWEcDr
RhGy306inDRwIybQlgyK+G2adOvDHMn5mMxDMpZ713XZJZq7KgxBhBSP2WCztSTM+VOukE0jE9r4
WHqp5LqX1l37XqNmW/Hr+3hAHaS3ZnFANwLl/ByZwRQjYbLMeGBXpmc4iqbvPTx2SLw3GnamhEgx
KeDfzvMQs/UM0BNDVwfe+ZgnMyUWF23Bh2Y2f5jZLFkQ+bBw66ceZ/XwHgOQSV1BuKjS6mNlKtQ0
1kxzp1RWoD+jVTwOcygPMqDVjlZOEeRmk4NiVjAGzvHPdi7UKwG9Yiz8ijlQDtfOawIlJbclz0Dq
5GTXUfzdcN2ToJG5XelVffai47H364JPOTZwpLnDJuWRPHfbIPUBUsTFxExnLFg3qR7jxbkLZCTe
LfYe6BkigrLy3Chb9LXQ1AwrzS80YntJBLjfoVFhnUc65ERRbl1y8z8aYcGIX8rcDBtdpBEyETkQ
CU6sDc4RufKoFJxeh4Lcj3R+h3AsmU5TV2ZBSag6Pw9PEO+8aPicj/96hTTFfMGD+St0F7QtDzHQ
ziBeRdxNUCIOEwcXGI0H5n/XtFcC9YK2kPlWm02QU5RRpy513f/Rpo4IFt7ILNGFqbOj9AfurOWh
YW4wfgsljgOV5QEeCI4DZONvrEzHBTsp/+xa2vTXX4VfRKjO3VJZr1ipgcEBwiXnXJJ/zRXCfiE1
5mDDJAfLBavGk44QgxQdUMgmt2czqUyGnBoHXpDtaz9Dahx5NNSsvWifQ0uUFdDU3yiB8i8k7K/x
dP2vnnSJ6+khUSZ1ePb49kEY71dwCKFvolI/uNlowinGtVwiZJBbHTUx+oqHfqT3dNHLhis6RpEU
avDYqnBbE+iiaGAguYAENew6+6gOmRKfSpI8/TWx40rl38Uk6ohX7gofhuEc6w6dmqNWAvDk4pzO
Aqn/TYSSJgiWHEdjQBA8LYtd1amPT7ntbQgsWPSbV2RSvYmtM/CiBSdT1+g3UcJccVpnNZaa096A
/t29rlmEBzPO/6+jDP3UxCzkvJVnY5OtHtsMXZw2Jhp2Jvsmv+GLu/5cc+9ImMh4qOuH8ubZ338W
xv3kNV9BOIXtsmi0r8bbGNbWWh8yxDLmg4lk7wIep0598UbdMezS1SgUPnPVLdITg3rq5yWNKGFD
6LwsgrmXSqOJpBNTtQhlnxZdlxx9pA6rmxYOqZ72g/NY+lXSO0Q3C63nauGHCIVw/qVyDkzknvzD
X3HtchKS7nHzFuWHec/mVkXPGNCdEgwkAUhVTsMeXcf4dhxmGOi2yEmQ5pRwrzT/0tGf0mYpyjF3
vf9EfbxnW7uwFUHaL+FYd0dCngdZYUfvGAwDYT+ZqvnAq94/hqpCbSsOCpR645X+MlMpsU1o2PJd
L1V1MxNla73zDMbpiiGXS3JpWqfcKBwGJOlWyFOqOIydR0q3hSMKBOjcO1yqbKMnoa5oKhVlC59b
GWkbPGTr3HvtnRAsEfxu6pze6lK3d27cVivlZNyhk06x+YuZ9E/wexggGIVK+qsdgkKzhioUvqB8
eZ7RA4k3CxojHcRBapo7a0cBWktfRDFlWoC4m/xPddl+Kw+SZkVFnYF1cxZgQ0XrHN0JZ0/yBQhE
r8t8DGrqEMFmjAfRXgfRW4isvixgqnhUWJzl1dmFsE3wR1E1DdgXlV3/nV9nIi7Tn7h3yrxaobGw
aXdkjOXHbhaEwEi2oI9yC6Sm4ZowuGvGpjE9Re5QsjyQZlsjTv0XDPTpLcqNR6h23wYx31rChRyw
QM7RvEmt9po88CZvuJoLzG5BG4GX2HgiZ24c3NRk7iJzKT7MPK8b0Ia4Sxo9InE2lNqrpcqv9lzX
pTtkHIglrJomRiDhN5rPKGZAAEyiXmzDuBymJpJY9bS0a+dJ2j7FdDFsnadLmCWiy8I0idcVQU0L
mGKG1VnWGZSpt/ONT/rmc7QyhLI+DBgQNsU3kEiUxab6Kno/3QYqGoMpUuyZsDmaBs9TNjXNhKSB
AFmqQREQ2eTh44ifC0YZ3bOF8tJIqKEcdpW5Nxd60z/5XowxunqynF79LfVa/eQePu2VFWbAOWO2
J68eRYch6rlfvlfOmAhXhdYEjzV8Xr0uRS2H+zcirSHJYMH3DLke6PJSaW7BdpkcrEx1HoVvvBfg
hOaDXosUlS1FgksRpJ9Y5VIL5syBXYp/qebcjZw7nN2IkLjAnj4M8lcUz314dUzGxOZwM1p8EZ/e
n53ovS38/pryOhS9tZWGE4CzbPdq0BRpgoPyOwvZfMYaEdRsCqL+na2/rYyFVkUAIvYaDYVlXHwo
jXxLjv6ckRYizujhCrdSwsaUXScn4BRJg+CSQP5tsY2cnwjs6UKLdW2crqk5Q7jGpsUCktLh/rEm
5rJcTxZrYO8SzNnLvf3Uaizf7nHceyZYof2yOiLO6P35qFkWW8rYlXusDrazi8iy0HxJw3HkbloI
dacUFgY3bUXYRy4jSOJPXlLK6pfHTHVnKtZop1e/ZkN6Uza15YwjyBRUPN8EiF5HaJ/6Qx/b1T8+
2Rv6UGBLXGAGE/A+x1P1/5afxTaHN2C94XfS+vdVFFUuF4AXRY/KELOZHXwCYDu7EvHNyZa2lxhW
rtd3uEZy7jq1cRXrYG2UWEdNWWrmjqt6fRm5vVzoDnze8L6k2FHuIyREc7dDGxdT9EZ3KwBl9yVL
Y2mLeh7//TJC/zMOOcq4zZ98jj3JW5suC2s8oL5xMgsawaCruoQI2R50dXtFOmseDu6MNrRr/5NX
tXt9aRqVzuTmTBWl/xrz45rSu9Jp4BS6wFsVwBgy8iEXAPkp1IHNO0eiWXpqYJ/DhYmgJyYD87PL
qZL//qDFbBabaoQacDQ44RiE3yR3sqR9r09zF7AJPbWlRzAg164gweyS1e6z8CnkAc7ssWdeHjov
kJ0QMpd6CGPV9o9w4ei5a3VAg0T5SPJI2Pr0tb+R8mFlSY8HS64+Im6gTkgrs5WHJVCqPP4zR1Vv
6yz0PklNkt4SfaugcAEDgZ2znl7XW+hbGaxlJcUQbeYCSv5uu8NHgom54G1Gu5GIjRrPEohK6ys+
MFRjBG0TJhOWGCnFG1gLGTZwRLZhbHFRwBIkNl7x2M/5QkPZXge1AHsdB7ijlBO/FXACUWCB0q74
V0hawkXKq9mx6fOGAbipzBuNBu8SkhX6RkpfmHH9b1u5+B16qrF4PStgbdWrhaLabLczwUgVzDBj
Is/0GanetLSy98RVyGpz7CFfpaNs4i2a6YmgYFimunfMyov7BbxrdTox+MI+1oX5o3VmVfBB91KM
Cml/ZbLiYP88pZKmBld5DQX8dup2Rq7mbQFkXwUdkC29cAfaUaY429hhTU3c+Ynu9QyMzB0vhUJ6
Qfbwz61qpNI707e8krWc+2Rs9PMROleUDXjbO06F++h5EFtN+Qxrm1N0zFaqpXDMPXSmt9LOcOxZ
vkAWSqUvIBPlZv6IUKXLe8ix4S0v4r6xzwD16hk23g8n+Ik19zZfAxH0IJj/PIC4HIp2djyXAjrK
ROfxk326CYgvjGsy/F2H7YUOVDIH5oWXEH8ePCdXmzC+qCjanKHqWEyETHU+uUXloDgfH1RvNF21
mgIHxyxX0bqNW8II5msjLcvnZlJuLCVHBp2I0K6MWNx+b2ZCuyDnjwtFUw63QbOW2MI7n40kMfSa
vdPCSUqIJ+D2IksHUnFaMFTG6RB4C+5JROaQ0aQuudwavNO8vskY6XDpvSw4SmByxu6uEtEKso1n
AfPuE0K46lMMmvoKdtxhxjagEjHRKA8OJvGZcBcAtgAU5UTth/xNcKJ4h8NREN4a4tS65g64uhy7
vwfNR6+15SfcH6NPmFkb9GWl2891sTDfEHuUusSmeT2zUyA7a6hyMoZs1sL8m9lOetXn8zshohbY
u+CVrEU9r0HNSh45x4yjd1xzpUw8bUgZ80npnyIhtQUxZPNjnWPkS4WbTyh7Hy9HOVBMDxSMl0v5
3C7/5OP8pw0S84ky+aPI7mBgs3uetuB91tBcCW7/p794ayp8vExtpCt/c31OfzH4dS4H+hnIaahI
sqcGw6mNxPxaYwbD2WjOwmswWpB9UwqJOlMygmArJtDJCwS93yc7vjUjI5qUhes6/oSiZeU4jDUa
G/76u1GsLHy97gLVCJG8coBDOwrymsW7UxGklQtN39Kz3VjfpVvE1XwNPxfJwRKuGc4bjBO6Q2x7
n+UdOSX2DSd8wQ2HT9O58dMI/TzlVj+YpmpJGuNeb5Q+d/RrepB3u3/mIgsVvdsJ0ksDrIWxf7a4
acc4HudJS82EICKnGHEB2iw6PvmeaCCO2CXAUxhDTDsW+WOb9x7xRQJQtL/UiaH6vOVdXxo30Vum
85QdUX0+/Gnog5v2dTh+V54gIbD36vzd+huJJz8NjDChmtWn8wHpSCfPn/t1JXwUCx+jCe6eEhFp
mRv4IpgXsWUNCPLvdPLTvXvd9whbC/N5ae4Wqxv0mE/uzt1W03lm88JAJ+n7y9iMo28aYoOAA1IU
uRfQq8o3g2EyMQN0TJ/dR0JQ5PKl+aKCO1by1O2ssqHnuvGoTzwFg/OxM9DEHIwGZWTpbZS8BA3R
VbPzwgWx8BlAp+6h+wwsqxywWSXHh4Z38+pEZPcf42FlzggnrowG7XezMZA+/+YzPz9soMr7V/B+
iKSsS5YHsKf3MEVO5S3fuli3WrOMk2728qfJFitiIt9hm6us0s9VBzfSvJ3xhQuzPd3Hga3zLaBw
mcgU+MdghXqYOJOD4VRbZMlLaxDCV8rLmsdsAkzPsR3e6AmNsr3gjoRsEqZNiRkK+dodD3s3jSLe
noXwy/ptxWu3O1o+3oASQ84vfW0+hW5H27W624i2q+cd0Z2tE8dPKQSVfF3cesvDZb8HBPQeQCO6
uPqZj/6fi2E6kJFupWFH+KwxktFQQ5LWqNi1UCJb23H+PyqnRaaIwbfUKXhuX1v8o2mSeZuk8+Sd
XOukAzcmYhOuTbqPVFkFQvl2lZCMVdx1LTm+7GoZ5J8oKw57M19Ht1SKUsT9UxASVroe2oRCQIxq
kq+VanHS8bMN1GRgtzO6+9XU/rsBeeb8Y76E5RmTAypF9/Q72KDB0YWu/ITcAfYCB8kGBGm70Gto
XiaI+w3ufZMYPVD+XSEW4+uKrzD8/zcxXFlMcdScVvGxFhtAQRkCmOmqJ02wvTE1h9HsnGzMqVP5
OpAAv9TscdtK9US8s9HCBNXEvRUIUjHMG1MsXE/Zl2yBldco61r7eArSGyEZ1Vp7FGGXwG0rDnXF
Q5xjUnzMMRa8r7tTMGYfAi3UtLDbHwGCFIIU9Uf0IpH9xvJYHfTuja6b+T4O2A7j9w+p0wd0hLE4
ja1irVPukPse78DZULzoFFxn3h6OPAX9OkXO/423VHrfdW9LjiaMdB789SfpT6/weDcGNWECzK8c
KOkS2nfzsir7ytf/9QmXIW9E8Ss6M/cVxelGk3PPOYoKBh8g7sNULvhguJ9Grln9CJT0j7tlsItX
mGCQvj9AZLgiF8zrMnOba/1gHWMw6WSZYlbOKDckPLt1YJx8Aon4mQA9aAKafbXcR/r6zKHCDOKd
SoXhxM94RQ2CmO0icQixVkZxbDMqYGF84KjRdGHgCHYwB6B9zfkpmh/hJsjjdZeC7b+YxzFzxuy8
OPQZ+VvgptTX9DkItNPQQHhiJvuAco1Yi1rh9fOfeE0763c1nsAnj4QhJP3vn2iZkG9Xh3xayBME
Vw/JDRfn2sin6VqaKeIpIDBtVlRsK2k9yrcGnrkXZIn+8dbIUKMVnxbREaMsTJ5wkp/r756zlKmv
2aZrBzMNrv5Gb6WUv9XheeUWAbi3gM2JGU9bH+cv3hMW0i7Q0EUudO3hkR98CorjANae4vavG6aN
ifaDqxVadTClMDBFCciPc8oY2KFEcq7Ayoo+DAKtO2gS50YNtzsq2mekvY03eZZGfanHXX+DZjfK
du76ibXHZ5ErmqTZzuculDOPZ3Lac17NmLarWTwtH/rcbNYcybN64k0oMkxQliMqEeG2bryvDxi7
m2DFgFJIco44bEZfLTX4cdhbfWrnqz/ZWmz55iHnmLDXYsaLuStpGekpb/AUE3G5JffQbo7lBTx7
UGxR546GvY66bvIoNvX/v5xLlczyFnumZvX1sYWNBxX7QvcluwskGn7jiruJE3pME0G7ESVLqsy9
DQoQVdaUiP1ISKXjc4ZP8TwpKiIcWGrcxeepomPgkcblzNBuVhxHF8GziKXPWFZcMBFJnsB3gvSq
W5hjfqk50gsUx72GQj51PYF2pHzOmRXJ9Yd3pGPyiMzYmsHX+utkqNRoXXNYfVE8HVEdSgpCwp5g
xslDiGvKKtcoe1e0vvHe5WR+986Y0oby7GRnwhR64Ag4vZaaog29coeqfmXuU3jXccwBP6hFIOMA
MaAkgOqdAIUR/jYxW5jaRhULQi2wXaXxbg0SVvfFCfacOsWZAMCWmC1+dNxmL6QQoClr7XCzYbZH
pn02OuXzK1379LQsCp3qYyqDCqZTWHyyxWkqDsevm4eyIUUu1lNBStydOTvM9cZyfNDhJ/th3/Iq
OlagBXzW+UTCju0LQVVD5RgxPds0VOHRIzHbgrgZWYDmRQ3PlBTv70O4Fm3pOh/aShOelt8nNhQZ
iXTQomvjOD1sLtncznyGjHB+9ws/d2yr2O2iyguS5h8yxws7O20htV/m9NzdBUxOL6KMkVbUlGFK
vgbeIska+bqrajTFnlDPCpRYmm8RpJv1mEQ6HYjNu4RpE26kpuGaB9z0NrkkT8Qn3RuA5HUNJX3F
3v43gieEV7XUc84RZcbYEw8FEgcAqgrw19MID8rsGO7oBrbimS34NYyo7KCY8P+ms00vl/xxu8E6
9Vncp7Tf3lVd0CeQLFiXWe3MZ+893ooyMYYrgYKhvQzSoJ+D8t9i66apC4zEAhNOT8yTinJuVDzc
XYfajvNol+1t9UTIuk8gmh8G6tB9PuuEckQVzC29a3HW+MNRuyyy3wNP/JD7AdUHhaQc6tXKeAvz
hRcTdv0tJYhsR/8ug/5kVZIvu1T7JMydO900IYFAhNS15x5amEg62kKK4aUlQpZVR5OxOV/L1FZ2
IdeMmq3nb2j9fPUORoy22b3IFP39E3mSXlsFSIgJkcD30T5XIdHcoOk6EfQ7uLNf8PXmOe2JrAj1
rhLyNANoz7ITgHzaY3tq4uVeByvxUxe7nfW208axPgJiSiBYFZGzxtJCmpAbTsPvFzU2gCgIjZeH
2w6NOreYzjH4Cr4iPYM/5VdlrC1PXdQ9t4jtUA7cvGctOgvR39QxWBn9c0ETA9rWkIt53cdZfNnQ
z6pXydHvYB74zelWd6lf9srTe4LPCoC5PnKVQPgTH5+I2Ebz3PtghcbZMhIoTXiT6FJfihEMnwNH
nrc5ijc/SofJbNnbdz0RP9hsLPqBttlEccp7MqYgJR1CJMo8xFuVNYF8YI0sjY1HQLQ7Pz7Npv4P
o+gfy36YH0GxbqBBkYutKujL62CeGj5Dk9jnKO2uP7eyJeWENuNKOJG7sCe9ZOUjw6FqXTTzuX/b
ngdLBBYQhuxrrSBE52ogOxuVnTANpUpfIKeyJLXHIXLOwQE4qmzhtVg2WvcRhTfUsoaf3srs9mGd
pdJ4W4r7+OZRdjZMEzrdf0HT0l0cC34Ass7zKvlDeLzNQ8KEjAk7tCMmeKyQI95XGiJBCtbLIFVH
YkxzrOQyfCXACYfkTwNFX7OXOCc2JEHQyaPy+ZZJtWuSTkGwgYVDIougN6bTXRWj83/wGMDBGoiZ
eVIEuCYOyc9/1yA6kl0Rxm6LDEbO9p23nFS5cKYdUjbo1W9Xus4l+VSL1QkzfjQeBcohypLqEL8E
YHl2F8TO4OnRSzNUmGRpj4E41XJEjcCHls4Veg2TPntRPIIXeo4ZCkDJqD3Q/Ypjy0lkm2Bbeq6p
qDv1EuKCqfnSpx5Qzkd1Fn97lThvQDg5NFdFhU3iKV5Qmcl+dZqPVXWegfzGFtIVKt7PNLQN8EBp
wt63TWOPo5d+jpuo8aNYCYdB9tSM2YtbzWTI/UrHAXMAyCLL6RIzE9BgaaW14vlCzgDkfxUSlwcD
9XWjd51wWHFFNZ+N4iOcLwKSUjARsh18mY88E6itnbwyYx54HYK1PVy81T90nSR1wSTmAuamIny+
eqkJUFphtivvJgMxtYILKBhtG5HRAOLtlZ9btC5lo4PO/v0kOSA9oal0MXezTy0FzJWSB8uExl1v
A12rVLTPZAGRe/hQd4Glty35W+ngx++Cm4SbKuCeizb0DBCCACSf/W0hQIEVDnSeRgjR8iFCkkQF
r2dRrCRGZ2rXuvrA5JVX7+Wt5ZaY2zkCDPqgcQtH41/3tA1owNVcQqqjQUAVz+salNbwgDDp5eor
RyP5Cd++7VOSw6beIZMml7A82usCaf5Yf+gB3yJ7o0g1lw5hqmApz5Bhm+UydXuHeYZ3A5eqatlT
jdYM7sKhcRlI7m1jsA10l/QYH19J4Rvi8q4l9vPp4TSZiufU0QbhyUaHxgfG0erShTntUnsDZ7A4
CoVliCCgPFBvLHAKQNaQuLJOLxQsvD2VPRoXcFqOu7PDRwQp+n6TVHMi+pPWn0dm2pAJoYZeDNVo
oxRiVKjlRbhzkpqUWoEhN9iOhWEfjN5RhHjBg91wcEMCTTylU7SVIy0CBCQ14FVMChguWlM/e6ys
TxHKH8faA9jnakRhYPEbUQBTZgI+mppoN3qLg+YMSQxJUHR00+P0NLKCoidXk2LjoPJkDjO9d52r
zkQN6b1CPgJEMrMT3SbE+hgMK+As1Ug07+w3zGysYCO6bPRaTEIYbi/5rScQ4lhH56tKkflYE0J4
RJWjlTO79pibLrbI+qjWOZ4OXVg86vJq7Ns7hi3BE4wFSzVqxd1Qr5ZlPOD3XGXd6bvijfqVaU8H
BTYEWJI6Bk9MCIbtqubtRxKvO5NOf/dl+dx33o4RnrcSAaofKVP2v2J6iQemGeY6pWl2/P8O0YKi
L5Qad3sAH4tNQMSsESz6Yqruwb/w1iQ30VQMjAAaXKghuTwUoNMMYjF0wAonBSROAepOCW/Gf0Vf
Zhx/a7HHjHGyZ1HLp/jUAULeVnWS2vmpPzUUfR+1jFDfd7jBBLyGO6dtzWjgBIKbnYRrks2UzyME
Ur2UwVD9JPL7fL+wpmfhD9WSEbuJmARcRIJfCKagDP+x8LZfXTT7vMLQllwUQmd7C3pyKXgv2tOO
5pgN28AFQXa0olYA9aMilyBpuSSwdNJv1q8YNVS4d+2+9i8PH1XSlUOEd3ed+v7nV9krUij2oFIx
LrgsFVFn++RZuWUqLLmyP0K6lkgoChjvT/1yXIioavMblBJ3WezUoB/+X3qmE8WlG67iGIgIXCzz
/8kYRV/tryolPUzTAKHeZ5YcFAzQUdRSGpLG5X0hqch7TakVJZQXS8Foaf4XX6kZDnQmyZOaYa5I
Zcs46gQEkTCZUTMFI81EN9BfJbYYA9Xf7ABfOh1fnsSar2fT6F/U17FA3mspOjNzw3tWXfpEmtIv
NZgXocJCbZ5dIhqxVdyDv2KQ8IBhRayAL/rQ830scLo4sAsk3MpcSVUnZadKt/ynpkSUlb003iKL
h/KmilvFMxJv/ML8potK9FX/9fMScoE2wGF6wTAn+LIr43LuxMtNi7815I/5KC1zEdPWWEtNm7UY
bDxakqmLYOmNHtky7iPmlGXTfYwtRbO7RMxqZFpmgVDDZKEyUSCk8m6qkeD/aQM764LKKNJUaI8D
8/GSqMuEjTChis3CdBe9opw1C8FzcbzB+IDAuQOHV7FWNSwP6UUXMSgnEAwpCKSwqreiRK5HPu6Y
7BM1yCFs+cmXeLADnFYU2Sc9VP3CGHwnHniUdA6RHVNPH/FT/5LVOKRJk7YQlABd7naDF/sRlXom
fWTfBiKE6Ht4Re9YI4o9qy4q8gn/+rbxA4VSKDbbBYr0STl4/5nJq3InX/Ebf5/N7wZaVKdn068a
+VXYoJZOfzuUk8fmombOEaiIX9XK19xM5TTETqWtr4Xg+fXIXRF7ceJCocU4bBFbgdsCVC23/pUl
dW+nGDoZX7nx7otTXZRVfmxLd4Eq1u9a7VYhgLQw6Yg06mNgkJTM4DpUc4gbEF4jl/Xhls+N2mZM
asy1ARwsh1mm6yvh7DcByEKbcYADunQjyLu7hBWdycsEqNVL/arGyXx8KvQANgfDAwiDBLZAyOEp
MmOQwvcLoR4WQ6qYat5ygqNXVFcFtPskpppz2A940xsDb03fdKTYRUilodcv0I0mEOTa8ldrJR5c
UBr+TVXNufQxwvce46AMXIHWDw063t1w1XEhvmd+hK4tFZtM/Xjtd93+20PcpyYGLaYKUWqeagDl
tKIqQ0W8TxKT7G/uECWnCzWrnayQ2tRc3eX1l2SsUNNM3pZNlpKgnolh/2aRNxwHk3S8tSKDJcQf
6IqEw2dTRlEno7jcYx79lcmuSWMFKJSn6qRsEGs/FYFgScMaiSAxB5xsOaRWUZoXQg96J4acqmSA
+z48SmvbIjQTxGNaPusbLv878dfyHQYTv6JKnnNofVQlze4WjJfsLOxWMud0VtGhhSrUwG94j43K
VIubD/c6D/pf+NwlWnpJugdnjlIHz6eu5vDYtrfKvBjLHuLmvxm4rPRM8We62o6Vgcd3dCLyjdH9
Fwe0tavWjIgfOHkGfsQUbwYOYS6TyRexgakeYL74BDg49fZEZdrvl2yqKNLzuYrhuWMBK9VlqkoL
tADpSToNx4fdmKsdeVufeqX9bzg0uuevMLpl8BHDP28w3P7cJ41mt2mXKCvvLjFVxixd9Qq5lGu6
bqZYOVk6xZn3Jr+HyeLNf8PFwiMNvisTEjm5ov1vyIUSWiVcBQeY7Ka9oIXeKz2oC0+LrY5Oih3S
0QYMGVE7rqNHbHfFIZxA23RayUnCw4EOUr6S3e5Bkb/LSuJI+sySr6+JN2ctXGu0HAGy37qxTQDj
pjTzazZJqKDnvMVpSNdCBQDNRmXpuP7IXZDPO5W8ABjkPh+oc/ZC7YtreE60SV5bijWOjJHwU4mC
1PNJn91cNclmWOVnLSekOdFXWDIMvpsuHEwc2KThIBGpoUhI9BQ5eCgvt8zygh25JQmRFlcD5HF6
QA/EP1v3s8LhKnIHixL4adG/wT8YJWuaunaYCUrsM5+JdZTzr4jvouKW64LVobbC5ctgw5i6HTqv
l7EikDWc223WdkgLbhEXOP/4yxUwFeetQB7mPe9rAxQxhfmeJsTcxSL95HA+6g+1Esn34I0wloBV
hX+Xj/06Y58IU4DavGy4snqr3k6hYPH/UYALv6KTLGx38175DiGCVls5eUHL47+LwV9G7OH06GgD
6f/xSMU+CyLHxWDZVV4HUj6jkXYcZssAOb2Co19GpoJmClUlC+xsHU0TE6gvK1BaDR2YnGzGfL3k
/58dGXB/a6nNFmPiHXk7ILrtVMok1B6fnhDVF664z4sbuIeDfemzXhRuTVLIDlprapJ/2dfQFJwC
H8y96J7hBYZisIy5azzT9FqhruteKd1qVBpwNz3zDLgzEOd09MAURUKeIK/5O7c1LyzTM23Isndm
9h45R+Min6sPO1n+syJ9VieFxfnkZm0B8IluLlC3CW/iaM2NZJ3YBPfs3/uI8PHmT5G6ohZH7pH/
0jiRMp55FRy4O1UvdYHNpRa557VIPTipIZT2klBGhnxAOJMJKC/eKoUvDFcLvJXlqom+dnk3pMK1
I/fxEPxqlLiGB16rFl9Ypu8rMVXz3RIsYpDp/3gDbm3u36WUYeF8xRONEn9wTQfg6iYpuvPy5NRM
NjZTemWu4MM0ihe3fBUSzn09o+nhcAjwetS7sixtrShbXg09WTrYlHxnpjsmqRawN/trtFSxpBQu
6QJRVxkdoJCenAm4UnACLX5tbHjo9Ut5bMoZFBF0YO9qiaxj0kf9vM4QKJMtVIJemC/KdLhMQmfT
XjXVDN6xAzwmbd0X/c3CPwZINywTgcP5zxE5II7DYBFNI0B0WtT/pGqcEHmAA3r+OqIdhWdn0wad
sGHc7FqGonjnsRMK1rFrbM4ks4ihWAqYk73i+updqPqac3vpQ0Yuh3be72X5HGtbhiP8mwy69oGS
SH0sttmph0bpz5pMeEfRqeUO36Be2D6f0u5FfkucvBTm/ypZqYz2SrOljkpv4E6guLhJXAG+AWMP
zhER32XyhawqmR89spk4rI8Checu0nIU4JuSJt/KBlcGqJ/FhKda8TyirNOeXaVkBZaRmaQtNjNZ
v14GCdhDYPVZmmhvOvpB5Ix7AQTVnSED2amZynOiVzzRK1sSEnQIkhDum/tG71vDTZ6hxD/wOo1X
eV3B8Ku7oaREGClm1bd8kkNX90Qw9geiUfziVjWdF9yvO4eM10IHcEQvhi9sfU2QWEzfyc40pw/U
PEVcf8hhL5Hnm/43orzEZFufwtWepmC0RVNZEA6V6za+0mzv6mabjiJpcxvvIrPXwiPOfrIzM2Ey
DzmG/rvNR+E+3MRT18jtaGiE3GFx1Va0z9/9lLBZp1wpdaP4GHWS7f3P9yw57WD9WOsQqdTisgQj
+IIAXbcTrx2ExpgvSkPdKkmK12PcGPQeEkvS5/NSU+s+t1+95Q89uS/zgf5rKaeyEkRuTL8F/wt0
ogD5+YYoaDrqCiKugkAXFOvzl8c+pcha7T/bnw7fzhbTNSAssqcyyVOTIKazFf3uwHQ+VJeszhgp
0KNk/X5NCDgFzs7X+z2afMcsnyvFrYslNmU9TfOaxOP+4qbB4hhWu54UFsvwok4HMXVczoyXY0/i
VKDmWuSuMMqJI5v9JtFErEAtgBCp3fBhsHSy1eojy6q2LpO+2xyk1SmQxTOSaP7qzqo6MrMHn2QR
uKbIBUJfLjF4UPI7lNf3nlhU/N6FtNlEUkMjZYMVOqAF09VueBZ8fMr/wda2lFE7l6+dCh/y0rpL
ETpzUiQgS3z5rkq2xTN7oW2rlWOK/0OrgT4QNMh4oaFplB0zAjB9cr5n8SCv3He2WfN+1zcPBBNl
jgPm32pMxE8lHG2CeHT3MH2prmJX5H+HzxkDMpupSOzCdpy1GkoHyE8mIOxrPqXD78wrJdMHnQMb
v/r7G3ONiAIJPDv6P2zYl6TPqzYHl2zgOALkWC3OCrHIVK0Vw0jz9q0i2ARmr3i5XsdjN3V27BLr
gT0XUWbidLP8+flTeiEStv4O2i2lV2Og1z7nmtuVfoUSzFCkUWGiX7Vd+xZ3h1fknHGOXrOe6P0E
euo6Ge5Xke2cXiDXM9caIaLoMgRF6+JJ50nb85wfy07adyG+xSnCHeVd7MCHV+gwRaYujKMB9B2P
sH/tJLpqYwNDmA3cCClFeqqaE+uIOJjrcoStF+AeG0FD/1Z+ljedj9b66zwQU7/Gcj041i08uOhW
uEaEACma7SBZI4zqLD2rnnofX3zrINKVgXv6YiuE0T6EQUOxX7t7vitBvCMO6V1KAHaJgitckW5i
HGTh2XTvjqFlh1VfKf2hSd5mrg2PDLWDR5jbEEJzODbrgsMdhI6C9GDPm3aPh9vW85F5dR7OZQaX
0KNsE3T9QDXxW2G+b6yKsPmrB6Teh/+0YMGelZpWLfDPXY/A93gaXT2PLBwQ6m1Tcpc1BfiqkSIh
1xcD2zfojTvu5+5gXk5JzdWZg+QuLulkcBKlgPZv/ACCOhizlp9giu494pCIQHQ5bH5ox5z5OSLO
YE+adb1UVVCR/RRspd/cMSQZpBcQ3V2+oNoi+y5p2LeTalW0/FwIxFnbvm5ndzAuuUEbrJjMgicJ
kQgpvIhbJSVrKY8cRZivGHYf0aWwph6x+oZhjTkuaTzJlx/CGVBsXyRQRE/KLxGPrNNmh4ihI1a/
awE0v0LHAgjOkPPCVjJFE73hyPvJodd4CzG69eM0+0bc5bKmDCfDGCebVzG9I56CXFtOUWnFOxJ0
+Z4/bAW045h7tGgdy/cMEXOuE2BCqmRvHTjUC0SdK+wEGEpXeBWTQ31q8jPirYFkhF6hMB0GRQJn
Ogf67DVvLD9pRubumqqn0gtJZZ2h+kiyJXVOADNj5AIrwPUlA0Lxi3+Ce48BJewlA/XtCZ9d6Jhq
Ved6M3cprqJRdv+SeCovYz9hUShVVEhtBWBqjFV7l+ykclzwFquOTqY3AU5HWIL8OcJFx1Ic282T
DoI8WluDrDvycYSiMOso4U2XtMVu6J28OxAXPtSowWAENdWpX8n+eMjjE9dkxWGM+NLf1tYEHqj0
b4ChYTWzVZt9bvvMxpqFQl3mIRg0klMxA1OvK6BWpwtn4/EumUNe772mZhzFk6ywGFYYbz3rWFoQ
ACIw0lyF6/uvUkBOkJ2s6iM3n+1f7xKYM8YW+FLrpkhXX8PAIw9MQTiKoRn1jEaH9xuLdXOpUn/c
Wq5EoaFkvomxv2UqP3cIn5dnCb7Bo1GZynkusIar4Ti6Ww4iSfRrg9A2qnFVBagsI3EVJ9stttSa
z0lV5PCdqB6C5XI3tpok8apHPBF2U/XStV2n6aCmU6E4bVQjrJnQczNv1IOyrVq1fqvd0XC4phw7
NUBnkVjUf34ze2ZoxKs5qfwkZAHoqloTBzfDHgBaqqvNzpdrQoV7kwEDCGx0s6GodK03FzGkiYFu
MzUPNLvkkHRnS8vNMrHb2kqZfwa3wdUK9qP2x8aQ0YUg5ld/zQscS1w2i0ocSlObo1SkuvrsIRqU
ULPAQY4gkak1gkNz3DHZqcl9rBCjd6y9Tyhmil3IzoOOiWkxftBzIwbPmafwJx45WZn0Gf9QmI9X
e2GMoy2aMtqyTL4lsGVMbiLfsf2DmEvHcYQ9g1M7n6OgeUE2+cOvUZWmn9tMmHkkuTvVqlQjIiK+
Iz+amPiXxDRmDMZpNyOo/KUq0eWMJNcDHJbKvTJf5ydY5kPImsLiYabFEoYWNNP3OfiocuAVec9b
pWurSpSNq3FIu/E+0kW826AAqsCYysV/pUcuhVXavKZYn770gdFwdUhDBFQfvpPvRmi7kb2byATH
aFloJ6EIJDNdk84UPzEo+eeBNSX35HNLUgMJ6hfH1CklSA1uD1VE6wjXI/4eFL69tBtAopBV8w0L
vNtva4N+9F1Sths49Yc9lehNIzkWRL5MaPOVH0Sf2UaFWBRyf5EwXlm9aCPARWbJe2oUObAJdx2M
7NPmrF+G1gzcdIq2MijrOHl5FMJT0+aV1FiMdj4rP7ZTqU8ElPsjBKOYXj1SLQ2jbLMG4PV0OWPI
e2ZrNTIXMI5yyfRxjD/X7JSW9EFwfjsRl2RccS8ioSfKyl7ENM46x1UBQ/srGzc9AmrW63Kx9eX6
DH7Q91NHg5Y1SAZQbQ6FYeDPKQXnUeyjXQleNNy+SNeyEax95EKPNI4DPZVElnO40eVjRVJW17sN
itAj9f7G1NUWFA6jY1EgClClIdtLKzz8pI6n2+zSJzeTwdNPSFvNMBGTRgDwmzBmwm9QkClNQSSi
7HiIP+kQyh5mUqssHQb6zHz+85mPYdly7beVqOUDFb+WLTtJNp5l2PHm4FbOM01q0hQrbFTraHAh
fYRphkQZQLFgjLGTKwqwXUuFKbI0bthNvD5edQBIJNLVrj60BiEFfWoRr3o3hFAeuu7RXYNZ8xks
PE6YSuYLD2SRerAGyxhsND0yKzdsgeZRs0bZXhGW4kWHrKr6U7IDNbUQ47Y7uHq1T/T0Zr/GiDlz
WOSUf78w81xyi/35H175Q3MA6Y0BorsXOH/qN5ohtaw05GAd8mH79cnqGHfdTVl8yndIugBe3Jqy
I+OsgqM5CDea70CMW2G3tzrlO0fNzI4gz3jWli94EzE2Pqk223i0kRMWN6MW47ed+RivoY2ftsut
O3CN0klMF57KPruf973oknkT52pRER1JNWf+13UlMgf4ssgH4W0cLQzvpW4+syimi0YbmruhPYSN
RClMWn+4rdmWF49uBwAUxx1FgORTMuoHhJ5wgGglJzByK805yEJN1FT11cHgTBy92i653BPQHdvV
FTY3S8RGCaiiPXOZ6rwSqNqWmYwH28yvC6GHF7kMn+0tm8T/G9RBjeJuOT1qGntRxqM0YBv0Id12
/oJpcboSj+h7O+vw0NAIDFHUgVHLKpjn5WM1mFFj8YpskGj60lmugmBgg5pWhWBGmoOGEhc+mSgQ
fY0u/mb0El4HhVuoQthvMlmSeGYXD1vMT5Myko/vtE4/46E3wafXjN6/QvfwaxXPH8MzzhmrePYH
nsvbZT74gshNq+qET9grKqN6GvWon1uTx5lW5WSbO8iW1ODJyGCZazC01cp9tlwKiwa5s0xQttlA
aPOFqb0CGnE00eYEN9tkioIVCHq3NKE4oysTuVZwoEgEIUEDnfurXhzfxxiQE7ndomlUrLE7T/jF
X9IQrh3rBzauB/C4wd4FFw9vXZ9vcMY+LfGNyI0NPe1YSp2Xyjoku5/QAAMvxDjRAeQGOxHPG/gr
Mo1TcT4uEr8AwdjBI36ijXFef5QLHzp0eLRqypQgjYhXZD+LeOLFgN2AXMbs8pXbmWl2/Fn6jUAY
k8ggCNOlqp59j7QhbNA7+MIULSbRIekX1jyBZP0QWXuwdx/NHnOVMA7Vu7WJ6KGeBydI85uQ8qvF
rZXAJfixO3nZ5YAIOLZ6VJuAICUu9fnztf4eGj5Gmj8Qm3bcweQAK12x2+kdPq0ZE+scpjPHs5WA
Mp2LDZZyjUEEO0M6H7a6THB4F+b0xqgEO8mBIEaQ7Ql3qAhe7OdEy2Og1YG0aKWn6c6f1B+X+JoR
dL1lPBWJbVAvX5rAkdnAls0nOMfrgYwb1gXytR6Nb29vmLrk7NODMRRT5pYQaLGsrdDvW0uU7fVr
wQsOCjTr8FzFg+AX+maBUwKJmRJZpP4zVtp7VCYfbVV5lfUAFQw+JrEVGNiEbOtF3dAIQlu2395Y
j7Il0yAmw8KLctyfAHu5LotHYObQHfeULKidaPGpTAwpgXf/6T+duDRf2HmArOfILzGt8+kLStNE
ydLXziIfoi4a7iN7n8roiwOdzXoEJaIDj87wRiLf1jbZj4H0T0xyMIZ6nq1lxQgRFYEvyKycK6Kv
+/F1BjeNrVOH4Xlz4uy7CHX8zycINoaEkySLKIfo/tfOk5j+BHBTcGhwDiExns3+cRyCTf4VJRDl
VFE2r6FbVMMrCDRrDgCGHNkhnZ+grI/4vYTWsuQ+V4TGwqZTqwqQDoaAQdyvwDVPfk7CaXRCRD39
e/WFYLsSF/FdkxgtcZTzz+yfCW5rhYBkVndOEOBJQcOTf+GcvRMK8NamKiwjbqk0RlZYzgZWuwm8
ttkLxhm+0UoF+fJfLyembnf6HDHUmIq7eO+vApcQa1/APX3gj6gdwsPkZl/5bUvLOyVTo9KCuwWj
jBMu3nUQAjOXEXDZxOnc1i3p6LmhiVxNIND/t8DNM2smYPr1C/i5bAR27BsU6+6teOmKGmcfUplr
6y2WTajWvgC7iw54sYBQXkfVw9w4LjJ0Sv9uJdvhNcz2vp3A9vQf1u9D8D3A5KBnXfj4BMNEUWJw
ZrOH2ZyoASbhJP3YWY1oxglpxnbkJ92MJOcN3LiNysF18JzXQsHU/fnIjD0ym1sdPzzXTxmPFMlC
YBi4FkmO3esehfOPlxpeMxZA1T5e/dJ3c5rm09B1OlRr5qQZ179NzdZ/MWnnhRF6ggzXKYa2oToM
jzx5RmfpWJ4oq8p4AJ7aQIFoO0HEvNSG6YijbUA2x1J/8o3oLrrCCK5j1IePMvAE3SbNPCW8XkP5
rvMOAwAvaipleYMAJ6rsDdGRcw6/842mct6+LG4s/fI00XqQE7TTaTAFW2e9ThAOeu2MGtnKcg8z
XXNO4txp83tXw2pqUDv3PrnFJlO7QygNR/B2y7/wXuWp10H0pTH5VrR5NiNj4y4I5tuRfyFMctma
e1CgVfpwyUlYTRB1fT08St9dJQrZW7OXUgHcVponxzzjacpjWiwVFxputbkPzzoOVBzUi2tRJffx
1LV4tAPFaJtPOjUX7VSWGFAi+xwuhFYkAQbZsE8qizjTg/TdkYLg6W8fWGQIVqb3vyQSNS4B6xFm
u+JExRhhuTAHWruqafaHZ6vtWkqXZb+cCBfj2p8utpFvlpcS5r5b7q6BIGvQfS9v86f+IXR96X2v
jTOgxeVgGpTmb6/YAb80n2OMxGBSlILYWQs4MSGTrOSEyge1HYjYt5Rxiiwqyq/vS5h+zd3HD31P
93yW19HixwwRHS06fiBY+smTkKfqiAbaP7gI+/Qq7efTfbWKfYPZ77ArZF1p8RQBNPBzXKby1LNN
iw45bx2IZ/aAi9/c1vy7k2CWaVlUj9etiRH3SLIffZ0EBhna09bk9duMDXYPqxaMUSAsP7h4Gf0Y
1bRy9MmjCaFdMz3nlblyBKmMXcnUqpgUYpU0yeIa+GpuYVf0EAswdewtuaqNSa4Sm1PTxIsyJLOz
gn0ms+0xY20Ot9ECzZNRDRRzJ3hnDl2wu2sin0C8ZVxJKRN68Qd68ELAvKACYzb/SGCAdVPMZ65f
78Sw7iWC0oUONkL/UKUTMnMLrzXqFiTxo7DflrP8Em5iF+7WqeWAkb1/o0iav4eIa1xkbGEsT9Os
bj7uHttCRzsVO8P/DbRJoOTXgVb/G8XZWC+GwA8tHjgiTDS1LRgJX+f8aHVM+siRN1ZiMy6D4DBE
C7rH/fOyiAX5ux0NI6XFKdnHSuC+74IL6dPu0V3CVQxdyhhsSUB/hkMPls5/RDovZK55Td157o2r
GMV1TbMhs4rMPuGEz+NP1s8EZtgbmbvUkFcI+DxEZxx43BcXJqFOOFjLK/pbyqJbK/HIQnVSmCOl
n34EwJLapfd1ni9wKkeDkYQH39o4oNJEWxRM780YOwyZSWh1wNgrcaK/UGK7trgyvPLJHRLhYKA5
YJhoRuWj/y734U1coav4h4cXazcm8OXresdRnN6e8HSQTkhdd5gxm5RiWuBcnVuWncPWmat/gc/n
hARafJmzFjdbGnVvnqlnnrzhTnYBCRoPcgMd2PWIcJqJmjEP4AI+0CTtiSj+KiALSQlgbJMOfCgw
u1KYgRIqJw6ptL6Phm7rP2kRsloAGAv+MgjGJALs8NM0FkuhXJh97AlCvChyXNGEz48dvdDhZDpY
E8ckXkAbLDU40OJ6/LeH1TTqJcKu9laBCGa+4hTyM/WtjULUSBwMmKRFtgmHYCWxxvp5JC8R+iTX
l6YENI4rA8SlsYpWnouCZG6MVV6hPCzQJfMxc/EnsTTSMMGEqE54cEfqfNQSLzsUd512UfIA0IX9
4E8vZgPJxzGpse329ejCIYaH2wm4VIXbohsn2O1WM0tMzb17fu4FyMRN2JZhNkNtvZdsxgdV+206
Zg5X31Q5BxmengMShM5/NWYE1rPHyKJXIscQx+yVNuzUOUr8gX7CJcvbpxRxxABBgUHaOBr8oAnf
kNW05HtLwTOj8ynzjxkmejbycYL6dBm64wdL3vCV0z46SxJXrbKgAwCNGS4Ox2I1F3M1kd19U7RX
WHH1rQsrKSx+wrno5ChhGvGpLL27I4q/IoyBdYAfK1U5kBEDk7DRGeHBh4bVNdmj6SPlmYhpubdB
6AI3gvDbjkedOHoZKaK5+pKzJBYtSiPigbydrGrkblB+27mhLCDmk8x2PtlWZYtTB01tMWHeiGr8
lNA50cXoILPIPVhcANEBy8jJVBI/enCeeSSkcDMoHWILI/k+Zeue+E7QxsdcRKmr6KPcYElPMSyj
v9HctslooryD3GT4B8463a8Ofho0wvmVrgQ5NGt8+Gz4jfk7m6SQHl8skaHbHwtZ8nUWDieIB21p
4k+pn4JBfSGC4nWbthXusU1egtVAN8uv9rXmJpOgMnNo7tPbVwPAPvVqjuu1C0y6jA79t8897OJB
C2LfH9NjZVenna/w5cfyDjFdhi1mYmfpHe1aBZJaawytwHznQ8m+rEJLO5fEzdmeGJ3G5BLOzkqr
/JlajUt1mpW0+JkE/Cbp86jyuAs6EXCbEl0gEqJX1wR4miv0J2wu5AflbwdblCjzDRJnR8Uvu8yX
aZ2GnSH/nrEof498hgYqshZgf3LTt3pSTy1XaEHy0wBAaaLFIkkDZvHWhz48BJs/n6sSLK+x5Pyd
nZ4kgjGUgkW5GwMXshJ6fZ8sJbKwQhfMpXB34VrR6T/ZR0k6dmz4UoCfUjTABU20LUTC78vP/iSF
TBQReeLxLJmyWQfbJ9VZwPcXJQsClRpKnTu9xfbjv6e8vWyu8kDHJPPiE3yBwFQcU9HZLY5eBOX4
xLTLqQfnyu5MWbZMBjzIt4dYy3F0q/sPm9Wat6XdkXTtnreydDtT14b0C3gqsaGMFOp+Nuqznnww
l9/cn26vyIW8KiLexrqaMg5RIYCTnco2SVh0/kMyd9B+y4/msbZBfKvj8y8fkoVB9q1BS0sg+DgM
jQvxg7eAPeoe74l7zzjE7SrCgB/Z/NhIKUsSzp6p+IZVNXILqRUaIM0jiP0VSszO2RKt0gtogXAN
4lnu50ojS/TETt/SvKG+9Gvg1LPTqBQgseKiUjAIqlx7o1HOufi2RJ1LjiE8/URLyOl3NG+7Ce0U
a11FbZWb4zF+Vp9tkVm/d+zKISl8ePwU8XdnLapFQQxqSpGJreLOWbd2W5rFDpUpdePgT8dSae6c
U8hDYNbHiC/2dJBgp2cHkSAT62DQn0WwNvz4VnE78xi+eWEanTvn/I6TCE+dLzA1rVKL68ijfLYO
L+2d6to6jHQU+myYLjCkmxGyz5xQbzct0UpQ78k1Soiw6nh2y+Npz3lZLjyji2S0Y3+RBejRU1yW
RLkYv1lTkcHNTlnLfEPsiZjmpIOPb6kMXesiU024a7FO8G7t+L7Re93R0mqPnu9FXBLY38imDffZ
dfaYvwiJ+TcuinLjidUvyeHwMDxhMdBIJyB/hrpyeD6NmWLlVuPe5+D4matiLzS0Ja7vlHi2sKur
ddok/SmK4OHqAJglguvX7XFZMfVU9F//1wMi+UVV55+JXKMz7X8rAcRGEeWdXHxlJZjw+X3GR33v
VYFibXg5dXSz4DQG5gFqWvC6NaEqJu5j0xS/5FbK8Zj0QxYPHLQnL9Niuk08KwxsSSZM4q5wDVqj
gFsoHk1DfkUAZuyAzTngN8pSuXgne61cTQJ7WNmaR7QK8GaCgQ940/2p8TWM7OStJitYzMsK9iEv
BBjq2dahbVGfIT5veETTbc3Gim+i1RY5DKxRJ/mqJuqtI0eSd0Kms+IvZDgXVhKJHBASdOMiW4AC
SAmopgmHlaJDVgEalmSCCiTXMWvy6P4V4363mYlAuAEbiMvdScH9OF8ASLcFbOLDtjC65GwaLcuG
GRSfqlHb4UEu4wg/LdSU7GAs2Sz4M/pksu+53dOgZ9rqjarIvJ7IX5/nzi/IwLIcir2KxVp4p4Td
8+PTOZClS+kiw/lCy+hgmAAInqcAZL+rfDOrYW4XtJGvSt8FO73WM2P9oUtlglKeoNGGl3r5ai/X
IfXb2HEaD81NXnS6rnQ/R1TywYNcsCEfdoGL2Ph4fUCVk/ZOkKPJJiEkpAVx1UkYm8tB1HuISrzl
bVJU//i1RdLds9ebd5PCj4pstiDZxn+QbyWzq4rxzciNLuNe3evEbPD9l6n7AqClUKj8/cPRlCp4
xgd1pgr3heEmXaaot9sk++PnGKm3/VT5MzhqFBYw0/GhMxrv3iiNo9xxudCVoI6d4VeUGnxFNnqK
jYb46ctTzPdt8YjLnLweYk/TgK+GUXRAfp0o8pnmM1j3W5asrsu6wmIBwapEelhEJANUISIFwITz
tZHg5/Q4T0ClSzBmcUB6bJMRDwxiWRc9URZ4nf0M98NkcDeBVHu2zlpl/gjDBaGGFjSI98WycStD
83QVPhFTHJQdx3ZC0yvojn5bv/mGXuGlNMgHnIPahCZ/F8p2Xls0Wr4Yixw9B7SVOmTKJjOQSRMi
MVswJNWwP0rcR1OYyQqP3MpEkBzNJvjoG1TL6vIZx68aJz70h51DCmPCGsrYUS5i68iHKFrjUZjG
Y3H4BJ+kJFELx5pRiz4mCF/NM6E2e23ERsof17dsAh5vNPylBx3s8/cC83q1+HWubBAWmyCb6tir
/S5FGd5Vcs86bQ4npX+m9htFsTq/fHehDP4/AcwE5pgcB6t7sKNcKa23t/0m7y9xc4KtJSsCkxab
eKejxFhTWiFWR4NZxt3YOwD/6yMfIls8PYi5G5JOWVcha/EVWRfCar8VJ8YsTl0m3gTtvNcE9XwN
ptTdW4PVTdlEFlHsnVrx5NiasWQe+PWXgScGvqWhqcG5O2up/U9QC/wwGhXLA4pWtG8oY2JYqVEA
gGm4ababZLe1o3OUUvpgXFoSXTs2+vFUuKCMYAWcfpBLqSghIt21Y7zdTRfsxjgUH6kC0M9oHAUp
6dqRq4m0VDEiTh9fiLp3xphJ2+VOOlk3PtvURLxQ4h3F4H4dXwUzjOuWWqFourcPg3/jHejdpXsR
bWyGLv4oZHdxE23UBt7uosEN01+6DLyqrmPFXya29/F2oE/WIjuKBH4OBXuj+p2vx/Fu87rsID8K
/oZmauBicG9RqHNyK69t5W9pOOVhfhsyAtuakkgpxEAw5OFG2mgNB1YQ76AMXUhdX6FKrxXTuZSq
spQ5xhYWkinHycmCrqQxMCtPiQzEB3YlbgCWIl6wy7/YDkopnm0JuR7k6gR6jaGE+AccADEIPc+v
6tVP0e/pEf9J/kDbEzzKgJ1lfPQJZog/QLo6dnDRZYOyIccTMU4kUwODBwygBaUlNFfA6nEw6kag
P+ydYymkt7+tkxNgoR+NFIBCLwIpd/mFOce1cbWW+2Ost2RcpYO8cD6CoFfyv3PAx38E9ZtyIymq
ebllh6Qrl6tBe+DmX5poc/fNx4MolC6KVli9mZE5/QRjRVvE+aUflZ0968bye+fc0PiW3ePBlafv
+W+uriwvk3yLQeE/B+21S7w3bexSvTJNWcNHplM5TPp1hu1q1NHc1i8yjdWoeczx/nQwwG4W2UXI
y9ozROxOTnAJL0fjtabdgIzt6C3+Co6Au6fyedDXa4c5JRIblNvKdjGmToxXDgHVWa3M75ho/oO1
EBQRsXISLirI7w4wLUVRgihWoZX7W5k5P6D1mVasvTThJp5PQ7qKJD43Cg4CM37Qm0yXHjBjlu0m
GmgzoBHyKJW+x/5gHEGdgd0L1ZwuY1FxJJtMf9bypVWUaXtBJRSSrLKIk2nTOUl6kY0wIfRT+XsO
FbAashVySP/9ozSLJ4IOFUc27f8pQ5QCoCcEYHr4tcyXxcnYjEYI/YTqQmYPDnmsf8sqF6E5elhm
5VNMGCzO1EyQlOlLognxUiz/8xqUvaHkImaiBwMyNurbSq4dirUUwsE9VyOTSLAVE3pQQ+JQgcFD
MMh/q1FvfqTK5q4j9vaXnWHyCgI/lIxo2L/sKbf3MwJYy9+OC9PscGdMZWqt/L6ycez1WVb+ho9E
Kwwxy9rK96PC420L3NWi55aQseAzDzYXFyJRoJ+O3c2ztqXfZy33IZmbWdNnSWO+q2GwcytefpEq
StlH5ZXo4Cyc/Rw9MpqwFzdsXiNY8iBeEpMDlBBHOooZjTplGSlK9THok2BI4uAGrdQY60+zL+JV
7ybHOGKcUfP1FL5pMtMgYaqAH5YgIu6jGWzTvEG6ojRjtPwd+trp6wuAFinX2oFQpt5xNNlJ+gwB
PLgeotmturFIoSyuyEhtexVOH4Chyb3nOuYkrJ+sdiGO2Twj7aRKi5HsSvHv/KpGU1rGzwdMNwWB
gx7sLFdo9nhcyHoVTW6rP5uTbxq8efTwar5/JD7XXHUw7A0I8gkp5oTqBh/aq20z5XwtEF26/ovZ
T7Z/RFeVyxhi1582spT/KUE6EC1iqfkNrDHh8ZagiWQUvLGg61XkA06FljSxQBsiu4xhvrVRiedp
8iFMZBvQXccnLDd5vn7vkJEbOyQvPkSf/ll0BcWQ3hg/b/3CzBePCJ43XvjFkQiZ0UNXdPPjS7O7
6c/HacvmB+q5EvbWxyvpALUaIQK3248LxVza5ehtBGs85hgoO/ri+g/Dng5sPLZZp6jH5UmcdzMC
dCl4wQxmBnyLq3kUOu7Umq1jwLl7LJd7I2rBkvyna3Exq0xov7MIVfQGAws+h9qUTkAJckavsBkE
Q7f0jPSjR05/1M+JmGrMj7wIWbEbt3QwS7+Z9mVWsagHzRNbsBaSK7PxVLz41NYZ4pIz8reQ4Z//
52dr+42iJSMCWQj0Hax4IGlnTOE4QYcOwSVgWxcyMlcAnGtIiDST8vnEXrfQiq46ya19h8/q7HnZ
YyrSIRmLtAbQlW4+ah8GB/N3SwI0bGu2rOVW9nzO6A9TAvXNeB092VQ+U3vmGJ2Bwk6Gi2pM+uDO
tiXgHnQdmovFao1sq5NHBleuHQTLNQkNVD65v8qRfLm1+97iN0WPQDS4WpUuU/W5VlwtpjmMP2wN
a9MEYc8oMq4Nu6jorCUzzCiIw93gAfSvuQs3vpugV87m9dQ28kHLqgTwQarbS3KqIWDGmuBLDLFD
xJyWQvIKLJ14dQEvWvPKj5Ee16JJR1lsje/gzWOcpIFX8PgegH9bYbWYXJce1aPPZ7Dseef5GdqX
iayNkCW9Vw4leOMm3e7lkk/M2Nd4WL64pm9O51ZQAhTJ+fUuq5lOvzGkbcqxkWM+VgcLMYZvwz0+
rl7zf9BJ7Kn/n9MNPck0MHeET7tu4UgkFAsImJSpLFHk+4GjWbVcCukwQDJFNAt7awkdx89L6s6J
DtVZ2fAN3nEWn+WoBJBNV2kxEty3o0+uFEK4kCgHCzc9YYF/RuGPKM0sJDqscUfbSgw4AWSSgI0f
uvkvvSeB5TvuogmtmP0X8VffRgsb0J1QhaOEndTEgUFm1jY3WNn31oQJp0pm4ELkOoM7vVsac+BJ
R3xkP3+W4n5/5E1ZVtHZMjybA9i8yhNaK9UFuuIQgeIS3Jv4S6dek1L5UbCz4gxEEDJ3La7XoutT
HOlKlO6O7qa8Ht8eztnxBTsJut2Qw4DUnZw9WpMGFNFCKT2VSrSVo0fYoc7zG3ekwmNQKhnUDsRm
r6JnMLiFSY/7+jmEmfBgJlUbjgajWJO0iIYaK0HuwsOXsONclokswD9ByIQ+jw+lP0k59VUVpNH/
8h49ulHysoV7KuUv+qgYNIp7H4O9JOEibwQgWC/64Le54sfh9fRzcsDi4/FSkXe8K2UZPrLFH2T5
L8CM7F/henOU/0Bk49Iy97yXp1qv/HeVhvLa6ScBHlX69JPfOoVfe0HkUqK49irmaeCXofKBVg/Y
zDwZqqrOW6g0H+BhfMYtdsFwRG5vsQyyNmpBDk3+0BFIwHJMKkH72TBJF3HPkw6dhH6rNN8kXDQM
te2s5sDbIDYJMUCfKKotucqc+qew/GVhIk+6xJnLPrtX3css6RcebIIeK0sfmqoDuj/JSLnygwH6
y1QPJbYwiCnFtJhVw9YppScIq69ZivsUA8+dE2jEnxuewyQoZwQyk2poZ1P8Zxr1yChrnRRrWAXR
adxZFQp3cA73Wg7nPzgfGDJoL9i8G89HLppKLxQZMBObQwxZqdkV9h3x10ktix8+Xz58eB3VzXBB
b5zUreUUcLarulwiECR1271JFHLrMi7Je4ZbU6fThBFeoauuFFyVvb8TbhdY9H3x1wYFnulPRqz5
A7H13OGyAKY3AjO4Pib69zXXOG3X7jYa7vHODLK+UBpn0swxxtWKHrIe/gL3Ir1N9ll7U4JX4Ih9
5Ba5OVHYhvYwfWoEJMWIKxX+y62nkHuA5yc6bKweFlxVKmYAsQFa5QY17I0fGZl5dbMcMHLf4vHO
dNoYMmncBbjjT4+NYLw1OB/m2bbngjmoph+gQtiVBDtiRycZy41bQ5hS/yBMCsnCM8bM7PB3bBk2
OajTXCiG+nmYkMOI3bQ/Np2n3rxwxZ0WD0b1Xytubm/VcFgwFgrxiznn8tdjoadPtki3yKfoA+WF
99bZBz/6emvqKTsidHkt/QhnVpiR1VUlYSjnaAXmNjO9rAgC2XFFVnIznVaGFsff2DjtRP2os9bJ
w+aoW3Spz3FXyQ4jhqa3IbgtCquV7ttO+y/nNNT06LEOiuYhFcwoQAb31m7toD/ZBwbkjYYkCPHg
NGPkic99eYGMOxjaciLErrAZrr9KVGRsgWQlubllE3jrjD2YAOr5TK0a8UpP30QbFjuEPM5nHUUg
S3AzlFf720LRYqoJ17BR1RZ4i/mOwXln1IGVqyysdbhYB/dxDDHJ5ri1zJ9cUcOaEwESxmv4Ss2a
PBvsenLBrWpGkpUdmreX7TrXLu4i3CyJi03FALscJHGhyyTX5N4KwrJ31sqBPMfLbFmQ733mkuUu
XjrqFZ7eS01pmLbnqe8XBlUYR2FtcpbRsORdSyuFa7Q1QZM0lp3q20KtADSgw4s+te+cTs9AUGSj
tzf031MO2uZhdyPbhLOGv27SC6/cQKZ3lSbnqz1gNJYvdQLhQ7Tu8OiDyvwYDS1dXK51PavCGRko
SwR5y0TnuaeYSIzvJ2RAYF+if4n3WFRBduCHK7G62Y4NgYOpHmYHni9ny5LnkUGDEwkds7KAgu95
WbQN3wnKIOJPMD/FBzS2XKCL9Kp6OBQl31/dwzIZ9t9uio1BWAu3xLs4h+/4Tsra5UNhMl1Upba4
d/hDbPDdbOBmaszgPGzGIcCHPk+uhoo2Ovre8IA4EFGeiaqS/DpE2ABikM2KnuqOo77oOGmM8FA8
NByKFWiQFHOPZHxJitCnTSPanA1mfwppUdNlL1FAjufs8wnOuGHRL80o0Cf3Q7WzJplixECgHMVX
vVldNICF1RvSqSk9zOMx2Uc8VxlNTq+R0aBpjiOqdDCVohHzk2poUwmNJ2leJQKObu5Uo3Bp4SNE
BYVm+UMd4qOPTEfzkbfgzvfW42pvFcNBoXZ9PcOBhEATkFShfomdtl6s5i/8yRRsz0QaHH4BRRxj
0V52sZsNngrQyGA10J6rmjyHSVLlis6tFHUu2RWApT4IWNnsohHVp23mAKTeCgfWMnzaiXnp4qtr
6/wtEcLNSNQNocIAi7y5hGqN4sDnhpZzHkI5KwfDXbo+wTnr4wFT4ayAuKX1uoUfFL5/x3SJeVll
E6juv8q+lB9CS4dwrU6z0qVdYiEfqtDs4I/rK9+pIGWB2C6cXd1fKt4X+PVpDEKVI353vWVjUVmk
QayqkKbwcFVoUoTmBiiv/5u8UYVnlhxOcly3AX0pKHlqz3pHPC6ShfmY9NBnNuTa+dXqFn+OVWsS
WhM1xleubaWWsb4wWBUFADJpUjPjoJchW9G6J9QS2VCDgKlTm/ddbu1QjPsqDp601IjGwOU6kdEW
cFAY0Ef5T7OuM6vZyu8IvrF+xhLEeWqGaDF3vqQscb8hiAUMIs6UU3g57JmhpXVTxXVDPGuk8FNP
F5SzyrSNVnCmGlxCAjqpm9Y7iZjWj2CUdB7fyEER2eeVPYFcupDrO8dLP/IcWqMs8DhWTVaobIMO
eGDFcMBrIrhaTIGJTqbG/YkdPIOiM1Y8zCy/Cu8u6Yjk7GDNtGMnfb+TwKVJs49BRiY79R2VD60t
HPBYKWEzX8dKjs0xCkqWsAU1nZhEz0oT2l9hML8evPFEQccQ4moreGKIN83dbSXqNqhWn72lq2zb
HYUl8w7KvvX6zkTWwW1vCrLv4LpJFFSM72Hi3nPzyp3270TsNd7/0jeQjLGP6Mh64ufzafeNwnGc
nn0wpIWFDEQkgHTS9b43av8PQ/PCk8A6oI+Qx+0M8CjftvN0qrIHGg8FjhIqAX4MB28CktDg1Bj3
3UYQMfUdJIc5D9AAEH96Nd2HHlg+FZPAt5pY2P/03nVKaC9p6CWo6oN6W0cWIAj0ZwMUmvjKrskU
qVkRNwERSu12ODDcgrhjcIrqoJJ5w1soRZfItw6lt+Rp4vUVzAXitFOIKwH/rVT+02WnGZwJM9mH
lVWViFrVtlDuxGxEIU9WXEvtMWaRj21EQeMrkKCrQnctNvE20vALqXF5XfHIAEMfdP3Gfc/cWeOH
3W+qcwiNXQJ4LwQq5kosO/5fv5Lazhi8Rfv+37f7j8rTdIai5h6fTb7i0DEnmiuKfT1N2ZyoORdT
GyQLYQqzWqcH/vrQo75YUoLphE9kYQqLPmPH3F0y+RR3av1zYF7w7TzEAZG7dKZZJR99lgW4ylLp
A5lUetGrBH6bgDTss8MVlwgE+81QsDo6nLBkOmNl1TiZLQSIDqfAKtglwkhaQ2FeTj8PHD4iO5bo
91zSudv6BcXuEBaq8mEEUChjjrO0NcPSU51HbuYgaDTCjXtJpTrLLKBvA0iz3SWAXC6AGsnuCX5C
Ynh/ikHHSentmlw6B/8RYFTkmG7NveO+bp+oM0lN7TIM/iT30DR5EEb0kUNuRhyOs0OPuOxysrD7
RQNi6RtJ6O+oDO6lA/swRVxvOzEpGAqH1va8naifCfbBDA76gT4q/ZnH7/jWqiphlGkUdQem/25O
P9Rfy/kLLVCfbDgHGuIaAbPaVWESKk2FL1itUz9ZYnXI7Kt/0TP999a0MehH369KYeIaL12rbOY7
ifwKpHikRHdTkZKFQvV4JShCO+DEEGYqMWUdXN5etN4Up2/f+ko03o1UKjYXLmLYsr74SK4DsD81
ShVnDU13/TMJDa3Ac1GLNBKgKaCB02M+pPjWp1ClXK/CtOUZG0bLbVIK4v4YNECBJRJmJUrwtEyG
vdn4d43u63i/gC/m856gH/PiadzN3FmdRYkMvg35mOax8A6X9I3/+2vnvn4IkAeHiUJM9NGeMQW7
a2EWoqPbOTEtbHbINGjh+VcMPrmFa9HOGsOuCecUcbP35pJSo4mYBIff3VLrlqbNVg18H0cB81lw
SEUanBxed73lVQFg8O+g2IIsDf9f7lfXe5tDro1MoBNKcaRsYbEvipXnA9s/C9uH9mafrpGYpGS8
Z54HJ1e7U3c20/CHY3QpLYR6sBgq1K0rEy6+Ev8ckGsKzzdMOGRJ7Tj7CZd6QtZKTkiuZJzLS5fv
df4fJEbdWqaclO97rYikJzHILYVslsUTKrTfLlKFGrCeSpuQYJqAQG+ODFfDr4r4fXnsjH3gyuEI
F2oQ4C2ps+gep6rlWfFTvJ36ukkbXNWax55+XRriH19fEigrKzRGCe9jDUjyuIcU6ljm0uOgx2hS
WsKlCkdEncfFGn3MUEryj+DJP5JPcjqXawlYitOGPVz5dZZTya0UoBLR3zz4ib5XPYexx6Zc+5BR
7rZURPUQ4HsNI3s09nVDO0uzH5EEkl99SjDSFBpHzv0wId9MvaM8NB5/Idk59VUOGTXFK364Ql/f
7BUlPiQrZw62DHZPasPcT+HyCa1nGLz1vEy0e9U+jbcxQaJ8hzXxP28aNaWqadCX14292QAqHQ/N
nWysckC2NbVDT+0sql5rOh6h0DdvZXLnAkvs2JlchFR8r4NJb5coW3lWn9cHW1G0izp9NzurWu1m
iOHceXVDQW8MbEDolVR94n9bJsdNuNji80FQTATnE/FAkvuJ7Y6kj1b6wD32J9IilvQfmLvZIhad
wDCub9Pxvm9gLqVmQ5CG06DQAbsvA8LmFuzgQsGK5WI1cqhO8wJeBplCGCjfH+xxlFRO+uHIIdiF
aMYW1QrzgTql2jFADA++edAU+2A6wbhj6YzCMu5A6ZbWrnyhUwZkVWtm+Ofi6/RN10vErdwvM6a4
pXeP+6CHP5tMVDifCNeZhvgqJrd/9bCmzoy1LtPPqRL0FC1KjmAhin5z/OIGMWcSzzAWHxJrUC/4
QGz8Sn7McOdxZE3Z1qKm+zDEKb6LiNP0xKp7dqEYufnQGZ+AClGS6lpK9tPmKimsrW2r51ggzgb2
6k9hjqCAYgGUQD4OKRVtRcPyViDUI46w55jYtYAo+CfTJc6a4oBDpJK2bIbWs5RhTbRrb6akmSyH
S3hssWNWpBoz6KvO52fB/bOZpPRzVHnER1R8dp/6AgLbQ9W0CXWD4TOFCTDdqozyiz2dqaA0QUqD
Y0MCLhIqYYyWz/Db5URrXloI9sQ8DuNLrjhkJpm+CUhK66DUmVH1+6VCACEfG3YzZId/zFss4Kpk
fqhZ1A+6EO0ELa+RZrSKa3vmsFDqqF705GRhP/CW0iwFL6qlPwlGB/oBoBABs6S+qDTsujFIcsGt
B62YFYFM78Q0uyTe7X7CCOOvdCpra8OjN3+PdNh9TefJGR1A7TA9ea8z1yy4HC7EhP9LwELTA/pq
nq9SZV7Rn3/qo83zR6+d0S5exB9bF7B/tpifYtFvhn6Zsg4adlLy8FAIbQccRKEGwIAdLnG60RYV
xpvTIcZPM23QchCx5BZx3b8AjA/PERzJ7HWJwcFSswKLE9UbW5Uzh7AEbZLmeePmOlIeIXD5owj3
GH/auIvrUOtjeU4o8AjQXfXcSo7+WOCqLFsnqAlGpIW+CDLcVvXzoQ33uf5LH9PZxebXt/rGtulO
gVLXF7uwctTLW4KYc/uXuVrqwGDCq5l/KTnx+ocAZT+UZHy4KwHucR0GXSfElE1hw6Tv7tdSRUF0
tIr6R7/JWT3wwLDoO9wFynPG8qKzZqMqwf5EBDRNllqDicTCTck7dCWwAIJ4VNzXbbgC7YHEQJfe
aeO1PVn371oVTQbbmgF9axcn0jUnosYpamc+UUsi56x98lfgJshgh0SS/JHSY1m//xoqxq7BPOzl
5cTdSBN0A3uJTOfQypcUL17wK1YAtz4gIL+5gllI1j/dEdWboltbo9guPFVn1nbO9p/7PiXhfBNy
4KLDwhdYOfbePMWl8QA4HQVpfvisJEUhwV1MC4BwXVLi3oco+ijT4mCPrcVktYngoyClxAbG04Av
4DgulIkXjOh0yCEa+cFswe/M4KJwB0BI9VO7geZsVR+zKEp6rHS9j8Mg8RqpSw4vC/As/ot978Z+
xy8hyOY2J6sq8nBP4uiaxeYCDf77JcANRJPv2Khu6uyNuBQheaiGITXYNQvVflqjqDva/jui+emu
WcWxGSyP2TDHrydzB0W9Lae378fMu54M3gjx4nuemGBEOFc2hZ39i9McSLjswTfmD4MNKrs5V3k7
L5k1s6a7de1+FdM6/uokbtavvUHMgEQmbU2+EV3c/vJIh1zyX7/Wyeze5tvA1UVTyHfOp+a7IVRF
v2MgN51cWbdMvAGanGDrYYUKbiQdPiaxG29jT6wdBa6uwzDSIOc0CEadW7+LErQt/zcGRG5a9vsW
14YcSe6G0oIILK7lfxBUeDYZmdHbD8I+39zj3IC4RE9o1Vv+PWQG9TQ7ypjTGcO8lDmsEN7lmkRX
/qTDi5FRFwZhxM/GdK/Px/RUCWofmgezVADkavYBRVIpov+hsbzMfmaXAI9Ay6aZJF4msep7X7R7
GbZLHSR2NmMQREwKMZePqwOPJ4W7ujrhsEPGJKY2cdlTE3YfSwWnSFOZdmLU7yeJK54kExgQ/Srm
hC5nXqsN9biOv6DgJX8LAre5/TByZPisa3VBYkaBZdtCinPDtW1yhKqBpNK9irSwI6t90a1y6vDA
O5LHlGHOjQV3lpASKfU7DZCYtHddK8aeNlHxhEsvjTzFsN/AQqfc3zOXuypJ0+4w6K38ThgjDx/y
l8YNICJFmrdA2p+3aAPKv/SP/sPgyIjC0n/v431tYPlYklzMUiE9ADrNYLoVoWrlgpdyPmxQ1MNs
iAa9bRj+Qh/bxVVRaR5NEElXwa2dTPWVsEqCyBIOzL4bNRc2r1AP1wj7ULcF9G/6SPPQg+vGDPRl
elAnJulwYYHiVOJVE0KiFrclxINWeM+Tro5Y+Hi99T7qk7w9juoqWNWnxwmyIZDudkPjzvPFNA2L
aYlij9dInv8f2uZs4KwOmruMxSkgaqvf0WnlqKMP4DG7qH0qGnEiXonzo0E3ejujTJ1s4Wjy3kk6
gXFTRbi2+JD9+fxPpQl2QnlaR343YM2M1HvASzsVnfNle29AqIjxC30xVtbUYFkeXMJujNhRA6K/
nilzbMVdfXK7DInI2Ut6JDNpG3FwnWOoDRCtG9h9O/S5GvAmcvdwLoThyLGCVWogY4AXLGvgtAls
KkVdeP59VFjR+uwRVT9gJ6Oka57EiQZPt7fSegmeNSeZOu8EA1DTdvK/cDLODKUneIDoO1/nGysZ
B+U2iiH3J+qGgkWMEkx5YCHbcYi+OZFpUpjgeF2u0FXh2ZQZ0axLnPv7JOHhJMdDIuRcDBhAxHV9
HcbctmSSySxZ5KEbcAidA2fQoo0N6qxUO/IQ6Ed7qAliyFwkFtD8Uo2GlW+9JhOHiEOurs/EGzWd
89xVt82lHJK52m2zhW1603YJOspSgD/k9FyJ6i7pI5FBsC0IR7UhOSXngNimE3OAomQNguhVOp+M
MYfUdFIppJNeyGBlzFfHHqoQw/DDYdrubVcKQKlZU4OjGNHfyCMqkv9QzVqjiqe9sK+qWkg4WlMO
de+0bes+qQtWNLPGy8mYOhDRPvcldDtjtToVj/zV767YnvXQY3Y73Pa+r+2h6prRg4iyAcdeXr4T
ecTRp7ruIrisMpCLkJ/2fPFhlZxz+PIOoQbA7kzZOEeKxKTxm9UWfrQXBWSIz6h33E6tIx15GUAZ
45ZQdYOC8MwFl2AnUDINNBPj1V+x30MkcfQYzwGOlFiEfShgmX4g695xeHKGZhVLB3IJElbQyEY+
VKCFSq06FyDzL13MFtNpOkOaDZe8ejQzuTfU5iMcuqNjJG5kGVlPGk7eaN6c+bhCc6r4GzRQcMwA
zf6pGUW7J6F0/JM6xC6IXzdaos0up//+4MboIfOcZd8oMtuK3LdJDm2hTxuNml5Pzjn8vFepfahF
Gfez1IKHLWhEaz9MWGFvI8RSL8V+eJmX9tzdI7mNLx6AzH/J7CXEFY1TmDyFTJWzJb5RaexiXWSS
GX3HUXa2vF+KP8uyMvHTAe3PR9kMeMQHWw5HgN5FfMrTb75mk1jbYohTo3D6hz57Jlr37TkfkWZ7
NBBCzQUwp/liyt3pY8ax1E5AG8q0WXIJj4bRcly6OJyzcIyJhU5y3P2GVvxNDQFaDTq5OEpgR1Ao
BYSHc2QNzmetSHLo6k7zZetAkDecNGWknBBC7Yia+qIpbadiwapvSUe4dGP4K5nx6FuBTIrJxsDk
HnyEKYd4AgNU+2apjQh3fY5Gs5oW79tNofGlzkvwaedimkHMEQES8W8vvjHB7g5qEB9g/TbMYEtn
XYrCyk1ThT2EPhgyNREtVXYYX9FkxdxePI33zs4aj+TClFOe8vG0N0pxa5zxmnrkJznDf1aLmqyG
zuo9F2EUEskFrQMFkxh1m0bgfxFzZ1v5NCLkPOfYwYs+Th51U3psAdWjM7i9v0D87imCyTOJbxFo
EXm7e5cJKlM/Tu7H+FinuDI3TPL3T2ULfjvaU3zycXEtmmDtJwBNvLRWRMfd2AvW+ODsd32if72r
oToxLmW/Mrk4ahjVvsPl0S461+JHLc+Q+RD0eA3Q68nfxEHs0bYMAOSbkqTZWzC/YeBwguUXDsw2
iED/cXRO67/56Yg5NrF+WFzD8uh0+xrdUpQ3gxGrVRy2Vevzc/shLFCD3PmcPo/d1Si9TDaL0Xcf
WvFy5uDPUQlR146F/9OhBQO/hNHHjw8TWxCkiNlgmxcW2g4NNCDkt/axX0R8cPCz7YBAYiPIOeQG
BIq3tlvFdcylETphiMLv/YNAN3bYJ3M1I+e4wD3KEKPrDxAuDkfTY2f6yeKfjvAv3q2f6ivWOHRS
nzD2eLIWXCkEYnhp0RWkXuKgvvEW4b4ttOIla58opNjp8RCaz+HufwDNnDuOZ5O6JrxOfD5lDtp8
7ezJdnM5yS1SV3dIxbRNcDeNztlyezS9H628CqXJSaGRRrthfBOrjEVAMlU462Z42S/j3mAYKGeb
lH6I+0PRqBvlB58XVnv1+t0sB644u4kiTNU+sBxOfMf54cqe8SRG4QW2elk4fMsnq2AYjIUaMGoe
V4Iu05+O9gUYHah1SkOkl1gGgSSzuXxCJCRo13DkMaQSaWnBB0aBG15CiJuGhfgI2ztBIfUpvUK4
fFEbpoVtWpGU2snjT6KcxWihDmCGjWYd1omifwX1sv2Q03rlCmQVQ38i0fCzXRYAbPLRyPzBlV6G
nGcUTkH65EgRWU+HMABILuykQBhH7VY2KzC9YWNI6WPCwJUFDU4Rum/2+KKYiIMHfLy3vDnkBGf0
qHG3vMfSIPbEqQDM7sh/Fx7zfn/nQgtkCBgoQ9uF1n2n10ChYhRjsHk5i+YdeW80NtMJ2SMncIQw
xYu8rq2w8F5C840RVbuqXqzrEiTItpM3h6KDubHKOuqtc0eBCYoUT88NTpzbxLtlJjeGioq+45ui
n95ynatoZ6WzWm3AJ78rU/7FtHxdUvUJFY2UzMbnrb0slvSRyYM7/BbWpJyc4LU8dG4533rmVbnG
WPBtbTXxj5BUpYMQvlAE/Yz277hhGSbYYxsZFMx+/aMq8O3cwEZ3SijUlct/rYFMI02fkg2A6jpQ
TAvNayq+M0jP+zBGVRU5pqDcifrqdodQSG+GqlSQMEGEt2Vmz6yhe5iTHSmXjHUS9BM8HxBCFCqZ
EnwSor3q76fhCvQdmXjG0RSSspty8pLEpb3NA49gg+TxjhtJQsNJGUO31mEx7wfAxuHLDv0C/8gi
7ojrR1VvlX5es5W8UHgj+92y0+YXOjKsp7bHX2BodI3qmwqktt8qB2QV+ITr8j6vJ1beN9VZcu1c
S1fPoprwB4MYfFda2fS2hrizkaQ8J05d67Vw+jg7bOrWYV4Nu+BQtnCuEFhXb0Y5dvUWqxeDj8jq
SxstP7J7Ux0uCj7TR7eHU4BWcBjH5FZ4Ij1tuImNx7hvPp9EGXQIFI7xQjewaOn5DlbbPxaLA/pN
U9ZHG16J8pCQ0PW5hFH/Dkwoq5ixMFVMMkQALZmPNp7Zza4v2rFFVUSC0mqwb0mopsD9byUQeoqB
Qm8DgRI/sCGUeJz3vEM9YZIhxxcch8hGXgW4VQteiLyj4pVj1Z+ytRTRTBgI7pv+H2A76tWir3C+
svRsce+d+rFj6ZKRJUjRxF3Awb5BteL00CjdLhnQrUD5LIbHjQMSrLwM3ijHmo6Q6MA6ImGO4z/s
7SHCxvnXZxLGUE2mPpMyZqt40x5gZru9XS+M7ksFe7nHG0IPxk6GJQfqSmDxpRMjXBGcyiSd1o3H
Mji0Xj3Z7Ey1QakVLqRDBpd9+lfnhMRPazoX3k879USDJuNmXcT3paoVd8OqLKFnmpL5PekfvzVs
r8W0r63/wo5RUqZ2Lj7jLmQCNjWvUvOZnguoklLpOkFi0hzOmNtPYgfe8jCRiCNoZD2R1ORiF4Fw
TaoYUdAtws7EkclGPnufXuo3t1PUCqvuzn/Ad71ext+wbMnyDh4+wgw0Lyi3J2L9dyuIGwanLzX2
t1sliG+cTyrUAAbzYGHcFznCdQtY4vkUkmWP0BNde5vfKonQg2z6YbL17mN4bB7h2D4f7FLTgJRv
5+ARv8EenEoCh4UW0vckpjGTLH4SzoVSyBPam1ZvP+Od37Y9WKbjQJWVcT7dEFDB8JphyZ82FDsr
6Y5YXjpE3StQ6p3f7BPZZDq3F+PhrqmZQz1PsLmuOLgBT2xRAPgXMLjWBpeaflkxE818Xkb67dve
mbbZbzS0g+bh+Ro7Z+u4nEGglPgmq/NVv9/2rZtx8nJ2hd5rNAQksgERQzRWs7jTD3wOMB9Ydgej
/svsoqV8kCt+23gc53HyuYOhXFjB7XnnGwxeOCyiisnuYXU3O9BtpkC/1mB8CSzWv22zKT0VsYIk
maSh6Cd7r7cMYeb9KsTGU1Z8FSAzh20HJwJ+zPMFI0Ldbgi6zKfp6EF59+ZVCCdhj+sVwbQFPNQ/
kHaSgDaZjINB1kRLIVRlRdQGieymV2uW8Hqh9mBRGlFNhitzVPSYJAdyx+IavWZgSh/7TXCQpG1T
PQYaE5Ldb9BKTJOl85e4dN0VWzr/PqyPTqvhstNrsT+e0UH+vfVGpCvoUT230meqMtgqFfd5dlpF
6QGthOHBWrFZACqdX5ZKp+4482FJXpj25Oav9Fgi9b11EoqzsHLI6EcFjBw2RvNkxAjlGxCfrpfQ
F0/O2QV/TNeALd5MIASH1E3/iA7goX9HiPDijdEb6PJCeVvmeaye3RbxrUPMVjqG0+2gCuDy+C3Y
Sb1rrfuzyKPTe+j4DSWQWY/vEpUZpGrtLvakKlywxzDld0vtQhW3xb3t0ivTUqqQpsc0/H62XO5s
nPtxLgpgtxRMPpTX26xMuKHcsumX21pbySj3GerRMk/oveT7+ylHawAG0uTUkxlf8MocFxYwgUPO
xXXvbHdAIKhX3iX5gCEAa+Vdf5mWTOSePHP2H83Xqs/sA6dSHVSU9eqiM7DbySjgnQ3y1W882qob
4ZgH8JbEagGbdt1UpKXnBU/Di1Ibj+qbM044+GD4IGvxWXaFwNtAGTuiUqygiAaUnDL7kiYSz2Wg
OFxpSBNo31kyd2ZOlMkNZ/hO1suIvigKlLxNu9rkh8Dk2KyOIqBrCrcsP7g8PsarOfCQg9oOa9jz
h4DxN5hNpCcJlbfh6sy0slWOKD+LsrWd6ygtJP3bxhQOokArQtaUUchbx8/uo5tROs2jcYCZF3T1
byGXX69Qs0QI9Sp+mVAwKGUrtEYAEdp0UpBd6/WYQD7Stk5O1vwLD7i4cdRzmkZRT8wxc/MzmIbu
FKqX1svnIFpJ/rRyGujxaDnWhhGyWpKsdGMFq4zrU5/EWx/WgHeocFY8vusFzLD2e6+G1RZDPMaV
Y1eD5rjuP3rsd73pcyoSZ47aJEqOa+OY06PO7HRwhq4FryXkNmx4/IcYOKLV/PkrIWBEWttvb66A
XzDndMws90AQFWay5Ow5o6eEwEBOd6yQzICGc36bgsmRe5O/E8zctfZ+Wn31YA4qavTwOpfjFzDG
KCisq58CqW47gSUXdUQ53TdDMXQbvAa0fcG+ff7r1/Sa2MaGto9GJT7h4KDxuCRVGHkxE1oIHATb
ADRU2WXPoy2SSa+aeQe1KxudsjDOuW3bOJnQ7+++RryyrSczS6nZww6QJA30ueYG8wZ6eCDHaNcH
rBdyA16CCTL6QSVS61huVAPYQJflzuiCtrdmQGxcDy9LqPUhD/2FMroMdct7p1GgqYnRfDEUs+fV
8kJBv21MJuibDWX6VGmQtfUkhSF5dQ7SgobvBVCKYHd0ZINpmyGArw0mXsv/OYMWoZqj6pUmFmcV
vs77sPt314MnPihdvhWZmEvCPW6zxRkadigivBc8ZloBLO1x/eMxhJtzHfBZ0if27f+C+31fhnqn
m5iwplzbQJL+twwh9Oy4yR50JVNKNo80hsV/Q+pCigSJUXQzqBJDJfGfweYkdZHXaHrZ7PazXqa7
ejaEPWeYW4Y3098glurqvBnaweu7Sv6rEemkxouAZPIIT5g9bPFDdwuZuSSS1S+T1EO0VOtakU5Q
TCipKRjPdcn+Wt5UsKxt1LvsP1pqxMpaB/fxamkNDd0KoskNQKOFlP50H4Nklh9+1TxGo55HQG8h
MwHCeABNvOc+hQZ36jK4mI43anWShBjbhnJWp9BLvm90EG8Y6ZgWIYXXMk3xT0VNd9uukCLAn5Wq
ExUyY6T8r5wIjYxNqhTEpYP12DsZlkbeQ0+p4sK800YELRN/3t5hhrLVZxzpGopZ2yibzZAhwpxb
FLuYwinDQj6Z4Xnkq300u6U56eEfyX2e8tvnqKBfpk8C+YaUX2LFydpVcf+ExhQwYFCl9sEV8ZAa
VG0Ub5B/RqBk11qT9qYRarXknm7n01S/UKFixvUAQrB9/CXurSv46ZlOEJ9DZlagFJc5B3yIu71E
lvbOxjkVCsjdl141ar2FgfvVWX0ArnUAhVl6vMq2XHMD+Rr6DZpkrLOM6tuyiSRIuRcDE8WO1jYa
q8QUhW4i3y4rvQ+cmASVThtA5LyGCTE5pfCTHJadmJ7Sm5RrMxH6SJDM5ZGUfJ/tYSbD/CSMcj3W
qBkF/hL5EwUkqj82qyQXA4fw/QhpTh+vKmvMHtS0ThlJAalAeSuUkv4HJtGHXR5+qPppDTtkTsXc
GndWd/ObzoeJ4F0v4nz+xn6e6SH0B5Ol271eMO43395HYlRs/I9LHvv0G+8tjJPnjszY2yRThj2p
PbgpCgdXcATNwLMr4kZm5Djpjqmm8FybQcmcu4z+C8p1tIBEMUQq4UyGAARErmCjc9wpPQyQkUeh
E/wAmus5xvW294BEpvXU5weeWV5GdWryL6FSbrkw7mBxrYajQ0czutIwS9mGUzOXF75uB59nqMlu
j+ulv7Lvv8oOV3+AJnLAMyoI6aicboGqY8AA4MoiwXJmM9VlXEMVxASQQ7V5Tn/PRX0BVfbZsWLp
09bXA2QcvLBwHJi1yBWRoGXAFHGUoX7WMukoquBiC1quqv7NcfF6t33Mcag940l77j2XRDUNGtjA
ijAQGawQ9cqFkWA+uvCTj+CeQW9ydTziLj7xK1Ydflwful9fysdVQcFQiA7J3ap8y77jvtgFEZT/
ba6y0OjbLYUEh4sgHOoqcRDV8Lns/2z3kNlxp+YJqlRrDRApwITzTyWnYTCVbI6bt23ZaBeny4o9
W1VcDPfJDtatuq1/JsvId3c8OV7IOZbA7E22e86GW5DEFOhHU1TUcoV1qdv0ohE6zKzexlz6SpIX
AWRSMtpLdM/gGiDRzXrGt1jtVnYthArEy91jhOuYKJgwKJE+T3kzbZiwAg3dfO5K2BJNRfH6ZuxQ
Y1dq/FDELZzDR61YtmNkTsCJ+nZTzDIrPzW6iPz7Mzjil9y9/IIkZQpc4d/QF+68LNhiaKNvEGXj
N3lUjl6L+qdgSQxUnPNoAJv1sjwB7uXSJ9esqY3hy31HlebwHwfuX52mlyHPRmXTQcnwjO2msWYH
dJUKXx5kPNu4sGoAv69VAxJfivkSQqZOFO/HPlecY2nQsj8yf5S3vmM01FxRp+ZAHBhex7SzAR0Z
PnouPcqPeiCLN8j26l/v/g4VSPaQqOQUJ1zKrtdxk2q14OJS8pQ/GWv3Dn9FTTKLitPD1UDT8AmL
GAS133a+16Npl5zbPLFY0aeQ0hrM2JlI1XrayATwCCIVyX7RSloU/tmjSZG9k+iWevvAerZL9f15
BGUEuTGaON43i48rgIgQdXQqC61sPHk8qYDKfTm0teBA5u5ykJlRXmvvmh+3+MyOIplf3z+Wlp6L
tlB6td2ZKCdL/VOYIQxbVmDz3QDmjqbY5jIoeEmavdNu2HV6wA0t1oyEIFeuoYXhHH1y+/wz0g9j
l0PDjnTfkY+Bu5sDawB91HfH3Jw4Vi4dtTQTxgxk6CNTxFlyi3UnN0Y8ahVpmuzl/8A6pY8iJ8pB
QsxtfRCKEQfNgpJI2UfRBLBludiY5GYqynta52j290yQbr35iaQ53WJul2+QCaAPnD80urtzE10w
gJDjhelD2sUPv3fBrKuK83Dzer8+iyF/lKZVpJvRhu/Uvq0uGj6oJiaUCMel/hcGv/C4IgsoXe8P
D923r4bVkDoamLdUz1cKfUdm6K5yQ1ouCzVfjkyiie8cy6dakBUhcbM5Hnz5akeli3vWLMfphIqS
fONK8Kx+U8IfJqvUpAUv8J0sb7z+o+ay4gt+MvvMbmfGnvg92Dbg9ku1/o6YJcAxoXDoqBJxPfYc
pyZuo2VfPoTWmDxqIZvFCjceu6zDKQrtx45FLRiLnkWZzehgH7gbIWzuR3Dbl+P7GqyQcL3pZOpz
LHZ+XXo/3lJ+dBpmUkid2QGLQ7+2JPk7/HilB3i59MrDWuGwdZL02z3fRaneHpiGBxam0Aw5/5Wb
8xnBoMBXsWSpjHZTDjR7bfCcYLF+8j8VOgJFAG4cUy1Ht/cmNPeD4ve6tSV4A2pCpNGk/SXTw8+i
9Jz2XHpgxECBWafBuo9gqBeQcxADgPcvjjqjz34JrNZ41+z5jcNf8yj3ualZ6Zj2qpCfjbhu8wXG
TZYt0e54AkFi22qvzMwZ19XH/eBaA8bRqWNbZUbyEy99oORvGhVg/FbulOKBoRMCoadfAIZ1AQel
kyUxhraKeInd2L5BOijOvpPGs/yhN/fXdjWTNZAWBcF5PG/qJZ6144grxY4LCafegyIchSpQbcJl
i09Kq1JGsMGWR4XojeLcP1t2Ge7VMLslofbB8ygyZDxXjdwKdq69IsYfx1WJjxfNcXDZICEwhzwz
HxNcgJx83+XYlU7K1HvsCIzJfioDLTIMNiZ0PRgvEEjpQZxKmZLcl9dHHlA1i/Z/gFDYQVMNKlx6
EPxN0YBP7Hz40Mtc08VuflKeQpSe4rp6d/C83EmYI3tOFZLvtURxGB7Fy3TCcwc9MGefnscqqWEh
X69RcLaSa78XNFEHLMUD+QrLbDvV8nN43DrbVzR6fyqOlxza563LD9BRWx3OIod/66Pcymr0syeO
yCZOzRubGEd+s946Fif7guYLrPksU8vDTjEW97Iz+DSe6KMNG8cFTdkfNyUBfIpuWEg8TdfAq5IC
1XoFaeJ6fvlkeuBK7Z/SYftl6s1F6pWTxG/AbCY1bzYt3I5nrmFdMAmPAOZaUGwVE4XqxeQAO62Z
6CrZgmh3/OXwnd95Cfd3kxahKB+UYksJ3qnsfmeuSYrYFPkpWzglr/LHXUrk3beRjMeVNF2L0Ix8
IczSqEvu3Nlur3Lhy4rgQB6/3WEfMd3P/7u6nzokOvhtVMRAG7LNgoVbEPesSKc2HExeloF8+TdZ
Snl8Le2WSLk/WFgzZiZFjS13IIDuZdrarO1HCE0QRwrtrpZhqSrxQCVlWxz5clpMG2EDdVso70sK
bLJNkgtpsP1ps7YfMxirrKugfOqNzgT79NSB8ROvUbPoTfVGomFYsry/aG/oVVhlb8iVxuXkPLtX
25/h5doHAiGs3CdY3j2zyYX3tqP5A6Pfta15UdPd9L82dykfBmtpzwp9XSfHF5DjYkWaa8dbsciB
2v+jpFjRTCyjoGQR8FWAPv+GAIR8bMXe8Cl76vp2A3qpf8OXymd+qWCDCm9P9ocAROspL0+WRCxd
LY7bCRlpUx4wRO29IxXJVKgIt6m1LmdK1jVj4uh8S3ySrBCI8xZ6GwTMVQbsoy8UREkX6vIfFiCm
2J+ZLndtQXYKzuq2INSFl1zBPN9+DvY186bieJk6t/hyBsqZWi//jfIz3IKbP8rXnZ2PcUxP6ZM3
vjz1qdIZSHBCFCEKhtedRX9UUwK3eDNs4NqeV2j74XPJNZA5hyb3ZTEvr2F8m8ssv/WvKQaBzu44
UM/V6w1FhXZ1HUEMZC1HWoF7gzOEO4Z1qZAB6AF8/EMetE2lqMQWh2W48I3FXcxJoumSNsgMvqA4
Dxh5t/MXSTeEwnZBeGAzsCD+v63n8nUEb6G0PN/v5t4z2bZsaJY+RQeeKfnDZwwLJ0zkE9ptfWcy
U4WSwg+H4E/nQoo7t6JQrRdXuTn1+NOIuVFefpV7eFdI5iWiFA5uhJvqdYZseP7GNT2THSocCdCs
szsYRjvO2r0VJjSPc2OYGIkrWg/J0jLw5wtsIQ0wEB4b4CyTNxYjQj4sfgKNJy1pIdJ5Bl6q6V22
GTuQovfEwsP7m6itFjMmPoN4QS3c1e5ywrBKC+lMiyTwSp3op1nxRd+BuIhfpixpizv/PN+JI3pC
t4istFNpmOweQ61c0niTPydBU8Ey3KjH8qEVrd9I4vXxZX8bMVTWQmmTvDw927d0BLEfNrpNtRNh
X9zThsvyLMnUJyFuNDxmoivfozYkI1z+vm78/pKVEnZgOe6dqG2uMUONDFRVHkyxvGtXw37qxpvK
JQ1uRHruaIvS7BUGtQdDQGWldd96NCKM1Y9VFfZjH8q9h/5857WCVVa30zL/hBg8VI5L6DnkWcHs
HiXvn6vsWSUd1FRxIUYLad403/OnLmsyXlNazn+S5tQhOSjIxkeuiszpN1LVubLxM06QmmihTWXh
H/QYREAHXz1sca1GySHb6t6sfu5dTWKdChb8cJap42XBE912AHda8pGoDjh8RSgGxDsRqfwQTMuz
CUPybzrLE7SjNurZPy1aD1C1Fnwx2ZFHDfwYJyhv+GD8oX26uHsEFcZLB0CLhy1+jaDl5V0R02SO
4Wa46S7fz8qMDWRWitKl07RZiR0Zsd7D6lZSyRMqWh5LWc22XGuKeHcS/ZgF7TVvoEmIFwwhgYNp
AtaBZZrF1Lr7z87O+y4uaH/mF2kjMp70yqklpXvSLKI2cvbWETyzV/+t5mmm41tVxg1g48nPJBgV
IiDznXfCpMBnoGTKqIGKyalHUepoD9eq44r3k5gNBenudZBXLbhdQtm9I7GQ7q3Swqaio5ijBx6q
l4kxN9VraoDCqcmfiOjA6pXuKoE7lK8OxVrxHcYgHOsAi75QMQE/cWb1LcKXTYaFXSbuHZrPi/Vb
1h59C9g2RNc57BSZKdSXL26/5VjMjiQFQtXB+WEo11gCDCJz2dlsQu1kmR9M/Nsh3mfM61VXY5dW
+QZrv3xK96Jx9aRHKw5QWVmyOeNrIg2xLM50Qg0hNlaB7DNRKKHziZCwilQuv5N3ZYnZ3mwgNKwt
xDQdSADrUxlywM4wQ+ctzr2tofyQ8zSDtkMghBycyGwaMBVu3UQUGAg5T1cNjohv+IZOBWVPmYIr
2nA/zqW0kG4j9dDX1K0mP5z69dbyZBzzES35vZK+kyBIwqTHi2MGBUaAyTdxaL3gKsklyjcKpYqH
PgS5+oMQnMgV/979JP0v5MBCL4rkFMCQ1B+iPVOeoNfLOzGvzYXF+2OyuNT9u26Xbl9zxDoZgl5c
AHAPuRscaDdIQW3xmRmSEfVtsmTHRqTDbbZH2Hy0DRAJ7Vi/tbxRqmyU5NdqIcpOH+CxlSZIg/kK
/4bYrd+3Q+/q+LNo+xNT/U4rm4mIPVfDBnu+POUWjD3jamfWYYtdvkNnFsFgdckjCoCaeIkmIf6a
KHQ8Dz8LfCwBTi0P3oCfstYN7Mnkmntadk3ViS2X/ew85G7H/wl1k1Oefuuf37mifFosr2KZt0cs
z4fzEbkxqTdPMpnKFZIUr+C0RIjcZHWcpYGsTHP8SlYZ9bwKZvn5B7oQoGARywfRYhrxXye6ai+z
Ul1N24RlZKnFwL9XmnxCRdiCuifILeQj6yJy3/Sl5ejcs0ul/PyjtwZ/h8RzlhSfftvdsJ3iUqbO
fWi4leMyFpJ1GAWCSSpB8+o94LSWR5oW1+1HHTpWOLc0kY/cehuBn+bGZ4qbJNlXp2XqFtZjBr5G
3PnBYy8KqX57CIqaNGZFTZXYnCekzw2Pet4tp1VgsXI9A5UqjS4G2OvTGJCGKExF2gXNbHLSfi7P
NPat1uySwOUSlvvhNZ9qCLV59NOQ3soLKPCW1LNacFxUECSuWnPu5O5HiRhVt7fFn2qkhlVdECZQ
ViR9tvaCYGOtrInxl+svb3F3/ssJ2GXeUrLAVm4VxT1GELJ+CJUExIBAdshRmZ9Mwn16zsMDdhDU
h8ADLB1blYZMVAJfidowiH2qNXHyya4pfAlm94AOXoIM2VOiSkt9zLEQweZsWQnRUhITkyDALY8C
N3qlgiXfCwfW2dNicqyZVK/nP4BjlCDTaOhVC3mQuq9LixSnE6gWgMroM2pjnPAVmi8ff+YcKtJg
WJ+rtblhHcGJF/mQKjFBcx8GYl/DmMbmqRdKJ3i9t8BOY1wDFALPKWDlmfHuLx3KDxDJDgKwpREr
heCmDrlWc1i5pI8Qfd073nK1gqQznZ5B0TvIK0+fmCmsZWJmBtWC+Z1GwOr82frk3jfgUQ0kCSIK
26GOGh5jaVhRejgvj3EnkGWV+3c5GcI8+ggLG30z4hAd7xqk421t8S7qQYcaJd7bSE3nlqH8z4bZ
srm/QygnXutAZyqlP+D8ef0VBoygHp56ijz2JnOHYzr8NIJctAZ1Tzb4WuBD4vrkK/zF+jNHrZCC
Hpcx36qM+dQgOf+KaDzCzxn1FLXLc4TYxna96W49esKuqAWE1ptyPHng69BZjwJ3wNA9IeizYnPp
vPhvtQygTJ6iAmgp/Kidc5mUWsChIDeeRo43Wc2Ng18iu+5Sm+ZkiLTRX5LFYL/fJ7WSrIiUBO8s
AZdn+NFyI5ZkwEijH7wP6Iln/Zr1X9+xGirA3S8eAe0iqvxwrdxxgYfq07AmQq6JQ+YL7b/vDGzj
YBEkNfcbAsKqiPnyUO344bSsW2UD4eWAkCm5KK8fw7YZPnEvIolRQ9M/P0wmIBLU4WffUUYoug8I
ARaKYz4xFZzL8UFJOFeM7j3yswdBpIDN7BAb1y27T9J0PRrTS777rzaJgSeiRuDi0vVyo8pTy0Jx
MazHDywwVpL5qC5WZGeb751ncgbq0JIh6wkEACx/pmrQzazMxwK1UzV6KZrvWlIcUjNjBAVWIZsO
obBbpRrsaR6NV2paw5Zlk4IvUW0YdWlo8VMWGjPAxsgywFW99OlcpsDGY3yVdMB2iJY1tDJLaLLA
qR7Wbr+LLOr5aXwtLOekM6dbf191Eup6Rw1Shz4hfAwv/PmdSJ75okTKylUPw2e9+r6+IkuJzVka
jF1GKIjRDbEP/UNNRsi5RoIZM97BiOz3L2TWOVuMA8OTmiIcstZ1XGODr8Hj+tyVC8LpM3KQBP5f
oaFEN4ayG8Txshg9bdRvrb63OReo/hJQd1ZFI31V/aZfY8+/577j05MCA/6lTZBTUIhIQhwDN+86
ufmBhd1oPVZOUf1XhPTKxVq4F0GmkUngBpmYWK0L+h2XNlqlmF18HPGQVmcDR1Bhdj+F8W/L20kp
Zy+hqn9tb3JCu2UwBInS63Gyd/6zr+s8WOUWoRPSL234rYjVJ96jd+2cOx6dfZZXCFTAHduMFx8N
lIScFTGoG+yOV/igasrsk/Iz1r8Xz3Zy8TcbMacemSHZXoeA9rHbK2rvkYJfnyp8gR744LIi5ixx
x5KGcQk5C7Aas+4cCaiz1M3ykmLCeOY+QRbcvJR5WhFHfSCGj76yh/d5fqctbP1bjO2fyaZtyqOY
tlxmNyP4zXOLLm22wAce8FKlLZLJRT3GJikLFK7LaONX9Eg0jd1eUOeyvD1O7tHvwPBuILKjSggt
RCUD2EYnlsUYTOknMHhBKm00ZlxdeYceuGsyhT9AaqhzmlnbGzKjOkKp5CC8WjRYGR8Qfw3iU/Xq
MhM4iP7UUWahZOGBzTPfOvIbrTaVF64Vw/vQN0U6rTCpwPV5IpMKwhen5e9qPu3DuzSlEi+c3bXY
bWt+SjsTFMmji0yaSPcfm0X8f1DpMzBeCOHN2KsiLDA/OCkY8wH0DvCWHA/HuncWAWy+hNKjEDQ/
VHY608ERZlwE3veCn/q12WWCRZJ0OmQmomB2ax2M4q+Wi1piBdhknE1s8B7T9WYmacInicYEWcoY
rPy4PsojjISl1gwyuk40hzP46SwB/rlSBFVpuSvJjU1FuZqCBWA5OMZfb5g8d/DerI7zJt4vI59Q
GvAXtzaRhAMkhTxTGQf4UPRmt/lzlBYVE6hSanbRBTCEACw/lDPYTCIFWCiQOTdyhL3lxVU3Z0bV
vdMQ7ZnoXRcJuTQgoa+2RJfLuF2iTGjLXOgWE0SOBzyJfj2aSIDUvSpE7zSDRMHTA840hQGcJGx1
Lw3qIuuMz5Ux5igYXn0Ruo/ae5eU7Z4Uy2/+qFSeyHM2gIkc4Z1IMucOvw0WidtReIxxR+V0CitX
62qdkiK/sJYJCI9mcozpoVSX+tJQUX0NKqo9xJ6OhSvqt5B64Gp161EnwQSbTRGCPLsL08m31XZk
QwEP8vWxgHzpUifDXlaLzWbvqDJqAK5z27TKJIs6anA5PFwx6+fmodyUujLHdW8Fz1d+PdemTiZY
/F+DOI2TyRKcS41ariQg2TZE767dmvV1JsnrK1brUq/cjT5G0N71H2ZETAAYeIDbb9tHO8/BdbdO
knlCMjpZgc+YEm5YIEjyAxu/9yYc+lLpKX+LgbYwlEr89+wC/wrtK3H1aeQhf8lvlGaVJx8Zl5TS
MLV2HF+KhCbW94LuKMarH9IV9HXRDhzYuEwppSC+OJDTMxmo2h6FQFEFOnrvuvq+SUXN1o2bVigy
WSeA4FRqbswL9E9blk+GzPCEJaHHi0KVpv82T3/2bCQMuwj+sVjsLhu/F/eudfwbF8mYutAl9Ujq
t++OtJ7mNBwwpGoqpxk4jOXSAP+Z1JLpvZepoRHQbSXBRIGhnkxSbeNIqhKZjc1lRsosjFiipk8G
z/i28M59FlOrdjN7Pi+UfDj5oGkEk5nnlw0X2tXa6dU+VjTjlJvkEfgmNR4jVH5mg7OSxIEnmKBt
Z2vDuIJlB4I2hpihqw6YzUDpuVXFIVaw3XF+FGOQLLsmxyl5WZ3mj0eiwLbUMJ5ViebaGFSi5oye
D9ZSQLYbgjLhOipYS2zHDtRlKNnhsqAwhVvdKehzA6NTXusMsuXtMIW0KlrF67hhvM/04ltCui/D
KYNDAHXa0V9CQxhabqH0CWFhQJ73Y0cc0s9b79vA98rrmLiAMIo8rHrVcrdQCroi0X/WxSNLC3Ej
iTflRdTWYisXv3ZQznarGahPfssDf3TFs5GEQK8bPrA+KCCzfFuh9TfifIryla9up+fCq25KpY1k
q25iUy2HyJaiGRqeVU8WzmL5s6m1g3jAfikwKrmymSdEXOdvnGQgAhkfXDwQZ1bBYC0w4zi+oyVH
iTA7kU62SYXv4URvn4Ef9t6UXhDliWu/NyDmcryn71Hpa7Z3PORrHMbXUiZnjJj0y8mqd6DTZhu/
r0kE71wcffPLYhZ4kne1wjyfhK9/2Tt4yCffRdeTE7+get96a5eE54F49noN2CIX4mZPvU4zeUsi
FPHaap21WhjUndEEzmgR65Te32kQG+XQ4LVBsPud1gFW9hx6L0aRNE8abHhSdGYni78bKPHvaElX
tZYkOWR4wQvSv7Xd5vD/hOnwWI2VDhBdZgsv6ZkwXhkFHoZqxcqVAWAs7uomj1f6an/CXljwWWC5
UiXyvZF+m+8fqx9AynrTi4enfxuweaUKUvDTvaYTp4IOTfJbUT2drZeUazXTUh5Bog3lxMNadWj1
LajeTpmvRlStdcXBQjfKdMWChYwofwQ53zGb7Ch4O8C4gnYkBexVEEhcJw2TBnPhItXGsVsjqTE6
HaN9Ud61zvepVyWDdD1awnYOAr5VicJpuPIJ/fXEn/zdY2Xv5ZTnC21RfTR8/rgjUMEpXjFygJ5s
W3B1VvR5djMuJTVjKVKpQGqh0TUPCjXCMFbxgq9XUkl6FPyBcTnqWkhzknFkvdNuqwSyKOADsP9Y
Gj/1Br1sFxXr8Z2XmO9p9lFz75H8qew72fnRanluLOsITaJxLj3O41BJqi2qbEXH8mZm0q4zgMWT
0ylMwooaV3K+dgsPdbtbqM8/OMec6+tiJZbr5yG3UVc4fOBLZeH8VI9gSeNKC7Ai7fe3w8sp7qmK
KHXKgF3+lNrHFkRVotlnTf6ZX8dxO8NLPx1UuKarDUyeOI3yb7FCN5eVO+9E88l78LDjUJhAuxbZ
B0H+ZY2FAD2tidc4nPK+1VNiP6+99uxhd3fVZ0Qfbidh7+gZRbrmpm+fXaqHQ5vGmc8nRE1B8kQI
z7nYvHkxnQzi2qtIkMr3981kN9F4Dmc9yUpmn0PodxSSYxk8KFTTs9AtC3EdYL6bFOvbLj1XobVD
HJYJpNJf01rI8Qj/vaIxJKthT0ZADSwoZ9aqTGvao9OltnBjQSGiDSm7JULQ+SFcD885SBlLU1Jf
KZeQMeNXOZgXdP0TBnScY70OrUOxyDqf5k/tXtgTQY+cPkcOo19j6mQBwu6sbGzdBSy33TshOAQA
mRDATg/PgdvUVUjAIUmw+MupVi5pWo2PkHjHh9BM+HF+tfdSEBsl5BEafmu/BkJp+zAhuuovA6Fk
fu9VOcVkhfLXSKw/2at3hCMJxnp1J6TphvNXONpGGwPUGckyrsrMJCF+Ea2ntGCU+Dj1La8zDJn6
ExUcL8BmkkfdAAzBNVoDXCgCbu/NrekgnEq2hJsY494gRWpIyBBLn6qf5mImlZ8I2EzrXafbNWIO
D6tsK/wnpH01F+sOu7VIXYiGkVTKsR/XypLH4TnBwYrYVy/Gbg+fbVwxFHYwsFDARwqhdY2rc6fy
UahTJOZqVa8CbAGH2AZFFtVx+o8eisxQJiSTltJDcA8gJ3gv4gtTr80Ol5BjBIGmYTX+TH51a9PR
TljPUnOG6EbOk0kcKe3SjForij57ORfdPa/RbLD/gqCHYOdfVpvfHCgQIAlqx327Mv0F1EVg6gLw
eydFe9KMrCdCCICnBKFgsaKUiPhMaC8Ea/rGiPEQ2qpN9nOFMJjX9+IdzVsHngLWFTzHfQNeR5pV
JQ7emU+2AWFmwuSJ0GztFquxFe4HOTuNkwT4BwPNb4lLmddygc8LqMgZ3Rj7UIKLmpSj6EiRMixh
wiECmAfZaLTFpRKaADPt8dewf/S0zVGQlooa+TWwW84YOj20InIE9NI008ztaWaAUzmlddSsCoPS
86hPnped0lRz+5Rkh2kb5Pb1Cs59eRXD4Is3xhDsXbCJeDHzBJyhMeNYfh41qp78QBEba03gZy9Y
BNMX4MJJW8YNSF651xfIKTl/h4KQ2mK/QnS13y0+RaO62ReV+TRJd00G6bGkMC6InXklA4uJiHj1
pyM4VjjIy9d3sum6tpDavmtP7CNR+IXAh9BV6BYjgRTxW/u8ONfsPxVxelv4ugjdrUr3QL4631y6
wxL7Kfoycd4iSpHbZKFHFCsSnb/jPKM8GDy7z4UNldvAKPnNf2meJC0BsPT0ISkV40J/gz/WTIcl
om4iD4GBVYd1x/Q82zAv+/pwpXDlVCIl4dIb1qZoUIKgJGBVQNVFPI3S+4vdP4z5zRylZSZk6+kJ
vtdpFe1SzFD+ewAF6YDJYlHAqaF4H26jXliB3eU5mCHY76OWwkRmrSWxAebscSzyabpJkiZFRODc
ZtUDbMiC+XtAdDSgcSIwE3uZJC9bb5SpXOGQPQ7rhJXxh9d1ijnsNBxMGRO8mKKC6DEy+Ka+h3UG
qjvmszZrQiKYir769ruu46sv9CxA+OeX1H4BD6pA8XQFJwzSh+yTWPcWJweBTYarWD3gK7IM2wOj
RfyynEJXsBWzm8D0/gGipKWYINzwfIkShMgszioT9gQKpKnCkxuSkJVhX+KYEa/aK/1/SPXpoNZ1
IdCgwrn+cfmz58nM3qaN+8qz1ipWQT9q/UqlyeLBqUKu+3P2JDgJpOJgwOxGJsUR2cH3bSzmnDma
+lMEIO1Afb0xHN3zB9p/OAnQwXb7d5sas6G/7PwenXkeLjBf/jlo/ubOi0PeFYAXchWPWYApQ2qO
pOGjsyM4/twNPk+soLRlL8xSSaMu0xtbubiJ9TRV1SkO3UkE4HuEfteWgQZ7fhdJtrhoMrvHMVq9
vRaPBI69M3F6oWb9ScmbcuakrTXqiCcg3ONHKiuXvEifJRIs3EI9qnlOOa+OWJak85oSM8SVD3wQ
SPqa1CQStKNLxZooe6akKOw/9W+WujHj+Ik2TyLR+smwSACqkPXxZFe6dU+aoJ3GiWiW73GE9oJO
dwEoLVqcvNwOkfLJa1DAx4VwI8D1jYoxYih4YY8JDOlPtVgFHo9PIHd2TTxrn3D1N/2yL3XQM0bL
uiBus+oKgKB1Gk5uKhoWwi6IfkjFLM/cT+B1K/aZJgPKOEDmLkzssRvlIW9o7qzmtJqZEYCv7LXN
E83RXBsbdMgi6wTEzbSZAJzWWwm35Yqb7Kl42LHC9WfCRvKu495ZFPRQbo8iJTNFOIv8cNnw5dqt
R6quTKfDxuaBwmat0Vj3wS1jlk0i8cAZMCzvjSGPeclACWivjv1zSCvGfkuVt0MlXqyxCIdyip7b
FbjeSJyBOhds/osB5hSCQgrzMUwjubN4eK0smWEaFM1XhPbZjGVc3DpYX3Nkx68l9t0jOFsKy4Nd
1JDCWSnJw2MUf20iuAEdYoWbOGotZf3cwkuwSjieMHSkLfTS52VODDFZrSzwQMaks7FPV2amComI
6HVXZjEYhfDYw/5NUrfC7dDdkPre3LLaV5MyPM/9rfUIbkguYOGGg1QF6hON9e678VWUXngWXdBq
/H8KATDNTh7GaixUtIpvRgPr9Npayo2otn1BU3wRbKM5QiqlvExWhXRxkFi7xDPNQthWaiI+HUwy
qpaICxCFeznuQYImDJICnMetzz3HfXTlAZwPhTfgUKDJbO5PYP3A2ZcoS+r/vVtAhwMD/Bcl8HJP
ym3IieNekW0+kC42li0Dx6wUDKivVGfxm1n3r6MqCeCOzABgPsPbsaH7Eqj+r0NY5q9J05PM7tqd
Q1Rw3I5+KKgT9g1tefsNjHf+mT/BurpMhrBsc6uL1lFs/9SrBatZkbJscnqRWfdC4PzSJLLOZAU1
cqc1dagOB7r0zq92uXuomM9hYiOdLi9TZclPfhDpi2bvbjg3kRviaZ6bsdHp4l9w78QZ69jfvveP
XevsREJdZHfk1oYQ2L5tlrQHz3elvENcYJZbjqDE8ehkGbgGcyDTBge6xyzQ79CCQMosaNh9coYx
CqVZxHqaMn7q0BCAJ91JcBQYgsNREdn3EATXGIT8Wafj32owb5TnJvJjG1DSfRN0IUH3c8pH3xlX
yVXQSGUwppdEwRuHsx9fuT/FOKBz8P9hGwdGpGqWTxq/f/SiAUAiBkhUzpHWyOC2ZBM2ASGGFClg
1viPmcCK3MappKg4LitjmscpXFZDOEdnpsDUfFzBG3+YssQPCMrYePivSg7FgfTYVY2Y69qVNeiC
gMz7j6LG0eGGJ11EOB2UwTWX1jMImI74yDqoyYuJjdPwAjiukM2NiANbOt1wx9PYCKJ6P5XA+hBY
5fCqp8xCcRrGan1tN7BXT24PdDZVwy3peGEjRxdXIFpgwd0s4bq23lXCa8I5hrs9MJqoqV0KNwXu
q1nNmdUWIM9XWzSYN+zuRaRO26egio+SQuENxU3o3YhrSO7AKgwPveuHm0FGNwKZyu3VVGGMyzki
+pE+YiUI/FeZeC14hiOvI3amhUqm1+oMQGVxYHvNTa7uw6yKovv2qSXMkAO90XuXvl+A2pLmzG2p
8XkLmeRWHPcWcK7nr0Wkuy5Gp0qmDAPoJkX+vejCR44/aZVa8FLZxC1R+u2H0rWPLJIvxh/F+Z6B
CFTuTIxmeSX7gl7zmXLM3ff3SBkawBivhTyx0PPeaN3ipvstljQc0MM2t47t/BDnYdTg7GfA3FH4
rVMIIahQWZSqb31u5HAGlhbHZYnhQ8BwK9E/gbUSkwfySnnv2c30DX/kdweTvKaq0/5DglAdfQ27
khfK2+0Qqv9lb23jiGrNv8RupacyLfeOqwPy6WXQlmN/tpOPDfkY0mvcsPjEFmZTveAyo+YlaDmp
u5vlh7/JwuVFQwEN3d+JkDR8Od78B01JZteT+30db5sUHFtlRihttT2uDfFSyyME0d3qCzNHU3Tx
yI58KSOnwjryYyMSUUC1egIWcNP5ww6TLpsL/9rOsmW2+e8M3ulas6CXLSV3EH9YQOrsKNdh6kYQ
6DnpEsQRnFadRSgMAt+3f5zvsPs+fjBIE8UbVjIu1qgWry7xO7uhDufV6LxEbeInmDoSR5vqc+Tx
Bcr2uMFQ86G20XMCvr+J9I6ZEMJk7yKGDn29gYyf/r36rfu82qVd8di/PjUZQ0TUGzJ9V2cey2nx
2UCXr+UiOSld6erX/uL2G47wHQ9fjNmkLh6DCIvI5Y1jCzD0t9nSzjgfrE6jC053rGF6AW7DwHeV
VlP0zBmSOZyc77YnmxXxM81gbhDHM54s6HzmdTkM0sMo9UOArku6N0MX5gS0rKOFl2jEfAuGCwZ1
1kRGzzQKPaUZs5ok6+xTstHWg+91Ssg7qKV0+h/nfE13qaUI/W52Bn+M0jqXSDLKNhAUITKkfjn+
vTkM9pDiJ85O6slqdAXEWByCN7V7v03ZJG2MtfBU3NbCUaGOxWY5tSgqGvhNBFFAd5tvVuN4LkMp
NpLB96WC4z8esj4XZjaWv2mPHS2WjZuYlXJd/uRdZ//53hzbdffx6wv7sfiRmcJwYfLjWGYWpo8d
rmlLtmHNzzATWuxNgvNQRYPmRiNfTBC7MN/+Cz0G9G8J9E4weA8B+kjTZEDkOZUmJdUJCUyIzHIB
1p7vz4IkW74t+ARU/X/E3kNRS+5ElW8NhTXYazDf8CC5YD2tSospuFhez/8YV05HHeT+EUelWUrT
jGK7nTv6Pr5aFPn/LkC8yDpchKqupbDb0mVYTEzz7i0nkSJIUOehl2ibMQNIIrX/Hpi9wttmV0To
lnrONmUc3iLo4JJziJmY3H+GDLaZutDTziNxQXcP54gJ3RKrJ/BhLLreLbj/YmK8s6+/S5hOVUB2
SdH1AsaVK3V4tCCsUMcpux9WGkwMKZXVj3hjPx7BuTTH+nTsJJv+OUYknJYNOS8q1bMD0x0fy/KN
fyRr0imc8COaVWBOuTm0LYh2l5KSiZxTwKmOvMFjKctiJJaVpikg5TnBZNLkwqsE4LuQBQ7dYexU
6FcncUWMnfvbocfcAAbX6bFq9LEdEWOaffxbUlNfXlb3iAkWPpzw2/HMHQVAAEb9hrT19LiENUN+
QX4kfndqrMiD4rM0bJ1oIq6SyUNMYLOa349O+oIV2I1sNtKkTWtAKehvdZxQSNB23+3ATTF7bhY1
zRy4v6st0h+5LjwCAxmiSm25zW9TWvxzOu7pBwaqQwuGK8PxvdvY8HBbaKYGaADlDP6SxOaKThgB
e9Ip1zEWckJR10lH7RlejwZrd8++D3uAhRvQzUGWHRLCeKbtZ9IDL4OmAoIv7MworZ+KxLKxX08a
TQSCd3wtt6QtkgzJDbhtCnzYZHUUKsSRArIZVSntcPUV/UPN4pavSirggLyAobn+CWRbW3hvNOSt
Nhb+e5ZQecoQ6xrEgpR1/kNo3Q6hqW8VzpSGv3P68w44WJRhN235gzV+h+48+Kl36/j901/mfGfz
d1rqkcotHFB6GaJTR2BEYi3Fxzb6qsOqjY35HjwFtKKhnaY0u6Zc1Zb39dJFqofPaNwHyb88xOGV
Ar3HaoizsfN6iViUyztSZ/vPYjnzdVwDbvTcy8H6qN2LNFGzMIWBhCqdFVp3oqSQXjwb0+ec7VSm
PM9zwlfxQwrpvJF6qXjb5HSIbyRozkpgU6isihym6k3Ry4DoRWt3/vYSej3ntp1f064I4+Xf1R4b
mnpLPILToTPW2Xz90o7se9gcMuSmni0j2fCdTsdReyQXygW5XvN3URNcG5Sfrrv+WlwiwrSY7qlH
cC4nTsXjV1W8PaM08LBKBBFsYbhWoEv/4VwYnDSvITjzE9W6aLkSpCt1UI9OcbzMeSQgYqyV8d3Y
P4xtgosbYdJY6czLVTskiA5+ZgnqZtnvtYXoWA049Rwy8XEbvHyxwnSyURHcusmuxAA66INg2HAC
5OnBAYH27YITS1/sY3auvxgnRm54wrDRu8qXN9VRw3UgIqpJFqspkngzSzHgqLFnatzMU6dcPWYm
2gpA55TwQpiXZJnl1hLnu0TgxnRqdXA8jUAct3a5Ap8Iuiihlzii7k8hAoOnHdU1tsV/Jr2TXJMV
8HHgNkoSXe+vdxAnngAvFXHKjCDQVJHvdXAopuSu9H89Tvl3oZr7myEuNusJBRqKHEyXbqjzUpte
J3vTsKjz93xpstEqdUMoZ7kaQCJVOeGzTqGHwQDrI+ssvknomG04fk5jZzEf+IJwRxliyG+ykSrn
TodBxe8VP5Vx9fGZpBxgnJ/6Ogwy9r/vNDMhexazehl3jeC50TdOFsEV3dlMJpoS5CmzHpxrt17O
Si0px+rxHQwVF6sDodAZ/ojfmRbuPcj4odnxA8EAeaGgAUGq4tD8XoZpwPje9bNWiy8ud8GFAQLI
oQCo/Ph9ByGY08conz5T46CqT8fkw2aP/82uDCcHyBxY2+j7vv47PIpQ6Offbvg1u0DufacN0lih
VahO8DoTx3ziPIftr9TPCigCYCfWf/dV770UPaeHkepAMgJUo2mHHJmHWw59+2a221LkwlL2u0D7
fGE2ZSBrj5ZlaM+d272Stj5g7uMWZ4jzS01Vaixg6qX5i3KJ4wPrp7IgF/L3qBxwOqnvwb0BOIzL
KDULnryDyoD3YRPNP/W/tPygzTAKDQskQamhxR37/YWAxiPzO7UrLJDTed0WEaeaVmDZEjhz6rCm
OAmglTs/A8x88jgtd0Bjdxps/hz5aVF3QrT7+a5WjlAYY636h06VLw/5mENDrjgGqjcjKDjYJErI
F6H6Zu8awrbyjVIp1rmWL6nEGzh1NbChTLdpqKhh1zFrcsZQ3k8zlPoUZJPksp+snw0IN8xvGeG8
d/Yq6f4hACQlFe/9C2t6A3tMFGURsUj3aVN9TF1J/caU3YjtAFUl/rCPjhoF6xGtZOixeA2gYaA6
tklT1f98Z+kq2NdRmUpUo26wzArCyQ7jxAnWoCpH1uQz8xneojAyjgyvMQxH+H/BykxsQ1ii0H0q
9yInHFG+ctjyONPhB9nnmOLiOEp1vaGLfslIbJJEAwkKk/DL844w+8XRRVoaI+Yv1BNDjwYQz6ow
uw540q5zucrdCo/cfcD3pOkc67+FSWiHXusbN7FB4Kc69eaIGHpcWD6pPmG/l6F1Madmzpj1O/h+
nqeHevK3UqvqzNXhI5NZDEwzcaaSXgBk7zP3czoQXdUbkyVbvMjXz5I3UtJe8O3K6GsqsJYhVcIu
3hTiwI+rkpkZgCqJcAvOEOWOpTc/BsIFEG379PNecan9Q4Jl+wYdPKbWlBcHauqKSnzRueM9KeEl
9GW26j0vrDPz7W9JkoQLlxCX3XshJtHezqWpU8ymz4L/ZeKd/lF9LF/jOtdxf/zXCdkDerM/fBXD
Za1adsH2kKqf/23IwovODMRpVa0SoLoqNv18X06Ka5ADmfcO38gBJxVZGZtRcf2cpDWLSLbJfLcz
ROvAQZUv6pxGG11C2iylKlSltwblncKoXj/rXi74X/SfbbdnnAQObeL+QVhaJxtDQl81caKdJUeL
/qzAY04+O0K05NGcNO0kU8BrwuCrVoUMh2WetkxDR15S2HXtVWeTrRwfGDrKdps98HsZ58i08/Ot
NFhSqeQYsQCZiO5Vcsuj28Xbfiz9jVmJJXinZOMyY8H4o6REoLgzPZfZsb1cfPFNKQ1u7s80GoVd
hnwRJmlOxqGR8p04Efx5nzddQVNh0zUtqzlYW0oACKXcKgulLF04Di3KBg/EG8+Cs4o+mCFvdAGW
I2xwiMFueGOqJLdwArQwHU0esrQCOm4qzZTxtMzg/nlMPvTwdiQUaEsI7hWTNikRBnwhfKLHKbs7
ewuphK3DQQ4MPh4HQjznnUPjlEk3N0xaH6knpiFRdHJal82aXFuyBkoJgdnEuVHzgrqa8tVtVpDL
gTPgjjq0tl4rv6L7tJJHx6idJGGqEYMdd9jkTE2MAWXKkcZHrDBnJ8QVP0KUdkS7yriF8FQ+zhh6
3AFn/oWLAzpZofVZ7u4lEHzNtsmsbZmHAVKOBPzYxKOPxDL+DbX3tB6BRgVC50fjm5wQAig0W0d1
1c1nXVBCivv+DpE5gVvyMzhVFNrdZyBJjQgl++ZE5w1H3uNVcYQ2JLCve7NMomyBlh/hojgPrRrQ
O+yKSCbQ+4FFTa9XAMue78T9H6NyB0orJKtqfcZmjqoWaiMgdpiy60Ntc6MgWgPYgXyd2kV+WUVv
nJQRIWM0xrG+x8rRgiNw9xDPo0g/UwcG1Wg2mWWEM7zV663XYHKrwatuc6omNvV4yOFnk0hgxZvG
6W4AgCOMxsnybtE3twxfF933lFdmgobX+qYmKNIMsIlzv0EunimE+ssREfStA2tz/vgac0GJMVGq
M2LRtKrTrrJu8Aa37WgAXPXB9hVKQCfFwOdP6hx850bamkWXoh+0+f2Zb1Jr2ZtBDcKt737x3v0f
RYWy27YI9Gghruy0VDA1l0N3lCKAQXLj/zufePdlGwD+3n2ogsztLvCV++nbFeC3hAwphodgMFj1
mlrjLG7QIs+FCR5LSebmkKEQkUYHgBNA80omgyKyCUUoUGINN6xUe5kDB6dszqtTLKvCGaFt81cS
Gje/zGzLcdKoprsjVaSIcRV5R9l0R1eS0geKsjc27kEmKHD3G78JdCektFo5gWl9H0Vt2KjOGrJf
J/5MTF4mqa9iRHxs3EftobBZv1syILwU16UJubWMUNUw1q9YoWpMkoL6ZTPM9XxEXeCkAyBllcAx
crULHVftM1KX0amApVcDYCA+8x/NZYM7sjJrorIF9gKbfKLtmjlGKGjU8OiFAooDU1PULiO38hUI
9LZgzAJHcQf9JpoB296yZScMML0Uu4K+ntclIH2bbWq4VuhPdiebms8kkPcVX11/2vkAdf40pS9W
cl6nXVk3S+LZ0ygUjHJRqqUFOalhA8lTxiyoPFz8cpzvH2jHT5a4VqkO+Gzix2CUjymzTeLrvqlc
z7NkzLvcoNy7IqW6j9xqyRFP0eeORlNRqTOvviU4v4xw8AIWoBJctrhpDi/z2NoTA99nT2iNiepe
esiYGauawbEBOVGeYnjqpX4mdLfoxGpqNg5BkhUOFyznNslrnjaeubeDkD6NOIXhS+rxD0XJdUJC
ZjDuPlYbtwS8kGIb8UETQv8p1Z8RE3m+ZtLx8Ul7CaqWGL1mi+U78ssuC48iAXS5k9/d+k9EQmP/
+pGlv1ASg2yimmCEjK/Sj8dn7DohMadIxSFO4ZbVzzVaEjKq7YhYNbn1aK2sxSqWvEdSsoiCGWGz
AolKkhzV30mQDn5Ont1geQd1y9JVzlF1midB9+MsBxaTdilVpymaX8J993nM9ZpgYgPkSOIJSx4o
T/HDH2Bg1dNOJlWdglAoZxFWkCXCTjQn+o4vX1L3e1t2ALRd2pmgStDR4U7kcce5+CdhVPbySDs7
nfGJeV/LVyQqIw2eR9J44G4RbgvIuQnDn/am4vjDJVsaM8GZUO4RTSc6k60UMPee+1yMNFzZekhc
5uD/TMqeeXKvXUyoEio0d++quRzAs9SSzQoYRfh2sHfDnTiAezXQE9cBbwzjOSuwx5WwgLG8Rh5G
RJ02z9hCuq5eMcWnxN9FGNgimuTx6iTJGsiTKJivjg8Lf9kx0bpiICiZ2F+j3yjRw7S0Hy+fEVX4
ukcNU9yZ0cmof5esAHPX5uZaHSfE5GuLnmVCOxseqR2n0luihE+lHZlDJlqervPBom/Lmi97cPZ3
AyaVayGe0G4funQMyk6bHqJ+YYBFxB3J7ffMSQDg1PLB3Ea9LXBQfNy2kgSMdyOJrhF+1nm+8Mv5
ty9F9/sIXsd1qPfdUdJhDf0lvZjXh+YWclr9d40vD2A6iISWX8hYiYjBoRQOsS30Yv04uOiEPwV+
ACNlSrlde6aGL0XGPaVkS7hbZ8mLJI4OuvOsOsxYlJRmjL/b4Lr/6ejgSH0KR18JiRRrz/3UIiMk
ir5VATMMCNXLYqgrZtqOMNxg9O+1Sd3jwFIT9zJGNsLYdc5w4IjNifj0Jev+zS3/2y3kpJHbWkai
n0qLL+pblG8y4KEXDZ8Qoy7FYiYM1qytFggwzfTW4OFnwQtFNVCDE+q201jzjF167si3IBK7aXXp
uOlYvZ8YsbtFuEclwfmD09l6VZ8F5/+toDbBtCi+I0AeCsvLszuBNkOt1OOWlv8gN7gT4oARDJIl
RzBmqVwFlof4B7aPGpDYDMX+SvrlCTkatJe8unhTGIO4T++ifetq8MX/xzO4JMIycSkSE+s8/LTF
NFqujYpD9MolOyjB1rPjA53ATcJXw41MwZlHegD334gM1gflNMwsyH2BcgFcL8EGOcmjxl/HsnyG
Oe+/oHnLQVJCAKNQzzjkj4j9HmgCts4mvcUAE5yErPOAb5sMjqEtzM5Ik02OKHYgLS2xUKFQGBlx
gZSaYBOSeGl8CZAjPB+Vl3ufHygtvfpG8cJIs9RZP7+cS458KRzb/r9fnkpnPLh07Dr6BQT/ZQWV
3BRUfD+SfOYmk48BPkumLOgjruGvEas/2HboGdmIgBzJQ+E9rB7fB+/zXXEbxp8Pb/MehmKpeUOx
z1zmgBOLwA8ie+TuBfWByN6SGdDVLAqIJgsHro4zSyQ+Ca2gkBVdAji631JgKKf/ClKQ2I2nxX73
qu/UI+TDU03ReeNIrhsiatHpdSzUAEl+6ks549Vb2VyJw2uBTeHGkjF92yvcaGHOOPgbfHfiExdk
i0cJAl0cm6f1rineV9AbCXSpDy/kWCg/du6DdrxJQJGLiS7wrC1QZkCbGyYCoRNliZrTKOrWnqBB
lmL/xiBtcDfU5TweKbD2JAeRt6kwX1zbFKN2SQsQMzm196Ud+kNhKWlwhsDqttTUftA0vjaA2s1p
KOb+7pubHhjBzzflLOJjWd5eyZPV3q2faKYdci/QyQDWYDlF7PUtvGubMiUljRGwPcf5P1hsUybc
Gko5yFxdzbevE9yl2jxxQO0IhDZ7ksaPUNB6V9uYpbZhP4j7xQ8KbPx0FQbgCJLuo1eXhpQzjOBQ
AKyVr6pbSuuxOaU6ko/CJo7RlwcO4olChmIu1A2rXtt8vFsLkw7qhaQ8BAAW0wWSCN5s2sCJbnBx
TMV5JE86JEKj9UGkUg1qnm4H1Vk/b4F9yqbRGq2UXrrt4DOjSO9i/FzQKsMsowFQof3ADYvqXLHI
rxi7Kofxxk7/hhTjT01fQIXklvCR+1HMQjnvdt3DOAGQkxDtkS4Fauj+6uCrAv91xy+9zZgfvvYN
VabWy9iIjUNPHCVOnQsZYf9DPlUAWPYGAXnNSq6Sz+tA4ALtWAYk/8zE3KcLO91tnTccedT81lP5
b8yHjiZTH3t8T5MhGqnh+hceXMhhmsF6kjjwoOEFLD0P0GD+BL5XL4oJxJ1Cc0yB13DS995CNiXH
NIFZNzVIG45qGlMmnqfj/4XSE5khY3EK36p9x19Dj+wvoNeGAQlS09QR5PC/mIWPU9GZrNWsvdvf
/c9+7rm8iUHdvJEWwwjsxST6Ze3TpqO8VocoevcJrdGGStORRMphi5n3BIIz6v0Lxf3RE5ejo6ox
TZB0zj+cUpXsxYiDy6pPUN6BH/TVcjzkM4JqSvCAYI8m3fcuWI8Q/DzDQ1dEyuPfdAO6J/sPkcws
CXz50uSWAVIm2HMkxlBYkHjTTGTm7yOrZwFNDQwCQevO/oHM0JNXRRp64FnB8kz15WMGTM0E1O5r
D3E+k++Xvnugz8IfO8zxrQm1/rHnRmUQ9JQlOEmwAYDnoUIw8ozN/9BUyIg8IOtYc5N1F6ci9/iL
GnJRJ5q2I0cjdsKs3ExLdZyDNCjiTmG7ae9ezO5/U9d5WLGB6i0hjtmmfiUoem3xfpMWNMMw2Aye
zPrD2/1m0e6peOkM0AM41o7JUYTXSCO5UybqfZjGlvseXGFEZnCCx+2wqsAFqv2jBNouWum7WEGZ
gFwZPZKbnwRU0A2CYWDzNwdGkMpUZ2fheTEwloFhIzfkoiwCNcSb5RwRn7WZnNeRK4PnUUlh8Rd+
3am1e7oYj3yMSpP5dmvGPuF3iNs2H4F1c9nmeBd78K3midWm1LJ+ADZJ5b+gRpiYoh47qUAZQQ8v
sN32pndcORNT8FEck43lQON6PgsfHquwIHnSlcXOEOCeE6vO1l+Rsn4dw+KN6XPDvrABWdyu6n6S
IkaMoh/uk9xBXFYCbIeLhcyYtZP2/J7DSuIa9SIN7WwL0KxhLnPBGURRzhUluVSd+NCEe/OW8V+H
gXqj30mXcmN+ymTr7+Zu2XLH2wmDXOFnL9xsuhIu+yuc+HSswCh6n5pdLa15+WRT2k41zPUgYWYM
QXbjvvlA/gkVLzPzdEtB3aginftzm5PL1mi0AA1B3UzZHqjBtWawLme51EUbpeBTe5k0xI+WqdMo
wJFmf0eyyMXSMSn441FZT1T+mGNk+sudhdl+LwUr+0E76FA04QWdIiQPduOJhuVj/3+KeNeDOMdq
IQrZBdV1UY7oj7tV45m9MFuj8EBGjfDmz9msYIBcQTKrPlp4pDtAkkYcLa97vQjhXg9UIy+gMSwL
nk8FZxkvRjefxLpL6usFSU43P16nvu3PofeAGQbzNWBvf8UqkzvZtvqzIOC2fMN+iTJgJB1IR2y+
YiPWVJzPez/koXjRLJDpavdGvDXck3aK8osiOjTkdVH1q3GUqp8RM/LRM2d+A3BuVl8c0AcrOiQf
qco+WnN+YfV4fSJwE4nbb18z5UH7BmYrxKzAWlXmKeb+1CqLHGG8x6Q0Bojtzt0adClRTqugPxqO
jmIsXBzWysl89cDDxIwhhHoysXoq82BznOqlnlPdu1doRaus6nsw7XSkipPXuThS0c/3wGPV+kEO
rxmNaS5wKEqmIneyuerY/olznW3+nQTwBQC1X5qJ99P8YVsiqXfD9s8W96yJ9I4nlXsiwWJq/jtJ
UpkIvxU+gRowMJ+gqqpBh3bHDzryI4laOvqoL6RTqk1eCfVgoZU9sI7TcJ0UkstFmDMKiiJhFrir
9PsXnuZloW8xd1CGbliG7nJLODdFR6ohtlK8sOVmbF4OQ0A2CotMeTPAQkuW8/OxAxua5whdMpWa
RCYJ9leWKS+j1c0h/d5+raNd6HsxgX86RmRJ1pkwxh/5xtjoHqmBY9Sxox5KHroEY72O5PEIs6uA
FHqjCIJeYtiz+ZMYNZK/onW0fY8a+waerOBqHcb1nrpKPGuJ97iPz0QBiA3fkbFEu0xy05lD/iO2
Xf1ZXOpa6fGiL2mk4SxtHr/kfAUW8gBaud1iWmvdxHqcGbRNkvkhcGxIlFMumwGcIH0BKU5pDLXt
F1aS/rrTgqObmDN/p6gPJrlKdp2zU5insrYMuLYyEcIMpxgM0uaZmi7WJPID0EN550rSOLzJCXdh
IEplMiVnCGAhdk2BGu3pwiSXzIxFdkM1N+XBkZsHEuFg2ZTJzH6zhHOdhn7dUnygEM1k4u+74b/5
N+EvMo/bmOSalO7Rr0Q2W8NhOaqJrO1JEY8J04y+q1rlgWtYYLD4+3CeD+VIE1dyL+rAQ69onF0+
lpvT/vqVVjquGzBHmD2RnwgfjJqHl9xYnI/f3rNnaHv/XBrVkXW1dW8QLEqz10fDze5bhmM0l7EJ
Av+Ln5NGj5J/IIQTtfAUm4gVwmgr/+eCeKNnfmTA25C6WYcYUo02HMmEXHrvBw/kACwxbsa0SBZ9
gTicacPF/HiZKA8lF4G/5Bsd64tGR8lTR8yFwChY5xg5T5UDQW28v4d+VT6Y2EqLpHoIX3fiLOQv
u5FoUYLgKtrYhYgzwGVlTDI5SfquQM2p8HV7sNHbNYxSr8kWHTyTcyH5bYEPLDhYW2rBwCfzCPfj
zyM94MNIw8LLyvALIWec07j9G2QWxUtdOrMM9QIegG5Pp1vmbpIJpCcYyVG9z8wguTIGQl/rD+tV
p0xvwO09ZIAyBOarEe0gB3mvEOTiSRkxuaKNITK7eRH337LKGADaeHC9OuQI7MtAXVq8M7qeDbO4
BpXrYhgd/mYsiw+yki2870ix9zJeB9D8jJP2ybtc87vTCy055hv+GzfRQ43yEgonIi47xTSx1sK/
UC19AkoJUPx4+Q2+BjYaG6gQrEDTavAsw62bVxKTX9/Rm5xTEURjcTY0OLCwgvGMA0OyZy2fAyRj
qcApXWeXu6szLAcqYwQywsjRHaKji9OHIPyLQ2JrwIP63+Rh9WFU+yXOBrQshf8Lny1LazFmeRmw
aiQ6h6NObyIdkZeTX75MDaa5qgz19hV/IqIyKQ7o5WDVgs6fxGcjriDosJHvcKcz9/iWZo8RED0j
BrWnzKhGP8HKravAQ9eKLSzHrV6ygRheFI4NTnH0jn2tkVamDGVcEA7GnxMxn2DaQCwK6C6kdNIa
87AHT6hD8ER6q9rEynJXvOADISxp+QEu1r+qUc0i5JZ6nGctXm0CcKBRZT4G/V2W8LubfWSoUO5z
Cj/EgVTPOy8dhKGLMjOL32fdLh5KgU9L+JI2oRvLKJHgW9TYLHGStL0EDD7HijE8kE9+bdmXBLTS
VBhGjGDeLp9TFd5ufwjhdkaKp3bKJuFa5l60leN2WWO4Y8jFLFEbCmjyUVFO+Eo/cRAaqTC+01hd
DtlJ4uLWIh8ca+ZRUjnW3x1wPavLYn5sUA7za1jDZ8ITlzaixi5AedvTinO/naj9UFSrn2BAd8NX
GXQnVMFEmxcFXnCWpAbMqgXt8gePZm5fm/iqZXS1O5tscwQtOV0tf3ngsmXhNWGWFB5sngQ8MezW
K+MLY14Igin8vHWBk0CwrHgEauVs6ltXDWlP1ANBIb68MX2ALT7i7IESpo6w2Dc5/+Iep3RtnZp5
WcomFTAKL0zclTyRT/QPzJhW6+zY8Uf5k92jnix7wm/dK0tGZVGKFJZebv6FkFJtKc8H3RuZ05jU
f8IDNC1/SQSl9CsevViCcbHckyGB6RmG9PBiBJA8Kz5VjBNJe3pWoafDE0yAq1+C4sm8g6rRwSZx
rdZAr+aiNEOSqvzkmsRBbrBw1PNktB6Hm9ICCZq8VS2qIxvfusDfiBh5nYkLEnWWwXWVDzT7tDwo
yZe+H8ZTjvYLUoWZpaijNvkGR1F/YfmsWbhT7GDazronqUvvbHxQz8TcI3CWPiFaBSJA3vnf8CoA
XwbArV8+m1QgEo8ZVS9nOCXR4/vdNwv0l2dqB1IUhWeYzrTSTf9yz1TkAnDsP/NoY0UoUQDWSny5
jkRR4mXrqKahUI3qa9iLmcW+Mk6lxFglLNI+32i37zhSt3W6iJzeFIhsomriu3rK00kAFUECps82
3TDY9PxIwKZnD5lBGX0WK9zkoxtZzzspJ7GpUi489plaWuH14qKFg4ee65gRpxTxeu7P2CgvArXo
AYFz/CKvnHEF6hSjtubTDFIGT7N/xcZ4JwOhdLf5tk8u6hLXZcH0WeR5jVEhIxFjSxSkBfJMDoBW
GvI5CqJ3kgaZms91Z7hq2viznT37WRAKuVqkPueZWvyJ/ry33Kuz34di6X7m4FLdT0W4pM/Nby4M
EMWPzQyEkkWzyOCfrYf1o3NQQhTe2rFxOuTyopggjhyFHqSlQX/TJ5zleXPY+m0Bhomll1TnIvma
u4xS8aCW4j+qgX27YsjmmxE5onopZcW5iHXv9D46p2CVUkvqUgaK0RQQDwQZNO13nnJrOSFSpyD4
6b0q0FIywoIjcyQ0v9MMcutRN19NE0KzKDTqhVNPQE6tRpt/lxMZR5dsQCxWU5BMdzbYaaAC37ce
XYCwpp0ZoRwoAgOp3qY0aIGjJnq4Nf24wcY9+cnqEgnwiACpRgM8O1dOs4XWxW9YrhHdOA4mPGo7
IU4ZbmtE/gqFnelCd+XQisTH+Zb1V9BrH/a0DWhV9BRzEGWXj51lfwifCZmrafNBLkt9veYDatAj
rdhyHLXmFHQemZIyVH8R6GrDWc+vdzXCuxC/OrPrGKW7FpUakcoNAwC8B+9tg5t0yiJ4VFHhKU66
7PTBr+L9jD+5puMuLsDSZjW7+UMvUxR91iqGFXsyO5TySdzTPK8nY33tmVs+rGkwsNt1kuwhtI7a
G4QcGBKe3osO0ajOtSegBa5F1EK7kIYMGtiuyTwi5H2VpSVZABcmEYW+YYVohTBvSh8y7e+yCW6B
KUpHSzZAZ/SQkpKG92TwrK+xokcForgQClO8pmHCZRV9hg4rJHE16spozO6Ge1R/99pMNCUmvt+K
L5g8oN9WbfmcqBqEadyTe2d5CPuNmW3NCSSTkQcUKKIERzhkK2ezwPMV2nNbTMdQC25ie0lQUjSM
UvdI2Q6sz64TiDCl49cYgcU22VchZvNSP0VBR13RTNwXMgtm5sT/0PywQRZslnM0nTYEdM7GlXKY
3MgTDEEuL2BnkEGADP6KWCxkSh7tucPTNat17TePd/sVDVh9sKRDobETQOTLq2Hdo2EhyIFMo0qP
6KdLnjU/xi51P9m6eQIJ1ijKzl0xmRlmz+/dR2v6DlGbXD8AlIUjA0l5np2R7XP7JL31vM06/HzI
/eFf+2ZpNOJV5ahe/hsjHSIvB3htaE+73H9TnKwAq7JIk7ExSTtVA+yDzjn4yEbbKk2JnFhDFbbn
vYhJqohvBo8x79Easyi1dKfeB7w7F6l1Qx3WnGSx9pyMwsOPNzuABnC6ed+LVFV9QAGpSQsvMeP0
IgwDBw+0d+0Z+F6J+XsAs5fJ9hj1QS2hG7CzdZVvHfgWsc4fNPWQRQGIGUF8xXTXMNvb96XkneZ/
V/K51zuCkD/Wyy2/fZUPLTNWxBbTZOjHsgvU4lwsr9XOA9/NqmZo1wyfNcDkkaI4OM0Q7xKpSHO7
ihglPwO3GaaMpTK5HQkr7+BVy8MtWj2Xadp22OtwlIij2bNljnkOLWD74WE8CHMWEpGxdjgO1nCo
YiDEDONfIxQmMrRvP4kRf0Ml/jYRHyvnKcoYMiGGMghgo1wZqkPGHvijwh18z2Id+NUxiAU4jt+M
6GQn286Pu99GJqmtexH2h8NxOzkspjhesSNgxRN2NN9Dk7zqZHzcijYHmtiEKM2qCYsoUiMlcj+C
Nnh8RLhu6Qwcv+E4s+9kLmJeqXdXgI0eqOo9epNNUKIcW/VyEfah+ylLahgRDZIV/xs+7Ngialq+
cM4fJFic9lbVXFRf3XLmUjjDQyYGNSKfzKj9JCABZtPSWcjM8wxXItUNjJCOXniV/488ZpRSQR5h
C+bePTWnn8Fc8aAe0Fnhd94jEYEsIwZqWo5DNQQzVEilqPz64frsHaU8gPiXG4mIs7RexMn2ptvY
HaCs34QdVLw5vZ1mzlC6yA64qSeWxxoMtqv4qyh2KXNzVHvuF/SidvbTPFcUFoljA04BxsCstUj2
H5Kn9nuOmBYccEBN40TsWaOeLWlER2PPI+5Hyl70GS7wCFg/Ahhe3w8xf1Stae8+DwgyEAssDtBn
SgNrbaUcizuG72Lm+/gmnOpvzXzOebsT44j2kvM3RHQrgHgH+eZQacxAjbDfeqfeg+CmuwX7buAx
l2YA7WYUI6gQThy7Q6itaEtQR2ol+JBoXcptQV/aMd03ofqxc6QR2CVjBoCohZ9vINslP6IgJHDj
0iuJmJctaVAdQT+u4NL3QAMiSa0cn7y1D2cYmmggE5oYFfvCeKj0jL3eXIN4edQbDVNcIjdHB4fp
N5hjgsq07/2XQy6d8s3SVuQMCn2p7VfvxyjKDd5gJuzp8IKyyV2X1N3YOn8omn+NoYoWOp7nmlp4
yczR8oS6RB2ZlSbSGhmnyU4TxaafLCKR4nsFTHD4mqBx/FSt1Xt4LQB0wt8oRHTduDz7iw+Djs0C
tf1fl4IkpjQ2JSc1Hxfz7/W/tcwarnyYPUUu2BhsGgQq5hUMgS/oi0aE2Uz0GohhNI6dS0LwBXNA
xAwiICSYiiUKDHvW1TfDV7kqVAGE13SxhBBaaQ7hfjooYbiUhLerB0F8o21ZKgLwGkbqGRvJ6qoW
mvr7kFt62SZbvpSQw8Sjx7cm54TyOXAhwHBHZYpVpMttgNiSNAxen4n3rIqidghXXB0U7lmKZM9B
sqNmQ1aKsCnkcqHIAZlnz5ufBteLbfwgMsYmZY+2NXFTvXmerw8XffzM9DGL2JCf9Zxq1+2n7+A0
qr3kaFJcm4OhbbiCmqtJO0zQtyb5/eBxKmP8EQeooJPZCp4WZVxjcRr3f9Al27ylVj0sEApA5mWF
U/4EU7ergWzV6IJE5xV55LehN8a00LywI37NkdokQlBsJEmoRsRli3Q7e03BIyNG/1Bfrpc1U4xX
g0EaXBTEZoAclRtdESv6hdnXiqH3Pqsw49MYbU+HsqUwu2x3mwkHThvifvRoXe7VYBLECoUpOf9L
h1/pXGmdUKmdSEP5dL6tgaIS7GiWKqmh86vq+4a1JjAWhIaxeGWuL12vd0IjV2zXP0wcLZWxROeB
Nfl1qraOYD6yTXyZpjWKppWRj8jer6zkDBbERYeTDjWsQsGfZTVhzXYcVx/CqG498rfGGPLqnTue
EEDM9M848fMLGcz8JlsbxVBXv4OWLph/+tsTimAYTkmZ6Z7mn+2axAvaPyC0ncsNlI4CQ1AHyr++
3OQIRVSqi65bj4RAv6Fk05XtqEF5Xkr0UxlufmWjYW4tA49/Arec9fG6TosDpP1W0eFn8reK4WSU
/xUoN/pg7NRqlB8clgBNlqZ6n3bfCVLNW/yxTwdZnRnFJi/gXZDvNxdHUXn6fPmYgzN0S4GnKLYy
5y95O4wIdU6HkQJl4irAkDKotfs8TEBWabVqs8VhyfMkV2Ggmswlqku6xD3xxzMxeEptPoFwiXuL
OeN8jtWbED/bsgGpNVYcdXB/2h2RylU5JdpnUPK+1P5DzVTR9ZqC37/c3c7N6DiK0FT1PO7BFzmH
AMS3lNdbQumHGxRMDdMmGZ+k1q3aRMtAKOuuQa7B1Xunu68aUqj6D5l5Zkr9LuA5U/I1bvc4xzAG
DI3GQs3woNcCkuXpzG1tQF9uo/z6LMTdAx0V8IWz8++Y3xm1W9AVoIz7JSwTWv5XMWZlmUjFSE3Q
JRFxf7npmn61EPGYlyhmZ7QowPRKm6e8JDyEVSL9ulgpW2Tj7DZ2YzOV4IIaDMLiDFxvhPONTb9D
y+B7elF1NclHifbiOQAkV45DyxapYgTaCnIJmlothq0ADBSY84o+1fcVtjgs5I5yXj88X0vjPANB
VrCoOEw0kI6C+1ObxbtU9V7rvvaQp2ybs0zuVxdu/8uoLArHKvH1diFnsfnuLdAH4tYjJLh2DPxC
tJnMeohBuZUSGca8MdNLksQ0EhXAm4KLSJDqpl+XL+KPg496UQZKw1dxmX3RK98Qr8P4mHUOt+kK
VFY0l1lpWneUf9z6gDvrmNZO2wjERyIZRfry9dhKyyCL9kOp/cf66t4/SlrHv+Z3b6v+Nh7yuIXr
dSWZtI+b+2iEcQDslmEcQYBz/+gWMVbD9xlptiehPSyfOl6CIBupXxoHXpq///18B6IZojPYHuOK
Jxc4BRc5M5SoP9pbJyk3JdX7qYd9mc1HG7sfNdeYq57KWm21EEjzUwD0qRmhDO3WkN04j5piu1nk
WI0a0Sll+qfmFXONx43p4hNaRu2Ag3Jb09wVwJwBbQjpGZ8ipsfGcycUc5qnp+JbRcaut/YRXDZR
omFieFFwRzDLPliO+zwwgVXPpxHff7jk5Y7kSHtwCCZTLyU/hHZey5b8a10FfMBT1vUtxDkJMsnv
LhAYi0hWvBE8oyfTzEQjj+6aJS0PMWepUVEq8UmIy/KNhdzMwt7XYdUm4HKgMrlfhSF61cLfUAil
j0/wtd10OTAm6EhooFbUeUr6H09xsFVVVUTtKoZvkeUr8qYyuydKqPCc3hmMzMXF8roLfsKvwPCB
eEew4UPA+Nq3ANVvUGIPZL5HG9AZpHpCmARL2O72NTtAjWl2jkj41nm5+vAeOXCgIRzmc8u7FKCM
8n32s6iUV02kxvibqgHEq1q2Zf+xhRi9PIk6BAujr+h2FzamVJcBdArHrFqcWU5sa/G000oux2Kz
QWUKJ8S9q6F7LdcYbCSRSTFFqFbKTpSWknh+h0nTJgDdEjO5iBsM6BqYaYUPgp2KDk87ZYhYLaEK
wIMjkD70lLJn+XqsByD51Tto6oOg1v1NvTg9RN+rybi6dzDYCisDmzJcUExyn2Ss4zLRevb/9zdU
2ORxoBun1IlFkHHAd+C5EJBztc9QlvAKuQAl1avwD+fCbDFz9L/SFSbPli/oIE+asv6iHrrR9unG
GZ9wPCmbhO/ERPYT6KttyPZRh9o+8h8URrGW9KKaVDa4bKdX+EYnDWyl/wWjMmRhBLLbabR4p6Dk
r7El5ukHuYpsH7vXlN0Vd5iMPLee0yIB13hc6MouPtCRrb9b8QXnnXtsrmxXmHr1WmadbqMYxaWd
UMO2+jAoZ+QLw3CA7mHkNR6AoqnvLVQKohOFO2E0cqSJU+lleuI8Xw9IVInj0cm1DqsjiyORUqeF
wQ7dvi75X9axO1BhF2csrFAnA+OldO94jlUwohV8oGhjmInX8Phh/nrliAx67z5NeFNOfAGqLWdp
b+w54JAD4Pgw1796LK8MA9mJib6z6jmLOv5a2DI3GDxzrrg42aM7IpyfkB3cJ/GjfDf9wUz7FBRG
K2M2Erm+mNY8Drv6nfaTAJsuqikn7J65FueLlw9WKJayj9XcIt7nC8MYX4zh8uTI6MHQdl/r7xGu
lNNtHjxRwevV/t78jvGwPaP8e2Gbjppqn5q9+o0s7dj74YqTvddf0GX9KbglOB/oc6FEd7Gg06VN
hbByC7ynTdfGQHT42lDWjoW6viF5EJdjkTxnsOooYfYG8Mjj0eqjQb6lmLjaVRhVoWm1J3dWCdbG
adeDIfdPRg+HJuC2Q3Jgx8cyaFq2V9q/PkIyivwhcZpkeNoj9YbeMb0sOClGJF35L3grctDkKQHo
xVzU4Of0MZI/gEmMzW1Q/7uvdrwNcszo7guxwth0VoUP7qGXdwMFjIzsQLPzjS2WGO/D8dsx8wI2
SMJBpOAbhI3TQf5FUf2b+hPCUqUMHwkuGFCXBamPqiHc9++VOs7mWiFezPVP7o5H+5fZrRyJCIsm
+f8NITBlXXm8NIyFxotrnOy4CWiDxUmAqbEFvkTaN1d9/9MyQsoW56RYKZ2Gh2/VnDQPLp8GW+W2
cp5JGD+G31SbYxmjgzvBw1xodvWHxp2QxmnX5nXNHnE0T28aSSsdUa4ugT1Hf/5DtqxdO3Tyfg09
RHyrrWFc92G3Fgfxi0Zj58lyUbwMGJqaM+Ejvind7kz4jZLxCSY0CfyMKTefTeqLfVILrMBym5g1
BMkJw+BKuq0OqdUvC4X0HHYUp3RT3vw786jNLzhIDD4Lxtl4M8DjBUuUJhGM7S8JF0lz3fpThpQ4
2zI9Lqysy9pfZkwVVNirJ8KAfDdG4ibw/dfIbKhX5U4xJR7mXrQMXd2clQVxE4uLHTfFEROJ9lPy
Rov9vbxwqDFI3YSW/gpXj8RMQxNMFsaj3wKGgL6uAPOPDYqk+YC4EUgi09yBjHLESghMvwSrBce6
C+r2lplZMBTRRtALgW4YH9E3xOBCm/K863cn7rAKfWX24kersI6fHBdb87ewrXwW5OwpMe4GWoHk
tgRRYVi/UwDiaCj9w5ftpqQkeyvGMjg/r82fM9orIlee7XMMwizc61dB8f5j5XyDsABkg3hV/Rfx
AOAZgwDYk7mHGJjh1GUGuUE2LqF8tcczC6OZX3Yo1l5CoJ4iznBbCNpPjEnMvCtYncMvmygIhknA
UeMaeuzSFnDNx9x4IeaZJ7YbYp8GzfOEUFcPYhe6kDPZ0lRvrSJbTsO9XxW/EWDwCF9fyOSsvWkY
CgKoxM6sNNLJtCQVneViS2H9avP1e3WdqpTVSu54PxqnUDSTElf3PpDxheX3M9THVHo66fm4BQjA
TzDkrAsacAJX4H+kOY6/kidqH6LuuwmLyeh+RF3nKmMEJq2e8JhTs7Mmxj7oTkzdJs4YEui/f1sp
Geph/jPSYHAM/TOY5L/o9IWBAnilQcFJIj85ZUB8KQA2EWKTujb4uJPnKDh65oBgseMN59heLtkl
2qIBpSbcZNNlLKnZjsgxwvPD1gCXSdiiZwckLdfYivPTXpUM6u191Y9aI9FHLbGOR0vyY/xVTmMs
ehqpZvcosFs9LeFIjtsHprJm6X102TPRVOupe/hUpSPUknv6/6I0R8F8gr+qoZ1y92D48Bbj2tWX
leyXU0+bg63EYkTzMdkp4k0zhTlbbcRvq+k6awNZole4I3ZT71VBmdZHUIVej0847jxSrpquDi6m
Xr2wZYmIqNKHeM2BdlK1W31h70LO2aNnCBP6GGORZ6raVtcOd1vjr0O3/tIb
`protect end_protected
| gpl-3.0 | 9bd112b250c4720a04fc1664ef902788 | 0.954946 | 1.825565 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/tb_dff01.vhdl | 1 | 722 | entity tb_dff01 is
end tb_dff01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff01 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff01
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 2ed45fc40eee020299f61801e85b9d1c | 0.567867 | 3.389671 | false | false | false | false |
nickg/nvc | test/regress/record38.vhd | 1 | 640 | package my_package is
type my_type_t is record
state : bit_vector;
aux : bit_vector;
end record my_type_t;
type my_array_t is array (natural range <>) of my_type_t;
end package my_package;
-------------------------------------------------------------------------------
entity record38 is
end entity;
use work.my_package.all;
architecture test of record38 is
function init return my_array_t is
begin
return (0 => (state => "101", aux => "1"), 1 => (state => "1", aux => "1"));
end function;
signal s : my_array_t(0 to 0)(state(1 to 3), aux(1 to 1)) := init;
begin
end architecture;
| gpl-3.0 | be8fef0254cf45be50b9bf3e17b9c840 | 0.535938 | 3.595506 | false | false | false | false |
nickg/nvc | test/sem/array.vhd | 1 | 13,236 | package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
end package;
entity ent is
end entity;
use work.p.all;
architecture arch of ent is
-- All these declarations are OK
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
alias a : int_array(2 to 3) is x(2 to 3);
begin
process is
-- Positional elements cannot follow named
variable e : int_array(1 to 2) := (
0 => 1, 2 );
begin
end process;
process is
-- Others element must be last
variable e : ten_ints := ( others => 5, 1 => 2 );
begin
end process;
process is
-- Only one others element
variable e : ten_ints := ( others => 5, others => 2 );
begin
end process;
process is
-- Single element aggregates must be named
variable a : int_array(0 to 0) := ( 0 => 1 );
variable b : int_array(0 to 0) := ( 1 ); -- Error
begin
end process;
process is
variable a : integer;
begin
x(0) <= 1; -- OK
x <= ( others => 2 ); -- OK
x <= 1; -- RHS not array
a := x(0); -- OK
a := x; -- LHS not array
end process;
process is
variable b : boolean;
begin
b := z = m; -- OK
b := z /= m; -- OK
b := z = y; -- Different types
end process;
process is
begin
x(1 to 3) <= z;
x(1 to 2) <= z(1 to 2);
x(x'range) <= (others => 0);
end process;
process is
begin
a(2) <= 4; -- OK
y(2) <= 1; -- OK
end process;
process is
type int2d is array (1 to 10, 1 to 4) of integer;
variable w : int2d := ( 1 => ( 1, 2, 3, 4 ),
2 => ( others => 5 ),
others => ( others => 0 ) );
begin
w(2, 4) := 6;
w(6) := 6; -- Too few indices
w(6, 7, 2) := 2; -- Too many indices
end process;
process is
type letter is (A, B, C);
type larray is array (letter) of integer;
variable w : larray;
begin
w(A) := 2; -- OK
w(5) := 66; -- Wrong index type
end process;
process is
variable n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 ); -- Error
begin
end process;
process is
variable x : integer;
constant c : integer := 3;
variable y : int_array(1 to 3);
begin
y := ( 1 => 2, 2 => 3, x => 5 ); -- Error
y := ( 1 => 2, 2 => 3, c => 5 ); -- OK
end process;
process is
variable x : integer;
variable y : int_array(3 downto 0);
begin
x(1 to 3) := (others => 4); -- Error
y(1 to 3) := (others => 4); -- Error
assert y = (others => 4); -- Error
end process;
process is
subtype four_ints is int_array(1 to 4);
variable x : four_ints;
begin
x(1 to 3) := (1, 2, 3); -- OK
x(2) := 1; -- OK
x(3 downto 1) := (others => '0'); -- Error
assert x(2) = 5; -- OK
end process;
process is
function foo(size: integer) return int_array is
subtype rtype is int_array(size-1 downto 0);
variable result: rtype;
begin
assert result(0) = 1;
return result;
end;
begin
end process;
process is
function plus(A, B: int_array) return int_array is
variable BV, sum: int_array(A'left downto 0);
begin
return sum;
end;
begin
end process;
process is
subtype int4_t is int_array(1 to 4);
type foo_t is array (integer'left to 10) of integer;
variable v : int_array(foo_t'range);
variable u : foo_t;
begin
assert int4_t'length = 4;
assert foo_t'length = 50;
end process;
process is
subtype a_to_c is character range 'a' to 'c';
type abc_ints is array (a_to_c) of integer;
variable v : abc_ints;
begin
assert abc_ints'length = 3;
v('b') := 2;
end process;
process is
type bit_map is array (bit) of integer;
variable b : bit_map := ( '0' => 5, '1' => 6 );
type bit_map2 is array (bit, 0 to 1) of integer;
variable c : bit_map2 := (
'0' => (0 => 0, 1 => 1),
'1' => (0 => 2, 1 => 3) );
begin
b('0') := 6;
c('1', 1) := 5;
end process;
process is
constant c : ten_ints := (ten_ints'range => 5);
variable v : ten_ints;
begin
v := (v'range => 6); -- OK
end process;
process is
type mybit is ('0', '1');
type bit_map is array (bit range '0' to '1') of integer;
variable v : bit_map;
variable b : bit;
begin
v(b) := 1; -- OK
end process;
process is
begin
assert x'length(1) = 5; -- OK
end process;
process is
type bad is array (integer range <>) of int_array; -- Error
begin
end process;
process is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := ( (0, 1, 2), (0, 1, 2) ); -- OK
constant d : int2d := ( (0, 1), (5, 6, 7) ); -- OK (at sem)
constant e : int2d := ( (0, 1), (others => 2) ); -- Error
begin
end process;
process is
variable b1 : bit_vector(7 downto 0);
begin
b1 := b1 sll 1;
b1 := b1 srl 2;
b1 := b1 sla 0;
b1 := b1 sra 1;
b1 := b1 rol 6;
b1 := b1 ror 1;
end process;
process is
variable i : integer;
alias xi is x(1 to i); -- Error
alias zi : integer is z(i); -- Error
alias xx : integer is x(1 to 2); -- Error
begin
end process;
process is
variable i : integer;
begin
i(6) := 2; -- Error
end process;
process is
constant c : integer := -1;
type bad_range is array (-1 to -5) of integer; -- OK
type ok_range is array(c to -5) of integer; -- OK
begin
end process;
process is
subtype bad_sub1 is int_array(1 to 3, 2 to 5); -- Error
begin
end process;
process is
type element is array (integer range 0 to 1) of bit_vector( 0 to 1);
begin
end process;
process is
type ten_ten_ints is array (1 to 10) of ten_ints;
type int2d is array (natural range <>, natural range <>) of integer;
variable t1, t2 : ten_ten_ints;
variable m1, m2 : int2d(1 to 3, 1 to 3);
begin
assert t1 = t2; -- OK
assert t1 /= t2; -- OK
assert t1 < t2; -- OK
assert t1 > t2; -- OK
assert m1 = m2; -- OK
assert m1 < m2; -- Error
end process;
process is
subtype num_array is int_array; -- OK
subtype bad_array is not_here; -- Error
variable a1 : num_array(1 to 3); -- OK
variable a2 : num_array; -- Error
begin
end process;
process is
constant k : integer := 5;
type a is array (k) of integer; -- Error
variable v : a; -- Error
begin
end process;
process is
type ibv is array (boolean range <>) of integer;
variable a : ibv(false to true);
begin
a(false) := 1; -- OK
a(4) := 2; -- Error
a(false to false) := (others => 1); -- OK
end process;
process is
subtype r is integer range 1 to 3;
begin
x(r'range) <= (others => 1);
x(r) <= (others => 1);
end process;
process is
subtype str is string;
constant x : str := "hello"; -- OK
begin
end process;
process is
type barry2d is array (boolean range <>, boolean range <>)
of integer;
variable b : barry2d(false to true, false to true);
type ibarray2d is array (integer range <>, boolean range <>)
of integer;
variable ib : ibarray2d(1 to 5, false to true);
begin
b(barry2d'left(1), barry2d'left(2)) := 5; -- OK
ib(integer'(5), boolean'(true)) := 1; -- OK
ib(ibarray2d'left(1), ibarray2d'left(2)) := 5; -- OK
end process;
process is
type enum1 is (m1, m2, m3, m4, m5);
type abase is array (enum1 range <>) of boolean;
subtype a1 is abase(enum1 range m1 to m5);
variable V1 : A1;
begin
assert v1 = (false, false, false); -- OK
end process;
process is
variable x : int_array(1 to 3);
begin
x := (1 | 2 to 3 => 5); -- OK
end process;
process is
variable b : bit_vector(1 to 3); -- OK
begin
b := "1fe"; -- Error
end process;
issue86: block is
type integer_vector is array (natural range <>) of integer;
subtype ElementType is integer ;
subtype ArrayofElementType is integer_vector;
function inside0 (constant E : ElementType;
constant A : in ArrayofElementType) return boolean is
begin
for i in A'range loop -- OK (issue #86)
if E = A(i) then
return TRUE;
end if ;
end loop ;
return FALSE ;
end function inside0;
begin
end block;
process is
subtype bad is ten_ints (1 to 4); -- Error
constant c : ten_ints(2 to 4) := (others => 0); -- Error
begin
end process;
process is
type e is (one, two, three);
type arr is array (e range <>) of integer;
constant c : arr := (1, 2, 3, 4);
begin
end process;
no_file_types: block is
type t_int_file is file of integer;
type t_file_array is array (0 to 1) of t_int_file; -- Error
begin
end block;
billowitch_tc586: block is
type real_cons_vector is array (15 downto 0) of real;
type real_cons_vector_file is file of real_cons_vector;
constant C19 : real_cons_vector := (others => 3.0); -- OK
begin
end block;
process is
type bad1 is array (real range <>) of real; -- Error
type bad2 is array (natural range <>, bit_vector range <>) of bit; -- Error
begin
end process;
process is
variable n : positive;
begin
x <= (true => 1, others => 0); -- Error
x <= (1 to true => 0); -- Error
x <= (false to true => 0, 1 => 1); -- Error
x <= (n to n + 4 => n); -- OK
x <= (n => 3, others => 0); -- Error
x <= (1 => 0, 2 to n => 1); -- Error
x <= (1 to n => 1); -- OK
end process;
process is
procedure p(l : natural) is
variable v : int_array(1 to l);
begin
v := (1 => 0, others => 1); -- Error
end procedure;
begin
end process;
process is
function f(b:integer:=0) return string is begin return "abc"; end function;
function f return string is begin return "def"; end function;
alias f0 is f [integer return string]; -- OK
subtype r is integer range 1 to 2;
begin
report "x: " & f0(r) severity note; -- OK
report "x: " & f(r) severity note; -- Error
end process;
process is
type bit_map is array (bit) of integer;
function f return bit_map is begin return (0, 1); end function;
begin
assert f(bit) = (0, 1); -- OK
assert f(std.standard.bit) = (0, 1); -- OK
end process;
process is
type a1 is array (0.0 to 7) of real; -- Error
begin
end process;
process is
begin
assert m'range(5)'left = 2; -- Error
end process;
process is
variable v : foo; -- Error
begin
v(0) := 1; -- Error
v(1 to 3) := 0; -- Error
end process;
process is
type t_alert_level is (NO_ALERT, NOTE, TB_NOTE, WARNING);
type t_alert_counters is array (NOTE to t_alert_level'right) of natural;
begin
end process;
process is
-- Reduced from UVVM case
type rec is record
x : string(1 to 3);
end record;
procedure proc (variable r : rec) is
alias a : string(r.x'range) is r.x;
begin
a(1 to 3) := "abc"; -- OK
end procedure;
begin
end process;
end architecture;
| gpl-3.0 | 2dddbc7bcb3c21b6c1e98228c5d25fc9 | 0.473481 | 3.775242 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_mngr.vhd | 7 | 25,964 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_eof_detected : in std_logic ;
tail_updt : in std_logic ;
tail_updt_latch : out std_logic ;
ch2_sg_idle : out std_logic ;
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
bd_eq : out std_logic
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle_int : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
ch2_sg_idle <= ch2_sg_idle_int;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_sg_v4_1_2.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle_int ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_sg_v4_1_2.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
ch2_eof_detected => ch2_eof_detected ,
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
tail_updt_latch => tail_updt_latch ,
tail_updt => tail_updt ,
ch2_updt_done => ch2_updt_done ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle_int ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_sg_v4_1_2.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
| gpl-3.0 | d6fcc674435fb12a7e79b97a6b947452 | 0.357379 | 5.116059 | false | false | false | false |
tgingold/ghdl | testsuite/synth/arr02/tb_arr02.vhdl | 1 | 874 | entity tb_arr02 is
end tb_arr02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr02 is
signal a : std_logic_vector (31 downto 0);
signal sel : natural range 0 to 3;
signal clk : std_logic;
signal res : std_logic_vector (3 downto 0);
begin
dut: entity work.arr02
port map (a, sel, clk, res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= x"a1b2c3d4";
sel <= 0;
pulse;
pulse;
assert res = x"1" severity failure;
sel <= 1;
pulse;
assert res = x"1" severity failure;
sel <= 2;
pulse;
assert res = x"2" severity failure;
sel <= 3;
pulse;
assert res = x"3" severity failure;
sel <= 0;
pulse;
assert res = x"4" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | e2ba113bac60894f650292a181a5d6ba | 0.583524 | 3.237037 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_cmd_status.vhd | 7 | 19,774 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
| gpl-3.0 | 1d0c5aa5f088d5380b75f69685ce5570 | 0.422929 | 4.909136 | false | false | false | false |
cdsteinkuehler/AXI_Reg | axi_conduit.vhd | 1 | 9,637 | -- Copyright (C) 2015, Charles Steinkuehler
-- <charles AT steinkuehler DOT net>
-- All rights reserved
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of the copyright holder nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity axi_conduit is
generic (
AUTO_CLOCK_CLOCK_RATE : string := "-1"
);
port (
clk : in std_logic := '0'; -- clock.clk
reset : in std_logic := '0'; -- reset.reset
axs_s0_awid : in std_logic_vector(13 downto 0) := (others => '0'); -- axi_in.awid
axs_s0_awaddr : in std_logic_vector(13 downto 0) := (others => '0'); -- .awaddr
axs_s0_awlen : in std_logic_vector(7 downto 0) := (others => '0'); -- .awlen
axs_s0_awsize : in std_logic_vector(2 downto 0) := (others => '0'); -- .awsize
axs_s0_awburst : in std_logic_vector(1 downto 0) := (others => '0'); -- .awburst
axs_s0_awvalid : in std_logic := '0'; -- .awvalid
axs_s0_awready : out std_logic; -- .awready
axs_s0_wdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .wdata
axs_s0_wstrb : in std_logic_vector(3 downto 0) := (others => '0'); -- .wstrb
axs_s0_wvalid : in std_logic := '0'; -- .wvalid
axs_s0_wready : out std_logic; -- .wready
axs_s0_bid : out std_logic_vector(13 downto 0); -- .bid
axs_s0_bvalid : out std_logic; -- .bvalid
axs_s0_bready : in std_logic := '0'; -- .bready
axs_s0_arid : in std_logic_vector(13 downto 0) := (others => '0'); -- .arid
axs_s0_araddr : in std_logic_vector(13 downto 0) := (others => '0'); -- .araddr
axs_s0_arlen : in std_logic_vector(7 downto 0) := (others => '0'); -- .arlen
axs_s0_arsize : in std_logic_vector(2 downto 0) := (others => '0'); -- .arsize
axs_s0_arburst : in std_logic_vector(1 downto 0) := (others => '0'); -- .arburst
axs_s0_arvalid : in std_logic := '0'; -- .arvalid
axs_s0_arready : out std_logic; -- .arready
axs_s0_rdata : out std_logic_vector(31 downto 0); -- .rdata
axs_s0_rlast : out std_logic; -- .rlast
axs_s0_rvalid : out std_logic; -- .rvalid
axs_s0_rready : in std_logic := '0'; -- .rready
axs_s0_rid : out std_logic_vector(13 downto 0); -- .rid
clk_o : out std_logic;
reset_o : out std_logic;
axs_s1_awid : out std_logic_vector(13 downto 0); -- axi_out.awid
axs_s1_awaddr : out std_logic_vector(13 downto 0); -- .awaddr
axs_s1_awlen : out std_logic_vector(7 downto 0); -- .awlen
axs_s1_awsize : out std_logic_vector(2 downto 0); -- .awsize
axs_s1_awburst : out std_logic_vector(1 downto 0); -- .awburst
axs_s1_awvalid : out std_logic; -- .awvalid
axs_s1_awready : in std_logic := '0'; -- .awready
axs_s1_wdata : out std_logic_vector(31 downto 0); -- .wdata
axs_s1_wstrb : out std_logic_vector(3 downto 0); -- .wstrb
axs_s1_wvalid : out std_logic; -- .wvalid
axs_s1_wready : in std_logic := '0'; -- .wready
axs_s1_bid : in std_logic_vector(13 downto 0) := (others => '0'); -- .bid
axs_s1_bvalid : in std_logic := '0'; -- .bvalid
axs_s1_bready : out std_logic; -- .bready
axs_s1_arid : out std_logic_vector(13 downto 0); -- .arid
axs_s1_araddr : out std_logic_vector(13 downto 0); -- .araddr
axs_s1_arlen : out std_logic_vector(7 downto 0); -- .arlen
axs_s1_arsize : out std_logic_vector(2 downto 0); -- .arsize
axs_s1_arburst : out std_logic_vector(1 downto 0); -- .arburst
axs_s1_arvalid : out std_logic; -- .arvalid
axs_s1_arready : in std_logic := '0'; -- .arready
axs_s1_rid : in std_logic_vector(13 downto 0) := (others => '0');-- .rid
axs_s1_rdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .rdata
axs_s1_rlast : in std_logic := '0'; -- .rlast
axs_s1_rvalid : in std_logic := '0'; -- .rvalid
axs_s1_rready : out std_logic -- .rready
);
end entity axi_conduit;
architecture rtl of axi_conduit is
begin
clk_o <= clk;
reset_o <= reset;
axs_s0_arready <= axs_s1_arready ;
axs_s0_bid <= axs_s1_bid ;
axs_s0_awready <= axs_s1_awready ;
axs_s0_bvalid <= axs_s1_bvalid ;
axs_s0_rvalid <= axs_s1_rvalid ;
axs_s0_wready <= axs_s1_wready ;
axs_s0_rdata <= axs_s1_rdata ;
axs_s0_rid <= axs_s1_rid ;
axs_s0_rlast <= axs_s1_rlast ;
axs_s1_awid <= axs_s0_awid ;
axs_s1_awaddr <= axs_s0_awaddr ;
axs_s1_awlen <= axs_s0_awlen ;
axs_s1_awsize <= axs_s0_awsize ;
axs_s1_awburst <= axs_s0_awburst ;
axs_s1_awvalid <= axs_s0_awvalid ;
axs_s1_wdata <= axs_s0_wdata ;
axs_s1_wstrb <= axs_s0_wstrb ;
axs_s1_wvalid <= axs_s0_wvalid ;
axs_s1_bready <= axs_s0_bready ;
axs_s1_arid <= axs_s0_arid ;
axs_s1_araddr <= axs_s0_araddr ;
axs_s1_arlen <= axs_s0_arlen ;
axs_s1_arsize <= axs_s0_arsize ;
axs_s1_arburst <= axs_s0_arburst ;
axs_s1_arvalid <= axs_s0_arvalid ;
axs_s1_rready <= axs_s0_rready ;
end architecture rtl; -- of axi_conduit
| bsd-3-clause | 444930c51532374aa1df0725220f3564 | 0.499429 | 3.717978 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alut.vhd | 4 | 1,708 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_alut.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package alu_types is
subtype alu_func is std_logic_vector(3 downto 0);
constant alu_add : alu_func := "0000";
constant alu_addu : alu_func := "0001";
constant alu_sub : alu_func := "0010";
constant alu_subu : alu_func := "0011";
constant alu_and : alu_func := "0100";
constant alu_or : alu_func := "0101";
constant alu_xor : alu_func := "0110";
constant alu_sll : alu_func := "1000";
constant alu_srl : alu_func := "1001";
constant alu_sra : alu_func := "1010";
constant alu_pass_s1 : alu_func := "1100";
constant alu_pass_s2 : alu_func := "1101";
end package alu_types;
| gpl-2.0 | df98cb3d0ea8e178811db24c518cd3be | 0.614754 | 3.753846 | false | false | false | false |
nickg/nvc | test/regress/issue101.vhd | 1 | 566 | entity issue101 is
end entity;
architecture SIGN of issue101 is
signal TRIGGER, RESULT: integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process (signal1, signal2, signal3)
begin
-- wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
monitor:
process(RESULT)
begin
report "RESULT = " & integer'image(RESULT);
end process;
end SIGN;
| gpl-3.0 | 1915bd05e35b135a624828e192a68569 | 0.621908 | 3.85034 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1146/ent.vhdl | 1 | 730 | entity ent is
generic (
t1 : time := 2 sec;
t2 : time := 5 sec
);
end;
architecture a of ent is
constant t3 : time := t1 + t2;
constant diff : time := abs (t1 - t2);
constant shorter : time := minimum(t1, t2);
constant longer : time := maximum(t1, t2);
constant ratio1 : natural := t1 / t2;
constant ratio2 : natural := (t1 / 2) / (t2 * 0.5);
constant ratio3 : natural := (t1 * 2) / (t2 / 0.5);
begin
assert t3 > 6 sec;
assert t3 = 7 sec;
assert t3 < 8 sec;
assert t3 /= 1 ns;
assert t3 >= shorter;
assert shorter <= longer;
assert diff = longer - shorter;
assert -diff = +(shorter-longer);
assert ratio1 = ratio2;
assert ratio1 = ratio3;
assert t1 * 2 = 2 * t1;
assert t1 * 0.5 = 0.5 * t1;
end;
| gpl-2.0 | 4c0f28839a63f8eba2107e475a1ab90f | 0.60137 | 2.552448 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth109/tb_ram4.vhdl | 1 | 1,322 | entity tb_ram4 is
end tb_ram4;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram4 is
signal clk : std_logic;
signal en : std_logic;
signal we : std_logic;
signal addr : std_logic_vector(5 downto 0);
signal rdat : std_logic_vector(31 downto 0);
signal wdat : std_logic_vector(31 downto 0);
begin
dut: entity work.ram4
port map (clkB => clk, enB => en, weB => we, addrB => addr,
diB => wdat, doB => rdat);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en <= '1';
we <= '1';
addr <= b"00_0000";
wdat <= x"11_22_33_f0";
pulse;
assert rdat = x"11_22_33_f0" severity failure;
addr <= b"00_0001";
wdat <= x"11_22_33_f1";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
-- Read.
we <= '0';
addr <= b"00_0000";
wdat <= x"ff_22_33_f1";
pulse;
assert rdat = x"11_22_33_f0" severity failure;
addr <= b"00_0001";
wdat <= x"ff_22_33_f1";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
-- Disable.
en <= '0';
we <= '1';
addr <= b"00_0000";
wdat <= x"11_22_33_f0";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 85d461cf829229e3e80f37ad7327a65d | 0.55295 | 2.905495 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_10.vhd | 4 | 1,680 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of bus_module is
begin
behavior : process is
-- . . .
-- not in book
constant Tdelay_synch : delay_length := 10 ns;
constant wait_delay : delay_length := 100 ns;
-- end not in book
begin
synch <= '0' after Tdelay_synch;
-- . . .
-- not in book
wait for wait_delay;
-- end not in book
-- ready to start operation
synch <= 'Z' after Tdelay_synch;
wait until synch = 'H';
-- . . . -- proceed with operation
-- . . .
end process behavior;
end architecture behavioral;
| gpl-2.0 | f432a46c3fe3e6b1034d70c34aa81587 | 0.576786 | 4.363636 | false | false | false | false |
nickg/nvc | test/simp/protfold2.vhd | 1 | 1,791 | package protfold2_pack is
type id_alloc_t is protected
impure function next_id return integer;
end protected;
type rec_t is record
id : integer;
end record;
impure function get_next_rec return rec_t;
end package;
package body protfold2_pack is
type int_ptr_t is access integer;
type ptr_array_t is array (natural range <>) of int_ptr_t;
type id_alloc_t is protected body
variable counter : integer := 0;
variable ptrs : ptr_array_t(1 to 5);
impure function next_id return integer is
begin
counter := counter + 1;
return counter;
end function;
end protected body;
shared variable id_alloc : id_alloc_t;
impure function get_next_rec return rec_t is
begin
return (id => id_alloc.next_id);
end function;
end package body;
-------------------------------------------------------------------------------
use work.protfold2_pack.all;
entity protfold2_sub is
generic ( r1, r2 : rec_t );
end entity;
architecture test of protfold2_sub is
begin
g1: if r1.id = 1 generate
begin
p1: process is
begin
assert r1.id = 1;
wait;
end process;
end generate;
g2: if r2.id = 2 generate
begin
p1: process is
begin
assert r2.id = 2;
wait;
end process;
end generate;
end architecture;
-------------------------------------------------------------------------------
use work.protfold2_pack.all;
entity protfold2 is
end entity;
architecture test of protfold2 is
constant cr1 : rec_t := get_next_rec;
constant cr2 : rec_t := get_next_rec;
begin
u: entity work.protfold2_sub generic map ( cr1, cr2 );
end architecture;
| gpl-3.0 | 3aa373489065ceb482dd12804072cb22 | 0.558906 | 3.98 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_0/sim/design_1_axi_bram_ctrl_0_0.vhd | 2 | 15,632 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_7;
USE axi_bram_ctrl_v4_0_7.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
| gpl-3.0 | f4b806d3dbad8a3937b596d8e581f14b | 0.67074 | 3.098513 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue520/alias.vhdl | 1 | 899 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_extname_driving_signal is
port(
clk : in std_logic
);
end alias_extname_driving_signal;
architecture primary of alias_extname_driving_signal is
signal counter : unsigned(15 downto 0) := (others => '0');
begin
counter <= (counter + 1) when rising_edge(clk);
end architecture primary;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_tb is
end alias_tb;
architecture primary of alias_tb is
signal clk : std_logic := '0';
signal vector16 : unsigned(15 downto 0);
begin
clk <= not clk after 10 ns;
uut : entity work.alias_extname_driving_signal
port map(
clk => clk
);
blk: block
alias counter_alias is << signal .alias_tb.uut.counter : unsigned(15 downto 0) >>;
begin
vector16 <= counter_alias;
end block;
end architecture primary;
| gpl-2.0 | 727d7924ca872740da05d25c3e5ca8dd | 0.698554 | 3.367041 | false | false | false | false |
nickg/nvc | test/regress/vests15.vhd | 1 | 4,784 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2959.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02959pkg is
FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit_vector;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN boolean;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN character;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN real;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN string;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN time;
end c02s03b00x00p02n01i02959pkg;
package body c02s03b00x00p02n01i02959pkg is
FUNCTION boo ( PARM_VAL : bit_vector) RETURN time IS
BEGIN
assert false report "boo with TIME returned" severity note;
RETURN 10 ns;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN string IS
BEGIN
assert false report "boo with STRING returned" severity note;
RETURN "STRING";
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN real IS
BEGIN
assert false report "boo with REAL returned" severity note;
RETURN 10.01;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer IS
BEGIN
assert false report "boo with INTEGER returned" severity note;
RETURN 55;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN character IS
BEGIN
assert false report "boo with CHARACTER returned" severity note;
RETURN 'Z';
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN boolean IS
BEGIN
assert false report "boo with BOOLEAN returned" severity note;
RETURN TRUE;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit_vector IS
BEGIN
assert false report "boo with BIT_VECTOR returned" severity
note;
RETURN "1010";
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit IS
BEGIN
assert false report "boo with BIT returned" severity note;
RETURN '1';
END;
end c02s03b00x00p02n01i02959pkg;
ENTITY vests15 IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
SUBTYPE bv_4 IS bit_vector(1 TO 4);
SUBTYPE bv_6 IS bit_vector(1 TO 6);
FUNCTION foo ( PARM_VAL : bv_4) RETURN bit_vector IS
BEGIN
assert false report "function foo in entity e" severity note;
RETURN PARM_VAL;
END;
END vests15;
use work.c02s03b00x00p02n01i02959pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02959arch OF vests15 IS
SIGNAL c1 : bv_4;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
c1 <= boo ( bv_6'(OTHERS => '1'));
bb <= boo (c1);
bv <= boo (c1);
bo <= boo (c1);
cc <= boo (c1);
ii <= boo (c1);
rr <= boo (c1);
ss <= boo (c1);
tt <= boo (c1);
WAIT FOR 1 ns;
assert NOT( (c1 = "1010") AND
(bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***PASSED TEST: c02s03b00x00p02n01i02959"
severity NOTE;
assert ( (c1 = "1010") AND
(bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***FAILED TEST: c02s03b00x00p02n01i02959 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02959arch;
| gpl-3.0 | 46c90ab13f5a3d7712d99c8bd2417bf5 | 0.611622 | 3.6659 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xbip_dsp48_multadd_v3_0_2/xbip_dsp48_multadd_v3_0.vhd | 9 | 10,163 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RRooMx8aKXOKuw0jba9AAvNqcv1aOAWx0dmOeAMZtfEA8NEQBycfD1he5bNQ520rjDcafpEIYoFH
8wShwJiQKg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RgXfz+8mp1qbBTyetHH5ngynBLMwZxu0rxkXLh6QHG9XAy4+BbRKOjz1+c6cH6NYhRRfM4vT5Wl9
ixg8Rc8Yc/S242b09BUNorP5ATo1wne5IxcZ3jC1T4BUzl0tgUScvpD0uFueK3/IMnEjC4aKr60w
VKR6qyW4sq2X954pF24=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oSpqzFUI/f1Ucw6UHNSsuY41hVH/I8MTwUZaCMUrE6zrelZVctDl9yufZENXxn0WT1Yem6/W+w1g
j5QeVJm+5hjC0WIxLupVJMkqfzQw8dGHJPDGoEaTB2RcDqLTnI9CrpQ+iJb7hrQn6dDmxZImAuMq
3pJVs+aaFHAeNuzZZhE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
X4Fi+a1OzUk68cyxZUSzfNpLCwkSC0wmt8tY0kB574VuReti34LgiOkcPXhGDj4gSUKkUF4A/Yda
WDzaAnabrJ3zv3CWcxwC2pPrD1rNotHPICUvwJpTTNzK8oCLdrgMtygrsL5CwXaOVNz1a++BWa6C
QlArFRdlccowSRhXDf5tSyKNSLiV9tJxHNvWPzIowxyUtoVMdFV+wv3UhZXGP74OmYsEJ9ESIEXz
q0P+Tc5gairxuvjskvUVpqbsNEBOq90+NKAEaLtPOQ6vY8kzp+eWm8uf5f3kgAZZsAiQGswk7vU2
f5LaUSeubviPjfs+8uQjBW2DPBwJbScjsXNcQA==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ro6yqNSieyMPHHxOuV5fgYIFX1ue1fCOQaUrsWRJcJVYR01otjGNBK1LpULF9osLOrFWk4AtTJqV
rWcIGuQTGE8iRA3XlZBfUPo5Auyp6hG2JT2LLT/s9g6oUGrueNakH+McXpdG6aUJkgH9/eoBjrLX
DrPrHqq40IlnSppHpDAOq11fRkZk9TkYdWeakR7Tqj5fMix/Hves5J2MNw7M+0/bs9k7crMC3AB4
hiMav0upztwGMWPFQOTJLcPJQ9Jmlip35nCdHQRH+L1Pz5yPl599XvkZh7InTkLreIaRmIpZaIPJ
dSX841g9ZA3G2q8OiDyHBCZOsKYNN4/R2I8Cjw==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
K8DR1xFh8LdLJFzLYbjbQJHVBapMV/A5ef8aS1igRTqWTzaxTp8rcNFvJmLeb2FVSABbW9ENq0z2
4PAQuZAFntoQZCy0B96/GhJqiwWNdo9SkQAXHie4qn1yl5LCT837iglxkr5T9u9hdW/y32580N70
9mwvaao2qtKVUj2WO7a8JbZTzIZj2kxqfrfxG+wf2zMcUTQ1XZCsGULlRMnDM7exK4fGQxqbrLsN
3z3GB/1h4CYvFQCvVlD3CURFCtPUP/5toS0Ja6ccVb6/3q73spZWxAHrzIuZDq1YEczGdzSMR+k6
s98cQiYspIArx3y1cvwLR27cpPujPAWuCP8Wyw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5392)
`protect data_block
qSsiLyvJuChi2E0XpHgqvrKS1epB0U4feczmHFW/2YJen2AC64LL92z2ukfDjg3+ewU/xhyTUUya
hpuPjtDdmNZt5KWa7/PuPHL7xOFVFYYc3SSiqP1piTh+GdjPoTRU7RahZaPBjJyxnRXyOc0FXGMj
r/CHS0dSVkGoh6MWYHj2vwUtfJ9/+u66M7alxAxu1erH/iwheMyTYZ5+Mr0Qmi1CQutQdGnOUROp
43sCgrMtFOFoYfSRECN0Ta3B4EX32Z1GWAVrJ1kfmrHQeiVqycBVSoSAIUAwV3TYRAuv1aDJWJdW
IuZz9dg7nO4/z+s+WcScTEsd4Psr3PJxUtycpFY3neH+RzgIca215uITU2H70IoLE2DqcG47DMpg
wmlVrey5JGiqoaFs4Q0lMo1o3F1sc/prLO4TlOxmxulR2Z79IdhMKiel22nsOV294Ay/O72fqJTo
HTFvV+R2C9y94QNdnXt3ULowPaCPP+UFGS+pmbwSndIZZVvY1YtXj5Jjmy2mk3gUvM8n9yi1qGBr
9t0JoWWVuWqgYcCr5IGyPrOImfWe6g8uwoAqGuMK44HsIwMt5/yNzgzRkCNnEdahF4yL3/krQF0n
BrHclMY3jxuLtQQXGPI+JmM06pBOpuwUDSk9q7YIXG3PiCYT62yhy5a2UhMooDOhmUKCz0ZfOjPr
O1GxGPzufCnOLGn4nSrWIpyzpf34hSjpZQ2Icbds85xRaDryyubxrtiGnDdbqZHt5XijCOTQAefw
YYCgq3QY/rsFV9rf0eWFKCC2bdh9lmbBCmctAwtdPzPWI+N0w81Z9KT9rIXdATwRlTDamU3oqIWX
qu0efy+WVvg3AiyjRtJY2pfbdI4Sxp622k2+uEL4afpWlgLWJcWZVyTnd0NAtmV4Uf8XWNk5YkDZ
50ddNLy3qokxc+vP7N+qvr4zt7K4O/cbqczrYMSWyJ58n7bIUrK31DcOZWjfdlfn8/ZUWwH1GIX7
FZBLFdT98KPUAOD5g7EB1C+jxIO6OCESKUu+AYu83IpnKWNZv8ObHo0YiRxggrf+Bwek5K0rpIrp
0BQE8zfLscnwfaUmlEYVN555uc/Jnv5e7UZf7sR7o+iBh0Fj90D+H+PGPENGxvNus9Jmpnz1t500
KdAIMv5ArD3g0O1H921fIdbMXBt1fzQElA9060j0w6rFc2Bi4p/D7A94wE0O8xH5hmiRC3/k6VQX
ZiKiSflApUafYsyYcVy2quejOkkziZwW2RnXnjwKpvvuOt8J1dHqzcT80L3B4Vu4eKYa7axF8yjf
kYMP1H7VAUb/8g8UUeQ8IuSqH4tO4JzxuZr4SPMVrjw1Un1vdYEXLzS+ppKQhmU6qrMvPZsKfPSj
1tlWQ30KdBqwFQia3U/XSgL1NRDkLBBj+wWX2uNnTl8Dd110g5RQrjlfHCs2J/CU0tv6+eQGKu8M
yFAxGQKCXJAHTWBQ0ws9nd83TihT5SaBNGNixCvEbUJ8sHTvx0I02ZJqhNh9CPLUnH3cZG9ZYgjw
safHBxZXzirApHKfol7GBoxIVStQyI3qnzEEULHG61iVn7272MtNZllIORwqqHsEeAWGTy/oMtTF
qx41kEJYKJWPznXcfDr9kPiradRBoYA96+xaVT55APbz86jyxEaLjyaSXR85n6fvpwlJ3JaWMG7p
SDsIU8CkxAk02G6oLNnmBgByRGUEv2XCHDa6OOj8YCE9N5bnmeIybidHIUZaxsWPXj+Vct9tI9kB
Xqu8889CB6WZsN4u79U9eFUEuHC0CMYToTkYD4Opljwi9rN/7aa6JiLSBOv/omud8ozFN3i6xp1p
CX17uXVuDrJFN/sBwKh8Bb3vsVQgr+NrPRTSxXbAPCROkv6Vzd3wwS0XnLmb/fm4+vMTBCzf2b0J
ddMzpezmquaHLmDpABxff5buJ3AiWv605St1jkqB6kV5ExtY34Yph27LbiLy9ba7yvSEUNy2+VTG
JufDz/O8u+BiQlHeGUmsBAajArnaejhV4xFuN1QHAIL1jv3RrtR6Tkn/X6Z4MIdZY6ZS61KM61+E
QkU0zdVOPyK4WYLR/CcdCjO7A8gpTvlC+9+7S5zLJXrKCumhur5hX1BDwX8AsjkTTIKKEtR1KP1m
LC0/nqxtsebCHjmWeplfz8kY7UVUGXiXWxgmiO/KOyX6kk1kuhypiMXd4pbioTr6HbDkcgJ5ToXg
z5+NooylW6pTFjb99MXhoPN2Z9bsLayF4sTvddtYYK8Lzbq7fy7vdco9AzdQHXG4LXLHISjP+DF3
U8TWjWag9CHZ8+eCvWBhn8j7ZHrXvmgz4pq14/a1djdoUQGxHj4VosOG5tZyAnvS2SlsoNvSeT14
XdMcakkz/s+BV8jrDAZJ8cGtQns4lja4SBYqNSJj/ZiZEtLRiyg2MmIBQMZiz57K4KZ4qYSP/XaZ
UmBWgCwPc9emczXr0rrffT33X73AyeaNhvJZsENg7Kb1bGWlO/vb09Clsl1QPfCBV7bv4+irbZX9
ZoPBZV323IogCcwP5YP66238XURwYip7ZDp8GahEIWnItm5fzYsjA+HnG8l+BnB0Pkw2FX3lqbc4
Hs2kLsV6xLwIGmbtP0A0kzGXEugwhOwVyETk/J+XWmQ60Lbk50pkIj1lXLAbro5w3kh30A6yIWu0
jrbTrUhQiyK8/2v91azUoSbwL+kIyPakPultH5YqPy50eR+Jq3db+WuwGayFwdiePxpY7R/1IvqJ
ClVuJVNQ3BtXkMmavNtRXazcr8EbYFEjc4ULd0sfmVCvNmNV2pvrN7bOpxphuyALjwey+uLiB0B9
4Un3dmXt/u2Em+7McXzSsc2c7LZEcYeq1W1vILFWfLM+PWnJVWOKfqGHKkjrntoJnkgg8OhN77n8
/1PbwD6uSzYvyOT6T/s5kCtEe94Hj6QZ/AEwnIpQ7ef55hwdXjUGJJa5SKEuBtSPaWnGjYLb7fbm
iZpDtGG9ivpeBuj5fBiH/6UDrMgz/DtvyIA8fi0VfYBFEfF1WUF/TfuCK4NBVR5UQl9YdtT55akg
2/RKBOvRpBwI6dAeuGVaUF0C+Mw4R7tihE+seFhdmQccQNMcTpHDwISSBbYl/+OIky3FPJF6Ub8W
/EKDoGnrp0yE8SQCWZr9NzI/LXcJ5mI120baCpq3hW85p5fWOuEfqTqgA+d5F+p8fN7WhWVaWRk9
bIJtu210DPFThCGUy0SjLA1PTh+O0T7uvX5hX/CcqmySdn3tJ3Akma1c5kMdfbf9Tr6eAkSPmtwD
h0uS2i2/PHr9zoCz4+bwR8uzwR7IFpAjPH8qZewGGe6RjbCyxJXOayouerfBIFmUPEUBxzPQxBip
QZtYDgV6WufLnkAL3nQVy+b/WH4e6x0XuvA6UwhAUi6qrETp0o8xwfu71hBxr3JIeI/FrujALShv
7xR0mYa7wssZ/rX9HNAq0iNCK99/tPXDAQMOMOLF7FmVcMzXlbB+VAyEZvZriU57bQwyHvlwWyiz
/TV7TSW17TozNKMTSZ7hz+xslRn2xCLc8OOI2KGseu1a1ULoY85lxixLkdy1u2Ie1C0Ec+H1Xxbo
jr8f4NdzuzOzJp9yDzdzybhtTY/rtCbAVapO5magpGwsNluRhArPej4A1glRV5EWeiYUTpTszyhk
CkOiRnkM/TXWpcb4bmyX8mwycaLpE3tl5d2ctyZ418fraNNhIKcDX7T8XfoYxmuygUTdpnEcNvgs
A0BhHaxGn8TPYsv+yOaqufscqqA0uK77TP654HCXvLz4rZn9uCNNSBsAemgpff2bWVxb2nhBMlY/
vpR8p/YJn+LSOKay5eBqO8UFp3RCioCmYSJ8cJfrweN3DQsyvbrFczBIa+6lbzHUBdBbwO6wsDMb
30gFQcNzA8S8Ynhx8aw/KKcpWytU8vF7edwxgzkCSxLdW+ugeTKrtlxWfQekpZ0IpqnxvXvnWXoa
pWZk3AlP1zt4inhpBawHuOupVb9haqdgFwxaj8J18+3BZZrIkqNHeXBJ85dTFo/qsWXsFqp8hoHT
/ivy9TWmoIB7iKGXbjD8eWPg0mJ769jI58aBdvcT9K4Vj7dByjy5H6za/6hJ8dNfZjE+x3gcjXeH
1bTgHDMA2VmWGQOmnSvsDziccUq2jS8D8qCyyNVLuXvO6A9OfZA82dITpLD8YF4fhoXE7B9AxVob
sB0uRd7cwTbfWQXtI+MI9bYZBO7WwVr+KlbPDRXOapabibw2FhXl1duqCIe993uiG/537tuZhl8j
/S2Y3X+9ZFuSS8qt4UlC1zkgIoNf7U6rlBL6KCDIS2ftL4K7WZL/ndoxvLBehozq5BMPtn87k1O1
WBiphqtb3B0w21qQGxGa1Ul5XWVVjYoFSC92L0k11aWbgKLRY5/v/c6kStv5wed9nYwrHD0CgSvL
FcsGrJ+25fsPP8uOBQ3YDY4vz6EdepeEfc8X84dQLYP/XDZU0xmJd21+q+nMBA4o8fOTBZCNUcst
rRYo+dSyV5eYItW53Fjdoq8nvcvtmFCOoeoUzeZLE8aNqRRm6+dl6gAHWmoiZlnixA/Xiv5ajbf2
FZ58F+tff0nFwMAHREo/Vg3Uc1KHqgzfco6afxC5M4QstJdgnQQlc1//kQM01psHdMuViOVBFQE4
NVmGYcJCttJv4WRxXGhGVyseyokRnwJYrBTkoDV28x3aZ5II80pDb/cCKbk9WLUXXysgVuuJHphB
3gbgkGCkVcscXi82EdCKeZi17ZjV6bdqf59bWPkwdP39Y1IDhQRPTtk88alhor2xOelPiWJNekey
C633DjUAmiZv8IliA9bZo8Kjr1J/IjBxODREFUctkztPUqpGOKwHOfbWLiNwPWmkud/SHwHZchy1
LxSzI6Ue7QZkMTlt/73tZ7AV+U/oq7n8vh6Q2nY83bgDWY/WumtsLOWAvTEiNQYxdnYEt3xh26Vj
2sFk+l0pDX8NXTkxZD3S6QtRHARAJyi2jb6QwXOOIvCvLIerZ8Y4PbN4LSiPxXzJyIs2fhdruswn
1pNku+Rp3XkF/jL8VOlz25SrsalJYFSJe0GY5gnwe+G4iEyC6RfY69UzRinAZN/0mvUZEENVrRYA
0humU+qYNKGislj3803oXBRhWn5iBr6Q7/yZCsqGFLVcZABG900Lj8omc91BSAdRGfnT1onQ7JdE
5fafOSNvqyJha18FDq+KpA5dyOs/nvX3IbwSe0k2wAEtX541MYcD5jEbQnH0fgKedfDBzwb6yqFL
jh7bYtThZWi5/sukIp83mr5VxY0aa2w2wCjvnf4exUmbjUFXZmEoLi27EWCFgOH6jjTnjNr+rBIm
xBRTTVjG5ic4a+123byWbEFqmYYLmKCa+WWugUOjsaBfo6BpQpxdYokdNadEdKoYBSaykGnqJNQt
QICupdGEIbSjjtvhfkuD+hzPPIi4HeMFOVfTzxhi81cyshXgL22xXN2ZIrvWYl1covinC+WECyYe
uZ6wGQXzcyDXxfP1M8hGqXM4GabRq6pUo/inOk07WfNpqhSoTXloa2C6jdDyoHXhHteS/Z3a6p4+
6XI4srVCP5eQ2HHoxl0nBQx63yOf9GFLcQyUZeYSeNDl8yCkSOe28V4mKiHBIUhXnGEGVdRBBNte
okrVAgeNWGSI7J03PyWZl/uXmih3BusH9JX7vxemWcTcY3QofpV1UZlbM8n4ARxMn0SdoEKtwcUv
k5wbWGKNIW7Jj7NHZ70Zan41reWEOoJrER8XjoTB/32wAssv8jR5xcjSf+CpKCTlXyEE9rPZaXiy
qBgofvGlrnSy+dMyRrXN7t9OxBMGgdlO5aRTV/NeMZQp8GTiz3vPGRYpy4oSEpiv0L1Vdr6yUWIt
gczgDam6kaq9ONoKLyn8tt1VrRh4vy4cIN6z2pjF671ttsFpmdZQx0DD1/QM1DVgXW3r6FFsc8Sr
b3gwVi5ir5x62CYoVwgZkqK67fbiWW9zvTQiE7mn7t3P+G/mcjFKkxsKAJ2zhW4xAz06TJC+S3Ce
3mriU4VYpQUmAXAF/sR9ywJOAJP6I802O7VXTwwk96wApyveZa64LmiOMnT78kBWFsX09oP+IO9p
p5AtglnSYtOBxGq9jFZJs5I8t2L6skoG/dz4xVtzYk7jLrBJ2/rX5oKZgRdGetjr3lXtz62m9pQA
9UwuDbWh593XXRtiNp5ggjmYNN8gHGaOqCaLc1wA86wiJ0Vu41q3c31JsLMcTkKlHoaTeOb3oowr
xeeAhZqsNJG3KnRLFXt7FloJepoZOq/M9vHBTuMPVdFjhkZTsGXd3goS34hOBDZ1gzcFYg4dKFOB
ff+hhRYhJPbXAkqj+Y75aVtOdPk2ZfElDIYGPSJj2nGh3ohs1R8IhRd5N+A+cQ4QmxEIdCCBPowR
BF7zxaTsul42PrfEpIgEwK5fk1W+ubyI/S7y3SCRWgeO7UBucI+QD00S29+pXDuyt3+1goYU53lH
q1W2uZNpiXVyprjDnTR8PbhcN+SydEoxQ3ZqekuZWswgkyCl7RNxCA2ZEJsf9rhMBzVW5uRVEhBv
Hreq8gMysjciXOSiisIx4z+KS+dPNXqBZ7J0JVJo1gwmG/kooh0opHoJMIsgBsV8iERnzhec/kUK
eW8TFThaG/9ZfQlZhuD+959/HCNQc2ojUgXgQE8/g9+S8bxJrrbL1wl8+zqLq0lMvBNOUCnwSdJy
jbmMBdkuqSwNvw+c0RX7x8jJZY6KTGyyQyICEAK/h7k6e5g7umAk3APVKHnMKIz7DOLojgSpvbDO
ALjGDA3vfztum1DJvVwhf5sirhya54VqWBoKjeWArZXzztB2wau3jWB7Zz3tf6ZfO71Ev9IL5N/6
NvRxx6xZKP06vXdHrWbwV7/kOY1jCVnG0yCpLdwv4nsBUyFCSl0n0pRXJvex+1EZDX1lRgWcYaMa
jzEc4aNoP9V2jhmvfbHdCXReRfily3bGWBuhh0JMaW5woAAbH0C3qBKGi6hYA43vCYXvTBezb1Hv
zJitLFLjND6nJx5RuXgY0M7wYI/d8SNDuq9/01sTgPY5rTwotDE9rTx8VtPk7BKBl/1Ctow1WfQv
ZTn2hFEdxII4sIwO1xsPWuvPbnQH4mO5peV00rryyCEER0sjUPaY1u3hsaQ/piYZOm09fBlgUQ4K
a5CSaqQhyVYD6AdBYmgSc1MsFb7U3xVCb36+8yFhSgkdYg==
`protect end_protected
| gpl-3.0 | c7e3f1d180cc627bfcfec37f38bc3637 | 0.921578 | 1.936547 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/tb_dff05.vhdl | 1 | 1,076 | entity tb_dff05 is
end tb_dff05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff05 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
signal en : std_logic;
begin
dut: entity work.dff05
port map (
q => dout,
d => din,
clk => clk,
rst => rst,
en => en);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
en <= '1';
wait for 1 ns;
assert dout = x"00" severity failure;
rst <= '0';
din <= x"7e";
pulse;
assert dout = x"7e" severity failure;
din <= x"38";
en <= '0';
pulse;
assert dout = x"7e" severity failure;
en <= '1';
pulse;
assert dout = x"38" severity failure;
din <= x"27";
pulse;
assert dout = x"27" severity failure;
rst <= '1';
wait for 1 ns;
assert dout = x"00" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | d9cfb39aca18f1675e9861120cf33377 | 0.550186 | 3.250755 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_06.vhd | 4 | 4,392 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book (in text)
entity computer_system is
generic ( instrumented : boolean := false );
port ( -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity computer_system;
-- end code from book
-- code from book
architecture block_level of computer_system is
-- . . . -- type and component declarations for cpu and memory, etc
signal clock : bit; -- the system clock
signal mem_req : bit; -- cpu access request to memory
signal ifetch : bit; -- indicates access is to fetch an instruction
signal write : bit; -- indicates access is a write
-- . . . -- other signal declarations
begin
-- . . . -- component instances for cpu and memory, etc
instrumentation : if instrumented generate
signal ifetch_freq, write_freq, read_freq : real := 0.0;
begin
access_monitor : process is
variable access_count, ifetch_count,
write_count, read_count : natural := 0;
begin
wait until mem_req = '1';
if ifetch = '1' then
ifetch_count := ifetch_count + 1;
elsif write = '1' then
write_count := write_count + 1;
else
read_count := read_count + 1;
end if;
access_count := access_count + 1;
ifetch_freq <= real(ifetch_count) / real(access_count);
write_freq <= real(write_count) / real(access_count);
read_freq <= real(read_count) / real(access_count);
end process access_monitor;
end generate instrumentation;
-- not in book
stimulus : process is
begin
ifetch <= '1'; write <= '0';
mem_req <= '1', '0' after 10 ns;
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '1';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
wait;
end process stimulus;
-- end not in book
end architecture block_level;
-- end code from book
entity fg_14_06 is
end entity fg_14_06;
architecture test of fg_14_06 is
component computer_system is
port ( other_port : in bit := '0' );
end component computer_system;
begin
system_under_test : component computer_system
port map ( other_port => open );
end architecture test;
configuration fg_14_06_test of fg_14_06 is
for test
-- code from book (in text)
for system_under_test : computer_system
use entity work.computer_system(block_level)
generic map ( instrumented => true )
-- . . .
-- not in book
;
-- end not in book
end for;
-- end code from book
end for;
end configuration fg_14_06_test;
| gpl-2.0 | 7e91a06f75b9dc74ce3a6abc7706b11d | 0.574226 | 3.684564 | false | false | false | false |
nickg/nvc | test/regress/genpack6.vhd | 1 | 1,452 | package poly is
generic (a, b, def : integer);
function apply (x : integer := def) return integer;
end package;
package body poly is
function apply (x : integer := def) return integer is
begin
return x * a + b;
end function;
end package body;
-------------------------------------------------------------------------------
package wrapper is
generic ( package p is new work.poly generic map ( <> ) );
function wrapped_apply (n : integer) return integer;
end package;
package body wrapper is
use p.all;
function wrapped_apply (n : integer) return integer is
begin
return apply;
end function;
end package body;
-------------------------------------------------------------------------------
entity genpack6 is
end entity;
architecture test of genpack6 is
package my_poly1 is new work.poly generic map (a => 2, b => 3, def => 10);
package my_wrap1 is new work.wrapper generic map (p => my_poly1);
package my_poly2 is new work.poly generic map (a => 5, b => 1, def => 1);
package my_wrap2 is new work.wrapper generic map (p => my_poly2);
begin
main: process is
variable v : integer := 5;
begin
assert my_wrap1.wrapped_apply(2) = 23;
wait for 1 ns;
assert my_wrap1.wrapped_apply(v) = 23;
assert my_wrap2.wrapped_apply(2) = 6;
assert my_wrap2.wrapped_apply(v) = 6;
wait;
end process;
end architecture;
| gpl-3.0 | 8e70828aad621c7639feb962f9122f25 | 0.56405 | 3.978082 | false | false | false | false |
nickg/nvc | test/regress/driver10.vhd | 1 | 1,759 | package pack is
type op_t is (IDLE, DO_A, DO_B, CLASH);
type op_vec_t is array (natural range <>) of op_t;
function resolved (s : op_vec_t) return op_t;
subtype r_op_t is resolved op_t;
end package;
package body pack is
function resolved (s : op_vec_t) return op_t is
variable result : op_t := IDLE;
begin
for i in s'range loop
if result = IDLE then
result := s(i);
elsif s(i) /= IDLE then
result := CLASH;
exit;
end if;
end loop;
report "result=" & op_t'image(result);
return result;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( s : inout r_op_t;
done : out boolean );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert s = idle;
wait on s;
assert now = 1 ns;
assert s = do_a;
wait on s;
assert now = 2 ns;
assert s = do_b;
done <= true;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity driver10 is
end entity;
architecture test of driver10 is
signal t : r_op_t := IDLE;
signal done : boolean := false;
begin
uut: entity work.sub port map (t, done);
p2: process is
begin
assert t = IDLE;
wait for 1 ns;
t <= DO_A;
wait for 1 ns;
t <= DO_B;
wait;
end process;
p3: process is
begin
wait for 1 hr;
assert done = true;
wait;
end process;
end architecture;
| gpl-3.0 | 935b6a785f65f2d3d356e6a5251a1a9c | 0.480955 | 3.900222 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xbip_dsp48_addsub_v3_0_2/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 9 | 86,743 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
UX6FD6ob9guh3imTUKsptv99prnxS5V+ZeRz42iTpwYqxDUtZEPmWKp0vkj99C5+MrJp4VoUFE73
p6lv2DvDjg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jlpiTccme4Znd35yyy/78EzYYFf9wXbr3/CN9UMuqfuD7fLs8bN13fKyBXTKIKVZnTkfZXQdXiSx
WRD8ytGYG9iXOOLM+O93g6YzZyjra1HTe3QuYr5CR95qlmF+FAa4+oi3bKNg1oR/jm1OY3QZxThq
Wzu4d4e+4QuFcf6Mokg=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MKNTF7yAvoucxavBUUE+B1Lvuam3j5q8VimTsBzaIegdoOscYMp4fsimSedb3DGNoSAs8b2GFL7w
CvXr4aAg1x4d0o1OXAJcF9tdNrbayr1tLYPmRlUjdIq2biRkjfnbyQ8CT3G9bBODMX5yL8O/gBQA
Y856Vzu48CG4p/dOW/U=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZK8Q6i3oOMte30rzwOY9jdJm4ji9eYZ12acaUo+uDhiYWX1mTyhN2wEog5/jl9+8Pv+nsKj609Pg
KBDwBgeuPS7nh2cCtlkrraZaZJors1ajIRnGGZtDSy60gqrJxdTYJJYKfh2EY1GAIwvyb6IkL1jX
1Wl3BGMvuYLZ7W9KctQWbVwljKt5QocxrGE+OnQNSRlGwUoMV83DjxElx9S+yOj4K3Q65CdLCxsk
o6HnNvjeMohewGbDpyoKXtbxjj5CDJiz2gLx9SLuSI3dyBSZS5Xm72ZKYBE95euqnjmZrMoJ4ZPL
+2Hmo/bl0I7vSpXfU1yX03+JZ41oNX1p6N3TVw==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RY6Q+f/b1QQveiV7BWdqPZahXfBjCLZApkPiUwgDHso0uj/+Ug5djvUVey+4y/svMhTiWs/KHHAU
EuNhMn6PWtxtIlyOwLOVC/mJORIkOxtUqPrkJ6KJ+WpLHh9OIIVwvZWaj1lZZ05yEhOZu0Bl79VK
2DzZtVwQpuosnOavJg6aBLTz8U0mhGRE2+pldlBwqL4aLWAtRAGKbcanrDuIfhBZV2hAkGrJR70O
/uNkIYJbEpJnZ69bNNXOZxe8SK7w5Y9Cz+8O6UpWuMNlPafh6KmvTwVzHXMKXKF+6mbgfPtIAU7b
UJaisuqsks2D4Vrpm+OyLmK0k2StZtSdq45VTw==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAxveHqZmP0SeAU5WyXLrhCvuTZRKsZsfWJ7n79L/CjZDLBMPWk+uDPmgZl2B/Ta+NNgMu7T2uSH
Sf3WIBxcnYosYkR5815L+0X1tHIYp8pIBWSxp9SOdOCkJ1NGu2aTsH4aoxcObHzXpvMUkdHuVzBV
lPjmijiAhaYdThgWWw1buvDWW4yuSGpYfrFddBZPHSH+Xshz2pl5LNT7Y0KMQTzmaoUlro9f8hhy
OBWuB/L1u+L4IXYfP6Sxn3WNlP5xFVz5maiAnq4VdUHhKrFvyl326br7Vm5UxDAuWq2hgBr59CNh
JnsuSIgnmTb0dAknXjP7yDnyMhSg/KyTsgQsMA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62080)
`protect data_block
+cfLoFQEuK/WEIzqIlK/QCV2Pip6WFxMWcnA+OJZaY2xLvUzsIyCIffQXCOezHPIAkvgX6NAUQRL
x/Z6SbsCWhbnwloBXqEE2abOHIHtHxIDjBOkDGywmkEBf8n9CIf6xqxKCgiPyyIfB3qmFwYMAvqW
jjVG2h2czg/43ziemw/yQXjVNBp+jZuBJ4ixL+5yeBzWwoL/nH+rbbsF2ELu+69HU+XpBuxqM0J/
Is1UMcpF/nPfdzdoRySz63+2aH08QFUPotxmH1WNX1PP0QYQkghq8wOPmn5OoUF2cn7RiZgXqdyP
KAi23e9EyqUsRW+w3kGFN57Ff51xydxiiHDxilWa/pRwIIX0YVYJg54oQe7c/78XtcBGWkyfGpwb
auEFVY+MBjKwXdXZmEghcjA5jdA1QsasQofJnEyDUQXXHh2Expb3ZO3eHrLFgH7qKSXZWl0/v2m6
VgvDOLUJFWBJ2GNqDT8enWXpEPSryUV3oAn8CYf3RzyCUmSw1HocBzN4hYTnWuUjsQ9M3EcOwPPf
xZ4BVlv4cu+W/HBCa9yD+1Sjpns4IjhBmxlOjkpmfvuTnZpWOyLLfZaoLwjpqL3+//3NtaRUAWWo
W5/SymdezymeS9dN0bore8TVFe2NtnpTMtWznUyxNAV/TTMIyq1yl9y/Eq/nRMFqPPm+uXt5jWd4
ECnEWZNo9X/Z6lpyeZNEGNKCNWl7yWV87NzzA9Mmobn2/qEldIAXSjmywqSR2+/bRdLRYGRLjFkw
im3LUmii+BLGUj+8RqLzxj1uMuS9TpKOBb9NaQIbaPvHgFG3u4dOvG0CSwosQ4+lJKguBKIzp2Oo
a8lGM5UWW0xc1T43AqHpl5qOMKZZw2g+08WojMVeo86gH3J0t30hSVE7O2/gAajqa0JLkMlTmaqS
Bsj5qow1S/gczQIPSHbVDpiN65RM6M8sqD2e5gSuORBgbB2T2ZpJP0Dae9wMgwUP4wTYxegjjRn3
Bo16DX4Nmxmz8Dm+LeUlKg2SHuPaKGBJQ5rb8Q0zp6sMFwWl2KHOlF+TBy8eAvo+WPQ4xRQtnK0Q
QlMndd3rgbtPI9spg+YJG7eaC/CzY8yZsP9Wad9tMHvE5IQ+u7Ki5eG0XrUjCjnYa8L0xPAEikb2
Dj0ArOm+eIgEL88gRcLyMtZRP70z03Qy/d4E7uVrfrR7KwOcz/FTk4GTXUTJUYF+3d1iUNVR3Gjt
5HhHGQvl5y6rLKtYtpi4Rz74CZGEbWJCGcKcBXlHc1U1U40MN/qA3J6XzAFwncXa8rPVyuRXM6V/
c7nmmQ3QfIAw+j5rTLbClCNrZDzX2M/3kAiucA1lmXLm40KGQ2q78UGTjg6jNApg8yigzTrouCgm
zZLN00J0lVScGDe1Oe0V3iR2ckE8+YnfEvmTgwq/A9H4fGoylBv2S1y9N+xn7H3naNgbRfbu/ZeQ
QoP8DioA7Ho9JsJD3GwtQRaNOJoNK6C+Z50VW2hPw8rDGV3xS6lDavzfsuXoMDQk9EFB2nnMoIwy
7oce5r3IsnMxxHxWIJoViIYFxPjE9Kvs9NtsWY9w2s8PkuE6IZrO6UvYLeFXYKaMKHON5d10/MRh
NBgLJ3zjcIL/lDtLz19hS3PDGIxI1uaFFRhPiLAW2nOaecg2XZscsoTj9jDeD/A3AqvoZKFgsBpb
fkZsM+RuMBVwE1ogRYgdSC/Jh2ipnEzmO+0nvogNmmvz154K7sdSbyBalNXGZgoJCvTzYFnraqIA
nWt/TlZ/etAUbsSjKEow2rxaQuhtXQmk/UaCtT6hh/gKrT684OtZsgz31CyESHqkOz5pmUj1KjmC
NR1oFza4J4oGUWGDUOJUuoD+Ux0acAvn7DSrULjLV8YxDjzEpy9kT3wIR/EbainO+NmDj0tefOlx
GM4NdWqmrPrm0y0BCRolK0HoA2P/w1XZAYhvo9ENnmkQ+jlXozef3mMBui4wLfLxadS78v24dx/p
hxS1Hx7ta5SlNzFptOKUN7UT/VQfuTILlhSH395xJ7xzk6EV7CO/0mtuAx4Klx9VrClkOrHfn+Vi
V2z4C6UiLVNZjMaBFHQEMeMWZZam3M2QYZtcQBksx30AnnCJi5bysrQb30zFF3Ex8uoQNKCrW3iQ
q3yc839Vgut+H1dEl5CX6ICij5oukVRHm4YriPH3Gu6+VnG24TzTr+HSPRrw1ocQh59weyS0SNVK
iWPicliC1BU+6kpNFH9je1qaxzhZsKX9JnFrNBQpzoxhV2iJFWf6I3wd7khu+GAA66rDPQNX0X7L
dKTf4t9GMWrcurwBwbAzXUB9sXCMd8mZq2XeI8J5CtpxPwXkuGPEtf6MCoW5bFbehcjZV5ufDwVr
A7srlf0i7pG2E4q5+rAzHW2dXWp33mjLR9s51IDi+XVrO6vfQ/ncIpzC8KvNpU5/Q9oHejuTRYst
JuR8DdqX5Veu+eY47bTVUfaNPGmj3KU79K3I5bB29Qm8SBFhE7WzDzExV0lYP+F9Rtvbxiyw3RQy
X5f8zkuPgkzrCKW22ROuGF4b/yg9A+1DO1d58EZLzUGqd4oQCXi32UCH/hzO1oIkGR0qm3bBjgwP
qy9Xzk6gCQGo0v0OVFuvELcTqZbxchqIRSsdkVqgdeJEwKAMF7YO/cf5Z3W7GMpo8WenbxDvhKY6
LfWTKsgKLL65r0CChRcdlX1y7DKjehNa/XPDfKp+DxvVnKb+5TiqgBJZ83d5Qk6UDolN2OYZQDad
0VYP+Kg3G/FrWy2BiMzUWlKexN0Ni0EebqWVr/o/oICjAfEGNR6FPEJW6M7I2eQKtO9lNsvVuuZg
+JRnrnpgW+18BSDKCVHl7mOOg2ZNu9XL/o5q+7vHHC/x1RHay0OkHW5Zsm9XP8q0sfolxAX2686U
gGSpC8Y/m+u1S9jY8/J3jZ01YMO/gTkLdDtjbBeM/25/vDNhaUokQIwQVuFaAuACmcM914haQGEU
Lh/uuvZVpwX6zGBDE8XFW1IsSdigRhfbuNWYri/boeZkh1KiUfqqEUa+g3/iYfT7qvP+W4626Ja4
f9lQrE1ITkSsKdhIJ9vGEb9uwc1HZQGo1lD6Q36Wk7c/5AZnJkCV8K6FV6abM05atFbj8glWRtHe
5sflgB+tOvzrjU+dTTy9QisEjvdkN4rN88ivrcDY7VmmSqXBGgwX7Nx1gOpnYw3el314Ma+/p2mU
ZA3FfjGMm/pXDFRqsKxCQE56gDuONDf23jguvJqql9gtcDVFa9GCG/QSBvxC9mb2GcCZVcda2GiA
fE8Sma/37mEssGqFMQKOvrkk5Kc7PNdnpcBwfhZzZL6RRqZpaOCNY8osVJwQ59PH20S9D0UHT3nb
MfY7pArsLoqmiyS1VDapJblvJd1tpotgbYqsHPBLRIwlNZk8B2lW5JlMXK7ZljcxInwONH5H18Yd
POvpTQC70ezJkra2Qk82jF1viFU8cZmgwOq/IzvZhOwiAmJZjBGkoTDJ/bPWNLNci1wRq5u0LY0t
uyZSxXq1hdRpTX0cwciinWLQHwRicHuwxrL5gEptdqHr1G0NueIxqF8XRbpudPJMzvs99P9zVTyB
+35kYXLhdTccqI8EBWGTs95Oyqh8qQEQ2R+O+zqvEh4JISXDFktvp7Wb4RjcN5q7uM4wqd7SG+0R
89gv9nrd8MbWv1F2cpaMDpt3x4u2G14G3h5I7ZR77qySHQAMMsGMmF3IxYCjebIvdN82nQ5bkzBP
xSyYrZSQXghrdj4Jx4oGSTA5d+tWRpUC4Tv63Hl3VAVM2QYwsTBDO247URys8LYOT2zHb73QRLQS
o7IXhUAE2y05gA4rMowYIJ4Nayfw51j/4DGvtIbJ2eM/hkDEmbfbH8L0nDNiQbXzY1PfokW95BqU
5mm25fZiZGKyZy5FRF9q4qBYVSwCkD5+cZbmz7JIZ1v5wv2/Mw/8zROj1L5Cn9YqCFwmgDYmGOXJ
zE0gfZEofcW5wU5tNs59q9gCLuCQMCW6QkPzrGt19lmIyPKxDrg0s8VGL6XyvDUndHl5q4ZevyUu
N/daT+TGmlWAqAeXT6WJrAV2Jt2seqsmrroFCzu/5KgFkz+U8EqZwlmBzSq4/uWhEJQ516iR8jg7
Yyz4R3RakOBQFDXaZm0GBnGk9m3knTR2KQ9Jz9XK2sZrJd453TXN4foxYosqB5CgIrTDj36uE8ce
eJejkLPWpiJV5qbcBeaGno8AbQLhzmioXmy5+C+wG9EO5bV9IMCV5hkMHt6D/bKg450xUUDlwpV3
SFltK4dorndYKW9+RPOvlq25H+VsStESU++WbcLU+eEDGyiIn+kzbck987L0N5tHEy9Uf+vYACIh
8vMDJZs+J1TKLueGjy/ONmb/tDxm7i1qwuo3JkSEUdybhjEpNE6f3cBLv3A3W8gWyC4e5I3b4AKf
kJxxq7LRLQu0hyh4sryQ8ZAl78K/JojGfskMsjw7PWX9AUNIggi1uN8rgOBpwN2Xa44Swei8MB2u
e1u1AFcp3KjC+1m+W+RFHd0Q8X+6GUrk4jFQN1aP2blODAe98KQRigVuRTXyyjyd46S201FGlIg0
3JNEFpGviaG04vhTLMXA/G39W4Bk/X5vU1OsO2jmV6SHp5+3Y9OfQD3wgcA3kMnpRCam2FjXx2z1
5AvN3sxSEwU1cjLbC5wY0d1o+2KhZZvD5Zd/kj7rTpVp9mIYUw00+4Y3l3QWrBJPoM9nhLsXRIOf
jPdIK3oCYpfFzZeiFFi1YPLXFGW+AMTtGuAP3sn4G/ZgdRk/IYwZCpXd9Qpz4PnY/kFQjJ3Yl3ks
bZHMsb84fmdwUvd/ClTbF7VyfcK/UyC/vKx1tVAnd+X4eBjwJvQ4Dah7v6p2Zn3zL6WvnXxvMrxn
E965ORT4fv6Zh+Qb3kEQcOg0dZAC+MgX//p+v8n4/czEnWmzG9jDexDgDZ5wfCrKeyXousZz/P7T
8Sr1JSb6PwpZTJ9W2WRlYTz1h8aMb+yluaY/XZt6n5xPKRA+zkN0WswuftOILQgElWg6GcWBLHtD
mhBYoa0Ft0wNnpTvHj26hPY2l/LuO1xphMtQeW0T0JJ5TepkfSUltU+gfWUdfik516ejDykLtibK
mArrrKopwj8kmKLJRPkPXoT52nk+lkQf9sXbcJxmZtJgDviPh+PBtuFgzFRhFAHRDx6XUrG5gE2N
lEaL04sXuyY/42kVIEC32zasOYKKtnftg3I2mNj+AUoNWBw9U9k6cjKvbVcfDF9jM1tX5Iv0L8pG
0pNrbTd6My4bWhvTwcouB+CsRh/A02tQG47W6lLJ+E99OyAFvS0q14JARvr/+JZ7g71HPvzolVBb
yLmfTpf7yUtEzYzuw6Q6tVrLx+j4yoeZagHYg4GY4UBuHJ5XTOOzKQCdEb6JAOU7iFIi9aEgGHlL
rfEU13NDgQ8aX0BR83OKMN/3rFPIOynVUH2vScww55t02J6HYxvhwNIPEGTr/7IKoXUrvNL7aOZT
vTXbtqI54SQvH2bb2CJaA/APPHU8D/3EcN98fWRr4WOfP8ctAMj2fsm2eI4OY74lSwGZYHJ5piOh
Bo1nc57c4dycjRHEfXs+cfuBHeA0JjL4b2fQ4gxHgh8+Vbnrto1oheXYm4s8nKrnJVM8Y1yVt7Q0
T44zMLqQ5E7XxftvGJCHM5+YWzUjD8CZIlAABNC5S4Pfd32DPKh/ztH382C9YeGgSR8ZOGBORFl9
dTa7qF57Su+6QVqKnsxlO/nw2+kv9SOAFjTMlOWRmT/ZugzZxTfuAXlldFRnSL7yWLT5AYXi5/g7
RN8useqqtgj9PruouB8AfU0WU1YlQsy4eGo0DidHg2VIIsUEV8DmtM+WUexwu1jH0PtaNshAMnjz
iQbu0QGiV9LskzlieyoC0kWV8USVnYkUNMmVmst6SziPyKY7fq96XQujGIj6oJpYMIda05Nihoml
4NkEaMvT1zuwuRpkf5XMqbOZxYkY43/9nKIlRY31s7ugPxR0ZgVLdStzmVxeSD/5HP24csaoI5ws
bXzzwsljPs4VJwQlpC6QozVlPgjPpWblht2lvYp8x1b6MWLrMHaQ+03Qv5Oi7UR8vDrHqngvsmxX
ZH4UBSdr53nC4PlebvoNpUv4PYnj4AnxATDvFO8RZbD7CeRknlwVoSusx10FN7K+OBYBui6VYGXF
CpZC1D+Lzf4+DFi22giI2P/YIvCyarjPn71skz23quANpXUMCzeAIU1kyxNuxUPPXZkxvDRjKHdj
MBMNEQhs2vg1B1XKetvBk2EWGo7BMd5wNB99q6d1DHIpXfTwAcD6MO2jY70vp706pQytl9mRoJ1R
HUPofVryoXDFk1IEYS+5q3MQYf6sZ0305hlyef8I5HiyAL/eJstZAIsPPXms6RF3X+I/aUpVxIsD
L8SyisBzPn1ETvEcrbTMgMgg25MCX8t1uTBBetBbThBcZ9jQYLLRuWi2YBNOxVb4CFlRCioHPsjs
aAeHI4usTaohvS4DMgbHmP6QiH9iE3h+PFKBPGVGD7hcMvoWceNTUAvYFWtfHjE3k6nmir2z9ePQ
dA+e/g/7o/+ZCLkIB4rCytJUhHtOYToLFQAO4QiRtyL/6N65I+U0zkFHaM4SVZi++Q8m8A/68gWd
8zB9CJmnhv7jfHBOlR5QPJ9Ihm64l6rs15HiGNZy0mr3vvYsNn9yXP72JRoqZjifwB2/Flgu8Qhi
wAqiqa8EGcKaKCiwOEWJNZKxjtBwaMc71CKEugvNtxg5c+6zYDY4Fi0DhmAxXlNmmNuSErU6X7i3
bNnhR9cxYHCtQ4ZG4eU5lf7CKSCWXjW31KrR6uulzLxU7yzMgjCa6LKOSynz5om6mbuasIhcwnEj
jDdComv30HIOq6kx2ayGpt+C1H/EuIY9ExDZ+TN+FoCc19om1Z/13OJ4u5Iz81n5wvSCQhF7UKVn
QjSlEgRPDkydsQws0Xjti/N+zOICdg6PQ/WnAqzAXYY5+LmlSGc28yPVCmiqARh29j/5nDBm6WoO
mZXrq2iHvMVUX52RH0nrd2FFWn7fxAt0Jt1wwPMqeWu8x0m/5hszZiCPRfm3SAyVHY4daPrDNLS2
/GF/EtVBbCy1EFO4GhMZKZ3kNKoPv9Dxm3oi7kMQEmD+e5b31RoRbL5EkUXTov9QMkSyB41qA2E5
aEtrv+0m44gVVvkRYgInr5jq2CWqrq7NMsIhyYu9aqEnXV7OpHRkVZBJ2sP4A+iF3gi384p+3/94
kMGkzLPIcVNZxzkr3z/99R3ENcgalW4MVSTpCg/nPTw9gk3YA0g8GeKDDpif2AVJUZJiw+uxOvCa
l+qJg4GkLu+QN6hIbcFARgmSIRUSb2EKrGxIH9/RYbgA399GKEn6givD5cZUTML2+cIWuXvjJm66
fEmrkmwVIUA2cgFrn1bT/9ri/uDWYL1FIyHAm3c4IRUVmVuk1cgcIMM98qkvyljvrE6ROVSFYlHb
QIfg3AKY/2vYOU/kOcvasFkFp7MK2haQotB3Q4lCeGbJgroCm9jItO7sgJsxGtVHY9GCuMDwO+7C
OWOBV9LusbRaSAe5CyBH5EbbrI0JlRgwrBYFWRr+/9QWf7ALx2zKG6JUSQtX0PI+22bU13gxo0xB
8HbkIcXskXyYmjcGllz6kQ/xZbgV3KOhpJvqoSxU7Ev1AhXvXbnI1X01HEUzvw0xyeQ8ybN4jqRb
bfShwOQuEl+C+P9Sb7xCaR+Vx02IZRv89+XvbnaEtV+KLsd37ADL2jg97zTKW5nuR8VwLgghF8kN
qBZY4tTsIIryzb7zW8R7d7x/VXs4OIG3AlWqy331zxTkSERf72Ob1yQCG6zQo7SelmcojNdikafC
LyK4bA6jLzfbz5g+Q9tVIGMI8Q1dQMtawzkukCIJw7qWNyYqHPkyn3zdjxvueVkKUuYl+7ylXjYS
bfRVLwW7wJgPtHWmCWfnNdYcYcL5BSHdvxDjWUD1oDU9vbcJHC0enb3fhLESie6VjdMgV6L0Y4fv
violuw5oSNU/UfyjHDGAO57T6EpZjUt33FPvEUy+gzeXhbpxQ20Qvmt9Ld7tnimExxzrN2jgrbxL
aO7k7+x3LcCsLbwq8cbx7e//ZoyrHHHhhbzZVrGYyjGn+p+lmIU8C3TvCte31z/+coV13CVEa5Tw
6FM+N/a4xjFFsUalGqcJComZq/svq/yk1mhWn31CRLEPzSKo00TiDwpmlvQjOVvN5k1hSCaRer0B
/55Xki+GCSBQlzsAlw+3viePZFCmozP2D6R+cBNk8XI+7gyG2FH4hPor4XKldzqOKD9TwyPQkAK5
Ip2WI3JuhYvhHxTtuio0pgkw2Eb8rFRAFYSyq9W0tpUQiPc8Tjqx4dHypkry3CfSI9teH/Aex98i
dLUrQ5BGV7bNHdp9Usfc+0nXD/SKwm7lDoz8+hXE6q1fx9hZZdEg2ZqQTFjLeTzG7X6/akw+M74Z
ji3UcMQmltv/foL2uMHbeMw/V71cYeyR2703RPPiOCVreDXPuL6KqfumEY5hAtMtzlcv3gO1w4qD
Ftd57XJ+UU642ER1ijBjFb2krgeovM/q9zxD1ZxoeZHL/6hAFmf4UDrDkHBdZa/k6wi5vLGYP3jY
7LZaPis//Hw6Oie1AeTfdHPw+uY1YKETwxY06FT0+Rp/NgSI2Wb5iDBg3jLOOFC90eCQ64dAv+gd
31MCEJqfQMWgf8SqJpjJ6QN5y93Rl5GKk8Yfv/y2CjfJW6Htw9a+h8pjfOF8If5lW+M30otSVQSd
397IyWxTWz9kAVwyl78zAZbcbTCCcVY2Cw/ulvifb5/zdBTrgMKhTN5JExWykc8gWofv6q1NMCo2
w5u62UHzqcSTVWC1r+n4evzaIWoSTdMVRgLZ94gOk1kqNQaimLBQB03u84q5IhEoOT/PuiG5NsUK
orsMV8akRnjZSXQO9FlwVHnI8/9dv9mwDDnmtLgm6frKkELqzOH5YBJH+quh88eefNlVEoKSyC7I
BJBAcpTlCsnzWSiLee865Yz9ox/UjV8dnBcsRiW5qeZBXeh+CNkPDd30622LGUfue76OHdQASz6m
0xKi8B2vhQ7pH73ZMD4WNXppKRltPoa5WlaHeu2M7WVluU+JruPNfFpuPGNvmmJrB7T6TASJUFaJ
/t2L+RRkwCBUP7sNdcZ6+02naD3eB67IZeMuMgI6stkM1VmEICbdKeuisNs+Z/RDwQUA5pg+pUIx
EYoudGiqfCAf+eBIhjwc4zp46tgAql8HxfIoGoe/Z3YveAQtg/imQu1kX8s1FyO5ddrV500O5Er3
618CXbxsYdtwDIK63hCF9ZInErnaKy5uN39xV5Kd/oVsvHraFkkDBrHxGrzCqpi3QyyH+vu9ESAe
a19NvOui75NnxfdZrwslLyx4HUx+xgwe/yLwhWinSZFl3z+4H2i/kD5ZpgvWRzbV3C6LQCK9cGds
/u9MGqt9+S6QP0U7K48vNbbCXv/AcjXf400RSQBeUDui6vtX/6pHNAvwFQTDoyp6Kc41sGoIUZMz
gxFGz3DPNUVslyKdD/TgnOd8nUM2K0ho0ydwKOO5N0uv7rvzhhww375aO/nmWj0m1f3W8smMZX8x
dDXv1IQHkiQVgqhmZxtAGhuEOq0TIdPrJ8idLNdmf/vhlAn4LvjB1+tBz66sFy+ta8nY0DvW56Wx
IwggfeT2Ta+SbFhO/saOtLJ7hlsNv8IjiILOxixHXTYO6Mdu3b38zbwk0+HNc5JN9IrMef5jpsj6
F/VlelrnZCCrV+M8GBLx25wmYcQQzAuk+rVhdAkYBu6n11b+oxRmnYzS5pM9uEI/Ai04ccYSUiae
+3eD1hcza4+8x9XYbkfaJXAijOBon7WyZX6qH51w1qJ4cWFDvPlk6xdPIlAYZeBwW6/RTEaoE0w0
c0GDyMTbyjBtf3Ky56YbpBOcdBz5k/qGrrm90eYq2I+bwrBb+bd2UfCeqYbzUIcAelupL0N/xnx0
/m/zGNx3VTLHI+LCWQO77aIrdxtKjGC4xRTlHLFMwLm7SrGl+3SqyVexZZ6sZsW9EoJ4laHm5QcR
E9Ik8+W9CE244CgKi09uhnJwxdEye713Svq4e4SicwSpu1VxY2YTojJGDA9m4ptdhmrnUa2VGTP5
uh26HJ0gpX44KTCaN+FI/q+zSeU5our0xJeD0cGl+TDIkJ3lb7H9F14poQLx0dkPk/qnVmYhXAUD
QrqanU+o1HItqnSM/LM6mdMl1D40g1N8O5TgmJEKBWmYl5VtVS9OT+nECrw08rWZqqHb5xEWxyZu
mFDBen8p75Iaw8A9LiZOHFYkiaoHtZ6JKKiiVvQMx2LSlq1lNcGP6Keij5qzRL9CmDNKJ+KrPpS6
339qQ9Y0b199UV4r3TXjcQoIP6y3bIZNYh6pxL6Z7p0bi0hK9moesYAyzXN3jZZXV/VjMf6kDsu+
E25wtPQ5jROkCG6N/k7SEvRBCQlCpk6pq15djnjgsilJ4XyGoHhmnAv0opUDHAhWDMuqFj/6SYiE
0OFIPvZ86Kr+PTmBrbGRCwAWyaO3f+pYf0NkyustFwmq9EtS9JLNC/ir4XDHdseVxD+VNURDeQ6f
/XCqJd4ELtNPLaGzqxamtjCD2gMFZaS46Ym+p6F3S7fa8A/wi+h2HQMrUc+CKY+5OnwFlHQbYNsV
/omHNZhyBJVKyPPrVy+pQIkV7KhQw0heM3sT272OJH34oVE0OiqZeT0NOzru94/yTOXwtbm8SVRt
3SGLL7Lvp4coldodIm3Sdf9HAa42R7+obvTDc+yUUY3boZ0Vkdzdmb1jvDV1rjETx5U1fUCdIYof
Sb2e71O7lRf30pvNW+Aq4woXlDTlAA4+bNTHccfX84C0AORwgBnBRkMpODC5/m97euXdIn7ROgim
CYtYaFnFvyXlGHUEdd4w+VmtHls04SBLJm9cBOin+mmTizNNa3dLBfxGc45VVo++Djytk2JaKa7r
amwoQBt++7XCzIU2UCqlTpLfWA8LLTteGouz+U3QayU1L+zYFYoZ5qUF8OjHjz8Ccei2fC8j+ahk
iZs4NkBSSGjTsdnkrTEbphGqxxOehRSrEWtJlKWKgHwd2SdhnAj3ayq+Gkj3MlJonnmOs4eXbNEz
KnolsQ4Q0biN5rUzU7P4ogE3ONDGcEvvx0Zl01m7bUZM4KkWirrGd2LKwpd1G5PD5RwVRYFGUQHX
DOov1iG4jtd5swrh203VodSwX+BGpysxxbsHTb44do/UrHnjK062FSjjIX4S4anlUIBX5rQbyU5e
BQZw//WjtL50bSqV+HCJVx30/qhU/YG4V9UtQ5apSLj6GzGFPoXwCDnwLgnYCXlsMziupKST+GUH
Dsi+trgx1cIRTCXEmaSh8WuCzml8Uf24Pc6gCGhwclWCDlTAcrAfBd3yPjXd84rThhhoJZr3DMPE
R+6r7dNjOPjKWZjbxqOR39vXkex00ZbQSdPlsmfiGdphivs8sOCRjzledQlMEJ9x6RrXgxo6b+Cp
hBJuO87EkGyjBiEBCYsGv1DaAZ9gyfhEO6A54CstWnhFVSF8mn+yf7gr2zzH/5iKCXniuXNxs7/6
yn4Swm8nB+k1YHdPHLDW1CQEGxPOR8mXrkM9ayfkuQkNETuZzI56BUVE6NdCw2hq/ebN9mHE9nyz
Op5lTJ1tJWWTdxgI05IX58VDsrcM8Wo1gYo+IyWLTk0yLA05IDAYESLYEN1d/+ZoWd9om4eooHjL
Kfbcf3qAMw6Tg/rIoXKIPfOUvRhewBmkfRzSr/CfqT1BHNAG5BZBDEdLpaUff4Dv+I+oN9W3GVYf
Y5SmEqJEvJwX9nwZKd7baEGLV8C74ROpPz/Sr9BoEg6HCX8130rj0/qL3gkqOKyTX2xoEeqwj1lJ
/Yo4JEiftR72wkCFz3eJF9NbPh7cUSzBAnLVLKK7QGOR1nlOzahOXvR73BjyaY3tYD2LQdeKlc9v
ZjPnbxboog1cYrP+6/0lvWm+1shbRUy+609p9XBjNtNTXfOH1eDO4nqWm4lmadZylZHnCRBTOH6g
U54czqpsFSVpYV8gp+1C8fIn5sjtCs8BNISIqr4NRo6bzZs4SwSFw7OKF0P6cbK4zpqJlEXeeNFS
8gEwmUOtZvBcCLdQQiM6oWZ77Tp2Woj/vxpmFSZiWOLXEDNm2y+4hHbvZvSzJTXrgUfMHCC08Bbu
vSMGieClufJM1WlGotZYEnGs7bS57TO+xbZZag1UXrlC68Cpgp2/KtzHZd/8j1uB8Tvyh2nGj8gw
GUAOe9BSVMkHeWFvcbShB8rD6AyJeZotZp2uWDXeQF13Wea86eaqHbCPYS0nGiA7H8m8+HEX+A7l
Cf7yj3uhQHyLtUsVeTbo9lU+pjSkwpQbbbUjMg5TjiN2UUEd5QLMJIGFb3RdxQlM+cSF592QCViE
u2703lZsDcIDEdbDy35DgqV97/FX9Fiq5pBcnwjtxYc19xWc1fP5J+TOesc6r8kZ0m+WeIV3+Ept
rJnmM6HPHbMdkD/DEXVtLF7heXwl9tdK4hxEQ9kWC7e3gBP+fZFSNpOdyK9hLKvDcyw83jXFYdwl
juUttsPH5GBQLHUa3lqNTl0UqMLb13aNf4oeQxGfn/cu+bvu5zPvPEb3w0eAdt9RVI7GUL304UgQ
nTP6MG3ZknD3CMzhxVcvdXQI866NiW4NVTbYhgBJQIunD21B2sj9yXeNybHyOT3oUvwer7DzeGq0
vVAgE75/lxnklOPlWT8o2cdC4zHs6d9O2lC43obvF1eI1soZxQe49iVIhZzkhrCXbVInrZIPWfCq
wjhpsvaLDzjtdCovjlmQwa1HTSA8o2G4AC29UahXQxNulZptM+DKTaC3PwAoP+EsPevPh+w9kpzp
bfIZt7Vn2D0OqhyaAKvYf7qbXXo3qgsuF7OIAP7uCQ3ng2iq9pbjbCc3gB0VAHd5BLDw2efu4A5F
bqD7EBy9LsMLxSFm7hpErngNL2VuOUvL4MJMMpH4WNbsnInmxjLOa6gW3IKDGfsWAlsF63s8LOyz
4BofUph8iAgqxQDPAVF26y020qiTb1YgCAxmEp6RP6D7+TcWlTw9wnjB0RmSk4E5BYb/OT/sfQeR
5T9o1wzj/u525NDZzzfWccrwsauAjYP+b9TcpZ7cs0hCTdlsNQNeB4u9df/HzQygIe8jso53sho4
Wm9L8WFyiPYyojRf9i+Zm9RkMgd3Qg4Tw2ti3dH9Ns+9dYG2+muII4BmBPBYfD5lPklzUqQVzFp/
fhGcsy6zjGD8B12/j7z+MU+CFnXw4KKM+WKP1rV90HV0CIMKIz7opca4YbL3VglEPpiNQsvBUMXl
Bn50hA1rd2wrrQJTbpQSoN/OvNBLVJk8McGRPluyqhXetF/M9/wLoMP5f+f7uPNF9HeVte+m/S6d
t+EUwvDQ52y9Vdxia2TdFAdxKwXG3ACDsoCDy1gekgh2XXmOCRjYbRx1KFZd9D9nExHYfbqrd/gL
1tb16caejEedey75pSgEYs4DlROmANfeXCek2qaKDtVZi6yMfp8dixFRCnnKEjrHWFp6PR51sPV/
4AqD0B5aUTi6Jfi8icpz/u5B5gRaEOKYS1VpJmpI2kxX1ESeqk1gAgSLIbU9y/cxglBUzDLa5Jj/
ShSDYmV9dOzuHm+kfkZj9gLhmY4kM609dia4p1xOf/Q849IH/udbEgH17BjXI7OJmP41rNJfb8M0
pQdI6MiVfTeRV4BNaHqMLvdsdwCXeScjZK1g5lC606xtSXKHta9xih86zmavte5LgWUd9WxT2urM
LHNEF1xSzKleR7gJPCp8I4zmysCY814uPfNH2lbI9+Tt3IL/hGII07lH6P4zpM7mpnp1EzvgPIY1
djstW59pG1C/mOshRfroJzAsWm0Rzi6lGCbsUslkLRRCnq3YmcLvtu2boz4yuVodmL8xRvC6k282
NEwLKr2DbPY7aFXgoPW3wvX6HjGvQP5HECdRraqrPUyLSeWMK53JwGn8oR2+CiMJJwJLMHKd1dqV
9yRnNw5NKcj4R7GshKz9ogXK2gwFAlKX3W2duMTJCiVVTK6AwujMqRfYKjBkMT0PEYE54mPiR5Jq
PYrtfP9D+3rCD5EKRuU2gDirI2onP28KNw8hIWqdmVf50tUoPkaX/FYPWtX4NEqZLOY/8aYSPW2g
/Lxq+ClmfPaYlFz3WgAhLdPpvRLn/diuV8AmvpPn8KNjs9ZDW5s3knRNMWPgreM5Z2QZyL8xTlCH
I36NBk4hhEtdcRuouccQXnC9DTU17UxzgUBmyY1m3ESbUsTMykczIlIXnCkZXVVVeiZ3AwpNY3b3
QnpCiL/uI+mzkY1gfdZZJd1UcY937hMMYt7JinNQNU5gSmlU5OHQ2j670TRUFM/RcHxqH+JZNp6o
hkrCHRZ3pt+MdydQesr4tp3qPOn1d3clrpScu2AC5slS/aWSftasY3PtSsvxlYcXIbv/2S4BfYvS
FrMcneTC+bWq34wvv4hkX+iVAGlkhm8/edD9UA6V230fHVt4ipILIH56Wl6XJ4etuCYMnhsy1oGa
YL+GYVjAz09RmOHH0PbXnkHLU4R21XwVPLzgqDQ1j46NSkWz6If8EMtjJyIug3nxMNPO/DP0rAU0
0tQnkhL3O95MblZtjnAQZyYLUofr24PAB4VhdmUsHIDIjp3zvzYlj1cV+u/RmAH83BdgyATmVnIU
HNqht2Gt9SqfeIq3QDmHyllMCu9UgR8Q4DBkwlzGHxa51LYHfo1B7Xrb7Jr/jDgZr/wfeFX3C+gE
85YH0GgYg8uV/v9xWSM4emxEyAN05TkUybteUPHO9UXbpkO9bLPLNg1H9wxx5IU3TDf1z5fd2Rlr
O2f9Hk/LfNxaGf3jud+PFL+2EpkaTB76XfTlSlDMdpGXN05EqapCnJ/74iBegqGFs+n75xYxE+8K
NuESpzE2Orc5RCQo9PzfXCoppbjHnPorI3d0kKx31IlRV+x0lwuD4pn2nvq1hA4rRcnjiRk5Xg8N
bmdvSTIyJjTzcbBLxDPIuIUeLwHD9w/IE/T6km1SQx6wrznajScqoae6/FVwwgE3tq/PQznnnZtg
9C5eZt5LobYkf80v3QjdycdtmcExLD06umacv+DV9kquzxm3HfJ7b0zfvL8Y+1v7ZK8fUil4D9ES
hBXc+qIW9ZXqOzIQfV0GH3hCQVmh6zABVwjN/7YqJ5UmrIvHjd7jr+bEumcvLX/wlABIZjFPiIfa
x7Kw1S3f39VOnlfAjj8Mx7UzfTA5KNTLKNUU2RM2t5HhXIHwHZP3pDhQN3YwL9KULJPwbYTPx5kq
6gIyFWXDRO8TI7xfV7/f6wBCSDOx+ediAGsGn++ypr1p0bn2BnZoaljOMuYiBGi/m2FqOPJMayvi
4pedxvCjTeVd1juLUck2zfWxvrCzhpGmiEHpFa2OyYP1wyClAH+EwcunwC4WsDC8llpPGkjfSjqf
VJ9gLUzo1YQpcLCbq2CDxnlinI+p7HkQWz2+4NbG6+30oDjyoTnw6MWN9ozrl50LjDGaiFdD4I9z
d12e3X+WCDuv2UvhDhiDJ48OF7GD92rBVWZwFz7IOFlhJFaldfE1znszDWN8JTl2h8YdVatjLrnl
74KT5ur0/BC8sDFhmpx5nor3XvaajLHuqfAgOMApShAyVaF2WWoKgpaoMkfyRSrGg5BLDObhATeI
Q+PynrcGw+bVVDdYA0vwke7NUfcGJuWNJB5zpE3CV1ooqd/PmlQXec117feBFJCFQ0c4PCbwvxE5
qdygIDCq+uVSb+pRFjLGrIM8piY4EO/7X3OKU92Ks9nYlS2fonCS6r2tecpJkq1GMTTgMFf4lZMY
riRtZWzHbqf5HfIx63E9I+pzTEN0TbVM5x5+MfGchCyV5mAJJxV/OZK28X7bVyN46rfKoE+PPCjR
PyAh47d/xK1DApl8hFrrjoNz6ezH+rwU2S779HnW6zfLKDXvjsZYa6ZFpQHLMLssht+92JlahR6A
qP14HrwazIRvlVrRD6JSaCra6oTSVZ8T37/DA3aE22ZwgRdSdAinZ+i3J7Bfycg8sWjVfxatPuyD
BR38LoAEGx7MCJa8aRWr4n9H7o5ANLyvch45XoQvws2MrmLL0yFClcBIiogZFvEt4AbTVRuSTlVT
p0OUbi7oK63t8ewaC4QtLvciFbwdf8DTM38J5ZvpaWnLnE+zitvM4QzjC9AdqrF68Z+RBcbu6MVt
Qk4aCUHkHCEAWSCsqHwuBJdHoe4JWGmgaFGwjnc1z6zy4DV4v1fHhdJFMH0o+BGkcHgi0pjF8FYz
Ax2yFa1z+nygA6VAFUHW2k5+HOCnKBaxzIUrMNGkSsPOc5Lc9e8IC5ssNNTKFSD62V0Daau33Out
0g4LGAgJ7NY0RYxZN/z7pDhtHZVGlHe/wwBICDJ5ggOG26WvqJbfUw+fcfu4ptRtT543uu8ioyoQ
P3Fp3hKHAxcnY1aeijv4085nn0TDOh+ZV0QGkfKXfufrBRQkeHU90ZOxzONU+8+mnbfXzTpaC6Bi
vwdyoqgtxDs8BTRWbo0lHlC8+uwt4Uavz9R0AurJH4IuIkyKtZ6Nqcx4ReY+yATfdbcvFiAcMD7P
QfXh8acdKhyOhMqHlLSw4yM3pzP5ydCryXOeJWs+F88pC+LI/Vns8PHdaOytZZ+5t1mNMHIZFFPS
sAN3Ca+5EY2Xd32tzl9KWOLmWGKHmYQm8ZWDMbSnTwzLhmdl+Enni8JU/V68ywdgkaoR59cQ4ZbT
ovWFZWoAXoZpWARjceE7O0sd1M8mAtEQFw1SS7uXf1YdtKOWceSOFyMHBmOmwhz8l4DTfefi8Pe9
KjZmiqjKfdw4dFbRjmx9W+Lrv1qZGFblAEdTQUeTmXD9H95hbioq4PRKg/6Q2q0HMWtzEUT+XPr2
BQe1UigmFHW0jT5bReneR785V125FSooRTHlzQQdTYDOBfos2DAhN9O50GBxJvBwet44r9JXP3uF
pBth4xhP8YbrPuHunrfhteAdyfZWZcqAwICeaoQeLErvDZOVmgZJBdT2SYbaJMiHaGlRxiw/U8/H
/IqElrAweeKZSPNmB65Ks4BwG9FHcbUsBJ1l5ts9svjQ6DuRwLltF4ozJCWmiqovhmrmXTo3ku8G
eu5WBp4cl8hpD1kxBReQuXceg/GTl1vpVXNi3eYugMNV++RZVadBPuiTUf3geYo2Wv94WM2p5nwn
jBqqtz4cNpp+hpumzHQTb4iVqmA+A/+bWcAO0o4xvG5zqQX6+tbLq+pFLiqfV5h6mmYSN9beEFpQ
rfPov845craDoqVmRbPPOUuBMhWSUIOhfmtqM43gdpAUZRdUKMC1mMlddSz3O6B8eu1H847buGtq
KiDtkUTaiV2L/LBwwefV3O7lCMg10I+zzuJS3q1qbqDbduhNo3e5Cbp8PW0kRoAyQkrCz1Phbpkk
zS1qv4lQrNbEHQlLlzAIEJlDwxWabNSthy1Oa/eOjUTLF3guKZG/OBT6aWASaqo2WL6m8s3lBIS0
r9B+G2Eg2fbgxzEYDZY/5JmmdYUfPdTimHIZnabttdK23UmTc73d32sqU0Kyml0G+B5IY7MDt2XW
GDC+sAA32b+AvSJ5sS9oFLPW5jfEdMN6LBNioZa/iqVM/4TdgtJXjY72/Zdzc6UXw9tvtPWBZO1A
lbz82sVrf6xjTv2NdnaCss3dAraDKgS+nXXDssjUDHqC/YiwfbYl74fBAsNdNVfMwoRMDr1GgsLH
XLa7G86PXXYZzA+gF92Fpva2j98QWp/mtxfg1ORZd16NrNoWZlJfKhScETJ1HtiZtGsmrRJDkZbF
DCQsNqPh5M37r7pNdxNJTxDMPLhxgRy8xHcVANYcPdy9Lv0rY+9TuumhSsxRVhf3gyYXZfXMwRoZ
BSXpsFlfyLZJXgyqcur6z7t4ehUHtdSPRUH/E+DZW1OMDGPOGn0zBBUcm/FPlRnuo8nFMUHphxlb
BmzmfDxlWolLtOiUK2CL/qDGmqn/h5WF7pugp1+BnEnC8BU25Itf6GS3IZvhY0z1BNP8zbi3l1rv
K9+hl2OZ8NGI8d/+HDKKUMIdFE5QlvHLFAEpB2ZTAJ8kCXk92ijDsjlGpkawr4d1U2rt5oGvRb6R
5RjXbK4FpuwO/qHyj/wA8cyUVNwEZ9TshG7xv6g7dfF5mXnUINHo2SaXG5adq4ggZLk1ju6n4IcL
Tb16aycvbXZJhvYHpLn1nseCufyOJMwrAbAvV3Y1DKbtMr1/S3ce7EYfozGdzWRqau96VfyfFr7/
AILNFxUMnGK/kYv3zUeDb7lfiJK4XKVgOIJZHSLiCC0CawsQgbBIuojUMXB1s8q+g7CJMw426sL8
nEMBthv8A8VAtWlMnTAD7H1V58LS1xGr1jhtqoYC3UB9K9sOTb5yTQ7mxlYZTzcKQrA3ZhAPMHIx
SAdqYV7oPg9cjedyiLSHExauHk2KhaUNBRwJw81ITkT5KXguVzVPi4M7HZQz8JcI5tNO3BUFfxM6
cPYaOld7HStrXnkOHCvoiT24X6gmDDk4PGS2sK1TgPVSs8yKbd+tfyhqH33vOukY9Xj6GD0w98wD
5KktU/MFg3R5c8fW2jzpTx/2i+wmRigA71ryKeLqL80xGCxEhjtaDPO2C9H5JSz7wdXQswDP708C
i3E5ihabPTOJe7qpTgl2NEuPDO4bBcjVuE4V2RzM94I1V2hsfSEXNNuI3Gm7Rs58wDWVY+vocnXE
DDjfLkfcOMR7oPoYS2GNBUL+kMflHJ13ADBD9gBqUqqlj2/sSQ6cIF4aIYPUZUkckFpZ31UVU3SJ
sA0BX+PPkHGfZGw+SZgBY3nDciJLAyaMBwuc6bOVNU+xnJerW5mSML9ni6UnKQmoxZxcZHjTDpWR
VEaY9xloETLyIRV6buPwRMd6LypanNokXHniNAr944LbgJWNuC80LXh9JWIhOldwnKmraeq1hPdm
VWO1AHC6rNsTgo7LKJpRNVe3+d2B/y0fPetv2/AzydL2tDQwpKmy3jmWi/GRjf7zjI17yQPObXS6
52XjKJrLAEUDPquAF90U/IaMtziCxUQHeN3aV2JxuGF0JQVxnnSAGAlA9aP2JIqUjB+Nv0otXpYU
J+XoEc2YqRco+37oZGvEytvzdiyCKqXQEWgmaW1+43O48+UUDt6n/s3a/EIY190/dS0xxLhXNXsJ
gUdZd13yo/oUPq2KmdqvQkNj0RlVmXNZBWFyUhjcEGIdS59x5OHogohxsZqALKdyY0vZoe96oXbg
BDFk6/ohQwXDDCRTfG3TBjeCC9Gh+bBHZVneVRGYorXtvm9doHfpFx2sDqTJE1nxqoJ2eV1BHAmC
oZP2jnljzE1PuR0TpCvlZK41vVV/RxaxcVLjYWWf0DhO3jkV9bBD97oqKG7z0hwzgfZHmUXEy5tf
LkuEmg89olWSAb6kAiByCK1hbQtjyHbwPXi98Kn99NJlj60I6muyNmZU5AtU7By0ahMwUYjpv3Ua
0U/rJ/It6fvVrlHWKfsF56PhUbk1AkGavdz6NQ0xJyxcFnd1X4odz3znganFI3Gug+GYasdSHLeS
Jg6AjNGs8qIAhVaiOjCr0V3NSUmM9A+WPMHWho+5XceEDafm43ZiYrje047MKlozY96geOElI7tD
LTxxM5OGSRMCzwmGLpNHHuVAHVgxw6DOqQKCwwSazBdY8DCeLILpuIEd1nGDx6tBDgAHK0tAjtuK
Mz5E0sMghLv9FvJF+elUSRj2TfpV8dPmEDeIhM/JospOGxi0s82QJITZsBgU6Br+ti36bOmo2g0O
Dmys1aIvVreEA57rzmzfixXD0NmMvFoKlPs2B0QhpOvCzuWsvyaD06qocvby1bOiCIwcO38XKmZG
GGv17CacNWgyhjfUCPziZ69GWLB60s8c1kYoh81Sn/Zz4GnWqcNjStDFjtyiWX+v0AQ5lUCtBESk
phMGm5Di/IfqpiePN0NfkVpWIfG68gakXUK4+Nv+M+76XSqbxcJwq6udAt2zUkJuO1IvZncVqOzP
fw1OX7QRsbUcB5VsboYo/Qyc23EQwLW6bNgY0T9xmDHsqAIwDm6FFz2eerotHEWpiSNrK++4qtIM
bhLE8cVXhgrpgjDt37VJFa1ix2agrQ1mgrZ3BBUhVlPsrEKxFdbuLt3NTaahKm3Zu775wV9UPZHw
U1y81kH50R5x0GB2N+onypFysoG24KTHMQnjzjOt7Aehmwv5fWJDimXpoHd4llZmVMObppaXrmFn
/LKfX0/2bF8lX/wfuuP437g3jxuvx9gx/zTtjIhPCW2DoSSCNzevp6zRxT3piNA/s4V2RmnTzm26
UiesCChteFsSU8miPX45/H566yDiHZTdfDblRw/mEiKydZNJxTW3x2QlHcTkVzBRLw17Og+sSQJe
/y/3Dv8SJiXxsp56fISA1tDp4l4LE6GiMEAN0eLbSqThxzsRHsmruzUar1vnI+pkXyd70TOp2Iqr
nozv3eSemPjK/NsCmP5/9nPm9lC96AUJyilme3hRzC7M/Xqypmd4b/0xl98M5IHmb1vwapD/OPwl
Rl2JztoY/DRTf9lrWg/qz4NpNffVT3hHXfidFsNsiRImIyRz6J1yZg2+tZwCLq6tlVNOfp2CSl41
hsto+WbOvcT0iIKN3JjO+kd0MrKVqPcITh70w9RsIHSqnC5si7szXQKGpGNZpOGqktRxoEGmA0uI
uiTKvzoqUQXruSJVSdppSPGe36Euk7SvKZWr8WkzshbbHRzgtkYT9ac0m8BE4ydrT/LdiiwiLrIR
yusfF2cNf8J19Z6hMt1NR8bE921LkOm/mH+rUh1DGeCdvUgIwB/SVEQ7mioGI9u0G0KAZ7Y+miTm
i4m0Sn+FPRYzM9HYMBAXz/KYFoWp/J4siZlDTioJNMJbOtDybMbbhe10fbj9365CgT797nV/Z/CB
t4FYAOSk0WS5LX4ZjnQnzZaYIoRehzF9D4GGx9w+TcylNl6tuJoXmxhohA1GLKtdPnyv5hKHJQH2
nkA2ZJh+NLXvdciEI1WvlUlWHqYDiGZkoeq3zcZDr9LkP0vFZsWqTXpsu0Uz21Zh0XEQiT3E7GGv
WSG5JNtq+yN0UJyJm2iYGKIu1MATbQsSP0bpNyfC2LDjRvexEi0UARLraIRZjT2Y2X0QwLh3WF5d
iUKjfTAUuUpSbCERbC/wwGJN/8Q9s3Y/sB4oNV7t3VqrJZLOdvkmDaEaRv4gGUo76h7Km0YwP7zM
wNnLB+vudemRai/bQ/JBfppdyzUC+jOZXiPhl4QnID0fZVd21TH7jZrmJyP7VneSUy1yQvk7wFlk
b/2UUUPucQ5/m/8Mfkpg0rSX6cQ9a0mTS/nkkPh2t8dKXelfO8hQy2rAEUEKEoMgjEd21HDTFImF
8qrkNOpquQp0t09QZYPUsQu7Ms1J1b1uIY7gW0OG1r42N0TnFDCUzZif6sQ+XQ+mfTxNKzyfWNrf
QryNJXsEPrbF+LsViIwDsDSCJ55fsgWwo0WyvrEN9fXb/5+cD/VtrWtX6nzFm22NZSU1V3bPNxhg
ohBYz//w7Qahhk4NyqLuf8MIhvyjgFtwblvp6z5x2bRfg1AB5KbhjBZ9hufEgpVywTwerHH/lUA7
GLzglHb67oYc8gkIYQKDJiN7Tl6xaajDR/uHaNy1LJKo7WpoDbkXALXAs2RDLgqQxfhJEsB8kE3G
B1oi+rTbNwMHXoBdNM725X0MN7PHu7P5lj0XI49goDvPNdlCC0RRFD5jKQ+nY1CuX/GCnZ/Iii42
oqF+EYjr+rH89K8zgQv6sTJkOQxw3X7Dx6CG7+TgqKGxW6CLpGAB6L+fvVTOWlSnsUa7yCiVjft9
KBWtp4aOj0v83/e2UN36JM39z/8MjcHInbjH/W6C4RuNKVXYzVacF9FevbfL0lIGzYOOgbaiO5P+
Th9jSq9Mf6LFTNC+jdOVIWCNwTGIIK9fxkeBxAoYgz+80V/ZwQFfql4135vCq2JPW4fHBf+iWAoq
RxpriPqsMOG1a99KCtzrQ2c+szEPsrjnA++7XUI0Y1WNzZqE0uGo8Wyiu8+a+2jC+TY8TAVhY9O4
AXu8phxuzlN5EPuhgJTUr0yKn9dnE5qBgoXaqN09ASMgvNFuBwtPhXXyH6js+cUqe7oZ2qP3jRmS
CbhkuuSxR8LNRMDHL5CddUDBcOKY/uIGpZtoXX8on2kAfnP8VlkHgdyqRdvanFtBkCAAwkrbprxn
1Llc5tRj2kZM+t01C4QEV7c4gANkvNwcCTWhVu+by57n8GYLhNfD9YPSW5CqUJTnE5BkTGU5sBJ0
2VrJUqEZE4+oXqBQr21JJ6fsy5GanVmuzqxVp4unNJlmc5nVv2TukBCSkGRcXsh/dvlTnuSU2c/i
/Pjc5OFdTTtz+gS0LDirEvCd2xBfOXS1P4s5TDofznYqMw410aSyUaV4Xnr2Ijoah9ev8o4TjJcS
/a6yg3bHTeGh2jhadcLIlX9D/hl63cLoApS7zkn1DGdjab4acQATuz1df/+j8+KEqORYbOJ6kqm+
P7qy9AWjShUbVvGptnW8F7NS7mDNrv7kXmG7nurCUhKV7IND3nLFTr02MfvsJBWtv2EyMX3jwdHx
mWoGm8gV4WB7dU2YjSUN/VKHPSdu8RstWT5nJJK/RCXsVGKDtLQy9SqtCSh4Tk/dpZNoDpRz955g
kGK5ZGJgKiqQByrGjHDhMC3w14ycwCAFejOw8Yc8laMfHG3afta+eVzsye+vRwOZOoy7HWMuUMVi
zwuVjpYQv4OO6JR4CRfUrpjgH7NC81ugqEExPScvjnqjHQ2U3a6WF1eM/jZhx6LjPuBtgcGRZnAV
IYMZWP9IUNBPO4zuZCVBBmOZIC2OLaqFT42EIAqHwfyiLcLpOtCTM8EdlM0aZk2Ju8Y/sYDDxcu/
pTiGVEQHk4Lu1+rLVMbhueCdUzhRbTBGTR5mXK9c2mkkGx6Y6FfIGewILSZDPuaZ2J43KWTS1DiS
K2dVWyv8NA5rrZY+mLbjHgzn9kaE3cpFuT6cb63CHc5Lr/nPwWGwooy3MdYIQQtrgi2wbAzxG1nL
5pJLU5yNFHfsks9DKsBTjX0H8jgx/+od3uIuI5Eu2dyklskM/kRxatwShHzNLPmVv5SlcWzyJ1P8
e8kKJqpC612w7cDTUONw9rR5T7c/PUS2WqSwakwtfVVRVvJZ76+ex3C6izPIhfUJZ17Ney346f8c
rDgO1b1I5ZTkGlcDl48XhktDBe2ShDUHTssBmTv4DunjJYFOpmar88VqWLimAM+DaiemdL4MJ8JA
GbBXt7R4j5WfMR5L5uNt34z3A3z3HY2iK/514veljiziIhwteC8Krxc2MnBoyR3GuxRfgRm0mQ/g
pPeebCTsWR7Ux6Q4qHRjnM1SpiTjQqXKoaSnPKLa5VEFthHtdjpysMeCCfEe9Y94+ubdZfmUcvFi
USpO+8W9XIL8ZBuFmXQEBFE4Gy26hVmw9e3Qidjm8bdhVQR++Fydi2rC3LVMQ63ollb1befvIojc
my+8U32s3LyZvKPatpB14Mc1ls4J9tJmV26lAOGtHAmszV68Ug+Y5vZMCiekFFxCYsETCKZjhKJJ
23FACqLhTwx5tG6tYLU6veAA1YJ8a34Axrvz/KXOBeXR58HbeTEUqG4puaSG5DE3L+Q1uE2uD9ye
8MJCHvg+qIHCHbHE82m9h31P77XOPMnENIk6VM8ylc5UmYOAy89jQM783gw9gAQuwJI3ioK8darc
NDDrHmO4movbYpbJ6JTZD4c6kh/z5rh9Lmk6v2MTYUgXeI5OMKujOPqnGaQeGwd3kuvanu4ItPWL
oLP8aIIEZlIF6yVTv51yMov9cmgwx2bIndPmJV2wHVTBk0G1BuY8eZKnDVYo09hcpfzDlaEk3rzh
a8erWTAHgFBVxi9xP4ho2lkNxOWiWzrrM6XMBTnt37FfWLHAwQsDSZ+4+qsN0wZKZEKJpAwAGwE4
AKScA4eJ+NsoDenRufW2wKDCmHRKR0HI4EB35GC+hNRLLsUPDxbg9cDU0NJcBrxSjsF4QL9/JsXh
2UP6yciP1uNDvFd1P5Mv/iyASSKSErRuVhfjSNL7vZ1Rzz6I8z7gtjxw4IxbbFg5KswMplP5dV7j
8NdShi7ry9J+ohZLDJeDFwNOSAEq727O4J6CRtWVKAtjY845+KnR6yaxdz+qZVCM+yWzKJD8vkjr
+gJqm5cSM7G7NFRB0BzC6m4xqLC9viT1tvqHryEa7ZKsPYRsXW8smuErUZ5VkZVl8M39ZmtEe64y
GV1F/mTvYLiBtndYKaPJYcH20iM5NvXgb8rkduQ2490lhdY9zuUJg2C4EeCQ26aD3svVIndn5mBj
l+MwSUprmRWJGeYaU+cuCUGnJxM55/DJir80iaTcIAPv0fpzYc68VxLXaEbzvBA+Jf0JdKtyZ9RO
3KHHzZMbBoJYfsObUhW0bXl//ed1BUppB4bQi0b0ClB1YPfZOdrgCmgDLx9+UtKi/vdKAM3Tag7F
EFMeKlTWsyudDuNQ2xpWFFr6SE86X8/Ku8wac+Y82ft5Jnwc361jFE4rRcKhmwDntIKsXe+2wYIF
uZ5ym61xL9mb2yr/oTeiieIQKRzzE3JAFTZW6dYV9+pwEoVHX+waLAIgCPwKm9O/8Weu6TB/07QN
38XheV9qo238nk1Pr8ToWL7Jlj5/HWFT7NbmZVkWlw7Bqu1z+Xq1pD/gd+JnifrQUwT2rE4+JX8m
TvL97SCNy5fH2oG0RgbfuzD/0yONCv7OBss48ZhlU0iGupD67arZ33xORBMmDBFK/V0jkxTF3Z2E
eEd9NFGS/pME/IvckJrDngAHS945rLqZwsU74u4JyRDjaUu2X2JgIQYjHnxvgWhwgG5QY3hW9oJC
eh44c5J6twntsg1l6eqvIBGeX6Gj6RXbqg8fXg/KHTmCJ3zMj5ivzBnEUIG21dwzITudt2K4sNTh
0+lOLjAl2wbHwblh9KqgFqucOwhzaiCGaOLtu8zPkwrpL8vX1KLPiDk9+44+qFo9VMNDFdaKeWEw
bhAba1ifBOmkPzNo8PK08BAsLA3+Esj39SgSgYTd5GUfiBYJEyMPEQxdiER0L7fss9adal+rB42d
FHsgmAlE0v9x36Vuocfjh7EXGGzKdCj7OMxpl3ylogXBr/P/s6z0cd55ZAie35JNErzHEjjRIqr9
x7c13mBNBjSPsUNgz4qElVGOC4d22b5rpfNmIIeZ/AG2rl93wML3cyzX4FJRzhnElVF6jQdykfHz
RrVNpyYquuqdV07rInyaYDa8hDGVKz1heWm97NQEltTnglpnEvEvDmIM7CZCI9TXaEu3yysJQGhC
VlPJAkFciqQ+elvqXOHcClkRi+Rr4+ZXFMIcNepWdsCRMADvq2UOi8zgbFbnbfJU7FQP4uHs57gP
GY1hWZHLNQMcbIWsFdmvS1j6ubVWlH3ix+3S+CQwkIskFgyd29BrBSlqChOncHOgEBhwCoJzjja8
eWvD9zTIiYz3pYPeU0ivToqI4xuH3UV9gTnC3bsLz+wmIUrQwv4Mj7IlivjLSQrTTAG8DOTXqBE3
a+8WipuNgUhhCgaM83tt5jia/ioxBhDGXxNF1uhUwcig1XRG4wpZFcXi+6ZL+IfS1ZFaFivcw7u0
MfX/Tqwo5mDBC4S4hn9ff9IKX7fOm9ZsKgj0z/x1e2eyMdOxe4Stf2zBnaOWNJEuYrXDGxve2fs/
tnAtj/sLYVejfi0k8hwpcU0QlzT/P3ho6rEdALOwG9c9Mv0LzdnWA0g5UT6WazbxeOYSZYkxWw9S
YU5o6RhnqCaDh8noGQkP8ZaqPMXw/aL7++IYXbeQQR2BJLhgIvC7bXSzngdjuGst74pH1sZQV9i4
cOUlCGXIlL84gDaCyKxfzCXXVUiOkpydjBJI8ri0S7KxapwTVBVBV1I+eJlpAKqjJ6NzEr3C73DE
Exy8CPv4QMYeGiBEj7kDak484E2D/lxD/Dh09259qdWXfH9Iu7+67GKANSth3Dqk8XmM5LNnxICy
qlzs8wgnYflyh3M9ELQRkc/c6gmtuRmJ48sf+AD9JnUGca5P27vj0wAA/zpTUjEKbl83BuRkDsbD
Cfyiu/RiACdyjgszCDg6nQBhwQ6uGhlUFq+4vETsTIOdsdY3LnCjto7vRWyp33cFK1WI9nhyxuDH
janGtbNbIANXiA+JpFAXNbL4zImP886sodtR4FhlrE9Lqa10N46bKYVx6WpG6Tt/cMUI/YQvtZFg
y6DxbmQ3/A4uQqe3VTB20stnQwYOMc8F5EzEQs1zC9Ra6RzXYlbsxf8xgU6yPgjVkGZTn+QeMH5J
hb+s+HljyZ1VsoPAoBnlNyrBj9sud9aXfU6pyAvhwcjYRbrx7iAfQ3eCcJIL0hMN0ffNDaEHCGDu
4j8IyS7s7Z9JwtAiGl6AIDLEgqTCwwA75lFuAFmdrOFf37LXz/0wChHxJPzHXc7+iGxrfn25xLO+
vQBYaFp0Xwv0PbYD4YL20e9nWdlCbEQEc0RmQN0DHV6qQ/iGEpzhW4NsR0MgKAkYuLsLrY71pv6B
cBjtsvHeE1Swh32bVQWGg1Dw2ft2/BKL+BHyYmXN6fcyl7ORStqrEuudHe9KbrbGCDCUhp+rlOhw
ftBm7QW+TqRIAZjZJTlR2iztVmuHytvExv4jJw29UIu3I0p0/2pnoE5Jc8uV+4HnK9Q2NjJ+QU4z
RP9nhNPlqlhzCfTrQPCCLQ6QlNM5AMyEvgsjeb203PD58a84bH+OjfiWcNaB3Lb0GiyYcnLw68Hj
Csa9OdAdbYxEoF+O+/qygIpEJMotByp0KXjuPtVwuzdixKLGmDoTfJpQl4trSxkdm8a4MVIYuj/D
9KOxyuiNdX6qYdYWgDWzpZ8YC0TEOg56gudw0RzZhqeg8pfh88k1fkpVGTpqtN6LrYyEA1MA7/sL
N8KebQfRnheaFid5X/cpTS3Bt3zIh0hWvoWL0fAGFmZ+UD5dzr3W7Jy81+Zl7XOuqYIaHk3ErcZR
ld9EsA8tjjnAWPP6UapHFoeEG5VoeQJQT9n5Fz7PM+wSEKq00otx2GifNFSjDahMknpSe0RIfkG6
TNEPZDTlqp/unNLGmm2frYHLVCm6+yVt2HupTWEyAuuH2NSzr7jCWKEfeDtDu3nHKiDMJcZJthM1
9N2USO7srgprnLatxqgr9dqmv/HiJIUKUzxbikh/AnQ37gEl4kXrnNiv8FXFe4kgml2ykBoois/C
TTOkZqE7kXwvsLK0LQh9Evz+7agAO0Qnk0DZTN2fSwabNckl0ERA0PWIxTP2KOMBBz2o5VtKOZVi
CchIuNB22q8y9zrbP62dKE3CIODyxhd8JSrQQh+LyhWEWnDu/4ou+ziObYEC9fVa9rKFT0fDYjXZ
WHV0pSuw+or+hN6rYD2aAMkEyRb3gbshfJw+aHre4goL6uQbz1b+ydNzkzOZU1QQJyuv6qQfT9XA
S2SiR8OunJmMmqGkif6SEMwGOrfrkCQI7dK4hMtNEjUGDWfctJOD0XtIPUZl8WP9nvYFXOHnGAwN
iELlv3d7iUJ+iyqLAKab1a7jljyO9has3lEcAJcjqaUkVm4uL4I/xXZdmR+GmnRu1ruowiWWjWlR
EAiuoy0n/rHppCMOuzjs9fVv7pMMWfKcTQNMn8XpRg0S9RI39W7w231xBthchMNNRg5LHVbu283L
rkknt0LtgQhTjeM+aozW8FKW4gcxB6Xm97tE0ZC5Wc6GqkNmvsK34AxlrB/TyIXIT8PHiHZryzUW
4/v49fIoSWR8DDrD9wzTEicH8g6thUEzgj8gH+lRAYl+0ZHES1VpeffiTcMWiWkfGetFmgI4sgLi
UV68h8aM8YekYOZUbN19QkIPUz3qsHaRNPzXxYWDplbbJHrY3n2e17lSmYTbo5EU4hdsiDukLurt
AnC6ii2oz5h2x09t3CXlKJPc5/t2YWpiaxlXM0mQU6eguaV5nVumEn8tp1HngdWicTv9TIGY90Qm
LaHXhK2IIhNMkrMG+Qc9p+ktd3bVCWPoeTWybDvy/JGobs8eJ8+W0Gk4UVIQsaL7qSfWICTaqWH7
fAcW8Bs+VWbWzucncgaOymJRMHsnx8Tsff1UAlc4tgPKm8oC+q9XCsFgogrp4m9o4tlTnYjSwKmN
veoessOOuH+V8XFVWxd4jHJJV/INne86H8YchegevZoD7YZGVYyMriRBa3biOfj9KV2WvstzmnT0
Cm9P0FRxQKybWzV+dVHMnhjryeE1RZsINiHJBLgZqQBu00LlSwP3JzpTs7aRbFLWC21X9cbSeC75
cVmUdZteCp9WJeJJWrHqw7UWEX5bpCsmwBfZD7K/Rh7TWSpU3PRCgKoAYREE42yM4kFSY697G9cD
+QsyrE2ShRlxeh59zHNzVq2EZnoZMvZ7/La6eZYN7pq7EdT6++TsAjmqQ5ElKqd1ERY8HWQXCSna
mws1WnMi3aNCdtsMml64BPy7jmcsqXbxdNxFrMhYYZaARGh+7xT1xb2d06LxfaVyR7hn8HEcvkdH
D+FTdN2/JfzZmHMls0SpiTrQY29CBCWqOmAiQDnhwzOwVV2Ws5mOT4+qhWFTaIzS+NxsCXRMfNj1
Pfle/fAwaTlGUElZgKgKxfUahIVy1tATlbpdcfTfLc6mg+biYHrfEDASitYJawLeDjnd/cckvU/O
R5/x2aVJjhc47rhO1a7MMJfCjfJgvL9lZ5azbH+mo/wqcj5zcvvLkLLVdFbCf7KzcH1dwMHldGSb
fjL4xZYxltfm9xVcEfInWOmnWQZaJpeiJdqAqiHveDddchcBTMMGgPEbDl35HXk96sl3ujoN15nj
JrYjWF9tIMGFMaB7uRezhLa4vStDB+WN6DQnJI6JWFekxPc6VFC80Eci3q0mTHZ0hLjAvRziKHVb
22iQNVS03ArcOW/JASBN1snQzvJKgYTaMd5izUe89TR6zeOqiILhW6seirvtWv/abxL+5NKxL/xS
uex3eeT9WNx/Xe6+aNUU29Vkqq0JSSQpHzaeAr2ym+jLB83Hf49XbtnzhN/wgTeK00Wu2vqpI5iz
eX0lX0/4vGq1S7reV49ylG4dpmlBTaoXPi9DaBxwt0MRSAY0vb2QX2ncuDLbckprcVhW8YqGis9j
0+B+mplyOguWPFQduaE21K2PKk5c/fDYtpyfgnf2kVRAfF10LWxacdPGl8phQuJ915VFuLuC1dJM
pwkUpDwUk8AN+5DKUIM8fCMebN3+2z7bm+PhJfOaCl5H1LjwzPO0ZpeJkfRtBbCdlDpR29rVLTpt
inJlvUebbE6SxFkeP0vNmVjXwXYNAksYKGG0R1mE3vkmZcLVNmdx6KcmVEph/Hk/41XTrjaHtQsz
bTmR0hRHORhXB9hKBWgsucvxIBQQeFsCS2lVSxjWmdhwZJx8dyKICSCVBoJyp1g+07fUdw37p281
k7F7p3a3emZTCJf0CCO8Um1VfWIHFLoLwY7Eukiq0nxuZfJrt0fu2zEdEH1O1yuKGuiHxkKZZakM
9SEM5pOkooC6AcUpn7lpkIvi8hv4Gf/4GK5+lWTecpfdk4Zlxtab1Dm2IksRs/FN0AvgEgNXVMWH
r8Kca7P59UxFutsUtz6DSRZ8fWkUmLerZNNH/xpZjo+W3UlaN0fZMfUklhQjbiWuAoQ6MPZspKzM
If4Na5wo8j5SCB3b82sREE23bgn+rIksCDfBUkYYuR/BnLrQviTkQaUbCgTUy7aDasSP9gOSnaf6
UZMX9zr8uIHzgM2nQXSKvnBkajWyCdKwlAqzdi+u4zNH5Cao0fiBln+AW22mGk86N6ctsyG9e2id
7k7OYWz4C7clvKowDqIThbCwujRQyU7UtyqJPvii4EDo/7wAh2PYSNx7sWC/zbQOso/xk4R3NOAt
SB8F1SiehVWQYTgSVhNmd4khJy3CBks2fRqt8ZHrHKIocbhHvsdfMr1wvKitKfAgamqKWtbQS1FC
MGMwlYMBSvPKyw3hc9pyDEKE2xqP7vs4Ct149LEkjurddryKEnP6klRMCESaLiSK4FfrVWCt+PqG
GE4s7uDJOWtLuGXC3WVrT5wq1N+H8HduH1ILbPgqiJ/mx5Q9BBnwDwEkhl2rlE4xtrU4rxhcOHJ8
0I6BHOX1pYb/rspagbzP8I7K3geDCKA1exOHPSvd5ZelkcjuXEpvYvA5QbHOPOMfieSPXZM3/S/u
FToDjA8t8vVI2HWKnU++RYTds2wSr/1BO0EmG8kHJR1W1ynOH2hfcv4dyQRx1wK9bcBkIkP5/QW5
DmcNfD7ZXuglnW2/lBTJSiJeXXwi+M81eNVsf2Rx42qFw53+7p15ej62heYc9u3p9oqxO5VOeGuP
9k0m7EHWTMyntY7iMiIJuqslehRpTdhpBLE75bhqbg0DEDon0U70KevE02grfGtd4IiU8cHq/ukn
udBZpg0GATiJP9yRZJzKkRzYWX0NmFOphnwygCVSKy3ALib1yYTiskcq6B1yMJhxmvjo/UVmVnKD
s0XZ7EFSGxBHAfooroEBhEcltYKTRnZZNM1FKefQMNA9sZl772glgltfkvbmPmNmnXuPBcxWdAx4
EmiFop4i8Fwr9MiIxFdmJ9RHBqJO9pmKUwgn7KhlfWjVifcASNBTrls4AJ9cvHtQJlCP8OmYeblI
oKnU1vIcjSbCRcf+/LgB4xwS/bM32Ae02OMoXxgGpbnBK3ienEsTitKWH69V/aRWn/OLJTLBb6fz
OuourPPLwAepAgmcK7xaUitQv6S+MqBnoUl3C4ZksjbzJ/QMEomliakoEfNtWCf30ruSbjtCQ38c
VBzsdrCX5d2hEUzlrfkXLyZhAfIJTUDmCO6ejxI4Ec8zS3jGBxYhJ2o8cX8U0343B3iD3XfJ/LR1
OSTezCyIcYgxsc4R2Ce4EVwYT+PREgTditEeri5Qm9ObsyP8OSvvH82vsvOivl3kJGU2epoGDvaW
JoSR/3tQAYkXasZjGAXvIMiaDvN3KfRPWGaY45IBkQ2FX3YrI5WzxUBTdIPQJoRoYGkD3UZM5uMv
KrJhwshn7cK6yppKq1ias8GVFVSwzXUdm40SWonOsjpUhuP6AGq92aSDS7lQozKVVg9VYcM3aGVG
uzniPTF1p80yDB7AzLDyWzhrXfMlIXNnalVly/rMv29s2k8VE+xky26hTSG2ivnmhlDdAAjMbGt9
4P070k2lkUJT4Ymfc4ZncA+QuMWzZ+JLNPi2nr5ztAq8oKbu4xlKK76ro9uEAtbZ81DHb7MD8WEv
7m+yCNtgyC9Q0z1qVGnyYP9vbsW6hGa0BD+HscxNGXKVXryndlQTU6357AhUSoEzx2eSq/65gAPj
9LWndNj7A3r1o8espEi0Fj8CR847nUu51iIlmkehfJpFmdyoeToMPf3XUn7DR6Wi4G+0XCsQP5d9
kOXlED5rWKPHQ1roAOxRvEuoqiWTDoy1cm34f5AXahoHL3vOALPjrfVPUPf+6cVctrn3kIPwx/3p
Y6vHfHZyHMXx978RhM9a3YMbkTj947FlbZG6BsI4p6eyFNd4T1f+AAwtocCy/01AfUtA6AR0uWh9
W2IFgQInpdmaofs5INPITR/egyoQDogp6EgGNiVsDaCNeSK0bvmVlwYUMn9uh1bj3+HmMx+k8qCS
Nl3qXofjkPwO+DpHHrlc+FDkZfyZyFuDjRmRT7FTi50BhhOk7ba7C0nhY0K5wqQA1er6mJK94H0n
NjkIfD6ibvvasO930KOQ79VDxxL1at+Cl3xwJnIHW6ge9MsmiUQyHxVzKbZ1RpDczmhl0DEhOpyb
4QIbIJ9e25nQeHOaaEhJdtaMhXtHWpPzqUBKzexeKD4sY52natZpEWS1O+QAuo5vaquZ6GQiOOYx
qtVsFkw36ERyQ6FDdpH9g1HDVd5io8WSNL3qaDZKoSaBvdNX2z6LvoDfO5G5j24AduMquztDzT0i
yU9rTu0tiI8xB1cZqHYZ+3wEL2ACNXrOwfqPdgAiMOw6oB5FsT8KUM828QRAcJp1KIoj2aa80GzT
RAvjbx2ljTrbA3rY5eapwNC+hcVKmpvJCE7EXf8Z1opcoPWTY1AFvpNA43lx3rlYN66meiHhsH8z
x65vVFfHtAmuYbChy+UFmTf76sINttHXGftGInGbCXTyTN1mgDhl4RY4Is7CBC0Uy/EfJhrMYrdU
KHYKrGOPOFtk9oDu9/SWVOCJ7fgaIKcgNsXfPC4Rvhx9YXAcDuehZrL5mfn+H+5oJpl1edXOmymo
JdUMMTg7SPEpFyD3Zo4e7AIdPvJDbiEz+kkpRx4qxE66Z6mlF4+kLLTK0+gnZZF6ZlJMf6XyuqSW
KpLSvI+6Q2ApwCAfP14FOPws0X3OocYFF+zvtVA3y5qul4os13zrwsTfzcI1+Znpq/oxiTBVPN1+
Ey5TsWK8gd7qsE6uBxvsdc4m0FTCxC6pyV5VnZkb4Jw1dBgsZbZIQ3TLD/4QzfENlSRKYrgLH3Ar
qi/2yRJx+Mjux1/VMPIPCPsaI6eCz0HAFBcNmDYuCUpZT84XlbirQCXqSlwnsybWJFd0mHm7NtFw
qzPIhivbag+XRWYbfivJauo28i9ebGIx8y2zagSImDA7D0XTl/6ubkhK2TZuoVHVLDM9VENGdWmQ
JpvYuz/JO0856RQnHjEHebXg89L3rO6R//AJReGV6i5ig5mCv1Ic4FeeouilyUxh3Cf9v5C+YP3X
HZ7aWdBASJhXQF6bONRd0tu9sLrRGhAiGkVaUG4kOmEh72kuBk5Foe8BMvkDP+zpHK62riOfiVRq
zsiEyQP09B+ODSitHWG/djl7q4U2mTNNTHGzka63n5yzG5hD963mwoelbWNxKfYa2+NzvpC+utf0
WXoQLDUuyHT/5NRogUyNmYy0ZvQjdeqW8PlCwnrzuRnJqammUP7YaXtQnTk65dyws/ADR5ccKim1
A/ZUfdhP9CQrd5vhjY2nl7Z0mR0Bxj+xjBXvqwEusYExbWc3fUX5kpGgwQraC1LJIy8lrevC2T84
p9vddKgVB7RZy4uybMHA4m48qAugbH0XBQipjhvC4Rucja/m1ybXXv2ZA6wF8xo/KdjC1tss0zYg
A6XmDbyZllIVVT8+oF0DQ/RaK99CWPK5wbCfcm1RWwhs2+Z/OZsV1Or0ocA0a98MHEnHgblXzSCv
L1RwFKP7DDlvLtgMpQvvKE952yR8G73DvW1NCX15h/nNuDOfFlh9yxIojdrV/yQWP+K1wxGx3NT8
oQZHYru8JcPYI6hgSVVQn/nyYYIHCg47uvBaeEraEEx/LhD5nglknCs8luejVrxNOW+nkxS/kErT
3HKRzjn46AGHhYdci6dfQNbXL/s1xrJrllSePy5i+2Y/jwfqzHty6WNBQEgpB0sNp+Zigud/B2wR
hEmVHf12vG6NViEssHBfYph6bKhP/Zl6jQ7QhbvEbnduZi6dk3dYxfmSAEVgwP9om1It/aFq/jh0
PYy69N8MmqpI9B14SQXW5MhCaKMxluoAQabkG2roBAhzcBhenEGSZ3wxfnx9D4744RNJK1QXiRVR
L5Xy8/rUhMfcZ5H07G5kPPevZmd9uvOpGgY6Y44kTMlhf4TVuRsF7heReaiNbkXvb9cs7cUI0G0X
En/8uLH/IYtWqmfC3iEdW3aPaC6ChmTAqxOKCf0xkMpj3MpwlU5Xclv4rur/HKW3Pn6/hgoBF1TY
9sP0lPBn6Drz/hDiBbaU6yNh5CkgQ2qOtscGOhThGFEuRbN09FH81aBemeQU7hMrtkX2ACe6Fl/S
qFReAp1FPknEfABFR9Xkil8jsdNlG+tVNeIlVEdJjTn6fuPH02a+zDqvGCPJJlBobDDk+MBjegEN
K7gjHgo8u0Sz7u8oDzzLxolvJhqmnQ0xnWMkIanImwN9CThkFrErMOBJieUPxHFtak1GT6GGMMr8
Ght5jlIjbgeiaPYY8jBDBdsk3LZizpzUZPFu3H2WeqpgdJqurII6Q7jWCm8vc315tlhx4fy9SMNu
DpRj1WVr7vdj16Kb1yjgIoFydc3233ZkUwWV2x915qh+MYGGmaA/4WJ/pofCpwwg5ukLt+kX9cMA
8jcf4wZ08Wx7p2bBA2p6zjfzGbkLi0e+fegE5+PsPinsFrH1O2SX8aWC61cPRwubWKqQt8H8aBMS
y1EBK7vS6GOAcUM2DPMSefboIFX/vs7u8FgUj0QQMRuylq4A65wpd65dXTyG0UwRt3wLTq7CVvO4
o+8BfXQWRPztzHuRVRnltwTsXBdV05VwGtMQyRaO4eTk5dSUoZ4zqnu3YACzFX9fT8mU+q/SXqcr
sNL4rDczG4v2ZfA/+lkS170YV+uHwvR262+7T0GVceKnqBa/B/osEAv/m+Cb0NrTlPlXeI7uSTGC
61tvi0JaHKcTsaERNpW/onZajJPY9etp3V6CKi1YmhmpF2dseXCbeQa5gKYH2wDLtMft2yfNIcGH
cYvkUT99uXgqFJa2O1lPfhDSIWi0glDdZpXfSGs0bbu1vQDQmjq3ECu1rI3EFJNkqFuiBOR/n3bJ
jPheKZPkeTDz3sgNjVe50R5wQapky/Q1zbz9Gl4txnu9yWhbW71P4y9C5ux+LUSRXm9o9SQ190Ef
YLHIQsaZnKahHET1D5wTHT13M1slivxgxETvg97yJd5fgqvRVwVuoOTmP1ONbbTGqJaTyDvDXp8I
+orNi5C1Oyay/Jmh3fmEKV+TUniohvqKl1XlEYZH0Br3fX193LCJ7vBMmE36U58bz79NPtWUoips
Xk9gZHVvSebkOdYRrWuNKJVKR7L9aA7fF0BMUCvSpMXGOYr4fRcVeELuFFWPhugcxnzbx+85JtVF
i8XmzzNh6J3Jj+aqsPsG3ClGidCXzk01yW7CnP71GAgQavMu702GflG0kvywh96WxoijPEtOgm2H
sAKw2R1lyZZo8Be3ermeWX9FFOtpss9d1Du1WQ0tALiJNARyzstngPnTAkswBX8gPFCFECpRxSgn
DksgkjLhs1lHgiecdF64gBr+kGjx2nHoMACSh1D3L5XWbkQn2tV4Jfxq4IiVV/0pV8tlfd4s4Il/
rHHPGzJm7wjG4wLqQOhLa2TLspcE87/qFuBxEpAkUt8WJVxdz6o6VCFlgk1HpxB9Tnh2eTyhAIsV
TH8UFjN/7MjutDvh+191dNg6SJ2UQQcLMUwHB0BAsjcNDDW5DUmVJ2C5Z8CMEpVuQACLLUwtosfA
tXmZ6QunA2Ub5qZLPpPv4u5rWuqtQRyNSMihQP1yk+yWhi5d9pf8tynQUdoxwxpyO+OvZYWJn30b
2PamCSxp4Er3aDnsQIIYzZpgwEq5j5to9vTABJmQQy4/W6b3A5jFlTS6p1AFY60WSkcTJgah6+Hx
Wz5pcBt/hNOVkVP4lXRj7jSvYfgyfk1OIej4DaUl/NcPvgGDZiLEoXfi3i0+A3eIvtBM0XzQlxAx
pyiexS8nyjFrlQn+mgJynDRM22A85kXYauUm/q4azmSsyGgvb+RKAOPFlObU9A1y99utOvWpb0ne
1MmAdVKJrD5nM5wZw8d0NPszbfPpSCxi38xKpn/9QxDGjk3W7un/kKDslSgmqMWj87OB1VS64c60
yG1q6wRoJWanMDATkIiN0/N5Mfiqx1ZMMBbzzGfiyMGWg3g8e3J+Jf7+wgJdKNWLIJhBI/GG3gdl
AdaxOSi2kZHsyWocIeE+jV7Gi4GzvZcRK6wr+NYmTRuva69vocXo7F7bFqClxTc4sxBPYVduqM2t
UTXALTNU8OtNge2Lzfg/dq/8JHD66yH1lLkIuvqUfsdF+8r862BFanwZCTvcD6fUbwVvMR73Lebs
C3Teh6nE/4K+tCNsgZU8wVnwDcbRtMkn6Q1P3jtQ3lnsPzmJ8aWcT57nnnNGswlLJ9NeRJ7H4ISR
GIeDonccUeEjjFaBEvbQhki0Y3VmH0F2xXDmkcEyB/w9mtmagYZga5fSDJTX+M4OR0OoHEtca5pv
XcqRHfZ6ZgbN3EpW5nZGoxIJKSmzm16j2J5p1yq0IjiOcIdZvrWXjri6BWqHdYJ3m5u8ScBtrFTj
aLC6BAKCRI0QYB+l2ulqSpj/M0RM9gelxQktWsgjUTk1azQh1XJHPVo+nC3X7K5qE80Ld9CXwVhQ
6EkrY5Dz3x0qJ/at2eQyyEBiqz1OPaPYSvr79VT71gCTlNA/wNLZaXdCpVYA4DlyvYyHoip0Hnf5
z5sNKImoYIcpb6pWEU/GTy8P4KS1z3Es5h9hrD6bughS2v6x3JtSViL5rZIX8gXfxe+UEZGg4HOx
p8L3dH6gQytrbuHkPgpogipx0ZEYfC9cOwsNB4GMPmEUj8YYwKGE3qFBwG6pm4fTc0uBX90faDnI
0QTHBGtbVYkw7+l2gKQs01KctDzJw72TQrYZZMXwMGCIF3wShmhm9/achkNVen3KScwUc8/rIjqs
pkjiaQVwidmvLZx+q9DifawpIQN8AodMMl9ulAK8OzKHnuAI+vxStOI1Pg41FNYva/xic1pTi2YM
ikbY8rQI4InBrIjKgVhNH+XWQAyXwPb/b1dYPqEm1zKWpKAupIYGhUCWszD6QfBe4+yzrlE0tPDp
/soBu9KOEY9uhjRiWFQ0VusvB1XYhe26MWeTLrw+gMagrQVjMA13PM+Ex6CO7QEg2UHRe3xdHj/Q
xJAftKJhfGLFDq2eVCve7NSoAupw68K5ZXyDv/nmRVJhM72hHjlz97kdhUX1npmr8O7lOc7rgBdc
IXKc1qwGK1OsYJV/uCKQl0MWLku3uicMjK7WZuGOKxulydODagk8XOUcfemejDJjeDJEmtiOiNcZ
+dFgSSt8nT0nEo9dEFkhEBpoS84W/ow2DkD3ZluOTD+8d6+P23mv9poHIR/ln3nP4W7iUpdCL86Y
ufs5JuzaZwUlgZqtUHBIMhmrxq4ZYLqrYX/bl9jARCa4P8ANVhyTA9wuGn9dY29UTJAo15ySiiCA
f6lMJLq/AHENoYzdMb3af7cGImWEL8Tv3IY+6eL4JdLW8HUdpiv3sdjnogWh8rxPzOi6DbimIUte
FY24wq1PigGrbfAzhL7CDXAEfKNKEWDV6AWa4iX/fGRtcdYXHrHbLLukdh6NEdfX+wd2L0s+DK3Q
D7VosVivH1h2zkzWiF4m86x3oVJ90vAE1Rrd9hbdEW7YQRPC0+uDiuo2yNlw1den0ceLxPNZNZom
BKex0Jh8rynSmg3n2Hr71LywOoLmyZeAshxDoLY3zYgAgKWqwhs0GZ+qkREgRsy2LSsZ1Fbs5h9U
y+jrHpSlViTJhhu6AolnIRabZ/Eil9trwVMBZbd/P9m0aGW7d2u3yjglYBYm5GWdNd1JTGxcnaNE
2iUQi9bD2C3JhJ2Xfd6U9zNd7zySP2PE97PtjnVxZOReFS1+TZ01WQrtsqDDCGhh1tUVd+ZhcnVO
Q6bw5+QGP/vS5IcD8mNFP68sWTAfZK1CJzXoDi1qLyTsWy/DtOLicBgsjRADLMYl5aYOCJOqni0C
QX/qbVaMa0G7NEErA9mieo0EMIUNUHDYSLzGmPgRtAQeHz8+145+8w8PrZGntQPTt3Je/eAI9dQ8
HumODvBSekCoed/XGuwjbO9LDJXKkg1PDSCCnfvE5JmzyNXiIUB+V+GU44RyLSP4sFK7BFs/EGgu
7SCKLHdm+V02HlG2lgaEeyJy6szXDowO6SKfBFkx5g5xHUabkDGZ8bx4+HHzfkg16iDRlqxWzeZj
thlKYoU2pbr1xITLiL250vK4A6T4cFc7ESCz6LbPQFwTMtiW569yW1fE/oy9XLgc/6Vgwk10aHT7
zWVqNHfdzMqDYOB6EQ0uaSLo26j/4te/ts4tLBUlCAKtoUHqAsnncUPqOc9PUTpDZV7Jf9ev0UMI
n7nxXk6/KXxRQcJDO4aqY8AsXINdQYPQOIftcVX2/nVpOwbsFj/QeAsMcF2M7AiGkBImAhAmkMeG
i99eKGFC4rnq8jVt03zd/9YWaSdrwALvzLtRvK/Y66h20NIiZ7AHW2sFwgpyowuh4bckpY6p8hDh
8mijzoBUEZqi4ADeHob1CrO7T6Dl0bQAYxHj1yu4R16jL8TaiEoeQehyHV8pzF6mkidvJRNN1tRR
Q3A4BOYC/+KrAdH7bL3tBE1O1Lmk2rk/GfgO6wsLdcBqxExjUsuq2Z4H4IWyANbdYPWjUWVgTgXx
uGnbOFSbSSN4+u0sasW5jI5vVXOm85kcNoCbJVR9yDVGpHml0LkWCAox/U18vfGkE3jkGNULIRQr
j4fRNB13HFt21FQcWjJDRE1Yp4+gnKElfm/sT4rETLW0J+/Btfyn7CoipzJmMAhGUNKZRT/blQsd
hOj9ROKt6ek/SMwyKufhhGVx2ou/qmWstwLqNyCdHxhAd1vMpX0+DsyJX53yXvdmYS0LTVkEL3bW
C73VXqaCvPIqQRF8Ji0QUjI74M8MuQoC5mxs+w6q927vfkXvw/zBNqvXPJ7BnO9o4kd4sadTq0T5
oLyTWNtnLSkNNBBM9qXGBlT6VPeYAuw1HztLzNuqcQCSx9nuD59Ghh+jQB5KUP6VlDd0F1T8gBrH
A685UmgWkYARTXkFP7M2C5Ru7JxeaPQlebS09R9I6BUPmgCoMxay/qwFNZLXYsfRqT7XFb41SEbt
EfSe1KvJYVBVViau/wiNXcCA54MsidxcGAfwHBWUCVQcj6n/PglbMBOxjKTySu5i5ra/362ZXGR6
YWkdNZRT3di6FiFlAsl8LmeqB1mywLM5vKki7OhEf4xgSsQaJUXz01gHfe3WzXtdSfpkrtmZaf5G
SkiwvXxooWDB1FE8mWbjIbCEoXjthe4GsczCUYzpaGiU4jNyz7E9aMN4ha+9DlZDKdFM/Y34R2bB
gfyZjhyMsFAPd94sj2vtVXpUCZjAzIzG3HNMDTFE01fSWnSyBUvlL3O3aaMqFKfeho8jHQM59+3L
BaGVWl2KZuRh1AJoYZEuvr/Fv1gFUdO+M2ls1LsiP036hLccv9nkdeLBz18WNV4NDuAGgDo9pA4x
HznfnCk5xV73cdC4QWr7fMvKmnbu49ysS+thcR3NwYE07upRez7wggapz8ClPzSHoMDp6O3xFXg7
wzNTnyh9/3trOUOecD462S7StfO5b+lAuDdclhBek1zRGpo3qrLJEoxek5wcZ9lVWQ59Zic46rsy
yXja1Ou+IrjLPtWSFtVMS/khc/gs9DeaaLj8or9Qfrb+ZKajjG324gYJdrcu5/K3NojbPLXb8iGe
XnS4fn0O91+roHtTOSrEAbfWMMlmorEToTkwXbILXGwQsv/H1dDiwYXoFw/1WZASycwhhZClpAiQ
AAmXB12G+QBxv+schG+o1McpKrlLxNhjZY9y0Ssw+h89CkAHBAe1JtfrrA9CWv/1C/yFBVuyTJcJ
XIE3/+/fIbdKErMge/Py2EbNA1iDXGYhND/6yPSzOKniBfBuT1H7UwjVFdlSOztXgzDhKY+1xM2t
ZOOfigy9hZruS4YIBuZ+SDts830DY0Hzoy+BSIDH0GVDlcIkscm3svPR7UpWFN7dIJDQ7zIBlMPK
kWhjNf67p9b/8FN7waRoN7Qn9oBTN5Lulhci2HFL1dcdyftMLCr0lotMSyh1xfqYbR19fylAVAoT
yJFyPqumhe8XYq0RhkK6zmYKu6oCywPKDpgiSuF32rAV46IA6h72+8wBJMHeZQuCbxq/9aw6TMW3
e9BEIqEBurVAwhrI92nGeR2gAoJVpuuqWVwd+3iQE1FAu+AQCR8WsT/sAyZGfuSrevKPlCTXQGsT
j8gVioSPfPvPS595KS7YMD9uHU3NhqJMYwoCB7Mw7JsGFz+RN3vllawvGvgVI2Tc6waN0AsERaUV
ISdlmvbJtIB6qIyTtTj8iPb0gUSgj+JuLs31TjR7ooB0uk/Q1HK20jFvzeMR4SessQD6NDCecWFF
FpOlG9Yr+xxaXSSZurV4ZzInO8WnnJhnO7o2yuvKUue7zP6pTD9TfIaFdMMUWCWeuuy0Qbvqq4Fz
rOy9QpFC5kWjCv+KBCKsK6NQhItsX24UpiqoOHBkYN7pJ8E+cHVYaq1K8+IS2d07s3JB3TMJdMWT
kUAHrVq4HsTZsvw5SYB9yWzroDgNgjiL7xOizpWFgRBdnEfXiAzJGUDk1BwjSLxX0VeU1dSHyQqn
D5eQjpKzVz/ytQtAi3HfZAhX6EwuyuPPfE99crfnr5WrsXu5bC4PIGLFX0xhIjX2kWNd0jAKExUZ
X7BOZlULYVnOy603g1p6B++O+GL4Lbom0nY/2z2CqJv8sp9cl6TRsPw23o5LE0ey6VEIu88+9rb7
hs6ULmTe+Qo3vn4w3Jq7/mVGtcZSo8Ke0cLk6VkAOwQEqc1oKvY3ykwddfafZSgzGC/IxfYGUWC7
/usjkAeQ6gaAq6gbYIHfyEZpH2rjQd7CDinNK5v3hiUoqIrR/6jt1UFng/TVD4I1chNBoYKmkxLQ
V82els0exO63GptpmSwMFSNpAafopz77wk1S4gWwJaQTRZXrki54QTdEw1/U2MVmAuLlHvE1rz8C
A9WnKUpjFyQQVNTgU5AafpLdREPjmJP1d4My4UCcsSv5gmr+1QQb+2NPwwNtLiWJfBUSUfNo9eEY
87dmRKcTQCQM6cNb8g/8FD5NkYxsoyvKFNHcG28+0LuINkX3ygI+0F3XBTWXUUaLTvAYISG5WsBO
E/YRM41j26FspU1uGfH4wBQ9SJN5BSDkSp4fFZhYzVxbZWoLR+Nauuf28z8yb8wnTqV3JyetcMeV
gZDhgAIAwE0shIqMfq0LzyLhHt6TWKwxbHkt0BE0/ylq7ojJhsp7gYcaspMStlvZciyq1tnsekeD
jyfnByU4+1LrWHGoIJr7yzlGGpUYE9LNmt76sxK6n/JYoIjWEssc2Vue6rsMBfXA2YlghJ53eI1G
l2pcj3ya4CVB0VwHuBFTfL2EklvK1wHEsFsEiBLQDWJPqSCv5D/ikRB9RU0hBpYbxrWHjybgQaSz
gRzJOE+NnA71yrAZddUJGzJe+rf2InRxK3lfW/I4aPC0ceg1Xhl/HFhZqrFHLhmfg0m+RCcJ7b/S
EItYvISwUV64cPiTTiMSg1GbGOUrEz7bsUWqUf8UwjhLjMzwWzMq8wWw1sCPyuzKT/Cx7aFR2d8Q
IR9mlO/DHKjupJzPK/JvVg3EFws/6SgWnZJqi5DWoF37Sie7WkLwFYpT7PqXoIbfTOu+/Mx5Thgs
2FtDrN2RFXc64AaiWFYzHsigYPluzlkMLTBJZzMExkfs8D0f7vlB+yUzn4Hp+Dk9Rlxac6ch5j6B
KdZ6FcQ61oaWOF4pB8P9wDKo25Cv51Q5c0bcFRfkalPSwtwltLiL6L5ugy4zk4LQ9k7SJaajsCsV
c4OuO1+5/WFu4bdIwNjhGSKFGJAE7tQqYHpsR/R0GdeHPS7J0fr6UQI9xYrUf7Ifi4GiNUrZdufQ
D4NM+eC5Xx1FB4Rd7Dn5VLYNIqGJ1E4FmaRsiP4boJ2Jpvg4oW/LAyNC+ca6mmteDWrVInH5kSn9
2kLp7S4An5j+IOY/2AmB418RudnOOXJZ9GnKmdXKYAX3dpmmqPG6y/qaLGWbt1UvaH1ydNCvhViX
QaXWTWEaGgcB9h4Ce68dnV5FgCvAq3Sq73L7d92GuN4NX72PaucUCYbZKsLWZhT22lLNpBvOnZ+R
7hCJNDYXsPtbD4fN3IIMGWGKX2DE041+oN8PjMmSHZVEJmFnF4Rr+ZcCPCIeDn95lngTLJ5LirpB
h4g+3O4sCWT7/cF0b6ytt45V88jvqTHb1Z6tBenwEad6rXMcnrQN7OUmwCTvJnqLtH5Ro1lZmBfS
eV6OXLJbUnWeTYj3/hPHIyoIfuoZw0wZtckGR5wLrcJIE2OzrjFprvGNfpdH1P37ITg7AzOyUdYU
y5OplghpL15lGx8oH9XrR++LAe+tno3oPft3Kx0hheJCxVF36kCCBKmZej87Vw9igsNG8MesFNsV
mPziON6Zea08jQTRRcgHRdlLrEbQmseNX27BO+XHtXpaRpFOSrAe9n7sXHDlVi/lcia01s1pzIO6
6bc2yPIaBn3eBuwSoV+9+XLWQtHQJxtHDg6fpTBww7KVcnHosKBRaNrz/usRL+gnxgdnUOS+LjQw
ijpFNGD02hSzjp8582BB5jVk59DJBYyfaZeoxs6utdrmTZ2Tut9cnb8oOjdl5ZeEUmIMJwq3vLQN
myCagJYEhHMz/EPJQGpuqtWk/hvWxkSPpG0rjw1uvU9Wq2HDPY5aB2QpzwiY4yuJ9cWOEBLDxqWz
d+L1TPYUDl9YM5ec7+2fDH9/5lrXs0H7j9obGcRViTfFqE15qfufN/g+AkgIgsZQLTDHL6G5aE87
LhdZHuWYG3/Yb3c01OmnYPES4+1vgb7Bjpjq5jbM1Iuuk/4g48WOBHkFEBD87qv8zko0gA0alhhW
fBraZjQldoBejtoRCxTfLpXXYseiMazKSZYixvEoBynk/cTEHdXIU+ujTk1xx/BhFrgXdINIeZOs
8zzc/7Epb+FShUWdYRGtBCbs5RPQqvuwiVUxbSxa2GXZGy+5p5TW/8CMuuH6xO266sdCKUYqJK7R
NolZvjeB7ovdrJIvoY/1+Qw2t/KsDhAcmkKZ/g+0A3/E8Cq+ZBee20/lJv838J7PCdRBNLWVNX+K
UQ6ZGUD26M0YCKXukWPMwhQwYRhAjhh5JSfEq1lZervRwk5JGqewG9P/PGoLQyv0wdrkpWm1hqCE
VpAa66wQvyjjgLH6cK1ev/ZtTODSU6DcVM0tkSbhmB81p/IML7rSK6NOgVR6VI+kK0pQvyyg0paW
+L3EzRC4m75IZhTf96pnJcOaHM6IU/MebyaEa+9xiRJzMtY3MrzTx79qBp7/uheJPZInBWc+zp+/
q5nr9KTHT+nL/wRtLQ4VQeyVLlX/NkqXV214nxZ3jaWRB7QyDIBcKp/mamsLevMF+RuaB8sWOS3q
Vo9Nx+1z3am3DG6MEDpuZ5cZjdqQMTtwRAFZ88lfvSaLVajk6NsqsgbxKi0RQOQi3GY8Jd2/DuoM
krF/tu1pLLCgxn29kLxTtNUUR/jnxbUmUX3tZlSC1h1nCti2mHy/T9onj//xQlbQGQWc3uS2lbXe
nv/0cbPg0GC12g7YfGgdy1tLW/47nrSAhZDqKxMZZYA3/V9hLts98pHuJirI6zbOdmkFmSfYjhba
ualdQfmkQ2v8lYdfRNNyV2PCHDjZssIB5sLSi/LZMPdRH5h7oDq696mxfut0sPvRfDuf400bmoR5
YFLK8mYBftTm/HC8fj/Km2NyFEt6XwDW9WYzXZANObphjS8cVLTIu5388Yt41vP3h6GPiTdY2WKO
PjaTaghydGvT2oLwoAuCMTlOP3sU+cNz9b8OGw3QxKgrS23xdTeOY9JUuTqEjUeAZqGN5kGmBCtS
+/q0My8IWxQlMM2r/UCwgrDjy3+GhHgoBVgvhlg3jV8j1HlgqcLl5fE0uYv4dUP+EmfWW5psz50G
fINFDefPXRClr0Smsq8c9rpNPk2XhPajbRamanr/Z8r0sPepya/FxpP0lCELYxpv7o9Svb+oIDL1
A2yeuPWdaUh1N3/UbmGTd0cmao8+QSjy4hY3C3y2S17tGwQKE2g0jfX5grLAqGPcVhXxS/2CYLCr
RERtJgwrceG6Q6LHasy3YmnAKWEDcuCf47QnIzBDgWFV2nR6xJYdypOiH8xr94LspghPIM4iSPtP
7FY/Rx5dq/6CqXkg41SN+JdLQ3BSFusAqg85tOf0VwJLv13CALXpzBxZAn4diB6V+fZESB0WZfHN
7/g47RPdiNqmz6ruTHqURCDIl1MPulhkSsUFhsaW20KK0rPy0jRj38nmGbVvGfC/4dakuB+iqIqX
MqV7tOxCmG+PnZQxbg+UYgjBK+xCgm0yqjV2ozusrxc4b5PxWz+QRfbCl1M5+3sMY91t3OL3ttFa
vqRF90nJhnF5fupQIiCFM7cX7rfxprPzTKkhFzGBI2MePJvpHYfCXkoKJHQ7W7Km6ljHMA3XsgRi
Ew3xQr8S+IudaUJl+L4bLYhevu2gKGfL+XjzUVEgaGIhIokG3qVtqlDuJmW+2dLgMPIovWoxTtkU
+E5QfqApQ52iy8ATnsng+bvLn2k5uSp+iSaT+2Pl4e9eIDMpH1V2yFsZb2UKqGbEiqEB0yN/9jR7
KBQSWOXzxqVuZSorf5q/vFMFVpFE44Em04Xkg36Z5mhgzRTCSIGi1eq6F8KzADWfTu0zpSXdw8aD
Tquex6QsdWppVme7v93n02GtBQ0D/4fxxTaRPERL4iSMdEib4DH3bxvEC4AujVsGnltKD9CkrvCj
EHRR4Q1BJHDLoDw2bt7UU7ufQoK+vTzbn1Meq2KCMthJ70TqWbv4bVd+an/D+Xr5nyKJ4VH5b960
Z1x3gLEjWvLX8xqUwhoAZHp2SH+cH5sQWoof27cotbBaViKoUaNDoHPybwjznjEfQCHDSSBg5qQN
viWoGa4ORGgUY6EbBUSSCUI/a3qy+iFfEju6Tco/uB6gEaXYy0Q8JahHFDj7Fzfrzuw/8/8WUNVB
XhRZjNneXTS5qdvSWPMBGQ+wl0aU/ZMsfYEQIrjbTWBZtQMaYK+oaxGYW6QyzmWtW7Eqp2ebNbmB
7h/iXTLcq752/L4Y+cEAJq7YW6bmMve/iXPNIYYn7aWGX5wZIXLbl7NEpf3W8OWkavsqwG/gAhSX
r2fjChdZYvYczdn2+mzvj2f2m2t0TrUfWfHcFigW5rU1spmXgLO/9oFWBA5adRIsDDe1GQhi1Z1P
w6kqK1k4RhyyRIfEt6Hw/8J8xCybw0Kr4q2ziG+ioW6eyvV2VZNMIswmXVpCI2hNGPr8R+Wf6Zhs
tU22D58G+eFsL/PeailU690NmFGxtK9m8Kj7nUSWClSTqydlBhYtRVIlORAJnOyIOz87KxL0t0FX
cPdGewehUdjUya08EeS+/v1M/EYyenXhiZf67B6dhFWwSg8FnU61y/ci3Aa5spRE1zBvWgI0LcRL
b7MwgtVxgc/vjscUyML7uOEk3Ea9EACJekLKfnQ8c3VEX8B8dnOpY/D20huZvryh274wI9OJQ3m5
nm16WgI7TdLHi3L0B91KeafVhLkl0RZIzNocJveLTwAThX2WyHqk4UhzD3ISyd32Uw94GSHOUzoy
2sszI3oMmat/c1pqUFn9QbfLP4mZSl/T+Xb9JoCUNg1yUtIJkj6MqcuguZ5MU20B0Yuc2JibheWm
mEQiPqKG+KogW0agxkGLVVfTC4XgffT2AmCjUOw+8wuL9U1aN529GJiRWvRD/kBEJv/JMKwhIozZ
f45D/PBwvaNxLkgzSj93RwON7/QQ+MQwpbtLKKYvPx24DQOLZKNs5pL8cynSaysFuc9mwAf6vI+j
m5OyVwHLnJctsL7tRWoiQb23t0vNElJm0+r7SBC1i1xHtbhanALMlsdKwAqmrXDVRbC0IwVPCT7k
/imo9asuUiEtxDFNyqprGOF0tJEj2tPDR5IH0sBdFg/nc5TsYa7MkWqM3mmNTouWjbRe3MCkVGGH
tVq3LrdJ+yKmeGzxvNjojO37bsw1AaoRiwY0XNRyqgY0SfVJZUS9O6Zoy9ClmXxqRNHiWFel/XTy
8/9WtOASVMJgA03RUUyahfAyCwpmmIDfi4091rKT1yKLso8LQMJ2n2QRmhszQVTcFtqUqJeF5sox
MHVAOk8o0MJ9jPhwVkKoyvFBUmyaNXRrh0x2Sw90pRK0nVpx4KGP4Gn9q//POQzWVbdimwV/1F73
eR31jyadCHGN0cl8s8SJC/GSlZIlUj8yCuMHBzmubTIIAKDPt8UDkJHyOfje0hIKJi8r6uEpnpVo
G891VheFHa8q83t6xAih1+RbTUTtXwsZ4vwHbp6JnBgJzLoYsQrDAtwvi2mPIRzSZHvZcAtMnEYF
4c25OvI5eoV7pl2Kbn/quJY3YrfwJIxcOjZgSLXFtXlWRp6yDekriNFx8ryttE1aBKxwNiZDpZUV
jqUz+uPk0pF3IrufPELK38K3m9cl0X0019kpKE14qYhCvJZSbLUGxZTSRRdiMCCCQXtHO3csamuq
XtE2KX81zuc7+x43wCz5QFmpqK0ql8XDpAn7kNRyGgo5G0qHqxZgi6W9ZvlOlQOq7ezMwvhMFq9u
4L4Ugyv2P/I/mtZ6zzvOy8dy50GZK39pN8JxPq0BZP/r2DCX6Gh75e6y8bF/D1BaB16RSuZzv5sO
S6GCnsTzj8woyUOeARysBke8d0/b30MxycDUn+RDXfqrlgTI5B9TKDkkuureUTtC2G0EBoQW0Ms4
oNWgXCwhnB0s0OATkXrYLy5xJNmjFR9+pbKLysSQBXQEx83r4R/OnuhRp6zMJX4YC6Jy8Z/5j7UW
7Sp1QisxFdG7fKBHcRSUUJrquoDV9jllmLZ6DsaE9aC/O9XyzjX379fpLVALB4+N9yMHPSZgoUHf
7nO8z/aXEuIspDL7oft0JIBVK9N10O8LQWzkCWOwYTzVFfWDEFTtv4n3tAR32lFu/BUbP+6VQm2C
EErvCbCtHWP6v4bsMHaXK5M6vxUEkWWSCazUsfNTdVv2IdlY6yC15kmExbz89QpxJ61GhjcKP/oq
sqnYjdYhOSspvoVIhKT+O831or2bMqRmR54Hxiuz0NXqqhQlfvrIaUhEf9Jjp7DDzKOZcy+LWTzZ
f5MseA7Ck8Iyn1m4f5+XeFpb6stT8NSj+0E6eR/5GA0ZX1UYjtVst87R+Yus/pNsZ21doeI+vUBM
QYjZiSLPAstp+EKnQluhP4V3eP3AR3wNajwIuYjwT7sCIGHcFAVGR3aWksH6RMMfVuB4kbmue7Ms
X5TUgfzNo+lE5KgeJkC1PVphO7/xQ9mCIhRS98QhcCVLFNIRolTpf2HDT+2utwtl3fUPH2XlYH+a
bpovgjksY4joj8l1TSgYC32zPZI4sfS/ekWlACY2AcLnSv8AQtadAgFvYGiPAwFsvXzNuFCHbkY5
J3k3+h6Td2NjinmX7WPVVd2q4lbhZZCh8xtQ7D2iqsSX6ANQV6p6yw4dY7cMd5eoLe+rzg1vXjbV
i3RxSXoCLeCncxnJn+lDD1oELIjWB39ieX5HgLzFNXQndX74Bb117Ldbd38zRGOYGLhYsG0nEYxs
YMJeOqTFIjroEGhbn1kbTmX9qGmG/I+vQxJv9jDfqrybGSlFvzcrgX0h/rv0AbB81A8C+UBysBi2
vByZCmkgwZjHKXCuAqSG4EH/5EoTMzllFjRo8lfkT/xyJj43fJKtV2VGmBajtKQer/5DziNykXVp
xXCIbLYWAShdA4NhvmBQsQSwy5UDMy7Dv8AmMZ3pfWxouISbe75HWJCnVStusI0uDKQbVQKjnBQC
dbTy19FmjCHg8jmmNsZCbQqy71VCYM98ccyO5AkwFmv4kh3bDyLz+fuBn2dHy4JGQV4Px4bwwwXe
fx02D1Whe6nemEkV0bBm3o318rFqm5DDdSE7wcKGVXiNhYW4BBatzxzqomPub9wNZbwVMibbQ7Dw
9SocSc3AJFfLSQk0otMxibGz1BEEIj18TXjQOZs1PDiG/M9vrPWz7gmkA5QQVhG922RyNJKvGTG2
YRLy6Sr7evTD55970IQdb0upHc4ZBq+xP/HWM0pAx5JgOvr51ciE2Q7IiTRNfffBWOZGee0373y6
JUmXEweaP0nF+rCJK6j5h4CWNAjlL5Or8xSC9Loqz4iZSU44Zf21J4jLR7wcTV6PbAGodg9NZdBj
1sBJmER3iMKMUOLJm0TnuOuQF7Ef9nFGVXKLK+4pUISvDNVeb9Nh+WdS/DtZw3rahuOYx7McEk9S
VWJ0GhzeKkaTGnij53FNnGbTw9bgOBAjLT3hzOYRjYGxU7NHcH+5dm8A0od5wHgNJeCSNct0E5vb
6fNbcmM3UsEvZxmFkUn3ezpIuomjO08aDwBIAqU2EFmDSip1/E9oTYAknj2R4wGpGkySXq/iTr7V
2UTSLfkS6+ZVZVCFhm+NxRrITmbq5wenl6gxQWz9lYrzEaUOtVioiPH9y0CXlhrim0AFsA9OPkje
kqHOBZEUx1sz+RpDFzbjpdWysBuhBYxFT3yX6lx0sSoPcg2pMpJ3R5oHKySdWyCYNl2QRDr/ZhTI
/ZKgOIb9cRtQObZlFEOoBmbJGkphWB+dIL3WxIIFH4w9J/c8Q+EL6GvvXrYJFoMdsxV1OgTRkjF5
oiTTSfCkqJzgMQlCckk6qUUpmvz2SJ0OmPQC+rcszFY/AayV1tJcfaWrWjYDYOt7JqK5M1XiFP7B
elwdpKleTEtmpUXg2tW17GhmvNOeK2bEYXZ/HNhQ0m9AqlYrbkrToFCgBXnEFGDq6FsxwzbwKKUF
s101gyQFU9fN8vX+hmkfny9M3opExAGQvwIf4Kvy+CxbLUe4wEu3LdJGya2ZhpMogEDySgESepa0
eyE/9Ax/87qyWvstNb1H3QcWF7coWRr39zJqzSNbOdht75knGdBN2gazR+TkQvFG25iumvzvKL5+
myekwSAi4rb7DOGMKlkWJLAh+0EZ/Qa/t2Tq6QSl86fjALQ1IWNUA1rPvZflUyM+k3/KFc2guwUw
YwHEn6QixY55iCgSw42BZMVdiN2y6fQ+rxDUiAggx6fMlrV2Vh8dFyHyO9SU2UFaoVD4xKu4uJhp
ijuQzyLTaYB2N0nmceOC/qPfWBWdDFHt5QFfvYa4RNm4MupwrCQavOIcYjj6qKc0ltC56pzk48xM
RG+JFHE9ezmvNOWQDX0dEIlLMjOBrYB5iKslzocCFu5Sq5TXm/n9/jUbR9obFgyxTjfOJwxMn6kx
1zSWLS576KMtnCfAGcBx8czm654FrJ9zikxazNn9hCvLm5OWf8tYLqCCw53UMgtWmhV3xx2Qrukz
ZKJu2GmKWq97URL1meBVEuvtEYwuYKovkG9cJhKhPKPFqZP2CuhlI6b8klCFQd3pBARKd/TAO7zH
BJzNc6wEPNr8OZCZyACB1wYz197a7DCcEKPyJOdvmiGj//AIM/QxKd5mUmcKL5/NClKuCgvLpDnH
a/ULR02ostUr+kH/vjy+9JHS5U7BvFuaSjyUae8li6uvlQxOwOXGR89spzgt8LRQ10Qsd6WDFC81
QHT8PtwQBYgFfWCk1RCHVlhRF0PHVHXorJ9Jf3X/7YAWBgU13bpI3Q11c0xBGMr2bzML+hl/CZzF
7z0odRZCasreticBB7f1GN6hRlZZMcqIgIJpU3DDIEfMAUYvSdx7cwaA8TkcmvBfGC4T26X22GM/
F1AzbWk/kI7TVaByCHWg4/3UHWnFhmDW7YeDmq8CpkR5UIoJjESkM9BA53ClsPYV46I2RZM0BAzl
06lUVKJc+R0bnjua3zGkXEGUeS5aN6SfeZUM1m+NJSQdmKWRv3rNIYaXsWhanGUc9NFqwjDGB/US
GdPcA8KXSupNoYEX7uYbfpzNYrEnVvi13tHx54W9ZXNHIOSHAQ/8cHnz9ExxuPRag/3GxxARj75y
grMv/YoQYL5a9b2Yi9zdu6ZEm9oiGWSlaqOVouSAj4oPVtdleZFSlmQzPdm/vUV75E7aRcV3JUd3
vgEjuj7juLnsSLVFU+9LuFw4HLU9UklqLuWgt1IpwZqY1dSKbrJIMVPQqMPagfcTPXC4KnejWIGD
lIvGohvdZStoVjoiM+3mySDzcxePz0ae/DhOybKuuIp3ScBPdKvv/TSR9HTGMlK56VcckPDmfrCP
IEapKmVIceMWVkHI5BenpP7/nP8vIIrzMSsP4TSLgeiBBH8Gkfol7xu4x/3hONJaXgoKGMVAeF8E
66kJ3eg2tuA5zosLKnj1XdANKjzU8C8FSXWwV/yQLEaj044uRK6GutoX9OHNV7xuIS495swY2Ap/
HwYlvCiG8SlSRCFRYhrSO2r87jBQlcow+WckLZJK/J0XoeQdublDquvG54D02IigEFtComH4gHnJ
Iqte7qLyZ7l4OGNQ8RbAAdvICF+tkB2Z8bR/QEvram1nPvJ1PkTQ3BEj/QoxnERG2LS6V1ocf+LZ
qYfYHpWKX5QY72hx0D0cTkrRcsAhpOiEC2mgodaJLTM6IF+PfQ+ACQQJ2Oqg0gDbPgV0Ex0smg/H
XNIIawgX3lxHJqJInxiA7TLqEqSvOsWMjHIhxSSN7x7PQPzxBofCF7TKuv2BPtBIOcCGQE1mPyTX
vZDWNOvpZLzUMhFi2YC+dSPaForAH6A658jHL+/o/4jSB9xpvB38Yz9i6I1zb3q9FQraK4msUc2a
xD+MOyYB48jvcJiSGyRGJzpCkKqDf0HxhkEnGMsv0iKdhJJ/xLxKj7iQW3pWjKCONyIi0gthCZPk
xlUpZ8lsB69K19K5uDIRGrdzliefLK8eCKiQiOLMfldhDGLCGjZ7FJYBWyCc/clCXD4pjrIRdEic
E5b+lEigIUofifvmOIaBuQLpDMcvTAL5oRGDD0itJ7wfQglEVQOSy0jim8eUaXoUK4m4jVdpb/FX
/uQUAeNijuVZ8xoI7P3ltDFEYzm+clSzTvK8iO+ML4UKuaK3fYoDpSuVDQ0wUPnjdINnvybrONtu
C/hMhEjb5PTYPrqTKmvGcGPv+8eG4MvTiyolHGRCsQkqcmVi3cktcDyVNKxIGQLphRjnxrtXLdSP
SFpkeDnA7UAAr1CnXFb8im+QDRZ+vSfvx3IwTgzpwRdHKEjR3ZdMD5c2GqwpzMz7a87ckdDpfpo5
9FZEp6s8wRaXpgHYExLhU9rZaeBBNuVUeFLnufnovB53BUTtsC6yCU27c6988BxZgFbTjsVZCVUj
ZkOEq0GcTdSBcehT+IFzc/UmZk47R+T1RppRfZtQKABInnNp5ZvOacCG9zOnTPC1xtX+wOtkPpWF
TTr9buCWYzFomIZGIxuCcKEYs5wmE5ppF2yoV7KBTC4TYHma5eLttXGW5kqSvZWBJA5jMItWB3zr
NI7BU+s5tB2ihYG8bVZ/GcRKOk/NzyVdlo1w5jYTNok5SECUs/5ChnudLw5xPp4Ab36ojwcK24N/
X5GzADBsEfDNkgW6JOz7y+NLUV2mn7Bq78r5rKkSpJ47aJKm1Z4k9dtMpssBYs279tlM+1D/eVaP
tGOFszw/LEjHwUg+CNuoO98oYU2WG/LVSt47NkXOnzshTc6FZkvpOzE3/3Llw2x/xxqIFbOPra/z
ZIaxyHATAnyTo7j5jma0DtdL4zIpA0ZiDUoZer1MdtwW6rxAjeRjcrbiC7SPYDaItde5DWhHq0Eg
E79qmkL1kpp5S0xYgl5sVCFR+bBCm8AFJ3U1S2P6e41Zkx3/zRKa7n/Qw2G6iutKjTWh7sTEn6jO
V35iZ4HijrGuBB/h/jlQG35rdyler05DRLK9VLYIfGHRmV9o0Mwz+g+sA1LG4j9nChCUFYNVflpY
eMVap6YCoFnhA3EPT4FReTwFCvbzaLA8Fhg5VwdLmcF2jOgdxfXXM0gFRje3LDndNuCvHamiX4Dp
bR6I1ycrg1+KbFvO7MVr9JYcx1nkLLOe6XJ1VcQxOQwXhtAJjCUvTPQ7yBbEPnY7cDUfuKjwh01t
fKLjP6vW+tRQt7J6VDlMVWmYhj2GmoartBQvknlyUfQa37b6Us7o9+kA9GarxdtZ1FzZ+SRDLZmX
/XLzF0ePGjiC/5fJ/61Q2qH1pPT4Pz2Ywz065HtyVkzjh4JF4HrlwsdETr+NFuvrSOHmLdM9kQ4a
BbPD/HovgvDYQCtxZcJvMSGXM4xq2g1ff8/tAB9HSK4Ee0iS2Pqro/NFMtmCdOdDMTTcwqNZaEci
Go5wYGy6BUKu/6Bs9ndxtzd4ML119mHQi1m1Z+aucV4sb2icETvkYUS8w6zNft1HONcOGkurva6O
SynfFNdkONbzg2j6c0dAe54qvE51x3nhSTzcvEGl024R3SbEtwgRe9qqVIka6JKSI/bLaY4mpGJ/
1utfAlAfD1x9Jyw52o+mywHP9HTZ4yel18wADj1UJZKB55TT0Ife/+TxOq5cvOgfUtEXfF9jDR2A
pdLgngc9HMWbtCZolppQQrbnAhAVcvKRgKc5dysUQAGb8G5uuWiImUPhGpnTMeV5lvfKtyc9Ugco
3cfVOVFRWRuTuDNjf+y1TP6ZOMblmISWg3/uO3r6SiNJFZnJvBfHIzUmMjL8dp++yMog2m7KN4xD
b0gAa6PAF8hY3Tt7n7rUC6TNmKlcx0UAKOG/lYGx1r0/jcH8PceU55fQvHX6g0QZN+odmMJ6sc7K
M8k9J5R/OzObJoGdNVHjujmTbD4plH/MAXH3PDYB4ME8lzx7BBg9r02H87jmu4ERyn7mEPshcXNr
W3rjLW87vaJWnkxUlS5Ds1h5+yaRtHlejKZISepK5DeUROYV76xZlee3X2u8CpwcEJ4ZogGb2sk/
r9d4zZoLgkwHQeBo8tcEW6iF+nCxZMXSKO7TZwfXR1ZGDVHkdkT/aXa/ULmsQQh4o63xvuJH8XIQ
6aYl5Ae7DZ5aqYo3bx1ZhOQ39rEkgrw/YUZSGdzBtxIYIkHFDy4VWs4nemVoWNR27JeS/gjG2Jza
mS0/hZ6JV0GnTQxtyH6yb2VuSXd00V//HkBJeZSh4sEaLacjHiKJ0iC7ge2vR93ElShrd4xwWaTd
DpqXy76H3lvUh1clIBhO7D2Q3A4i+kbdJ/Lo3JiKpmI9NrFYPo/N37sSnEyPkLWPk8fSpNWyU14u
Mk873XYU/XgQT+MTb/GBeS1wY9nn4pTvbsJC+3gOjy5hKHT0wQorox9rpZRTGcYT1IuOEVilSd4G
b7Mr0mHSUU1QGYwERyqnpvqP7x7AMqf7LZ7FSpM3piCfeEKonFsglRiTZ9KHuietXqGflVWwW6Qe
52QhX31bva2lCkYzxS/KOCsJgPOZ7cP17RRnRpZhBO6T61639xc1JVT1gVyhKYeAYJ/7B25+JaJd
e1xU6Y5zMUWoPuQ8l7BMbdyy+J4p3POyAR/7mXA7YXVfRcfd4jjUpHiTwHUGGyOZ+4rGHk+E8v3w
im9KQyAVheOWXS1SqYPGG0em2oTMJqMjLkXzn0o6YB8HCboGqcJQST8Q0Os/HSZQGubss4gkiHU+
HD5dakWMStTBtlBRUhjhIYGfCJ9cSfMalLHJajv+2cJr0sy6rcmlI6cbNes8N0qG/JEr26uZ+7xW
w2HJRBIf2UFcb+hxmprbaUfSEUtizjpGfTR3CpUGPHKzjjd7MKivyds9IN5CX/W6AE9cW3+0/rjK
fk5VwyjcGGEpBLYVixkaVANVdH3AZ7QSaaCqqEoRxKZTbY4+Q/XuD3X2ek469hEbvXWUqhWjWhVp
Q2RbclcnSadqZBr8OkTH+NhOLf6zf5sKP12EUQ6ZwKs0LyXw5hfIl5LBgEcOYYe6ajkGiV/24oFT
jsjWrHG3SBELJTqDSkXbX6o1pUTAVn/vDz2zHIxUEa30Ah1dw0tY5ggT6gpkWiu04/RR3GZ/Y8Ww
cjNrA7DMZU3QwQMnNdVDV03ntP8j2LfniTg2EisCWgiiJxazg65qyQ6bUc8s5nt/1eF9ULXdEqR9
cvGiekL6n7pBsM9WgblcLmSN9CBiBKUg119mIj1FxclJF0DC+zVNuUAPFWL7BjKZDvdeEElcjrwB
OdIFlcJMuh4kqizm4PgzI2IRr5X9ipWiG8vkfKbBLLWcW0VR8ZhfiICWaFy0Gb78x5xKCVBow2Xm
GTUGResHTuwB4wt4HDo5iYXE62YWAniP/z28jUOpj3/ZyixWX4AvkX/W6a3QwAQAtglOI4cQ+5xq
b0NJ88qdllzSm2OsBrxzSkz9CMYCoDss4Hbbd+hY0k5LbnBEqs90DKzCCOl+x6oOqUcylqwdspRF
lPi+3u9bU5tVQ0+GqE+Pmqlttn8J0REFM4KbU3MWpDRAZ6is16v+F1C0TT314rq+LChctBqvKuQh
SkgP8znvhbKIKFWDq4SbdXkquBc9XKxueLn26MOr72GPSutFCBB9turfLN+deasgldUJG8nWwiL3
JVmeFE8jyVBkN28rkFxOMtNczvurqDuLIZahIIO0mGCGoJAEJRR8pKjfyATOGM3aZuv/q5lqTNl1
0LL7KGIxRbgT8sEno3DWFaO9ZttCEfMmt8MPGmZYlYiGyuD6Eby53kjgJ2/+2uEYKzls5VUWVHwO
DIiLd9tP01F9q9KlNbiAXU7Gg0kwP56mzMuqUSE7N34Xdt19EtrhqvHuYZasznRtg3NysJ6HTdGj
KwxLmKNIWh4hfiVo3bQtXv3y0vxAoVo4DSQIXsgXkaglBd9OUM2lqCewehJso11+EyJt10RoXVpj
PhMprekHHhzw/3Aunuu2EydQcmD0/qJq4M4CuvaZ2PPvGLEuxSgZ1nCr7Xk01RHgGEPgfM1ASfeg
nagagbcal0ySLBtuOO1Ra0/JZCeKGI1uHEz6/ZTxBhSMtRHNwjATEOELekyKzv4HU7adzpYNtKMU
iqOe/afQwwExy+DPZqDHhheUXAwSuBOy7rSFPWwoxuoco3qwl/LAF4xQWAOkq3ms/JFAwgbO2bP2
WzRVyVrf5ycbZTqJZ4vUOXKXbCtEF5jT1pF+iXqEyE95dO069rjsbchXPT+0qSDxh+yC65b+Lezn
LxWHt1yhwS6TnQ/U4T4mexKaYIOeCFdn1Mm5wojMOvuy/6goHzgyTl2YTdeLXJuPhf45BARsuhaV
74n4o4xkmsmGyDCBTWPo9RaCqWwnF6c+ndg6PaPys1/6fzQCKReCl/XhEmDkFt17/bAwFKekgmdZ
mFHBe0DvvkcEJwLyZ1Qpm/mzqWAalWV9/ojJKxVDwgRqOMcH4IJnGLuDFRxT9RO+TXKXIdGQsUrC
m+rUIdwkOOW2BVRn4vihL7AXNwkmdi7fMp7Jzj5wh8EZ6tXD8u1Og84Dncs500RDw9Ov0eXq+3zq
0YsSjrpb9AJWj/dtuKSBKkEWNn/yft3e2w5xWFKRBqiACOvunC3zljzgw5vv8OPUcGX3vJW0NvBB
U3wcmTegKimKq0CehDq4SF2MW880Zh7GDGB2zyIFZuDz9h8NJvTaFIQVBmjrK4/XubeegUWH/X4f
I+xBhMigyCFXyEXdRApyazMtsD4Ogfdl34nFD/zJ2ZT9GC9IWIf6ta1AVbczz2Dj/KwR4bemvqxz
XK6NVOEa7KqJYQvvSz/Jzc9t/IgLOX5zl8ouGA7v44wGMIx3zItgG6r9TdshDV2tkCGP3N2LI/xM
7Oxx58FMa37mLogZo32oxHSW2AGYhK9oMxko78m896ksrP8ViH+yymXPNOC12GGte38HvrnmTSeT
RchJ6dmESbmqobPaZBHbLrl5y/QQicdyopEgnD2uU0PnDxW0ZxS834nqAsDBtWniKZB30DDEk1Cq
qZPopWDPNPB1207eDqdBQZ1sYvb12Q+EKITdaUCZ3/ZeALiDarGMvmh0wNNVyIi0y3/sRrcNqJuK
+Yb0rfaOQcKQ5kO5GA84Xq2p63D1N4V2p7BHAPi5GIRP4/OZhrinjXR9eDJNSLNSxCu9a+khEdux
078eSwCmiYyLdzU3jtr98Z7Wgr6/ey3tuSYBxpgURo2+nRp5V9DzJl6hYlx50+Tc5p0swNcUKpBS
rYFIy8MmKMP89t97vIrBQNExpIxm9+ix5OPO1XdV/LU3yRBbN4GSzuctUrwzVyzAzjCx9GoSUZkH
fHXf5CYyDDsm7Iu7UoTVSeb2I7MeBrh5KWPJsiPhUtN4flKTBM1WShGp8h2rp0+VrFO3pYj6TpYz
bAachnUGxSvw4oAUJsK2c7khlvwhRYh+wIWytC3Sa4v6+syuWi6gfuZyHhwBO+NtbPR5EML96n1E
EX2cdYISLFSniFmDbyjEt+YTrxZVFqk74eIc1cGxLWDpoJTh3h1dW8Y54PeJkHSCawLge4oRnSfZ
0d7ekc3JB6tnmMjY0GLqdqNbwOQxhlBdDcFo9EgBAIiTrOke4oD6UeDZHU7yyrFjzQsmf9mMzjyU
khrG8tTNAEIBEwkTUcpyVDnPoTSVlWEKn2EEspeh+dPxiMxoRCaCDaR7Bgig9HAfT5+DPOPqY7vt
9AdAKd90N6h7RrOFfxu+CJ1TceD09CanC79sFXrloT36Go7Ait3umTtLuYNGoljL2a+79C42p2tl
FIAyMpjWrKuLqb1SZUpLa74gihqpDHR1rH06RcQYN8VuVL9f7+qF0VxciuGgquIBq1A0FDmItIAc
69Lb7XkMhsc7rV5ZLptl40MNm4POO1i9oCbAyePceVJFEnjMeUhgvdBICx1kBhaJ4fqc3y7Aedyp
XlLpuLfwc0cO38czcgBtt6faLWbbOkAcO3Wj2e9kSRyDGxOP/bV4IWY25yqhC0mtwv+/6pPnQzKH
hT1/X3cRkzlb8/aVcZ63a0qlIePZbz0a9dMQS8ik3VpjihYceu0sIhC49JRgBKmDEHxOur30IxQi
9x4cuddkOm9K1YtZ5Lf6ZbtqFwfT2u+dw0fww+eUrvU1N3kDYFUu3W5TfGpP3+WpMzNYAuBS+wxf
P3gTX+eHgDuqJirt4FPG0iOciCjPj+7azyqmmfhj4Xnw8AVUVeuG/9uO7mPSq0It+HMZ4zrDxIxp
UKjDyOo2oC6g6jTaMvTPpnEMH0VKKksy6Dnb129oVLJnIAJr4zL/yBTdvfer8RJNVP3vz/LW7Tlm
Ilbi7MeTO9/7WMoBxbE4vQjTvt38COMsrlITmei9HNJmtBR4EALioD0K/F3VbW4JsfYJSihPX5Wr
J4ZFpEwZVK2sWfZQS2SLRCMGDiCEIYOHetw0wWiCEVjugcqSD+YjlraBeE0yU7x0nx6jcwX5IYTw
amZDv7oIE/5/747bhlkcl4WV4j0AXDSoFwHNHpdyA6L0+Yo3h3gphoYN+MFBAw3qaMPE1sxhkvze
kmlpQKjyl75jzbnXPyj/x/Y11dzfectqSu5WA/4nN9pfYak+t2EaNODeJmKpKpyXz5dEboa/9Gye
rIIAY0P0cKmDQ7bm10NQ7H1I+r5jKm9XGvJxlyTpjiz2vGXQke+YTMD9Mjzo/O9Ppgn+rfrW4Hj7
GwIRnb2CGOuYqOoMCyj0giUTIsxTqWfxWJaWSINeu+qUZiOg/NS8djHPzy56M/0q3F62quWgGogI
qibHQHjUca4597MKJ6vMcJKiK3ff5YoquVyBBZRGLrgurxu/BcgIXgkRMBF85LPtVbxG5ejzr1zu
8VmN/1Nr8muwgnFrPz9H4A1OS/oJqcWg6nddMqFlDhmA3FMJDon+zJVq8p3XdRM2rqh0hiH3NpSC
L2mRbEE39AfBrbufJuSigCAbX0mP3wkYdhi2erQ9FmQNrxvxeF0guiGukKmQI1rLyjxuwF9KfSjV
lSzbElkUrVXFMEUZD1ti4VZqfE9fH2Jwv2x4UYapPPj4j6fhSwXIl3j8Xkp7AAB2q2Ck5xoN4MuF
0Ue2zc+oWd7/k5vh7m3CZglss3FqTApm565UVG/y2a17YEWyiaVkiQksvv09XplPX2DRKEtpXAI3
fI+6c0T2mEjxpgo88gwfCpn6DNdwYcnb9JYhNfXqfSj4JxSOfkJ3X95mcwXhCU9kpVJW/h7pFCp0
Ql07LGCK1gOPqu6+Z02RPImEDXR69mBs664POYb58LHhT4MwfY2U4kUnDS0NtsQqvRjrrgx/9UsZ
U89FGXPQyY9mfht3TSnTgRM+EEoPuSqyXwhVJmEne8TEfap80iS0bYUl084QISTPvuh10yLMeRpy
81l919ja+W9vID/EWIMv2pj/beZKakZj1l3bZP+KYwKzYQDVSF08SirH/7ogVdcbXgt4nYToRI4N
ucTE1VE0pjtElSIN4pdqa2bS/B0XryEKZfsVeXcAZWyEW+XCCQ+9B+sHo2qsWvNxUz00cGrIqGNJ
M6ryqzzz8nA7eQpYMhv4yn7ZFim8yttL1ZtZ7L1FPme4r9LWCqdN6MR77BrsKktkM3keXV6ILvlz
Os1xIE/pG04EuJ0reTw+LMKBVxcyxEsbFmj5Fqlj1wtjyiQ8lXOhqNroBJ9COTrL47WMtwaip4Vk
vnqEnxwUCVaA2UpEgWpqN/k+dw/N9AfcSnpngboJ6J76SuZyeCswzsiebaIVXX+XB481IZe/zcMr
kOE8kOIVrhzVyJ9y7InrfmiyFBChRHuDxbiknhNqAfEGf7qSBzJUZmflo6gG++aiGWbMjrqpyXeV
operkcA55gGXSLS57B9/gPypMJ2a4qnRL6kTQaRg6HyrT77S+fjmporqn7zoM59mNvWqYpY/EGNE
EnzsX5/UDE/WcoX/WeI+u2KoP1gs9fnLrZLQOycgkShxmmyd6sl/j3AizJnU1/X0ins+yq4lT4I7
dve6akR7fsLaDIUlXHfYYo0t5l6MTCLI3htgMqjs3mtBz1IHmpEqs4xGObleZzWD0e0wcj3CNK0R
xOV7RfjBfJuoQJMQACjgLDKPbW1fGg4sKpF3B07H7qg9W7+4vVBCIStIiFkdLSFJSMFsYglZLzG/
PQdO5iTrmEuad/xj9kdA8/1ObNusfys6TRnbkqB6mTkWF1KGrpvEADbLPd+nJYHIsCKfA/Rp/ANK
bW/dsWSvEwmhsPhYTL2eBjVcDJc5GYlupVnNhGeWa/nV8NnU5LA8g/7NuWb1GkKMthsIpo3/lwPr
jkdQ733cOHDjPIF9C2dVJ5yHOMgAHBdFcyJMYSQPXtkYAJFcL+cOZUCVazlq5v43KZ2z0iUO3gbD
5bZTMFAp1XAoXok6jUQz2s2phI6mVaHrwU2FGMfeu02Q/057Xg66Mk0raGeJEh2TqpRvK30Dnogg
Ro8AZAxTK55WD5vcduYP6WLEl00nyXPAiLEz8SY3DQmbty/C2KUc2O5nM+2ashH9ZNem+DuAW7vi
p6KMWg+/9eCK/2nXioVn/GraPygHue6ZkuBfUnJ4lce8aScdxN7Lc+kpMLQy/vEne7zTJHy3llfd
Wmyxn6XWW+f7KSQy+kmxLtAa0Cs6FH+WhYBTmwm6O6Tcs6Q12uwExY2IZLERyat40mi0Sa8QSPP5
0AN4KiXHFSdZrJaAvHklouBQ5Cxmi+9Ul+RJfaYtt1JgCfq5YQWafn32DI1VhM/DxOknfMxu2Jyz
XyPo05yaCk+cb8FdIum0gRYVx+sezY/U+OoBcAeI3+kl6YCLdXp5N6wcWY7ceOk8+wbv4leuP5c3
4tCIYEsV1dlRy5nY63FndXQ972mNNmozhiuYtsFKGsgMFz8WmPStKV8b+4d6c1J7xHCkEMt1GpuA
tIcK8Qkh4OLDieOHaTK/tKbV8DmtWUDVSXAZ5fTw9tF1lIJRTGWle+EmNF71QRqJ405g+eG2QRXK
8jgTI1qzHZ7nywXYJELYX3yLSyiOBkKecLshiCSu6i/BJG8UXnqG3jk4Lqqk7oCVJ/x4d4VTSSfa
l811awbLf4gLeqDAAYd+FEPtKLLmTS2q4q/BIlPfjLhDxlWWlSmaHlvMZexqh2sbdD7t9eU3VSPU
1gmiKPAggq0L4Kc1uz+aig5A80Y7C8OYb6dYGb3TKfpfRp8qZJXZWMrmwzrJtXs925tWgF1QFic0
3oygz7zWWABVoCTpYHQyLyKBnsJj9FPYbfufYvX/l13lTnqM8jaIWW85mggRfyeI+4cKt/ao7dO2
Z0qnn+5u6ywLHt+JQOocVcWckZyv1My2JgbBXalEIhZvYSl1UGudSpcgux74zfMHnB1//gWa9av2
onNabpG7RSVgM/l5TzhmVDD4p8kBw88puYzTNy1rGMc7bp6MXThslz5UyJdNjlfbSSAErTK5DlYP
XrNBR22ODXt9inP9YjeCx9CMykMjWX2fHtmd6iM/2acYsyAWDNTF/+83Rs8GBb0KhahrRBPPr7iR
RbPi9jUyng9WKiMgw7ZY74eeJSkxtIlauknUBfWMOu/7teOvVgJJqBp25VCMakuA189Cvdwqx+rB
PDNRdw6fSY1qH1IeStrzOya+Wz/avuMngznS0Qxr/mI6WyQ1/+qxyfxfPvsu5hYVs5PGa25C8yBt
Q8ctLtWpnJs3/VeaGzwBbZt8Cv9RouUckYPh/HknnrBpqEsXVZXGmIVTd2+ktgwzV2qACGk7p7gY
WSgKS+I6lumJG9pD8042JR96Hfgnx8ZdPq1PPbd+xtYrheBok2U/gmHJilGUECRbsoajfyMYgaJX
Z1FVl8bWCN6bSaansDxMKNyv/4ReRdZLM3/J+4Ongppm2tfBtMxFAiBdQgPqqj0hk4C2vH3rujPB
MDIaZD9d9fy7JWjODD5O3mL+pUSAXhWVbrIIm3W5yMS6uXz/KdA7uhiQu5kZCBfXsV8ZDz69L8eD
7NeT+6BhpJmO72tgO2vAz5J8z2ztFm0S1ZBtPQpvkq7jCAQW/MBrgzZ3icTjHgH4br6kCShe+Dh2
deiEj27dOynxrpD0vhUMEJXfAmZL4j5UmuBHZ9OlT/hs5CnO6k+wgQofjD5PgmYl/euOpV5tRyLp
1CRb2yKXo+TJP6SDSyNtI3OGruNggcm/AlhGKSuGoRPNkNKLVm5N946+5CSaSMw98zOX2sr99csa
Ctl7IujqSn22krLmaawFz30wN3j5q3iZ+tRqZF5yK/PumpqipRUTdfYx6jTX06UFRYIYgQe80sLH
5vUpkdqvTSzJwsjhe7TIkJ9i5EIqYaH8TgEx9QSOtybDCIUxe7ndgLFGKj1Nffq6FBt1iRXzqYdL
w+YXv6K4yry3U8FheaAMGx6D6WhvP06Pz/JyEdexvuqx3Z/Be+sM/9ybQIbfCJAAsjNC9ZZa3830
0vXpe5/b9QYlvm+TU2BF3OC16Up1jW7zVm3a/XaKttNQn2J00yeX/IBYxMrbNIZaVKNBd8a33n5M
FdR8cHvY82TIVOE1RvfirRL9OmewzNo35cBPgS/mMSomRtcghsDDPyRzzfMMhJuVOU25O7Hp4Wa5
E1kGt8Yn+ReWGeYxRYrrqHMwJBN1tvzigVlxsXnFXccRzoOdHmJcjEAkHXO7G4TGu87mmfNzwmVD
dLsBu16jZwQJX5GEVpPofoCLQcOOfoPhcayJBvzWF2aAKDjK4zNzeiTUGe9j+VjL2GyDfF3nyEjF
/d5uqKygZy5kiO/qjQThma+7uGzFe+KHrxiTfxKFt0NSaBApuq7yHpVlg/KBCrCwetr7FmplHUky
RDPNZle2STnknJMbSboDucy3YfJc76GvSDrfOzWk9e4It4Z0On52XuEKSHQx9TfZz0UeyqhgRHte
0qKz8dBXLK3Yz1U2p3uh+GxYYFd7AG+MoXXE5px2v+qvbN3ovmCYeeEQsihLGVHvwoGSPHgvYYPf
sr+wJG0hMRU3v2kWTtqnnsPISZO+4W7A33BFvgMJor2IPq8YsvKTy8b9IEE/DOSBsZrIONNqTwsY
OlpTtsftZFM+pUGVYV79n4nVMAJ0v40vwOHloPMlBEtWHbbdhXvSU2tNjsZdpJYvkR3NzMVHzHcB
UHa1ryrx7g54xtG3+hmXTsjrS7Uj4cVnW8ivPCQTx5fGmsGtChBDFZC6rK1X4kerIqukKymuemy5
BAO0tjRdk3XNrQUZEZrUke3UMOnVRhGgO9ZHkq14T+2NsI4q2ATDzr+Hn/ouKi5SEvIWtDgbmHUJ
6VyIvDq3tLs3gLDYpsKp6boaC4K5h6B5ujTYZp3KnrFK/3mlG+amG/4cNX0RMlfZFiRGhZ3qm6I9
wRljrOdvsIxB9YP9EnxjdHsfM40BwG2wBPKCzbOBfg6bC4ZPIA+h56pGgGg0oIFv8OIBXAV5d+dF
8bXSDCnC9ubgmwZ6OCZ2l8y4JgzkPQlL4RCYBRtHU7SoxqUVaVAILEuXQqVO4ctvcuJsMPyPvDZ0
50+OD+uBDnqhqHee7jvT2sBYCi956sUzMzSNvhnfW/uO9M+gR3B6pBW4V5rtDw6kCpXPee6nzgxi
Hp7Y6VJrKh6F4k54PCHip6fS02UQZ2gs8RptsyVB6poR00en8xVgVOpOmaatV1kLBYm46sdX19Qb
nXzKv9hcM6/JtP3kslnDqwHvMRdGMyzJHEoUbsPE+7Me1YkohREZFZXNdG2nwJIFupybXfXC85bh
iAO6SUFFMtG2SWG60T1rLOy32lU0hVxNcMdauYHCeZFqoxIHANR7GzTaOS8TZUJi/Bx/HVOPq1UU
UYQLxpdaushSdk63LZHA+wdemZTYO4SvPXOUG0X006rzPGclfUNtVldsEDqWD4dpPMzCgI9Bu6aq
z9LnPYI23n0TqapNufuHGkPzDnfYJuKujCVT0cHS1KWmCooxOtud5tXS0ToIv5kAIFhUBh5+EMaX
g6ASFHis3rLdt6PIqEkz2K+6e6XWlmhBwxM5kuaRQIp0JkLArVjlRcMCgyUWCVoCCns2GdPt3w7R
9cLBCrBbaI/g7ldYQe+06O1kjP1TdSgtW9UuI/t0SPhFOnx0myJJn7Q/IGr+s7mtN2P4BaCMTy5w
5LOFF9SdJGA06V95mczZmJFS9OINWOoE06c7II8nJjrghVf4A44mBPMjZFOOWcYDKgnTq25Uq56I
NlwrGmvR22tqju33LZNoaeG6RrWOd8AxJROyEWt2VWoNPDSOzKfK2pblQnRrW/C7lRwHgLQXc1rq
EnTYplCmoxNtfCuBag6QB4qgG76GyndCuMTteMEgH9XErzgGY5Q/z/n/R2VTdB2jXaThSC3xGcw1
v2jbxgJ1fEzuRi4gV8W3DxMbLDxhkmoVl7hA9WqWUMkEHnefsQ+Y8CANL4Vffgbqba6SeIgp73oL
t/JrtCJwCDeRKNO/0QcxEhvHzwkMOacp/ZNi+Zw/c2/qM1GGS+Fe+O6NyNfbl+s/ltZOP+0ffwr1
n9MYJ/dM9xtOz/DK8zJw+Hfikw95tXDy1LOV6qUsPSyYNHOHdPLUKF0i+z2mS5PTfrk1q5n+ESAJ
TyUD0uQT41CWVkZ3prTgpBtoqDaxwDc5dcV9eSxZot+6X8EBMsfV46gQCXp5WS7tx45C9DoS/+IR
hE+WqVSHSVP76tZdNu6M3EFxraDQFOPNj8mH7P8DnHvVi2w0pHCtSl2gVpj9Qgpz41kjsRqsCFI+
zvfnCzAt4d7Tlm4Oot51+UbfBMzkeRx8bZNO9zlcX2UKyWl2B2JZGLvOKrB0ACq4901f2zEfTAzR
cn3ndmSNHcwb5VFA3MZ4P8GVhubA9lI5+4NQsM/PLtttCf1VTf+6JFXDG1EGQVOboO0IExJhu2F+
m+vwitaReDiHGRwDQYBUdsN3JDKTitT8EGxFpHg90tHAsA5hje9w4EcOkGPH79a+KL0g1Itww+WY
JzfILLYumBKs/VR9fi4mv12pzqLwm5XgI7yjJbSxU6JCWfFF95Quzt7ZNT1wHsLsFssm5Guej09j
EO3KTzss352et971q6JXxZChEzulNBgtBbcppNkuvnK0WcxNepQ9TsJdbkGYliimPePM8UTPMy1Y
32r8qC/Zc2CLK9iKULpxShLoWKG0oNfhM6MLTjvaBvmBrNlvl7mmsFHJe4B8ZFq+3KtCmIslaX+x
jm52n6Tsy7JZBxED3h3REXmxXtMhBUOrmrJycYknP4onToHY0J8ZfJY0GAolD4xOyq/hemK7wzhl
YquoWO50oICPbZ2YcaNeDJHP3wjxP3h5loqSu9O3AzsgOYViyfgj2Wr5u6D4twpNes4uOvms4Xkn
T1P2MP5HkVFZjCOe1JXvLT8dKzlxLf/l+DyJOZ41UGZl2bivUtzp1MDSHZYAQlGfxWolkvs1gYgw
fhh3aI54re+NfguyTREGn3Ue3jwqlpVHDsrJuerMS+DOud4MVEwDml9fHso/L6AZW4ey3+B7KIcS
5JLXiXUFOznVxyKsabeivr9PWEOBvRNAgeUorD2czH+0pAkKUGLOiLGBKemNfqALp2sMq632m+OW
gT3HLnXq8lhcMNlZE0qk32rvqrDcRZ7iYLjYgBV+3m0k7KyyC3KBHBqaSAz2DWLZcmrhfvS3zOUv
5wz/GdTd5eHTa206SclDSawl/auLMW1BwBOAEeRMp0aGXLkiWpkqdnnyQa5hQCJ1m1JFS0wqsCSH
1tyqcOb6kPtjKZLXsn5XQWGs7sA6l1Ta3Y9hZGdSkEauYKNQwJ7O+LGtEYAU6jA6CJHP9LRqG9na
ts5nv4NdPeb+/RRKKlguiPCo/Cd8oUTn0lxzYrdaDFXCp3zZzZPuuEO7Mza8fWqe9v6hQOwM3NBK
SvzEPGsGSpoAAo/UtGVMposgHyg58HAyTt/nbcDruUR7mrKx7C7xM9HJrdg/0+bSJeuW0RfHpfd6
q3Mf1LtGFGl1ERXGAnHUZPIKAhrbGwG4P2pmN5opYbQxeo4QpEvm+fVZUVmFt752pEA7IS34jJBC
zF+4gYJolu7AjjZdpiF4GmeADBVQ9uHyp9DLAZfE0eOhOnsp/CoWkiI04bLwitreh53X3l5pJpcO
faUtvnuIrnVHAQy93ZBmHe4PrErakmVEMhfGrv6m1542ZWDPanHZjOx3i37Wpu0BawchoXurocO5
HfArydC/usMb5ASfFJou6vKxGdbQklLb8Yj0sdvbSEZe3jJWo86lLWwIK2b4ocQ5Gy2HvO/QII11
v5HFtQu3pGC0LTecRFoY0lQ69uYILyhKN8a7qoniFELGuj729jLIeSIKRVNeWZ7aJpevJNnhzD0f
wPXGAyeREVkAbVajGbgn+73DeacyfnM5RzYANeeEjdjP4e8skEnZ6HMKljWfqUjPvsQujhzqRRU0
Gq9XdzN7h5w+TEpEa3az2khuulh+DhRSblcPNedX36TbMRJB15ZiuTnoVdhq7+NZO2myUkDVYIsQ
rRfoN1RvBGnfSkf/N4yt1Qs0Hc9buRpkaNXfPwdYLTOWikHkrU5e24O+upPkXMeomEfiDuWfds91
cXzIzQ3F6qJZ/j1n1gXmfHmnuTwU/zMfpfbla9Of/J3jpQ/UH+KAj5iRtWYchFM+rM6MAmwt2UAk
sivpMomJKVN4xxKMGruwbKYYyQ34+MjVhGAgNSEl3NAcNBLMqoG8YCv6R14mONEYA6L2VVTXDkTU
9tZeo0D6cy/O/2Fie35Ts+K11mPwcDfVuk2x6buCnda05yI6eKPfCu/6tee6KZ2QVnIXblA4ugEq
tNhGDoDiDI4dhx0799BmdGnLXP/7qPgqSFlSrCaZt2rMw8yQ0f7/9nbI+yONJqZHNUZ8aypYI09i
i0org+mRlZfD9bdWw87QoFH5ZmqA2vD3AzTraem24SuV5QYP+h3s51NWI1sJPSe46G7kGIKqTnKJ
krVfQUrZ934Leh81gsWO6vGFS1s5l/NECILboLewM6LX1SXFFNKylhx1ry62WlI/LTl/T4kX5toF
toipKF4f0nosSothLyPY7jDwAT/CAKA/d+t17RS1NTVvsjG3rz1KcBGQ8fWZYkp1AZ/OltBFGM/H
VczwPcIQj+yFiuRJguO0hN1w/aR7JroztESRso/82JpB2TqP+IQFALSyc9SU9Aut1VB4woZqRZlt
7gZEkoGnkmcURusu6qfxb4dUcJuGyq+uhSavc4ETK3PoEeDhZBAOqwLH6KtaTnEJYLjHHLjx1tGb
klWPJjtzwJCGTRMJ9Sw5CsQDc1EQDB803ca37JhEZdtX8FV4JJYa6i18OddqS1VYY6f4sxGtY/rZ
R1R3lidVggaItpnaZe9IkJfJ75fxQg836QyDZZp77MIjIV5V1KjtfNYPj53CLCkkfQ1DB0InAwRO
OkQ1oUZRgLfpC/q80PS6RfsdhYa34piewjW21MYy3to2mDDE3Ea/gHseMQ0Ly0Vghh4vBqH1JLhJ
MSMFa7mCrUEpRYXwAKFPJTRqHcweCjt/NWyC0nW5ae3Rk8/Ndf7L3MrauryDwb9bnfSr605rhWEt
tdEae1mxxtAzHlmXv/ZOcHd7CjNc8YoQ/OiOIrCLP97we795icZXwqo/3tfB7a/GJiBaCRUJv0Y+
gov/t6yE4id1YecO+b03zXlT24QRTCSO22SnWt2s7Orx7V/14yA6NZAHVKhcKc/f8ybeKBJWec5j
Wu1DPq6h7xbOfiWzQTdhuEoIm0C4ERc/Syk+f93XsoiOT6zlP06Vd2HY5ALAzceoih4+OYQho7Na
O+Qnvi6TgiQ3KEE33ghsLczrPWBURpxAJjuCyzokzrzy/iKFyi1LcJO2QuGgFJ0PBPT6zemgnOg0
L4UBRlE3vU6hPWiKU8ltvKF2veRWcoTUJYCs6wPd0IX1XGT+Cq8UbsK4iq9Z3WW9IDCCvCFc3gmH
/jYMwQaxa5XMMXRoRb+aI2Q1XsGL1nZnmgt8rcRKvSQ/p2MWjm6n8lu9/iSwSsmuUYsttBE7+ci7
pFzR/zxmkbYMbatX1GC7HuaGMUxECHAVXIsNkiMiVTV4JTDLq0po5+OH1nbn+ONtMDac5TBTF/LZ
eePVyWnfgTLPKU25czsPKX4kTS5RMeSbKtYGbIoO2pm1z39WuhwsV8SNdE2Uuqp2lB0gqNMsCp+h
mKwvAEJt6XOc37oVQyOILZaksZRwgldroLxs6I4mW8V1FAwGxGmyIWfUwaQpttdpp1dTWc2Xi9gl
/gFhIzEbDXQ0772r13l0D1jy0yUq/fOiNREQZ0Qh9MXDBU3MrXmORkwJOIVfjDwZUS75mjtl0194
sRPmq1gtRjJIBAmXvFHyUsD+0ur8EyGg5Wtozm0m134m1Xx68wZ2xS/Qzstzuxu60oayztas374q
WvTgQZpNB1V0zI/cFM2ooOq0mlj/0KrdMF2KBjvyCrZPz1E8ol0aw9NKdq2tJankYeCX6Faxe3Qs
T6bsYwSU0tUoC6SJeOeyPW1/H9Bzy6X8uFltZYbMl2wK7hlWRfJY8XcsSX82P8D1VKDyF41YxOKu
cEIDKB6vYetYr5LxS93sE4CSujUEIuFRephL3JoGuSpBi6qvZvGklpmZVFTbizh4n/U49FRu6gKD
ilFumRcm8iiDcuxspybMOIcDrVbK3TjMBYx4tbE6DA3hdBYlBdIBxuY0b1s2Xp1IP6Z5LXL/H5lg
QzK4d3/OKDXZ8WZ4Zoe09+v8vd1tF9qqpOxXh0FGtkBrd9o0T7oCdybGdnZszwIe6ije6y2KWJLN
Tff/RaLZNSX+/ne9lTS5i5C+ONPa3dcjqlnVePVahh/k8t1tRWfMUwtt1mj/MKXqZzKsCw2NwMXc
hAZ/SQLs1sNT7Ofespfx79hs6mRWpE3zxGGCwQBfNFNSU/87u6+h44X95NZlUx1Pwg+aUoi7ZglU
VIeTqkwe/0MQVXybNzpXQLRkbHKMiTJvy2pt+6b2BtCjJCpCN2ta355ezofsLv+AHrBDz9WB8ICp
zEmM+K+wTz0heb2O0jZKuJlC79TAQ8xhKqzBjqVnzLkcghGBiL8xxA+vh9WgV7hcRj8iM2B43YXd
F1Cmb61o0xCYjSP0liVnTD1ZcjNXMJcWFZs2ZOpg9q9s4M8I2Fctaltr9scWGLpwnbW4KBJBYvrO
dF3A9cZdvsuaLbkX2J4E64ZBfkfPu5QUNvRhzkH2xy6sY3cvT+UMe6qY5R1Xg1SNFYpw9jnO0CBm
C7nZAjpFEypK2K4RjMgxnMiC2GR5He2YwlKP/JGu9iC4lBb9imQ9nDnjT7Kz2jFlAyMSHng5udYf
zQuELqpAiD00fzr9SHKKTpNKqzL0pKIu3yJdGswez0PfUnmkQBdDXEy6d4ygsQ109yEQ6sQcWrSU
iKaVhCkyOA/xKnhSqiLMA/Uiid/ieTNG5nmf7HXMEFsi6YqPwX5QiXLMSOYdlSet8J15MQK11ehE
dYV5mhY/+Jk+W9ZpndoqQcj2m3F30HZVCQXwawCU8urIJFEfAZTcumCfe67NHQZKv3M/y2H0eB5o
mE/yl9de6vP+wRvyJqLB11alWV6VOHJUbzSBRGZJ8KY2AMN5S3RBi/BTVzNjm0gY/ROa9R34C5Mr
I/qhujnPxv3jFy7JqHzRIfpKrcAkbvBXs9FB/3xVVRtOZJz4aZQsiUqZTFGx6aciPJctZgjbYkW1
Uk2taBFQici7waJn9wXFRCA+z8bvT8L+aVgvJO1FLjcMzM+EzahpZC/4XBGBsh5V+JFeZawcdZ17
/QBoFT0PPbALo0/Xb2QdoKtQDFBfV0X1KZwrkYKyq+xn+8k/2iYo2sCPxnnv+2JtAQ5jS651Ww+d
iKsWBZ3u6jNDD1IQ8SbGDIRKFM0W+c7lVkUubkocYoF3jX7+tXCAz6O8E1KneNO0UGiOK9BOo4dv
Kwtze8Hs2qbrME4vNTQoqNwajkN92NgH/tHuWqy8z3QXl0o2F3r218XEt5LT+ZB5/JB2H0VsPNwf
dYNAe7FoAZSmi3xXhDgBnBrobG//zqdpWvUqzim3hzNKPDVz7ie9IZHqnXd+hu6HLc03uLKq5Dj4
i1CwcpouTZbVpKjHd3GPCyXg4vtjktruJYXfozFEtTKo8uakEouAQ8m+BiU/savlDs6nAV0ysQzt
WfP7wPNlZYs0lZ0AUhT19igERhAoewkxPeEnzb6L8ll++kWP8FwdyS12hgpwgIBnvWb7IBX38Vx6
jmdxESkMrZOfCBHROJuN+FsGqLsYUZfsXEpO2juXg/zI4RQHHj3vu5c/4Y/kRgQfibmeP460WpdV
8RL8IrFp69GgtDOaXt1fgPrqbbgntYneSVbyqQHeDcYlaHU7aDGWnryNBA0F019HPkchL04tLaW5
veQLR+3qsU2CepoAjfcvLoUhGFSVwcbdkTyL6ck08s3w6fXTZ4fD2ehwQP8jiJAC3lCpS1Cp7LtF
KOIHyamBGov1XRyah/5Jczkfg+2hSPfysIk+tlvC1a/Iyc9QtxiDZHVIXP+oT9qYoWqHb/md9j3k
1RoVh0C+5ogh5DaYeNb9rLJRHBXQK3IElb7CciS3v9Tk++LhuFF6cR0C/Q3IhIZipjeHl1UW7BCl
8pv5tXnW3x1VqrhEJJdF41izBCwhMK/UHL8CI8QgIrTH316wwDO3KnccN9Yfx/JZBxKQY3M5+E2H
5oZrHfbgdh350975Jmiid5IbDj8/b43JgFpsDh3gX5bH3nNeDGQY4rNUofBl3aFwKKQ+4oWThRNl
3wKM7Bfq29BkilG+bVhuM3MQPnbG+sHTlX60TEhNZayUoHiD7OSR75G7ICPBKH84ceaxRIgbF8PJ
P7EQmswOYkIWwSk93HRkJkBOfFqmgWdOh8V22G7ZkMgY/CgCwp5wyqMeyiNngTI1P4ccodTcD1Tc
9Il8xpnq8JkNqJfVoBwJyxQA4/e5NbJNjaXzxUBOTFFEyTEn/35YiOhAS7LUTMQYIzw/poAcuCS4
ozJVqqXQXGnn7VuUMgu0JRhcGXUDgwXHn7cRivYZXylNGKPoF1hALdvS+GkGft0euzG0ucrEPO8O
J/UEVLpxlsaKQRDQT1STmM1Y89ZWca30eYyeIBHooCz7+i1EfjhpxeW6SXQ1TWun024DwfY1RpgX
SZdM0gLNsg8eUxv7gxC9pfAb4rc2KHFGmgoKYWHs9FjFeRW83U83Z32CeL+/2L52QIDtIU71Ddjp
4hI8myeILJkM3haRE4k0iqX7qCPW8N3OmfyZeti3FBGUap2s3uaEKTBJDfJWkb0mGQ5XYNSLAjyd
xNymkxD30F+KSpPCzK+tDrmJgUzG2fCqzU8XbLMLL5leEaXp4oXi3F6imC8mI2j8bYTYZuFHDf0C
9DPnGDkukLcYuFn5gULnAlx8D/pB8owBzVUADh2Rj8bCMYHI/th+22zewd5veWi7Alrvyw2KwanO
8AV8t1Buw4PgQRe0TolpNyM8AwN5V2PLsF4zyB0giFnXHv00u9GwEdpuRPWyBRQNqaH7Rv9YHZqJ
8afbrHVCErhQRtLzFOaxTwoIDqJsptpeQzQ6gRsKFoWCrUs3BsEvNYaCr1h8ML7dw99YgTjo7OO4
khmyatlDhQn1Lrw+MZLEB/2HFzbP5cr6UNOCiaRjU+VKEGEjvqu8ST6UysHbFTYOcXv66WBZPGNm
pOW8h3ojmNQSDJ5ama9cWCQZKuEjRLa3p8mxxmesuDvkqev+6+bogljk4QG7kFpB/77KmiVLOPiz
yc+1HZLymFwQaz1ddnmCnUX5WnrvSKLhWyCimmycXq2I2b3uUHHy9/ELnYm9bQmUrAdSkAaE2eLP
OMJgBemWV1I/fLBZTUG8arGG+T254tesXMv43G0Rf3vSNgpwzQBEpAxOLDCmmFtqh33ORoP9kpm4
T8rXYCtHc9tCM/4+Rmry1xMm4YXQSfyh2VyF2SENh4og85WVLhej+45fhgM5Ti/17y2cvWDutYwn
nC9Myb87Nu/y4rovBpFOgTKj0OLo/7oM6JOn4kI9sYq6Hez4csQOmNsEXvF9ojC34Q5Uy2rTs3lC
ahYuEdtprFCUFeDbC4B7vnyvgtYLwCREoFdJ8K9DBADxEJh3coumgdPW6tmsWTeNNcsi4PhXFgqv
kV/vPltViYpQB8/qlEH1J7Lj78EN9JpKxNP/jnpPN0GHpCeIdzkt/pDilRWWuSKqse3/BX/pr3rv
0MgWBYA9fTyC0VwD6mV8db3on6nBVeea3lNGoIUnAF6sN4ndvgwLhJnab3M1VgNg8/Lk7illA7K0
cGUYB1ZULRnqVrQKiTUBOhlmLtwPq6ZYO2E/QfeScQ1G0Qn2Jjk+z9LgSxxt8prYWNha8EOPiaDF
dMV9uqjUyhKGAaDTyssGH/Rc9/ouRVEabNKC0RPqVVeZzgTphGFVk0XNZyq1ckT4RcZiN/1sble3
RHxLIHIbnF3CDkGdmPgtel6oU6dEA40l832ENHFPM5Qgux4qY+8szVI4+7n+BUtxRPbKqigLh13Y
WBHgGUW9ylFRMuGUx2LvYkqxlA8MfAoUjUsRKFzbK/W2esgRLl5jDVkTb2Kg1TDTGO2wrtVrG5T8
ilfPZ0i+pIQV5YbqU7B0bw97TeShogEcghnhqhFIaZUvzBg8X90v7tOc6CW4ThhyacdVwAhGxM2S
2o708kxyGf8OIR+sIPkHgGoTO5ekYtKYjt28xDAcFcYQLquXmCOrX/soE0VnUZxr5Ze+3bgRXZrq
sUWNMIa9SAlnMgNw6dOtVHwvrkoNTUWMeGzCAjWGnzoBQ5YgxvjRSREX0zOajBothJ4aPwNvQ4f/
Y7RO1t/DziqJZrmby03t9wwGCMX64gJdV/hFrM7slT+RyOuodNyi5KWrBeNR4QBKFt8Aa/d7+z5e
Nho0dQjhSp7kP5DfgN4WuRWrELgVOfzgGTB2EZqfgdpVgddE1Z1nIpT/12MfSbI1mVp2FvQye+p6
ivON7hY0KoQD+YSQz1DiwmM7n1jzgaP5bwibyIkbI+xghpeLOotap+W9l+u9Ow+CVD0Tsw/HY1Hb
uO/vs4MM8QwAkz0awkxd1HhPz0cKQ4EkIDxYINUS/ALy3Z6pbW8kgX0lD5r2o/Grew1PnuT194Wl
O+SAuqX6bkuWoI1Y15jy/in0pfXnAe4mtCr/NKTOC4X597t/CIinmYpJQd2iMQs4/LqI4ddJV9zS
ujfXVymkNuCDX8got4rIIDSIUEsBqr6PNqq4jvyeNlVSIf8jCwuhfY9OyWckeRWzghsSSOcd9FBr
1tV1ryW65y+8LZPQ/K5MXbhPD8/xU6fk0/stNGud0+z5ufD8M6kd961xNeXOJcRZ4++Du3z7Ezwl
OZF5bmeJ8PVZ8puaRuJDucDsBLvvCYwfxBBM9O/sb0Pbjy9epPtNs859fWkirzfx5BE5bB6OP8oW
MJ+7zxZnaMvxb5sIuGocWqS77nCp1ZEhMv1pHXQz0RKAXSAPHKt/iwIOpikVUZiU+q+UQOOOQcpT
TZS/pGCSNgO1RoNYCNmc8yXN9MDqeAHUn6tF4vYqXDxZRGvgrZe7B/BetPy7KRTmpcJ7PDSrEJwa
/ZDab3vsju+ItyGm+aj88EbXLz4mJ90eXYW2i2SlJY3M8PC4cMcoSOFBIIR4oh4rdvI5nvnt0ksg
hNEtjpJytY+SV8MDL8Ibv2gPkPjJVm7F9dA1X3baDK7GiDU67kRUzL3PHxmkgY/zjx8jnSVHTkxr
eHEvwsyfRHkoET33SX3+1xxepWhseAkKIoRUNSXmZUemsHO0jcTsDTCzSgabIlnXaCNxYJn+qAXp
yH7M5SSFgeHH/AXU1WOHUNJnkGOFJwzjJddRoUfd+gI4I+7H8h9vdCcVviCok+7RcatVvaWvchbT
zqAvHJViGEZuIGdd/Qkp8YRJ/RMxrd7i3P/7eTwF3iHHq5mFUBgdkxwliS94Q8Fvu5jRwYKcb2Mr
fL55kD805DWtWbw3TuXqq4kdVGOfPZiJp4nPoX4P7ol+7TNDPUvLlX21g7MROmpXWU61AtR7v3Zz
f7EGVsG3yUbwh67MntRlFf/Vsz73/md0yt1r2HxlL4hhHXabqTA0v4rKnFnQQLcKZsP2dImYGY7/
Bg5RnS7c59t1c+vHq+N5Fvl19h8Na+aup8oTmRdPkJh1ZNoDYVOrzDhBasbcWLLvkROKJYkDPdrN
H9ZfAJHAPaYoNJxdvU+zv2MVzzMwAYWTL6K71ghBebok0/g53H7+GWYeNNciSr0BTRt97zI6HyMm
mgbrdOmEJFvBoLOLTiCMEuW016iS0uUVnezWUzizRnycoy+uhP0eYpWVIR1RgO5tKD3J/1d3KGLn
TpW6r4MbW3URS2YI/my8S32XhKzD3RNuO2byD0Vj32Dul2SmlJJsKZNA9nt+WfZrX5Xw+vfL9jXx
349mj9zeOAGzw1LCGnOrX8Dptt1LQHNC5SQsauWKcoOh6k0yHl4uFM71Ev5a1No12ZTXEFtaw1/r
nCNuCHvP2+AmBadr79oA602GTHWwq+v5ClZmB43MaNxRF65HlQVnPTnaLK/5kD+CsFkSLeOMEqVh
IfetnXD+2NXIGyP9+CSA4mkm4oe+0fxmjzKcnY6ww8QtZeLaOuXQ+RyWewjcfw5jYyw7pevMrYIo
YlmrrrjydTwj25O3Lt/h+7AEuxheB5MrY92Sd6Wu27vOBwhpqQUpUVuPJFYyStmNdOsQgVu8L8Xp
drb67ZD5k0395xfzDfiqusKKpwqTpMXNDP2Mf8RuR2PhwzXZqUPu7bSljS+SqFIpoOaCYttrqIKN
8+aQSzb9mLVN4LfzCb2SekZiKlbl7vOtH6ZiTwyxMh6NYi7A3i9PAztQFnNUf92cbw0Wo0tNufrq
gyTMuuxVEY+9HfCGF4isHuB+u93EdKG87VIb98y8IvK9txJCZmGNC7H11zuUqMRHeY+owHQ5h7Qu
OCtbF06VwuAodM1G/JIv4AYiRJ9Pf1mz0ySPlMacmc1tlFXX1+a7YW4YlJSu3KMC9odHva6sFbnB
gBj72SkKZQhjRzkZEatHIE/PfokMjfmCG4wPkpW4JAnOa5QZYAIMYTrMW/ddUM1lK6sQpc5/8FxI
uxKeJclu/EtWUCbrS5Qgds28hy9dpQJkRh5xAWB/UrqHTM9WhVe3dzdeJypQaHW7povXj265G3bB
jw8g3/G/g5XU2yo5+5duRY6MzcAoiFD5hFsDRZJOJHwt3Df3/1UtQ8yKOtpmpDepj/m92H8IJzDW
cahPpyTAPgRkKcmUrwldrma701uhNkQnbwsZCDVIrYg/cRXWwPBgSpUFio+6skJ9j6y0q5bJaFyp
EuyK5eJvS1CdW8ihmzP7wlhI9c3Usk7jKFUi0CoCoSW+St4Ox7o5kB+FqwN9uqXEF2DlON0JYXcm
dM1poFOCcboGuvVKxfcu+rFIP5Jkr+sB2y6kdlEPZ6zXHzkU/IKiKieOH4/K4/UM4oZ0nar/XTj/
Vw3Gfwtf7AYnnDTB5QrkMf3lGqUxbn1uV1OEZ7/+EqdJoWg00IO0fOkMRaQFQ/31Nhe9iQM+9c8U
Eaw6P6wIYA446EkcBbfFKsaIltiBmCaB//Wd3MbBdeQNbeMiF8Ehh10WLkG/gzOI4Fi6sfjgwHlJ
Hp8OCFkxpWMQ29SPbxp4K/3qdb8k4ArcfyCYAlO61RiDocFwGM8MD1aS2MpvIEwI+EjAgDEOXk3U
CLMrr3bU2KY4n6dgcnFuCI3aouW1ykc8w+Y4H0J89h9sWBLe8lHCl/Z1ZEZUPRn63vx6WGTE4AiE
wyFXXc4bCOifQZHEChYxhC+NyIwrPTAPThswiAYtAhD1pxO/ca7Yv5RSM8k712ybaYX7w0n0bsRi
i6eGrlvRAUAtWtwXCxFBlkYBhnVC3DijlhIr90zwXMWS4s3LjdcmYBa0IrKtXd9dp165Vd2hCaC2
sYeC8FvIzfjkdFxyZJdb5zTOo3l6BC8iulmdhz38leADbmUQqc/d+vzuFW8UN6CUwa8LzZsl0DU5
XDvPXIdwqnBsKeQxZSFjMyVpjc2+VPIP2bzhzA5zIWJNgCSOkx8ggjM53jTIeGYh+FmG/ZJfgBxY
QMK6Q2MrryG3wG5acjS4iE60QcfGD3U4WCH8YoIE8zU+3qka3PwNK2yaxENraPrIXHGszat7u0NG
69OTieNkWH1NajTPAZygsEhbGaGbMckFbeB6yq8FW1rRIH0zYRwlTBbIyk92LZ+0s9Vn6LFenEy8
R8/XD9Y8P8FlvVr5NW4JgEIqBlJA/fO8CyjjQv8+UmeKeAxq7utL+Npu7ReBEh8dKsjTD5a8Q2QK
wyGq6aX8O2fIQjf4g/tSsIIJgroDPxjy9LSBCR9jGUf8DtKDArJE2ZMTkIEGOUY8iNTbumj+1Y0S
S9oCUDbZeH3Ns0VV7YxCz8chLU1VauJvXDF7eRddwNY5nWWG+3Ag0Y0vkyBsSAkEr4JopaM1vuC3
GEtudRRBOVor6Cablsj2NoVHcvKcuaukUVD82ZC4IyoIfDlmmvFEDmdw2QF97Bkf8xDJcyNIeu10
EgjoGziMbrr17se3PNHFxefq/Zb/41EqqAivRbBVjcM1uKnxhf1fpJzUUIzhW5r5wP5SpdTwbwSu
S6zsq2dP6G2qIkuD49Qk2WWxDawM8tAYHiQnGU1UmGNRURFu5bHx736gOteITcOPNEE5tThWPhiB
dqzjZ4/IS/AcX+T+Z7gIshOoxSjE24Rs2zedDYnwGweZSatByG73p8JtkWmcpgwd5zxn5ZUa475w
3bCRvok1lD1ImYBqOi94WjYUrd2q9oCUeBXOdC9voah7YlTAPVi6KQ5j/J+3lpEFpoffRq2b1T/S
l6X+sVwgNiViw+vQE7BaTof9/jatyXCVzXCmyaOIGajPUShkAWFkIqumwMFpvAYl7hcXfeJ6MOLg
gNGTRLOF0ZsjAhAxA8dRruCfv7Gy64OoUzknBBeCbSox9v6xEdyN3I+VkGrTb+qErLEBhY0h0cvg
d6Z4Aid3/O2nCuUQEv5gBEdch5Ce4c0L9ODWG6cZKpqG+J4BvJTiweSEp3HSI4TkmpQppEfFMyIe
T0pjT7BtLbTrSOvX0E9TBVMyH3m87e9BGqdXCnNeqg0AfCsvuLohPy4d//8dUeqx6fYfiHj76qhg
Z3I76/j+bq2DIV+Q1E9WtDx0SIDVeGPYTCdsQuNfzwJpjymgIK4WcRD5vZLZUiVsRTjlumSVBOQU
HKG9KYRa6xZ5k2vLEq8/iWQHsTVzGQFY4tOwwx2GopOCld0ImkFm9it7V0dGPWxo03Zr0xz0XVBJ
IXn1Blr9EsCB4IA/FyVXVk0JqWCkbM4dKLshSLmUX3DS3tTe9n69HqcTBZcHopon20PbELhTZSoz
xNpk5aEXnIgh6UNBBJo23kj1ZHqdt2Z6QjkmwLvzH62v/Pf6GvctZgK/EI2xPS/3MJaVCJITg75r
A5R85gpiNuF0MtcFaTFZSPQh2h+82U9Zq5zW9lJdXStqZyClp/+t88+dEDBvQsseeBTPZPV5Pkpd
M0T4fJrmGVvogKmZtBe6uFlJtK3VxSmemdCcchhH6U3kLe2ZXUtpLittr4XBvzp8Fq91Y7PeI/4c
B6Y7Xjmx9cVGpPMBJ7vdV2L3S8cOqx47asvQQ3LpNdtu4NrBXmSJWZ6+dSaCtbIj2qmofpArPJ6H
oB8R2PWDQGn63OAIhpMUz67fMFzbvcC6IOuY+vAwCMZfmIq0MMs1AXZNNXMkxKalHuNf86cK3E7B
8UkxxLImUioU6t0UchzhXh3i4RQcSV6k7D77T26kLcUxCz4Yr/D7PHjQoADmWk/dlEc1x3NOIDen
qbLloZI+2T9hJ/F8xxymzZExpQBtS706L0QxplNYkra3GF28913qQCRXTYaVmnyrZTyePqQ19uc7
w9M4cGp5DfOFL2XXodOb7VbIwnZHCWrtwsQRwW3jQhq00/PNDMrsJ/5MW6i78yic35RzDuL8CAT5
ftIt46TVLvg4eZKJnZtPDqVtRgXOJd80v/SHv7//pT6bRw+kZuH/86SkT5E1C9NJK0VGbPP5lklh
WUYT3w1ej7JtWryxERxSLP0zkK6oqUahOQAiL1PbUUXRioZTRSNxi1WkCRJWMplnKHSOvUqOcoYw
vuSvZpHWyl9C6lEgPOeFXuBZgPDeVAWmNfnV3rZ0e49Dp2pCMGSPbhCSLV7QxzX/AYYoedhWCYeF
KINX4Jt2s53qSocnZm/bOnbT28P3prmnDPO+PfXNsDXOrZ6eWx9b/9CIRCr45desXp/L5n+OvKAm
vvc99cyVHIBtoZe6TBimvYcag/dOcRY2j/EeOLqkXrAdM+vVuPMlluw3C6zHQcslB3wRIg7QWZee
+AWn+El7snzln1v0jJ2cuV9iFw1YODeOmYUU+n/sYU/Qh68WnX75geZsGqFOtSP5TCJaim/HzCV8
S/4r6g5fhJAZWJgytdV7bNgbH3p/EAhxQmtyZ/YIxNixTClTqwwtHBj0tp3MoUL5RKEtEkuHX0iR
uni8wtQb2IqfoVa3HLRrU4Q6b6jr2F66ezre1pJEczkwmMIaCLfD1ujGdmikqUIlK4UNIgJ2OUgi
3NgUv3icDFE/ANh5VKFsIGJMNZMoXH2Q7ldmcSeUJsve+C9cvpqZnlHwSV14fJ/yP63We3xeoJWR
tZwhQjmR4WrbMg2G4PzEJVK6YQsTZdpccffN5sAKzZL8qv9B16bPd/8iTRbit6oYOECMsFcKMCL6
M1e0iGt4+nYrJSv6wXf81d21w6ih2qW5z5DTenPoglBzcUD1VC9QzEhjDhHQN1D2r9XdZwcrwauU
hzZuif0NPxdVC+9Gr43q2yIt0/TEVgIoJvVHhvLRDhMF4XnKdPUTZmd6cudwUr1k/YAWFyGRCWqz
CHPcocCY26wGZYrsVtbDbxxvSwyJ2UPTb6qce3z+N+z2LlEqL8IYR1Vyy5z1dEWg0HeiBr330wgJ
pX1/kJi3cKstB1oUXdYCDlrU3xft1buQBHVoTeqwLa+B19Qc6z9BP/TV69thY12GbMc5/P25xXcc
7TikkrQm4SiprS/9WLz0HScNB0UAS1Gbf8nKyiZVYOainqaCktKLrHAjaNXKeIJybDnlu1ndXws2
ZznqtEXnXCqe59wERZkgdCMYJ332gDqvEMtTrGPKH6p3G6L7TqrezKrJqGOt3EH7rd5k5dpavxWB
WPpPLTfuYFsY2mBv5np1SN5y4blK+YiP6MKTVh8Pu8fIbH+EBRph9nJmsSb/KzJZN/3JoHtuKCFW
8Y8jglddXGBZ/pAhlZYBmh4Q6USDB3SQ8e0okSu+vxqEwW0XrhIbPPE3/wxo9W3BwQG3TSJwBgW/
mr625nw1baUbH0GhmhqCKP90qu5kPIYlz4by2CAv5M+cQdIQqVsxWXC3vguxdW4G3HCjGDOBsppd
xPfxpw6ijkXQC1+PR8w5DrC6F3vI1k2Z0BzhdYqi1KQxsN86taXHzoqRbWVjtO/XFP8UTZ91s8hg
W7LqHq4mlG4jEpzeFeBHN4mmBlgz+VmOCQbH8VA6aOg5xYgOLfMQ+fKM7ZG0dj528ZubRoyYohYu
19D6QdNkzvwjGKKPX09ML3ScJ2ew7Wzmb5Ms6Cm2kfGwBEMp2MbVg46yuhp6vESyfpmimuhui0nE
EvqYQzb+W6Wgti4JH1CnS4p683G+DvZWEWT1vB4rn8Wi/zvFf1QACmD5Yew0SDw9G3h9wLGNs7WG
sITNaJdWKuf2fh+TLCH1h9vD6YaCYrVl5CotSpJx3gvSC/ybkbtQ3WSS3guwu7IjNhwNO3Nx3O0o
wWe1o8s4fisEJwGj741vjAWstQx8p4F1NQcRPxFLaaaDSu+copLo/2sY/95C/pTFeEoEQTz5wDaW
OkJ1RtJuSyguzVzdbNtvn1RN0jhgelCjqYML3I7cgks1SNW0Hdc4xZPz/ulAlO2G/hvR7NVmDAoF
HpN0f3sFLnUN5TW1YLrc7k0nEs1hDr2lCnqKifvpn9+5z+z8c5D6bBhE/kcI1KwPKXjJsF46AnSn
KjoA4ycnyfx/IZSqZzkBO+iotYTYir3ehDD0NXxGugBNOSev/TZKdd6VxSesEUYwAl4BKK1LS3hA
PTVPR6SJVvxvFKvCHgDMwYzrXKlGkyltSJPvu7oQOpvQL7sbNK4LB9TdVc+0AHSlCPlKcJmGie78
0e8G2IhDZZDUKmUSictYirO0GpWHo3rFA1uL3tIg42zzowTCqKl6rb7u3AbcI5tTNZgpAr+T3jU+
9kXE736PmAyqtQyd9Dk3I7f+/T6WJ3gNCUqFIs91P10JlcmM6SKV6E4R96g9AD9RDxamf39RUzwY
HoCQPSCQ6l8422+TrdqZiTTXbvDvC8spSo/6WoYFJQ80I+7ps2Z6AWQ+tCdanhUbQmEaPsANVnuX
wclYhZNpvPI388IXwleFtmWq/geIqYnqgcv8WfuH9PEXA4dOWzZotmDCs0PqmTvYhliA/mjCT9rg
vALWuelkHM3CbTrWlotgm8jrzuirZAQCK/stsiY8lUZY5N7j/8Tfzqy85BUzxnFKleoMJCKu4bqg
EyKj1Xz0xc4Kiu2shUQrQiTvtcHw+tU2uiSL6ZwInVGUmoavD1C6Flel9+MNz9QOSEF62qS8sqv+
gVMlPnkSsfGcKVqhKRcEpoOelaDeGiNVWwOYi3AtgMipHniZ6JqO2UAhgTrgPLro69U4WkBMi8ts
RXaeq7s+6zjGaeItNqkv1IJtENX5iNclgOXpkXYmgHqlGLn/7LA5iqjDgDfKQ/FczQ8VZVyJbHjG
sIz8whMJ9CIHZOFxkXBd4nz3KcSphZ34F7apRiVGn8nzJQuTREWZOkm6U4wiwAns8qkR8jPzTca9
zilzpN/gEosS85raq1onAt1BleT1eaRtxNS08rkSvtnjWaMJWV1k3oJNqeAqwd34HIfaimvO8UhR
hE3okyW7Nth+wsyFysid2qyk7P6nWWGkQJ14gRphXYpc7rjULlQJvmzzv2ohE3ZDT0vxW5p6B4G/
baTD7Uydv2327Ck5bnUNC8EZiPUPkuw8ZtbUTJODRpm88f8VHOxnVM8V/2F0+7ZKhEWtyPlchyRN
WUTwBAwVzcBnX1bFh/jvDvnc0Q74s58Gt4JPlRgtQwRoKUaF5M+woczfEuu/Oe9p47OqpXBH/Q51
XvdmDYUeoRuacR6JQblDDlRSK1LqirpOWI+ozjuX8mvzKRCCVZAJ3lZmLawWNpKrYF5Ctvma33Mz
B1IxE+KRMcrEIN6C1kxGAdEJQk7XqWO2MH1Z6XbwBMwKOEvpt4I3YvFSHNvw8VGCvAdwCpbZjySo
D9Z+8QEBMbE858GJ5uEAhhr2MN2NPuhnEZgwij/LGL+Y0creFWSI8ImjN/3O1Fp1+fusij51EWYe
oqV8F2XS4bhwe5dfQ227NWke95HIqfhzv1HNz6pH/oTp1SmRzdv2z8+Q16dEPrV/uWnqUCx6cCK9
bxR+1Zi+bKee0hqjnON0GHHmQTByH5cYr+2ANBI7zZzzC0zKqOlvuJ9BNFOe5Nl0WmB1iiRpoZGw
GA6IbibjmNBO4sLta/vw7VZQ7VjwwOf0noQ5/NQmFh26T0g/ppk0rig/ju547Jhg4bLRCWtDy/or
qdqHUiOyZyC+qG1zW9qY8N3DHp/J9+BdnSg3SMuT9hXtH7AViLAEJ9RvxpXZ4ctnQqf5oF2eczaw
PXUrJxIi6JkR7UgFMCGeJiQDdNaIlMDJ9cGl8d/YQtkUYBn3qo9q7RDlUs9O3FlM6/cYFBAyvg1X
h3c4jBTOIqid2Gz1gtPvZItiaGKsbZD4wtXs+6iMM5swtWyLC72zf+Rpv+bw8Hi5AK3BzqhCIOuV
9A6oWu3KUkAT8Z8+Xyc4FIleaxMkssz2Y3p5dPYOxipm/Mp2SEwXq6RhIaZ/9yoAwiCX/waHT7G1
u6Z0+gI+DkoWAGOaIowhBDjqm9xw3Yg3A0JpX/PtEDZw0vlOya5IZ2RSc0ZMG5atCFThNzgHMtbB
LOk5Jh1PQLBZ9fal+/GaH3P18UONRJP6VQOnMbzsGUglSGU7LBoBXovAozYqQiCOTyvg1cJhlbRJ
GZhcZEpuc0G9Buh7aE3Qz6Ejt2Vvs2C1rih/v8xGHRC+Wu734iMlAvAdaXdgU3uWR+ght50//dcX
OHhuMTHeszFYn0KbXpgz+rrKk9YwiLclh2Lhqm4BUlznFTbidpHss/ALRPFz4c13NV4aejvwgsRm
DBsw02bXnDVVvcP7zau03q1n2yY7nw+4zwo8MK6Cr4pem3a0f3GtwOlKzReI3+f+956TlIbUBSa9
OH5DXj9eR+hQItD7GRB4HzLv8/QnYUsgPw7C99ajx+HQRO1vE+q9MJ0d1kXjVK7AcSTRQZE/d7nj
kWO2BsvjVTQOq5VjPaCGowKt7gn/ZJ7+eunuRd7Ezqpk+SaCduOVkbIe+hTwL7ltsv9oDw1MlIrI
C8RnnjGTBoVXT6sNlMxUoaILLxMCa7oKkHoCV7WT3FBq1SoRz/tbf/wsNhmtCvxoQul020CTPCVJ
2l2VcYWIrteK778atKSa0vQ7hQn1Tu/hcu3R5pgOpN5yHkzx2CdA7EzipjQDAmdnH8mtltbz8Wn5
1BHC7HUfi1KKMrDxz48V663tXgwRt8KROmiMm8A8znvQwE/FDvAduCQAUfGry74ZiX6866USX2bY
LQru/Eh4FOkgobrsyaaGobyGikmupHanAq1wcqEBJWeL7npm2DQkF9vu329BoAQxnU3kzgti9iuY
0cT5pZhCPbr3SKkBKNSNjVllx8aYYy8a2923mmS8IiIbclm9KX9Jm8i/YQP/JqRDfoAMUfYOia60
Q6OXWvlgfS6s5ELjHyEnx4GXIqpBV1u5Eq/92e7rH92IrAmn7D+I56vCLw5+1sbT4DYY+CMIGwpD
mfNoJnICRvnAHn94LBYKklg2lmdsOEWA4tyqUscJHrw015Lfhx/6KNFm7Q0gzKmQx2v3ORZfsNq6
Ka2IDU4aC5LejBiLPHs6Kl3IJLdQjyPS1gG233IJ9ZOQ72qN/GKRUi6DtWjHdaSt0zCkzz+MODtC
AEwot0dIfylBzRVopvdfEL95RFi54pYiSRJGFe9TvPYBBdImBhoTx+CxsL7dLGVFx6GQy3Ra+Fhr
WTDZMuY3269C93AFVXcYkVP/UscsV6mYAffMPLDIX/fvhC7ii0c2pN3RiMxr0fVLN5+cTDQnrbIE
dZnPFA8B9GfNl1NBEnM1CI0n0nhVehGbL5k/AxkNn2chw029sG6iMMnmUhN9mXpwDkAqImVC1Ege
4Vanzt6eHKGzRTxAX9efuqV50vaa/sXcH1nuZOjejl+Ee9KbDohaU/r4IcYTzUX1cHXZWHLhuUJ/
Opz+bfomEtO+94t2EaVPrO13wsthIiRmV3yMeSN9Nj1U1grM3ZKt1xh9oNIVNMYg+G204g0hdn2s
o1FYvPQKu0D6wTVCTCJF2zkXG2qsp5kHAkxR0PpJOxovD3uCgWHILZSB94AKK+udGMuw7sUXwCKK
bINP3ipWsq6KApmOQnN6wTy48TJeapDrmZqBmVd7t6jvMnywCoBNfNuUw8eUzCE+63+DNRPEBchF
NsKIWRg0vV1gO/5QaBwP+hsrLyo3YS7bOZULgrOxzS+CwiuOBZLbFk2UXtsWJN2Puql2y8+yEfH/
7pJtUr/VYM2B1xbnBInOSDslZFIl07h/ZpTMbz3YFpMYJYxsayqqmO0jBfzEJFbb+/XmYRPCZYNy
xd/Rwo0voBTwaNYJWW8w6UrOW4lbdxbLKyGIEkgFMH+rfvZh/CzOUwXxKYZCEsoWTcUMalNf7kOD
k8x1vGDzbraDw20gLvk7j6vT2nhjRiszPkdCZjJy9b4mLyVgMp3uek0kCdPyb95I16R3Y3DfoN5B
y9fZzV6do+Wz//MM2Pizysj9xxSiyTE/3OyLa2a7O2fVxVD1FJu7Uf9G1P6nHqx3dllap5Cm2MWv
AFNu7yKsokNwWHrjCkBDYYOgbM5CzXUODVxIHlzJeTSOpa3dgqMRtJLBZuF3ocOkFl3sNBAcaW7r
4dxOMdErdRvvg66eT8cM7xGzateVXH8Mjbe84Jy6sWgVUg9jpE40op+XwFKXyOPW7qU14PNz4b86
STOuEKvwN9q27jth8rmR+Q2pfkEEsC5LZrQmasRGfB+cUf1yGAquVx1LQLQFlr8uk2nGApKeRr0T
cn+HoX4WDK0ZvzkJ4p68T6yWsDLdwkoVAgRryv6j5SpSwYB5LBciUK4WsFa1dKDeRajiiIjz3Ypw
N/vy1/TQL2nSx0iK5htdbECDAZo/sETuNY7E9dMPaqhpEQzmmnlrxpZYNkfT+U08JQXyym3E5Z3K
O8vbwCs3f2+SvgIUcWoyWMsu7PmdmFEtTF7ZTsNozxoKvy/D9z842aL1NioUmN+/uTxeQI/Bkqa/
oPO9PYb8o1HGt3pEQRYegGDKYFOgRLadncZvCp3VJQCYHLwadFzUvnADKv0OCACn5no5/zJLb1qM
JmLKQ94AfA==
`protect end_protected
| gpl-3.0 | 3d2c8d193d41ab8d6972baa7d360093d | 0.951454 | 1.830446 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug039/repro.vhdl | 2 | 640 | entity repro is
end repro;
architecture behav of repro is
constant c1 : character := character'value("ack");
constant c2 : character := character'value("'Z'");
constant c3 : character := character'value("'a'");
constant c4 : boolean := boolean'value("TruE");
constant c5 : boolean := boolean'value("TruE ");
constant c6 : boolean := boolean'value(" TruE ");
begin
assert c1 = ack report "value incorrect for ack" severity failure;
assert c2 = 'Z' report "value incorrect for 'Z'" severity failure;
assert c3 = 'a' report "value incorrect for 'a'" severity failure;
assert c4 and c5 and c6 severity failure;
end behav;
| gpl-2.0 | bcecb9605b27c7e0316fa92452a7f8fc | 0.69375 | 3.72093 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket89/project/src93/methods_pkg.vhd | 3 | 164,815 | --========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : methods_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
--use work.protected_types_pkg.all;
use work.vhdl_version_layer_pkg.all;
use work.license_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
package methods_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_DEFAULT_MSG_ID_PANEL;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Enable and Disable do not have a Scope parameter as they are only allowed from main test sequencer
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string := ""
) ;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string := "";
quietness : t_quietness := NON_QUIET
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean;
function matching_widths(
value1: signed;
value2: signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean ;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) return boolean ;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean ;
-- procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
);
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "integer"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time
);
-- Overloaded version with additional arguments
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_bitvis_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_bitvis_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME, ID_NEVER);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME, ID_NEVER);
end if;
--show_license(VOID);
-- if C_SHOW_BITVIS_UTILITY_LIBRARY_INFO then
-- show_bitvis_utility_library_info(VOID);
-- end if;
-- if C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO then
-- show_bitvis_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= NULL then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", "SCOPE_TBD");
when name_error =>
alert(tb_error, "Cannot create file: " & file_name, "SCOPE TBD");
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", "SCOPE TBD");
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
) is
variable v_file_open_status: file_open_status;
begin
if not shared_alert_file_name_is_set then
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
else
warning("alert file name already set - or set too late");
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id := ID_UTIL_SETUP
) is
variable v_file_open_status: file_open_status;
begin
if not shared_log_file_name_is_set then
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
else
warning("log file name already set - or set too late");
end if;
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) THEN
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all & lf);
writeline(file_handle, v_line);
end procedure tee;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel -- compatible with old code
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), C_LOG_MSG_ID_WIDTH, LEFT, TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", C_LOG_SCOPE_WIDTH, LEFT, TRUNCATE);
else
v_log_scope := justify(scope, C_LOG_SCOPE_WIDTH, LEFT, TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, global_show_log_id) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, global_show_log_scope) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if (msg(1 to 2) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
write(v_msg, remove_initial_chars(msg, 2));
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, replace_backslash_n_with_lf(v_msg.all));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, LEFT, TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_info_final);
end if;
end;
-- Logging for multi line text
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = NULL);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
tee(OUTPUT, text_block); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, text_block);
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
tee(OUTPUT, v_header_line); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_header_line);
-- Print header using log function
log(msg_id, msg_header, scope, msg_id_panel);
-- Print header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
tee(OUTPUT, v_log_body); -- write to transcript, while keeping the line contents
writeline(LOG_FILE, v_log_body);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
log(ID_LOG_MSG_CTRL, "enable_log_msg() ignored for " & to_string(msg_id) & ". (Not allowed)" & msg, scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
when others =>
msg_id_panel(msg_id) := ENABLED;
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string := ""
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_string(msg_id) & "). " & msg, scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string := "";
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_msg, replace_backslash_n_with_lf(msg));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify( to_string(now, C_LOG_TIME_BASE), C_LOG_TIME_WIDTH, RIGHT) & " " & scope & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify( to_string(now, C_LOG_TIME_BASE), C_LOG_TIME_WIDTH, RIGHT) & " " & scope &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_string(alert_level) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
assert false
report "This single Failure line has been provoked to stop the simulation. See alert-message above"
severity failure;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_string(alert_level) & "s by " & to_string(number) & ". " & msg, scope);
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
work.vhdl_version_layer_pkg.report_alert_counters(order);
pot_initialise_util(VOID); -- Only executed the first time called
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
work.vhdl_version_layer_pkg.report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
pot_initialise_util(VOID); -- Only executed the first time called
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT " & LF);
for i in t_alert_level'left to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, RIGHT) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, RIGHT) & " " & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", C_LOG_MSG_ID_WIDTH, LEFT) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if (i /= ID_NEVER) then -- report all but ID_NEVER
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, LEFT)) & ": "); -- MSG_ID
write(v_line,to_string(shared_msg_id_panel(i)) & " " & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
check_value(attention = IGNORE or attention = REGARD, TB_WARNING,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_string(alert_level) & ", " & to_string(attention) & "). " & msg);
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
return shared_alert_attention(alert_level);
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_string(alert_level) & " set to " & to_string(value) &
", which is lower than the current " & to_string(alert_level) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
return shared_stop_limit(alert_level);
end;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_SEQUENCER, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", 100) then
deprecated_subprogram_list(i) := justify(caller_name, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_SEQUENCER, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, ERROR, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1: std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2: std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum( idx_leftmost_p1_in_p2('1', a_value2), 0)) and
(a_value2'left >= maximum( idx_leftmost_p1_in_p2('1', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1: signed;
value2: signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
if not std_match( a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0) ) then
v_match := false;
end if;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
function matching_values(
value1: signed;
value2: signed
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
begin
if value then
log(msg_id, name & " => OK, for boolean true. " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Boolean was false. " & msg, scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for boolean " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if std_match(value, exp) then
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " '" & v_value_str & "'. " & msg, scope, msg_id_panel);
else
log(msg_id, name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & msg, scope, msg_id_panel);
end if;
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := matching_values(a_value, a_exp);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, name & " => OK, for " & value_type & " x'" & v_value_str & "'. " & msg, scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
log(msg_id, name & " => OK, for " & value_type & " x'" & v_value_str & "' (exp: x'" & v_exp_str & "'). " & msg,
scope, msg_id_panel);
end if;
else
alert(alert_level, name & " => Failed. " & value_type & " Was x'" & v_value_str & "'. Expected x'" & v_exp_str & "'" & LF & msg, scope);
end if;
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
if value = exp then
log(msg_id, name & " => OK, for " & value_type & " '" & value & "'. " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
----------------------------------------------------------------------
-- Overloads for check_value functions,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
begin
return check_value_in_range(to_integer(value), to_integer(min_value), to_integer(max_value), alert_level, msg, scope, msg_id, msg_id_panel, name, value_type);
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
begin
return check_value_in_range(to_integer(value), to_integer(min_value), to_integer(max_value), alert_level, msg, scope, msg_id, msg_id_panel, name, value_type);
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, name);
if (value >= min_value and value <= max_value) then
log(msg_id, name & " => OK, for " & value_type & " " & v_value_str & ". " & msg, scope, msg_id_panel);
return true;
else
alert(alert_level, name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK. Stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, name & " => OK." & value_string & " stable at " & value_string & ". " & msg, scope, msg_id_panel);
else
alert(alert_level, name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope);
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & msg, scope);
end if;
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0,1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time, using overload for the integer version of random()
impure function random (
constant min_value : time;
constant max_value : time
) return time is
begin
return random(min_value/1 ns, max_value/1 ns) * 1 ns;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
v_target(i downto i) := std_logic_vector(to_unsigned(random(0,1),1));
end loop;
end;
-- Set target to a random SL, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
v_random_slv := std_logic_vector(to_unsigned(random(0,1),1));
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + integer(trunc(v_rand*real(1+max_value-min_value)));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := min_value/1 ns + integer(trunc(v_rand*real(1 + max_value/1 ns - min_value / 1 ns)));
v_target := v_rand_int * 1 ns;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & msg, scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
begin
stable_req_met := false;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, name & " => Unknown stable_req_from." & msg, scope);
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, name & " => Unknown timeout_from." & msg, scope);
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, name & " => OK. Condition occurred immediately." & msg, scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & msg, scope);
stable_req_met := true;
end if;
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & msg, scope, msg_id_panel);
stable_req_met := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & msg, scope);
stable_req_met := true;
end if;
end if;
end;
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse " &
" for " & to_string(pulse_duration) & ". " & msg, scope);
target <= '1'; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= '0';
else
target <= transport '0' after pulse_duration;
end if;
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse " &
" for " & to_string(num_periods) & " clk cycles. " & msg, scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
target <= '1';
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
target <= '1';
wait for 0 ns;
end if;
target <= '0';
end;
-- gen_pulse(slv)
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(num_periods) & " clk cycles. " & msg, scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
target <= pulse_value;
wait for 0 ns;
end if;
target(target'range) <= (others => '0');
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period / 2;
begin
loop
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period / 2;
begin
loop
if not clock_ena then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end;
end package body methods_pkg;
| gpl-2.0 | 38ddd012b9bcbc7550c3133ec81dcf5a | 0.543227 | 3.878821 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/tb_dff14.vhdl | 1 | 722 | entity tb_dff14 is
end tb_dff14;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff14 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff14
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 8af7c323437f13a6d8badc70f5fc6aa9 | 0.567867 | 3.389671 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_13.vhd | 4 | 2,995 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture detailed_timing of counter is
signal reset_ipd, -- data input port delayed
clk_ipd : bit; -- clock input port delayed
signal q_zd : bit_vector(q'range); -- q output with zero delay
begin
input_port_delay : block is
begin
reset_ipd <= reset after tipd_reset;
clk_ipd <= clk after tipd_clk;
end block input_port_delay;
functionality : block is
function increment ( bv : bit_vector ) return bit_vector is
variable result : bit_vector(bv'range) := bv;
variable carry : bit := '1';
begin
for index in result'reverse_range loop
result(index) := bv(index) xor carry;
carry := bv(index) and carry;
exit when carry = '0';
end loop;
return result;
end function increment;
signal next_count : bit_vector(q'range);
begin
next_count <= increment(q_zd) when reset_ipd = '0' else
(others => '0');
q_zd <= next_count when clk_ipd = '1' and clk_ipd'event;
end block functionality;
output_port_delay : block is
begin
q <= q_zd after topd_q;
end block output_port_delay;
timing_checks : block is
begin
-- check setup time: reset before clk
-- . . .
-- check hold time: reset after clk
-- . . .
end block timing_checks;
end architecture detailed_timing;
-- not in book
entity fg_16_13 is
end entity fg_16_13;
architecture test of fg_16_13 is
signal reset, clk : bit := '0';
signal q : bit_vector(3 downto 0);
begin
dut : entity work.counter(detailed_timing)
generic map ( tipd_reset => 2 ns,
tipd_clk => 3 ns,
topd_q => 4 ns,
tsetup_reset => 3 ns,
thold_reset => 1 ns )
port map ( reset => reset, clk => clk, q => q );
clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
reset <= '1' after 62 ns, '0' after 106 ns;
end architecture test;
-- end not in book
| gpl-2.0 | c66947a59222aafe709c5eae4a069121 | 0.599332 | 3.815287 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd | 4 | 2,347 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity zmux is
end entity zmux;
library util; use util.stimulus_generators.all;
architecture test of zmux is
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3 when sel1 = '1' and sel0 = '1';
-- end code from book
end block functional_mux;
--------------------------------------------------
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
elsif sel1 = '1' and sel0 = '1' then
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
--------------------------------------------------
stimulus :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
| gpl-2.0 | 256d8d9c37c34b6d2771cd1a958fed2f | 0.590967 | 3.610769 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1711.vhd | 4 | 3,058 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1711.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c09s02b00x00p10n01i01711pkg is
-- Type declarations.
type SWITCH_LEVEL is ( '0', '1', 'X' );
type S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
-- Define the bus resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
-- Further type declarations.
subtype SWITCH_T is switchF SWITCH_LEVEL;
-- type WORD is array(0 to 31) of SWITCH_T;
type WORD is array(1 to 32) of SWITCH_T;
end c09s02b00x00p10n01i01711pkg;
package body c09s02b00x00p10n01i01711pkg is
function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
begin
return( S(1) );
end switchf;
end c09s02b00x00p10n01i01711pkg;
ENTITY c09s02b00x00p10n01i01711ent IS
generic ( GenFive : in INTEGER := 12 );
END c09s02b00x00p10n01i01711ent;
use work.c09s02b00x00p10n01i01711pkg.all;
ARCHITECTURE c09s02b00x00p10n01i01711arch OF c09s02b00x00p10n01i01711ent IS
-- Local constants.
constant Three : integer := 3;
-- Local signals.
signal A : WORD;
BEGIN
-- Test signal arrays indexed using a generic constants. (locally static)
TESTING: PROCESS(A(GenFive))
-- Local variables.
variable INITED : BOOLEAN := FALSE;
variable NewTime: TIME;
BEGIN
-- Perform the first piece of assignments.
if (not(INITED)) then
INITED := TRUE;
A( GenFive ) <= 'X' after 10 ns;
NewTime := NOW + 10 ns;
end if;
if (now = NewTime) then
assert NOT( A(GenFive) = 'X' )
report "***PASSED TEST: c09s02b00x00p10n01i01711"
severity NOTE;
assert ( A(GenFive) = 'X' )
report "***FAILED TEST: c09s02b00x00p10n01i01711 - Signal arrays indexed using a generic constants may be used in the sentitivity list of a porcess statement."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s02b00x00p10n01i01711arch;
| gpl-2.0 | ed063419b33d1aea15527a235a3d83ce | 0.662852 | 3.527105 | false | true | false | false |
nickg/nvc | test/regress/concat3.vhd | 5 | 2,156 | library ieee;
use ieee.std_logic_1164.all;
entity shift_reg is
generic (
WIDTH : positive );
port (
clk : in std_logic;
reset : in std_logic;
shift : in std_logic;
din : in std_logic;
dout : out std_logic );
end entity;
architecture rtl of shift_reg is
signal shift_r : std_logic_vector(WIDTH - 1 downto 0);
begin
shift_p: process (clk) is
begin
if rising_edge(clk) then
if reset = '1' then
shift_r <= (others => '-');
elsif shift = '1' then
shift_r <= shift_r(WIDTH - 2 downto 0) & din;
end if;
end if;
end process;
dout <= shift_r(WIDTH - 1);
end architecture;
-------------------------------------------------------------------------------
entity concat3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of concat3 is
signal clk : std_logic := '1';
signal reset : std_logic := '1';
signal shift : std_logic;
signal din : std_logic;
signal dout : std_logic;
signal running : boolean := true;
begin
clk <= not clk after 10 ns when running;
reset <= '0' after 30 ns;
uut: entity work.shift_reg
generic map (
WIDTH => 4 )
port map (
clk => clk,
reset => reset,
shift => shift,
din => din,
dout => dout );
process is
begin
shift <= '0';
wait until reset = '0';
wait until falling_edge(clk);
shift <= '1';
din <= '0';
wait until falling_edge(clk);
wait until falling_edge(clk);
wait until falling_edge(clk);
wait until falling_edge(clk);
assert dout = '0';
din <= '1';
wait until falling_edge(clk);
assert dout = '0';
wait until falling_edge(clk);
assert dout = '0';
wait until falling_edge(clk);
assert dout = '0';
wait until falling_edge(clk);
assert dout = '1';
running <= false;
wait;
end process;
end architecture;
| gpl-3.0 | ace4111086c67b08188e89dd62066967 | 0.495826 | 3.955963 | false | false | false | false |
tgingold/ghdl | testsuite/synth/const01/const01.vhdl | 1 | 736 | library ieee;
use ieee.std_logic_1164.all;
entity const01 is
port (o : out std_logic_vector(0 to 31));
end const01;
architecture behav of const01 is
type slv_array is array (natural range <>) of std_logic_vector(7 downto 0);
function conv (v : std_logic_vector) return slv_array is
variable r : slv_array(0 to v'length / 8 - 1);
begin
for i in 0 to r'length-1 loop
r (i) := v(v'length - (i*8) - 1 downto v'length - (i*8) - 8);
end loop;
return r;
end conv;
constant init : std_logic_vector (31 downto 0) := x"01020304";
constant res : slv_array (0 to 3) := conv (init);
begin
o (0 to 7) <= res (0);
o (8 to 15) <= res (1);
o (16 to 23) <= res (2);
o (24 to 31) <= res (3);
end behav;
| gpl-2.0 | 95bb613f24a9cbcfce331bce4e422dc8 | 0.60462 | 2.875 | false | false | false | false |
nickg/nvc | test/regress/record11.vhd | 5 | 696 | entity record11 is
end entity;
architecture test of record11 is
type rec is record
x, y : bit;
end record;
signal r : rec;
signal a, b : bit;
begin
process is
begin
r <= ( '1', '0' );
wait for 0 ns;
assert r.x'event;
assert not r.y'event;
assert r.y'active;
assert r'event;
wait for 1 ns;
assert a'event;
assert not b'event;
assert b'active;
assert a = '1';
assert b = '0';
r.y <= '1';
wait for 1 ns;
assert b = '1';
wait;
end process;
update_a: a <= r.x after 1 ns;
update_b: b <= r.y after 1 ns;
end architecture;
| gpl-3.0 | c60d1c8a2e366ea919931b32b6150603 | 0.491379 | 3.428571 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd | 4 | 2,080 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tb_piston is
end tb_piston;
architecture TB_piston of tb_piston is
-- Component declarations
-- Signal declarations
terminal n1, n2 : translational;
begin
-- Signal assignments
-- Component instances
Force1 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => n1,
trans_neg => TRANSLATIONAL_REF
);
mass1 : entity work.piston(simple)
port map(
motion => n1
);
Force2 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => n2,
trans_neg => TRANSLATIONAL_REF
);
mass2 : entity work.mass_t(ideal)
generic map(
m => 10.0
)
port map(
trans1 => n2
);
end TB_piston;
| gpl-2.0 | b0237a0a48e06919f00ef92f7cda2493 | 0.577404 | 4.07045 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/float_pkg.vhdl | 2 | 2,542 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Floating-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
package float_pkg is new IEEE.float_generic_pkg
generic map (
float_exponent_width => 8, -- float32'high
float_fraction_width => 23, -- -float32'low
float_round_style => IEEE.fixed_float_types.round_nearest, -- round nearest algorithm
float_denormalize => true, -- Use IEEE extended floating
float_check_error => true, -- Turn on NAN and overflow processing
float_guard_bits => 3, -- number of guard bits
no_warning => false, -- show warnings
fixed_pkg => IEEE.fixed_pkg
);
| gpl-2.0 | 67be2a985c0d1a67f9d686420a748892 | 0.584186 | 4.4363 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_doHist_0_bram_0/synth/design_1_doHist_0_bram_0.vhd | 1 | 15,494 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doHist_0_bram_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_doHist_0_bram_0;
ARCHITECTURE design_1_doHist_0_bram_0_arch OF design_1_doHist_0_bram_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHist_0_bram_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_doHist_0_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_doHist_0_bram_0_arch : ARCHITECTURE IS "design_1_doHist_0_bram_0,blk_mem_gen_v8_3_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_doHist_0_bram_0_arch: ARCHITECTURE IS "design_1_doHist_0_bram_0,blk_mem_gen_v8_3_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no" &
"_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRIT" &
"E_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DIS" &
"ABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.7492 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.7492 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_doHist_0_bram_0_arch;
| gpl-3.0 | 069389aa2bfd86361f00f7f163138626 | 0.632826 | 3.033281 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2013.vhd | 4 | 11,637 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2013.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02013ent IS
END c07s02b02x00p10n01i02013ent;
ARCHITECTURE c07s02b02x00p10n01i02013arch OF c07s02b02x00p10n01i02013ent IS
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
BEGIN
TESTING: PROCESS
--
-- Constant declarations - for unconstrained types
-- other composite type declarations are in package "COMPOSITE"
--
CONSTANT C0_usa1_1 : t_usa1_1 (st_ind1 ) := C0_csa1_1;
CONSTANT C0_usa1_3 : t_usa1_3 (st_ind3 ) := C0_csa1_3;
CONSTANT C2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
CONSTANT C2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
--
-- Composite VARIABLE declarations
--
VARIABLE V0_usa1_1 : t_usa1_1 (st_ind1 ) ;
VARIABLE V0_usa1_3 : t_usa1_3 (st_ind3 ) ;
VARIABLE V0_csa1_1 : t_csa1_1 ;
VARIABLE V0_csa1_3 : t_csa1_3 ;
VARIABLE V2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
VARIABLE V2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
VARIABLE V2_csa1_1 : t_csa1_1 := C2_csa1_1;
VARIABLE V2_csa1_3 : t_csa1_3 := C2_csa1_3;
--
-- Arrays of the same type, element values, different length
--
VARIABLE V3_usa1_1 : t_usa1_1 ( 1 TO 7 ) ;
VARIABLE V3_usa1_3 : t_usa1_3 ('a' TO 'c' ) ;
--
CONSTANT msg1 : STRING := "ERROR: greater than operator failure: ";
CONSTANT msg2 : STRING := "ERROR: greater than or equal operator failure: ";
BEGIN
--
-- Check greater than operator - CONSTANTS (from package 'composite')
--
ASSERT C2_usa1_1 > C0_usa1_1 REPORT msg1 & "C2>C0_usa1_1" SEVERITY FAILURE;
ASSERT C2_usa1_3 > C0_usa1_3 REPORT msg1 & "C2>C0_usa1_3" SEVERITY FAILURE;
ASSERT C2_csa1_1 > C0_csa1_1 REPORT msg1 & "C2>C0_csa1_1" SEVERITY FAILURE;
ASSERT C2_csa1_3 > C0_csa1_3 REPORT msg1 & "C2>C0_csa1_3" SEVERITY FAILURE;
--
-- Check greater than operator - VARIABLES
--
ASSERT V2_usa1_1 > V0_usa1_1 REPORT msg1 & "V2>V0_usa1_1" SEVERITY FAILURE;
ASSERT V2_usa1_3 > V0_usa1_3 REPORT msg1 & "V2>V0_usa1_3" SEVERITY FAILURE;
ASSERT V2_csa1_1 > V0_csa1_1 REPORT msg1 & "V2>V0_csa1_1" SEVERITY FAILURE;
ASSERT V2_csa1_3 > V0_csa1_3 REPORT msg1 & "V2>V0_csa1_3" SEVERITY FAILURE;
--
-- Check greater than operator - VARIABLES and CONSTANTS
--
ASSERT V2_usa1_1 > C0_usa1_1 REPORT msg1 & "V2>C0_usa1_1" SEVERITY FAILURE;
ASSERT V2_usa1_3 > C0_usa1_3 REPORT msg1 & "V2>C0_usa1_3" SEVERITY FAILURE;
ASSERT V2_csa1_1 > C0_csa1_1 REPORT msg1 & "V2>C0_csa1_1" SEVERITY FAILURE;
ASSERT V2_csa1_3 > C0_csa1_3 REPORT msg1 & "V2>C0_csa1_3" SEVERITY FAILURE;
--
-- Check greater than operator - same type, element values : diff array length
--
ASSERT V2_usa1_1 > V3_usa1_1 REPORT msg1 & "V2>V3_usa1_1" SEVERITY FAILURE;
ASSERT V2_usa1_3 > V3_usa1_3 REPORT msg1 & "V2>V3_usa1_3" SEVERITY FAILURE;
--
-- Check greater than or equal operator - CONSTANTS (from package 'composite')
--
ASSERT C2_usa1_1 >= C0_usa1_1 REPORT msg2 & "C2>=C0_usa1_1" SEVERITY FAILURE;
ASSERT C2_usa1_3 >= C0_usa1_3 REPORT msg2 & "C2>=C0_usa1_3" SEVERITY FAILURE;
ASSERT C2_csa1_1 >= C0_csa1_1 REPORT msg2 & "C2>=C0_csa1_1" SEVERITY FAILURE;
ASSERT C2_csa1_3 >= C0_csa1_3 REPORT msg2 & "C2>=C0_csa1_3" SEVERITY FAILURE;
--
-- Check greater than or equal operator - VARIABLES
--
ASSERT V2_usa1_1 >= V0_usa1_1 REPORT msg2 & "V2>=V0_usa1_1" SEVERITY FAILURE;
ASSERT V2_usa1_3 >= V0_usa1_3 REPORT msg2 & "V2>=V0_usa1_3" SEVERITY FAILURE;
ASSERT V2_csa1_1 >= V0_csa1_1 REPORT msg2 & "V2>=V0_csa1_1" SEVERITY FAILURE;
ASSERT V2_csa1_3 >= V0_csa1_3 REPORT msg2 & "V2>=V0_csa1_3" SEVERITY FAILURE;
--
-- Check greater than or equal operator - VARIABLES and CONSTANTS
--
ASSERT V2_usa1_1 >= C0_usa1_1 REPORT msg2 & "V2>=C0_usa1_1" SEVERITY FAILURE;
ASSERT V2_usa1_3 >= C0_usa1_3 REPORT msg2 & "V2>=C0_usa1_3" SEVERITY FAILURE;
ASSERT V2_csa1_1 >= C0_csa1_1 REPORT msg2 & "V2>=C0_csa1_1" SEVERITY FAILURE;
ASSERT V2_csa1_3 >= C0_csa1_3 REPORT msg2 & "V2>=C0_csa1_3" SEVERITY FAILURE;
--
-- Check greater than or equal operator - same type, element values : diff array length
--
ASSERT V2_usa1_1 >= V3_usa1_1 REPORT msg2 & "V2>=V3_usa1_1" SEVERITY FAILURE;
ASSERT V2_usa1_3 >= V3_usa1_3 REPORT msg2 & "V2>=V3_usa1_3" SEVERITY FAILURE;
--
-- Check greater than or equal operator - CONSTANTS (from package 'composite')
--
ASSERT C0_usa1_1 >= C0_usa1_1 REPORT msg2 & "C0>=C0_usa1_1" SEVERITY FAILURE;
ASSERT C0_usa1_3 >= C0_usa1_3 REPORT msg2 & "C0>=C0_usa1_3" SEVERITY FAILURE;
ASSERT C0_csa1_1 >= C0_csa1_1 REPORT msg2 & "C0>=C0_csa1_1" SEVERITY FAILURE;
ASSERT C0_csa1_3 >= C0_csa1_3 REPORT msg2 & "C0>=C0_csa1_3" SEVERITY FAILURE;
--
-- Check greater than or equal operator - VARIABLES
--
ASSERT V0_usa1_1 >= V0_usa1_1 REPORT msg2 & "V0>=V0_usa1_1" SEVERITY FAILURE;
ASSERT V0_usa1_3 >= V0_usa1_3 REPORT msg2 & "V0>=V0_usa1_3" SEVERITY FAILURE;
ASSERT V0_csa1_1 >= V0_csa1_1 REPORT msg2 & "V0>=V0_csa1_1" SEVERITY FAILURE;
ASSERT V0_csa1_3 >= V0_csa1_3 REPORT msg2 & "V0>=V0_csa1_3" SEVERITY FAILURE;
--
-- Check greater than or equal operator - VARIABLES and CONSTANTS
--
ASSERT V0_usa1_1 >= C0_usa1_1 REPORT msg2 & "V0>=C0_usa1_1" SEVERITY FAILURE;
ASSERT V0_usa1_3 >= C0_usa1_3 REPORT msg2 & "V0>=C0_usa1_3" SEVERITY FAILURE;
ASSERT V0_csa1_1 >= C0_csa1_1 REPORT msg2 & "V0>=C0_csa1_1" SEVERITY FAILURE;
ASSERT V0_csa1_3 >= C0_csa1_3 REPORT msg2 & "V0>=C0_csa1_3" SEVERITY FAILURE;
wait for 5 ns;
assert NOT( C2_usa1_1 > C0_usa1_1 and
C2_usa1_3 > C0_usa1_3 and
C2_csa1_1 > C0_csa1_1 and
C2_csa1_3 > C0_csa1_3 and
V2_usa1_1 > V0_usa1_1 and
V2_usa1_3 > V0_usa1_3 and
V2_csa1_1 > V0_csa1_1 and
V2_csa1_3 > V0_csa1_3 and
V2_usa1_1 > C0_usa1_1 and
V2_usa1_3 > C0_usa1_3 and
V2_csa1_1 > C0_csa1_1 and
V2_csa1_3 > C0_csa1_3 and
V2_usa1_1 > V3_usa1_1 and
V2_usa1_3 > V3_usa1_3 and
C2_usa1_1 >= C0_usa1_1 and
C2_usa1_3 >= C0_usa1_3 and
C2_csa1_1 >= C0_csa1_1 and
C2_csa1_3 >= C0_csa1_3 and
V2_usa1_1 >= V0_usa1_1 and
V2_usa1_3 >= V0_usa1_3 and
V2_csa1_1 >= V0_csa1_1 and
V2_csa1_3 >= V0_csa1_3 and
V2_usa1_1 >= C0_usa1_1 and
V2_usa1_3 >= C0_usa1_3 and
V2_csa1_1 >= C0_csa1_1 and
V2_csa1_3 >= C0_csa1_3 and
V2_usa1_1 >= V3_usa1_1 and
V2_usa1_3 >= V3_usa1_3 and
C0_usa1_1 >= C0_usa1_1 and
C0_usa1_3 >= C0_usa1_3 and
C0_csa1_1 >= C0_csa1_1 and
C0_csa1_1 >= C0_csa1_1 and
V0_usa1_1 >= V0_usa1_1 and
V0_usa1_3 >= V0_usa1_3 and
V0_csa1_1 >= V0_csa1_1 and
V0_csa1_3 >= V0_csa1_3 and
V0_usa1_1 >= C0_usa1_1 and
V0_usa1_3 >= C0_usa1_3 and
V0_csa1_1 >= C0_csa1_1 and
V0_csa1_3 >= C0_csa1_3 )
report "***PASSED TEST: c07s02b02x00p10n01i02013"
severity NOTE;
assert ( C2_usa1_1 > C0_usa1_1 and
C2_usa1_3 > C0_usa1_3 and
C2_csa1_1 > C0_csa1_1 and
C2_csa1_3 > C0_csa1_3 and
V2_usa1_1 > V0_usa1_1 and
V2_usa1_3 > V0_usa1_3 and
V2_csa1_1 > V0_csa1_1 and
V2_csa1_3 > V0_csa1_3 and
V2_usa1_1 > C0_usa1_1 and
V2_usa1_3 > C0_usa1_3 and
V2_csa1_1 > C0_csa1_1 and
V2_csa1_3 > C0_csa1_3 and
V2_usa1_1 > V3_usa1_1 and
V2_usa1_3 > V3_usa1_3 and
C2_usa1_1 >= C0_usa1_1 and
C2_usa1_3 >= C0_usa1_3 and
C2_csa1_1 >= C0_csa1_1 and
C2_csa1_3 >= C0_csa1_3 and
V2_usa1_1 >= V0_usa1_1 and
V2_usa1_3 >= V0_usa1_3 and
V2_csa1_1 >= V0_csa1_1 and
V2_csa1_3 >= V0_csa1_3 and
V2_usa1_1 >= C0_usa1_1 and
V2_usa1_3 >= C0_usa1_3 and
V2_csa1_1 >= C0_csa1_1 and
V2_csa1_3 >= C0_csa1_3 and
V2_usa1_1 >= V3_usa1_1 and
V2_usa1_3 >= V3_usa1_3 and
C0_usa1_1 >= C0_usa1_1 and
C0_usa1_3 >= C0_usa1_3 and
C0_csa1_1 >= C0_csa1_1 and
C0_csa1_1 >= C0_csa1_1 and
V0_usa1_1 >= V0_usa1_1 and
V0_usa1_3 >= V0_usa1_3 and
V0_csa1_1 >= V0_csa1_1 and
V0_csa1_3 >= V0_csa1_3 and
V0_usa1_1 >= C0_usa1_1 and
V0_usa1_3 >= C0_usa1_3 and
V0_csa1_1 >= C0_csa1_1 and
V0_csa1_3 >= C0_csa1_3 )
report "***FAILED TEST: c07s02b02x00p10n01i02013 - Ordering operators >, >= for composite type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02013arch;
| gpl-2.0 | 02fe8478fd77f91f87a5a0bb78a2ce17 | 0.555641 | 2.653215 | false | false | false | false |
nickg/nvc | test/simp/issue425.vhd | 1 | 6,310 | -----------------------------------------------------------------------------------
-- Used to crash randomly during constant folding
-----------------------------------------------------------------------------------
package SMPL_TYPES is
constant SMPL_ADDR_MAX_WIDTH : integer := 64;
constant SMPL_DATA_MAX_WIDTH : integer := 1024;
constant SMPL_STRB_MAX_WIDTH : integer := SMPL_DATA_MAX_WIDTH/8;
constant SMPL_SIZE_MAX_WIDTH : integer := 8;
constant SMPL_INFO_WIDTH : integer := 4;
subtype SMPL_INFO_TYPE is bit_vector(SMPL_INFO_WIDTH-1 downto 0);
constant SMPL_RESP_WIDTH : integer := 2;
subtype SMPL_RESP_TYPE is bit_vector(SMPL_RESP_WIDTH-1 downto 0);
type SMPL_A_SIGNALS_TYPE is record
ADDR : bit_vector(SMPL_ADDR_MAX_WIDTH-1 downto 0);
WRITE : bit;
SIZE : bit_vector(SMPL_SIZE_MAX_WIDTH-1 downto 0);
INFO : SMPL_INFO_TYPE;
VALID : bit;
READY : bit;
end record;
constant SMPL_A_SIGNALS_DONTCARE : SMPL_A_SIGNALS_TYPE := (
ADDR => (others => '1'),
WRITE => '1',
SIZE => (others => '1'),
INFO => (others => '1'),
VALID => '1',
READY => '1'
);
constant SMPL_A_SIGNALS_NULL : SMPL_A_SIGNALS_TYPE := (
ADDR => (others => '0'),
WRITE => '0',
SIZE => (others => '0'),
INFO => (others => '0'),
VALID => '0',
READY => '0'
);
type SMPL_W_SIGNALS_TYPE is record
DATA : bit_vector(SMPL_DATA_MAX_WIDTH-1 downto 0);
STRB : bit_vector(SMPL_STRB_MAX_WIDTH-1 downto 0);
VALID : bit;
READY : bit;
end record;
constant SMPL_W_SIGNALS_DONTCARE : SMPL_W_SIGNALS_TYPE := (
DATA => (others => '1'),
STRB => (others => '1'),
VALID => '1',
READY => '1'
);
constant SMPL_W_SIGNALS_NULL : SMPL_W_SIGNALS_TYPE := (
DATA => (others => '0'),
STRB => (others => '0'),
VALID => '0',
READY => '0'
);
type SMPL_R_SIGNALS_TYPE is record
DATA : bit_vector(SMPL_DATA_MAX_WIDTH-1 downto 0);
RESP : SMPL_RESP_TYPE;
VALID : bit;
READY : bit;
end record;
constant SMPL_R_SIGNALS_DONTCARE : SMPL_R_SIGNALS_TYPE := (
DATA => (others => '1'),
RESP => (others => '1'),
VALID => '1',
READY => '1'
);
constant SMPL_R_SIGNALS_NULL : SMPL_R_SIGNALS_TYPE := (
DATA => (others => '0'),
RESP => (others => '0'),
VALID => '0',
READY => '0'
);
type SMPL_B_SIGNALS_TYPE is record
RESP : SMPL_RESP_TYPE;
VALID : bit;
READY : bit;
end record;
constant SMPL_B_SIGNALS_DONTCARE : SMPL_B_SIGNALS_TYPE := (
RESP => (others => '1'),
VALID => '1',
READY => '1'
);
constant SMPL_B_SIGNALS_NULL : SMPL_B_SIGNALS_TYPE := (
RESP => (others => '0'),
VALID => '0',
READY => '0'
);
type SMPL_SIGNALS_TYPE is record
AR : SMPL_A_SIGNALS_TYPE;
AW : SMPL_A_SIGNALS_TYPE;
R : SMPL_R_SIGNALS_TYPE;
W : SMPL_W_SIGNALS_TYPE;
B : SMPL_B_SIGNALS_TYPE;
end record;
constant SMPL_SIGNALS_DONTCARE : SMPL_SIGNALS_TYPE := (
AR => SMPL_A_SIGNALS_DONTCARE,
AW => SMPL_A_SIGNALS_DONTCARE,
R => SMPL_R_SIGNALS_DONTCARE,
W => SMPL_W_SIGNALS_DONTCARE,
B => SMPL_B_SIGNALS_DONTCARE
);
end SMPL_TYPES;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
use WORK.SMPL_TYPES.all;
entity CHANNEL_PLAYER is
generic (
CHANNEL : integer;
MASTER : boolean := FALSE
);
end CHANNEL_PLAYER;
architecture MODEL of CHANNEL_PLAYER is
function GEN_INIT_signals return SMPL_SIGNALS_TYPE is
variable value : SMPL_SIGNALS_TYPE;
begin
value := SMPL_SIGNALS_DONTCARE;
if (MASTER) then
case CHANNEL is
when 1 =>
value.AR := SMPL_A_SIGNALS_NULL;
value.AR.READY := '1';
when 2 =>
value.AW := SMPL_A_SIGNALS_NULL;
value.AW.READY := '1';
when 3 =>
value.W := SMPL_W_SIGNALS_NULL;
value.W.READY := '1';
when 4 =>
value.R := SMPL_R_SIGNALS_DONTCARE;
value.R.READY := '0';
when 5 =>
value.B := SMPL_B_SIGNALS_DONTCARE;
value.B.READY := '0';
when others =>
null;
end case;
end if;
return value;
end function;
constant INIT_SIGNALS : SMPL_SIGNALS_TYPE := GEN_INIT_SIGNALS;
begin
process
variable out_signals : SMPL_SIGNALS_TYPE;
begin
out_signals := INIT_SIGNALS;
wait;
end process;
end MODEL;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
entity MASTER_PLAYER is
end MASTER_PLAYER;
architecture MODEL of MASTER_PLAYER is
begin
C0: entity WORK.CHANNEL_PLAYER generic map (0, FALSE);
C1: entity WORK.CHANNEL_PLAYER generic map (1, TRUE );
C2: entity WORK.CHANNEL_PLAYER generic map (2, TRUE );
C3: entity WORK.CHANNEL_PLAYER generic map (3, TRUE );
C4: entity WORK.CHANNEL_PLAYER generic map (4, TRUE );
C5: entity WORK.CHANNEL_PLAYER generic map (5, TRUE );
end MODEL;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
entity issue425 is
end issue425;
architecture MODEL of issue425 is
begin
M: entity WORK.MASTER_PLAYER;
S: entity WORK.MASTER_PLAYER;
end MODEL;
| gpl-3.0 | e5167c430b12d16a3aa3a16a13745ae7 | 0.445642 | 4.034527 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispout01/tb_rec08.vhdl | 1 | 483 | entity tb_rec08 is
end tb_rec08;
library ieee;
use ieee.std_logic_1164.all;
use work.rec08_pkg.all;
architecture behav of tb_rec08 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec08
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r = (a => "1", b => '0') severity failure;
inp <= '0';
wait for 1 ns;
assert r = (a => "0", b => '1') severity failure;
wait;
end process;
end behav;
| gpl-2.0 | a7a56658620beff22c39ec9de0594f89 | 0.590062 | 2.96319 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/non_compliant/ch_03_ch_03_09.vhd | 4 | 2,040 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_09.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_03_09 is
end entity ch_03_09;
----------------------------------------------------------------
architecture test of ch_03_09 is
begin
process_3_2_d : process is
-- code from book:
variable N : integer := 1;
--
constant C : integer := 1;
-- end of code from book
constant expression : integer := 7;
begin
-- code from book:
-- error: Case choice must be a locally static expression
-- case expression is -- example of an illegal case statement
-- when N | N+1 => -- . . .
-- when N+2 to N+5 => -- . . .
-- when others => -- . . .
-- end case;
--
case expression is
when C | C+1 => -- . . .
when C+2 to C+5 => -- . . .
when others => -- . . .
end case;
-- end of code from book
wait;
end process process_3_2_d;
end architecture test;
| gpl-2.0 | 6a1cdbb7f433ccb37ea3fa2202a1bb0b | 0.519608 | 4.312896 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/sub_217.vhd | 2 | 1,725 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_217 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_217;
architecture augh of sub_217 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
ge <= tmp_ge;
end architecture;
| gpl-2.0 | d613b2deaeec4053d30365840d179813 | 0.624348 | 2.578475 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2277.vhd | 4 | 2,391 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2277.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02277ent IS
END c07s02b06x00p14n01i02277ent;
ARCHITECTURE c07s02b06x00p14n01i02277arch OF c07s02b06x00p14n01i02277ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable INTV : INTEGER;
variable DISTV : DISTANCE;
BEGIN
INTV := INTV / DISTV; -- ERROR:
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02277 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02277arch;
| gpl-2.0 | 61a6c6b81cce19a51d175f829efd82cb | 0.580928 | 4.038851 | false | true | false | false |
rogerluan/Arquitetura-PUC-Campinas-2016 | Project 2/uc.vhd | 1 | 8,341 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.components.all ;
USE ieee.std_logic_arith;
ENTITY uc IS
PORT ( Data : IN STD_LOGIC_VECTOR(24 DOWNTO 0) ;
Clock: IN STD_LOGIC ;
Imedout : OUT STD_LOGIC ;
Rin : OUT STD_LOGIC_VECTOR(0 TO 3) ;
Rout : OUT STD_LOGIC_VECTOR(0 TO 3) ;
Rtempin : OUT STD_LOGIC_VECTOR(0 TO 1) ;
Rtempout : OUT STD_LOGIC_VECTOR(0 TO 1) ;
Rsysin : OUT STD_LOGIC ;
Rsysout : OUT STD_LOGIC ;
ULA : OUT STD_LOGIC ;
debug_state: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ;
END uc ;
ARCHITECTURE Behavior OF uc IS
TYPE States IS (DECODE,
MOVI,
MOV,
XCHG_1, XCHG_2, XCHG_3,
ARITH_IN, ARITH_OUT,
ADD, ADDI, SUB, SUBI) ;
SIGNAL state : States := DECODE;
SIGNAL instruction : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL regSource, regTarget, regDest : STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock ='1') THEN
CASE state IS
WHEN DECODE =>
debug_state <= "0000";
instruction <= Data(24 DOWNTO 22) ;
CASE instruction IS
WHEN "001" => --MOVI
state <= MOVI;
WHEN "010" => --MOV
state <= MOV;
WHEN "011" => --XCHG
state <= XCHG_1;
WHEN "100" | "101" | "110" | "111" => --ARITHMETICS
state <= ARITH_IN;
WHEN OTHERS => --No changes
state <= DECODE;
END CASE;
--Every signal is zero
Imedout <= '0';
Rin <= "0000";
Rout <= "0000";
Rtempin <= "00";
Rtempout <= "00";
Rsysin <= '0';
Rsysout <= '0';
ULA <= '0';
WHEN MOVI =>
debug_state <= "0001";
regDest <= Data(21 DOWNTO 20);
Rin <= "0000";
CASE regDest IS
WHEN "00" =>
Rin(0) <= '1';
WHEN "01" =>
Rin(1) <= '1';
WHEN "10" =>
Rin(2) <= '1';
WHEN "11" =>
Rin(3) <= '1';
END CASE;
Imedout <= '1';
--Zero all the rest
Rout <= "0000";
Rtempin <= "00";
Rtempout <= "00";
Rsysin <= '0';
Rsysout <= '0';
ULA <= '0';
--Sets the next state
state <= DECODE;
WHEN MOV =>
debug_state <= "0010";
regDest <= Data(21 DOWNTO 20);
regSource <= Data(19 DOWNTO 18);
Rin <= "0000";
CASE regDest IS
WHEN "00" =>
Rin(0) <= '1';
WHEN "01" =>
Rin(1) <= '1';
WHEN "10" =>
Rin(2) <= '1';
WHEN "11" =>
Rin(3) <= '1';
END CASE;
Rout <= "0000";
CASE regSource IS
WHEN "00" =>
Rout(0) <= '1';
WHEN "01" =>
Rout(1) <= '1';
WHEN "10" =>
Rout(2) <= '1';
WHEN "11" =>
Rout(3) <= '1';
END CASE;
--Zero all the rest
Imedout <= '0';
Rtempin <= "00";
Rtempout <= "00";
Rsysin <= '0';
Rsysout <= '0';
ULA <= '0';
--Sets the next state
state <= DECODE;
WHEN XCHG_1 =>
debug_state <= "0011";
regSource <= Data(21 DOWNTO 20); --First register in XCHG call
Rout <= "0000";
CASE regSource IS
WHEN "00" =>
Rout(0) <= '1';
WHEN "01" =>
Rout(1) <= '1';
WHEN "10" =>
Rout(2) <= '1';
WHEN "11" =>
Rout(3) <= '1';
END CASE;
Rsysin <= '1';
--Zero all the rest
Imedout <= '0';
Rin <= "0000";
Rtempin <= "00";
Rtempout <= "00";
Rsysout <= '0';
ULA <= '0';
--Sets the next state
state <= XCHG_2;
WHEN XCHG_2 =>
debug_state <= "0100";
regDest <= Data(21 DOWNTO 20); --First register in XCHG call
regSource <= Data(19 DOWNTO 18); --Second register in XCHG call
Rout <= "0000";
CASE regSource IS
WHEN "00" =>
Rout(0) <= '1';
WHEN "01" =>
Rout(1) <= '1';
WHEN "10" =>
Rout(2) <= '1';
WHEN "11" =>
Rout(3) <= '1';
END CASE;
Rin <= "0000";
CASE regDest IS
WHEN "00" =>
Rin(0) <= '1';
WHEN "01" =>
Rin(1) <= '1';
WHEN "10" =>
Rin(2) <= '1';
WHEN "11" =>
Rin(3) <= '1';
END CASE;
--Zero all the rest
Imedout <= '0';
Rtempin <= "00";
Rtempout <= "00";
Rsysin <= '0';
Rsysout <= '0';
ULA <= '0';
--Sets the next state
state <= XCHG_3;
WHEN XCHG_3 =>
debug_state <= "0101";
regDest <= Data(19 DOWNTO 18); --Second register in XCHG call
Rin <= "0000";
CASE regDest IS
WHEN "00" =>
Rin(0) <= '1';
WHEN "01" =>
Rin(1) <= '1';
WHEN "10" =>
Rin(2) <= '1';
WHEN "11" =>
Rin(3) <= '1';
END CASE;
Rsysout <= '1';
--Zero all the rest
Imedout <= '0';
Rout <= "0000";
Rtempin <= "00";
Rtempout <= "00";
Rsysin <= '0';
ULA <= '0';
--Sets the next state
state <= DECODE;
WHEN ARITH_IN =>
debug_state <= "0110";
regSource <= Data(19 DOWNTO 18); --Second register in ARITH call
Rout <= "0000";
CASE regSource IS
WHEN "00" =>
Rout(0) <= '1';
WHEN "01" =>
Rout(1) <= '1';
WHEN "10" =>
Rout(2) <= '1';
WHEN "11" =>
Rout(3) <= '1';
END CASE;
Rtempin <= "01"; --Opens the IN stream in TEMP1 register
--Zero all the rest
Imedout <= '0';
Rin <= "0000";
Rtempout <= "00";
Rsysin <= '0';
Rsysout <= '0';
ULA <= '0';
--Sets the next state
CASE instruction IS
WHEN "100" =>
state <= ADD;
WHEN "101" =>
state <= ADDI;
WHEN "110" =>
state <= SUB;
WHEN "111" =>
state <= SUBI;
WHEN OTHERS =>
state <= DECODE; --an error occurred
END CASE;
WHEN ARITH_OUT =>
debug_state <= "0111";
regDest <= Data(21 DOWNTO 20); --First register in ARITH call
Rin <= "0000";
CASE regDest IS
WHEN "00" =>
Rin(0) <= '1';
WHEN "01" =>
Rin(1) <= '1';
WHEN "10" =>
Rin(2) <= '1';
WHEN "11" =>
Rin(3) <= '1';
END CASE;
Rtempout <= "10"; --Opens the OUT stream in TEMP2 register
--Zero all the rest
Imedout <= '0';
Rout <= "0000";
Rtempin <= "00";
Rsysin <= '0';
Rsysout <= '0';
ULA <= '0';
--Sets the next state
state <= ARITH_OUT;
WHEN ADD =>
debug_state <= "1000";
regTarget <= Data(17 DOWNTO 16); --Third register in ARITH call
Rout <= "0000";
CASE regTarget IS
WHEN "00" =>
Rout(0) <= '1';
WHEN "01" =>
Rout(1) <= '1';
WHEN "10" =>
Rout(2) <= '1';
WHEN "11" =>
Rout(3) <= '1';
END CASE;
Rtempin <= "10"; --Opens the IN stream in TEMP2 register
ULA <= '0'; --This should be the signal for SUM
--Zero all the rest
Imedout <= '0';
Rin <= "0000";
Rtempout <= "00";
Rsysin <= '0';
Rsysout <= '0';
--Sets the next state
state <= ARITH_OUT;
WHEN ADDI =>
debug_state <= "1001";
Imedout <= '1';
Rtempin <= "10"; --Opens the IN stream in TEMP2 register
ULA <= '0'; --This should be the signal for SUM
--Zero all the rest
Rin <= "0000";
Rout <= "0000";
Rtempout <= "00";
Rsysin <= '0';
Rsysout <= '0';
--Sets the next state
state <= ARITH_OUT;
WHEN SUB =>
debug_state <= "1010";
regTarget <= Data(17 DOWNTO 16); --Third register in ARITH call
Rout <= "0000";
CASE regTarget IS
WHEN "00" =>
Rout(0) <= '1';
WHEN "01" =>
Rout(1) <= '1';
WHEN "10" =>
Rout(2) <= '1';
WHEN "11" =>
Rout(3) <= '1';
END CASE;
Rtempin <= "10"; --Opens the IN signal in TEMP2 register
ULA <= '1'; --This should be the signal for SUBTRACTION
--Zero all the rest
Imedout <= '0';
Rin <= "0000";
Rtempout <= "00";
Rsysin <= '0';
Rsysout <= '0';
--Sets the next state
state <= ARITH_OUT;
WHEN SUBI =>
debug_state <= "1011";
Imedout <= '1';
Rtempin <= "10"; --Opens the IN stream in TEMP2 register
ULA <= '1'; --This should be the signal for SUBTRACTION
--Zero all the rest
Rin <= "0000";
Rout <= "0000";
Rtempout <= "00";
Rsysin <= '0';
Rsysout <= '0';
--Sets the next state
state <= ARITH_OUT;
END CASE ;
END IF ;
END PROCESS ;
END Behavior ; | mit | 7fa92a86243d14c24ecbcc8b6f005ef7 | 0.46745 | 3.037509 | false | false | false | false |
nickg/nvc | test/regress/wait25.vhd | 1 | 1,004 | entity wait25 is
end entity;
architecture test of wait25 is
signal a, b, c, d : natural;
begin
p1: process (a, b) is
begin
report "P1: a=" & integer'image(a) & " b=" & integer'image(b);
end process;
p2: process is
begin
wait on c, d for 3 ns;
report "P2: c=" & integer'image(c) & " d=" & integer'image(d);
assert now = 3 ns;
assert c = 0;
assert d = 0;
wait on c, d;
report "P2: c=" & integer'image(c) & " d=" & integer'image(d);
assert now = 5 ns;
assert c = 1;
assert d = 1;
wait on c, d for 1 ns;
assert now = 6 ns;
assert c = 2;
assert d = 1;
wait for 1 ns;
assert now = 7 ns;
wait;
end process;
stim: process is
begin
wait for 1 ns;
a <= 1;
b <= 1;
wait for 4 ns;
c <= 1;
d <= 1;
c <= transport 2 after 1 ns;
wait;
end process;
end architecture;
| gpl-3.0 | 7b7d68fa78417d3bc9d863e0ed6e4b5e | 0.471116 | 3.369128 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3039.vhd | 4 | 2,170 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3039.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p01n02i03039ent IS
END c12s02b02x00p01n02i03039ent;
ARCHITECTURE c12s02b02x00p01n02i03039arch OF c12s02b02x00p01n02i03039ent IS
BEGIN
-- test for first and last element associations
bl5: block
generic(i:integer:=10; r:real:=3.4; b:bit:='1');
generic map(i=>5,b=>'0');
begin
assert (i=5)
report "Generic map value for integer generic not correct"
severity failure;
assert (r=3.4)
report "Default value for real generic not correct"
severity failure;
assert (b='0')
report "Generic map value for bit generic not correct"
severity failure;
assert NOT( i=5 and r=3.4 and b='0')
report "***PASSED TEST: c12s02b02x00p01n02i03039"
severity NOTE;
assert ( i=5 and r=3.4 and b='0')
report "***FAILED TEST: c12s02b02x00p01n02i03039 - The actual part of an implicit association element is the default expression test failed."
severity ERROR;
end block;
END c12s02b02x00p01n02i03039arch;
| gpl-2.0 | bdc61851fce614320766ef285b352fe1 | 0.667742 | 3.659359 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1310/issue2.vhdl | 1 | 601 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue2 is
end issue2;
architecture beh of issue2 is
begin
assert (unsigned'("1111") > unsigned'("0111"));
assert (unsigned'("1111") >= unsigned'("0111"));
assert (unsigned'("0111") < unsigned'("1111"));
assert (unsigned'("0111") <= unsigned'("1111"));
assert (signed'("0111") > signed'("1111"));
assert (signed'("0111") >= signed'("1111"));
assert (signed'("1111") < signed'("0111"));
assert (signed'("1111") <= signed'("0111"));
assert signed'("1111") = -1;
end architecture beh;
| gpl-2.0 | 07454fa744b1758632ca78f33a34e594 | 0.607321 | 3.709877 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1238/tb_tri.vhdl | 1 | 546 | entity tb_tri is
end tb_tri;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_tri is
signal i : std_logic;
signal en : std_logic;
signal o : std_logic;
begin
dut: entity work.tri
port map (i, en, o);
process
begin
i <= '1';
en <= '1';
wait for 1 ns;
assert o = '1' severity failure;
i <= '0';
en <= '1';
wait for 1 ns;
assert o = '0' severity failure;
i <= '1';
en <= '0';
wait for 1 ns;
assert o = 'Z' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 84c9255d4e41f017afccb176e5987659 | 0.56044 | 3.033333 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/util/src_pulse.vhd | 4 | 2,373 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- Voltage Pulse Source (Includes Frequency Domain settings)
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity src_pulse is
generic ( initial : real := 0.0; -- initial value
pulse : real; -- pulsed value
ti2p : real; -- transition time - initial to pulse
tp2i : real; -- transition time - pulse to initial
delay : time := 0ms; -- delay time
width : time; -- duration of pulse (includes ti2p)
period : time; -- period
ac_mag : real := 1.0; -- AC magnitude
ac_phase : real := 0.0 ); -- AC phase (degrees)
port ( quantity output : out real );
end entity src_pulse;
architecture ideal of src_pulse is
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi * ac_phase / 360.0;
-- Signal and constant used in process below
signal pulse_signal : real := initial;
constant low_width: time := period - width;
begin
if domain = quiescent_domain or domain = time_domain use
output == pulse_signal'ramp(ti2p, tp2i);
else
output == ac_spec; -- used for frequency (AC) analysis
end use;
-- Process to create events on pulse_signal used for rise and fall edges
proc1 : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for width;
pulse_signal <= initial;
wait for low_width;
end loop;
end process;
end architecture ideal;
| gpl-2.0 | c04d45134c4b9f2767951f30bcfc5946 | 0.656553 | 4.098446 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_traversal.vhd | 4 | 1,721 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity list_traversal is
end entity list_traversal;
----------------------------------------------------------------
architecture test of list_traversal is
signal s : bit_vector(0 to 3);
begin
process is
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list, current_cell : value_ptr;
begin
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
-- code from book:
current_cell := value_list;
while current_cell /= null loop
s <= current_cell.value;
wait for 10 ns;
current_cell := current_cell.next_cell;
end loop;
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 | bac8ef5c5b5a5d5cabd00ac47a97f71e | 0.658338 | 4.011655 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/simple-subtypes.vhdl | 4 | 1,760 | entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is severity_level range NOTE to ERROR;
subtype tinteger is integer range 1111 to 2222;
subtype treal is real range 1.11 to 2.22;
subtype ttime is time range 1 ns to 1 hr;
subtype tnatural is natural range 100 to 200;
subtype tpositive is positive range 1000 to 2000;
variable k1 : tboolean;
variable k2 : tbit;
variable k3 : tcharacter;
variable k4 : tseverity_level;
variable k5 : tinteger;
variable k6 : treal;
variable k7 : ttime;
variable k8 : tnatural;
variable k9 : tpositive;
begin -- process doit
assert( k1 = tboolean'left ) report "TEST FAILED" severity failure;
assert( k2 = tbit'left ) report "TEST FAILED" severity FAILURE;
assert( k3 = tcharacter'left ) report "TEST FAILED" severity FAILURE;
assert( k4 = tseverity_level'left ) report "TEST FAILED" severity FAILURE;
assert( k5 = tinteger'left ) report "TEST FAILED" severity FAILURE;
assert( k6 = treal'left ) report "TEST FAILED" severity FAILURE;
assert( k7 = ttime'left ) report "TEST FAILED" severity FAILURE;
assert( k8 = tnatural'left ) report "TEST FAILED" severity FAILURE;
assert( k9 = tpositive'left ) report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process doit;
end only;
| gpl-2.0 | 9174c7eeb8a00dd56f1fb7674fe6dd8b | 0.609091 | 3.911111 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1310/issue.vhdl | 1 | 727 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port (sig_gt, sig_ge, sig_lt, sig_le : out boolean;
uns_gt, uns_ge, uns_lt, uns_le : out boolean);
end issue;
architecture beh of issue is
begin
-- all of those works
uns_gt <= (unsigned'("1111") > unsigned'("0111"));
uns_ge <= (unsigned'("1111") >= unsigned'("0111"));
uns_lt <= (unsigned'("1111") < unsigned'("0111"));
uns_le <= (unsigned'("1111") <= unsigned'("0111"));
sig_gt <= (signed'("1111") > signed'("0111"));
sig_ge <= (signed'("1111") >= signed'("0111"));
sig_lt <= (signed'("1111") < signed'("0111"));
sig_le <= (signed'("1111") <= signed'("0111"));
end architecture beh;
| gpl-2.0 | ec709c11c607c95dcadb0d2a26d5f4c4 | 0.572215 | 3.289593 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/sub_160.vhd | 2 | 1,735 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_160 is
port (
le : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end sub_160;
architecture augh of sub_160 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
le <= tmp_le;
end architecture;
| gpl-2.0 | 8a2c1da89a77594d4a75d38119355ba3 | 0.626513 | 2.597305 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/axistream_to_whin.vhd | 1 | 5,114 |
-------------------------------------------------------------------------------------
-- FILE NAME :
--
-- AUTHOR : Luis F Munoz
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity -
-- architecture -
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Conversion between a AXI-Stream Slave to a StellarIP wormhole input. Use when
-- there is StellarIP Block that has a WH_IN interface but we really want a AXI-Stream Slave
-- interface. For example a DAC.
--
-- AXI-Stream Master -> AXI-Stream Slave to WH_OUT (this entity) -> WH_IN
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity axistream_to_whin is
port (
-- global
clk : in std_logic;
rst : in std_logic;
--Wormhole 'data_in' of type 'axis_32b_in':
data_in_tdata : in std_logic_vector(63 downto 0);
data_in_tkeep : out std_logic_vector(3 downto 0);
data_in_tlast : in std_logic;
data_in_tready : out std_logic;
data_in_tstrb : out std_logic;
data_in_tuser : in std_logic_vector(31 downto 0);
data_in_tvalid : in std_logic;
--Wormhole 'data_out' of type 'wh_out':
data_out_out_stop : in std_logic;
data_out_out_dval : out std_logic;
data_out_out_data : out std_logic_vector(63 downto 0)
);
end entity axistream_to_whin;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture behavioural of axistream_to_whin is
--***********************************************************************************
begin
--***********************************************************************************
-- AXI-Stream Standard says these should be HIGH when not used.
data_in_tstrb <= '1';
data_in_tkeep <= (others => '1');
process(clk, rst)
begin
if rising_edge(clk) then
data_out_out_data <= data_in_tdata;
data_out_out_dval <= data_in_tvalid;
data_in_tready <= not data_out_out_stop;
end if;
end process;
--***********************************************************************************
end architecture behavioural;
--***********************************************************************************
| mit | 6fe73baafaa622dbc4a80233579102b9 | 0.41709 | 5.15005 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2289.vhd | 4 | 2,236 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2289.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02289ent IS
END c07s02b06x00p32n01i02289ent;
ARCHITECTURE c07s02b06x00p32n01i02289arch OF c07s02b06x00p32n01i02289ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( ((1 ns * 1000) = 1 us) and
((1 us * 1000) = 1 ms) and
((1 ms * 1000) = 1 sec) and
((1000 * 1 ns) = 1 us) and
((1000 * 1 us) = 1 ms) and
((1000 * 1 ms) = 1 sec) )
report "***PASSED TEST: c07s02b06x00p32n01i02289"
severity NOTE;
assert ( ((1 ns * 1000) = 1 us) and
((1 us * 1000) = 1 ms) and
((1 ms * 1000) = 1 sec) and
((1000 * 1 ns) = 1 us) and
((1000 * 1 us) = 1 ms) and
((1000 * 1 ms) = 1 sec) )
report "***FAILED TEST: c07s02b06x00p32n01i02289 - Multiplication of a predefined physical type by an integer test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02289arch;
| gpl-2.0 | a2b4ac197f124512dd8d2baafe7c5ce3 | 0.584079 | 3.647635 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd | 4 | 1,476 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_05a is
end entity inline_05a;
architecture test of inline_05a is
signal start_n, reset, time_out : std_ulogic;
terminal interval_rc : electrical;
begin
-- code from book (in text)
interval_timer : entity work.timer(behavioral)
generic map ( threshold => 2.5,
clamp_on_resistance => 0.01,
clamp_off_resistance => 10.0E+6 )
port map ( trigger_n => start_n, reset => reset, q => time_out,
rc_ext => interval_rc );
-- end code from book
end architecture test;
| gpl-2.0 | 865183ae1a904a0209490672c8f98826 | 0.688347 | 3.967742 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug040/shl_211.vhd | 2 | 1,107 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity shl_211 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end shl_211;
architecture augh of shl_211 is
signal tmp_padding : std_logic;
signal tmp_result : std_logic_vector(32 downto 0);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Temporary signals
tmp_padding <= padding;
tmp_result <= std_logic_vector(shift_left( unsigned(input & padding), to_integer(shift) ));
-- The output
output <= tmp_result(32 downto 1);
end architecture;
| gpl-2.0 | 1e27b7ce919bec93dcf6bea446e3449b | 0.704607 | 3.083565 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_sfifo_autord.vhd | 7 | 20,294 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
| gpl-3.0 | 4a60c4eb1df96fa1ec5f429f23876857 | 0.426136 | 4.959433 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue646/repro4.vhdl | 1 | 622 | entity repro4 is
end entity;
architecture tb of repro4 is
type channel is record
data : bit_vector;
ack : bit;
end record;
type my_bus is record
rd : channel;
wr : channel;
end record;
function init_channel (width : natural) return channel is
begin
return (data => (width - 1 downto 0 => '0'),
ack => '0');
end init_channel;
function init_bus (width : natural) return my_bus is
begin
return (rd => init_channel (width),
wr => init_channel (width));
end init_bus;
constant b : my_bus := init_bus (12);
begin
assert b.rd.data(2) = '0';
end tb;
| gpl-2.0 | dc406e7d35cec5e07863ef7a4c7c5905 | 0.604502 | 3.494382 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd | 4 | 1,537 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity quad_opamp is
port ( terminal plus_in, minus_in, output : electrical_vector(1 to 4) );
end entity quad_opamp;
----------------------------------------------------------------
architecture slew_limited of quad_opamp is
constant gain : real := 50.0;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : real_vector(1 to 4);
begin
v_amplified(1) == gain * v_in(1);
v_amplified(2) == gain * v_in(2);
v_amplified(3) == gain * v_in(3);
v_amplified(4) == gain * v_in(4);
real_vector(v_out) == v_amplified'slew(1.0e6,-1.0e6);
end architecture slew_limited;
| gpl-2.0 | 0c3a51b594e09d3509a77d86b6570752 | 0.668835 | 3.767157 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd | 4 | 1,404 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
entity lead_lag is
generic ( k : real := 400.0; -- gain multiplier
f1 : real := 5.0; -- break frequency (zero)
f2 : real := 2000.0); -- break frequency (pole)
port ( quantity input : in real;
quantity output : out real);
end entity lead_lag;
----------------------------------------------------------------
architecture simple of lead_lag is
constant num : real_vector := (f1 * math_2_pi, 1.0);
constant den : real_vector := (f2 * math_2_pi, 1.0);
begin
output == k * input'ltf(num, den);
end architecture simple;
| gpl-2.0 | 257b4779327295fdea5792e9301c6917 | 0.655271 | 3.932773 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_04.vhd | 4 | 2,140 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- not in book
use work.serial_interface_defs.all;
entity microcontroller is
end entity microcontroller;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
architecture structure of microcontroller is
use work.serial_interface_defs.serial_interface;
-- . . . -- declarations of other components, signals, etc
-- not in book
signal buffered_phi1, buffered_phi2, serial_a_select : std_logic;
signal internal_addr : std_logic_vector(1 downto 0);
signal internal_data_bus : data_vector;
signal serial_a_int_req, rx_data_a, tx_data_a : std_logic;
-- end not in book
begin
serial_a : component serial_interface
port map ( clock_phi1 => buffered_phi1,
clock_phi2 => buffered_phi2,
serial_select => serial_a_select,
reg_address => internal_addr(1 downto 0),
data => internal_data_bus,
interrupt_request => serial_a_int_req,
rx_serial_data => rx_data_a,
tx_serial_data => tx_data_a );
-- . . . -- other component instances
end architecture structure;
| gpl-2.0 | 227bf94a7b01777791b0fc38eb8ab5cf | 0.630841 | 3.905109 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd | 4 | 4,029 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity stimulus_interpreter is
end entity stimulus_interpreter;
architecture test of stimulus_interpreter is
quantity temperature : real;
signal temp_sig, setting : real;
signal enable, heater_fail : bit;
begin
-- code from book
stimulus_interpreter : process is
use std.textio.all;
file control : text open read_mode is "control";
variable command : line;
variable read_ok : boolean;
variable next_time : time;
variable whitespace : character;
variable signal_id : string(1 to 4);
variable temp_value, set_value : real;
variable on_value, fail_value : bit;
begin
command_loop : while not endfile(control) loop
readline ( control, command );
-- read next stimulus time, and suspend until then
read ( command, next_time, read_ok );
if not read_ok then
report "error reading time from line: " & command.all
severity warning;
next command_loop;
end if;
wait for next_time - now;
-- skip whitespace
while command'length > 0
and ( command(command'left) = ' ' -- ordinary space
or command(command'left) = ' ' -- non-breaking space
or command(command'left) = HT ) loop
read ( command, whitespace );
end loop;
-- read signal identifier string
read ( command, signal_id, read_ok );
if not read_ok then
report "error reading signal id from line: " & command.all
severity warning;
next command_loop;
end if;
-- dispatch based on signal id
case signal_id is
when "temp" =>
read ( command, temp_value, read_ok );
if not read_ok then
report "error reading temperature value from line: "
& command.all
severity warning;
next command_loop;
end if;
temp_sig <= temp_value;
when "set " =>
-- . . . -- similar to "temp"
-- not in book
read ( command, set_value, read_ok );
if not read_ok then
report "error reading setting value from line: "
& command.all
severity warning;
next command_loop;
end if;
setting <= set_value;
-- end not in book
when "on " =>
read ( command, on_value, read_ok );
if not read_ok then
report "error reading on value from line: "
& command.all
severity warning;
next command_loop;
end if;
enable <= on_value;
when "fail" =>
-- . . . -- similar to "on "
-- not in book
read ( command, fail_value, read_ok );
if not read_ok then
report "error reading fail value from line: "
& command.all
severity warning;
next command_loop;
end if;
heater_fail <= fail_value;
-- end not in book
when others =>
report "invalid signal id in line: " & signal_id
severity warning;
next command_loop;
end case;
end loop command_loop;
wait;
end process stimulus_interpreter;
-- end code from book
-- code from book (in text)
temperature == temp_sig'ramp;
-- end code from book (in text)
end architecture test;
| gpl-2.0 | 351e8420aaf16db32fd239decd4bb8f0 | 0.613552 | 4.192508 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/asgn06.vhdl | 1 | 534 | library ieee;
use ieee.std_logic_1164.all;
entity asgn06 is
port (clk : std_logic;
s0 : std_logic;
r : out std_logic_vector (65 downto 0));
end asgn06;
architecture behav of asgn06 is
begin
process (clk) is
begin
if rising_edge(clk) then
if s0 = '1' then
r (0) <= '0';
r (8 downto 5) <= x"9";
r (65) <= '0';
else
r (0) <= '1';
r (64 downto 1) <= x"ffff_eeee_dddd_cccc";
r (65) <= '1';
end if;
end if;
end process;
end behav;
| gpl-2.0 | cd29c99df5a4a36d08fa5fa4e66dad90 | 0.503745 | 3 | false | false | false | false |
tgingold/ghdl | testsuite/synth/mem01/tb_sram01.vhdl | 1 | 831 | entity tb_sram01 is
end tb_sram01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_sram01 is
signal addr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal wen : std_logic;
signal clk : std_logic;
begin
dut: entity work.sram01
port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat,
wen_i => wen);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
addr <= "0000";
wdat <= x"01";
wen <= '1';
pulse;
addr <= "0001";
wdat <= x"02";
pulse;
addr <= "0000";
wen <= '0';
pulse;
assert rdat = x"01" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | e3004496007a23082d3a72f5a02fbb7d | 0.566787 | 3.233463 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug035/physical.vhdl | 6 | 32,559 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- NAMING CONVENTION:
-- t - time
-- p - period
-- d - delay
-- f - frequency
-- br - baud rate
-- vec - vector
--
-- ATTENTION:
-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
--
-- It was successfully tested with:
-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
-- - Quartus II 13.1
-- - QuestaSim 10.0d
-- - GHDL 0.31
--
-- Tool chains with known issues:
-- - Xilinx Vivado Synthesis 2014.4
--
-- Untested tool chains
-- - Xilinx Vivado Simulator (xSim) 2014.4
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
-- THz = 1000 GHz;
end units;
type BAUD is range 0 to INTEGER'high units
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
GBd = 1000 MBd;
end units;
type MEMORY is range 0 to INTEGER'high units
Byte;
KiB = 1024 Byte;
MiB = 1024 KiB;
GiB = 1024 MiB;
-- TiB = 1024 GiB;
end units;
--
type T_TIMEVEC is array(NATURAL range <>) of TIME;
type T_FREQVEC is array(NATURAL range <>) of FREQ;
type T_BAUDVEC is array(NATURAL range <>) of BAUD;
type T_MEMVEC is array(NATURAL range <>) of MEMORY;
-- TODO
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
-- conversion functions
function to_time(f : FREQ) return TIME;
function to_freq(p : TIME) return FREQ;
function to_freq(br : BAUD) return FREQ;
function to_baud(str : STRING) return BAUD;
-- if-then-else
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
-- min/ max for 2 arguments
function min(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
function min(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
function max(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
function max(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
-- min/max/sum as vector aggregation
function min(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
function min(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
function min(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
function min(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
function max(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
function max(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
function max(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
function max(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
-- QUESTION: some sum functions are not meaningful -> orthogonal function/type system
function sum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
function sum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
function sum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
function sum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
-- convert standard types (NATURAL, REAL) to time (TIME)
function fs2Time(t_fs : NATURAL) return TIME;
function ps2Time(t_ps : NATURAL) return TIME;
function ns2Time(t_ns : NATURAL) return TIME;
function us2Time(t_us : NATURAL) return TIME;
function ms2Time(t_ms : NATURAL) return TIME;
function sec2Time(t_sec : NATURAL) return TIME;
function fs2Time(t_fs : REAL) return TIME;
function ps2Time(t_ps : REAL) return TIME;
function ns2Time(t_ns : REAL) return TIME;
function us2Time(t_us : REAL) return TIME;
function ms2Time(t_ms : REAL) return TIME;
function sec2Time(t_sec : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to period (TIME)
function Hz2Time(f_Hz : NATURAL) return TIME;
function kHz2Time(f_kHz : NATURAL) return TIME;
function MHz2Time(f_MHz : NATURAL) return TIME;
function GHz2Time(f_GHz : NATURAL) return TIME;
-- function THz2Time(f_THz : NATURAL) return TIME;
function Hz2Time(f_Hz : REAL) return TIME;
function kHz2Time(f_kHz : REAL) return TIME;
function MHz2Time(f_MHz : REAL) return TIME;
function GHz2Time(f_GHz : REAL) return TIME;
-- function THz2Time(f_THz : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
function Hz2Freq(f_Hz : NATURAL) return FREQ;
function kHz2Freq(f_kHz : NATURAL) return FREQ;
function MHz2Freq(f_MHz : NATURAL) return FREQ;
function GHz2Freq(f_GHz : NATURAL) return FREQ;
-- function THz2Freq(f_THz : NATURAL) return FREQ;
function Hz2Freq(f_Hz : REAL) return FREQ;
function kHz2Freq(f_kHz : REAL) return FREQ;
function MHz2Freq(f_MHz : REAL) return FREQ;
function GHz2Freq(f_GHz : REAL) return FREQ;
-- function THz2Freq(f_THz : REAL) return FREQ;
-- convert physical types to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function to_real(br : BAUD; scale : BAUD) return REAL;
function to_real(mem : MEMORY; scale : MEMORY) return REAL;
-- convert physical types to standard type (INTEGER)
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING;
function to_string(f : FREQ; precision : NATURAL) return STRING;
function to_string(br : BAUD; precision : NATURAL) return STRING;
function to_string(mem : MEMORY; precision : NATURAL) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
-- ===========================================================================
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
begin
if (a < 1 us) then
return real(a / MTRIS) / real(b / MTRIS);
elsif (a < 1 ms) then
return real(a / (1000 * MTRIS)) / real(b / MTRIS) * 1000.0;
elsif (a < 1 sec) then
return real(a / (1000000 * MTRIS)) / real(b / MTRIS) * 1000000.0;
else
return real(a / (1000000000 * MTRIS)) / real(b / MTRIS) * 1000000000.0;
end if;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
function div(a : BAUD; b : BAUD) return REAL is
begin
return real(a / 1 Bd) / real(b / 1 Bd);
end function;
function div(a : MEMORY; b : MEMORY) return REAL is
begin
return real(a / 1 Byte) / real(b / 1 Byte);
end function;
-- conversion functions
-- ===========================================================================
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
if (f < 1 kHz) then res := div(1 Hz, f) * 1 sec;
elsif (f < 1 MHz) then res := div(1 kHz, f) * 1 ms;
elsif (f < 1 GHz) then res := div(1 MHz, f) * 1 us;
-- elsif (f < 1 THz) then res := div(1 GHz, f) * 1 ns;
else res := div(1 GHz, f) * 1 ns;
-- else res := div(1 THz, f) * 1 ps;
end if;
if (POC_VERBOSE = TRUE) then
report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(p : TIME) return FREQ is
variable res : FREQ;
begin
-- if (p < 1 ps) then res := div(1 fs, p) * 1 THz;
if (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
-- elsif (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
elsif (p < 1 us) then res := div(1 ns, p) * 1 MHz;
elsif (p < 1 ms) then res := div(1 us, p) * 1 kHz;
elsif (p < 1 sec) then res := div(1 ms, p) * 1 Hz;
else report "to_freq: input period exceeds output frequency scale." severity failure;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(br : BAUD) return FREQ is
variable res : FREQ;
begin
if (br < 1 kBd) then res := div(br, 1 Bd) * 1 Hz;
elsif (br < 1 MBd) then res := div(br, 1 kBd) * 1 kHz;
elsif (br < 1 GBd) then res := div(br, 1 MBd) * 1 MHz;
else res := div(br, 1 GBd) * 1 GHz;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_baud(str : STRING) return BAUD is
variable pos : INTEGER;
variable int : NATURAL;
variable base : POSITIVE;
variable frac : NATURAL;
variable digits : NATURAL;
begin
pos := str'low;
int := 0;
frac := 0;
digits := 0;
-- read integer part
for i in pos to str'high loop
if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
elsif (str(i) = '.') then pos := -i; exit;
elsif (str(i) = ' ') then pos := i; exit;
else pos := 0; exit;
end if;
end loop;
-- read fractional part
if ((pos < 0) and (-pos < str'high)) then
for i in -pos+1 to str'high loop
if ((frac = 0) and (str(i) = '0')) then next;
elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
else pos := 0; exit;
end if;
end loop;
end if;
-- abort if format is unknown
if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
-- parse unit
pos := pos + 1;
if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
return int * 1 Bd;
elsif (pos + 2 = str'high) then
if (str(pos to pos + 2) = "kBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
end if;
elsif (str(pos to pos + 2) = "MBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
end if;
elsif (str(pos to pos + 2) = "GBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
end if;
else
report "to_baud: Unknown unit." severity FAILURE;
end if;
else
report "to_baud: Unknown format" severity FAILURE;
end if;
end function;
-- if-then-else
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- min/ max for 2 arguments
-- ===========================================================================
-- Calculates: min(arg1, arg2) for times
function min(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for memory
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for times
function max(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for memory
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- min/max/sum as vector aggregation
-- ===========================================================================
-- Calculates: min(vec) for a time vector
function min(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a frequency vector
function min(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a baud vector
function min(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a memory vector
function min(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a time vector
function max(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a frequency vector
function max(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a baud vector
function max(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a memory vector
function max(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: sum(vec) for a time vector
function sum(vec : T_TIMEVEC) return TIME is
variable res : TIME := 0 fs;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a frequency vector
function sum(vec : T_FREQVEC) return FREQ is
variable res : FREQ := 0 Hz;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a baud vector
function sum(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := 0 Bd;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a memory vector
function sum(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := 0 Byte;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- convert standard types (NATURAL, REAL) to time (TIME)
-- ===========================================================================
function fs2Time(t_fs : NATURAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : NATURAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : NATURAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : NATURAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : NATURAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : NATURAL) return TIME is
begin
return t_sec * 1 sec;
end function;
function fs2Time(t_fs : REAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : REAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : REAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : REAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : REAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : REAL) return TIME is
begin
return t_sec * 1 sec;
end function;
-- convert standard types (NATURAL, REAL) to period (TIME)
-- ===========================================================================
function Hz2Time(f_Hz : NATURAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : NATURAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : NATURAL) return TIME
is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : NATURAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : NATURAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
function Hz2Time(f_Hz : REAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : REAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : REAL) return TIME is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : REAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : REAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
-- ===========================================================================
function Hz2Freq(f_Hz : NATURAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : NATURAL) return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : NATURAL) return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : NATURAL) return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : NATURAL) return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
function Hz2Freq(f_Hz : REAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : REAL )return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : REAL )return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : REAL )return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : REAL )return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
-- convert physical types to standard type (REAL)
-- ===========================================================================
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1 fs) then return div(t, 1 fs);
elsif (scale = 1 ps) then return div(t, 1 ps);
elsif (scale = 1 ns) then return div(t, 1 ns);
elsif (scale = 1 us) then return div(t, 1 us);
elsif (scale = 1 ms) then return div(t, 1 ms);
elsif (scale = 1 sec) then return div(t, 1 sec);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1 Hz) then return div(f, 1 Hz);
elsif (scale = 1 kHz) then return div(f, 1 kHz);
elsif (scale = 1 MHz) then return div(f, 1 MHz);
elsif (scale = 1 GHz) then return div(f, 1 GHz);
-- elsif (scale = 1 THz) then return div(f, 1 THz);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(br : BAUD; scale : BAUD) return REAL is
begin
if (scale = 1 Bd) then return div(br, 1 Bd);
elsif (scale = 1 kBd) then return div(br, 1 kBd);
elsif (scale = 1 MBd) then return div(br, 1 MBd);
elsif (scale = 1 GBd) then return div(br, 1 GBd);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(mem : MEMORY; scale : MEMORY) return REAL is
begin
if (scale = 1 Byte) then return div(mem, 1 Byte);
elsif (scale = 1 KiB) then return div(mem, 1 KiB);
elsif (scale = 1 MiB) then return div(mem, 1 MiB);
elsif (scale = 1 GiB) then return div(mem, 1 GiB);
-- elsif (scale = 1 TiB) then return div(mem, 1 TiB);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
-- convert physical types to standard type (INTEGER)
-- ===========================================================================
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(t, scale)));
when ROUND_DOWN => return integer(floor(to_real(t, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(f, scale)));
when ROUND_DOWN => return integer(floor(to_real(f, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(br, scale)));
when ROUND_DOWN => return integer(floor(to_real(br, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(mem, scale)));
when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
variable res_time : TIME;
variable res_dev : REAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(ceil(res_real));
when ROUND_DOWN => res_nat := natural(floor(res_real));
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
res_time := CyclesToDelay(res_nat, Clock_Period);
res_dev := (1.0 - div(res_time, Timing)) * 100.0;
if (POC_VERBOSE = TRUE) then
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing, 3) & CR &
" Clock_Period: " & to_string(Clock_Period, 3) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
end if;
-- if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
-- report "TimingToCycles (timing deviation report): " & CR &
-- " timing to achieve: " & to_string(Timing) & CR &
-- " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
-- " resulting timing: " & to_string(res_time) & CR &
-- " deviation: " & to_string(Timing - res_time) & " (" & str_format(res_dev, 2) & "%)"
-- severity note;
-- end if;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
begin
return Clock_Period * Cycles;
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
begin
return CyclesToDelay(Cycles, to_time(Clock_Frequency));
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (t < 1 ps) then
unit(1 to 2) := "fs";
value := to_real(t, 1 fs);
elsif (t < 1 ns) then
unit(1 to 2) := "ps";
value := to_real(t, 1 ps);
elsif (t < 1 us) then
unit(1 to 2) := "ns";
value := to_real(t, 1 ns);
elsif (t < 1 ms) then
unit(1 to 2) := "us";
value := to_real(t, 1 us);
elsif (t < 1 sec) then
unit(1 to 2) := "ms";
value := to_real(t, 1 ms);
else
unit := "sec";
value := to_real(t, 1 sec);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(f : FREQ; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (f < 1 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1 Hz);
elsif (f < 1 MHz) then
unit := "kHz";
value := to_real(f, 1 kHz);
elsif (f < 1 GHz) then
unit := "MHz";
value := to_real(f, 1 MHz);
else --if (f < 1 THz) then
unit := "GHz";
value := to_real(f, 1 GHz);
-- else
-- unit := "THz";
-- value := to_real(f, 1 THz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(br : BAUD; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (br < 1 kBd) then
unit(1 to 2) := "Bd";
value := to_real(br, 1 Bd);
elsif (br < 1 MBd) then
unit := "kBd";
value := to_real(br, 1 kBd);
elsif (br < 1 GBd) then
unit := "MBd";
value := to_real(br, 1 MBd);
else
unit := "GBd";
value := to_real(br, 1 GBd);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(mem : MEMORY; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (mem < 1 KiB) then
unit(1) := 'B';
value := to_real(mem, 1 Byte);
elsif (mem < 1 MiB) then
unit := "KiB";
value := to_real(mem, 1 KiB);
elsif (mem < 1 GiB) then
unit := "MiB";
value := to_real(mem, 1 MiB);
else --if (mem < 1 TiB) then
unit := "GiB";
value := to_real(mem, 1 GiB);
-- else
-- unit := "TiB";
-- value := to_real(mem, 1 TiB);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
| gpl-2.0 | 7ce67465762e3e4330f2702c2c4a0164 | 0.619921 | 3.011655 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue349/ResolutionPkg.vhd | 1 | 16,310 | --
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Package Defines
-- resolved resolution functions for integer, real, and time
-- types resolved_integer, resolved_real, resolved_time
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 09/2006: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009: 1.0 VHDL-2008 STANDARD VERSION
-- 05/2015 2015.05 Added Alerts
-- -- Replaced Alerts with asserts as alerts are illegal in pure functions
-- 11/2016 2016.11 Removed Asserts as they are not working as intended.
-- See ResolutionPkg_debug as it uses Alerts to correctly detect errors
--
--
-- Copyright (c) 2005 - 2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file may be modified and distributed under
-- the terms of the ARTISTIC License as published by
-- The Perl Foundation; either version 2.0 of the License,
-- or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
--library osvvm ;
--use osvvm.AlertLogPkg.all ;
package ResolutionPkg is
constant MULTIPLE_DRIVER_SEVERITY : severity_level := ERROR ;
--
-- Note that not all simulators support resolution functions of the form:
-- subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
--
-- Hence, types of the form are offered as a temporary workaround until they do:
-- std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
--
-- resolved_max
-- return maximum value.
-- No initializations required on ports, default of type'left is ok
function resolved_max ( s : std_ulogic_vector) return std_ulogic ;
subtype std_logic_max is resolved_max std_ulogic ;
subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
type std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype unsigned_max is (resolved_max) unresolved_unsigned ;
type unsigned_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype signed_max is (resolved_max) unresolved_signed ;
type signed_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
function resolved_max ( s : bit_vector) return bit ;
subtype bit_max is resolved_max bit ;
subtype bit_vector_max is (resolved_max) bit_vector ;
type bit_vector_max_c is array (natural range <>) of bit_max ; -- for non VHDL-2008
function resolved_max ( s : integer_vector ) return integer ;
subtype integer_max is resolved_max integer ;
subtype integer_vector_max is (resolved_max) integer_vector ;
type integer_vector_max_c is array (natural range <>) of integer_max ; -- for non VHDL-2008
function resolved_max ( s : time_vector ) return time ;
subtype time_max is resolved_max time ;
subtype time_vector_max is (resolved_max) time_vector ;
type time_vector_max_c is array (natural range <>) of time_max ; -- for non VHDL-2008
function resolved_max ( s : real_vector ) return real ;
subtype real_max is resolved_max real ;
subtype real_vector_max is (resolved_max) real_vector ;
type real_vector_max_c is array (natural range <>) of real_max ; -- for non VHDL-2008
function resolved_max ( s : string) return character ;
subtype character_max is resolved_max character ;
subtype string_max is (resolved_max) string ;
type string_max_c is array (positive range <>) of character_max ; -- for non VHDL-2008
function resolved_max ( s : boolean_vector) return boolean ;
subtype boolean_max is resolved_max boolean ;
subtype boolean_vector_max is (resolved_max) boolean_vector ;
type boolean_vector_max_c is array (natural range <>) of boolean_max ; -- for non VHDL-2008
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
function resolved_sum ( s : integer_vector ) return integer ;
subtype integer_sum is resolved_sum integer ;
subtype integer_vector_sum is (resolved_sum) integer_vector ;
type integer_vector_sum_c is array (natural range <>) of integer_sum ; -- for non VHDL-2008
function resolved_sum ( s : time_vector ) return time ;
subtype time_sum is resolved_sum time ;
subtype time_vector_sum is (resolved_sum) time_vector ;
type time_vector_sum_c is array (natural range <>) of time_sum ; -- for non VHDL-2008
function resolved_sum ( s : real_vector ) return real ;
subtype real_sum is resolved_sum real ;
subtype real_vector_sum is (resolved_sum) real_vector ;
type real_vector_sum_c is array (natural range <>) of real_sum ; -- for non VHDL-2008
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
function resolved_weak (s : std_ulogic_vector) return std_ulogic ; -- no init, type'left
subtype std_logic_weak is resolved_weak std_ulogic ;
subtype std_logic_vector_weak is (resolved_weak) std_ulogic_vector ;
-- legacy stuff
-- requires ports to be initialized to 0 in the appropriate type.
function resolved ( s : integer_vector ) return integer ;
subtype resolved_integer is resolved integer ;
function resolved ( s : time_vector ) return time ;
subtype resolved_time is resolved time ;
function resolved ( s : real_vector ) return real ;
subtype resolved_real is resolved real ;
function resolved (s : string) return character ; -- same as resolved_max
subtype resolved_character is resolved character ;
-- subtype resolved_string is (resolved) string ; -- subtype will replace type later
type resolved_string is array (positive range <>) of resolved_character; -- will change to subtype -- assert but no init
function resolved ( s : boolean_vector) return boolean ; --same as resolved_max
subtype resolved_boolean is resolved boolean ;
end package ResolutionPkg ;
package body ResolutionPkg is
-- resolved_max
-- return maximum value. Assert FAILURE if more than 1 /= type'left
-- No initializations required on ports, default of type'left is ok
-- Optimized version is just the following:
-- ------------------------------------------------------------
-- function resolved_max ( s : <array_type> ) return <element_type> is
-- ------------------------------------------------------------
-- begin
-- return maximum(s) ;
-- end function resolved_max ;
------------------------------------------------------------
function resolved_max (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : bit_vector ) return bit is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : integer_vector ) return integer is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : time_vector ) return time is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : real_vector ) return real is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : string ) return character is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : boolean_vector) return boolean is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
-- resolved_sum - appropriate for numeric types
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
------------------------------------------------------------
function resolved_sum ( s : integer_vector ) return integer is
------------------------------------------------------------
variable result : integer := 0 ;
begin
for i in s'RANGE loop
if s(i) /= integer'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : time_vector ) return time is
------------------------------------------------------------
variable result : time := 0 sec ;
begin
for i in s'RANGE loop
if s(i) /= time'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : real_vector ) return real is
------------------------------------------------------------
variable result : real := 0.0 ;
begin
for i in s'RANGE loop
if s(i) /= real'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant weak_resolution_table : stdlogic_table := (
-- Resolution order: Z < U < W < X < - < L < H < 0 < 1
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'X', '0', '1', 'U', 'W', 'L', 'H', '-'), -- | U |
('X', 'X', '0', '1', 'X', 'X', 'L', 'H', '-'), -- | X |
('0', '0', '0', '1', '0', '0', '0', '0', '0'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), -- | Z |
('W', 'X', '0', '1', 'W', 'W', 'L', 'H', '-'), -- | W |
('L', 'L', '0', '1', 'L', 'L', 'L', 'H', 'L'), -- | L |
('H', 'H', '0', '1', 'H', 'H', 'W', 'H', 'H'), -- | H |
('-', '-', '0', '1', '-', '-', 'L', 'H', '-') -- | - |
);
------------------------------------------------------------
function resolved_weak (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
variable result : std_ulogic := 'Z' ;
begin
for i in s'RANGE loop
result := weak_resolution_table(result, s(i)) ;
end loop ;
return result ;
end function resolved_weak ;
-- legacy stuff.
-- requires ports to be initialized to 0 in the appropriate type.
------------------------------------------------------------
function resolved ( s : integer_vector ) return integer is
-- requires interface to be initialized to 0
------------------------------------------------------------
variable result : integer := 0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0 then
failed := failed or (result /= 0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on integer" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on integer") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : time_vector ) return time is
-- requires interface to be initialized to 0 ns
------------------------------------------------------------
variable result : time := 0 ns ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) > 0 ns then
failed := failed or (result /= 0 ns) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on time" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on time") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : real_vector ) return real is
-- requires interface to be initialized to 0.0
------------------------------------------------------------
variable result : real := 0.0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0.0 then
failed := failed or (result /= 0.0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on real" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on real") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved (s : string) return character is
-- same as resolved_max
------------------------------------------------------------
variable result : character := NUL ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= NUL then
failed := failed or (result /= NUL) ;
result := maximum(result, s(i)) ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on character" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on character") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : boolean_vector) return boolean is
-- same as resolved_max
------------------------------------------------------------
variable result : boolean := FALSE ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) then
failed := failed or result ;
result := TRUE ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on boolean" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on boolean") ;
return result ;
end function resolved ;
end package body ResolutionPkg ;
| gpl-2.0 | d7f31852e02f1785b4e78c68da820847 | 0.541324 | 4.415268 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1269/ent.vhdl | 1 | 417 | library ieee;
context ieee.ieee_std_context;
entity ent is
end ent;
architecture arch of ent is
begin
process
variable color: bit_vector(2 downto 0);
variable lcol: std_logic_vector(31 downto 0);
begin
lcol := (
23 downto 16 => color(2),
15 downto 8 => color(1),
7 downto 0 => color(0),
others=> '0'
);
wait;
end process;
end architecture;
| gpl-2.0 | 1ff6e1ea0b8c59c64551e88ddf277f18 | 0.582734 | 3.626087 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff02/tb_dff05.vhdl | 1 | 838 | entity tb_dff05 is
end tb_dff05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff05 is
signal clk : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff05
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= b"1_00000_00";
pulse;
assert dout (0) = '0' severity failure;
din <= b"0_00001_00";
pulse;
assert dout (2) = '1' severity failure;
din <= b"0_00000_01";
pulse;
assert dout (2) = '0' severity failure;
din <= b"1_00000_01";
pulse;
assert dout (0) = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 7173ab3795ff0f1946402d594cb5cd17 | 0.570406 | 3.186312 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug15702/example.vhd | 3 | 1,573 | library ieee;
use ieee.std_logic_1164.all;
-- COMPONENT
entity a is
-- N_BITS_DATA is nowhere initialized. This problem should be catched during
-- elaboration but it isn't !
-- During simulation I found that the value of N_BITS_DATA is -2147483648 and
-- that the value of N_BITS_DATA-1 is 2147483647 !!!!
generic (N_BITS_DATA : integer);
end entity;
architecture arch_a of a is
--~ -- Here data_s will have 4_194_305 elements and this will make ghdl
--~ -- take about 650 MB of memory. According to that, each element take about 150 B
--~ signal data_s : std_logic_vector((N_BITS_DATA-1)/512 downto 0);
-- This line make ghdl eat all the free memory because it is trying to make a
-- vector of 2**31 elements !!!! And there isn't enough memory because we need
-- about 2**31 * 150 B = ~ 300 GB !!!!
signal data_s : std_logic_vector(N_BITS_DATA-1 downto 0);
--~ -- Strangely this line doesn't make the simulation failed because N_BITS_DATA
--~ -- is negativ, but it doesn't increase the use of memory either.
--~ signal data_s : std_logic_vector(N_BITS_DATA downto 0);
begin
process begin
-- N_BITS_DATA = -2147483648 = -2**31
report integer'image(N_BITS_DATA);
--
-- N_BITS_DATA-1 = 2147483647 = 2**31 - 1
report integer'image(N_BITS_DATA-1);
--
-- (N_BITS_DATA-1)/512 = 4_194_304 = 2**22
report integer'image((N_BITS_DATA-1)/512);
--
end process;
end;
--
-- TESTBENCH
entity tb is end entity;
architecture arch_tb of tb is
begin
X1: entity work.a;
end;
--
| gpl-2.0 | 406e6a9b6637a998bf9851bac7252d6d | 0.649714 | 3.427015 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/tb_asgn03.vhdl | 1 | 696 | entity tb_asgn03 is
end tb_asgn03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn03 is
signal s0 : std_logic;
signal s1 : std_logic;
signal r : std_logic_vector (2 downto 0);
begin
dut: entity work.asgn03
port map (s0 => s0, s1 => s1, r => r);
process
begin
s0 <= '0';
s1 <= '0';
wait for 1 ns;
assert r = "000" severity failure;
s0 <= '0';
s1 <= '1';
wait for 1 ns;
assert r = "000" severity failure;
s0 <= '1';
s1 <= '0';
wait for 1 ns;
assert r = "010" severity failure;
s0 <= '1';
s1 <= '1';
wait for 1 ns;
assert r = "011" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 5561ddbc9347850df6dd2b81c3933c6a | 0.558908 | 2.912134 | false | false | false | false |
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