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tgingold/ghdl | testsuite/synth/dff01/tb_dff04.vhdl | 1 | 776 | entity tb_dff04 is
end tb_dff04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff04 is
signal clk : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff04
port map (
r => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= x"00";
pulse;
assert dout = x"01" severity failure;
din <= x"ab";
pulse;
assert dout = x"ac" severity failure;
pulse;
assert dout = x"ac" severity failure;
din <= x"12";
pulse;
assert dout = x"13" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | e6210b725fc70c739034f202a1e71aa4 | 0.582474 | 3.344828 | false | false | false | false |
snow4life/PipelinedDLX | alu/logic_generic.vhd | 1 | 916 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
entity LOGIC_GENERIC is
generic(N: integer);
port( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
S: in std_logic_vector(3 downto 0);
LOGIC_OUT: out std_logic_vector(N-1 downto 0)
);
end entity LOGIC_GENERIC;
architecture BEHAVIORAL of LOGIC_GENERIC is
signal L0: std_logic_vector(N-1 downto 0);
signal L1: std_logic_vector(N-1 downto 0);
signal L2: std_logic_vector(N-1 downto 0);
signal L3: std_logic_vector(N-1 downto 0);
begin
L0 <= not ( (not A) and (not B) and (N-1 downto 0 => S(0)) );
L1 <= not ( (not A) and (B) and (N-1 downto 0 => S(1)) );
L2 <= not ( (A) and (not B) and (N-1 downto 0 => S(2)) );
L3 <= not ( (A) and (B) and (N-1 downto 0 => S(3)) );
LOGIC_OUT <= not (L0 and L1 and L2 and L3);
end architecture BEHAVIORAL;
| lgpl-2.1 | f53962604d661a33d1c364c3eb93cbe4 | 0.645197 | 2.482385 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_03.vhd | 4 | 1,463 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity counter is
port ( clk : in bit; count : out natural );
end entity counter;
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
wait until clk = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
end process incrementer;
end architecture behavior;
| gpl-2.0 | 91061dcbc20a35946b8f277a6e374bd8 | 0.620643 | 4.265306 | false | false | false | false |
nickg/nvc | test/sem/wait.vhd | 1 | 1,495 | entity a is
end entity;
architecture b of a is
signal x, y : bit;
signal z : bit_vector(3 downto 0);
alias xa is x;
alias za : bit is z(2);
begin
-- wait for
process is
begin
wait for ps;
wait for 5 ns;
wait for 2 * 4 hr;
wait for 523; -- Not TIME type
end process;
-- wait on
process is
variable v : bit;
begin
wait on x;
wait on x, y;
wait on v; -- Not signal
end process;
-- process sensitivity
process (x, y) is
begin
x <= y;
end process;
process (x, a) is -- Bad name a
begin
x <= '1';
end process;
process (x) is
begin
x <= y;
wait for 1 ns; -- Not allowed wait
end process;
-- wait until
process is
begin
wait until true;
wait until x = '1';
wait until x; -- Not boolean
wait until y = x for 1 ns;
wait until y = x for x; -- Not time
end process;
-- Alias in sensitivity list
process (xa, za) is
begin
end process;
-- Wait on scalar sub-elements and slices
process is
variable i : integer;
begin
wait on z(1), za, z(2 downto 1);
wait on z(i); -- Not static
end process;
process (now) is -- Error
begin
end process;
end architecture;
| gpl-3.0 | 359b5c4e0bbd5478b4f05f9b9f443f54 | 0.474247 | 4.152778 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/ghrd_10as066n2_led_pio_inst.vhd | 1 | 1,541 | component ghrd_10as066n2_led_pio is
port (
clk : in std_logic := 'X'; -- clk
in_port : in std_logic_vector(3 downto 0) := (others => 'X'); -- in_port
out_port : out std_logic_vector(3 downto 0); -- out_port
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component ghrd_10as066n2_led_pio;
u0 : component ghrd_10as066n2_led_pio
port map (
clk => CONNECTED_TO_clk, -- clk.clk
in_port => CONNECTED_TO_in_port, -- external_connection.in_port
out_port => CONNECTED_TO_out_port, -- .out_port
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
address => CONNECTED_TO_address, -- s1.address
write_n => CONNECTED_TO_write_n, -- .write_n
writedata => CONNECTED_TO_writedata, -- .writedata
chipselect => CONNECTED_TO_chipselect, -- .chipselect
readdata => CONNECTED_TO_readdata -- .readdata
);
| mit | 5a8b550379f2419655b21879e1012e11 | 0.472421 | 3.510251 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth39/rec2.vhdl | 1 | 1,051 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rec2 is
port (
clk : in std_logic;
sl_in : in std_logic;
slv_in : in std_logic_vector(7 downto 0);
int_in : in integer range 0 to 15;
usig_in : in unsigned(7 downto 0);
sl_out : out std_logic;
slv_out : out std_logic_vector(7 downto 0);
int_out : out integer range 0 to 15;
usig_out : out unsigned(7 downto 0)
);
end rec2;
architecture rtl of rec2 is
type t_record is record
sl : std_logic;
slv : std_logic_vector(7 downto 0);
int : integer range 0 to 15;
usig : unsigned(7 downto 0);
end record t_record;
signal sample_record : t_record;
begin
process(clk)
begin
if rising_edge(clk) then
sample_record.sl <= sl_in;
sample_record.slv <= slv_in;
sample_record.int <= int_in;
sample_record.usig <= usig_in;
end if;
end process;
sl_out <= sample_record.sl;
slv_out <= sample_record.slv;
int_out <= sample_record.int;
usig_out <= sample_record.usig;
end rtl;
| gpl-2.0 | 0655746c8fc894ed441f9db845379aca | 0.628925 | 3.082111 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/register_examples/tb_register_examples.vhd | 1 | 11,576 | -------------------------------------------------------------------------------------
-- FILE NAME : tb_register_examples.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - tb_register_examples
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
--Library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_register_examples is
end tb_register_examples;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_register_examples is
-------------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------------
component generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end component generic_host_emu;
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_10_MHZ : time := 100 ns;
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_368_MHZ : time := 2.7126 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
constant DATA_WIDTH : natural := 8;
constant ADDR_WIDTH : natural := 8;
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
type bus016 is array(natural range <>) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal clk200 : std_logic := '1';
signal clk100 : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal rst_rstin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_clkin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_cmd : std_logic;
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal out_cmd_val : std_logic;
signal out_cmd : std_logic_vector(63 downto 0);
signal host_data_in : std_logic_vector(63 downto 0);
signal host_data_out : std_logic_vector(63 downto 0);
signal host_val_in : std_logic;
signal host_val_out : std_logic;
signal host_stop_out : std_logic;
signal host_stop_in : std_logic;
--stimulus
signal samples16bit : bus016(3 downto 0) := (others=>(others=>'0'));
signal base_cnt : std_logic_vector(15 downto 0);
signal send_data : std_logic_vector(63 downto 0);
signal
signal sim_count : std_logic_vector(31 downto 0) := (others=>'0');
signal we : std_logic;
signal data_rst : std_logic := '1';
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_100_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
clk200 <= not clk200 after CLK_200_MHZ / 2;
clk100 <= not clk100 after CLK_100_MHZ / 2;
rst <= '0' after CLK_125_MHZ * 10;
rstn <= '1' after CLK_125_MHZ * 10;
rst_rstin <= (0=>rst, 1 => rst, 2=> rst, others =>'0');
clk_clkin <= (13 => clk200, 14 => clk100, others=>clk);
-----------------------------------------------------------------------------------
-- Host Interface
-----------------------------------------------------------------------------------
inst0_generic_host: generic_host_emu
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"00000FF",
private_start_addr_gen => x"0000000",
private_stop_addr_gen => x"00000FF"
)
port map (
cmdclk_out_cmdclk => clk_cmd, -- out std_logic;
cmd_in_cmdin => out_cmd , -- in std_logic_vector(63 downto 0);
cmd_in_cmdin_val => out_cmd_val, -- in std_logic;
cmd_out_cmdout => in_cmd, -- out std_logic_vector(63 downto 0);
cmd_out_cmdout_val => in_cmd_val, -- out std_logic;
ifpga_rst_out_ifpga_rst => open, -- out std_logic;
clk_clkin => (others=>'0'),-- in std_logic_vector(31 downto 0);
rst_rstin => (others=>'0'),-- in std_logic_vector(31 downto 0);
sys_clk => clk, -- in std_logic;
sys_reset_n => rstn, -- in std_logic;
in_data_in_stop => host_stop_in, -- out std_logic;
in_data_in_dval => host_val_in, -- in std_logic;
in_data_in_data => host_data_in, -- in std_logic_vector(63 downto 0);
out_data_out_stop => host_stop_out,-- in std_logic;
out_data_out_dval => host_val_out, -- out std_logic;
out_data_out_data => host_data_out -- out std_logic_vector(63 downto 0)
);
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => clk200, -- 1-bit input: Reference clock input
RST => '0' -- 1-bit input: Active high reset input
);
-----------------------------------------------------------------------------------
-- Unit under test
-----------------------------------------------------------------------------------
sip_capture_x4_0 : entity xil_defaultlib.sip_capture_x4
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"0001FFF",
private_start_addr_gen => x"0000100",
private_stop_addr_gen => x"00001FF"
)
port map (
cmdclk_in_cmdclk => clk_cmd,
cmd_in_cmdin => in_cmd,
cmd_in_cmdin_val => in_cmd_val,
cmd_out_cmdout => out_cmd,
cmd_out_cmdout_val => out_cmd_val,
clk_clkin => clk_clkin,
rst_rstin => rst_rstin,
in0_in_stop => open,
in0_in_dval => valid,
in0_in_data => data,
in1_in_stop => open,
in1_in_dval => valid,
in1_in_data => data,
in2_in_stop => open,
in2_in_dval => valid,
in2_in_data => data,
in3_in_stop => open,
in3_in_dval => valid,
in3_in_data => data,
out0_out_stop => '0',
out0_out_dval => open,
out0_out_data => open,
out1_out_stop => '0',
out1_out_dval => open,
out1_out_data => open,
out2_out_stop => '0',
out2_out_dval => open,
out2_out_data => open,
out3_out_stop => '0',
out3_out_dval => open,
out3_out_data => open
);
-----------------------------------------------------------------------------------
-- Stimulus
-----------------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
sim_count <= sim_count + 1;
if sim_count = 0 then -- reset data generation
data_rst <= '1';
we <= '0';
elsif sim_count = 20 then -- enable data generation and enable writing
report "Writing data to memory";
data_rst <= '0';
we <= '1';
elsif sim_count = 100 then -- reset data generation and disable writing
data_rst <= '1';
we <= '0';
elsif sim_count = 102 then -- enable data generation and disable writing
report "Reading data from memory";
data_rst <= '0';
we <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Data generation
-----------------------------------------------------------------------------------
process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
base_cnt <= (others =>'0');
else
base_cnt <= base_cnt + 4;
end if;
end if;
end process;
samples16bit(0) <= base_cnt + 0;
samples16bit(1) <= base_cnt + 1;
samples16bit(2) <= base_cnt + 2;
samples16bit(3) <= base_cnt + 3;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | 0c65ac76ee74aa570464b0061f4a890f | 0.419229 | 4.057483 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug16695/lfsr_updown_tb.vhd | 3 | 2,757 | -------------------------------------------------------
-- Design Name : lfsr
-- File Name : lfsr_updown_tb.vhd
-- Function : Linear feedback shift register
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity lfsr_updown_tb is
end entity;
architecture test of lfsr_updown_tb is
constant WIDTH :integer := 8;
signal clk :std_logic := '0';
signal reset :std_logic := '1';
signal enable :std_logic := '0';
signal up_down :std_logic := '0';
signal count :std_logic_vector (WIDTH-1 downto 0);
signal overflow :std_logic;
component lfsr_updown is
generic (
WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock input
reset :in std_logic; -- Reset input
enable :in std_logic; -- Enable input
up_down :in std_logic; -- Up Down input
count :out std_logic_vector (WIDTH-1 downto 0); -- Count output
overflow :out std_logic -- Overflow output
);
end component;
constant PERIOD :time := 20 ns;
begin
clk <= not clk after PERIOD/2;
reset <= '0' after PERIOD*10;
enable <= '1' after PERIOD*11;
up_down <= '1' after PERIOD*22;
-- Display the time and result
process (reset, enable, up_down, count, overflow)
variable wrbuf :line;
begin
write(wrbuf, string'("Time: " ));
writeline(output, wrbuf);
write(wrbuf, now);
writeline(output, wrbuf);
write(wrbuf, string'(" rst: " ));
writeline(output, wrbuf);
write(wrbuf, reset);
writeline(output, wrbuf);
write(wrbuf, string'(" enable: " ));
writeline(output, wrbuf);
write(wrbuf, enable);
writeline(output, wrbuf);
write(wrbuf, string'(" up_down: " ));
writeline(output, wrbuf);
write(wrbuf, up_down);
writeline(output, wrbuf);
write(wrbuf, string'(" count: " ));
writeline(output, wrbuf);
write(wrbuf, count);
writeline(output, wrbuf);
write(wrbuf, string'(" overflow: "));
writeline(output, wrbuf);
write(wrbuf, overflow);
writeline(output, wrbuf);
end process;
Inst_lfsr_updown : lfsr_updown
port map (
clk => clk,
reset => reset,
enable => enable,
up_down => up_down,
count => count,
overflow => overflow
);
end architecture;
| gpl-2.0 | beee51013d445d7aa9c7b494fd68a0e7 | 0.519042 | 4.072378 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd | 4 | 1,172 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.MVL4.all;
entity tri_state_buffer is
port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic );
end entity tri_state_buffer;
--------------------------------------------------
architecture behavioral of tri_state_buffer is
begin
y <= 'Z' when enable = '0' else
a when enable = '1' and (a = '0' or a = '1') else
'X';
end architecture behavioral;
| gpl-2.0 | 102d957c0a795d21dd68f3adec619625 | 0.682594 | 3.946128 | false | false | false | false |
mistryalok/FPGA | Xilinx/ISE/Basics/Encoder4x2/Encoder4x2.vhd | 1 | 1,160 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:21:13 05/22/2013
-- Design Name:
-- Module Name: Encoder4x2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Encoder4x2 is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR (1 downto 0));
end Encoder4x2;
architecture Behavioral of Encoder4x2 is
begin
process(I)
begin
case i is
when "0001" => O <= "00";
when "0010" => O <= "01";
when "0100" => O <= "10";
when "1000" => O <= "11";
when others => null;
end case;
end process;
end Behavioral;
| gpl-3.0 | 706971938013f48ba5771758fb916486 | 0.536207 | 3.569231 | false | false | false | false |
nickg/nvc | test/regress/record19.vhd | 1 | 856 | entity record19 is
end entity;
architecture test of record19 is
type data_t is record
x, y : bit;
end record;
type data_vector is array (natural range <>) of data_t;
procedure mux (signal data_i : in data_vector(1 to 7);
selected : in integer;
signal data_o : out data_t )
is
variable tmp : data_t;
begin
tmp := data_i(selected);
data_o <= tmp;
end procedure;
signal di : data_vector(1 to 7);
signal do : data_t;
begin
main: process is
begin
di <= ( 2 => ('1', '1'), others => ('0', '0') );
wait for 1 ns;
mux(di, 1, do);
wait for 1 ns;
assert do = ( '0', '0' );
mux(di, 2, do);
wait for 1 ns;
assert do = ( '1', '1' );
wait;
end process;
end architecture;
| gpl-3.0 | 2a45872850c98faa6503d573ea46234e | 0.495327 | 3.551867 | false | false | false | false |
nickg/nvc | test/regress/elab13.vhd | 1 | 911 | entity recur is
generic (
DEPTH : natural; delay : delay_length );
end entity;
architecture test of recur is
begin
base_g: if DEPTH = 0 generate
process is
begin
wait for delay;
report recur'path_name;
wait;
end process;
end generate;
recur_g: if DEPTH > 0 generate
recur1_i: entity work.recur
generic map (
DEPTH => DEPTH - 1, delay => delay );
recur2_i: entity work.recur
generic map (
DEPTH => DEPTH - 1, delay => delay + (2**(depth-1)) * ns );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab13 is
end entity;
architecture test of elab13 is
begin
top_i: entity work.recur
generic map (
DEPTH => 3, delay => 0 ns );
end architecture;
| gpl-3.0 | ce2e5c8323afcb09aee806592c8e9253 | 0.497256 | 4.532338 | false | false | false | false |
tgingold/ghdl | testsuite/synth/func01/tb_func07.vhdl | 1 | 510 | entity tb_func07 is
end tb_func07;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func07 is
signal v, r : std_ulogic_vector(7 downto 0);
begin
dut: entity work.func07
port map (v, r);
process
begin
v <= "00000000";
wait for 1 ns;
assert r = x"00" severity failure;
v <= "00100100";
wait for 1 ns;
assert r = x"02" severity failure;
v <= "11100111";
wait for 1 ns;
assert r = x"06" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | ab9a9153f0603d7a576f5f01d1c85c82 | 0.62549 | 3.207547 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1614.vhd | 4 | 2,134 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1614.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p01n01i01614ent IS
END c08s12b00x00p01n01i01614ent;
ARCHITECTURE c08s12b00x00p01n01i01614arch OF c08s12b00x00p01n01i01614ent IS
--
-- Nested procedures to test return statement.
--
procedure two ( variable val : inout integer ) is
procedure one ( variable val : out integer ) is
begin
val := 1;
return;
val := 2; -- should never get here
end one;
begin
one(val);
val := val * 2;
return;
val := val * 2; -- should never get here
end two;
BEGIN
TESTING : PROCESS
variable v1 : integer;
BEGIN
two (v1);
assert NOT( v1=2 )
report "***PASSED TEST: c08s12b00x00p01n01i01614"
severity NOTE;
assert ( v1=2 )
report "***FAILED TEST: c08s12b00x00p01n01i01614 - Return statement applies to the innermost enclosing function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p01n01i01614arch;
| gpl-2.0 | 6f6b20070e8a5080e953b2a7eb34f352 | 0.641987 | 3.770318 | false | true | false | false |
nickg/nvc | test/regress/predef1.vhd | 1 | 5,575 | entity predef1 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of predef1 is
type my_int is range 1 to 10;
type my_enum is (X, Y, FOO, BAR);
type int_vector is array (natural range <>) of integer;
type my_char is ('a', 'b', 'c');
type char_vector is array (natural range <>) of my_char;
type my_phs is range 0 to 1000
units
u_foo;
u_bar = 10 u_foo;
end units;
signal sa : bit := '0';
signal sb : boolean := true;
signal sl : std_logic := '0';
signal sv : bit_vector(1 to 3);
signal sx : std_logic_vector(1 to 3);
begin
main: process is
variable b : boolean;
variable i : integer;
variable m : my_int;
variable e : my_enum;
variable r : real := 1.23456;
variable v : int_vector(1 to 3) := (1, 2, 3);
variable c : char_vector(1 to 3) := "bca";
begin
-----------------------------------------------------------------------
-- MINIMUM
assert minimum(1, 2) = 1;
m := 5;
b := true;
wait for 1 ns;
assert minimum(4, m) = 4;
assert minimum(b, false) = false;
assert minimum(int_vector'(5, -1, 2)) = -1;
assert minimum(v) = 1;
-----------------------------------------------------------------------
-- MAXIMUM
assert maximum(2, 1) = 2;
m := 6;
wait for 1 ns;
assert maximum(4, m) = 6;
assert maximum(b, false) = true;
assert maximum(int_vector'(5, -1, 2)) = 5;
assert maximum(v) = 3;
assert maximum(1 ns, 1 hr) = 1 hr;
-----------------------------------------------------------------------
-- TO_STRING
assert to_string(my_int'(7)) = "7";
assert to_string(m) = "6";
assert to_string(foo) = "foo";
assert to_string(e) = my_enum'image(e);
report to_string(now);
assert to_string(now) = "2000000 fs";
report to_string(now, ns);
assert to_string(now, ns) = "2 ns";
assert to_string(50 ns, unit => us) = "0.05 us";
assert to_string(value => 1 min, unit => hr) = "0.0166667 hr";
assert to_string(r)(1 to 7) = "1.23456";
report to_string(r, 2);
assert to_string(r, 2) = "1.23";
report to_string(r, 0);
assert to_string(r, 0)(1 to 7) = "1.23456";
report to_string(r, "%1.1f");
assert to_string(r, "%1.1f") = "1.2";
r := 0.0000000005;
report to_string(value => r, digits => 9);
report to_string(char_vector'("abc"));
assert to_string(char_vector'("abc")) = "abc";
assert to_string(c) = "bca";
assert to_string(bit_vector'("110")) = "110";
assert to_string(bit_vector'("110")) & "..." = "110...";
assert to_string(1 ns) = "1000000 fs";
assert to_string(1 u_bar) = "10 u_foo";
assert to_string(bit'( '1' )) = "1";
assert to_string(character'( 'X' )) = "X";
-----------------------------------------------------------------------
-- TO_BSTRING
assert to_bstring(bit_vector'("101")) = "101";
-----------------------------------------------------------------------
-- TO_HSTRING
report to_hstring(bit_vector'("10101111"));
assert to_hstring(bit_vector'("10101111")) = "AF";
assert to_hstring(bit_vector'("01100")) = "0C";
assert to_hex_string(bit_vector'("111")) = "7";
-----------------------------------------------------------------------
-- TO_OSTRING
report to_ostring(bit_vector'("10101111"));
assert to_ostring(bit_vector'("10101111")) = "257";
assert to_ostring(bit_vector'("01100")) = "14";
assert to_octal_string(bit_vector'("0")) = "0";
-----------------------------------------------------------------------
-- RISING_EDGE / FALLING_EDGE
sa <= '1';
sb <= false;
wait for 0 ns;
assert sa'event and sa = '1';
assert rising_edge(sa);
assert not falling_edge(sa);
assert sb'event and sb = false;
assert not rising_edge(sb);
assert falling_edge(sb);
-----------------------------------------------------------------------
-- Matching comparison
sa <= '1';
wait for 0 ns;
assert (sa ?= '1') = '1';
assert (sa ?/= '0') = '1';
assert (sa ?< '1') = '0';
assert (sa ?<= '1') = '1';
assert (sa ?> '0') = '1';
assert (sa ?>= '1') = '1';
sl <= '1';
wait for 0 ns;
assert (sl ?= '1') = '1';
assert (sl ?/= '0') = '1';
assert (sl ?< '1') = '0';
assert (sl ?<= '1') = '1';
assert (sl ?> '0') = '1';
assert (sl ?>= '1') = '1';
assert (sl ?= 'Z') = 'X';
assert (sl ?< 'H') = '0';
assert ('0' ?<= sl) = '1';
sv <= "111";
wait for 0 ns;
assert (sv ?= "111") = '1';
assert (sv ?= "011") = '0';
assert (sv ?/= "000") = '1';
-----------------------------------------------------------------------
-- Mixed array/scalar bit_vector operations
sa <= '1';
sv <= "101";
wait for 1 ns;
assert (sa and sv) = "101";
assert (sa or sv) = "111";
assert (sv xor sa) = "010";
assert (sv nor sa) = "000";
assert (sv nand sa) = "010";
assert (sa xnor sv) = "101";
wait;
end process;
end architecture;
| gpl-3.0 | 22d17efa14dd50f064f7148118448d24 | 0.417758 | 3.774543 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1120/repro2.vhdl | 1 | 379 | entity repro2 is
generic(
BITS : positive := 4);
port(
min : in bit_vector(BITS - 1 downto 0) := "1010");
end entity;
architecture rtl of repro2 is
begin
process
variable sum : bit_vector(BITS - 2 downto 0);
variable carry : bit;
begin
(carry, sum) := min;
assert carry = '1';
assert sum = "010";
wait;
end process;
end architecture;
| gpl-2.0 | bb34e3225c68f10f0eb89d05bbaae71b | 0.609499 | 3.445455 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_04.vhd | 4 | 4,384 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity cache is
generic ( cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10) );
port ( halt : in bit );
end entity cache;
architecture instrumented of cache is
begin
-- code from book
cache_monitor : process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file
open append_mode is "cache-measurements";
-- . . .
-- not in book
constant miss_count : natural := 100;
constant total_accesses : natural := 1000;
constant total_delay : delay_length := 2400 ns;
-- end not in book
begin
-- . . .
loop
-- . . .
-- not in book
wait on halt;
-- end not in book
exit when halt = '1';
-- . . .
end loop;
write ( measurements,
measurement_record'(
-- write values of generics for this run
cache_size, block_size, associativity, benchmark_name,
-- calculate performance metrics
miss_rate => real(miss_count) / real(total_accesses),
ave_access_time => total_delay / total_accesses ) );
wait;
end process cache_monitor;
-- end code from book
end architecture instrumented;
entity fg_18_04 is
end entity fg_18_04;
architecture test of fg_18_04 is
signal halt : bit := '0';
begin
dut : entity work.cache(instrumented)
generic map ( cache_size => 128*1024, block_size => 16,
associativity => 2, benchmark_name => "dhrystone " )
port map ( halt => halt );
halt <= '1' after 10 ns;
end architecture test;
entity fg_18_04_a is
end entity fg_18_04_a;
architecture reader of fg_18_04_a is
begin
process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file open read_mode is "cache-measurements";
variable measurement : measurement_record;
use std.textio.all;
variable L : line;
begin
while not endfile(measurements) loop
read(measurements, measurement);
write(L, measurement.cache_size);
write(L, ' ');
write(L, measurement.block_size);
write(L, ' ');
write(L, measurement.associativity);
write(L, ' ');
write(L, measurement.benchmark_name);
write(L, ' ');
write(L, measurement.miss_rate);
write(L, ' ');
write(L, measurement.ave_access_time);
writeline(output, L);
end loop;
wait;
end process;
end architecture reader;
| gpl-2.0 | d87a471d9844b11c24171ae47fab55ca | 0.557026 | 4.473469 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1109/ent-orig.vhdl | 1 | 2,982 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
generic (
INT : integer := -42;
NAT : natural := 21
);
port (
slv_a : in std_logic_vector(7 downto 0);
slv_b : in std_logic_vector(7 downto 0);
slv_eq : out std_logic;
slv_ne : out std_logic;
sl_a : out std_logic;
sl_b : out std_logic;
sl_lt : out std_logic;
sl_le : out std_logic;
sl_eq : out std_logic;
sl_ne : out std_logic;
sl_ge : out std_logic;
sl_gt : out std_logic;
uns_a : in unsigned(7 downto 0);
uns_b : in unsigned(7 downto 0);
uns_lt : out std_logic;
uns_le : out std_logic;
uns_eq : out std_logic;
uns_ne : out std_logic;
uns_ge : out std_logic;
uns_gt : out std_logic;
uns_int_lt : out std_logic;
uns_int_le : out std_logic;
uns_int_eq : out std_logic;
uns_int_ne : out std_logic;
uns_int_ge : out std_logic;
uns_int_gt : out std_logic;
int_uns_lt : out std_logic;
int_uns_le : out std_logic;
int_uns_eq : out std_logic;
int_uns_ne : out std_logic;
int_uns_ge : out std_logic;
int_uns_gt : out std_logic;
sgn_a : in signed(7 downto 0);
sgn_b : in signed(7 downto 0);
sgn_lt : out std_logic;
sgn_le : out std_logic;
sgn_eq : out std_logic;
sgn_ne : out std_logic;
sgn_ge : out std_logic;
sgn_gt : out std_logic;
sgn_nat_lt : out std_logic;
sgn_nat_le : out std_logic;
sgn_nat_eq : out std_logic;
sgn_nat_ne : out std_logic;
sgn_nat_ge : out std_logic;
sgn_nat_gt : out std_logic;
nat_sgn_lt : out std_logic;
nat_sgn_le : out std_logic;
nat_sgn_eq : out std_logic;
nat_sgn_ne : out std_logic;
nat_sgn_ge : out std_logic;
nat_sgn_gt : out std_logic
);
end;
architecture a of ent is
begin
slv_eq <= slv_a ?= slv_b;
slv_ne <= slv_a ?/= slv_b;
sl_lt <= sl_a ?< sl_b;
sl_le <= sl_a ?<= sl_b;
sl_eq <= sl_a ?= sl_b;
sl_ne <= sl_a ?/= sl_b;
sl_ge <= sl_a ?>= sl_b;
sl_gt <= sl_a ?> sl_b;
uns_lt <= uns_a ?< uns_b;
uns_le <= uns_a ?<= uns_b;
uns_eq <= uns_a ?= uns_b;
uns_ne <= uns_a ?/= uns_b;
uns_ge <= uns_a ?>= uns_b;
uns_gt <= uns_a ?> uns_b;
uns_int_lt <= uns_a ?< INT;
uns_int_le <= uns_a ?<= INT;
uns_int_eq <= uns_a ?= INT;
uns_int_ne <= uns_a ?/= INT;
uns_int_ge <= uns_a ?>= INT;
uns_int_gt <= uns_a ?> INT;
int_uns_lt <= INT ?< uns_b;
int_uns_le <= INT ?<= uns_b;
int_uns_eq <= INT ?= uns_b;
int_uns_ne <= INT ?/= uns_b;
int_uns_ge <= INT ?>= uns_b;
int_uns_gt <= INT ?> uns_b;
sgn_lt <= sgn_a ?< sgn_b;
sgn_le <= sgn_a ?<= sgn_b;
sgn_eq <= sgn_a ?= sgn_b;
sgn_ne <= sgn_a ?/= sgn_b;
sgn_ge <= sgn_a ?>= sgn_b;
sgn_gt <= sgn_a ?> sgn_b;
sgn_nat_lt <= sgn_a ?< NAT;
sgn_nat_le <= sgn_a ?<= NAT;
sgn_nat_eq <= sgn_a ?= NAT;
sgn_nat_ne <= sgn_a ?/= NAT;
sgn_nat_ge <= sgn_a ?>= NAT;
sgn_nat_gt <= sgn_a ?> NAT;
nat_sgn_lt <= NAT ?< sgn_b;
nat_sgn_le <= NAT ?<= sgn_b;
nat_sgn_eq <= NAT ?= sgn_b;
nat_sgn_ne <= NAT ?/= sgn_b;
nat_sgn_ge <= NAT ?>= sgn_b;
nat_sgn_gt <= NAT ?> sgn_b;
end;
| gpl-2.0 | 52543ceeb0acf3a9414e9a9d2e103031 | 0.560027 | 2.203991 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/assert_uut.vhd | 2 | 4,985 | --test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity assert_uut is
port(
clock : in std_logic;
reset : in std_logic;
context_uut : in context_t;
en_feed : in std_logic;
stdin_rdy : in std_logic;
stdin_ack : out std_logic;
stdin_data : out stdin_vector;
en_check : in std_logic;
stdout_rdy : in std_logic;
stdout_ack : out std_logic;
stdout_data : in stdout_vector;
vecs_found : out std_logic;
vec_read : out std_logic;
n_error : out std_logic
);
end assert_uut;
architecture rtl of assert_uut is
type vin_table is array(0 to 2**VEC_NO_SIZE - 1) of stdin_vector;
type vout_table is array(0 to 2**VEC_NO_SIZE - 1) of stdout_vector;
constant input_vectors_1 : vin_table := (
--##INPUT_VECTORS_1_GO_DOWN_HERE##--
0 => x"00_00_00_07",
1 => x"00_00_00_03",
--##INPUT_VECTORS_1_GO_OVER_HERE##--
others => (others => '0'));
constant output_vectors_1 : vout_table := (
--##OUTPUT_VECTORS_1_GO_DOWN_HERE##--
0 => x"00_00_00_16",
--##OUTPUT_VECTORS_1_GO_OVER_HERE##--
others => (others => '0'));
constant input_vectors_2 : vin_table := (
--##INPUT_VECTORS_2_GO_DOWN_HERE##--
0 => x"00_00_00_07",
1 => x"00_00_00_03",
--##INPUT_VECTORS_2_GO_OVER_HERE##--
others => (others => '0'));
constant output_vectors_2 : vout_table := (
--##OUTPUT_VECTORS_2_GO_DOWN_HERE##--
0 => x"00_00_00_16",
--##OUTPUT_VECTORS_2_GO_OVER_HERE##--
others => (others => '0'));
signal out_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal out_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal stdin_ack_sig : std_logic;
signal vector_read : std_logic;
begin
feed : process(reset, clock) is
variable in_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
variable in_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
begin
if (reset = '1') then
in_vec_counter_1 := (others => '0');
in_vec_counter_2 := (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
elsif rising_edge(clock) then
case context_uut is
when "01" =>
if (en_feed = '1') then
stdin_data <= input_vectors_1(to_integer(in_vec_counter_1));
stdin_ack_sig <= '1';
if (stdin_rdy = '1' and stdin_ack_sig = '1') then
in_vec_counter_1 := in_vec_counter_1 + 1;
stdin_ack_sig <= '0';
end if;
else
--in_vec_counter_1 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
end if;
when "10" =>
if (en_feed = '1') then
stdin_data <= input_vectors_2(to_integer(in_vec_counter_2));
stdin_ack_sig <= '1';
if (stdin_rdy = '1' and stdin_ack_sig = '1') then
in_vec_counter_2 := in_vec_counter_2 + 1;
stdin_ack_sig <= '0';
end if;
else
--in_vec_counter_2 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
end if;
when others =>
end case;
end if;
end process feed;
check : process(reset, clock) is
begin
if (reset = '1') then
n_error <= '1';
vec_read <= '0';
elsif rising_edge(clock) then
vec_read <= '0';
if (en_check = '1') then
if (stdout_rdy = '1') then
vec_read <= '1';
case context_uut is
when "01" =>
assert (stdout_data = output_vectors_1(to_integer(out_vec_counter_1)))
report "ERROR ---> Bad output vector found";
--synthesizable check
if (stdout_data /= output_vectors_1(to_integer(out_vec_counter_1))) then
n_error <= '0';
end if;
when "10" =>
assert (stdout_data = output_vectors_2(to_integer(out_vec_counter_2)))
report "ERROR ---> Bad output vector found";
--synthesizable check
if (stdout_data /= output_vectors_2(to_integer(out_vec_counter_2))) then
n_error <= '0';
end if;
when others =>
end case;
end if;
end if;
end if;
end process check;
read_counter : process(reset, clock) is
begin
if (reset = '1') then
out_vec_counter_1 <= (others => '0');
out_vec_counter_2 <= (others => '0');
elsif rising_edge(clock) then
if (en_check = '1') then
if (stdout_rdy = '1') then
case context_uut is
when "01" =>
out_vec_counter_1 <= out_vec_counter_1 + 1;
when "10" =>
out_vec_counter_2 <= out_vec_counter_2 + 1;
when others =>
end case;
end if;
--else
-- case context_uut is
-- when "01" =>
-- out_vec_counter_1 <= (others => '0');
-- when "10" =>
-- out_vec_counter_2 <= (others => '0');
-- when others =>
-- end case;
end if;
end if;
end process read_counter;
--asynchronous declarations
stdout_ack <= en_check;
stdin_ack <= stdin_ack_sig;
vecs_found <= '1' when (out_vec_counter_1 /= 0 or out_vec_counter_2 /= 0) else '0';
end rtl;
| gpl-2.0 | 7fb1828185cf446bc4c2d9046cdb7c75 | 0.565496 | 2.727024 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0100/forloop.vhdl | 1 | 1,102 | entity forloop is
end forloop;
architecture behav of forloop is
signal clk : bit;
signal rst : bit := '1';
signal tx : bit;
signal data : bit_vector (7 downto 0);
signal valid : bit;
signal err : bit;
begin
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
variable txdata : bit_vector (7 downto 0);
begin
rst <= '1';
tx <= '1';
pulse;
rst <= '0';
-- Transmit 1 byte.
tx <= '0';
pulse;
assert err = '0' and valid = '0' severity error;
txdata :
for i in txdata'reverse_range loop
tx <= txdata(i);
pulse;
assert err = '0' and valid = '0' severity error;
end loop;
tx <= '1'; -- parity
pulse;
tx <= '1'; -- stop
pulse;
assert valid = '1' severity error;
assert err = '0' severity error;
assert data = txdata;
wait;
end process;
end behav;
| gpl-2.0 | 01bed04adbc04133e4184bb26bdce2c0 | 0.467332 | 4.081481 | false | false | false | false |
tgingold/ghdl | testsuite/synth/func01/tb_func01.vhdl | 1 | 466 | entity tb_func01 is
end tb_func01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func01 is
signal a, b : std_logic_vector(7 downto 0);
signal sel : std_logic;
begin
dut: entity work.func01
port map (a, sel, b);
process
begin
a <= x"5d";
sel <= '1';
wait for 1 ns;
assert b = x"0d" severity failure;
sel <= '0';
wait for 1 ns;
assert b = x"5d" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 0260ae5dfaf13a22fa01203a28eb4742 | 0.618026 | 2.987179 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/fsm.vhd | 4 | 9,367 | --test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity fsm is
port(
clock : in std_logic;
reset : in std_logic;
--prog interface
instr_next : in instruction;
step : out std_logic;
--uut interface
cp_ok : in std_logic;
stdin_rdy : in std_logic;
stdin_ack : in std_logic;
reset_fsm : out std_logic;
start : out std_logic;
cp_en : out std_logic;
cp_rest : out std_logic;
--ram interface
ram_1 : out ram_instruction;
ram_2 : out ram_instruction;
--assert_uut interface
context_uut : out context_t;
en_feed : out std_logic;
en_check : out std_logic;
vecs_found : in std_logic;
vec_read : in std_logic;
--tb interface
stopped : out std_logic
);
end fsm;
architecture rtl of fsm is
-- read output
signal step_sig : std_logic;
-- FSM signals
signal instr_c : instruction := instr_rst;
signal instr_n : instruction := instr_rst;
-- TIMER signal
signal times_en : std_logic := '0';
signal times_z : std_logic := '0';
signal times : unsigned(ARG_WIDTH - 1 downto 0);
signal times_max : unsigned(ARG_WIDTH - 1 downto 0);
signal times_ok : std_logic := '0';
-- COUNTER signal
signal count_en : std_logic := '0';
signal count_z : std_logic := '0';
signal count : unsigned(ARG_WIDTH - 1 downto 0);
signal count_max : unsigned(ARG_WIDTH - 1 downto 0);
signal count_ok : std_logic := '0';
-- runtime counter
signal runtime_en : std_logic := '0';
signal runtime : integer range 0 to 99999999; --100 million cycles
begin
-- FSM
state_reg : process (clock, reset) is
begin
if (reset = '1') then
instr_c <= instr_rst;
elsif rising_edge(clock) then
instr_c <= instr_n;
end if;
end process state_reg;
comb_logic: process(instr_next, instr_c, stdin_rdy, count_ok, times_ok, cp_ok, stdin_ack, vecs_found, vec_read)
begin
--default definition for fsm control signals
instr_n <= instr_rst;
step_sig <= '0';
--top
reset_fsm <= '0';
start <= '0';
cp_en <= '0';
cp_rest <= '0';
--counter & timer
times_en <= '0';
times_max <= (others => '0');
count_en <= '0';
count_max <= (others => '0');
--runtime counter
runtime_en <= '0';
--ram
ram_1 <= ram_instr_z;
ram_2 <= ram_instr_z;
--assert_uut
en_feed <= '0';
en_check <= '0';
--tb interface
stopped <= '0';
case instr_c.state is
when Rst =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
when Sig_start =>
--signals
start <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
--if (instr_next.state = Ack_data) then
--en_feed <= '1';
--end if;
when Ack_data =>
times_max <= instr_c.arg - 1;
--signals
en_feed <= '1';
--transition
if (stdin_rdy = '1' and stdin_ack = '1') then
times_en <= '1';
end if;
if (times_ok = '1') then
en_feed <= '0';
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Running =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--en_check <= '1';
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Waitfor =>
--signals
count_max <= instr_c.arg;
en_check <= '1';
if(vec_read = '1') then
count_en <= '1';
end if;
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Cp_search =>
--signals
cp_en <= '1';
--transition
if (cp_ok = '1') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
instr_n <= (state => Cp_save, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
else
instr_n <= instr_c;
end if;
when Cp_save =>
--signals
cp_en <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '0';
ram_1.addr_up <= '0';
when "10" =>
ram_2.we <= '0';
ram_2.addr_up <= '0';
when others =>
end case;
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Idle =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Rst_uut =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
--transition
step_sig <= '1';
instr_n <= instr_next;
when Rest_ini0 =>
--signals
start <= '1';
cp_en <= '1';
cp_rest <= '1';
--this is for restoration : reading the first word of the right memory
case instr_c.context_uut is
when "01" =>
ram_1.sel <= '1';
when "10" =>
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest_ini1, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest_ini1 =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Stop =>
--signals
stopped <= '1';
reset_fsm <= '1';
report "RUNTIME:" & integer'image(runtime);
assert (vecs_found = '0')
report "END_OF_SIM ---> Stop state reached, some output vectors were read." severity note;
--transition
instr_n <= (state => Stop, context_uut => "00", arg => (others => '0')); --hard coded
when others =>
end case;
end process comb_logic;
--*ER reset combo logic
--if a step_sig signal is sent, it means a instr_next will be consumed
reseter : process(step_sig)
begin
if (step_sig = '0') then
times_z <= '0';
count_z <= '0';
else
times_z <= '1';
count_z <= '1';
end if;
end process reseter;
--TIMER
timer : process(clock, reset)
begin
if (reset = '1') then
times <= (others => '0');
times_ok <= '0';
elsif rising_edge(clock) then
if (times_z = '1') then
times <= (others => '0');
times_ok <= '0';
else
if (times_en = '1') then
times <= times + 1;
if (times = times_max) then
times_ok <= '1';
else
times_ok <= '0';
end if;
end if;
end if;
end if;
end process timer;
--COUNTER
counter : process(clock, reset)
begin
if (reset = '1') then
count <= (others => '0');
count_ok <= '0';
elsif rising_edge(clock) then
--count_ok driving if
if (count_z = '1') then
count_ok <= '0';
count <= (others => '0');
else
if (count = count_max) then
count_ok <= '1';
else
count_ok <= '0';
if (count_en = '1') then
count <= count + 1;
end if;
end if;
end if;
end if;
end process counter;
--Runtime counter
runtime_counter : process(clock, reset)
begin
if (reset = '1') then
runtime <= 0;
elsif rising_edge(clock) then
if (runtime_en = '1') then
runtime <= runtime + 1;
if ((runtime mod 1000) = 0) then
report "Running since:" & integer'image(runtime) severity note;
end if;
end if;
end if;
end process runtime_counter;
-- process only used for reporting current instruction
reporter : process(instr_c)
begin
--report "Instruction: " & state_t'image(instr_c.state) severity note;
report "Instruction: " & state_t'image(instr_c.state) & " (context " & integer'image(to_integer(unsigned(instr_c.context_uut))) & ")" severity note;
end process reporter;
--Combinational
step <= step_sig;
context_uut <= instr_c.context_uut;
end rtl;
| gpl-2.0 | 71ea3255f820c3b35155ea59b4dbb91a | 0.530266 | 2.74934 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1069/tdp_ram2.vhdl | 1 | 3,897 | library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH_A : positive := 12;
WIDTH_A : positive := 8;
ADDRWIDTH_B : positive := 10;
WIDTH_B : positive := 32;
COL_WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
byteen_a : in std_logic_vector(WIDTH_A/COL_WIDTH - 1 downto 0);
addr_a : in std_logic_vector(ADDRWIDTH_A - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH_A - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH_A - 1 downto 0);
clk_b : in std_logic;
read_b : in std_logic;
write_b : in std_logic;
byteen_b : in std_logic_vector(WIDTH_B/COL_WIDTH - 1 downto 0);
addr_b : in std_logic_vector(ADDRWIDTH_B - 1 downto 0);
data_read_b : out std_logic_vector(WIDTH_B - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH_B - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
function log2(val : INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2 ** i)) then
res := i;
exit;
end if;
end loop;
return res;
end function log2;
function eq_assert(x : integer; y : integer) return integer is
begin
assert x = y;
return x;
end function eq_assert;
constant COLS_A : positive := WIDTH_A / COL_WIDTH;
constant COLS_B : positive := WIDTH_B / COL_WIDTH;
constant TOTAL_COLS : positive := eq_assert(COLS_A * 2 ** ADDRWIDTH_A, COLS_B * 2 ** ADDRWIDTH_B);
constant EXTRA_ADDR_BITS_A : positive := log2(COLS_A);
constant EXTRA_ADDR_BITS_B : positive := log2(COLS_B);
signal reg_a : std_logic_vector(WIDTH_A - 1 downto 0);
signal reg_b : std_logic_vector(WIDTH_B - 1 downto 0);
begin
assert WIDTH_A mod COL_WIDTH = 0 and
WIDTH_B mod COL_WIDTH = 0 and
2 ** (ADDRWIDTH_A + EXTRA_ADDR_BITS_A) = TOTAL_COLS and
2 ** (ADDRWIDTH_B + EXTRA_ADDR_BITS_B) = TOTAL_COLS
report "Both WIDTH_A and WIDTH_B have to be a power-of-two multiple of COL_WIDTH"
severity failure;
process(clk_a, clk_b)
type ram_t is array(0 to TOTAL_COLS - 1) of std_logic_vector(COL_WIDTH - 1 downto 0);
variable store : ram_t := (others => (others => '0'));
begin
if rising_edge(clk_a) then
for i in 0 to COLS_A - 1 loop
if write_a = '1' and byteen_a(i) = '1' then
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A))) :=
data_write_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH);
end if;
if read_a = '1' then
reg_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH) <=
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A)));
end if;
end loop;
data_read_a <= reg_a;
end if;
if rising_edge(clk_b) then
for i in 0 to COLS_B - 1 loop
if write_b = '1' and byteen_b(i) = '1' then
store(to_integer(unsigned(addr_b) & to_unsigned(i, EXTRA_ADDR_BITS_B))) :=
data_write_b((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH);
end if;
if read_b = '1' then
reg_b((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH) <=
store(to_integer(unsigned(addr_b) & to_unsigned(i, EXTRA_ADDR_BITS_B)));
end if;
end loop;
data_read_b <= reg_b;
end if;
end process;
end behavioral;
| gpl-2.0 | d5edacf16d4f22a39e18e2d24035f6b1 | 0.519117 | 3.415425 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/altsyncram_db0.vhd | 1 | 8,340 | -- megafunction wizard: %ALTSYNCRAM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: altsyncram_db0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altsyncram_db0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END altsyncram_db0;
ARCHITECTURE SYN OF altsyncram_db0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "SOUND.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 512,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 9,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "SOUND.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "SOUND.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL address[8..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram_db0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram_db0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram_db0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram_db0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram_db0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram_db0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram_db0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | 093d6ffeb9c8abfd8d4042c3f7b9e365 | 0.670743 | 3.493925 | false | false | false | false |
tgingold/ghdl | testsuite/synth/case02/tb_case03.vhdl | 1 | 942 | entity tb_case03 is
end tb_case03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_case03 is
signal clk : std_logic;
signal opc : std_logic_vector (2 downto 0);
signal arg : std_logic_vector (7 downto 0);
signal res : std_logic_vector (7 downto 0);
signal par : std_logic;
begin
dut: entity work.case03
port map (clk, opc, arg, res, par);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
opc <= "000";
arg <= x"45";
pulse;
assert res = x"ba" severity failure;
assert par = '1' severity failure;
opc <= "010";
arg <= x"55";
pulse;
assert res = x"aa" severity failure;
assert par = '0' severity failure;
opc <= "110";
arg <= x"57";
pulse;
assert res = x"57" severity failure;
assert par = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 937e2b425a776a8bf30f3dd92596b9e2 | 0.59448 | 3.328622 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/tb_asgn06.vhdl | 1 | 830 | entity tb_asgn06 is
end tb_asgn06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn06 is
signal s0 : std_logic;
signal clk : std_logic;
signal r : std_logic_vector (65 downto 0);
begin
dut: entity work.asgn06
port map (clk => clk, s0 => s0, r => r);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
s0 <= '0';
pulse;
assert r (0) = '1' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cccc" severity failure;
assert r (65) = '1' severity failure;
s0 <= '1';
pulse;
assert r (0) = '0' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cc9c" severity failure;
assert r (65) = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | ac3298a22eb1c3532d982f9b3688c8ef | 0.59759 | 3.097015 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug084/func_test3.vhdl | 1 | 1,085 | entity func_test3 is
generic (NBITS: natural := 6);
end entity;
architecture fum of func_test3 is
type remains is (r0, r1, r2, r3, r4); -- remainder values
function mod5 (dividend: bit_vector) return boolean is
type remain_array is array (NBITS downto 0) of remains;
type branch is array (remains, bit) of remains;
constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
r1 => ('0' => r2, '1' => r3),
r2 => ('0' => r4, '1' => r0),
r3 => ('0' => r1, '1' => r2),
r4 => ('0' => r3, '1' => r4)
);
variable remaind: remains := r0;
variable tbit: bit_vector (NBITS - 1 downto 0) := dividend;
begin
for i in dividend'length - 1 downto 0 loop
remaind := br_table(remaind,tbit(i));
end loop;
return remaind = r0;
end function;
begin
assert mod5("101000");
end architecture;
| gpl-2.0 | 525aab619259f8b5d9617ddcc29b6458 | 0.4553 | 3.847518 | false | true | false | false |
nickg/nvc | test/regress/genpack5.vhd | 1 | 1,456 | package poly is
generic (a, b, def : integer);
function apply (x : integer := def) return integer;
end package;
package body poly is
function apply (x : integer := def) return integer is
begin
return x * a + b;
end function;
end package body;
-------------------------------------------------------------------------------
package wrapper is
generic ( package p is new work.poly generic map ( <> ) );
function wrapped_apply (n : integer) return integer;
end package;
package body wrapper is
use p.all;
function wrapped_apply (n : integer) return integer is
begin
return apply(n);
end function;
end package body;
-------------------------------------------------------------------------------
entity genpack5 is
end entity;
architecture test of genpack5 is
package my_poly1 is new work.poly generic map (a => 2, b => 3, def => 10);
package my_wrap1 is new work.wrapper generic map (p => my_poly1);
package my_poly2 is new work.poly generic map (a => 5, b => 1, def => 1);
package my_wrap2 is new work.wrapper generic map (p => my_poly2);
begin
main: process is
variable v : integer := 5;
begin
assert my_wrap1.wrapped_apply(2) = 7;
wait for 1 ns;
assert my_wrap1.wrapped_apply(v) = 13;
assert my_wrap2.wrapped_apply(2) = 11;
assert my_wrap2.wrapped_apply(v) = 26;
wait;
end process;
end architecture;
| gpl-3.0 | 04aaeb729a4047b11ecc581a8750d414 | 0.563874 | 3.967302 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue951/tb_ent.vhdl | 1 | 824 | entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal en : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.ent
port map (clk => clk, enable => en, i => din, o => dout);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
en <= '1';
pulse;
assert dout = '0' severity failure;
din <= '1';
en <= '1';
pulse;
assert dout = '1' severity failure;
din <= '0';
en <= '0';
pulse;
assert dout = '1' severity failure;
wait;
din <= '0';
en <= '1';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 578c848b10a014440742846e414af107 | 0.541262 | 3.282869 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_ila_0_0/synth/design_1_ila_0_0.vhd | 1 | 315,329 | -- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_ila_0_0 IS
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END design_1_ila_0_0;
ARCHITECTURE design_1_ila_0_0_arch OF design_1_ila_0_0 IS
COMPONENT ila_v6_1_0_ila IS
GENERIC (
C_XLNX_HW_PROBE_INFO : STRING;
C_XDEVICEFAMILY : STRING;
C_CORE_TYPE : INTEGER;
C_CORE_INFO1 : INTEGER;
C_CORE_INFO2 : INTEGER;
C_CAPTURE_TYPE : INTEGER;
C_MU_TYPE : INTEGER;
C_TC_TYPE : INTEGER;
C_NUM_OF_PROBES : INTEGER;
C_DATA_DEPTH : INTEGER;
C_MAJOR_VERSION : INTEGER;
C_MINOR_VERSION : INTEGER;
C_BUILD_REVISION : INTEGER;
C_CORE_MAJOR_VER : INTEGER;
C_CORE_MINOR_VER : INTEGER;
C_XSDB_SLAVE_TYPE : INTEGER;
C_NEXT_SLAVE : INTEGER;
C_CSE_DRV_VER : INTEGER;
C_USE_TEST_REG : INTEGER;
C_PIPE_IFACE : INTEGER;
C_RAM_STYLE : STRING;
C_TRIGOUT_EN : INTEGER;
C_TRIGIN_EN : INTEGER;
C_ADV_TRIGGER : INTEGER;
C_EN_DDR_ILA : INTEGER;
C_EN_STRG_QUAL : INTEGER;
C_INPUT_PIPE_STAGES : INTEGER;
C_PROBE0_WIDTH : INTEGER;
C_PROBE1_WIDTH : INTEGER;
C_PROBE2_WIDTH : INTEGER;
C_PROBE3_WIDTH : INTEGER;
C_PROBE4_WIDTH : INTEGER;
C_PROBE5_WIDTH : INTEGER;
C_PROBE6_WIDTH : INTEGER;
C_PROBE7_WIDTH : INTEGER;
C_PROBE8_WIDTH : INTEGER;
C_PROBE9_WIDTH : INTEGER;
C_PROBE10_WIDTH : INTEGER;
C_PROBE11_WIDTH : INTEGER;
C_PROBE12_WIDTH : INTEGER;
C_PROBE13_WIDTH : INTEGER;
C_PROBE14_WIDTH : INTEGER;
C_PROBE15_WIDTH : INTEGER;
C_PROBE16_WIDTH : INTEGER;
C_PROBE17_WIDTH : INTEGER;
C_PROBE18_WIDTH : INTEGER;
C_PROBE19_WIDTH : INTEGER;
C_PROBE20_WIDTH : INTEGER;
C_PROBE21_WIDTH : INTEGER;
C_PROBE22_WIDTH : INTEGER;
C_PROBE23_WIDTH : INTEGER;
C_PROBE24_WIDTH : INTEGER;
C_PROBE25_WIDTH : INTEGER;
C_PROBE26_WIDTH : INTEGER;
C_PROBE27_WIDTH : INTEGER;
C_PROBE28_WIDTH : INTEGER;
C_PROBE29_WIDTH : INTEGER;
C_PROBE30_WIDTH : INTEGER;
C_PROBE31_WIDTH : INTEGER;
C_PROBE32_WIDTH : INTEGER;
C_PROBE33_WIDTH : INTEGER;
C_PROBE34_WIDTH : INTEGER;
C_PROBE35_WIDTH : INTEGER;
C_PROBE36_WIDTH : INTEGER;
C_PROBE37_WIDTH : INTEGER;
C_PROBE38_WIDTH : INTEGER;
C_PROBE39_WIDTH : INTEGER;
C_PROBE40_WIDTH : INTEGER;
C_PROBE41_WIDTH : INTEGER;
C_PROBE42_WIDTH : INTEGER;
C_PROBE43_WIDTH : INTEGER;
C_PROBE44_WIDTH : INTEGER;
C_PROBE45_WIDTH : INTEGER;
C_PROBE46_WIDTH : INTEGER;
C_PROBE47_WIDTH : INTEGER;
C_PROBE48_WIDTH : INTEGER;
C_PROBE49_WIDTH : INTEGER;
C_PROBE50_WIDTH : INTEGER;
C_PROBE51_WIDTH : INTEGER;
C_PROBE52_WIDTH : INTEGER;
C_PROBE53_WIDTH : INTEGER;
C_PROBE54_WIDTH : INTEGER;
C_PROBE55_WIDTH : INTEGER;
C_PROBE56_WIDTH : INTEGER;
C_PROBE57_WIDTH : INTEGER;
C_PROBE58_WIDTH : INTEGER;
C_PROBE59_WIDTH : INTEGER;
C_PROBE60_WIDTH : INTEGER;
C_PROBE61_WIDTH : INTEGER;
C_PROBE62_WIDTH : INTEGER;
C_PROBE63_WIDTH : INTEGER;
C_PROBE64_WIDTH : INTEGER;
C_PROBE65_WIDTH : INTEGER;
C_PROBE66_WIDTH : INTEGER;
C_PROBE67_WIDTH : INTEGER;
C_PROBE68_WIDTH : INTEGER;
C_PROBE69_WIDTH : INTEGER;
C_PROBE70_WIDTH : INTEGER;
C_PROBE71_WIDTH : INTEGER;
C_PROBE72_WIDTH : INTEGER;
C_PROBE73_WIDTH : INTEGER;
C_PROBE74_WIDTH : INTEGER;
C_PROBE75_WIDTH : INTEGER;
C_PROBE76_WIDTH : INTEGER;
C_PROBE77_WIDTH : INTEGER;
C_PROBE78_WIDTH : INTEGER;
C_PROBE79_WIDTH : INTEGER;
C_PROBE80_WIDTH : INTEGER;
C_PROBE81_WIDTH : INTEGER;
C_PROBE82_WIDTH : INTEGER;
C_PROBE83_WIDTH : INTEGER;
C_PROBE84_WIDTH : INTEGER;
C_PROBE85_WIDTH : INTEGER;
C_PROBE86_WIDTH : INTEGER;
C_PROBE87_WIDTH : INTEGER;
C_PROBE88_WIDTH : INTEGER;
C_PROBE89_WIDTH : INTEGER;
C_PROBE90_WIDTH : INTEGER;
C_PROBE91_WIDTH : INTEGER;
C_PROBE92_WIDTH : INTEGER;
C_PROBE93_WIDTH : INTEGER;
C_PROBE94_WIDTH : INTEGER;
C_PROBE95_WIDTH : INTEGER;
C_PROBE96_WIDTH : INTEGER;
C_PROBE97_WIDTH : INTEGER;
C_PROBE98_WIDTH : INTEGER;
C_PROBE99_WIDTH : INTEGER;
C_PROBE100_WIDTH : INTEGER;
C_PROBE101_WIDTH : INTEGER;
C_PROBE102_WIDTH : INTEGER;
C_PROBE103_WIDTH : INTEGER;
C_PROBE104_WIDTH : INTEGER;
C_PROBE105_WIDTH : INTEGER;
C_PROBE106_WIDTH : INTEGER;
C_PROBE107_WIDTH : INTEGER;
C_PROBE108_WIDTH : INTEGER;
C_PROBE109_WIDTH : INTEGER;
C_PROBE110_WIDTH : INTEGER;
C_PROBE111_WIDTH : INTEGER;
C_PROBE112_WIDTH : INTEGER;
C_PROBE113_WIDTH : INTEGER;
C_PROBE114_WIDTH : INTEGER;
C_PROBE115_WIDTH : INTEGER;
C_PROBE116_WIDTH : INTEGER;
C_PROBE117_WIDTH : INTEGER;
C_PROBE118_WIDTH : INTEGER;
C_PROBE119_WIDTH : INTEGER;
C_PROBE120_WIDTH : INTEGER;
C_PROBE121_WIDTH : INTEGER;
C_PROBE122_WIDTH : INTEGER;
C_PROBE123_WIDTH : INTEGER;
C_PROBE124_WIDTH : INTEGER;
C_PROBE125_WIDTH : INTEGER;
C_PROBE126_WIDTH : INTEGER;
C_PROBE127_WIDTH : INTEGER;
C_PROBE128_WIDTH : INTEGER;
C_PROBE129_WIDTH : INTEGER;
C_PROBE130_WIDTH : INTEGER;
C_PROBE131_WIDTH : INTEGER;
C_PROBE132_WIDTH : INTEGER;
C_PROBE133_WIDTH : INTEGER;
C_PROBE134_WIDTH : INTEGER;
C_PROBE135_WIDTH : INTEGER;
C_PROBE136_WIDTH : INTEGER;
C_PROBE137_WIDTH : INTEGER;
C_PROBE138_WIDTH : INTEGER;
C_PROBE139_WIDTH : INTEGER;
C_PROBE140_WIDTH : INTEGER;
C_PROBE141_WIDTH : INTEGER;
C_PROBE142_WIDTH : INTEGER;
C_PROBE143_WIDTH : INTEGER;
C_PROBE144_WIDTH : INTEGER;
C_PROBE145_WIDTH : INTEGER;
C_PROBE146_WIDTH : INTEGER;
C_PROBE147_WIDTH : INTEGER;
C_PROBE148_WIDTH : INTEGER;
C_PROBE149_WIDTH : INTEGER;
C_PROBE150_WIDTH : INTEGER;
C_PROBE151_WIDTH : INTEGER;
C_PROBE152_WIDTH : INTEGER;
C_PROBE153_WIDTH : INTEGER;
C_PROBE154_WIDTH : INTEGER;
C_PROBE155_WIDTH : INTEGER;
C_PROBE156_WIDTH : INTEGER;
C_PROBE157_WIDTH : INTEGER;
C_PROBE158_WIDTH : INTEGER;
C_PROBE159_WIDTH : INTEGER;
C_PROBE160_WIDTH : INTEGER;
C_PROBE161_WIDTH : INTEGER;
C_PROBE162_WIDTH : INTEGER;
C_PROBE163_WIDTH : INTEGER;
C_PROBE164_WIDTH : INTEGER;
C_PROBE165_WIDTH : INTEGER;
C_PROBE166_WIDTH : INTEGER;
C_PROBE167_WIDTH : INTEGER;
C_PROBE168_WIDTH : INTEGER;
C_PROBE169_WIDTH : INTEGER;
C_PROBE170_WIDTH : INTEGER;
C_PROBE171_WIDTH : INTEGER;
C_PROBE172_WIDTH : INTEGER;
C_PROBE173_WIDTH : INTEGER;
C_PROBE174_WIDTH : INTEGER;
C_PROBE175_WIDTH : INTEGER;
C_PROBE176_WIDTH : INTEGER;
C_PROBE177_WIDTH : INTEGER;
C_PROBE178_WIDTH : INTEGER;
C_PROBE179_WIDTH : INTEGER;
C_PROBE180_WIDTH : INTEGER;
C_PROBE181_WIDTH : INTEGER;
C_PROBE182_WIDTH : INTEGER;
C_PROBE183_WIDTH : INTEGER;
C_PROBE184_WIDTH : INTEGER;
C_PROBE185_WIDTH : INTEGER;
C_PROBE186_WIDTH : INTEGER;
C_PROBE187_WIDTH : INTEGER;
C_PROBE188_WIDTH : INTEGER;
C_PROBE189_WIDTH : INTEGER;
C_PROBE190_WIDTH : INTEGER;
C_PROBE191_WIDTH : INTEGER;
C_PROBE192_WIDTH : INTEGER;
C_PROBE193_WIDTH : INTEGER;
C_PROBE194_WIDTH : INTEGER;
C_PROBE195_WIDTH : INTEGER;
C_PROBE196_WIDTH : INTEGER;
C_PROBE197_WIDTH : INTEGER;
C_PROBE198_WIDTH : INTEGER;
C_PROBE199_WIDTH : INTEGER;
C_PROBE200_WIDTH : INTEGER;
C_PROBE201_WIDTH : INTEGER;
C_PROBE202_WIDTH : INTEGER;
C_PROBE203_WIDTH : INTEGER;
C_PROBE204_WIDTH : INTEGER;
C_PROBE205_WIDTH : INTEGER;
C_PROBE206_WIDTH : INTEGER;
C_PROBE207_WIDTH : INTEGER;
C_PROBE208_WIDTH : INTEGER;
C_PROBE209_WIDTH : INTEGER;
C_PROBE210_WIDTH : INTEGER;
C_PROBE211_WIDTH : INTEGER;
C_PROBE212_WIDTH : INTEGER;
C_PROBE213_WIDTH : INTEGER;
C_PROBE214_WIDTH : INTEGER;
C_PROBE215_WIDTH : INTEGER;
C_PROBE216_WIDTH : INTEGER;
C_PROBE217_WIDTH : INTEGER;
C_PROBE218_WIDTH : INTEGER;
C_PROBE219_WIDTH : INTEGER;
C_PROBE220_WIDTH : INTEGER;
C_PROBE221_WIDTH : INTEGER;
C_PROBE222_WIDTH : INTEGER;
C_PROBE223_WIDTH : INTEGER;
C_PROBE224_WIDTH : INTEGER;
C_PROBE225_WIDTH : INTEGER;
C_PROBE226_WIDTH : INTEGER;
C_PROBE227_WIDTH : INTEGER;
C_PROBE228_WIDTH : INTEGER;
C_PROBE229_WIDTH : INTEGER;
C_PROBE230_WIDTH : INTEGER;
C_PROBE231_WIDTH : INTEGER;
C_PROBE232_WIDTH : INTEGER;
C_PROBE233_WIDTH : INTEGER;
C_PROBE234_WIDTH : INTEGER;
C_PROBE235_WIDTH : INTEGER;
C_PROBE236_WIDTH : INTEGER;
C_PROBE237_WIDTH : INTEGER;
C_PROBE238_WIDTH : INTEGER;
C_PROBE239_WIDTH : INTEGER;
C_PROBE240_WIDTH : INTEGER;
C_PROBE241_WIDTH : INTEGER;
C_PROBE242_WIDTH : INTEGER;
C_PROBE243_WIDTH : INTEGER;
C_PROBE244_WIDTH : INTEGER;
C_PROBE245_WIDTH : INTEGER;
C_PROBE246_WIDTH : INTEGER;
C_PROBE247_WIDTH : INTEGER;
C_PROBE248_WIDTH : INTEGER;
C_PROBE249_WIDTH : INTEGER;
C_PROBE250_WIDTH : INTEGER;
C_PROBE251_WIDTH : INTEGER;
C_PROBE252_WIDTH : INTEGER;
C_PROBE253_WIDTH : INTEGER;
C_PROBE254_WIDTH : INTEGER;
C_PROBE255_WIDTH : INTEGER;
C_PROBE256_WIDTH : INTEGER;
C_PROBE257_WIDTH : INTEGER;
C_PROBE258_WIDTH : INTEGER;
C_PROBE259_WIDTH : INTEGER;
C_PROBE260_WIDTH : INTEGER;
C_PROBE261_WIDTH : INTEGER;
C_PROBE262_WIDTH : INTEGER;
C_PROBE263_WIDTH : INTEGER;
C_PROBE264_WIDTH : INTEGER;
C_PROBE265_WIDTH : INTEGER;
C_PROBE266_WIDTH : INTEGER;
C_PROBE267_WIDTH : INTEGER;
C_PROBE268_WIDTH : INTEGER;
C_PROBE269_WIDTH : INTEGER;
C_PROBE270_WIDTH : INTEGER;
C_PROBE271_WIDTH : INTEGER;
C_PROBE272_WIDTH : INTEGER;
C_PROBE273_WIDTH : INTEGER;
C_PROBE274_WIDTH : INTEGER;
C_PROBE275_WIDTH : INTEGER;
C_PROBE276_WIDTH : INTEGER;
C_PROBE277_WIDTH : INTEGER;
C_PROBE278_WIDTH : INTEGER;
C_PROBE279_WIDTH : INTEGER;
C_PROBE280_WIDTH : INTEGER;
C_PROBE281_WIDTH : INTEGER;
C_PROBE282_WIDTH : INTEGER;
C_PROBE283_WIDTH : INTEGER;
C_PROBE284_WIDTH : INTEGER;
C_PROBE285_WIDTH : INTEGER;
C_PROBE286_WIDTH : INTEGER;
C_PROBE287_WIDTH : INTEGER;
C_PROBE288_WIDTH : INTEGER;
C_PROBE289_WIDTH : INTEGER;
C_PROBE290_WIDTH : INTEGER;
C_PROBE291_WIDTH : INTEGER;
C_PROBE292_WIDTH : INTEGER;
C_PROBE293_WIDTH : INTEGER;
C_PROBE294_WIDTH : INTEGER;
C_PROBE295_WIDTH : INTEGER;
C_PROBE296_WIDTH : INTEGER;
C_PROBE297_WIDTH : INTEGER;
C_PROBE298_WIDTH : INTEGER;
C_PROBE299_WIDTH : INTEGER;
C_PROBE300_WIDTH : INTEGER;
C_PROBE301_WIDTH : INTEGER;
C_PROBE302_WIDTH : INTEGER;
C_PROBE303_WIDTH : INTEGER;
C_PROBE304_WIDTH : INTEGER;
C_PROBE305_WIDTH : INTEGER;
C_PROBE306_WIDTH : INTEGER;
C_PROBE307_WIDTH : INTEGER;
C_PROBE308_WIDTH : INTEGER;
C_PROBE309_WIDTH : INTEGER;
C_PROBE310_WIDTH : INTEGER;
C_PROBE311_WIDTH : INTEGER;
C_PROBE312_WIDTH : INTEGER;
C_PROBE313_WIDTH : INTEGER;
C_PROBE314_WIDTH : INTEGER;
C_PROBE315_WIDTH : INTEGER;
C_PROBE316_WIDTH : INTEGER;
C_PROBE317_WIDTH : INTEGER;
C_PROBE318_WIDTH : INTEGER;
C_PROBE319_WIDTH : INTEGER;
C_PROBE320_WIDTH : INTEGER;
C_PROBE321_WIDTH : INTEGER;
C_PROBE322_WIDTH : INTEGER;
C_PROBE323_WIDTH : INTEGER;
C_PROBE324_WIDTH : INTEGER;
C_PROBE325_WIDTH : INTEGER;
C_PROBE326_WIDTH : INTEGER;
C_PROBE327_WIDTH : INTEGER;
C_PROBE328_WIDTH : INTEGER;
C_PROBE329_WIDTH : INTEGER;
C_PROBE330_WIDTH : INTEGER;
C_PROBE331_WIDTH : INTEGER;
C_PROBE332_WIDTH : INTEGER;
C_PROBE333_WIDTH : INTEGER;
C_PROBE334_WIDTH : INTEGER;
C_PROBE335_WIDTH : INTEGER;
C_PROBE336_WIDTH : INTEGER;
C_PROBE337_WIDTH : INTEGER;
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C_PROBE1012_WIDTH : INTEGER;
C_PROBE1013_WIDTH : INTEGER;
C_PROBE1014_WIDTH : INTEGER;
C_PROBE1015_WIDTH : INTEGER;
C_PROBE1016_WIDTH : INTEGER;
C_PROBE1017_WIDTH : INTEGER;
C_PROBE1018_WIDTH : INTEGER;
C_PROBE1019_WIDTH : INTEGER;
C_PROBE1020_WIDTH : INTEGER;
C_PROBE1021_WIDTH : INTEGER;
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C_PROBE1023_WIDTH : INTEGER;
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C_PROBE1_MU_CNT : INTEGER;
C_PROBE2_MU_CNT : INTEGER;
C_PROBE3_MU_CNT : INTEGER;
C_PROBE4_MU_CNT : INTEGER;
C_PROBE5_MU_CNT : INTEGER;
C_PROBE6_MU_CNT : INTEGER;
C_PROBE7_MU_CNT : INTEGER;
C_PROBE8_MU_CNT : INTEGER;
C_PROBE9_MU_CNT : INTEGER;
C_PROBE10_MU_CNT : INTEGER;
C_PROBE11_MU_CNT : INTEGER;
C_PROBE12_MU_CNT : INTEGER;
C_PROBE13_MU_CNT : INTEGER;
C_PROBE14_MU_CNT : INTEGER;
C_PROBE15_MU_CNT : INTEGER;
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C_PROBE19_MU_CNT : INTEGER;
C_PROBE20_MU_CNT : INTEGER;
C_PROBE21_MU_CNT : INTEGER;
C_PROBE22_MU_CNT : INTEGER;
C_PROBE23_MU_CNT : INTEGER;
C_PROBE24_MU_CNT : INTEGER;
C_PROBE25_MU_CNT : INTEGER;
C_PROBE26_MU_CNT : INTEGER;
C_PROBE27_MU_CNT : INTEGER;
C_PROBE28_MU_CNT : INTEGER;
C_PROBE29_MU_CNT : INTEGER;
C_PROBE30_MU_CNT : INTEGER;
C_PROBE31_MU_CNT : INTEGER;
C_PROBE32_MU_CNT : INTEGER;
C_PROBE33_MU_CNT : INTEGER;
C_PROBE34_MU_CNT : INTEGER;
C_PROBE35_MU_CNT : INTEGER;
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C_PROBE37_MU_CNT : INTEGER;
C_PROBE38_MU_CNT : INTEGER;
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C_PROBE40_MU_CNT : INTEGER;
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C_PROBE42_MU_CNT : INTEGER;
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C_PROBE44_MU_CNT : INTEGER;
C_PROBE45_MU_CNT : INTEGER;
C_PROBE46_MU_CNT : INTEGER;
C_PROBE47_MU_CNT : INTEGER;
C_PROBE48_MU_CNT : INTEGER;
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C_PROBE50_MU_CNT : INTEGER;
C_PROBE51_MU_CNT : INTEGER;
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C_PROBE53_MU_CNT : INTEGER;
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C_PROBE55_MU_CNT : INTEGER;
C_PROBE56_MU_CNT : INTEGER;
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C_PROBE60_MU_CNT : INTEGER;
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C_PROBE87_MU_CNT : INTEGER;
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C_PROBE90_MU_CNT : INTEGER;
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C_PROBE100_MU_CNT : INTEGER;
C_PROBE101_MU_CNT : INTEGER;
C_PROBE102_MU_CNT : INTEGER;
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C_PROBE105_MU_CNT : INTEGER;
C_PROBE106_MU_CNT : INTEGER;
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C_PROBE110_MU_CNT : INTEGER;
C_PROBE111_MU_CNT : INTEGER;
C_PROBE112_MU_CNT : INTEGER;
C_PROBE113_MU_CNT : INTEGER;
C_PROBE114_MU_CNT : INTEGER;
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C_PROBE120_MU_CNT : INTEGER;
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C_PROBE123_MU_CNT : INTEGER;
C_PROBE124_MU_CNT : INTEGER;
C_PROBE125_MU_CNT : INTEGER;
C_PROBE126_MU_CNT : INTEGER;
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C_PROBE145_MU_CNT : INTEGER;
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C_PROBE148_MU_CNT : INTEGER;
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C_PROBE150_MU_CNT : INTEGER;
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C_PROBE162_MU_CNT : INTEGER;
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C_PROBE187_MU_CNT : INTEGER;
C_PROBE188_MU_CNT : INTEGER;
C_PROBE189_MU_CNT : INTEGER;
C_PROBE190_MU_CNT : INTEGER;
C_PROBE191_MU_CNT : INTEGER;
C_PROBE192_MU_CNT : INTEGER;
C_PROBE193_MU_CNT : INTEGER;
C_PROBE194_MU_CNT : INTEGER;
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C_PROBE198_MU_CNT : INTEGER;
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C_PROBE200_MU_CNT : INTEGER;
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C_PROBE202_MU_CNT : INTEGER;
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C_PROBE205_MU_CNT : INTEGER;
C_PROBE206_MU_CNT : INTEGER;
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C_PROBE249_MU_CNT : INTEGER;
C_PROBE250_MU_CNT : INTEGER;
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C_PROBE255_MU_CNT : INTEGER;
C_PROBE256_MU_CNT : INTEGER;
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C_PROBE261_MU_CNT : INTEGER;
C_PROBE262_MU_CNT : INTEGER;
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C_PROBE265_MU_CNT : INTEGER;
C_PROBE266_MU_CNT : INTEGER;
C_PROBE267_MU_CNT : INTEGER;
C_PROBE268_MU_CNT : INTEGER;
C_PROBE269_MU_CNT : INTEGER;
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C_PROBE276_MU_CNT : INTEGER;
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C_PROBE279_MU_CNT : INTEGER;
C_PROBE280_MU_CNT : INTEGER;
C_PROBE281_MU_CNT : INTEGER;
C_PROBE282_MU_CNT : INTEGER;
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C_PROBE285_MU_CNT : INTEGER;
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C_PROBE287_MU_CNT : INTEGER;
C_PROBE288_MU_CNT : INTEGER;
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C_PROBE290_MU_CNT : INTEGER;
C_PROBE291_MU_CNT : INTEGER;
C_PROBE292_MU_CNT : INTEGER;
C_PROBE293_MU_CNT : INTEGER;
C_PROBE294_MU_CNT : INTEGER;
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C_PROBE299_MU_CNT : INTEGER;
C_PROBE300_MU_CNT : INTEGER;
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C_PROBE302_MU_CNT : INTEGER;
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C_PROBE305_MU_CNT : INTEGER;
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C_PROBE318_MU_CNT : INTEGER;
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C_PROBE320_MU_CNT : INTEGER;
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C_PROBE323_MU_CNT : INTEGER;
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C_PROBE340_MU_CNT : INTEGER;
C_PROBE341_MU_CNT : INTEGER;
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C_PROBE344_MU_CNT : INTEGER;
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C_PROBE348_MU_CNT : INTEGER;
C_PROBE349_MU_CNT : INTEGER;
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C_PROBE351_MU_CNT : INTEGER;
C_PROBE352_MU_CNT : INTEGER;
C_PROBE353_MU_CNT : INTEGER;
C_PROBE354_MU_CNT : INTEGER;
C_PROBE355_MU_CNT : INTEGER;
C_PROBE356_MU_CNT : INTEGER;
C_PROBE357_MU_CNT : INTEGER;
C_PROBE358_MU_CNT : INTEGER;
C_PROBE359_MU_CNT : INTEGER;
C_PROBE360_MU_CNT : INTEGER;
C_PROBE361_MU_CNT : INTEGER;
C_PROBE362_MU_CNT : INTEGER;
C_PROBE363_MU_CNT : INTEGER;
C_PROBE364_MU_CNT : INTEGER;
C_PROBE365_MU_CNT : INTEGER;
C_PROBE366_MU_CNT : INTEGER;
C_PROBE367_MU_CNT : INTEGER;
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C_PROBE369_MU_CNT : INTEGER;
C_PROBE370_MU_CNT : INTEGER;
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C_PROBE373_MU_CNT : INTEGER;
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C_PROBE375_MU_CNT : INTEGER;
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C_PROBE377_MU_CNT : INTEGER;
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C_PROBE380_MU_CNT : INTEGER;
C_PROBE381_MU_CNT : INTEGER;
C_PROBE382_MU_CNT : INTEGER;
C_PROBE383_MU_CNT : INTEGER;
C_PROBE384_MU_CNT : INTEGER;
C_PROBE385_MU_CNT : INTEGER;
C_PROBE386_MU_CNT : INTEGER;
C_PROBE387_MU_CNT : INTEGER;
C_PROBE388_MU_CNT : INTEGER;
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C_PROBE390_MU_CNT : INTEGER;
C_PROBE391_MU_CNT : INTEGER;
C_PROBE392_MU_CNT : INTEGER;
C_PROBE393_MU_CNT : INTEGER;
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C_PROBE395_MU_CNT : INTEGER;
C_PROBE396_MU_CNT : INTEGER;
C_PROBE397_MU_CNT : INTEGER;
C_PROBE398_MU_CNT : INTEGER;
C_PROBE399_MU_CNT : INTEGER;
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C_PROBE416_MU_CNT : INTEGER;
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C_PROBE420_MU_CNT : INTEGER;
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C_PROBE422_MU_CNT : INTEGER;
C_PROBE423_MU_CNT : INTEGER;
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C_PROBE427_MU_CNT : INTEGER;
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C_PROBE430_MU_CNT : INTEGER;
C_PROBE431_MU_CNT : INTEGER;
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C_PROBE433_MU_CNT : INTEGER;
C_PROBE434_MU_CNT : INTEGER;
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C_PROBE436_MU_CNT : INTEGER;
C_PROBE437_MU_CNT : INTEGER;
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C_PROBE439_MU_CNT : INTEGER;
C_PROBE440_MU_CNT : INTEGER;
C_PROBE441_MU_CNT : INTEGER;
C_PROBE442_MU_CNT : INTEGER;
C_PROBE443_MU_CNT : INTEGER;
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C_PROBE445_MU_CNT : INTEGER;
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C_PROBE447_MU_CNT : INTEGER;
C_PROBE448_MU_CNT : INTEGER;
C_PROBE449_MU_CNT : INTEGER;
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C_PROBE451_MU_CNT : INTEGER;
C_PROBE452_MU_CNT : INTEGER;
C_PROBE453_MU_CNT : INTEGER;
C_PROBE454_MU_CNT : INTEGER;
C_PROBE455_MU_CNT : INTEGER;
C_PROBE456_MU_CNT : INTEGER;
C_PROBE457_MU_CNT : INTEGER;
C_PROBE458_MU_CNT : INTEGER;
C_PROBE459_MU_CNT : INTEGER;
C_PROBE460_MU_CNT : INTEGER;
C_PROBE461_MU_CNT : INTEGER;
C_PROBE462_MU_CNT : INTEGER;
C_PROBE463_MU_CNT : INTEGER;
C_PROBE464_MU_CNT : INTEGER;
C_PROBE465_MU_CNT : INTEGER;
C_PROBE466_MU_CNT : INTEGER;
C_PROBE467_MU_CNT : INTEGER;
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C_PROBE469_MU_CNT : INTEGER;
C_PROBE470_MU_CNT : INTEGER;
C_PROBE471_MU_CNT : INTEGER;
C_PROBE472_MU_CNT : INTEGER;
C_PROBE473_MU_CNT : INTEGER;
C_PROBE474_MU_CNT : INTEGER;
C_PROBE475_MU_CNT : INTEGER;
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C_PROBE477_MU_CNT : INTEGER;
C_PROBE478_MU_CNT : INTEGER;
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C_PROBE480_MU_CNT : INTEGER;
C_PROBE481_MU_CNT : INTEGER;
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C_PROBE484_MU_CNT : INTEGER;
C_PROBE485_MU_CNT : INTEGER;
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C_PROBE487_MU_CNT : INTEGER;
C_PROBE488_MU_CNT : INTEGER;
C_PROBE489_MU_CNT : INTEGER;
C_PROBE490_MU_CNT : INTEGER;
C_PROBE491_MU_CNT : INTEGER;
C_PROBE492_MU_CNT : INTEGER;
C_PROBE493_MU_CNT : INTEGER;
C_PROBE494_MU_CNT : INTEGER;
C_PROBE495_MU_CNT : INTEGER;
C_PROBE496_MU_CNT : INTEGER;
C_PROBE497_MU_CNT : INTEGER;
C_PROBE498_MU_CNT : INTEGER;
C_PROBE499_MU_CNT : INTEGER;
C_PROBE500_MU_CNT : INTEGER;
C_PROBE501_MU_CNT : INTEGER;
C_PROBE502_MU_CNT : INTEGER;
C_PROBE503_MU_CNT : INTEGER;
C_PROBE504_MU_CNT : INTEGER;
C_PROBE505_MU_CNT : INTEGER;
C_PROBE506_MU_CNT : INTEGER;
C_PROBE507_MU_CNT : INTEGER;
C_PROBE508_MU_CNT : INTEGER;
C_PROBE509_MU_CNT : INTEGER;
C_PROBE510_MU_CNT : INTEGER;
C_PROBE511_MU_CNT : INTEGER;
C_PROBE512_MU_CNT : INTEGER;
C_PROBE513_MU_CNT : INTEGER;
C_PROBE514_MU_CNT : INTEGER;
C_PROBE515_MU_CNT : INTEGER;
C_PROBE516_MU_CNT : INTEGER;
C_PROBE517_MU_CNT : INTEGER;
C_PROBE518_MU_CNT : INTEGER;
C_PROBE519_MU_CNT : INTEGER;
C_PROBE520_MU_CNT : INTEGER;
C_PROBE521_MU_CNT : INTEGER;
C_PROBE522_MU_CNT : INTEGER;
C_PROBE523_MU_CNT : INTEGER;
C_PROBE524_MU_CNT : INTEGER;
C_PROBE525_MU_CNT : INTEGER;
C_PROBE526_MU_CNT : INTEGER;
C_PROBE527_MU_CNT : INTEGER;
C_PROBE528_MU_CNT : INTEGER;
C_PROBE529_MU_CNT : INTEGER;
C_PROBE530_MU_CNT : INTEGER;
C_PROBE531_MU_CNT : INTEGER;
C_PROBE532_MU_CNT : INTEGER;
C_PROBE533_MU_CNT : INTEGER;
C_PROBE534_MU_CNT : INTEGER;
C_PROBE535_MU_CNT : INTEGER;
C_PROBE536_MU_CNT : INTEGER;
C_PROBE537_MU_CNT : INTEGER;
C_PROBE538_MU_CNT : INTEGER;
C_PROBE539_MU_CNT : INTEGER;
C_PROBE540_MU_CNT : INTEGER;
C_PROBE541_MU_CNT : INTEGER;
C_PROBE542_MU_CNT : INTEGER;
C_PROBE543_MU_CNT : INTEGER;
C_PROBE544_MU_CNT : INTEGER;
C_PROBE545_MU_CNT : INTEGER;
C_PROBE546_MU_CNT : INTEGER;
C_PROBE547_MU_CNT : INTEGER;
C_PROBE548_MU_CNT : INTEGER;
C_PROBE549_MU_CNT : INTEGER;
C_PROBE550_MU_CNT : INTEGER;
C_PROBE551_MU_CNT : INTEGER;
C_PROBE552_MU_CNT : INTEGER;
C_PROBE553_MU_CNT : INTEGER;
C_PROBE554_MU_CNT : INTEGER;
C_PROBE555_MU_CNT : INTEGER;
C_PROBE556_MU_CNT : INTEGER;
C_PROBE557_MU_CNT : INTEGER;
C_PROBE558_MU_CNT : INTEGER;
C_PROBE559_MU_CNT : INTEGER;
C_PROBE560_MU_CNT : INTEGER;
C_PROBE561_MU_CNT : INTEGER;
C_PROBE562_MU_CNT : INTEGER;
C_PROBE563_MU_CNT : INTEGER;
C_PROBE564_MU_CNT : INTEGER;
C_PROBE565_MU_CNT : INTEGER;
C_PROBE566_MU_CNT : INTEGER;
C_PROBE567_MU_CNT : INTEGER;
C_PROBE568_MU_CNT : INTEGER;
C_PROBE569_MU_CNT : INTEGER;
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C_PROBE608_MU_CNT : INTEGER;
C_PROBE609_MU_CNT : INTEGER;
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C_PROBE813_TYPE : INTEGER;
C_PROBE814_TYPE : INTEGER;
C_PROBE815_TYPE : INTEGER;
C_PROBE816_TYPE : INTEGER;
C_PROBE817_TYPE : INTEGER;
C_PROBE818_TYPE : INTEGER;
C_PROBE819_TYPE : INTEGER;
C_PROBE820_TYPE : INTEGER;
C_PROBE821_TYPE : INTEGER;
C_PROBE822_TYPE : INTEGER;
C_PROBE823_TYPE : INTEGER;
C_PROBE824_TYPE : INTEGER;
C_PROBE825_TYPE : INTEGER;
C_PROBE826_TYPE : INTEGER;
C_PROBE827_TYPE : INTEGER;
C_PROBE828_TYPE : INTEGER;
C_PROBE829_TYPE : INTEGER;
C_PROBE830_TYPE : INTEGER;
C_PROBE831_TYPE : INTEGER;
C_PROBE832_TYPE : INTEGER;
C_PROBE833_TYPE : INTEGER;
C_PROBE834_TYPE : INTEGER;
C_PROBE835_TYPE : INTEGER;
C_PROBE836_TYPE : INTEGER;
C_PROBE837_TYPE : INTEGER;
C_PROBE838_TYPE : INTEGER;
C_PROBE839_TYPE : INTEGER;
C_PROBE840_TYPE : INTEGER;
C_PROBE841_TYPE : INTEGER;
C_PROBE842_TYPE : INTEGER;
C_PROBE843_TYPE : INTEGER;
C_PROBE844_TYPE : INTEGER;
C_PROBE845_TYPE : INTEGER;
C_PROBE846_TYPE : INTEGER;
C_PROBE847_TYPE : INTEGER;
C_PROBE848_TYPE : INTEGER;
C_PROBE849_TYPE : INTEGER;
C_PROBE850_TYPE : INTEGER;
C_PROBE851_TYPE : INTEGER;
C_PROBE852_TYPE : INTEGER;
C_PROBE853_TYPE : INTEGER;
C_PROBE854_TYPE : INTEGER;
C_PROBE855_TYPE : INTEGER;
C_PROBE856_TYPE : INTEGER;
C_PROBE857_TYPE : INTEGER;
C_PROBE858_TYPE : INTEGER;
C_PROBE859_TYPE : INTEGER;
C_PROBE860_TYPE : INTEGER;
C_PROBE861_TYPE : INTEGER;
C_PROBE862_TYPE : INTEGER;
C_PROBE863_TYPE : INTEGER;
C_PROBE864_TYPE : INTEGER;
C_PROBE865_TYPE : INTEGER;
C_PROBE866_TYPE : INTEGER;
C_PROBE867_TYPE : INTEGER;
C_PROBE868_TYPE : INTEGER;
C_PROBE869_TYPE : INTEGER;
C_PROBE870_TYPE : INTEGER;
C_PROBE871_TYPE : INTEGER;
C_PROBE872_TYPE : INTEGER;
C_PROBE873_TYPE : INTEGER;
C_PROBE874_TYPE : INTEGER;
C_PROBE875_TYPE : INTEGER;
C_PROBE876_TYPE : INTEGER;
C_PROBE877_TYPE : INTEGER;
C_PROBE878_TYPE : INTEGER;
C_PROBE879_TYPE : INTEGER;
C_PROBE880_TYPE : INTEGER;
C_PROBE881_TYPE : INTEGER;
C_PROBE882_TYPE : INTEGER;
C_PROBE883_TYPE : INTEGER;
C_PROBE884_TYPE : INTEGER;
C_PROBE885_TYPE : INTEGER;
C_PROBE886_TYPE : INTEGER;
C_PROBE887_TYPE : INTEGER;
C_PROBE888_TYPE : INTEGER;
C_PROBE889_TYPE : INTEGER;
C_PROBE890_TYPE : INTEGER;
C_PROBE891_TYPE : INTEGER;
C_PROBE892_TYPE : INTEGER;
C_PROBE893_TYPE : INTEGER;
C_PROBE894_TYPE : INTEGER;
C_PROBE895_TYPE : INTEGER;
C_PROBE896_TYPE : INTEGER;
C_PROBE897_TYPE : INTEGER;
C_PROBE898_TYPE : INTEGER;
C_PROBE899_TYPE : INTEGER;
C_PROBE900_TYPE : INTEGER;
C_PROBE901_TYPE : INTEGER;
C_PROBE902_TYPE : INTEGER;
C_PROBE903_TYPE : INTEGER;
C_PROBE904_TYPE : INTEGER;
C_PROBE905_TYPE : INTEGER;
C_PROBE906_TYPE : INTEGER;
C_PROBE907_TYPE : INTEGER;
C_PROBE908_TYPE : INTEGER;
C_PROBE909_TYPE : INTEGER;
C_PROBE910_TYPE : INTEGER;
C_PROBE911_TYPE : INTEGER;
C_PROBE912_TYPE : INTEGER;
C_PROBE913_TYPE : INTEGER;
C_PROBE914_TYPE : INTEGER;
C_PROBE915_TYPE : INTEGER;
C_PROBE916_TYPE : INTEGER;
C_PROBE917_TYPE : INTEGER;
C_PROBE918_TYPE : INTEGER;
C_PROBE919_TYPE : INTEGER;
C_PROBE920_TYPE : INTEGER;
C_PROBE921_TYPE : INTEGER;
C_PROBE922_TYPE : INTEGER;
C_PROBE923_TYPE : INTEGER;
C_PROBE924_TYPE : INTEGER;
C_PROBE925_TYPE : INTEGER;
C_PROBE926_TYPE : INTEGER;
C_PROBE927_TYPE : INTEGER;
C_PROBE928_TYPE : INTEGER;
C_PROBE929_TYPE : INTEGER;
C_PROBE930_TYPE : INTEGER;
C_PROBE931_TYPE : INTEGER;
C_PROBE932_TYPE : INTEGER;
C_PROBE933_TYPE : INTEGER;
C_PROBE934_TYPE : INTEGER;
C_PROBE935_TYPE : INTEGER;
C_PROBE936_TYPE : INTEGER;
C_PROBE937_TYPE : INTEGER;
C_PROBE938_TYPE : INTEGER;
C_PROBE939_TYPE : INTEGER;
C_PROBE940_TYPE : INTEGER;
C_PROBE941_TYPE : INTEGER;
C_PROBE942_TYPE : INTEGER;
C_PROBE943_TYPE : INTEGER;
C_PROBE944_TYPE : INTEGER;
C_PROBE945_TYPE : INTEGER;
C_PROBE946_TYPE : INTEGER;
C_PROBE947_TYPE : INTEGER;
C_PROBE948_TYPE : INTEGER;
C_PROBE949_TYPE : INTEGER;
C_PROBE950_TYPE : INTEGER;
C_PROBE951_TYPE : INTEGER;
C_PROBE952_TYPE : INTEGER;
C_PROBE953_TYPE : INTEGER;
C_PROBE954_TYPE : INTEGER;
C_PROBE955_TYPE : INTEGER;
C_PROBE956_TYPE : INTEGER;
C_PROBE957_TYPE : INTEGER;
C_PROBE958_TYPE : INTEGER;
C_PROBE959_TYPE : INTEGER;
C_PROBE960_TYPE : INTEGER;
C_PROBE961_TYPE : INTEGER;
C_PROBE962_TYPE : INTEGER;
C_PROBE963_TYPE : INTEGER;
C_PROBE964_TYPE : INTEGER;
C_PROBE965_TYPE : INTEGER;
C_PROBE966_TYPE : INTEGER;
C_PROBE967_TYPE : INTEGER;
C_PROBE968_TYPE : INTEGER;
C_PROBE969_TYPE : INTEGER;
C_PROBE970_TYPE : INTEGER;
C_PROBE971_TYPE : INTEGER;
C_PROBE972_TYPE : INTEGER;
C_PROBE973_TYPE : INTEGER;
C_PROBE974_TYPE : INTEGER;
C_PROBE975_TYPE : INTEGER;
C_PROBE976_TYPE : INTEGER;
C_PROBE977_TYPE : INTEGER;
C_PROBE978_TYPE : INTEGER;
C_PROBE979_TYPE : INTEGER;
C_PROBE980_TYPE : INTEGER;
C_PROBE981_TYPE : INTEGER;
C_PROBE982_TYPE : INTEGER;
C_PROBE983_TYPE : INTEGER;
C_PROBE984_TYPE : INTEGER;
C_PROBE985_TYPE : INTEGER;
C_PROBE986_TYPE : INTEGER;
C_PROBE987_TYPE : INTEGER;
C_PROBE988_TYPE : INTEGER;
C_PROBE989_TYPE : INTEGER;
C_PROBE990_TYPE : INTEGER;
C_PROBE991_TYPE : INTEGER;
C_PROBE992_TYPE : INTEGER;
C_PROBE993_TYPE : INTEGER;
C_PROBE994_TYPE : INTEGER;
C_PROBE995_TYPE : INTEGER;
C_PROBE996_TYPE : INTEGER;
C_PROBE997_TYPE : INTEGER;
C_PROBE998_TYPE : INTEGER;
C_PROBE999_TYPE : INTEGER;
C_PROBE1000_TYPE : INTEGER;
C_PROBE1001_TYPE : INTEGER;
C_PROBE1002_TYPE : INTEGER;
C_PROBE1003_TYPE : INTEGER;
C_PROBE1004_TYPE : INTEGER;
C_PROBE1005_TYPE : INTEGER;
C_PROBE1006_TYPE : INTEGER;
C_PROBE1007_TYPE : INTEGER;
C_PROBE1008_TYPE : INTEGER;
C_PROBE1009_TYPE : INTEGER;
C_PROBE1010_TYPE : INTEGER;
C_PROBE1011_TYPE : INTEGER;
C_PROBE1012_TYPE : INTEGER;
C_PROBE1013_TYPE : INTEGER;
C_PROBE1014_TYPE : INTEGER;
C_PROBE1015_TYPE : INTEGER;
C_PROBE1016_TYPE : INTEGER;
C_PROBE1017_TYPE : INTEGER;
C_PROBE1018_TYPE : INTEGER;
C_PROBE1019_TYPE : INTEGER;
C_PROBE1020_TYPE : INTEGER;
C_PROBE1021_TYPE : INTEGER;
C_PROBE1022_TYPE : INTEGER;
C_PROBE1023_TYPE : INTEGER
);
PORT (
clk : IN STD_LOGIC;
sl_iport0 : IN STD_LOGIC_VECTOR (36 downto 0);
sl_oport0 : OUT STD_LOGIC_VECTOR (16 downto 0);
trig_in : IN STD_LOGIC;
trig_in_ack : OUT STD_LOGIC;
trig_out : OUT STD_LOGIC;
trig_out_ack : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe32 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe33 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe34 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe35 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe36 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe37 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe38 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe39 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe40 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe41 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe42 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe43 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe44 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe45 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe46 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe47 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe48 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe49 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe50 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe51 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe52 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe53 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe54 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe55 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe56 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe57 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe58 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe59 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe60 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe61 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe62 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe63 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe64 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe65 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe66 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe67 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe68 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe69 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe70 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe71 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe72 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe73 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe74 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe75 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe76 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe77 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe78 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe79 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe80 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe81 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe82 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe83 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe84 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe85 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe86 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe87 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe88 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe89 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe90 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe91 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe92 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe93 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe94 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe95 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe96 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe97 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe98 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe99 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe100 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe101 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe102 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe103 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe104 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe105 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe106 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe107 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe108 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe109 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe110 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe111 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe112 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe113 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe114 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe115 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe116 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe117 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe118 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe119 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe120 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe121 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe122 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe123 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe124 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe125 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe126 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe127 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe128 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe129 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe130 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe131 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe132 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe133 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe134 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe135 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe136 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe137 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe138 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe139 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe140 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe141 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe142 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe143 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe144 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe145 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe146 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe147 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe148 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe149 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe150 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe151 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe152 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe153 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe154 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe155 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe156 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe157 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe158 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe159 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe160 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe161 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe162 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe163 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe164 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe165 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe166 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe167 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe168 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe169 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe170 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe171 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe172 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe173 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe174 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe175 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe176 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe177 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe178 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe179 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe180 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe181 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe182 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe183 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe184 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe185 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe186 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe187 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe188 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe189 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe190 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe191 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe192 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe193 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe194 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe195 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe196 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe197 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe198 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe199 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe200 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe201 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe202 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe203 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe204 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe205 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe206 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe207 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe208 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe209 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe210 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe211 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe212 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe213 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe214 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe215 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe216 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe217 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe218 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe219 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe220 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe221 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe222 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe223 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe224 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe225 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe226 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe227 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe228 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe229 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe230 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe231 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe232 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe233 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe234 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe235 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe236 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe237 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe238 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe239 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe240 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe241 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe242 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe243 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe244 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe245 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe246 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe247 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe248 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe249 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe250 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe251 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe252 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe253 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe254 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe255 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe256 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe257 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe258 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe259 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe260 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe261 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe262 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe263 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe264 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe265 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe266 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe267 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe268 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe269 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe270 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe271 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe272 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe273 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe274 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe275 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe276 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe277 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe278 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe279 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe280 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe281 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe282 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe283 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe284 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe285 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe286 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe287 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe288 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe289 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe290 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe291 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe292 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe293 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe294 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe295 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe296 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe297 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe298 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe299 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe300 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe301 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe302 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe303 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe304 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe305 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe306 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe307 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe308 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe309 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe310 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe311 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe312 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe313 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe314 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe315 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe316 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe317 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe318 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe319 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe320 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe321 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe322 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe323 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe324 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe325 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe326 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe327 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe328 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe329 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe330 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe331 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe332 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe333 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe334 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe335 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe336 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe337 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe338 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe339 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe340 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe341 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe342 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe343 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe344 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe345 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe346 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe347 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe348 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe349 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe350 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe351 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe352 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe353 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe354 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe355 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe356 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe357 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe358 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe359 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe360 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe361 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe362 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe363 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe364 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe365 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe366 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe367 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe368 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe369 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe370 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe371 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe372 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe373 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe374 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe375 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe376 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe377 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe378 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe379 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe380 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe381 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe382 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe383 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe384 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe385 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe386 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe387 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe388 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe389 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe390 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe391 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe392 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe393 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe394 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe395 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe396 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe397 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe398 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe399 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe400 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe401 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe402 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe403 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe404 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe405 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe406 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe407 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe408 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe409 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe410 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe411 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe412 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe413 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe414 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe415 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe416 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe417 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe418 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe419 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe420 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe421 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe422 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe423 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe424 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe425 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe426 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe427 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe428 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe429 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe430 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe431 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe432 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe433 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe434 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe435 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe436 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe437 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe438 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe439 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe440 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe441 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe442 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe443 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe444 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe445 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe446 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe447 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe448 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe449 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe450 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe451 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe452 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe453 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe454 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe455 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe456 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe457 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe458 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe459 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe460 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe461 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe462 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe463 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe464 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe465 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe466 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe467 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe468 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe469 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe470 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe471 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe472 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe473 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe474 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe475 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe476 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe477 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe478 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe479 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe480 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe481 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe482 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe483 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe484 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe485 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe486 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe487 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe488 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe489 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe490 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe491 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe492 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe493 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe494 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe495 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe496 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe497 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe498 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe499 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe500 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe501 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe502 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe503 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe504 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe505 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe506 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe507 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe508 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe509 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe510 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe511 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe512 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe513 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe514 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe515 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe516 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe517 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe518 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe519 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe520 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe521 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe522 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe523 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe524 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe525 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe526 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe527 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe528 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe529 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe530 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe531 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe532 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe533 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe534 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe535 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe536 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe537 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe538 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe539 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe540 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe541 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe542 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe543 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe544 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe545 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe546 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe547 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe548 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe549 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe550 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe551 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe552 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe553 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe554 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe555 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe556 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe557 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe558 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe559 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe560 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe561 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe562 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe563 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe564 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe565 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe566 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe567 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe568 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe569 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe570 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe571 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe572 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe573 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe574 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe575 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe576 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe577 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe578 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe579 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe580 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe581 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe582 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe583 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe584 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe585 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe586 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe587 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe588 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe589 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe590 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe591 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe592 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe593 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe594 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe595 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe596 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe597 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe598 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe599 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe600 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe601 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe602 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe603 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe604 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe605 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe606 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe607 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe608 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe609 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe610 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe611 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe612 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe613 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe614 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe615 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe616 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe617 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe618 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe619 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe620 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe621 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe622 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe623 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe624 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe625 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe626 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe627 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe628 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe629 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe630 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe631 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe632 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe633 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe634 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe635 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe636 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe637 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe638 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe639 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe640 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe641 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe642 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe643 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe644 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe645 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe646 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe647 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe648 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe649 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe650 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe651 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe652 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe653 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe654 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe655 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe656 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe657 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe658 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe659 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe660 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe661 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe662 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe663 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe664 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe665 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe666 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe667 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe668 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe669 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe670 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe671 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe672 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe673 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe674 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe675 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe676 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe677 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe678 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe679 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe680 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe681 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe682 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe683 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe684 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe685 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe686 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe687 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe688 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe689 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe690 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe691 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe692 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe693 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe694 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe695 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe696 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe697 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe698 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe699 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe700 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe701 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe702 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe703 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe704 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe705 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe706 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe707 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe708 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe709 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe710 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe711 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe712 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe713 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe714 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe715 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe716 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe717 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe718 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe719 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe720 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe721 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe722 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe723 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe724 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe725 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe726 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe727 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe728 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe729 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe730 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe731 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe732 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe733 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe734 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe735 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe736 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe737 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe738 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe739 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe740 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe741 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe742 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe743 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe744 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe745 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe746 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe747 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe748 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe749 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe750 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe751 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe752 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe753 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe754 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe755 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe756 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe757 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe758 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe759 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe760 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe761 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe762 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe763 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe764 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe765 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe766 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe767 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe768 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe769 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe770 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe771 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe772 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe773 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe774 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe775 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe776 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe777 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe778 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe779 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe780 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe781 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe782 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe783 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe784 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe785 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe786 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe787 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe788 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe789 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe790 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe791 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe792 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe793 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe794 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe795 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe796 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe797 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe798 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe799 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe800 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe801 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe802 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe803 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe804 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe805 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe806 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe807 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe808 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe809 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe810 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe811 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe812 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe813 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe814 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe815 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe816 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe817 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe818 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe819 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe820 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe821 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe822 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe823 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe824 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe825 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe826 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe827 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe828 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe829 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe830 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe831 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe832 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe833 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe834 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe835 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe836 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe837 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe838 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe839 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe840 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe841 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe842 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe843 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe844 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe845 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe846 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe847 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe848 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe849 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe850 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe851 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe852 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe853 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe854 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe855 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe856 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe857 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe858 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe859 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe860 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe861 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe862 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe863 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe864 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe865 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe866 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe867 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe868 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe869 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe870 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe871 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe872 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe873 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe874 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe875 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe876 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe877 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe878 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe879 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe880 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe881 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe882 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe883 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe884 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe885 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe886 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe887 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe888 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe889 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe890 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe891 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe892 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe893 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe894 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe895 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe896 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe897 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe898 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe899 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe900 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe901 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe902 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe903 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe904 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe905 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe906 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe907 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe908 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe909 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe910 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe911 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe912 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe913 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe914 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe915 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe916 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe917 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe918 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe919 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe920 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe921 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe922 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe923 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe924 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe925 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe926 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe927 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe928 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe929 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe930 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe931 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe932 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe933 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe934 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe935 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe936 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe937 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe938 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe939 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe940 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe941 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe942 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe943 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe944 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe945 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe946 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe947 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe948 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe949 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe950 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe951 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe952 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe953 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe954 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe955 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe956 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe957 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe958 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe959 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe960 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe961 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe962 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe963 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe964 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe965 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe966 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe967 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe968 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe969 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe970 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe971 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe972 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe973 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe974 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe975 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe976 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe977 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe978 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe979 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe980 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe981 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe982 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe983 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe984 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe985 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe986 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe987 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe988 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe989 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe990 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe991 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe992 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe993 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe994 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe995 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe996 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe997 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe998 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe999 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1000 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1001 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1002 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1003 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1004 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1005 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1006 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1007 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1008 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1009 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1010 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1011 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1012 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1013 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1014 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1015 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1016 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1017 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1018 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1019 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1020 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1021 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1022 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1023 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ila_v6_1_0_ila;
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ila_0_0_arch : ARCHITECTURE IS "yes";
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_ila_0_0_arch : ARCHITECTURE IS "ila,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ila_0_0_arch : ARCHITECTURE IS "design_1_ila_0_0,ila_v6_1_0_ila,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_ila_0_0_arch : ARCHITECTURE IS "design_1_ila_0_0,ila,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.1,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=9,C_DATA_DEPTH=1024,C_MAJOR_VERSION=2016,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=1,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=1,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=1,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=2,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=8,C_PROBE2_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=2,C_PROBE6_WIDTH=1,C_PROBE7_WIDTH=6,C_PROBE8_WIDTH=5,C_PROBE9_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,"&
"C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,"&
"C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,"&
"C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,C_PROBE354_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE356_WIDTH=1,"&
"C_PROBE357_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE368_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE371_WIDTH=1,C_PROBE372_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE394_WIDTH=1,C_PROBE395_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE397_WIDTH=1,C_PROBE398_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE424_WIDTH=1,C_PROBE425_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE447_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE450_WIDTH=1,C_PROBE451_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE453_WIDTH=1,C_PROBE454_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE456_WIDTH=1,"&
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"C_PROBE957_WIDTH=1,C_PROBE958_WIDTH=1,C_PROBE959_WIDTH=1,C_PROBE960_WIDTH=1,C_PROBE961_WIDTH=1,C_PROBE962_WIDTH=1,C_PROBE963_WIDTH=1,C_PROBE964_WIDTH=1,C_PROBE965_WIDTH=1,C_PROBE966_WIDTH=1,C_PROBE967_WIDTH=1,C_PROBE968_WIDTH=1,C_PROBE969_WIDTH=1,C_PROBE970_WIDTH=1,C_PROBE971_WIDTH=1,C_PROBE972_WIDTH=1,C_PROBE973_WIDTH=1,C_PROBE974_WIDTH=1,C_PROBE975_WIDTH=1,C_PROBE976_WIDTH=1,C_PROBE977_WIDTH=1,C_PROBE978_WIDTH=1,C_PROBE979_WIDTH=1,C_PROBE980_WIDTH=1,C_PROBE981_WIDTH=1,C_PROBE982_WIDTH=1,C_PROBE983_WIDTH=1,C_PROBE984_WIDTH=1,C_PROBE985_WIDTH=1,C_PROBE986_WIDTH=1,C_PROBE987_WIDTH=1,C_PROBE988_WIDTH=1,C_PROBE989_WIDTH=1,C_PROBE990_WIDTH=1,C_PROBE991_WIDTH=1,C_PROBE992_WIDTH=1,C_PROBE993_WIDTH=1,C_PROBE994_WIDTH=1,C_PROBE995_WIDTH=1,C_PROBE996_WIDTH=1,C_PROBE997_WIDTH=1,C_PROBE998_WIDTH=1,C_PROBE999_WIDTH=1,C_PROBE1000_WIDTH=1,C_PROBE1001_WIDTH=1,C_PROBE1002_WIDTH=1,C_PROBE1003_WIDTH=1,C_PROBE1004_WIDTH=1,C_PROBE1005_WIDTH=1,C_PROBE1006_WIDTH=1,C_PROBE1007_WIDTH=1,C_PROBE1008_WIDTH=1,C_PROBE1009_WIDTH=1,C_PROBE1010_WIDTH=1,C_PROBE1011_WIDTH=1,C_PROBE1012_WIDTH=1,C_PROBE1013_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=2,C_PROBE1_MU_CNT=2,C_PROBE2_MU_CNT=2,C_PROBE3_MU_CNT=2,C_PROBE4_MU_CNT=2,C_PROBE5_MU_CNT=2,C_PROBE6_MU_CNT=2,C_PROBE7_MU_CNT=2,C_PROBE8_MU_CNT=2,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,"&
"C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,"&
"C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,"&
"C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,"&
"C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,"&
"C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,"&
"C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,"&
"C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,"&
"C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,"&
"C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,"&
"C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,C_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,"&
"C_PROBE9_TYPE=1,C_PROBE10_TYPE=1,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,C_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,"&
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"C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,C_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,"&
"C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1},";
attribute syn_noprune : boolean;
attribute syn_noprune of U0 : label is true;
SIGNAL sl_iport0 : STD_LOGIC_VECTOR (36 downto 0);
SIGNAL sl_oport0 : STD_LOGIC_VECTOR (16 downto 0);
BEGIN
U0 : ila_v6_1_0_ila
GENERIC MAP (
C_XLNX_HW_PROBE_INFO => "DEFAULT",
C_XDEVICEFAMILY => "zynq",
C_CORE_TYPE => 1,
C_CORE_INFO1 => 0,
C_CORE_INFO2 => 0,
C_CAPTURE_TYPE => 0,
C_MU_TYPE => 0,
C_TC_TYPE => 0,
C_NUM_OF_PROBES => 9,
C_DATA_DEPTH => 1024,
C_MAJOR_VERSION => 2016,
C_MINOR_VERSION => 1,
C_BUILD_REVISION => 0,
C_CORE_MAJOR_VER => 6,
C_CORE_MINOR_VER => 1,
C_XSDB_SLAVE_TYPE => 17,
C_NEXT_SLAVE => 0,
C_CSE_DRV_VER => 2,
C_USE_TEST_REG => 1,
C_PIPE_IFACE => 1,
C_RAM_STYLE => "SUBCORE",
C_TRIGOUT_EN => 0,
C_TRIGIN_EN => 0,
C_ADV_TRIGGER => 1,
C_EN_DDR_ILA => 0,
C_EN_STRG_QUAL => 1,
C_INPUT_PIPE_STAGES => 0,
C_PROBE0_WIDTH => 1,
C_PROBE1_WIDTH => 8,
C_PROBE2_WIDTH => 1,
C_PROBE3_WIDTH => 1,
C_PROBE4_WIDTH => 1,
C_PROBE5_WIDTH => 2,
C_PROBE6_WIDTH => 1,
C_PROBE7_WIDTH => 6,
C_PROBE8_WIDTH => 5,
C_PROBE9_WIDTH => 1,
C_PROBE10_WIDTH => 1,
C_PROBE11_WIDTH => 1,
C_PROBE12_WIDTH => 1,
C_PROBE13_WIDTH => 1,
C_PROBE14_WIDTH => 1,
C_PROBE15_WIDTH => 1,
C_PROBE16_WIDTH => 1,
C_PROBE17_WIDTH => 1,
C_PROBE18_WIDTH => 1,
C_PROBE19_WIDTH => 1,
C_PROBE20_WIDTH => 1,
C_PROBE21_WIDTH => 1,
C_PROBE22_WIDTH => 1,
C_PROBE23_WIDTH => 1,
C_PROBE24_WIDTH => 1,
C_PROBE25_WIDTH => 1,
C_PROBE26_WIDTH => 1,
C_PROBE27_WIDTH => 1,
C_PROBE28_WIDTH => 1,
C_PROBE29_WIDTH => 1,
C_PROBE30_WIDTH => 1,
C_PROBE31_WIDTH => 1,
C_PROBE32_WIDTH => 1,
C_PROBE33_WIDTH => 1,
C_PROBE34_WIDTH => 1,
C_PROBE35_WIDTH => 1,
C_PROBE36_WIDTH => 1,
C_PROBE37_WIDTH => 1,
C_PROBE38_WIDTH => 1,
C_PROBE39_WIDTH => 1,
C_PROBE40_WIDTH => 1,
C_PROBE41_WIDTH => 1,
C_PROBE42_WIDTH => 1,
C_PROBE43_WIDTH => 1,
C_PROBE44_WIDTH => 1,
C_PROBE45_WIDTH => 1,
C_PROBE46_WIDTH => 1,
C_PROBE47_WIDTH => 1,
C_PROBE48_WIDTH => 1,
C_PROBE49_WIDTH => 1,
C_PROBE50_WIDTH => 1,
C_PROBE51_WIDTH => 1,
C_PROBE52_WIDTH => 1,
C_PROBE53_WIDTH => 1,
C_PROBE54_WIDTH => 1,
C_PROBE55_WIDTH => 1,
C_PROBE56_WIDTH => 1,
C_PROBE57_WIDTH => 1,
C_PROBE58_WIDTH => 1,
C_PROBE59_WIDTH => 1,
C_PROBE60_WIDTH => 1,
C_PROBE61_WIDTH => 1,
C_PROBE62_WIDTH => 1,
C_PROBE63_WIDTH => 1,
C_PROBE64_WIDTH => 1,
C_PROBE65_WIDTH => 1,
C_PROBE66_WIDTH => 1,
C_PROBE67_WIDTH => 1,
C_PROBE68_WIDTH => 1,
C_PROBE69_WIDTH => 1,
C_PROBE70_WIDTH => 1,
C_PROBE71_WIDTH => 1,
C_PROBE72_WIDTH => 1,
C_PROBE73_WIDTH => 1,
C_PROBE74_WIDTH => 1,
C_PROBE75_WIDTH => 1,
C_PROBE76_WIDTH => 1,
C_PROBE77_WIDTH => 1,
C_PROBE78_WIDTH => 1,
C_PROBE79_WIDTH => 1,
C_PROBE80_WIDTH => 1,
C_PROBE81_WIDTH => 1,
C_PROBE82_WIDTH => 1,
C_PROBE83_WIDTH => 1,
C_PROBE84_WIDTH => 1,
C_PROBE85_WIDTH => 1,
C_PROBE86_WIDTH => 1,
C_PROBE87_WIDTH => 1,
C_PROBE88_WIDTH => 1,
C_PROBE89_WIDTH => 1,
C_PROBE90_WIDTH => 1,
C_PROBE91_WIDTH => 1,
C_PROBE92_WIDTH => 1,
C_PROBE93_WIDTH => 1,
C_PROBE94_WIDTH => 1,
C_PROBE95_WIDTH => 1,
C_PROBE96_WIDTH => 1,
C_PROBE97_WIDTH => 1,
C_PROBE98_WIDTH => 1,
C_PROBE99_WIDTH => 1,
C_PROBE100_WIDTH => 1,
C_PROBE101_WIDTH => 1,
C_PROBE102_WIDTH => 1,
C_PROBE103_WIDTH => 1,
C_PROBE104_WIDTH => 1,
C_PROBE105_WIDTH => 1,
C_PROBE106_WIDTH => 1,
C_PROBE107_WIDTH => 1,
C_PROBE108_WIDTH => 1,
C_PROBE109_WIDTH => 1,
C_PROBE110_WIDTH => 1,
C_PROBE111_WIDTH => 1,
C_PROBE112_WIDTH => 1,
C_PROBE113_WIDTH => 1,
C_PROBE114_WIDTH => 1,
C_PROBE115_WIDTH => 1,
C_PROBE116_WIDTH => 1,
C_PROBE117_WIDTH => 1,
C_PROBE118_WIDTH => 1,
C_PROBE119_WIDTH => 1,
C_PROBE120_WIDTH => 1,
C_PROBE121_WIDTH => 1,
C_PROBE122_WIDTH => 1,
C_PROBE123_WIDTH => 1,
C_PROBE124_WIDTH => 1,
C_PROBE125_WIDTH => 1,
C_PROBE126_WIDTH => 1,
C_PROBE127_WIDTH => 1,
C_PROBE128_WIDTH => 1,
C_PROBE129_WIDTH => 1,
C_PROBE130_WIDTH => 1,
C_PROBE131_WIDTH => 1,
C_PROBE132_WIDTH => 1,
C_PROBE133_WIDTH => 1,
C_PROBE134_WIDTH => 1,
C_PROBE135_WIDTH => 1,
C_PROBE136_WIDTH => 1,
C_PROBE137_WIDTH => 1,
C_PROBE138_WIDTH => 1,
C_PROBE139_WIDTH => 1,
C_PROBE140_WIDTH => 1,
C_PROBE141_WIDTH => 1,
C_PROBE142_WIDTH => 1,
C_PROBE143_WIDTH => 1,
C_PROBE144_WIDTH => 1,
C_PROBE145_WIDTH => 1,
C_PROBE146_WIDTH => 1,
C_PROBE147_WIDTH => 1,
C_PROBE148_WIDTH => 1,
C_PROBE149_WIDTH => 1,
C_PROBE150_WIDTH => 1,
C_PROBE151_WIDTH => 1,
C_PROBE152_WIDTH => 1,
C_PROBE153_WIDTH => 1,
C_PROBE154_WIDTH => 1,
C_PROBE155_WIDTH => 1,
C_PROBE156_WIDTH => 1,
C_PROBE157_WIDTH => 1,
C_PROBE158_WIDTH => 1,
C_PROBE159_WIDTH => 1,
C_PROBE160_WIDTH => 1,
C_PROBE161_WIDTH => 1,
C_PROBE162_WIDTH => 1,
C_PROBE163_WIDTH => 1,
C_PROBE164_WIDTH => 1,
C_PROBE165_WIDTH => 1,
C_PROBE166_WIDTH => 1,
C_PROBE167_WIDTH => 1,
C_PROBE168_WIDTH => 1,
C_PROBE169_WIDTH => 1,
C_PROBE170_WIDTH => 1,
C_PROBE171_WIDTH => 1,
C_PROBE172_WIDTH => 1,
C_PROBE173_WIDTH => 1,
C_PROBE174_WIDTH => 1,
C_PROBE175_WIDTH => 1,
C_PROBE176_WIDTH => 1,
C_PROBE177_WIDTH => 1,
C_PROBE178_WIDTH => 1,
C_PROBE179_WIDTH => 1,
C_PROBE180_WIDTH => 1,
C_PROBE181_WIDTH => 1,
C_PROBE182_WIDTH => 1,
C_PROBE183_WIDTH => 1,
C_PROBE184_WIDTH => 1,
C_PROBE185_WIDTH => 1,
C_PROBE186_WIDTH => 1,
C_PROBE187_WIDTH => 1,
C_PROBE188_WIDTH => 1,
C_PROBE189_WIDTH => 1,
C_PROBE190_WIDTH => 1,
C_PROBE191_WIDTH => 1,
C_PROBE192_WIDTH => 1,
C_PROBE193_WIDTH => 1,
C_PROBE194_WIDTH => 1,
C_PROBE195_WIDTH => 1,
C_PROBE196_WIDTH => 1,
C_PROBE197_WIDTH => 1,
C_PROBE198_WIDTH => 1,
C_PROBE199_WIDTH => 1,
C_PROBE200_WIDTH => 1,
C_PROBE201_WIDTH => 1,
C_PROBE202_WIDTH => 1,
C_PROBE203_WIDTH => 1,
C_PROBE204_WIDTH => 1,
C_PROBE205_WIDTH => 1,
C_PROBE206_WIDTH => 1,
C_PROBE207_WIDTH => 1,
C_PROBE208_WIDTH => 1,
C_PROBE209_WIDTH => 1,
C_PROBE210_WIDTH => 1,
C_PROBE211_WIDTH => 1,
C_PROBE212_WIDTH => 1,
C_PROBE213_WIDTH => 1,
C_PROBE214_WIDTH => 1,
C_PROBE215_WIDTH => 1,
C_PROBE216_WIDTH => 1,
C_PROBE217_WIDTH => 1,
C_PROBE218_WIDTH => 1,
C_PROBE219_WIDTH => 1,
C_PROBE220_WIDTH => 1,
C_PROBE221_WIDTH => 1,
C_PROBE222_WIDTH => 1,
C_PROBE223_WIDTH => 1,
C_PROBE224_WIDTH => 1,
C_PROBE225_WIDTH => 1,
C_PROBE226_WIDTH => 1,
C_PROBE227_WIDTH => 1,
C_PROBE228_WIDTH => 1,
C_PROBE229_WIDTH => 1,
C_PROBE230_WIDTH => 1,
C_PROBE231_WIDTH => 1,
C_PROBE232_WIDTH => 1,
C_PROBE233_WIDTH => 1,
C_PROBE234_WIDTH => 1,
C_PROBE235_WIDTH => 1,
C_PROBE236_WIDTH => 1,
C_PROBE237_WIDTH => 1,
C_PROBE238_WIDTH => 1,
C_PROBE239_WIDTH => 1,
C_PROBE240_WIDTH => 1,
C_PROBE241_WIDTH => 1,
C_PROBE242_WIDTH => 1,
C_PROBE243_WIDTH => 1,
C_PROBE244_WIDTH => 1,
C_PROBE245_WIDTH => 1,
C_PROBE246_WIDTH => 1,
C_PROBE247_WIDTH => 1,
C_PROBE248_WIDTH => 1,
C_PROBE249_WIDTH => 1,
C_PROBE250_WIDTH => 1,
C_PROBE251_WIDTH => 1,
C_PROBE252_WIDTH => 1,
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C_PROBE256_WIDTH => 1,
C_PROBE257_WIDTH => 1,
C_PROBE258_WIDTH => 1,
C_PROBE259_WIDTH => 1,
C_PROBE260_WIDTH => 1,
C_PROBE261_WIDTH => 1,
C_PROBE262_WIDTH => 1,
C_PROBE263_WIDTH => 1,
C_PROBE264_WIDTH => 1,
C_PROBE265_WIDTH => 1,
C_PROBE266_WIDTH => 1,
C_PROBE267_WIDTH => 1,
C_PROBE268_WIDTH => 1,
C_PROBE269_WIDTH => 1,
C_PROBE270_WIDTH => 1,
C_PROBE271_WIDTH => 1,
C_PROBE272_WIDTH => 1,
C_PROBE273_WIDTH => 1,
C_PROBE274_WIDTH => 1,
C_PROBE275_WIDTH => 1,
C_PROBE276_WIDTH => 1,
C_PROBE277_WIDTH => 1,
C_PROBE278_WIDTH => 1,
C_PROBE279_WIDTH => 1,
C_PROBE280_WIDTH => 1,
C_PROBE281_WIDTH => 1,
C_PROBE282_WIDTH => 1,
C_PROBE283_WIDTH => 1,
C_PROBE284_WIDTH => 1,
C_PROBE285_WIDTH => 1,
C_PROBE286_WIDTH => 1,
C_PROBE287_WIDTH => 1,
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C_PROBE290_WIDTH => 1,
C_PROBE291_WIDTH => 1,
C_PROBE292_WIDTH => 1,
C_PROBE293_WIDTH => 1,
C_PROBE294_WIDTH => 1,
C_PROBE295_WIDTH => 1,
C_PROBE296_WIDTH => 1,
C_PROBE297_WIDTH => 1,
C_PROBE298_WIDTH => 1,
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C_PROBE300_WIDTH => 1,
C_PROBE301_WIDTH => 1,
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C_PROBE303_WIDTH => 1,
C_PROBE304_WIDTH => 1,
C_PROBE305_WIDTH => 1,
C_PROBE306_WIDTH => 1,
C_PROBE307_WIDTH => 1,
C_PROBE308_WIDTH => 1,
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C_PROBE310_WIDTH => 1,
C_PROBE311_WIDTH => 1,
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C_PROBE313_WIDTH => 1,
C_PROBE314_WIDTH => 1,
C_PROBE315_WIDTH => 1,
C_PROBE316_WIDTH => 1,
C_PROBE317_WIDTH => 1,
C_PROBE318_WIDTH => 1,
C_PROBE319_WIDTH => 1,
C_PROBE320_WIDTH => 1,
C_PROBE321_WIDTH => 1,
C_PROBE322_WIDTH => 1,
C_PROBE323_WIDTH => 1,
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C_PROBE327_WIDTH => 1,
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C_PROBE11_MU_CNT => 1,
C_PROBE12_MU_CNT => 1,
C_PROBE13_MU_CNT => 1,
C_PROBE14_MU_CNT => 1,
C_PROBE15_MU_CNT => 1,
C_PROBE16_MU_CNT => 1,
C_PROBE17_MU_CNT => 1,
C_PROBE18_MU_CNT => 1,
C_PROBE19_MU_CNT => 1,
C_PROBE20_MU_CNT => 1,
C_PROBE21_MU_CNT => 1,
C_PROBE22_MU_CNT => 1,
C_PROBE23_MU_CNT => 1,
C_PROBE24_MU_CNT => 1,
C_PROBE25_MU_CNT => 1,
C_PROBE26_MU_CNT => 1,
C_PROBE27_MU_CNT => 1,
C_PROBE28_MU_CNT => 1,
C_PROBE29_MU_CNT => 1,
C_PROBE30_MU_CNT => 1,
C_PROBE31_MU_CNT => 1,
C_PROBE32_MU_CNT => 1,
C_PROBE33_MU_CNT => 1,
C_PROBE34_MU_CNT => 1,
C_PROBE35_MU_CNT => 1,
C_PROBE36_MU_CNT => 1,
C_PROBE37_MU_CNT => 1,
C_PROBE38_MU_CNT => 1,
C_PROBE39_MU_CNT => 1,
C_PROBE40_MU_CNT => 1,
C_PROBE41_MU_CNT => 1,
C_PROBE42_MU_CNT => 1,
C_PROBE43_MU_CNT => 1,
C_PROBE44_MU_CNT => 1,
C_PROBE45_MU_CNT => 1,
C_PROBE46_MU_CNT => 1,
C_PROBE47_MU_CNT => 1,
C_PROBE48_MU_CNT => 1,
C_PROBE49_MU_CNT => 1,
C_PROBE50_MU_CNT => 1,
C_PROBE51_MU_CNT => 1,
C_PROBE52_MU_CNT => 1,
C_PROBE53_MU_CNT => 1,
C_PROBE54_MU_CNT => 1,
C_PROBE55_MU_CNT => 1,
C_PROBE56_MU_CNT => 1,
C_PROBE57_MU_CNT => 1,
C_PROBE58_MU_CNT => 1,
C_PROBE59_MU_CNT => 1,
C_PROBE60_MU_CNT => 1,
C_PROBE61_MU_CNT => 1,
C_PROBE62_MU_CNT => 1,
C_PROBE63_MU_CNT => 1,
C_PROBE64_MU_CNT => 1,
C_PROBE65_MU_CNT => 1,
C_PROBE66_MU_CNT => 1,
C_PROBE67_MU_CNT => 1,
C_PROBE68_MU_CNT => 1,
C_PROBE69_MU_CNT => 1,
C_PROBE70_MU_CNT => 1,
C_PROBE71_MU_CNT => 1,
C_PROBE72_MU_CNT => 1,
C_PROBE73_MU_CNT => 1,
C_PROBE74_MU_CNT => 1,
C_PROBE75_MU_CNT => 1,
C_PROBE76_MU_CNT => 1,
C_PROBE77_MU_CNT => 1,
C_PROBE78_MU_CNT => 1,
C_PROBE79_MU_CNT => 1,
C_PROBE80_MU_CNT => 1,
C_PROBE81_MU_CNT => 1,
C_PROBE82_MU_CNT => 1,
C_PROBE83_MU_CNT => 1,
C_PROBE84_MU_CNT => 1,
C_PROBE85_MU_CNT => 1,
C_PROBE86_MU_CNT => 1,
C_PROBE87_MU_CNT => 1,
C_PROBE88_MU_CNT => 1,
C_PROBE89_MU_CNT => 1,
C_PROBE90_MU_CNT => 1,
C_PROBE91_MU_CNT => 1,
C_PROBE92_MU_CNT => 1,
C_PROBE93_MU_CNT => 1,
C_PROBE94_MU_CNT => 1,
C_PROBE95_MU_CNT => 1,
C_PROBE96_MU_CNT => 1,
C_PROBE97_MU_CNT => 1,
C_PROBE98_MU_CNT => 1,
C_PROBE99_MU_CNT => 1,
C_PROBE100_MU_CNT => 1,
C_PROBE101_MU_CNT => 1,
C_PROBE102_MU_CNT => 1,
C_PROBE103_MU_CNT => 1,
C_PROBE104_MU_CNT => 1,
C_PROBE105_MU_CNT => 1,
C_PROBE106_MU_CNT => 1,
C_PROBE107_MU_CNT => 1,
C_PROBE108_MU_CNT => 1,
C_PROBE109_MU_CNT => 1,
C_PROBE110_MU_CNT => 1,
C_PROBE111_MU_CNT => 1,
C_PROBE112_MU_CNT => 1,
C_PROBE113_MU_CNT => 1,
C_PROBE114_MU_CNT => 1,
C_PROBE115_MU_CNT => 1,
C_PROBE116_MU_CNT => 1,
C_PROBE117_MU_CNT => 1,
C_PROBE118_MU_CNT => 1,
C_PROBE119_MU_CNT => 1,
C_PROBE120_MU_CNT => 1,
C_PROBE121_MU_CNT => 1,
C_PROBE122_MU_CNT => 1,
C_PROBE123_MU_CNT => 1,
C_PROBE124_MU_CNT => 1,
C_PROBE125_MU_CNT => 1,
C_PROBE126_MU_CNT => 1,
C_PROBE127_MU_CNT => 1,
C_PROBE128_MU_CNT => 1,
C_PROBE129_MU_CNT => 1,
C_PROBE130_MU_CNT => 1,
C_PROBE131_MU_CNT => 1,
C_PROBE132_MU_CNT => 1,
C_PROBE133_MU_CNT => 1,
C_PROBE134_MU_CNT => 1,
C_PROBE135_MU_CNT => 1,
C_PROBE136_MU_CNT => 1,
C_PROBE137_MU_CNT => 1,
C_PROBE138_MU_CNT => 1,
C_PROBE139_MU_CNT => 1,
C_PROBE140_MU_CNT => 1,
C_PROBE141_MU_CNT => 1,
C_PROBE142_MU_CNT => 1,
C_PROBE143_MU_CNT => 1,
C_PROBE144_MU_CNT => 1,
C_PROBE145_MU_CNT => 1,
C_PROBE146_MU_CNT => 1,
C_PROBE147_MU_CNT => 1,
C_PROBE148_MU_CNT => 1,
C_PROBE149_MU_CNT => 1,
C_PROBE150_MU_CNT => 1,
C_PROBE151_MU_CNT => 1,
C_PROBE152_MU_CNT => 1,
C_PROBE153_MU_CNT => 1,
C_PROBE154_MU_CNT => 1,
C_PROBE155_MU_CNT => 1,
C_PROBE156_MU_CNT => 1,
C_PROBE157_MU_CNT => 1,
C_PROBE158_MU_CNT => 1,
C_PROBE159_MU_CNT => 1,
C_PROBE160_MU_CNT => 1,
C_PROBE161_MU_CNT => 1,
C_PROBE162_MU_CNT => 1,
C_PROBE163_MU_CNT => 1,
C_PROBE164_MU_CNT => 1,
C_PROBE165_MU_CNT => 1,
C_PROBE166_MU_CNT => 1,
C_PROBE167_MU_CNT => 1,
C_PROBE168_MU_CNT => 1,
C_PROBE169_MU_CNT => 1,
C_PROBE170_MU_CNT => 1,
C_PROBE171_MU_CNT => 1,
C_PROBE172_MU_CNT => 1,
C_PROBE173_MU_CNT => 1,
C_PROBE174_MU_CNT => 1,
C_PROBE175_MU_CNT => 1,
C_PROBE176_MU_CNT => 1,
C_PROBE177_MU_CNT => 1,
C_PROBE178_MU_CNT => 1,
C_PROBE179_MU_CNT => 1,
C_PROBE180_MU_CNT => 1,
C_PROBE181_MU_CNT => 1,
C_PROBE182_MU_CNT => 1,
C_PROBE183_MU_CNT => 1,
C_PROBE184_MU_CNT => 1,
C_PROBE185_MU_CNT => 1,
C_PROBE186_MU_CNT => 1,
C_PROBE187_MU_CNT => 1,
C_PROBE188_MU_CNT => 1,
C_PROBE189_MU_CNT => 1,
C_PROBE190_MU_CNT => 1,
C_PROBE191_MU_CNT => 1,
C_PROBE192_MU_CNT => 1,
C_PROBE193_MU_CNT => 1,
C_PROBE194_MU_CNT => 1,
C_PROBE195_MU_CNT => 1,
C_PROBE196_MU_CNT => 1,
C_PROBE197_MU_CNT => 1,
C_PROBE198_MU_CNT => 1,
C_PROBE199_MU_CNT => 1,
C_PROBE200_MU_CNT => 1,
C_PROBE201_MU_CNT => 1,
C_PROBE202_MU_CNT => 1,
C_PROBE203_MU_CNT => 1,
C_PROBE204_MU_CNT => 1,
C_PROBE205_MU_CNT => 1,
C_PROBE206_MU_CNT => 1,
C_PROBE207_MU_CNT => 1,
C_PROBE208_MU_CNT => 1,
C_PROBE209_MU_CNT => 1,
C_PROBE210_MU_CNT => 1,
C_PROBE211_MU_CNT => 1,
C_PROBE212_MU_CNT => 1,
C_PROBE213_MU_CNT => 1,
C_PROBE214_MU_CNT => 1,
C_PROBE215_MU_CNT => 1,
C_PROBE216_MU_CNT => 1,
C_PROBE217_MU_CNT => 1,
C_PROBE218_MU_CNT => 1,
C_PROBE219_MU_CNT => 1,
C_PROBE220_MU_CNT => 1,
C_PROBE221_MU_CNT => 1,
C_PROBE222_MU_CNT => 1,
C_PROBE223_MU_CNT => 1,
C_PROBE224_MU_CNT => 1,
C_PROBE225_MU_CNT => 1,
C_PROBE226_MU_CNT => 1,
C_PROBE227_MU_CNT => 1,
C_PROBE228_MU_CNT => 1,
C_PROBE229_MU_CNT => 1,
C_PROBE230_MU_CNT => 1,
C_PROBE231_MU_CNT => 1,
C_PROBE232_MU_CNT => 1,
C_PROBE233_MU_CNT => 1,
C_PROBE234_MU_CNT => 1,
C_PROBE235_MU_CNT => 1,
C_PROBE236_MU_CNT => 1,
C_PROBE237_MU_CNT => 1,
C_PROBE238_MU_CNT => 1,
C_PROBE239_MU_CNT => 1,
C_PROBE240_MU_CNT => 1,
C_PROBE241_MU_CNT => 1,
C_PROBE242_MU_CNT => 1,
C_PROBE243_MU_CNT => 1,
C_PROBE244_MU_CNT => 1,
C_PROBE245_MU_CNT => 1,
C_PROBE246_MU_CNT => 1,
C_PROBE247_MU_CNT => 1,
C_PROBE248_MU_CNT => 1,
C_PROBE249_MU_CNT => 1,
C_PROBE250_MU_CNT => 1,
C_PROBE251_MU_CNT => 1,
C_PROBE252_MU_CNT => 1,
C_PROBE253_MU_CNT => 1,
C_PROBE254_MU_CNT => 1,
C_PROBE255_MU_CNT => 1,
C_PROBE256_MU_CNT => 1,
C_PROBE257_MU_CNT => 1,
C_PROBE258_MU_CNT => 1,
C_PROBE259_MU_CNT => 1,
C_PROBE260_MU_CNT => 1,
C_PROBE261_MU_CNT => 1,
C_PROBE262_MU_CNT => 1,
C_PROBE263_MU_CNT => 1,
C_PROBE264_MU_CNT => 1,
C_PROBE265_MU_CNT => 1,
C_PROBE266_MU_CNT => 1,
C_PROBE267_MU_CNT => 1,
C_PROBE268_MU_CNT => 1,
C_PROBE269_MU_CNT => 1,
C_PROBE270_MU_CNT => 1,
C_PROBE271_MU_CNT => 1,
C_PROBE272_MU_CNT => 1,
C_PROBE273_MU_CNT => 1,
C_PROBE274_MU_CNT => 1,
C_PROBE275_MU_CNT => 1,
C_PROBE276_MU_CNT => 1,
C_PROBE277_MU_CNT => 1,
C_PROBE278_MU_CNT => 1,
C_PROBE279_MU_CNT => 1,
C_PROBE280_MU_CNT => 1,
C_PROBE281_MU_CNT => 1,
C_PROBE282_MU_CNT => 1,
C_PROBE283_MU_CNT => 1,
C_PROBE284_MU_CNT => 1,
C_PROBE285_MU_CNT => 1,
C_PROBE286_MU_CNT => 1,
C_PROBE287_MU_CNT => 1,
C_PROBE288_MU_CNT => 1,
C_PROBE289_MU_CNT => 1,
C_PROBE290_MU_CNT => 1,
C_PROBE291_MU_CNT => 1,
C_PROBE292_MU_CNT => 1,
C_PROBE293_MU_CNT => 1,
C_PROBE294_MU_CNT => 1,
C_PROBE295_MU_CNT => 1,
C_PROBE296_MU_CNT => 1,
C_PROBE297_MU_CNT => 1,
C_PROBE298_MU_CNT => 1,
C_PROBE299_MU_CNT => 1,
C_PROBE300_MU_CNT => 1,
C_PROBE301_MU_CNT => 1,
C_PROBE302_MU_CNT => 1,
C_PROBE303_MU_CNT => 1,
C_PROBE304_MU_CNT => 1,
C_PROBE305_MU_CNT => 1,
C_PROBE306_MU_CNT => 1,
C_PROBE307_MU_CNT => 1,
C_PROBE308_MU_CNT => 1,
C_PROBE309_MU_CNT => 1,
C_PROBE310_MU_CNT => 1,
C_PROBE311_MU_CNT => 1,
C_PROBE312_MU_CNT => 1,
C_PROBE313_MU_CNT => 1,
C_PROBE314_MU_CNT => 1,
C_PROBE315_MU_CNT => 1,
C_PROBE316_MU_CNT => 1,
C_PROBE317_MU_CNT => 1,
C_PROBE318_MU_CNT => 1,
C_PROBE319_MU_CNT => 1,
C_PROBE320_MU_CNT => 1,
C_PROBE321_MU_CNT => 1,
C_PROBE322_MU_CNT => 1,
C_PROBE323_MU_CNT => 1,
C_PROBE324_MU_CNT => 1,
C_PROBE325_MU_CNT => 1,
C_PROBE326_MU_CNT => 1,
C_PROBE327_MU_CNT => 1,
C_PROBE328_MU_CNT => 1,
C_PROBE329_MU_CNT => 1,
C_PROBE330_MU_CNT => 1,
C_PROBE331_MU_CNT => 1,
C_PROBE332_MU_CNT => 1,
C_PROBE333_MU_CNT => 1,
C_PROBE334_MU_CNT => 1,
C_PROBE335_MU_CNT => 1,
C_PROBE336_MU_CNT => 1,
C_PROBE337_MU_CNT => 1,
C_PROBE338_MU_CNT => 1,
C_PROBE339_MU_CNT => 1,
C_PROBE340_MU_CNT => 1,
C_PROBE341_MU_CNT => 1,
C_PROBE342_MU_CNT => 1,
C_PROBE343_MU_CNT => 1,
C_PROBE344_MU_CNT => 1,
C_PROBE345_MU_CNT => 1,
C_PROBE346_MU_CNT => 1,
C_PROBE347_MU_CNT => 1,
C_PROBE348_MU_CNT => 1,
C_PROBE349_MU_CNT => 1,
C_PROBE350_MU_CNT => 1,
C_PROBE351_MU_CNT => 1,
C_PROBE352_MU_CNT => 1,
C_PROBE353_MU_CNT => 1,
C_PROBE354_MU_CNT => 1,
C_PROBE355_MU_CNT => 1,
C_PROBE356_MU_CNT => 1,
C_PROBE357_MU_CNT => 1,
C_PROBE358_MU_CNT => 1,
C_PROBE359_MU_CNT => 1,
C_PROBE360_MU_CNT => 1,
C_PROBE361_MU_CNT => 1,
C_PROBE362_MU_CNT => 1,
C_PROBE363_MU_CNT => 1,
C_PROBE364_MU_CNT => 1,
C_PROBE365_MU_CNT => 1,
C_PROBE366_MU_CNT => 1,
C_PROBE367_MU_CNT => 1,
C_PROBE368_MU_CNT => 1,
C_PROBE369_MU_CNT => 1,
C_PROBE370_MU_CNT => 1,
C_PROBE371_MU_CNT => 1,
C_PROBE372_MU_CNT => 1,
C_PROBE373_MU_CNT => 1,
C_PROBE374_MU_CNT => 1,
C_PROBE375_MU_CNT => 1,
C_PROBE376_MU_CNT => 1,
C_PROBE377_MU_CNT => 1,
C_PROBE378_MU_CNT => 1,
C_PROBE379_MU_CNT => 1,
C_PROBE380_MU_CNT => 1,
C_PROBE381_MU_CNT => 1,
C_PROBE382_MU_CNT => 1,
C_PROBE383_MU_CNT => 1,
C_PROBE384_MU_CNT => 1,
C_PROBE385_MU_CNT => 1,
C_PROBE386_MU_CNT => 1,
C_PROBE387_MU_CNT => 1,
C_PROBE388_MU_CNT => 1,
C_PROBE389_MU_CNT => 1,
C_PROBE390_MU_CNT => 1,
C_PROBE391_MU_CNT => 1,
C_PROBE392_MU_CNT => 1,
C_PROBE393_MU_CNT => 1,
C_PROBE394_MU_CNT => 1,
C_PROBE395_MU_CNT => 1,
C_PROBE396_MU_CNT => 1,
C_PROBE397_MU_CNT => 1,
C_PROBE398_MU_CNT => 1,
C_PROBE399_MU_CNT => 1,
C_PROBE400_MU_CNT => 1,
C_PROBE401_MU_CNT => 1,
C_PROBE402_MU_CNT => 1,
C_PROBE403_MU_CNT => 1,
C_PROBE404_MU_CNT => 1,
C_PROBE405_MU_CNT => 1,
C_PROBE406_MU_CNT => 1,
C_PROBE407_MU_CNT => 1,
C_PROBE408_MU_CNT => 1,
C_PROBE409_MU_CNT => 1,
C_PROBE410_MU_CNT => 1,
C_PROBE411_MU_CNT => 1,
C_PROBE412_MU_CNT => 1,
C_PROBE413_MU_CNT => 1,
C_PROBE414_MU_CNT => 1,
C_PROBE415_MU_CNT => 1,
C_PROBE416_MU_CNT => 1,
C_PROBE417_MU_CNT => 1,
C_PROBE418_MU_CNT => 1,
C_PROBE419_MU_CNT => 1,
C_PROBE420_MU_CNT => 1,
C_PROBE421_MU_CNT => 1,
C_PROBE422_MU_CNT => 1,
C_PROBE423_MU_CNT => 1,
C_PROBE424_MU_CNT => 1,
C_PROBE425_MU_CNT => 1,
C_PROBE426_MU_CNT => 1,
C_PROBE427_MU_CNT => 1,
C_PROBE428_MU_CNT => 1,
C_PROBE429_MU_CNT => 1,
C_PROBE430_MU_CNT => 1,
C_PROBE431_MU_CNT => 1,
C_PROBE432_MU_CNT => 1,
C_PROBE433_MU_CNT => 1,
C_PROBE434_MU_CNT => 1,
C_PROBE435_MU_CNT => 1,
C_PROBE436_MU_CNT => 1,
C_PROBE437_MU_CNT => 1,
C_PROBE438_MU_CNT => 1,
C_PROBE439_MU_CNT => 1,
C_PROBE440_MU_CNT => 1,
C_PROBE441_MU_CNT => 1,
C_PROBE442_MU_CNT => 1,
C_PROBE443_MU_CNT => 1,
C_PROBE444_MU_CNT => 1,
C_PROBE445_MU_CNT => 1,
C_PROBE446_MU_CNT => 1,
C_PROBE447_MU_CNT => 1,
C_PROBE448_MU_CNT => 1,
C_PROBE449_MU_CNT => 1,
C_PROBE450_MU_CNT => 1,
C_PROBE451_MU_CNT => 1,
C_PROBE452_MU_CNT => 1,
C_PROBE453_MU_CNT => 1,
C_PROBE454_MU_CNT => 1,
C_PROBE455_MU_CNT => 1,
C_PROBE456_MU_CNT => 1,
C_PROBE457_MU_CNT => 1,
C_PROBE458_MU_CNT => 1,
C_PROBE459_MU_CNT => 1,
C_PROBE460_MU_CNT => 1,
C_PROBE461_MU_CNT => 1,
C_PROBE462_MU_CNT => 1,
C_PROBE463_MU_CNT => 1,
C_PROBE464_MU_CNT => 1,
C_PROBE465_MU_CNT => 1,
C_PROBE466_MU_CNT => 1,
C_PROBE467_MU_CNT => 1,
C_PROBE468_MU_CNT => 1,
C_PROBE469_MU_CNT => 1,
C_PROBE470_MU_CNT => 1,
C_PROBE471_MU_CNT => 1,
C_PROBE472_MU_CNT => 1,
C_PROBE473_MU_CNT => 1,
C_PROBE474_MU_CNT => 1,
C_PROBE475_MU_CNT => 1,
C_PROBE476_MU_CNT => 1,
C_PROBE477_MU_CNT => 1,
C_PROBE478_MU_CNT => 1,
C_PROBE479_MU_CNT => 1,
C_PROBE480_MU_CNT => 1,
C_PROBE481_MU_CNT => 1,
C_PROBE482_MU_CNT => 1,
C_PROBE483_MU_CNT => 1,
C_PROBE484_MU_CNT => 1,
C_PROBE485_MU_CNT => 1,
C_PROBE486_MU_CNT => 1,
C_PROBE487_MU_CNT => 1,
C_PROBE488_MU_CNT => 1,
C_PROBE489_MU_CNT => 1,
C_PROBE490_MU_CNT => 1,
C_PROBE491_MU_CNT => 1,
C_PROBE492_MU_CNT => 1,
C_PROBE493_MU_CNT => 1,
C_PROBE494_MU_CNT => 1,
C_PROBE495_MU_CNT => 1,
C_PROBE496_MU_CNT => 1,
C_PROBE497_MU_CNT => 1,
C_PROBE498_MU_CNT => 1,
C_PROBE499_MU_CNT => 1,
C_PROBE500_MU_CNT => 1,
C_PROBE501_MU_CNT => 1,
C_PROBE502_MU_CNT => 1,
C_PROBE503_MU_CNT => 1,
C_PROBE504_MU_CNT => 1,
C_PROBE505_MU_CNT => 1,
C_PROBE506_MU_CNT => 1,
C_PROBE507_MU_CNT => 1,
C_PROBE508_MU_CNT => 1,
C_PROBE509_MU_CNT => 1,
C_PROBE510_MU_CNT => 1,
C_PROBE511_MU_CNT => 1,
C_PROBE512_MU_CNT => 1,
C_PROBE513_MU_CNT => 1,
C_PROBE514_MU_CNT => 1,
C_PROBE515_MU_CNT => 1,
C_PROBE516_MU_CNT => 1,
C_PROBE517_MU_CNT => 1,
C_PROBE518_MU_CNT => 1,
C_PROBE519_MU_CNT => 1,
C_PROBE520_MU_CNT => 1,
C_PROBE521_MU_CNT => 1,
C_PROBE522_MU_CNT => 1,
C_PROBE523_MU_CNT => 1,
C_PROBE524_MU_CNT => 1,
C_PROBE525_MU_CNT => 1,
C_PROBE526_MU_CNT => 1,
C_PROBE527_MU_CNT => 1,
C_PROBE528_MU_CNT => 1,
C_PROBE529_MU_CNT => 1,
C_PROBE530_MU_CNT => 1,
C_PROBE531_MU_CNT => 1,
C_PROBE532_MU_CNT => 1,
C_PROBE533_MU_CNT => 1,
C_PROBE534_MU_CNT => 1,
C_PROBE535_MU_CNT => 1,
C_PROBE536_MU_CNT => 1,
C_PROBE537_MU_CNT => 1,
C_PROBE538_MU_CNT => 1,
C_PROBE539_MU_CNT => 1,
C_PROBE540_MU_CNT => 1,
C_PROBE541_MU_CNT => 1,
C_PROBE542_MU_CNT => 1,
C_PROBE543_MU_CNT => 1,
C_PROBE544_MU_CNT => 1,
C_PROBE545_MU_CNT => 1,
C_PROBE546_MU_CNT => 1,
C_PROBE547_MU_CNT => 1,
C_PROBE548_MU_CNT => 1,
C_PROBE549_MU_CNT => 1,
C_PROBE550_MU_CNT => 1,
C_PROBE551_MU_CNT => 1,
C_PROBE552_MU_CNT => 1,
C_PROBE553_MU_CNT => 1,
C_PROBE554_MU_CNT => 1,
C_PROBE555_MU_CNT => 1,
C_PROBE556_MU_CNT => 1,
C_PROBE557_MU_CNT => 1,
C_PROBE558_MU_CNT => 1,
C_PROBE559_MU_CNT => 1,
C_PROBE560_MU_CNT => 1,
C_PROBE561_MU_CNT => 1,
C_PROBE562_MU_CNT => 1,
C_PROBE563_MU_CNT => 1,
C_PROBE564_MU_CNT => 1,
C_PROBE565_MU_CNT => 1,
C_PROBE566_MU_CNT => 1,
C_PROBE567_MU_CNT => 1,
C_PROBE568_MU_CNT => 1,
C_PROBE569_MU_CNT => 1,
C_PROBE570_MU_CNT => 1,
C_PROBE571_MU_CNT => 1,
C_PROBE572_MU_CNT => 1,
C_PROBE573_MU_CNT => 1,
C_PROBE574_MU_CNT => 1,
C_PROBE575_MU_CNT => 1,
C_PROBE576_MU_CNT => 1,
C_PROBE577_MU_CNT => 1,
C_PROBE578_MU_CNT => 1,
C_PROBE579_MU_CNT => 1,
C_PROBE580_MU_CNT => 1,
C_PROBE581_MU_CNT => 1,
C_PROBE582_MU_CNT => 1,
C_PROBE583_MU_CNT => 1,
C_PROBE584_MU_CNT => 1,
C_PROBE585_MU_CNT => 1,
C_PROBE586_MU_CNT => 1,
C_PROBE587_MU_CNT => 1,
C_PROBE588_MU_CNT => 1,
C_PROBE589_MU_CNT => 1,
C_PROBE590_MU_CNT => 1,
C_PROBE591_MU_CNT => 1,
C_PROBE592_MU_CNT => 1,
C_PROBE593_MU_CNT => 1,
C_PROBE594_MU_CNT => 1,
C_PROBE595_MU_CNT => 1,
C_PROBE596_MU_CNT => 1,
C_PROBE597_MU_CNT => 1,
C_PROBE598_MU_CNT => 1,
C_PROBE599_MU_CNT => 1,
C_PROBE600_MU_CNT => 1,
C_PROBE601_MU_CNT => 1,
C_PROBE602_MU_CNT => 1,
C_PROBE603_MU_CNT => 1,
C_PROBE604_MU_CNT => 1,
C_PROBE605_MU_CNT => 1,
C_PROBE606_MU_CNT => 1,
C_PROBE607_MU_CNT => 1,
C_PROBE608_MU_CNT => 1,
C_PROBE609_MU_CNT => 1,
C_PROBE610_MU_CNT => 1,
C_PROBE611_MU_CNT => 1,
C_PROBE612_MU_CNT => 1,
C_PROBE613_MU_CNT => 1,
C_PROBE614_MU_CNT => 1,
C_PROBE615_MU_CNT => 1,
C_PROBE616_MU_CNT => 1,
C_PROBE617_MU_CNT => 1,
C_PROBE618_MU_CNT => 1,
C_PROBE619_MU_CNT => 1,
C_PROBE620_MU_CNT => 1,
C_PROBE621_MU_CNT => 1,
C_PROBE622_MU_CNT => 1,
C_PROBE623_MU_CNT => 1,
C_PROBE624_MU_CNT => 1,
C_PROBE625_MU_CNT => 1,
C_PROBE626_MU_CNT => 1,
C_PROBE627_MU_CNT => 1,
C_PROBE628_MU_CNT => 1,
C_PROBE629_MU_CNT => 1,
C_PROBE630_MU_CNT => 1,
C_PROBE631_MU_CNT => 1,
C_PROBE632_MU_CNT => 1,
C_PROBE633_MU_CNT => 1,
C_PROBE634_MU_CNT => 1,
C_PROBE635_MU_CNT => 1,
C_PROBE636_MU_CNT => 1,
C_PROBE637_MU_CNT => 1,
C_PROBE638_MU_CNT => 1,
C_PROBE639_MU_CNT => 1,
C_PROBE640_MU_CNT => 1,
C_PROBE641_MU_CNT => 1,
C_PROBE642_MU_CNT => 1,
C_PROBE643_MU_CNT => 1,
C_PROBE644_MU_CNT => 1,
C_PROBE645_MU_CNT => 1,
C_PROBE646_MU_CNT => 1,
C_PROBE647_MU_CNT => 1,
C_PROBE648_MU_CNT => 1,
C_PROBE649_MU_CNT => 1,
C_PROBE650_MU_CNT => 1,
C_PROBE651_MU_CNT => 1,
C_PROBE652_MU_CNT => 1,
C_PROBE653_MU_CNT => 1,
C_PROBE654_MU_CNT => 1,
C_PROBE655_MU_CNT => 1,
C_PROBE656_MU_CNT => 1,
C_PROBE657_MU_CNT => 1,
C_PROBE658_MU_CNT => 1,
C_PROBE659_MU_CNT => 1,
C_PROBE660_MU_CNT => 1,
C_PROBE661_MU_CNT => 1,
C_PROBE662_MU_CNT => 1,
C_PROBE663_MU_CNT => 1,
C_PROBE664_MU_CNT => 1,
C_PROBE665_MU_CNT => 1,
C_PROBE666_MU_CNT => 1,
C_PROBE667_MU_CNT => 1,
C_PROBE668_MU_CNT => 1,
C_PROBE669_MU_CNT => 1,
C_PROBE670_MU_CNT => 1,
C_PROBE671_MU_CNT => 1,
C_PROBE672_MU_CNT => 1,
C_PROBE673_MU_CNT => 1,
C_PROBE674_MU_CNT => 1,
C_PROBE675_MU_CNT => 1,
C_PROBE676_MU_CNT => 1,
C_PROBE677_MU_CNT => 1,
C_PROBE678_MU_CNT => 1,
C_PROBE679_MU_CNT => 1,
C_PROBE680_MU_CNT => 1,
C_PROBE681_MU_CNT => 1,
C_PROBE682_MU_CNT => 1,
C_PROBE683_MU_CNT => 1,
C_PROBE684_MU_CNT => 1,
C_PROBE685_MU_CNT => 1,
C_PROBE686_MU_CNT => 1,
C_PROBE687_MU_CNT => 1,
C_PROBE688_MU_CNT => 1,
C_PROBE689_MU_CNT => 1,
C_PROBE690_MU_CNT => 1,
C_PROBE691_MU_CNT => 1,
C_PROBE692_MU_CNT => 1,
C_PROBE693_MU_CNT => 1,
C_PROBE694_MU_CNT => 1,
C_PROBE695_MU_CNT => 1,
C_PROBE696_MU_CNT => 1,
C_PROBE697_MU_CNT => 1,
C_PROBE698_MU_CNT => 1,
C_PROBE699_MU_CNT => 1,
C_PROBE700_MU_CNT => 1,
C_PROBE701_MU_CNT => 1,
C_PROBE702_MU_CNT => 1,
C_PROBE703_MU_CNT => 1,
C_PROBE704_MU_CNT => 1,
C_PROBE705_MU_CNT => 1,
C_PROBE706_MU_CNT => 1,
C_PROBE707_MU_CNT => 1,
C_PROBE708_MU_CNT => 1,
C_PROBE709_MU_CNT => 1,
C_PROBE710_MU_CNT => 1,
C_PROBE711_MU_CNT => 1,
C_PROBE712_MU_CNT => 1,
C_PROBE713_MU_CNT => 1,
C_PROBE714_MU_CNT => 1,
C_PROBE715_MU_CNT => 1,
C_PROBE716_MU_CNT => 1,
C_PROBE717_MU_CNT => 1,
C_PROBE718_MU_CNT => 1,
C_PROBE719_MU_CNT => 1,
C_PROBE720_MU_CNT => 1,
C_PROBE721_MU_CNT => 1,
C_PROBE722_MU_CNT => 1,
C_PROBE723_MU_CNT => 1,
C_PROBE724_MU_CNT => 1,
C_PROBE725_MU_CNT => 1,
C_PROBE726_MU_CNT => 1,
C_PROBE727_MU_CNT => 1,
C_PROBE728_MU_CNT => 1,
C_PROBE729_MU_CNT => 1,
C_PROBE730_MU_CNT => 1,
C_PROBE731_MU_CNT => 1,
C_PROBE732_MU_CNT => 1,
C_PROBE733_MU_CNT => 1,
C_PROBE734_MU_CNT => 1,
C_PROBE735_MU_CNT => 1,
C_PROBE736_MU_CNT => 1,
C_PROBE737_MU_CNT => 1,
C_PROBE738_MU_CNT => 1,
C_PROBE739_MU_CNT => 1,
C_PROBE740_MU_CNT => 1,
C_PROBE741_MU_CNT => 1,
C_PROBE742_MU_CNT => 1,
C_PROBE743_MU_CNT => 1,
C_PROBE744_MU_CNT => 1,
C_PROBE745_MU_CNT => 1,
C_PROBE746_MU_CNT => 1,
C_PROBE747_MU_CNT => 1,
C_PROBE748_MU_CNT => 1,
C_PROBE749_MU_CNT => 1,
C_PROBE750_MU_CNT => 1,
C_PROBE751_MU_CNT => 1,
C_PROBE752_MU_CNT => 1,
C_PROBE753_MU_CNT => 1,
C_PROBE754_MU_CNT => 1,
C_PROBE755_MU_CNT => 1,
C_PROBE756_MU_CNT => 1,
C_PROBE757_MU_CNT => 1,
C_PROBE758_MU_CNT => 1,
C_PROBE759_MU_CNT => 1,
C_PROBE760_MU_CNT => 1,
C_PROBE761_MU_CNT => 1,
C_PROBE762_MU_CNT => 1,
C_PROBE763_MU_CNT => 1,
C_PROBE764_MU_CNT => 1,
C_PROBE765_MU_CNT => 1,
C_PROBE766_MU_CNT => 1,
C_PROBE767_MU_CNT => 1,
C_PROBE768_MU_CNT => 1,
C_PROBE769_MU_CNT => 1,
C_PROBE770_MU_CNT => 1,
C_PROBE771_MU_CNT => 1,
C_PROBE772_MU_CNT => 1,
C_PROBE773_MU_CNT => 1,
C_PROBE774_MU_CNT => 1,
C_PROBE775_MU_CNT => 1,
C_PROBE776_MU_CNT => 1,
C_PROBE777_MU_CNT => 1,
C_PROBE778_MU_CNT => 1,
C_PROBE779_MU_CNT => 1,
C_PROBE780_MU_CNT => 1,
C_PROBE781_MU_CNT => 1,
C_PROBE782_MU_CNT => 1,
C_PROBE783_MU_CNT => 1,
C_PROBE784_MU_CNT => 1,
C_PROBE785_MU_CNT => 1,
C_PROBE786_MU_CNT => 1,
C_PROBE787_MU_CNT => 1,
C_PROBE788_MU_CNT => 1,
C_PROBE789_MU_CNT => 1,
C_PROBE790_MU_CNT => 1,
C_PROBE791_MU_CNT => 1,
C_PROBE792_MU_CNT => 1,
C_PROBE793_MU_CNT => 1,
C_PROBE794_MU_CNT => 1,
C_PROBE795_MU_CNT => 1,
C_PROBE796_MU_CNT => 1,
C_PROBE797_MU_CNT => 1,
C_PROBE798_MU_CNT => 1,
C_PROBE799_MU_CNT => 1,
C_PROBE800_MU_CNT => 1,
C_PROBE801_MU_CNT => 1,
C_PROBE802_MU_CNT => 1,
C_PROBE803_MU_CNT => 1,
C_PROBE804_MU_CNT => 1,
C_PROBE805_MU_CNT => 1,
C_PROBE806_MU_CNT => 1,
C_PROBE807_MU_CNT => 1,
C_PROBE808_MU_CNT => 1,
C_PROBE809_MU_CNT => 1,
C_PROBE810_MU_CNT => 1,
C_PROBE811_MU_CNT => 1,
C_PROBE812_MU_CNT => 1,
C_PROBE813_MU_CNT => 1,
C_PROBE814_MU_CNT => 1,
C_PROBE815_MU_CNT => 1,
C_PROBE816_MU_CNT => 1,
C_PROBE817_MU_CNT => 1,
C_PROBE818_MU_CNT => 1,
C_PROBE819_MU_CNT => 1,
C_PROBE820_MU_CNT => 1,
C_PROBE821_MU_CNT => 1,
C_PROBE822_MU_CNT => 1,
C_PROBE823_MU_CNT => 1,
C_PROBE824_MU_CNT => 1,
C_PROBE825_MU_CNT => 1,
C_PROBE826_MU_CNT => 1,
C_PROBE827_MU_CNT => 1,
C_PROBE828_MU_CNT => 1,
C_PROBE829_MU_CNT => 1,
C_PROBE830_MU_CNT => 1,
C_PROBE831_MU_CNT => 1,
C_PROBE832_MU_CNT => 1,
C_PROBE833_MU_CNT => 1,
C_PROBE834_MU_CNT => 1,
C_PROBE835_MU_CNT => 1,
C_PROBE836_MU_CNT => 1,
C_PROBE837_MU_CNT => 1,
C_PROBE838_MU_CNT => 1,
C_PROBE839_MU_CNT => 1,
C_PROBE840_MU_CNT => 1,
C_PROBE841_MU_CNT => 1,
C_PROBE842_MU_CNT => 1,
C_PROBE843_MU_CNT => 1,
C_PROBE844_MU_CNT => 1,
C_PROBE845_MU_CNT => 1,
C_PROBE846_MU_CNT => 1,
C_PROBE847_MU_CNT => 1,
C_PROBE848_MU_CNT => 1,
C_PROBE849_MU_CNT => 1,
C_PROBE850_MU_CNT => 1,
C_PROBE851_MU_CNT => 1,
C_PROBE852_MU_CNT => 1,
C_PROBE853_MU_CNT => 1,
C_PROBE854_MU_CNT => 1,
C_PROBE855_MU_CNT => 1,
C_PROBE856_MU_CNT => 1,
C_PROBE857_MU_CNT => 1,
C_PROBE858_MU_CNT => 1,
C_PROBE859_MU_CNT => 1,
C_PROBE860_MU_CNT => 1,
C_PROBE861_MU_CNT => 1,
C_PROBE862_MU_CNT => 1,
C_PROBE863_MU_CNT => 1,
C_PROBE864_MU_CNT => 1,
C_PROBE865_MU_CNT => 1,
C_PROBE866_MU_CNT => 1,
C_PROBE867_MU_CNT => 1,
C_PROBE868_MU_CNT => 1,
C_PROBE869_MU_CNT => 1,
C_PROBE870_MU_CNT => 1,
C_PROBE871_MU_CNT => 1,
C_PROBE872_MU_CNT => 1,
C_PROBE873_MU_CNT => 1,
C_PROBE874_MU_CNT => 1,
C_PROBE875_MU_CNT => 1,
C_PROBE876_MU_CNT => 1,
C_PROBE877_MU_CNT => 1,
C_PROBE878_MU_CNT => 1,
C_PROBE879_MU_CNT => 1,
C_PROBE880_MU_CNT => 1,
C_PROBE881_MU_CNT => 1,
C_PROBE882_MU_CNT => 1,
C_PROBE883_MU_CNT => 1,
C_PROBE884_MU_CNT => 1,
C_PROBE885_MU_CNT => 1,
C_PROBE886_MU_CNT => 1,
C_PROBE887_MU_CNT => 1,
C_PROBE888_MU_CNT => 1,
C_PROBE889_MU_CNT => 1,
C_PROBE890_MU_CNT => 1,
C_PROBE891_MU_CNT => 1,
C_PROBE892_MU_CNT => 1,
C_PROBE893_MU_CNT => 1,
C_PROBE894_MU_CNT => 1,
C_PROBE895_MU_CNT => 1,
C_PROBE896_MU_CNT => 1,
C_PROBE897_MU_CNT => 1,
C_PROBE898_MU_CNT => 1,
C_PROBE899_MU_CNT => 1,
C_PROBE900_MU_CNT => 1,
C_PROBE901_MU_CNT => 1,
C_PROBE902_MU_CNT => 1,
C_PROBE903_MU_CNT => 1,
C_PROBE904_MU_CNT => 1,
C_PROBE905_MU_CNT => 1,
C_PROBE906_MU_CNT => 1,
C_PROBE907_MU_CNT => 1,
C_PROBE908_MU_CNT => 1,
C_PROBE909_MU_CNT => 1,
C_PROBE910_MU_CNT => 1,
C_PROBE911_MU_CNT => 1,
C_PROBE912_MU_CNT => 1,
C_PROBE913_MU_CNT => 1,
C_PROBE914_MU_CNT => 1,
C_PROBE915_MU_CNT => 1,
C_PROBE916_MU_CNT => 1,
C_PROBE917_MU_CNT => 1,
C_PROBE918_MU_CNT => 1,
C_PROBE919_MU_CNT => 1,
C_PROBE920_MU_CNT => 1,
C_PROBE921_MU_CNT => 1,
C_PROBE922_MU_CNT => 1,
C_PROBE923_MU_CNT => 1,
C_PROBE924_MU_CNT => 1,
C_PROBE925_MU_CNT => 1,
C_PROBE926_MU_CNT => 1,
C_PROBE927_MU_CNT => 1,
C_PROBE928_MU_CNT => 1,
C_PROBE929_MU_CNT => 1,
C_PROBE930_MU_CNT => 1,
C_PROBE931_MU_CNT => 1,
C_PROBE932_MU_CNT => 1,
C_PROBE933_MU_CNT => 1,
C_PROBE934_MU_CNT => 1,
C_PROBE935_MU_CNT => 1,
C_PROBE936_MU_CNT => 1,
C_PROBE937_MU_CNT => 1,
C_PROBE938_MU_CNT => 1,
C_PROBE939_MU_CNT => 1,
C_PROBE940_MU_CNT => 1,
C_PROBE941_MU_CNT => 1,
C_PROBE942_MU_CNT => 1,
C_PROBE943_MU_CNT => 1,
C_PROBE944_MU_CNT => 1,
C_PROBE945_MU_CNT => 1,
C_PROBE946_MU_CNT => 1,
C_PROBE947_MU_CNT => 1,
C_PROBE948_MU_CNT => 1,
C_PROBE949_MU_CNT => 1,
C_PROBE950_MU_CNT => 1,
C_PROBE951_MU_CNT => 1,
C_PROBE952_MU_CNT => 1,
C_PROBE953_MU_CNT => 1,
C_PROBE954_MU_CNT => 1,
C_PROBE955_MU_CNT => 1,
C_PROBE956_MU_CNT => 1,
C_PROBE957_MU_CNT => 1,
C_PROBE958_MU_CNT => 1,
C_PROBE959_MU_CNT => 1,
C_PROBE960_MU_CNT => 1,
C_PROBE961_MU_CNT => 1,
C_PROBE962_MU_CNT => 1,
C_PROBE963_MU_CNT => 1,
C_PROBE964_MU_CNT => 1,
C_PROBE965_MU_CNT => 1,
C_PROBE966_MU_CNT => 1,
C_PROBE967_MU_CNT => 1,
C_PROBE968_MU_CNT => 1,
C_PROBE969_MU_CNT => 1,
C_PROBE970_MU_CNT => 1,
C_PROBE971_MU_CNT => 1,
C_PROBE972_MU_CNT => 1,
C_PROBE973_MU_CNT => 1,
C_PROBE974_MU_CNT => 1,
C_PROBE975_MU_CNT => 1,
C_PROBE976_MU_CNT => 1,
C_PROBE977_MU_CNT => 1,
C_PROBE978_MU_CNT => 1,
C_PROBE979_MU_CNT => 1,
C_PROBE980_MU_CNT => 1,
C_PROBE981_MU_CNT => 1,
C_PROBE982_MU_CNT => 1,
C_PROBE983_MU_CNT => 1,
C_PROBE984_MU_CNT => 1,
C_PROBE985_MU_CNT => 1,
C_PROBE986_MU_CNT => 1,
C_PROBE987_MU_CNT => 1,
C_PROBE988_MU_CNT => 1,
C_PROBE989_MU_CNT => 1,
C_PROBE990_MU_CNT => 1,
C_PROBE991_MU_CNT => 1,
C_PROBE992_MU_CNT => 1,
C_PROBE993_MU_CNT => 1,
C_PROBE994_MU_CNT => 1,
C_PROBE995_MU_CNT => 1,
C_PROBE996_MU_CNT => 1,
C_PROBE997_MU_CNT => 1,
C_PROBE998_MU_CNT => 1,
C_PROBE999_MU_CNT => 1,
C_PROBE1000_MU_CNT => 1,
C_PROBE1001_MU_CNT => 1,
C_PROBE1002_MU_CNT => 1,
C_PROBE1003_MU_CNT => 1,
C_PROBE1004_MU_CNT => 1,
C_PROBE1005_MU_CNT => 1,
C_PROBE1006_MU_CNT => 1,
C_PROBE1007_MU_CNT => 1,
C_PROBE1008_MU_CNT => 1,
C_PROBE1009_MU_CNT => 1,
C_PROBE1010_MU_CNT => 1,
C_PROBE1011_MU_CNT => 1,
C_PROBE1012_MU_CNT => 1,
C_PROBE1013_MU_CNT => 1,
C_PROBE1014_MU_CNT => 1,
C_PROBE1015_MU_CNT => 1,
C_PROBE1016_MU_CNT => 1,
C_PROBE1017_MU_CNT => 1,
C_PROBE1018_MU_CNT => 1,
C_PROBE1019_MU_CNT => 1,
C_PROBE1020_MU_CNT => 1,
C_PROBE1021_MU_CNT => 1,
C_PROBE1022_MU_CNT => 1,
C_PROBE1023_MU_CNT => 1,
C_PROBE0_TYPE => 0,
C_PROBE1_TYPE => 0,
C_PROBE2_TYPE => 0,
C_PROBE3_TYPE => 0,
C_PROBE4_TYPE => 0,
C_PROBE5_TYPE => 0,
C_PROBE6_TYPE => 0,
C_PROBE7_TYPE => 0,
C_PROBE8_TYPE => 0,
C_PROBE9_TYPE => 1,
C_PROBE10_TYPE => 1,
C_PROBE11_TYPE => 1,
C_PROBE12_TYPE => 1,
C_PROBE13_TYPE => 1,
C_PROBE14_TYPE => 1,
C_PROBE15_TYPE => 1,
C_PROBE16_TYPE => 1,
C_PROBE17_TYPE => 1,
C_PROBE18_TYPE => 1,
C_PROBE19_TYPE => 1,
C_PROBE20_TYPE => 1,
C_PROBE21_TYPE => 1,
C_PROBE22_TYPE => 1,
C_PROBE23_TYPE => 1,
C_PROBE24_TYPE => 1,
C_PROBE25_TYPE => 1,
C_PROBE26_TYPE => 1,
C_PROBE27_TYPE => 1,
C_PROBE28_TYPE => 1,
C_PROBE29_TYPE => 1,
C_PROBE30_TYPE => 1,
C_PROBE31_TYPE => 1,
C_PROBE32_TYPE => 1,
C_PROBE33_TYPE => 1,
C_PROBE34_TYPE => 1,
C_PROBE35_TYPE => 1,
C_PROBE36_TYPE => 1,
C_PROBE37_TYPE => 1,
C_PROBE38_TYPE => 1,
C_PROBE39_TYPE => 1,
C_PROBE40_TYPE => 1,
C_PROBE41_TYPE => 1,
C_PROBE42_TYPE => 1,
C_PROBE43_TYPE => 1,
C_PROBE44_TYPE => 1,
C_PROBE45_TYPE => 1,
C_PROBE46_TYPE => 1,
C_PROBE47_TYPE => 1,
C_PROBE48_TYPE => 1,
C_PROBE49_TYPE => 1,
C_PROBE50_TYPE => 1,
C_PROBE51_TYPE => 1,
C_PROBE52_TYPE => 1,
C_PROBE53_TYPE => 1,
C_PROBE54_TYPE => 1,
C_PROBE55_TYPE => 1,
C_PROBE56_TYPE => 1,
C_PROBE57_TYPE => 1,
C_PROBE58_TYPE => 1,
C_PROBE59_TYPE => 1,
C_PROBE60_TYPE => 1,
C_PROBE61_TYPE => 1,
C_PROBE62_TYPE => 1,
C_PROBE63_TYPE => 1,
C_PROBE64_TYPE => 1,
C_PROBE65_TYPE => 1,
C_PROBE66_TYPE => 1,
C_PROBE67_TYPE => 1,
C_PROBE68_TYPE => 1,
C_PROBE69_TYPE => 1,
C_PROBE70_TYPE => 1,
C_PROBE71_TYPE => 1,
C_PROBE72_TYPE => 1,
C_PROBE73_TYPE => 1,
C_PROBE74_TYPE => 1,
C_PROBE75_TYPE => 1,
C_PROBE76_TYPE => 1,
C_PROBE77_TYPE => 1,
C_PROBE78_TYPE => 1,
C_PROBE79_TYPE => 1,
C_PROBE80_TYPE => 1,
C_PROBE81_TYPE => 1,
C_PROBE82_TYPE => 1,
C_PROBE83_TYPE => 1,
C_PROBE84_TYPE => 1,
C_PROBE85_TYPE => 1,
C_PROBE86_TYPE => 1,
C_PROBE87_TYPE => 1,
C_PROBE88_TYPE => 1,
C_PROBE89_TYPE => 1,
C_PROBE90_TYPE => 1,
C_PROBE91_TYPE => 1,
C_PROBE92_TYPE => 1,
C_PROBE93_TYPE => 1,
C_PROBE94_TYPE => 1,
C_PROBE95_TYPE => 1,
C_PROBE96_TYPE => 1,
C_PROBE97_TYPE => 1,
C_PROBE98_TYPE => 1,
C_PROBE99_TYPE => 1,
C_PROBE100_TYPE => 1,
C_PROBE101_TYPE => 1,
C_PROBE102_TYPE => 1,
C_PROBE103_TYPE => 1,
C_PROBE104_TYPE => 1,
C_PROBE105_TYPE => 1,
C_PROBE106_TYPE => 1,
C_PROBE107_TYPE => 1,
C_PROBE108_TYPE => 1,
C_PROBE109_TYPE => 1,
C_PROBE110_TYPE => 1,
C_PROBE111_TYPE => 1,
C_PROBE112_TYPE => 1,
C_PROBE113_TYPE => 1,
C_PROBE114_TYPE => 1,
C_PROBE115_TYPE => 1,
C_PROBE116_TYPE => 1,
C_PROBE117_TYPE => 1,
C_PROBE118_TYPE => 1,
C_PROBE119_TYPE => 1,
C_PROBE120_TYPE => 1,
C_PROBE121_TYPE => 1,
C_PROBE122_TYPE => 1,
C_PROBE123_TYPE => 1,
C_PROBE124_TYPE => 1,
C_PROBE125_TYPE => 1,
C_PROBE126_TYPE => 1,
C_PROBE127_TYPE => 1,
C_PROBE128_TYPE => 1,
C_PROBE129_TYPE => 1,
C_PROBE130_TYPE => 1,
C_PROBE131_TYPE => 1,
C_PROBE132_TYPE => 1,
C_PROBE133_TYPE => 1,
C_PROBE134_TYPE => 1,
C_PROBE135_TYPE => 1,
C_PROBE136_TYPE => 1,
C_PROBE137_TYPE => 1,
C_PROBE138_TYPE => 1,
C_PROBE139_TYPE => 1,
C_PROBE140_TYPE => 1,
C_PROBE141_TYPE => 1,
C_PROBE142_TYPE => 1,
C_PROBE143_TYPE => 1,
C_PROBE144_TYPE => 1,
C_PROBE145_TYPE => 1,
C_PROBE146_TYPE => 1,
C_PROBE147_TYPE => 1,
C_PROBE148_TYPE => 1,
C_PROBE149_TYPE => 1,
C_PROBE150_TYPE => 1,
C_PROBE151_TYPE => 1,
C_PROBE152_TYPE => 1,
C_PROBE153_TYPE => 1,
C_PROBE154_TYPE => 1,
C_PROBE155_TYPE => 1,
C_PROBE156_TYPE => 1,
C_PROBE157_TYPE => 1,
C_PROBE158_TYPE => 1,
C_PROBE159_TYPE => 1,
C_PROBE160_TYPE => 1,
C_PROBE161_TYPE => 1,
C_PROBE162_TYPE => 1,
C_PROBE163_TYPE => 1,
C_PROBE164_TYPE => 1,
C_PROBE165_TYPE => 1,
C_PROBE166_TYPE => 1,
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C_PROBE844_TYPE => 1,
C_PROBE845_TYPE => 1,
C_PROBE846_TYPE => 1,
C_PROBE847_TYPE => 1,
C_PROBE848_TYPE => 1,
C_PROBE849_TYPE => 1,
C_PROBE850_TYPE => 1,
C_PROBE851_TYPE => 1,
C_PROBE852_TYPE => 1,
C_PROBE853_TYPE => 1,
C_PROBE854_TYPE => 1,
C_PROBE855_TYPE => 1,
C_PROBE856_TYPE => 1,
C_PROBE857_TYPE => 1,
C_PROBE858_TYPE => 1,
C_PROBE859_TYPE => 1,
C_PROBE860_TYPE => 1,
C_PROBE861_TYPE => 1,
C_PROBE862_TYPE => 1,
C_PROBE863_TYPE => 1,
C_PROBE864_TYPE => 1,
C_PROBE865_TYPE => 1,
C_PROBE866_TYPE => 1,
C_PROBE867_TYPE => 1,
C_PROBE868_TYPE => 1,
C_PROBE869_TYPE => 1,
C_PROBE870_TYPE => 1,
C_PROBE871_TYPE => 1,
C_PROBE872_TYPE => 1,
C_PROBE873_TYPE => 1,
C_PROBE874_TYPE => 1,
C_PROBE875_TYPE => 1,
C_PROBE876_TYPE => 1,
C_PROBE877_TYPE => 1,
C_PROBE878_TYPE => 1,
C_PROBE879_TYPE => 1,
C_PROBE880_TYPE => 1,
C_PROBE881_TYPE => 1,
C_PROBE882_TYPE => 1,
C_PROBE883_TYPE => 1,
C_PROBE884_TYPE => 1,
C_PROBE885_TYPE => 1,
C_PROBE886_TYPE => 1,
C_PROBE887_TYPE => 1,
C_PROBE888_TYPE => 1,
C_PROBE889_TYPE => 1,
C_PROBE890_TYPE => 1,
C_PROBE891_TYPE => 1,
C_PROBE892_TYPE => 1,
C_PROBE893_TYPE => 1,
C_PROBE894_TYPE => 1,
C_PROBE895_TYPE => 1,
C_PROBE896_TYPE => 1,
C_PROBE897_TYPE => 1,
C_PROBE898_TYPE => 1,
C_PROBE899_TYPE => 1,
C_PROBE900_TYPE => 1,
C_PROBE901_TYPE => 1,
C_PROBE902_TYPE => 1,
C_PROBE903_TYPE => 1,
C_PROBE904_TYPE => 1,
C_PROBE905_TYPE => 1,
C_PROBE906_TYPE => 1,
C_PROBE907_TYPE => 1,
C_PROBE908_TYPE => 1,
C_PROBE909_TYPE => 1,
C_PROBE910_TYPE => 1,
C_PROBE911_TYPE => 1,
C_PROBE912_TYPE => 1,
C_PROBE913_TYPE => 1,
C_PROBE914_TYPE => 1,
C_PROBE915_TYPE => 1,
C_PROBE916_TYPE => 1,
C_PROBE917_TYPE => 1,
C_PROBE918_TYPE => 1,
C_PROBE919_TYPE => 1,
C_PROBE920_TYPE => 1,
C_PROBE921_TYPE => 1,
C_PROBE922_TYPE => 1,
C_PROBE923_TYPE => 1,
C_PROBE924_TYPE => 1,
C_PROBE925_TYPE => 1,
C_PROBE926_TYPE => 1,
C_PROBE927_TYPE => 1,
C_PROBE928_TYPE => 1,
C_PROBE929_TYPE => 1,
C_PROBE930_TYPE => 1,
C_PROBE931_TYPE => 1,
C_PROBE932_TYPE => 1,
C_PROBE933_TYPE => 1,
C_PROBE934_TYPE => 1,
C_PROBE935_TYPE => 1,
C_PROBE936_TYPE => 1,
C_PROBE937_TYPE => 1,
C_PROBE938_TYPE => 1,
C_PROBE939_TYPE => 1,
C_PROBE940_TYPE => 1,
C_PROBE941_TYPE => 1,
C_PROBE942_TYPE => 1,
C_PROBE943_TYPE => 1,
C_PROBE944_TYPE => 1,
C_PROBE945_TYPE => 1,
C_PROBE946_TYPE => 1,
C_PROBE947_TYPE => 1,
C_PROBE948_TYPE => 1,
C_PROBE949_TYPE => 1,
C_PROBE950_TYPE => 1,
C_PROBE951_TYPE => 1,
C_PROBE952_TYPE => 1,
C_PROBE953_TYPE => 1,
C_PROBE954_TYPE => 1,
C_PROBE955_TYPE => 1,
C_PROBE956_TYPE => 1,
C_PROBE957_TYPE => 1,
C_PROBE958_TYPE => 1,
C_PROBE959_TYPE => 1,
C_PROBE960_TYPE => 1,
C_PROBE961_TYPE => 1,
C_PROBE962_TYPE => 1,
C_PROBE963_TYPE => 1,
C_PROBE964_TYPE => 1,
C_PROBE965_TYPE => 1,
C_PROBE966_TYPE => 1,
C_PROBE967_TYPE => 1,
C_PROBE968_TYPE => 1,
C_PROBE969_TYPE => 1,
C_PROBE970_TYPE => 1,
C_PROBE971_TYPE => 1,
C_PROBE972_TYPE => 1,
C_PROBE973_TYPE => 1,
C_PROBE974_TYPE => 1,
C_PROBE975_TYPE => 1,
C_PROBE976_TYPE => 1,
C_PROBE977_TYPE => 1,
C_PROBE978_TYPE => 1,
C_PROBE979_TYPE => 1,
C_PROBE980_TYPE => 1,
C_PROBE981_TYPE => 1,
C_PROBE982_TYPE => 1,
C_PROBE983_TYPE => 1,
C_PROBE984_TYPE => 1,
C_PROBE985_TYPE => 1,
C_PROBE986_TYPE => 1,
C_PROBE987_TYPE => 1,
C_PROBE988_TYPE => 1,
C_PROBE989_TYPE => 1,
C_PROBE990_TYPE => 1,
C_PROBE991_TYPE => 1,
C_PROBE992_TYPE => 1,
C_PROBE993_TYPE => 1,
C_PROBE994_TYPE => 1,
C_PROBE995_TYPE => 1,
C_PROBE996_TYPE => 1,
C_PROBE997_TYPE => 1,
C_PROBE998_TYPE => 1,
C_PROBE999_TYPE => 1,
C_PROBE1000_TYPE => 1,
C_PROBE1001_TYPE => 1,
C_PROBE1002_TYPE => 1,
C_PROBE1003_TYPE => 1,
C_PROBE1004_TYPE => 1,
C_PROBE1005_TYPE => 1,
C_PROBE1006_TYPE => 1,
C_PROBE1007_TYPE => 1,
C_PROBE1008_TYPE => 1,
C_PROBE1009_TYPE => 1,
C_PROBE1010_TYPE => 1,
C_PROBE1011_TYPE => 1,
C_PROBE1012_TYPE => 1,
C_PROBE1013_TYPE => 1,
C_PROBE1014_TYPE => 1,
C_PROBE1015_TYPE => 1,
C_PROBE1016_TYPE => 1,
C_PROBE1017_TYPE => 1,
C_PROBE1018_TYPE => 1,
C_PROBE1019_TYPE => 1,
C_PROBE1020_TYPE => 1,
C_PROBE1021_TYPE => 1,
C_PROBE1022_TYPE => 1,
C_PROBE1023_TYPE => 1
)
PORT MAP (
clk => clk,
sl_iport0 => sl_iport0,
sl_oport0 => sl_oport0,
trig_out => open,
trig_out_ack => '0',
trig_in => '0',
trig_in_ack => open,
probe0 => probe0,
probe1 => probe1,
probe2 => probe2,
probe3 => probe3,
probe4 => probe4,
probe5 => probe5,
probe6 => probe6,
probe7 => probe7,
probe8 => probe8,
probe9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe32 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe33 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe34 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe35 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe36 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe37 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe38 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe39 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe40 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe41 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe42 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe43 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe44 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe45 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe46 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe47 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe48 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe49 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe50 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe51 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe52 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe53 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe54 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe55 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe56 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe57 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe58 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe59 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe60 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe61 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe62 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe63 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe64 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe65 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe66 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe67 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe68 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe69 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe70 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe71 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe72 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe73 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe74 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe75 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe76 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe77 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe78 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe79 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe80 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe81 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe82 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe83 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe84 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe85 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe86 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe87 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe88 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe89 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe90 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe91 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe92 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe93 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe94 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe95 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe96 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe97 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe98 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe99 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe100 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe101 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe102 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe103 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe104 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe105 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe106 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe107 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe108 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe109 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe110 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe111 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe112 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe113 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe114 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe115 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe116 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe117 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe118 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe119 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe120 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe121 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe122 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe123 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe124 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe125 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe126 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe127 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe128 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe129 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe130 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe131 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe132 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe133 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe134 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe135 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe136 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe137 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe138 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe139 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe140 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe141 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe142 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe143 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe144 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe145 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe146 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe147 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe148 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe149 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe150 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe151 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe152 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe153 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe154 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe155 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe156 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe157 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe158 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe159 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe160 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe161 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe162 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe163 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe164 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe165 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe166 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe167 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe168 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe169 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe170 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe171 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe172 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe173 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe174 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe175 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe176 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe177 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe178 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe179 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe180 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe181 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe182 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe183 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe184 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe185 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe186 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe187 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe188 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe189 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe190 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe191 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe192 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe193 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe194 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe195 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe196 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe197 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe198 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe199 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe200 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe201 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe202 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe203 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe204 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe205 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe206 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe207 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe208 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe209 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe210 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe211 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe212 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe213 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe214 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe215 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe216 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe217 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe218 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe219 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe220 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe221 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe222 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe223 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe224 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe225 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe226 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe227 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe228 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe229 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe230 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe231 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe232 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe233 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe234 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe235 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe236 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe237 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe238 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe239 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe240 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe241 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe242 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe243 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe244 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe245 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe246 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe247 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe248 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe249 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe250 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe251 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe252 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe253 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe254 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe255 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe256 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe257 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe258 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe259 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe260 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe261 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe262 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe263 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe264 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe265 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe266 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe267 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe268 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe269 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe270 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe271 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe272 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe273 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe274 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe275 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe276 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe277 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe278 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe279 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe280 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe281 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe282 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe283 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe284 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe285 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe286 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe287 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe288 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe289 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe290 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe291 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe292 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe293 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe294 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe295 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe296 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe297 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe298 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe299 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe300 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe301 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe302 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe303 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe304 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe305 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe306 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe307 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe308 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe309 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe310 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe311 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe312 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe313 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe314 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe315 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe316 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe317 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe318 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe319 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe320 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe321 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe322 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe323 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe324 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe325 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe326 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe327 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe328 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe329 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe330 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe331 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe332 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe333 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe334 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe335 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe336 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe337 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe338 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe339 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe340 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe341 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe342 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe343 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe344 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe345 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe346 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe347 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe348 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe349 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe350 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe351 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe352 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe353 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe354 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe355 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe356 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe357 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe358 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe359 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe360 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe361 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe362 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe363 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe364 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe365 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe366 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe367 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe368 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe369 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe370 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe371 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe372 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe373 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe374 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe375 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe376 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe377 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe378 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe379 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe380 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe381 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe382 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe383 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe384 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe385 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe386 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe387 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe388 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe389 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe390 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe391 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe392 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe393 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe394 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe395 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe396 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe397 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe398 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe399 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe400 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe401 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe402 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe403 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe404 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe405 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe406 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe407 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe408 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe409 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe410 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe411 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe412 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe413 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe414 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe415 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe416 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe417 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe418 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe419 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe420 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe421 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe422 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe423 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe424 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe425 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe426 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe427 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe428 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe429 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe430 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe431 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe432 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe433 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe434 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe435 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe436 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe437 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe438 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe439 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe440 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe441 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe442 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe443 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe444 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe445 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe446 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe447 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe448 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe449 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe450 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe451 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe452 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe453 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe454 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe455 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe456 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe457 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe458 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe459 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe460 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe461 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe462 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe463 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe464 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe465 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe466 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe467 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe468 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe469 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe470 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe471 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe472 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe473 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe474 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe475 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe476 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe477 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe478 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe479 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe480 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe481 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe482 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe483 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe484 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe485 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe486 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe487 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe488 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe489 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe490 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe491 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe492 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe493 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe494 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe495 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe496 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe497 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe498 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe499 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe500 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe501 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe502 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe503 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe504 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe505 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe506 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe507 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe508 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe509 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe510 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe511 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe512 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe513 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe514 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe515 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe516 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe517 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe518 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe519 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe520 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe521 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe522 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe523 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe524 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe525 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe526 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe527 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe528 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe529 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe530 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe531 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe532 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe533 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe534 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe535 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe536 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe537 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe538 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe539 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe540 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe541 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe542 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe543 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe544 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe545 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe546 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe547 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe548 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe549 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe550 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe551 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe552 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe553 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe554 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe555 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe556 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe557 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe558 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe559 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe560 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe561 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe562 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe563 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe564 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe565 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe566 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe567 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe568 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe569 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe570 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe571 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe572 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe573 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe574 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe575 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe576 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe577 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe578 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe579 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe580 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe581 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe582 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe583 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe584 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe585 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe586 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe587 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe588 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe589 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe590 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe591 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe592 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe593 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe594 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe595 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe596 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe597 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe598 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe599 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe600 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe601 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe602 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe603 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe604 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe605 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe606 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe607 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe608 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe609 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe610 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe611 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe612 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe613 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe614 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe615 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe616 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe617 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe618 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe619 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe620 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe621 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe622 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe623 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe624 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe625 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe626 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe627 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe628 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe629 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe630 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe631 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe632 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe633 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe634 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe635 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe636 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe637 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe638 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe639 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe640 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe641 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe642 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe643 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe644 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe645 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe646 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe647 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe648 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe649 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe650 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe651 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe652 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe653 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe654 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe655 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe656 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe657 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe658 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe659 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe660 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe661 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe662 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe663 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe664 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe665 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe666 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe667 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe668 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe669 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe670 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe671 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe672 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe673 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe674 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe675 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe676 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe677 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe678 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe679 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe680 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe681 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe682 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe683 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe684 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe685 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe686 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe687 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe688 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe689 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe690 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe691 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe692 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe693 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe694 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe695 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe696 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe697 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe698 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe699 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe700 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe701 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe702 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe703 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe704 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe705 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe706 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe707 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe708 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe709 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe710 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe711 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe712 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe713 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe714 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe715 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe716 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe717 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe718 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe719 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe720 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe721 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe722 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe723 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe724 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe725 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe726 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe727 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe728 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe729 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe730 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe731 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe732 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe733 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe734 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe735 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe736 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe737 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe738 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe739 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe740 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe741 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe742 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe743 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe744 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe745 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe746 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe747 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe748 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe749 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe750 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe751 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe752 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe753 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe754 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe755 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe756 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe757 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe758 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe759 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe760 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe761 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe762 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe763 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe764 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe765 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe766 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe767 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe768 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe769 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe770 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe771 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe772 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe773 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe774 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe775 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe776 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe777 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe778 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe779 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe780 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe781 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe782 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe783 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe784 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe785 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe786 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe787 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe788 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe789 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe790 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe791 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe792 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe793 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe794 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe795 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe796 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe797 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe798 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe799 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe800 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe801 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe802 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe803 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe804 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe805 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe806 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe807 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe808 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe809 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe810 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe811 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe812 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe813 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe814 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe815 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe816 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe817 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe818 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe819 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe820 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe821 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe822 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe823 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe824 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe825 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe826 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe827 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe828 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe829 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe830 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe831 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe832 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe833 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe834 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe835 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe836 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe837 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe838 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe839 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe840 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe841 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe842 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe843 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe844 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe845 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe846 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe847 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe848 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe849 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe850 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe851 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe852 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe853 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe854 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe855 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe856 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe857 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe858 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe859 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe860 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe861 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe862 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe863 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe864 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe865 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe866 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe867 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe868 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe869 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe870 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe871 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe872 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe873 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe874 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe875 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe876 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe877 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe878 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe879 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe880 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe881 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe882 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe883 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe884 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe885 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe886 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe887 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe888 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe889 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe890 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe891 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe892 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe893 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe894 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe895 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe896 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe897 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe898 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe899 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe900 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe901 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe902 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe903 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe904 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe905 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe906 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe907 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe908 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe909 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe910 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe911 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe912 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe913 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe914 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe915 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe916 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe917 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe918 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe919 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe920 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe921 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe922 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe923 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe924 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe925 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe926 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe927 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe928 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe929 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe930 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe931 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe932 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe933 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe934 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe935 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe936 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe937 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe938 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe939 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe940 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe941 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe942 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe943 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe944 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe945 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe946 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe947 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe948 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe949 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe950 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe951 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe952 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe953 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe954 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe955 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe956 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe957 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe958 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe959 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe960 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe961 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe962 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe963 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe964 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe965 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe966 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe967 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe968 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe969 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe970 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe971 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe972 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe973 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe974 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe975 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe976 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe977 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe978 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe979 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe980 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe981 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe982 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe983 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe984 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe985 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe986 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe987 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe988 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe989 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe990 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe991 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe992 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe993 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe994 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe995 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe996 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe997 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe998 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe999 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1000 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1001 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1002 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1003 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1004 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1005 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1006 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1007 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1008 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1009 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1010 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1011 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1012 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1013 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1014 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1015 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1016 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1017 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1018 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1019 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1020 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1021 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1022 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1023 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1))
);
END design_1_ila_0_0_arch;
| gpl-3.0 | f28030cd11851d32c6d3a2f9965231bc | 0.711901 | 2.406081 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/extend_mask.vhd | 2 | 1,609 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity extend_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(20 downto 0)
);
end extend_mask;
architecture augh of extend_mask is
-- Embedded RAM
type ram_type is array (0 to 19) of std_logic_vector(20 downto 0);
signal ram : ram_type := (
"111111111111111111110", "111111111111111111100", "111111111111111111000", "111111111111111110000",
"111111111111111100000", "111111111111111000000", "111111111111110000000", "111111111111100000000",
"111111111111000000000", "111111111110000000000", "111111111100000000000", "111111111000000000000",
"111111110000000000000", "111111100000000000000", "111111000000000000000", "111110000000000000000",
"111100000000000000000", "111000000000000000000", "110000000000000000000", "100000000000000000000"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 20 else (others => '-');
end architecture;
| gpl-2.0 | 5e4dfdcdf9038edccd385fa53e0e660d | 0.73151 | 3.544053 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | RCA/8bits/RCA/Reg1Bit.vhd | 14 | 470 | library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg1Bit is
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end Reg1Bit;
architecture strc_Reg1Bit of Reg1Bit is
signal Temp: std_logic;
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= '0';
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg1Bit; | mit | bdd12d59fd0d731eeaaaba95e57638db | 0.665957 | 2.670455 | false | false | false | false |
nickg/nvc | test/parse/issue443.vhd | 1 | 1,522 | package TYPES is
type SHAPE_TYPE is record
ELEM_BITS : integer;
X : integer;
Y : integer;
end record;
function NEW_SHAPE(ELEM_BITS,X,Y: integer) return SHAPE_TYPE;
type STRIDE_TYPE is record
X : integer;
Y : integer;
end record;
function NEW_STRIDE(X,Y:integer) return STRIDE_TYPE;
type PARAM_TYPE is record
ELEM_BITS : integer;
INFO_BITS : integer;
STRIDE : STRIDE_TYPE;
SHAPE : SHAPE_TYPE;
end record;
function NEW_PARAM(
ELEM_BITS : integer;
INFO_BITS : integer := 0;
SHAPE : SHAPE_TYPE;
STRIDE : STRIDE_TYPE)
return PARAM_TYPE;
function NEW_PARAM(
ELEM_BITS : integer;
INFO_BITS : integer := 0;
SHAPE : SHAPE_TYPE)
return PARAM_TYPE;
end TYPES;
use WORK.TYPES.all;
entity TEST_NG is
end TEST_NG;
architecture MODEL of TEST_NG is
constant ELEM_BITS : integer := 8;
constant PARAM : PARAM_TYPE
:= NEW_PARAM(
ELEM_BITS => ELEM_BITS,
SHAPE => NEW_SHAPE(ELEM_BITS,3,3)
);
begin
end MODEL;
| gpl-3.0 | 48d59159aac41e1ecc7717c89875a46a | 0.426413 | 4.299435 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load_wa.vhd | 4 | 1,757 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity pwl_load_wa is
generic ( load_enable : boolean := true;
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time );
port ( terminal p1, p2 : electrical );
end entity pwl_load_wa;
----------------------------------------------------------------
architecture ideal of pwl_load_wa is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
if load_enable use
if domain = quiescent_domain or domain = frequency_domain use
v == i * res_init;
else
v == i * res_signal'ramp(1.0e-6, 1.0e-6);
end use;
else
i == 0.0;
end use;
create_event: process is
begin
wait for t1;
res_signal <= res1;
wait for t2 - t1;
res_signal <= res2;
wait;
end process create_event;
end architecture ideal;
| gpl-2.0 | df53040f702d28499b1349b33dfca05b | 0.638589 | 3.930649 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1967.vhd | 4 | 1,773 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1967.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01967ent IS
END c07s02b01x00p02n02i01967ent;
ARCHITECTURE c07s02b01x00p02n02i01967arch OF c07s02b01x00p02n02i01967ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := FALSE;
variable b : boolean := FALSE;
variable c : boolean;
BEGIN
c := a nand b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01967"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01967 - Logical operation of 'NAND'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01967arch;
| gpl-2.0 | 8b421a715824b7e62a1836b2e057e923 | 0.664975 | 3.678423 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd | 4 | 2,038 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity sensor is
generic ( threshold : real; -- voltage threshold
tipd_clk : delay_length; -- input prop delay on clk
tipd_input : real; -- input prop delay on sensor input
topd_q : delay_length ); -- output prop delay on q
port ( terminal input : electrical; -- sensor analog input
signal clk : in bit; -- edgetriggered clock input
signal q : out bit ); -- sensor digital output
end entity sensor;
architecture detailed_timing of sensor is
quantity vin across input; -- analog input values
quantity v_delayed : voltage; -- input voltage delayed
signal clk_delayed : bit; -- clk input port delayed
signal q_int : bit; -- q output with zero delay
begin
input_port_delay : block is
begin
v_delayed == vin'delayed(tipd_input);
clk_delayed <= clk'delayed(tipd_clk);
end block input_port_delay;
AD_conversion : block is
begin
q_int <= '1' when vin'above(threshold) else
'0';
end block AD_conversion;
output_port_delay : block is
begin
q <= q_int'delayed(topd_q);
end block output_port_delay;
end architecture detailed_timing;
| gpl-2.0 | fe3b554017a79e7e093e39ba527702ec | 0.686948 | 4.035644 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/tb_dff15.vhdl | 1 | 722 | entity tb_dff15 is
end tb_dff15;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff15 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff15
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '1' severity failure;
din <= '1';
pulse;
assert dout = '0' severity failure;
pulse;
assert dout = '0' severity failure;
din <= '0';
pulse;
assert dout = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 905b8c69ad23c5329c8c46de258b78b8 | 0.567867 | 3.389671 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug090/crash13.vhdl | 1 | 1,486 | library ieee;
use ieee.std_logic_1164.all;
entity clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic := '0');
end clkgen;
architecture behav of clkgen is
begin
process
begin
clk <= not clk;
wait for period / 2;
end process;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : std_logic;
signal rst_n : std_logic;
signal din, dout, dout2 : std_logic_vector (7 downto 0);
component clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic);
end component;
begin
cclk : clkgen
generic map (period => 20 ns)
port map (clk => clk);
rst_n <= '0' after 0 ns, '1' after 4 ns;
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else q <= d;
end if;
end if;
end process p;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report "start of tb" severity note;
for i in 0 to 10 loop
case i is
when 0 | 3 =>
for i in din'range loop
din(i) <= '0';
end loop;
when 1 => din <= b"00110011";
when 2 => v := 0;
while v < 7 loop
din (v) <= '1';
v := v + 1;
end loop;
when 4 to 5 | 8 => din <= x"a5"; when others =>
null;
end case;
end loop;
wait until clk = '0';
end process;
assert false report "Hello world" severity note;
\nd behav;" | gpl-2.0 | 53b4f7b445668f67b04e2aa04e5d7400 | 0.562584 | 3.369615 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue44/costasloop.vhdl | 2 | 2,198 | -- costasloop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity costasloop is
port(carrier: in signed(11 downto 0);
clk, reset: in std_logic;
op: out std_logic);
end costasloop;
architecture costasloop_arch of costasloop is
component nco is
port(clk, reset: in std_logic;
fword: in unsigned(5 downto 0);
op_sin: out signed(4 downto 0);
op_cos: out signed(4 downto 0));
end component;
component q_one_dot_fp_multiplier is
generic (a_word_size, b_word_size:integer);
port(a: in signed(a_word_size-1 downto 0);
b: in signed(b_word_size-1 downto 0);
mult_out: out signed(a_word_size + b_word_size -2 downto 0));
end component;
component lpf is
port(clk, reset: in std_logic;
x_in: in signed(15 downto 0);
y_out: out signed(19 downto 0));
end component;
component loopfilter is
port(clk, reset: in std_logic;
mult_error_op:in signed(38 downto 0);
f_desired: in unsigned(5 downto 0);
f_word_output: out unsigned(5 downto 0));
end component;
signal nco_input: unsigned(5 downto 0);
signal nco_sin, nco_cos: signed(4 downto 0);
signal mult_sin, mult_cos: signed(15 downto 0);
signal raw_op_sin, raw_op_cos: signed(19 downto 0);
signal mult_error_op: signed(38 downto 0);
begin
--NCO phase multiplier
N: nco port map(clk, reset, nco_input, nco_sin, nco_cos);
--Multiplier
M0: q_one_dot_fp_multiplier generic map(a_word_size=>nco_sin'length, b_word_size => carrier'length) port map(nco_sin, carrier, mult_sin);
M1: q_one_dot_fp_multiplier generic map(a_word_size=>nco_sin'length, b_word_size => carrier'length) port map(nco_cos, carrier, mult_cos);
--FIR Filter
L0: lpf port map(clk, reset, mult_sin, raw_op_sin);
L1: lpf port map(clk, reset, mult_cos, raw_op_cos);
--Extract output (Comparator)
COMPARATOR: op <= raw_op_sin(raw_op_sin'length -1); --Sign bit
--Error Multiplier
EM: q_one_dot_fp_multiplier generic map(a_word_size=>raw_op_sin'length, b_word_size => raw_op_cos'length) port map(raw_op_sin, raw_op_cos, mult_error_op);
--Loop Filter
--NCO mapping to error
LF: loopfilter port map(clk, reset, mult_error_op, to_unsigned(16, 6), nco_input);
end costasloop_arch;
| gpl-2.0 | 1b265db729d7b3e8821db086bc411134 | 0.693813 | 2.796438 | false | false | false | false |
nickg/nvc | test/regress/vecorder1.vhd | 1 | 1,373 | entity vecorder1 is
end entity;
architecture test of vecorder1 is
type int_array is array (integer range <>) of integer;
signal s : int_array(0 to 1) := ( 0 => 0, 1 => 1 );
begin
process is
variable x : int_array(0 to 1) := ( 0 => 0, 1 => 1 );
variable y : int_array(1 downto 0) := ( 0 => 0, 1 => 1 );
begin
assert x(0) = 0 report "one";
assert x(1) = 1 report "two";
assert x = ( 0, 1 );
x := ( 2, 3 );
report integer'image(x(0));
report integer'image(x(1));
assert x(0) = 2 report "three";
assert x(1) = 3 report "four";
assert x = ( 2, 3 ) report "five";
assert ( 2, 3 ) = x report "six";
assert s(0) = 0 report "s one";
assert s(1) = 1 report "s two";
s <= ( 2, 3 );
wait for 0 ns;
report integer'image(s(0));
report integer'image(s(1));
assert s(0) = 2 report "s three";
assert s(1) = 3 report "s four";
assert y(0) = 0 report "y one";
assert y(1) = 1 report "y two";
assert y = ( 1, 0 );
y := ( 2, 3 );
report integer'image(y(0));
report integer'image(y(1));
assert y(0) = 3 report "y three";
assert y(1) = 2 report "y four";
assert y = ( 2, 3 ) report "y five";
wait;
end process;
end architecture;
| gpl-3.0 | e311f76eca227b203763d90b939ea96c | 0.485798 | 3.284689 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/syn/vhdl/doHistStretch_fdiv_32ns_32ns_32_16.vhd | 5 | 3,100 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity doHistStretch_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of doHistStretch_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component doHistStretch_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
doHistStretch_ap_fdiv_14_no_dsp_32_u : component doHistStretch_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 12ea966fe7208ad080e1aef72644ed54 | 0.483226 | 3.68171 | false | false | false | false |
nickg/nvc | test/regress/access3.vhd | 1 | 648 | entity access3 is
end entity;
architecture test of access3 is
type int_ptr is access integer;
type string_ptr is access string;
begin
process is
variable i : int_ptr;
variable s : string_ptr;
begin
i := new integer;
assert i.all = integer'left;
deallocate(i);
i := new integer'(3);
assert i.all = 3;
deallocate(i);
s := new string'("");
assert s.all = "";
assert s'length = 0;
deallocate(s);
s := new string'("hello");
assert s.all = "hello";
deallocate(s);
wait;
end process;
end architecture;
| gpl-3.0 | 4a292929bdce08d64d207827118fcc34 | 0.535494 | 4.024845 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg.vhd | 7 | 84,412 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
dm_resetn : in std_logic ; --
sg_ctl : in std_logic_vector (7 downto 0) ;
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic;
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
ch2_update_active : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic;
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ;
bd_eq : out std_logic
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
signal m_axi_sg_awaddr_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal m_axi_sg_awlen_int : std_logic_vector(7 downto 0) ; --
signal m_axi_sg_awsize_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awburst_int : std_logic_vector(1 downto 0) ; --
signal m_axi_sg_awprot_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awcache_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awuser_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awvalid_int : std_logic ; --
signal m_axi_sg_awready_int : std_logic ; --
--
-- Scatter Gather Write Data Channel --
signal m_axi_sg_wdata_int : std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
signal m_axi_sg_wstrb_int : std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
signal m_axi_sg_wlast_int : std_logic ; --
signal m_axi_sg_wvalid_int : std_logic ; --
signal m_axi_sg_wready_int : std_logic ; --
signal m_axi_sg_bresp_int : std_logic_vector (1 downto 0);
signal m_axi_sg_bvalid_int : std_logic;
signal m_axi_sg_bready_int : std_logic;
signal m_axi_sg_bvalid_int_del : std_logic;
signal ch2_eof_detected : std_logic;
signal s_axis_ch2_updtsts_tready_i : std_logic;
signal ch2_sg_idle, tail_updt_latch : std_logic;
signal tail_updt : std_logic;
signal ch2_taildesc_wren_int : std_logic;
signal ch2_sg_idle_int : std_logic;
signal ftch_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal updt_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch1_ftch_slverr_set_i : std_logic := '0';
signal ch1_ftch_decerr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_slverr_set_i : std_logic := '0';
signal ch2_ftch_decerr_set_i : std_logic := '0';
signal ch1_updt_interr_set_i : std_logic := '0';
signal ch1_updt_slverr_set_i : std_logic := '0';
signal ch1_updt_decerr_set_i : std_logic := '0';
signal ch2_updt_interr_set_i : std_logic := '0';
signal ch2_updt_slverr_set_i : std_logic := '0';
signal ch2_updt_decerr_set_i : std_logic := '0';
signal ftch_error_capture : std_logic := '0';
signal updt_error_capture : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
ftch_error_capture <= ch1_ftch_interr_set_i or
ch1_ftch_slverr_set_i or
ch1_ftch_decerr_set_i or
ch2_ftch_interr_set_i or
ch2_ftch_slverr_set_i or
ch2_ftch_decerr_set_i;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
ch1_ftch_slverr_set <= ch1_ftch_slverr_set_i;
ch1_ftch_decerr_set <= ch1_ftch_decerr_set_i;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
ch2_ftch_slverr_set <= ch2_ftch_slverr_set_i;
ch2_ftch_decerr_set <= ch2_ftch_decerr_set_i;
updt_error_capture <= ch1_updt_interr_set_i or
ch1_updt_slverr_set_i or
ch1_updt_decerr_set_i or
ch2_updt_interr_set_i or
ch2_updt_slverr_set_i or
ch2_updt_decerr_set_i or
ch2_dma_interr_set_i or
ch2_dma_slverr_set_i or
ch2_dma_decerr_set_i or
ch1_dma_interr_set_i or
ch1_dma_slverr_set_i or
ch1_dma_decerr_set_i;
ch1_updt_interr_set <= ch1_updt_interr_set_i;
ch1_updt_slverr_set <= ch1_updt_slverr_set_i;
ch1_updt_decerr_set <= ch1_updt_decerr_set_i;
ch2_updt_interr_set <= ch2_updt_interr_set_i;
ch2_updt_slverr_set <= ch2_updt_slverr_set_i;
ch2_updt_decerr_set <= ch2_updt_decerr_set_i;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (31 downto 6) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (31 downto 6)<= ftch_error_addr_1(31 downto 6);
elsif (updt_error_capture = '1') then
ftch_error_addr (31 downto 6)<= updt_error_addr_1(31 downto 6);
end if;
end if;
end process;
ADDR_64 : if (C_M_AXI_SG_ADDR_WIDTH > 32) generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (63 downto 32) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (63 downto 32)<= ftch_error_addr_1(63 downto 32);
elsif (updt_error_capture = '1') then
ftch_error_addr (63 downto 32)<= updt_error_addr_1(63 downto 32);
end if;
end if;
end process;
end generate ADDR_64;
updt_error_addr <= (others => '0');
ftch_error_addr (5 downto 0) <= (others => '0');
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
s_axis_ch2_updtsts_tready <= s_axis_ch2_updtsts_tready_i;
EOF_DET : if (C_ENABLE_MULTI_CHANNEL = 1) generate
ch2_eof_detected <= s_axis_ch2_updtsts_tdata (26)
and s_axis_ch2_updtsts_tready_i
and s_axis_ch2_updtsts_tvalid
and s_axis_ch2_updtsts_tlast;
-- ch2_eof_detected <= '0';
ch2_sg_idle_int <= ch2_sg_idle;
-- ch2_sg_idle_int <= '0'; --ch2_sg_idle;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or tail_updt = '1' ) then -- nned to have some reset condition here
tail_updt <= '0';
elsif(ch2_sg_idle = '1' and tail_updt_latch = '1' and tail_updt = '0')then
tail_updt <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
ch2_taildesc_wren_int <= ch2_taildesc_wren or tail_updt;
--ch2_taildesc_wren_int <= ch2_taildesc_wren;
end generate EOF_DET;
NOEOF_DET : if (C_ENABLE_MULTI_CHANNEL = 0) generate
tail_updt <= '0';
ch2_eof_detected <= '0';
ch2_taildesc_wren_int <= ch2_taildesc_wren;
ch2_sg_idle_int <= '0'; --ch2_sg_idle;
end generate NOEOF_DET;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_sg_v4_1_2.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set_i ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set_i ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set_i ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set_i ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set_i ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set_i ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren_int ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
ch2_eof_detected => ch2_eof_detected ,
tail_updt => tail_updt ,
tail_updt_latch => tail_updt_latch ,
ch2_sg_idle => ch2_sg_idle ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr_1 ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_sg_v4_1_2.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ACTUAL_ADDR => C_ACTUAL_ADDR,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => ch2_sg_idle_int ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_cyclic => ch1_cyclic ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_cyclic => ch2_cyclic ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
m_axis_ch2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_sg_v4_1_2.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set_i ,
ch1_updt_slverr_set => ch1_updt_slverr_set_i ,
ch1_updt_decerr_set => ch1_updt_decerr_set_i ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set_i ,
ch2_updt_slverr_set => ch2_updt_slverr_set_i ,
ch2_updt_decerr_set => ch2_updt_decerr_set_i ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr_1
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready_i ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_sg_v4_1_2.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_sg_v4_1_2.axi_sg_datamover
generic map(
C_INCLUDE_MM2S => 2, --INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, --
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_INCLUDE_S2MM => 2, --INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
sg_ctl => sg_ctl ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_aruser => m_axi_sg_aruser ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr_int ,
m_axi_s2mm_awlen => m_axi_sg_awlen_int ,
m_axi_s2mm_awsize => m_axi_sg_awsize_int ,
m_axi_s2mm_awburst => m_axi_sg_awburst_int ,
m_axi_s2mm_awprot => m_axi_sg_awprot_int ,
m_axi_s2mm_awcache => m_axi_sg_awcache_int ,
m_axi_s2mm_awuser => m_axi_sg_awuser_int ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid_int ,
m_axi_s2mm_awready => m_axi_sg_awready_int ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid_int ,
m_axi_s2mm_wready => m_axi_sg_wready_int ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp_int ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid_int ,
m_axi_s2mm_bready => m_axi_sg_bready_int ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
--ENABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS = 1) generate
-- begin
m_axi_sg_awaddr <= m_axi_sg_awaddr_int ;
m_axi_sg_awlen <= m_axi_sg_awlen_int ;
m_axi_sg_awsize <= m_axi_sg_awsize_int ;
m_axi_sg_awburst <= m_axi_sg_awburst_int;
m_axi_sg_awprot <= m_axi_sg_awprot_int ;
m_axi_sg_awcache <= m_axi_sg_awcache_int;
m_axi_sg_awuser <= m_axi_sg_awuser_int ;
m_axi_sg_awvalid <= m_axi_sg_awvalid_int;
m_axi_sg_awready_int <= m_axi_sg_awready;
m_axi_sg_wvalid <= m_axi_sg_wvalid_int;
m_axi_sg_wready_int <= m_axi_sg_wready;
m_axi_sg_bresp_int <= m_axi_sg_bresp;
m_axi_sg_bvalid_int <= m_axi_sg_bvalid;
m_axi_sg_bready <= m_axi_sg_bready_int;
-- end generate ENABLE_MM2S_STATUS;
--DISABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS > 1) generate
--
-- m_axi_sg_awaddr <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awaddr_int;
-- m_axi_sg_awlen <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awlen_int;
-- m_axi_sg_awsize <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awsize_int;
-- m_axi_sg_awburst <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awburst_int;
-- m_axi_sg_awprot <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awprot_int;
-- m_axi_sg_awcache <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awcache_int;
-- m_axi_sg_awuser <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awuser_int;
-- m_axi_sg_awvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_awvalid_int;
-- m_axi_sg_awready_int <= m_axi_sg_awvalid_int when ch1_updt_active = '1' else m_axi_sg_awready; -- to make sure that AXI logic is fine.
--
-- m_axi_sg_wvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_wvalid_int;
-- m_axi_sg_wready_int <= m_axi_sg_wvalid_int when ch1_updt_active = '1' else m_axi_sg_wready; -- to make sure that AXI logic is fine
--
-- m_axi_sg_bresp_int <= m_axi_sg_bresp;
-- m_axi_sg_bvalid_int <= m_axi_sg_bvalid_int_del when ch1_updt_active = '1' else m_axi_sg_bvalid;
-- m_axi_sg_bready <= m_axi_sg_bready_int;
--
ch2_update_active <= ch2_updt_active;
--
---- A dummy response is needed to keep things running on DMA side
-- PROC_DUMMY_RESP : process (m_axi_sg_aclk)
-- begin
-- if (dm_resetn = '0') then
-- m_axi_sg_bvalid_int_del <= '0';
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- m_axi_sg_bvalid_int_del <= m_axi_sg_wvalid_int;
-- end if;
-- end process PROC_DUMMY_RESP;
--
-- end generate DISABLE_MM2S_STATUS;
end implementation;
| gpl-3.0 | 67d50ec8a6193b9ddea7256c2c63a89e | 0.402502 | 4.026522 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue458/repro2.vhdl | 1 | 575 | entity repro is
end entity;
architecture A of repro is
signal S1 : bit := '0';
signal S2_transport : bit;
signal S2_delayed : bit;
begin
S1 <= '1' after 10 ns, '0' after 20 ns;
S2_transport <= transport S1 after 100 ns;
S2_delayed <= S1'delayed(100 ns);
process (S1) is
begin
assert false report "S1 = " & bit'image(S1) severity note;
end process;
process (S2_delayed) is
begin
assert false report "S1'delayed = " & bit'image(S2_delayed) severity note;
end process;
end architecture;
| gpl-2.0 | ab984a5c9b53b0c8af2ec852bb5b2bb7 | 0.601739 | 3.285714 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug090/crash11.vhdl | 1 | 1,486 | library ieee;
use ieee.std_logic_1164.all;
entity clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic := '0');
end clkgen;
architecture behav of clkgen is
begin
process
begin
clk <= not clk;
wait for period / 2;
end process;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : std_logic;
signal rst_n : std_logic;
signal din, dout, dout2 : std_logic_vector (7 downto 0);
component clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic);
end component;
begin
cclk : clkgen
generic map (period => 20 ns)
port map (clk => clk);
rst_n <= '0' after 0 ns, '1' after 4 ns;
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else q <= d;
end if;
end if;
end process p;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report "start of tb" severity note;
for i in 0 to 10 loop
case i is
when 0 | 3 =>
for i in din'range loop
din(i) <= '0';
end loop;
when 1 => din <= b"00110011";
when 2 => v := 0;
while v < 7 loop
din (v) <= '1';
v := v + 1;
end loop;
when 4 to 5 | 8 => din <= x"a%"; when others =>
. null;
end case;
end loop;
wait until clk = '0';
end process;
assert false report "Hello world" severity note;
end behav;
| gpl-2.0 | d1325c633ac606780403e235e5a55eec | 0.562584 | 3.361991 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd | 4 | 3,267 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_mixer is
end tb_mixer;
architecture TB_mixer of tb_mixer is
-- Component declarations
-- Signal declarations
terminal mix_in : electrical_vector(1 to 8);
terminal pseudo_gnd : electrical;
begin
-- Signal assignments
-- Component instances
v3 : entity work.v_sine(ideal)
generic map(
amplitude => 5.0,
freq => 1.0e3
)
port map(
pos => mix_in(7),
neg => ELECTRICAL_REF
);
v4 : entity work.v_sine(ideal)
generic map(
amplitude => 4.0,
freq => 2.0e3
)
port map(
pos => mix_in(8),
neg => ELECTRICAL_REF
);
v9 : entity work.v_sine(ideal)
generic map(
freq => 1.0e3,
amplitude => 5.0
)
port map(
pos => mix_in(5),
neg => ELECTRICAL_REF
);
v10 : entity work.v_sine(ideal)
generic map(
freq => 2.0e3,
amplitude => 4.0
)
port map(
pos => mix_in(6),
neg => ELECTRICAL_REF
);
R2 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => pseudo_gnd,
p2 => ELECTRICAL_REF
);
mixer1 : entity work.mixer_wa(weighted)
port map(
inputs => mix_in,
output => pseudo_gnd
);
v14 : entity work.v_sine(ideal)
generic map(
amplitude => 4.0,
freq => 2.0e3
)
port map(
pos => mix_in(2),
neg => ELECTRICAL_REF
);
v15 : entity work.v_sine(ideal)
generic map(
amplitude => 5.0,
freq => 1.0e3
)
port map(
pos => mix_in(1),
neg => ELECTRICAL_REF
);
v16 : entity work.v_sine(ideal)
generic map(
freq => 2.0e3,
amplitude => 4.0
)
port map(
pos => mix_in(4),
neg => ELECTRICAL_REF
);
v17 : entity work.v_sine(ideal)
generic map(
freq => 1.0e3,
amplitude => 5.0
)
port map(
pos => mix_in(3),
neg => ELECTRICAL_REF
);
end TB_mixer;
| gpl-2.0 | 5d7a5ad8d3036bad47d857453dbdc2d8 | 0.524334 | 3.979294 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1288/issue.vhdl | 1 | 603 | library ieee;
use ieee.std_logic_1164.all;
entity issue is
end issue;
architecture sim of issue is
signal clk : std_logic := '1';
signal a, b : std_logic := '0';
begin
clk <= not clk after 5 ns;
a <= '1' after 20 ns,
'0' after 30 ns,
'1' after 40 ns,
'0' after 50 ns;
b <= '1' after 50 ns,
'0' after 60 ns,
'1' after 70 ns,
'0' after 80 ns;
-- All is sensitive to rising edge of clk
-- psl default clock is rising_edge(clk);
-- This assertion holds
-- psl NEXT_0_a : assert always (a -> next_e[3 to 5] (b));
end architecture sim;
| gpl-2.0 | 32bf672e4c5bc4487fe7941ba7d59a14 | 0.573798 | 3.092308 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd | 4 | 1,722 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed;
use ieee_proposed.electrical_systems.all, ieee_proposed.thermal_systems.all;
entity resistor_pack is
generic ( resistances_at_298K : real_vector;
temperature_coeff : real := 0.0 );
port ( terminal p1, p2 : electrical_vector(1 to resistances_at_298K'length);
quantity package_temp : in temperature );
end entity resistor_pack;
----------------------------------------------------------------
architecture coupled of resistor_pack is
quantity v across i through p1 to p2;
quantity effective_resistance : real_vector(1 to resistances_at_298K'length);
begin
resistor_array : for index in 1 to resistances_at_298K'length generate
effective_resistance(index)
== resistances_at_298K(index)
+ ( package_temp - 298.0 ) * temperature_coeff;
v(index ) == i(index) * effective_resistance(index);
end generate resistor_array;
end architecture coupled;
| gpl-2.0 | ec763554a373a9e3036e20dcfdea67e2 | 0.702091 | 4.070922 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2303.vhd | 4 | 2,715 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2303.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p37n01i02303ent IS
END c07s02b06x00p37n01i02303ent;
ARCHITECTURE c07s02b06x00p37n01i02303arch OF c07s02b06x00p37n01i02303ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
-- Test dividing user-defined physical type values.
assert ((1 cm / 1 mm) = 10);
assert ((1 mm / 1 um) = 1000);
assert ((1 um / 1 nm) = 1000);
assert ((1 nm / 1 A) = 10);
wait for 5 ns;
assert NOT( ((1 cm / 1 mm) = 10) and
((1 mm / 1 um) = 1000) and
((1 um / 1 nm) = 1000) and
((1 nm / 1 A) = 10) )
report "***PASSED TEST: c07s02b06x00p37n01i02303"
severity NOTE;
assert ( ((1 cm / 1 mm) = 10) and
((1 mm / 1 um) = 1000) and
((1 um / 1 nm) = 1000) and
((1 nm / 1 A) = 10) )
report "***FAILED TEST: c07s02b06x00p37n01i02303 - Division of a physical type by another physical type (user-defined) test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p37n01i02303arch;
| gpl-2.0 | 92df566f846268f79cfe886e89308083 | 0.572376 | 3.739669 | false | true | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd | 3 | 92,879 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM FULL Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all ;
-- axi_datamover Library Modules
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_reset ;
use axi_datamover_v5_1_10.axi_datamover_cmd_status ;
use axi_datamover_v5_1_10.axi_datamover_pcc ;
use axi_datamover_v5_1_10.axi_datamover_ibttcc ;
use axi_datamover_v5_1_10.axi_datamover_indet_btt ;
use axi_datamover_v5_1_10.axi_datamover_s2mm_realign ;
use axi_datamover_v5_1_10.axi_datamover_addr_cntl ;
use axi_datamover_v5_1_10.axi_datamover_wrdata_cntl ;
use axi_datamover_v5_1_10.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_10.axi_datamover_skid2mm_buf ;
Use axi_datamover_v5_1_10.axi_datamover_skid_buf ;
Use axi_datamover_v5_1_10.axi_datamover_wr_sf ;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_full_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 1;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) General Purpose Store and Forward function
-- 0 = Omit GP Store and Forward
-- 1 = Include GP Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and Reset inputs ----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
-------------------------------------------------------------------
-- S2MM Primary Reset input ---------------------------------------
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- S2MM Halt request input control --------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------------
-- S2MM Error discrete output -------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------------
-- Optional Command and Status Clock and Reset -------------------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls ---------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_full_wrap;
architecture implementation of axi_datamover_s2mm_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
if (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_status_width
--
-- Function Description:
-- This function sets the width of the Status pipe depending on the
-- Store and Forward inclusion or ommision.
--
-------------------------------------------------------------------
function funct_set_status_width (store_forward_enabled : integer)
return integer is
Variable temp_status_bit_width : Integer := 8;
begin
If (store_forward_enabled = 1) Then
temp_status_bit_width := 32;
Else
temp_status_bit_width := 8;
End if;
Return (temp_status_bit_width);
end function funct_set_status_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_bits_needed
--
-- Function Description:
--
--
-------------------------------------------------------------------
function get_bits_needed (max_bytes : integer) return integer is
Variable fvar_temp_bit_width : Integer := 1;
begin
if (max_bytes <= 1) then
fvar_temp_bit_width := 1;
elsif (max_bytes <= 3) then
fvar_temp_bit_width := 2;
elsif (max_bytes <= 7) then
fvar_temp_bit_width := 3;
elsif (max_bytes <= 15) then
fvar_temp_bit_width := 4;
elsif (max_bytes <= 31) then
fvar_temp_bit_width := 5;
elsif (max_bytes <= 63) then
fvar_temp_bit_width := 6;
elsif (max_bytes <= 127) then
fvar_temp_bit_width := 7;
elsif (max_bytes <= 255) then
fvar_temp_bit_width := 8;
elsif (max_bytes <= 511) then
fvar_temp_bit_width := 9;
elsif (max_bytes <= 1023) then
fvar_temp_bit_width := 10;
elsif (max_bytes <= 2047) then
fvar_temp_bit_width := 11;
elsif (max_bytes <= 4095) then
fvar_temp_bit_width := 12;
elsif (max_bytes <= 8191) then
fvar_temp_bit_width := 13;
else -- 8k - 16K
fvar_temp_bit_width := 14;
end if;
Return (fvar_temp_bit_width);
end function get_bits_needed;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_need_realigner
--
-- Function Description:
-- Determines if the Realigner module needs to be included.
--
-------------------------------------------------------------------
function funct_need_realigner (indet_btt_enabled : integer;
dre_included : integer;
gp_sf_included : integer) return integer is
Variable temp_val : Integer := 0;
begin
If ((indet_btt_enabled = 1) or
(dre_included = 1) or
(gp_sf_included = 1)) Then
temp_val := 1;
else
temp_val := 0;
End if;
Return (temp_val);
end function funct_need_realigner;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others =>
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for S2MM
-- modules downstream from the upsizing Store and Forward. If
-- Store and forward is present, then the effective Stream width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Stream width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled > 0) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_bytes_per_dbeat
--
-- Function Description:
-- This function calculates the number of bytes transfered per
-- databeat on the MMap AXI4 Write Data Channel by the S2MM. The
-- value is based on input parameterization of included functions
-- in the S2MM block.
--
-------------------------------------------------------------------
function funct_get_bytes_per_dbeat (ibtt_enabled : integer ;
gpsf_enabled : integer ;
stream_dwidth : integer ;
mmap_dwidth : integer ) return integer is
Variable fvar_temp_bytes_per_xfer : Integer := 4;
begin
If (ibtt_enabled > 0 or
gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width
fvar_temp_bytes_per_xfer := mmap_dwidth/8;
Else -- transfers will be in stream data widths (may be narrow transfers on mmap)
fvar_temp_bytes_per_xfer := stream_dwidth/8;
End if;
Return (fvar_temp_bytes_per_xfer);
end function funct_get_bytes_per_dbeat;
-- Constant Declarations ----------------------------------------
Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH,
C_S2MM_SDATA_WIDTH,
SF_ENABLED);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant IS_NOT_MM2S : integer range 0 to 1 := 0;
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH;
Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32);
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED;
Constant BITS_PER_BYTE : integer := 8;
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1;
Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT;
Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ;
Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF ,
ENABLE_GP_SF ,
S2MM_SDATA_WIDTH ,
S2MM_MDATA_WIDTH);
Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEAT*S2MM_BURST_SIZE;
Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST);
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going
-- full thresholding
-- in WSC
Constant WSC_STATUS_WIDTH : integer range 8 to 32 :=
funct_set_status_width(ENABLE_INDET_BTT_SF);
Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED;
Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF ,
INCLUDE_S2MM_DRE ,
ENABLE_GP_SF);
-- Calculates the minimum needed depth of the GP Store and Forward FIFO
-- based on the S2MM pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE;
-- Assigns the depth of the optional GP Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH,
S2MM_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0');
signal sig_dre2ibtt_tvalid : std_logic := '0';
signal sig_ibtt2dre_tready : std_logic := '0';
signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tlast : std_logic := '0';
signal sig_dre2ibtt_eop : std_logic := '0';
signal sig_dre2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2dre_cmd_valid : std_logic := '0';
signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2dre_drr : std_logic := '0';
signal sig_mstr2dre_eof : std_logic := '0';
signal sig_mstr2dre_cmd_cmplt : std_logic := '0';
signal sig_mstr2dre_calc_error : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal sig_dre2all_halted : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal skid2dre_wvalid : std_logic := '0';
signal dre2skid_wready : std_logic := '0';
signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2dre_wlast : std_logic := '0';
signal sig_s2mm_allow_addr_req : std_logic := '0';
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_s2mm_addr_req_posted : std_logic := '0';
signal sig_s2mm_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_ibtt2wdc_error : std_logic := '0';
signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal s2mm_awuser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug/Test Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADD_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen adds in the EOP status marker to the debug
-- vector data when Indet BTT Store and Forward is enabled.
--
------------------------------------------------------------
GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate
begin
sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker
end generate GEN_ADD_DEBUG_EOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen zeros the debug vector bit used for the EOP
-- status marker when Indet BTT Store and Forward is not
-- enabled.
--
------------------------------------------------------------
GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate
begin
sig_dbg_data_1(19) <= '0' ; -- EOP Marker
end generate GEN_NO_DEBUG_EOP;
---- End of Debug/Test Support --------------------------------
-- Assign the Address posting control outputs
s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ;
s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ;
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ;
s2mm_wr_len <= sig_s2mm_wr_len ;
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
s2mm_wstrb <= sig_skid2axi_wstrb ;
end generate GEN_S2MM_TKEEP_ENABLE2;
GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
s2mm_wstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE2;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters
s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_10.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_10.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_WR_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_10.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_PCC
--
-- If Generate Description:
-- Include the normal Predictive Command Calculator function,
-- Store and Forward is not an included feature.
--
--
------------------------------------------------------------
GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1_10.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_NOT_MM2S ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => open ,
mstr2data_dre_dest_align => open ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_PCC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_IBTTCC
--
-- If Generate Description:
-- Include the Indeterminate BTT Command Calculator function,
-- Store and Forward is enabled in the S2MM.
--
--
------------------------------------------------------------
GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_MSTR_SFCC
--
-- Description:
-- Instantiates the Store and Forward Command Calculator
-- Block.
--
------------------------------------------------------------
I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1_10.axi_datamover_ibttcc
generic map (
C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_IBTTCC;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2dre_wvalid ,
m_ready => dre2skid_wready ,
m_data => skid2dre_wdata ,
m_strb => skid2dre_wstrb ,
m_last => skid2dre_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2dre_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= dre2skid_wready;
skid2dre_wdata <= s2mm_strm_wdata;
skid2dre_wstrb <= s2mm_strm_wstrb;
skid2dre_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_REALIGNER
--
-- If Generate Description:
-- Omit the S2MM Realignment Engine
--
--
------------------------------------------------------------
GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate
begin
-- Set to Always ready for DRE to PCC Command Interface
sig_dre2mstr_cmd_ready <= LOGIC_HIGH;
-- Without DRE and Scatter, the end of packet is the TLAST
--sig_dre2ibtt_eop <= skid2dre_wlast ;
sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version
-- Cant't detect undrrun/overrun here
sig_realign2wdc_eop_error <= '0';
ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_NO_REALIGN_SKID_BUF
--
-- Description:
-- Instance for a Skid Buffer which provides for
-- Fmax timing improvement between the Null Absorber and
-- the Write Data controller when the Realigner is not
-- present (no DRE and no Store and Forward case).
--
------------------------------------------------------------
I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Null Absorber Input)
s_valid => skid2dre_wvalid ,
s_ready => dre2skid_wready ,
s_data => skid2dre_wdata ,
s_strb => skid2dre_wstrb ,
s_last => skid2dre_wlast ,
-- Master Side (Stream Data Output to WData Cntlr)
m_valid => sig_dre2ibtt_tvalid ,
m_ready => sig_ibtt2dre_tready ,
m_data => sig_dre2ibtt_tdata ,
m_strb => sig_dre2ibtt_tstrb ,
m_last => sig_dre2ibtt_tlast
);
end generate ENABLE_NOREALIGNER_SKID;
DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate
begin
sig_dre2ibtt_tvalid <= skid2dre_wvalid;
dre2skid_wready <= sig_ibtt2dre_tready;
sig_dre2ibtt_tdata <= skid2dre_wdata;
sig_dre2ibtt_tstrb <= skid2dre_wstrb;
sig_dre2ibtt_tlast <= skid2dre_wlast;
end generate DISABLE_NOREALIGNER_SKID;
end generate GEN_NO_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_REALIGNER
--
-- If Generate Description:
-- Include the S2MM realigner Module. It hosts the S2MM DRE
-- and the Scatter Block.
--
-- Note that the General Purpose Store and Forward Module
-- needs the Scatter function to detect input overrun and
-- underrun events on the AXI Stream input. Thus the Realigner
-- is included whenever the GP Store and Forward is enabled.
--
------------------------------------------------------------
GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_REALIGNER
--
-- Description:
-- Instance for the S2MM Data Realignment Module.
--
------------------------------------------------------------
I_S2MM_REALIGNER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_realign
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_INCLUDE_DRE => INCLUDE_S2MM_DRE ,
C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER ,
C_BTT_USED => S2MM_BTT_USED ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
-- Write Data Controller or Store and Forward I/O -------
wdc2dre_wready => sig_ibtt2dre_tready ,
dre2wdc_wvalid => sig_dre2ibtt_tvalid ,
dre2wdc_wdata => sig_dre2ibtt_tdata ,
dre2wdc_wstrb => sig_dre2ibtt_tstrb ,
dre2wdc_wlast => sig_dre2ibtt_tlast ,
dre2wdc_eop => sig_dre2ibtt_eop ,
-- Starting offset output -------------------------------
dre2sf_strt_offset => sig_sf_strt_addr_offset ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_wready => dre2skid_wready ,
s2mm_strm_wvalid => skid2dre_wvalid ,
s2mm_strm_wdata => skid2dre_wdata ,
s2mm_strm_wstrb => skid2dre_wstrb ,
s2mm_strm_wlast => skid2dre_wlast ,
-- Command Calculator Interface --------------------------
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ,
-- Premature TLAST assertion error flag
dre2all_tlast_error => sig_realign2wdc_eop_error ,
-- DRE Halted Status
dre2all_halted => sig_dre2all_halted
);
end generate GEN_INCLUDE_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT_SF
--
-- If Generate Description:
-- Include the Indeterminate BTT Logic with specialized
-- Store and Forward function, This also requires the
-- Scatter Engine in the Realigner module.
--
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate
begin
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
------------------------------------------------------------
-- Instance: I_INDET_BTT
--
-- Description:
-- Instance for the Indeterminate BTT with Store and Forward
-- module.
--
------------------------------------------------------------
I_INDET_BTT : entity axi_datamover_v5_1_10.axi_datamover_indet_btt
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_DRE => INCLUDE_S2MM_DRE ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
ibtt2wdc_eop => sig_ibtt2wdc_eop ,
ibtt2wdc_tdata => sig_ibtt2wdc_tdata ,
ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb ,
ibtt2wdc_tlast => sig_ibtt2wdc_tlast ,
ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid ,
wdc2ibtt_tready => sig_wdc2ibtt_tready ,
dre2ibtt_tvalid => sig_dre2ibtt_tvalid ,
ibtt2dre_tready => sig_ibtt2dre_tready ,
dre2ibtt_tdata => sig_dre2ibtt_tdata ,
dre2ibtt_tstrb => sig_dre2ibtt_tstrb ,
dre2ibtt_tlast => sig_dre2ibtt_tlast ,
dre2ibtt_eop => sig_dre2ibtt_eop ,
dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes
);
end generate GEN_ENABLE_INDET_BTT_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_SF
--
-- If Generate Description:
-- Bypasses any store and Forward functions.
--
--
------------------------------------------------------------
GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 0) generate
begin
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
-- Housekeep unused signal in this case
sig_ok_to_post_wr_addr <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
-- Just pass DRE signals through
sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ;
sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ;
sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ;
sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ;
sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ;
sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ;
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
end generate GEN_NO_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_GP_SF
--
-- If Generate Description:
-- Include the General Purpose Store and Forward module.
-- This If Generate can only be enabled when
-- Indeterminate BTT mode is not enabled. The General Purpose
-- Store and Forward is instantiated in place of the Indet
-- BTT Store and Forward.
--
------------------------------------------------------------
GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 1) generate
begin
-- Merge the external address posting control with the
-- SF address posting control.
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and
sig_ok_to_post_wr_addr ;
-- Zero these out since Indet BTT is not enabled, they
-- are only used by the WDC in that mode
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
sig_ibtt2wdc_eop <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
------------------------------------------------------------
-- Instance: I_S2MM_GP_SF
--
-- Description:
-- Instance for the S2MM (Write) General Purpose Store and
-- Forward Module. This module can only be enabled when
-- Indeterminate BTT mode is not enabled. It is connected
-- in place of the IBTT Module when GP SF is enabled.
--
------------------------------------------------------------
I_S2MM_GP_SF : entity axi_datamover_v5_1_10.axi_datamover_wr_sf
generic map (
C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -----------------------------
aclk => s2mm_aclk ,
reset => sig_mmap_rst ,
-- Slave Stream Input --------------------------------
sf2sin_tready => sig_ibtt2dre_tready ,
sin2sf_tvalid => sig_dre2ibtt_tvalid ,
sin2sf_tdata => sig_dre2ibtt_tdata ,
sin2sf_tkeep => sig_dre2ibtt_tstrb ,
sin2sf_tlast => sig_dre2ibtt_tlast ,
sin2sf_error => sig_realign2wdc_eop_error ,
-- Starting Address Offset Input ---------------------
sin2sf_strt_addr_offset => sig_sf_strt_addr_offset ,
-- DataMover Write Side Address Pipelining Control Interface --------
ok_to_post_wr_addr => sig_ok_to_post_wr_addr ,
wr_addr_posted => sig_s2mm_addr_req_posted ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
wr_ld_nxt_len => sig_s2mm_ld_nxt_len ,
wr_len => sig_s2mm_wr_len ,
-- Write Side Stream Out to DataMover S2MM -------------
sout2sf_tready => sig_wdc2ibtt_tready ,
sf2sout_tvalid => sig_ibtt2wdc_tvalid ,
sf2sout_tdata => sig_ibtt2wdc_tdata ,
sf2sout_tkeep => sig_ibtt2wdc_tstrb ,
sf2sout_tlast => sig_ibtt2wdc_tlast ,
sf2sout_error => sig_ibtt2wdc_error
);
end generate GEN_INCLUDE_GP_SF;
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_10.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => s2mm_awcache_int ,
addr2axi_auser => s2mm_awuser_int ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
-- mstr2addr_cache_info => sig_cache2mstr_command ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_s2mm_allow_addr_req ,
addr_req_posted => sig_s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_10.axi_datamover_wrdata_cntl
generic map (
C_REALIGNER_INCLUDED => ADD_REALIGNER ,
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => sig_ibtt2wdc_tvalid ,
s2mm_strm_wready => sig_wdc2ibtt_tready ,
s2mm_strm_wdata => sig_ibtt2wdc_tdata ,
s2mm_strm_wstrb => sig_ibtt2wdc_tstrb ,
s2mm_strm_wlast => sig_ibtt2wdc_tlast ,
s2mm_strm_eop => sig_ibtt2wdc_eop ,
s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
realign2wdc_eop_error => sig_ibtt2wdc_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
--ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
--begin
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
--end generate ENABLE_AXIMMAP_SKID;
end implementation;
| gpl-3.0 | 708a4a6a2d725679f5ee297dfb038b89 | 0.451846 | 4.154359 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/ghrd_10as066n2_dipsw_pio_inst.vhd | 1 | 1,535 | component ghrd_10as066n2_dipsw_pio is
port (
clk : in std_logic := 'X'; -- clk
in_port : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
irq : out std_logic; -- irq
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component ghrd_10as066n2_dipsw_pio;
u0 : component ghrd_10as066n2_dipsw_pio
port map (
clk => CONNECTED_TO_clk, -- clk.clk
in_port => CONNECTED_TO_in_port, -- external_connection.export
irq => CONNECTED_TO_irq, -- irq.irq
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
address => CONNECTED_TO_address, -- s1.address
write_n => CONNECTED_TO_write_n, -- .write_n
writedata => CONNECTED_TO_writedata, -- .writedata
chipselect => CONNECTED_TO_chipselect, -- .chipselect
readdata => CONNECTED_TO_readdata -- .readdata
);
| mit | 9121cfe3d8fc7715effd4256031527b8 | 0.45798 | 3.654762 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_pcc.vhd | 3 | 103,944 | -------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_pcc.vhd
--
-- Description:
-- This file implements the DataMover Predictive Command Calculator (PCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_pcc is
generic (
C_IS_MM2S : Integer range 0 to 1 := 0;
-- This parameter tells the PCC module if it is a MM2S
-- instance or a S2MM instance.
-- 0 = S2MM Instance
-- 1 = MM2S Instance
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the Indeterminate BTT mode is enabled
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions
);
port (
-- Clock and Reset input ----------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------------
-- Master Command FIFO/Register Interface --------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
--------------------------------------------------------------------------------------
-- Address Channel Controller Interface -----------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
---------------------------------------------------------------------------
-- Data Channel Controller Interface ------------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the MM2S DRE --
--
mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the MM2S DRE --
-------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ----------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------------------------
-- Special DRE Controller Interface --------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The last child tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
-------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_pcc;
architecture implementation of axi_datamover_pcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calculates the AXI SIZE Qualifier based on the data width.
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1;
Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH;
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH);
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH);
Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH);
Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH);
Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH;
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH);
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PCC_SM_STATE_TYPE is (
INIT,
WAIT_FOR_CMD,
CALC_1,
CALC_2,
CALC_3,
WAIT_ON_XFER_PUSH,
CHK_IF_DONE,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT;
Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT;
signal sig_sm_halt_ns : std_logic := '0';
signal sig_sm_halt_reg : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0';
signal sig_sm_pop_input_reg_ns : std_logic := '0';
signal sig_sm_pop_input_reg : std_logic := '0';
signal sig_sm_ld_calc1_reg_ns : std_logic := '0';
signal sig_sm_ld_calc1_reg : std_logic := '0';
signal sig_sm_ld_calc2_reg_ns : std_logic := '0';
signal sig_sm_ld_calc2_reg : std_logic := '0';
signal sig_sm_ld_calc3_reg_ns : std_logic := '0';
signal sig_sm_ld_calc3_reg : std_logic := '0';
signal sig_parent_done : std_logic := '0';
signal sig_ld_xfer_reg : std_logic := '0';
signal sig_ld_xfer_reg_tmp : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
-- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
-- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
-- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
-- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_last_xfer_valid_im1 : std_logic := '0';
signal sig_brst_cnt_eq_zero_im0 : std_logic := '0';
signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0';
signal sig_brst_cnt_eq_one_im0 : std_logic := '0';
signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0';
signal sig_brst_residue_eq_zero : std_logic := '0';
signal sig_brst_residue_eq_zero_reg : std_logic := '0';
signal sig_no_btt_residue_im0 : std_logic := '0';
signal sig_no_btt_residue_ireg1 : std_logic := '0';
signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
-- signal sig_ld_output : std_logic := '0';
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_addr_cntr : std_logic := '0';
signal sig_incr_addr_cntr : std_logic := '0';
signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_calc_error_pushed : std_logic := '0';
-- PCC2 stuff
signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_im2 : std_logic := '0';
signal sig_first_xfer_im0 : std_logic := '0';
signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover : std_logic := '0';
signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_btt_lt_b2mbaa_im0 : std_logic := '0';
signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0';
signal sig_btt_eq_b2mbaa_im0 : std_logic := '0';
signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0';
signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned_im0 : std_logic := '0';
signal sig_addr_aligned_ireg1 : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_clr_cmd2dre_valid : std_logic := '0';
signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dre_eof_reg : std_logic := '0';
-- Long Timing path breakup intermediate registers
signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_ireg3 : std_logic := '0';
signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover_im3 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
----------------------------------------------------------
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and
sig_input_reg_empty and
not(sig_calc_error_pushed);
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sig_xfer_calc_err_reg;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the DRE Controller Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE
mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE
mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE
mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE
mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE
mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE
mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE
------------------------------------------------------------
-- If Generate
--
-- Label: DO_MM2S_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the MM2S use case.
--
------------------------------------------------------------
DO_MM2S_CASE : if (C_IS_MM2S = 1) generate
begin
mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
end generate DO_MM2S_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_S2MM_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the S2MM use case.
--
------------------------------------------------------------
DO_S2MM_CASE : if (C_IS_MM2S = 0) generate
begin
mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
end generate DO_S2MM_CASE;
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX);
-- Start internal logic.
-- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines)
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input xfer register design
sig_push_input_reg <= not(sig_sm_halt_reg) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_sm_pop_input_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
--
-------------------------------------------------------------
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1' or
sig_calc_error_pushed = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
----------------------------------------------------------------------
-- Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_PUSHED
--
-- Process Description:
-- Implements the flop for generating a flag indicating the
-- calculation error flag has been pushed to the addr and data
-- controllers.
--
-------------------------------------------------------------
IMP_CALC_ERROR_PUSHED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_pushed <= '0';
elsif (sig_push_xfer_reg = '1' and
sig_calc_error_pushed = '0') then
sig_calc_error_pushed <= sig_calc_error_reg;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_PUSHED;
---------------------------------------------------------------------
-- Strobe Generator Logic
sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3
When (sig_first_xfer_im0 = '1')
Else (others => '1');
sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3
When (sig_xfer_len_eq_0_ireg3 = '1' and
sig_first_xfer_im0 = '1')
else sig_xfer_end_strb_ireg3
When (sig_last_xfer_valid_im1 = '1')
Else (others => '1');
----------------------------------------------------------
-- Intermediate registers for STBGEN Fmax path
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen inputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_strbgen_addr_ireg2 <= (others => '0');
sig_strbgen_bytes_ireg2 <= (others => '0');
sig_finish_addr_offset_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ;
sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ;
sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_REGS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_OUT_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen outputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_OUT_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_xfer_strt_strb_ireg3 <= (others => '0');
sig_xfer_end_strb_ireg3 <= (others => '0');
sig_xfer_len_eq_0_ireg3 <= '0';
elsif (sig_sm_ld_calc3_reg = '1') then
sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2;
sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ;
sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_OUT_REGS;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr_ireg2 ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes_ireg2 ,
strb_out => sig_xfer_strt_strb_im2
);
-- The ending address offset is 1 less than the calculated
-- starting address for the next sequential transfer.
sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) -
STRBGEN_ADDR_SLICE_1);
------------------------------------------------------------
-- Instance: I_END_STRB_GEN
--
-- Description:
-- End Strobe generator instance. Generates asserted strobe
-- bits from byte offset 0 to the ending byte offset.
--
------------------------------------------------------------
I_END_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 1 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH
)
port map (
start_addr_offset => STRBGEN_ADDR_0 ,
end_addr_offset => sig_last_addr_offset_im2 ,
num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1
strb_out => sig_xfer_end_strb_im2
);
-----------------------------------------------------------------
-- Output xfer register design
sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty);
-- Data taking xfer after Addr and DRE
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or
-- Addr taking xfer after Data and DRE
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or
-- DRE taking xfer after Data and ADDR
(sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or
-- data and Addr taking xfer after DRE
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or
-- Addr and DRE taking xfer after Data
(sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or
-- Data and DRE taking xfer after Addr
(sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or
-- Addr, Data, and DRE all taking xfer
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_OUTPUT_QUAL
--
-- Process Description:
-- Implements the output xfer qualifier holding register
--
-------------------------------------------------------------
REG_OUTPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
-- sig_xfer_cache_reg <= (others => '0');
-- sig_xfer_user_reg <= (others => '0');
-- sig_xfer_addr_reg <= (others => '0');
-- sig_xfer_type_reg <= '0';
-- sig_xfer_len_reg <= (others => '0');
-- sig_xfer_tag_reg <= (others => '0');
-- sig_xfer_dsa_reg <= (others => '0');
-- sig_xfer_drr_reg <= '0';
-- sig_xfer_eof_reg <= '0';
-- sig_xfer_strt_strb_reg <= (others => '0');
-- sig_xfer_end_strb_reg <= (others => '0');
-- sig_xfer_is_seq_reg <= '0';
-- sig_xfer_cmd_cmplt_reg <= '0';
-- sig_xfer_calc_err_reg <= '0';
-- sig_xfer_btt_reg <= (others => '0');
-- sig_xfer_dre_eof_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
-- sig_xfer_addr_reg <= sig_xfer_address_im0 ;
-- end if;
-- sig_xfer_type_reg <= sig_input_burst_type_reg ;
-- sig_xfer_cache_reg <= sig_input_cache_type_reg ;
-- sig_xfer_user_reg <= sig_input_user_type_reg ;
-- sig_xfer_len_reg <= sig_xfer_len_im2 ;
-- sig_xfer_tag_reg <= sig_input_tag_reg ;
-- sig_xfer_dsa_reg <= sig_input_dsa_reg ;
-- sig_xfer_drr_reg <= sig_input_drr_reg and
-- sig_first_xfer_im0 ;
-- sig_xfer_eof_reg <= sig_input_eof_reg and
-- sig_last_xfer_valid_im1 ;
-- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
-- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
-- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
-- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
-- sig_calc_error_reg ;
-- sig_xfer_calc_err_reg <= sig_calc_error_reg ;
-- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
-- sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_OUTPUT_QUAL;
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else
sig_addr_cntr_lsh_kh ;
-- end if;
sig_xfer_type_reg <= sig_input_burst_type_reg ;
sig_xfer_cache_reg <= sig_input_cache_type_reg ;
sig_xfer_user_reg <= sig_input_user_type_reg ;
sig_xfer_len_reg <= sig_xfer_len_im2 ;
sig_xfer_tag_reg <= sig_input_tag_reg ;
sig_xfer_dsa_reg <= sig_input_dsa_reg ;
sig_xfer_drr_reg <= sig_input_drr_reg and
sig_first_xfer_im0 ;
sig_xfer_eof_reg <= sig_input_eof_reg and
sig_last_xfer_valid_im1 ;
sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
sig_calc_error_reg ;
sig_xfer_calc_err_reg <= sig_calc_error_reg ;
sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
--------------------------------------------------------------
-- BTT Counter Logic
sig_ld_btt_cntr <= sig_ld_addr_cntr;
-- sig_decr_btt_cntr <= sig_incr_addr_cntr;
-- above signal is using the incr_addr_cntr signal and hence cannot be
-- used if burst type is Fixed
sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr_im0 <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0);
-- Rip the Burst Count slice from BTT counter value
sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX);
sig_brst_cnt_eq_zero_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_0)
Else '0';
sig_brst_cnt_eq_one_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_1)
Else '0';
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0);
-- Check for transfer length residue of zero prior to subtracting 1
sig_no_btt_residue_im0 <= '1'
when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 +
RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH);
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len_im2 <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- Check to see if the new xfer length is zero (1 data beat)
sig_xfer_len_eq_0_im2 <= '1'
when (sig_xfer_len_im2 = XFER_LEN_ZERO)
Else '0';
-- Check for Last transfer condition
--sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and
sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and
--sig_no_btt_residue_im0 and
sig_no_btt_residue_ireg1 and
-- sig_addr_aligned_im0) or -- always the last databeat case
sig_addr_aligned_ireg1) or -- always the last databeat case
-- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining
((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining
-- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0)));
(sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1)));
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
-- Rip the LS bits of the LS Address Counter for the StrobeGen
-- starting address offset
sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
-- Check if the calcualted address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat
sig_addr_incr_ge_bpdb_im1 <= '1'
When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH))
Else '0';
-- If the calculated address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat, then clip the
-- strobegen byte value to the number of bytes per data beat, else use the
-- increment value.
sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1))
when (sig_addr_incr_ge_bpdb_im1 = '1')
else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0));
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_addr_cntr <= sig_push_input_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and
-- sig_input_burst_type_reg;
sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0);
sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH);
sig_addr_aligned_im0 <= '1'
when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less
-- than or equal to the remaining bytes to transfer. If it is, then at least
-- two tranfers have to be scheduled.
sig_btt_lt_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
sig_btt_eq_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_REG1
--
-- Process Description:
-- Intermediate register stage 1 for Address Counter
-- derivative calculations.
--
-------------------------------------------------------------
IMP_IM_REG1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= (others => '0');
sig_addr_aligned_ireg1 <= '0' ;
sig_btt_lt_b2mbaa_ireg1 <= '0' ;
sig_btt_eq_b2mbaa_ireg1 <= '0' ;
sig_brst_cnt_eq_zero_ireg1 <= '0' ;
sig_brst_cnt_eq_one_ireg1 <= '0' ;
sig_no_btt_residue_ireg1 <= '0' ;
elsif (sig_sm_ld_calc1_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ;
sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ;
sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ;
sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ;
sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0;
sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ;
sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_REG1;
-- Select the address counter increment value to use
sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH)
--When (sig_btt_lt_b2mbaa_im0 = '1')
When (sig_btt_lt_b2mbaa_ireg1 = '1')
--else sig_bytes_to_mbaa_im0
else sig_bytes_to_mbaa_ireg1
when (sig_first_xfer_im0 = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1;
-- Predict next transfer's address offset for the Strobe Generator
sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_addr_lsh_rollover_im3 <= '1'
when (
(sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
----------------------------------------------------------
-- Intermediate registers for reducing the Address Counter
-- Increment timing path
----------------------------------------------------------
-- calculate the next starting address after the current
-- xfer completes using intermediate register values
sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2;
sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_ADDRINC_REG
--
-- Process Description:
-- Intermediate registers for address counter increment to
-- break long timing paths.
--
-------------------------------------------------------------
IMP_IM_ADDRINC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_ADDRINC_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_PREDICT_ADDR_REG
--
-- Process Description:
-- Intermediate register for predicted address to break up
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_PREDICT_ADDR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_predict_addr_lsh_ireg3 <= (others => '0');
elsif (sig_sm_ld_calc3_reg = '1') then
sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2;
else
null; -- hold state
end if;
end if;
end process IMP_IM_PREDICT_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1;
else
null; -- hold state
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_lsh_im0 <= (others => '0');
sig_addr_cntr_lsh_kh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0));
sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice;
Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then
sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_im0_msh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1') then
sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_addr_cntr = '1') then
sig_first_xfer_im0 <= '0';
elsif (sig_ld_addr_cntr = '1') then
sig_first_xfer_im0 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DRE_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the DRE Module (S2MM DRE Only).
--
-- Note that the S2MM DRE only needs to be loaded with a command
-- for each parent command, not every child command.
--
-------------------------------------------------------------
CMD2DRE_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2dre_valid = '1') then
sig_cmd2dre_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1' and
sig_first_xfer_im0 = '1') then
sig_cmd2dre_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DRE_VALID_FLOP;
-------------------------------------------------------------------------
-- PCC State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PCC_SM_COMBINATIONAL
--
-- Process Description:
-- PCC State Machine combinational implementation
--
-------------------------------------------------------------
PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state ,
sig_parent_done ,
sig_push_input_reg ,
sig_pop_xfer_reg ,
sig_calc_error_pushed)
begin
-- SM Defaults
sig_pcc_sm_state_ns <= INIT;
sig_sm_halt_ns <= '0';
sig_sm_ld_xfer_reg_ns <= '0';
sig_sm_pop_input_reg_ns <= '0';
sig_sm_ld_calc1_reg_ns <= '0';
sig_sm_ld_calc2_reg_ns <= '0';
sig_sm_ld_calc3_reg_ns <= '0';
case sig_pcc_sm_state is
--------------------------------------------
when INIT =>
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_halt_ns <= '1';
--------------------------------------------
when WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
else
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
End if;
--------------------------------------------
when CALC_1 =>
sig_pcc_sm_state_ns <= CALC_2;
sig_sm_ld_calc2_reg_ns <= '1';
--------------------------------------------
when CALC_2 =>
sig_pcc_sm_state_ns <= CALC_3;
sig_sm_ld_calc3_reg_ns <= '1';
--------------------------------------------
when CALC_3 =>
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
sig_sm_ld_xfer_reg_ns <= '1';
--------------------------------------------
when WAIT_ON_XFER_PUSH =>
if (sig_pop_xfer_reg = '1') then
sig_pcc_sm_state_ns <= CHK_IF_DONE;
else -- wait until output register is loaded
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
end if;
--------------------------------------------
when CHK_IF_DONE =>
If (sig_calc_error_pushed = '1') then -- Internal error, go to trap
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
elsif (sig_parent_done = '1') Then -- done with parent command
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_pop_input_reg_ns <= '1';
else -- Still breaking up parent command
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
end if;
--------------------------------------------
when ERROR_TRAP =>
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_pcc_sm_state_ns <= INIT;
end case;
end process PCC_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PCC_SM_REGISTERED
--
-- Process Description:
-- PCC State Machine registered implementation
--
-------------------------------------------------------------
PCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_pcc_sm_state <= INIT;
sig_sm_halt_reg <= '1' ;
sig_sm_pop_input_reg <= '0' ;
sig_sm_ld_calc1_reg <= '0' ;
sig_sm_ld_calc2_reg <= '0' ;
sig_sm_ld_calc3_reg <= '0' ;
else
sig_pcc_sm_state <= sig_pcc_sm_state_ns ;
sig_sm_halt_reg <= sig_sm_halt_ns ;
sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns;
sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ;
sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ;
sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ;
end if;
end if;
end process PCC_SM_REGISTERED;
------------------------------------------------------------------
-- Transfer Register Load Enable logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_XFER_REG_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
LD_XFER_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_xfer_reg = '1') then
sig_ld_xfer_reg <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP;
LD_XFER_REG_FLOP1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_xfer_reg = '1') then
sig_ld_xfer_reg_tmp <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg_tmp <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP1;
------------------------------------------------------------------
-- Parent Done flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PARENT_DONE_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
PARENT_DONE_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_parent_done <= '0';
Elsif (sig_ld_xfer_reg_tmp = '1') Then
sig_parent_done <= sig_last_xfer_valid_im1;
else
null; -- hold current state
end if;
end if;
end process PARENT_DONE_FLOP;
end implementation;
| gpl-3.0 | 7b9a5b3f90339d16249e3a54900d4f0d | 0.456544 | 4.283171 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/output_split4.vhd | 2 | 1,410 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split4 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split4;
architecture augh of output_split4 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | d1e77a937a9d3668cb0e16490b02637a | 0.673759 | 2.895277 | false | false | false | false |
nickg/nvc | test/regress/bitstr1.vhd | 1 | 1,411 | entity bitstr1 is
end entity;
architecture test of bitstr1 is
begin
main: process is
begin
-- Examples from LRM
assert B"1111_1111_1111" = string'("111111111111");
assert X"FFF" = string'(b"1111_1111_1111");
assert O"777" = string'(b"111_111_111");
assert X"777" = string'(b"0111_0111_0111");
assert B"XXXX_01LH" = string'("XXXX01LH");
assert UO"27" = string'(b"010_111");
assert UO"2C" = string'("010CCC");
assert SX"3W" = string'("0011WWWW");
assert D"35" = string'("100011");
assert 12UB"X1" = string'("0000000000X1");
assert 12SB"X1" = string'("XXXXXXXXXXX1");
assert 12UX"F-" = string'("00001111----");
assert 12SX"F-" = string'("11111111----");
assert 12D"13" = string'(b"0000_0000_1101");
assert 12UX"000WWW" = string'("WWWWWWWWWWWW");
assert 12SX"FFFC00" = string'("110000000000");
assert 12SX"XXXX00" = string'("XXXX00000000");
wait;
end process;
p2: process is
constant c1: STRING := B"1111_1111_1111";
constant c2: BIT_VECTOR := X"FFF";
type MVL is ('X', '0', '1', 'Z');
type MVL_VECTOR is array (NATURAL range <>) of MVL;
constant c3: MVL_VECTOR := O"777";
begin
assert c1'LENGTH = 12 and c2'LENGTH = 12 and c3 = "111111111";
wait;
end process;
end architecture;
| gpl-3.0 | 700088d9a3391a5bce9929db1c7d05f6 | 0.565556 | 3.492574 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue530/sample_slice_ports.vhdl | 1 | 1,030 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity submodule is
port (
clk : in std_logic;
arg : in std_logic_vector(15 downto 0);
res : out std_logic_vector(15 downto 0)
);
end submodule;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sliced_ex is
port (
clk : in std_logic;
arg_a : in signed(7 downto 0);
arg_b : in signed(7 downto 0);
res_a : out signed(7 downto 0);
res_b : out signed(7 downto 0)
);
end sliced_ex;
architecture rtl of sliced_ex is
signal tmp : signed(15 downto 0);
begin
SUB_MODULE : entity work.submodule
port map (
clk => clk,
arg( 7 downto 0) => std_logic_vector(arg_a),
arg(15 downto 8) => std_logic_vector(arg_b),
-- The casting of a sliced output causes an exception.
-- Casting of the entire output bus does work
-- signed(res) => tmp -- (this would work)
signed(res( 7 downto 0)) => res_a,
signed(res(15 downto 8)) => res_b
);
end rtl;
| gpl-2.0 | f39cc117cdb55fd418735d4a3b927cb7 | 0.623301 | 3.121212 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1953.vhd | 4 | 1,772 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1953.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01953ent IS
END c07s02b01x00p02n02i01953ent;
ARCHITECTURE c07s02b01x00p02n02i01953arch OF c07s02b01x00p02n02i01953ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := FALSE;
variable c : boolean;
BEGIN
c := a and b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01953"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01953 - Logical operation of 'AND'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01953arch;
| gpl-2.0 | a2194663f1195c2327ecab6b6f3687ce | 0.664786 | 3.676349 | false | true | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/uart.vhd | 1 | 22,032 | --------------------------------------------------------------------------------
-- UART
-- Implements a universal asynchronous receiver transmitter with parameterisable
-- BAUD rate. Tested on a Spartan 6 LX9 connected to a Silicon Labs Cp210
-- USB-UART Bridge.
--
-- @author Peter A Bennett
-- @copyright (c) 2012 Peter A Bennett
-- @license LGPL
-- @email [email protected]
-- @contact www.bytebash.com
--
-- Extended by
-- @author Robert Lange
-- @copyright (c) 2013 Robert Lange
-- @license LGPL
-- @home https://github.com/sd2k9/
--
-- Modified by
-- @author Kevin Johnson
-- @license LGPL
-- @email [email protected]
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Math log2,ceil required to get the number of bits for our counter
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity UART is
Generic (
-- Baudrate in bps
-- The baudrate must satisify the following condition:
-- BAUD_DIVIDER := truncate(CLOCK_FREQUENCY/BAUD_RATE)
-- remainder(BAUD_DIVIDER/16) == 0
-- Why: 16 times oversampling on the receiver side
-- Also take care that the remainder(CLOCK_FREQUENCY/BAUD_RATE) is
-- small because this determines the UART baud rate error
-- See constant c_oversample_divider_val for more information
BAUD_RATE : positive := 9600;
-- Input Clock frequency in Hz
-- Actual clock for SCOMP version is 14.72MHz, but we tell the UART
-- 14.7456MHz to make the divider calculations work out. This creates
-- a 0.13% error, which is well within the acceptable range.
CLOCK_FREQUENCY : positive := 14745600
);
Port (
-- System Clock
CLOCK : in std_logic;
-- High-Active Asynchronous Reset
RESET : in std_logic;
-- The input data: 8 bit - this is the UART sender
-- Provide data on DATA_STREAM_IN and set STB to high
-- Keep the data stable until ACK is set to high which shows that
-- the data is copied into the internal buffer. Then you should
-- revoke STB and you can change IN as you want.
DATA_STREAM_IN : in std_logic_vector(7 downto 0);
DATA_STREAM_IN_STB : in std_logic;
DATA_STREAM_IN_ACK : out std_logic := '0';
-- The output data: 8 bit - this is the UART receiver
-- Data is only valid during the time the STB is high
-- Acknowledge the data with a pulse on ACK, which is confirmed by
-- revoking STB.
-- When the following start bit is received the data becomes
-- invalid and the STB is revoked. So take care about fetching the
-- data early enough, or install your own FIFO buffer
DATA_STREAM_OUT : out std_logic_vector(7 downto 0);
DATA_STREAM_OUT_STB : out std_logic;
DATA_STREAM_OUT_ACK : in std_logic;
TX : out std_logic;
RX : in std_logic -- Async Receive
);
end UART;
architecture RTL of UART is
----------------------------------------------------------------------------
-- BAUD Generation
----------------------------------------------------------------------------
-- First create the divider for the 16 times oversampled baud rate,
-- the baud rate then is derived by dividing by 16.
-- Thats why the 16 times oversampling clock must be derived without any reminder left
-- from the baud rate, to not disturb the resulting bit rate
-- You need to take care about this when selecting baud and clock frequency
-- Substract one, otherwise the reloading step is counted twice
constant c_oversample_divider_steps : natural := natural(CLOCK_FREQUENCY / (16*BAUD_RATE))-1;
-- And also how many bits do we need?
constant c_oversample_divider_bits : natural := natural(ceil(log2(real(c_oversample_divider_steps))));
-- And this is the counter type we use
subtype oversample_baud_counter_type is unsigned(c_oversample_divider_bits-1 downto 0);
-- Please only use this final value
constant c_oversample_divider_val : oversample_baud_counter_type := to_unsigned(c_oversample_divider_steps, c_oversample_divider_bits);
-- Datatype for the rx and tx counter type, must accomodate for the 8bit positions
subtype uart_rxtx_count_type is unsigned(2 downto 0);
constant c_uart_rxtx_count_reset : uart_rxtx_count_type := "000"; -- Reset value: 0
signal oversample_baud_counter : oversample_baud_counter_type := c_oversample_divider_val;
-- Tick created every counter reset
signal oversample_baud_tick : std_ulogic := '0';
-- At this moment we sample the incoming signal
signal uart_rx_sample_tick : std_ulogic := '0';
-- The baud rate itself is the oversampling tick divided by 16
subtype baud_counter_type is unsigned(3 downto 0);
signal baud_counter : baud_counter_type := ( others => '1');
signal baud_tick : std_ulogic := '0';
----------------------------------------------------------------------------
-- Transmitter Signals
----------------------------------------------------------------------------
type uart_tx_states is ( idle,
wait_for_tick,
send_start_bit,
transmit_data,
send_stop_bit);
signal uart_tx_state : uart_tx_states := idle;
signal uart_tx_data_block : std_logic_vector(7 downto 0) := (others => '0');
signal uart_tx_data : std_logic := '1';
signal uart_tx_count : uart_rxtx_count_type := c_uart_rxtx_count_reset; -- 8 states, stored in 3 bits
signal uart_rx_data_in_ack : std_logic := '0';
----------------------------------------------------------------------------
-- Receiver Signals
----------------------------------------------------------------------------
type uart_rx_states is ( rx_wait_start_synchronise -- Wait and deliver data
, rx_get_start_bit -- We are reading the start bit
, rx_get_data
, rx_get_stop_bit
);
signal uart_rx_state : uart_rx_states := rx_wait_start_synchronise;
signal uart_rx_bit : std_logic := '0';
signal uart_rx_data_block : std_logic_vector(7 downto 0) := (others => '0');
signal uart_rx_filter : unsigned(1 downto 0) := (others => '0');
signal uart_rx_count : uart_rxtx_count_type := c_uart_rxtx_count_reset; -- 8 states, stored in 3 bits
signal uart_rx_data_out_stb: std_ulogic := '0';
-- Syncing Clock to Receive Data, compared to baud_counter and creates uart_rx_sample_tick
signal uart_rx_sync_clock : baud_counter_type := (others => '0');
----------------------------------------------------------------------------
-- Helper functions
----------------------------------------------------------------------------
pure function shift_right_by_one ( -- Shift right by 1, fill with new bit
constant shift : in std_logic_vector(7 downto 0); -- Signal to shift
constant fill : in std_ulogic) -- New bit 7
return std_logic_vector is
variable ret : std_logic_vector(7 downto 0);
begin -- function shift_right_by_one
ret(7) := fill;
ret(6 downto 0) := shift (7 downto 1);
return ret;
end function shift_right_by_one;
----------------------------------------------------------------------------
-- Begin Body
----------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- Transmitter Part: Sending Data
----------------------------------------------------------------------------
TX <= uart_tx_data;
-- The input clock is CLOCK_FREQUENCY
-- For example its set to 100Mhz, then needs to be divided down to the
-- rate dictated by the BAUD_RATE. For example, if 115200 baud is selected
-- (115200 baud = 115200 bps - 115.2kbps) a tick must be generated once
-- every 1/115200
-- As explained above we use a two-step approach, so we just scale down
-- here the 16-times oversampled RX clock again
-- Use a down-counter to have a simple test for zero
-- Thats the counter part
TX_CLOCK_DIVIDER : process (CLOCK, RESET)
begin
if RESET = '1' then
baud_counter <= (others => '1');
elsif rising_edge (CLOCK) then
if oversample_baud_tick = '1' then -- Use as Clock enable
if baud_counter = 0 then
baud_counter <= (others => '1');
else
baud_counter <= baud_counter - 1;
end if;
end if;
end if;
end process TX_CLOCK_DIVIDER;
-- And thats the baud tick, which is of course only one clock long
-- So both counters should be Zero
TX_TICK: baud_tick <= '0' when RESET = '1' else
'1' when oversample_baud_tick = '1' and baud_counter = 0 else
'0';
-- Get data from DATA_STREAM_IN and send it one bit at a time
-- upon each BAUD tick. LSB first.
-- Wait 1 tick, Send Start Bit (0), Send Data 0-7, Send Stop Bit (1)
UART_SEND_DATA : process(CLOCK, RESET)
begin
if RESET = '1' then
uart_tx_data <= '1';
uart_tx_data_block <= (others => '0');
uart_tx_count <= c_uart_rxtx_count_reset;
uart_tx_state <= idle;
uart_rx_data_in_ack <= '0';
elsif rising_edge(CLOCK) then
uart_rx_data_in_ack <= '0';
case uart_tx_state is
when idle =>
if DATA_STREAM_IN_STB = '1' then
uart_tx_data_block <= DATA_STREAM_IN;
uart_rx_data_in_ack <= '1';
uart_tx_state <= wait_for_tick;
end if;
when wait_for_tick =>
if baud_tick = '1' then
uart_tx_state <= send_start_bit;
end if;
when send_start_bit =>
if baud_tick = '1' then
uart_tx_data <= '0';
uart_tx_state <= transmit_data;
end if;
when transmit_data =>
if baud_tick = '1' then
-- Send next bit
uart_tx_data <= uart_tx_data_block(0);
-- Shift for next transmit bit, filling with don't care
-- Xilinx ISE does not know srl? So just build it ourself, hehe
-- uart_tx_data_block <= uart_tx_data_block srl 1;
uart_tx_data_block <= shift_right_by_one(uart_tx_data_block, '-');
if uart_tx_count = 7 then -- binary 111
-- We're done, move to next state
uart_tx_state <= send_stop_bit;
else
-- Stay in current state
uart_tx_state <= transmit_data;
end if;
-- Always increment here, will go to zero if we're out
uart_tx_count <= uart_tx_count + 1;
end if;
when send_stop_bit =>
if baud_tick = '1' then
uart_tx_data <= '1';
uart_tx_state <= idle;
end if;
when others =>
uart_tx_data <= '1';
uart_tx_state <= idle;
end case;
end if;
end process UART_SEND_DATA;
----------------------------------------------------------------------------
-- Receiver Part: Getting Data
----------------------------------------------------------------------------
DATA_STREAM_IN_ACK <= uart_rx_data_in_ack;
DATA_STREAM_OUT <= uart_rx_data_block;
DATA_STREAM_OUT_STB <= uart_rx_data_out_stb;
-- The RX clock divider uses the 16 times oversampled clock, which we
-- create here from the input clock
-- Use a down-counter to have a simple test for zero
-- Thats for the counter and tick creation part
RX_CLOCK_DIVIDER : process (CLOCK, RESET)
begin
if RESET = '1' then
oversample_baud_counter <= c_oversample_divider_val;
oversample_baud_tick <= '0';
elsif rising_edge (CLOCK) then
if oversample_baud_counter = 0 then
oversample_baud_counter <= c_oversample_divider_val;
oversample_baud_tick <= '1';
else
oversample_baud_counter <= oversample_baud_counter - 1;
oversample_baud_tick <= '0';
end if;
end if;
end process RX_CLOCK_DIVIDER;
-- We create the sample time by syncing the oversampled tick (BAUD * 16)
-- to the received start bit by comparing then vs. the stored receive sync value
-- It's only one clock tick active
RX_SAMPLE: uart_rx_sample_tick <= '0' when RESET = '1' else
'1' when oversample_baud_tick = '1' and uart_rx_sync_clock = baud_counter else
'0';
-- Synchronise RXD and Filter to suppress spikes with a 2 bit counter
-- This is done with the 16-times oversampled clock
-- Take care, every time the receive clock is resynchronized to the next
-- start bit we can have somewhat of a jump here. But thats no problem
-- because the jump (in case it occur) is still synchronous. And we save us
-- another counter :-)
RXD_SYNC_FILTER : process(CLOCK, RESET)
begin
if RESET = '1' then
uart_rx_filter <= (others => '1');
uart_rx_bit <= '1';
elsif rising_edge(CLOCK) then
if oversample_baud_tick = '1' then
-- Filter RXD.
if RX = '1' and uart_rx_filter < 3 then
uart_rx_filter <= uart_rx_filter + 1;
elsif RX = '0' and uart_rx_filter > 0 then
uart_rx_filter <= uart_rx_filter - 1;
end if;
-- Set the RX bit.
if uart_rx_filter = 3 then
uart_rx_bit <= '1';
elsif uart_rx_filter = 0 then
uart_rx_bit <= '0';
end if;
end if;
end if;
end process RXD_SYNC_FILTER;
UART_RECEIVE_DATA : process(CLOCK, RESET)
begin
if RESET = '1' then
uart_rx_state <= rx_wait_start_synchronise;
uart_rx_data_block <= (others => '0');
uart_rx_count <= c_uart_rxtx_count_reset;
uart_rx_data_out_stb <= '0';
uart_rx_sync_clock <= (others => '0');
elsif rising_edge(CLOCK) then
case uart_rx_state is
-- Waiting for new data to come
when rx_wait_start_synchronise =>
-- With normal clock: Take care about the ACK from
-- previous received data
if DATA_STREAM_OUT_ACK = '1' then
-- Revoke strobe
uart_rx_data_out_stb <= '0';
-- No need to reset data block, it's anyway overwritten during recive
-- uart_rx_data_block <= (others => '0');
end if;
-- Only here we need to look for start with the
-- oversampled clock rate
if oversample_baud_tick = '1' and uart_rx_bit = '0' then
-- We are back in business!
uart_rx_state <= rx_get_start_bit;
-- Resynchronize the receive bit timing with the input signal
-- invert the MSB, because we need to skip half of
-- the start bit.
-- We want to sample in the MIDDLE of the bit, remember?
-- This will be used from now on as sample moment
uart_rx_sync_clock <=
(not baud_counter(3), baud_counter(2), baud_counter(1), baud_counter(0) );
end if; -- oversample_baud_tick = '1' and uart_rx_bit = '0'
when rx_get_start_bit =>
-- With normal clock: Take care about the ACK from
-- previous received data
if DATA_STREAM_OUT_ACK = '1' then
-- Revoke strobe
uart_rx_data_out_stb <= '0';
-- No need to reset data block, it's anyway overwritten during recive
-- uart_rx_data_block <= (others => '0');
end if;
if uart_rx_sample_tick = '1' then
if uart_rx_bit = '0' then
-- Everything alright, we really got a start bit
-- Please continue with data reception
uart_rx_state <= rx_get_data;
-- This is the last time we can revoke a potentially pending
-- receive strobe
-- Your fault if you didn't fetched the data until here!
uart_rx_data_out_stb <= '0';
-- But at least warn about this
-- Not for synthesis:
-- pragma translate_off
assert uart_rx_data_out_stb = '0'
report "Receive Data was not fetched by system! Losing previous data byte!"
severity warning;
-- pragma translate_on
else
-- Oh no! Corrupted Start bit! Now we're in trouble
-- Best to abort the game and issue a (simulation)
-- warning
uart_rx_state <= rx_wait_start_synchronise;
-- Not for synthesis:
-- pragma translate_off
report "We got an corrupted start bit! Something is wrong and most likely we will now fail to receive the following data. Trying to reset the receive state machine."
severity error;
-- pragma translate_on
end if;
end if;
when rx_get_data =>
if uart_rx_sample_tick = '1' then
-- Receive next bit, shift others one bit down
-- We receive lsb first, thus we're filling and shifting from msb direction
uart_rx_data_block <= shift_right_by_one(uart_rx_data_block, uart_rx_bit);
if uart_rx_count = 7 then -- binary 111
-- We're done, move to next state
uart_rx_state <= rx_get_stop_bit;
else
-- Continue in this state
uart_rx_state <= rx_get_data;
end if;
-- Always increment here, will go to zero if we're out
uart_rx_count <= uart_rx_count + 1;
end if;
when rx_get_stop_bit =>
if uart_rx_sample_tick = '1' then
if uart_rx_bit = '1' then
-- Everything alright, we really got the closing stop bit
-- Set our strobe: Data is ready!
uart_rx_data_out_stb <= '1';
else
-- Oh no! Corrupted Stop bit! Now we're in trouble
-- Best to abort the game and issue a (simulation) warning
-- Not for synthesis:
-- pragma translate_off
report "We got an corrupted stop bit! Something is wrong - throwing away this data byte"
severity error;
-- pragma translate_on
end if;
-- Anyway, go to wait for next datablock
uart_rx_state <= rx_wait_start_synchronise;
end if;
when others => -- This is an illegal state - start over
uart_rx_state <= rx_wait_start_synchronise;
end case;
end if;
end process UART_RECEIVE_DATA;
end RTL;
| mit | c099cb296e3074cceb68b4d08d932b7c | 0.469363 | 4.766768 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd | 4 | 1,896 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity lowpass is
generic ( fp : real := 10.0; -- pole in Hz for 'ztf
Fsmp : real := 10.0e3); -- sample frequency for 'ztf
port ( terminal input: electrical;
terminal output: electrical );
end entity lowpass;
----------------------------------------------------------------
architecture ztf of lowpass is
quantity vin across input to electrical_ref;
quantity vout across iout through output to electrical_ref;
constant Tsmp : real := 1.0 / Fsmp; -- sample period
constant wp : real := fp * math_2_pi; -- pole in rad/s
constant n0 : real := Tsmp * wp; -- z0 numerator coefficient (a)
constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient (b)
constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient (c)
constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient (d)
constant num : real_vector := (n0, n1);
constant den : real_vector := (d0, d1);
begin
vout == vin'ztf(num, den, Tsmp);
end ztf;
| gpl-2.0 | 940dfc94cb858c17d8b6f9dedddd19ee | 0.665084 | 3.861507 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth76/dff03.vhdl | 1 | 606 | library ieee;
use ieee.std_logic_1164.all;
entity dff03 is
port (q : out std_logic_vector (3 downto 0);
d : std_logic_vector (3 downto 0);
en : std_logic;
rst : std_logic;
clk : std_logic);
end dff03;
architecture behav of dff03 is
signal t : std_logic_vector (7 downto 4);
signal a : std_logic_vector (3 downto 0);
begin
a <= d xor b"0101";
process (clk) is
begin
if rst = '1' then
q <= x"0";
elsif rising_edge (clk) then
if en = '1' then
q <= d;
t (7 downto 4) <= a;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 7141964d1b231486c2fcbfa883f0f97b | 0.559406 | 3.107692 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1238/tb_multiplexers_3.vhdl | 1 | 1,188 | entity tb_multiplexers_3 is
end tb_multiplexers_3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_multiplexers_3 is
signal di : std_logic_vector(7 downto 0);
signal sel : std_logic_vector(7 downto 0);
signal do : std_logic;
begin
dut: entity work.multiplexers_3
port map (di, sel, do);
process
begin
di <= b"1001_0011";
sel <= not b"0000_0000";
wait for 1 ns;
assert do = 'Z' severity failure;
di <= b"1001_0011";
sel <= not b"0000_0001";
wait for 1 ns;
assert do = '1' severity failure;
di <= b"1001_0011";
sel <= not b"0000_0001";
wait for 1 ns;
assert do = '1' severity failure;
di <= b"1001_0011";
sel <= not b"0001_0001";
wait for 1 ns;
assert do = '1' severity failure;
di <= b"1001_0011";
sel <= not b"0010_0000";
wait for 1 ns;
assert do = '0' severity failure;
di <= b"1001_0011";
sel <= not b"0110_1100";
wait for 1 ns;
assert do = '0' severity failure;
di <= b"1001_0011";
sel <= not b"0010_0001";
wait for 1 ns;
assert do = 'X' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 3818469d8b95ba1f1ff721de246d2743 | 0.577441 | 3.134565 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1069/ram41.vhdl | 1 | 1,648 | library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH : positive := 7;
WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH - 1 downto 0);
clk_b : in std_logic;
read_b : in std_logic;
write_b : in std_logic;
addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0);
data_read_b : out std_logic_vector(WIDTH - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
begin
process(clk_a, clk_b)
type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
variable store : ram_t := (others => (others => '0'));
begin
if rising_edge(clk_a) then
if read_a = '1' then
data_read_a <= store(to_integer(unsigned(addr_a)));
end if;
if write_a = '1' then
store(to_integer(unsigned(addr_a))) := data_write_a;
end if;
elsif rising_edge(clk_b) then
if read_b = '1' then
data_read_b <= store(to_integer(unsigned(addr_b)));
end if;
if write_b = '1' then
store(to_integer(unsigned(addr_b))) := data_write_b;
end if;
end if;
end process;
end behavioral;
| gpl-2.0 | 785df55c57ab00da948052790af7986e | 0.527913 | 3.322581 | false | false | false | false |
nickg/nvc | test/regress/vests36.vhd | 1 | 2,126 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2460.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests36 IS
END vests36;
ARCHITECTURE c07s03b02x02p03n02i02460arch OF vests36 IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
type AGGREGATE_ARRAY is array (1 to 2) of CONSTRAINED_ARRAY;
signal V,W : CONSTRAINED_ARRAY;
BEGIN
TESTING: PROCESS
BEGIN
(V,W) <= AGGREGATE_ARRAY' (('d', 'x', others => 'a'),
('d', 'x', others => 'a'));
wait for 1 ns;
assert NOT( V(1)='d' and V(2)='x' and V(3)='a' )
report "***PASSED TEST: c07s03b02x02p03n02i02460"
severity NOTE;
assert ( V(1)='d' and V(2)='x' and V(3)='a' )
report "***FAILED TEST: c07s03b02x02p03n02i02460 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02460arch;
| gpl-3.0 | 8575f3cc3559400b6cb97d194b72e929 | 0.634995 | 3.823741 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue1051/psi_common_i2c_master_tb.vhd | 1 | 29,129 | ------------------------------------------------------------
-- Copyright (c) 2019 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
------------------------------------------------------------
------------------------------------------------------------
-- Testbench generated by TbGen.py
------------------------------------------------------------
-- see Library/Python/TbGenerator
------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_i2c_master_pkg.all;
library work;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
use work.psi_tb_txt_util.all;
use work.psi_tb_i2c_pkg.all;
------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------
entity psi_common_i2c_master_tb is
generic (
InternalTriState_g : boolean := true
);
end entity;
------------------------------------------------------------
-- Architecture
------------------------------------------------------------
architecture sim of psi_common_i2c_master_tb is
-- *** Fixed Generics ***
constant ClockFrequency_g : real := 125.0e6;
constant I2cFrequency_g : real := 1.0e6;
constant BusBusyTimeout_g : real := 50.0e-6;
constant CmdTimeout_g : real := 10.0e-6;
-- *** Not Assigned Generics (default values) ***
-- *** TB Control ***
signal TbRunning : boolean := True;
signal NextCase : integer := -1;
signal ProcessDone : std_logic_vector(0 to 1) := (others => '0');
constant AllProcessesDone_c : std_logic_vector(0 to 1) := (others => '1');
constant TbProcNr_stim_c : integer := 0;
constant TbProcNr_i2c_c : integer := 1;
signal StimCase : integer := -1;
signal I2cCase : integer := -1;
-- *** DUT Signals ***
signal Clk : std_logic := '1';
signal Rst : std_logic := '1';
signal CmdRdy : std_logic := '0';
signal CmdVld : std_logic := '0';
signal CmdType : std_logic_vector(2 downto 0) := (others => '0');
signal CmdData : std_logic_vector(7 downto 0) := (others => '0');
signal CmdAck : std_logic := '0';
signal RspVld : std_logic := '0';
signal RspData : std_logic_vector(7 downto 0) := (others => '0');
signal RspType : std_logic_vector(2 downto 0) := (others => '0');
signal RspArbLost : std_logic := '0';
signal RspAck : std_logic := '0';
signal RspSeq : std_logic := '0';
signal BusBusy : std_logic := '0';
signal TimeoutCmd : std_logic := '0';
signal I2cScl : std_logic := '0';
signal I2cSda : std_logic := '0';
signal I2cScl_I : std_logic := '0';
signal I2cScl_O : std_logic := '0';
signal I2cScl_T : std_logic := '0';
signal I2cSda_I : std_logic := '0';
signal I2cSda_O : std_logic := '0';
signal I2cSda_T : std_logic := '0';
-- *** Helper Functions ***
procedure WaitForCase( signal TestCase : in integer;
Value : in integer) is
begin
if TestCase /= Value then
wait until TestCase = Value;
end if;
end procedure;
procedure ApplyCmd( Command : in std_logic_vector(2 downto 0);
Data : in std_logic_vector(7 downto 0);
Ack : in std_logic;
signal CmdVld : out std_logic;
signal CmdRdy : in std_logic;
signal CmdType : out std_logic_vector(2 downto 0);
signal CmdData : out std_logic_vector(7 downto 0);
signal CmdAck : out std_logic) is
begin
wait until rising_edge(Clk);
CmdVld <= '1';
CmdType <= Command;
CmdData <= Data;
CmdAck <= Ack;
wait until rising_edge(Clk) and CmdRdy = '1';
CmdVld <= '0';
CmdType <= (others => '0');
CmdData <= (others => '0');
CmdAck <= '0';
end procedure;
procedure CheckRsp( Command : in std_logic_vector(2 downto 0);
Data : in std_logic_vector;
Ack : in std_logic;
ArbLost : in std_logic;
signal RspVld : in std_logic;
signal RspData : in std_logic_vector(7 downto 0);
signal RspType : in std_logic_vector(2 downto 0);
signal RspArbLost : in std_logic;
signal RspAck : in std_logic;
signal RspSeq : in std_logic;
Msg : in string := "No Msg";
Err : in std_logic := '0') is
begin
wait until rising_edge(Clk) and RspVld = '1';
StdlvCompareStdlv(Command, RspType, "Response: Wrong Type - " & Msg);
if Data /= "X" then
StdlvCompareStdlv(Data, RspData, "Response: Wrong Data - " & Msg);
end if;
if Ack /= 'X' then
StdlCompare(choose(Ack = '1', 1, 0), RspAck, "Response: Wrong Ack - " & Msg);
end if;
if ArbLost /= 'X' then
StdlCompare(choose(ArbLost = '1', 1, 0), RspArbLost, "Response: Wrong ArbLost - " & Msg);
end if;
StdlCompare(choose(Err = '1', 1, 0), RspSeq, "Response: Wrong Err - " & Msg);
end procedure;
begin
------------------------------------------------------------
-- DUT Instantiation
------------------------------------------------------------
i_dut : entity work.psi_common_i2c_master
generic map (
ClockFrequency_g => ClockFrequency_g,
I2cFrequency_g => I2cFrequency_g,
BusBusyTimeout_g => BusBusyTimeout_g,
CmdTimeout_g => CmdTimeout_g,
InternalTriState_g => InternalTriState_g,
DisableAsserts_g => true
)
port map (
Clk => Clk,
Rst => Rst,
CmdRdy => CmdRdy,
CmdVld => CmdVld,
CmdType => CmdType,
CmdData => CmdData,
CmdAck => CmdAck,
RspVld => RspVld,
RspType => RspType,
RspArbLost => RspArbLost,
RspData => RspData,
RspAck => RspAck,
RspSeq => RspSeq,
BusBusy => BusBusy,
TimeoutCmd => TimeoutCmd,
I2cScl => I2cScl,
I2cSda => I2cSda,
I2cScl_I => I2cScl_I,
I2cScl_O => I2cScl_O,
I2cScl_T => I2cScl_T,
I2cSda_I => I2cSda_I,
I2cSda_O => I2cSda_O,
I2cSda_T => I2cSda_T
);
------------------------------------------------------------
-- I2C Emulation
------------------------------------------------------------
I2cPullup(I2cScl, I2cSda);
g_triState : if not InternalTriState_g generate
I2cScl <= 'Z' when I2cScl_T = '1' else I2cScl_O;
I2cScl_I <= To01X(I2cScl);
I2cSda <= 'Z' when I2cSda_T = '1' else I2cSda_O;
I2cSda_I <= To01X(I2cSda);
end generate;
------------------------------------------------------------
-- Testbench Control !DO NOT EDIT!
------------------------------------------------------------
p_tb_control : process
begin
wait until Rst = '0';
wait until ProcessDone = AllProcessesDone_c;
TbRunning <= false;
wait;
end process;
------------------------------------------------------------
-- Clocks !DO NOT EDIT!
------------------------------------------------------------
p_clock_Clk : process
constant Frequency_c : real := real(125e6);
begin
while TbRunning loop
wait for 0.5*(1 sec)/Frequency_c;
Clk <= not Clk;
end loop;
wait;
end process;
------------------------------------------------------------
-- Resets
------------------------------------------------------------
p_rst_Rst : process
begin
wait for 1 us;
-- Wait for two clk edges to ensure reset is active for at least one edge
wait until rising_edge(Clk);
wait until rising_edge(Clk);
Rst <= '0';
wait;
end process;
------------------------------------------------------------
-- Processes
------------------------------------------------------------
-- *** stim ***
p_stim : process
begin
I2cSetFrequency(I2cFrequency_g);
-- start of process !DO NOT EDIT
wait until Rst = '0';
wait until rising_edge(Clk);
-- *** Test Bus Busy ***
print(">> Test Bus Busy");
StimCase <= 0;
wait until rising_edge(Clk);
WaitForCase(I2cCase, 0);
wait for 10 us;
-- *** Test Start / Repeated-Start / Stop ***
print(">> Test Start / Repeated-Start / Stop");
StimCase <= 1;
wait until rising_edge(Clk);
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start");
ApplyCmd(CMD_REPSTART, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REPSTART, "X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop");
WaitForCase(I2cCase, 1);
wait for 10 us;
-- *** Test Write ***
print(">> Test Write");
StimCase <= 2;
wait until rising_edge(Clk);
-- 1Byte ACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 1b ACK");
-- 2Byte ACK, then NACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK");
ApplyCmd(CMD_SEND, X"12", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK 1");
ApplyCmd(CMD_SEND, X"34", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK 2");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 2b ACK -> NACK");
WaitForCase(I2cCase, 2);
wait for 10 us;
-- *** Test Read ***
print(">> Test Read");
StimCase <= 3;
wait until rising_edge(Clk);
-- 1Byte ACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"67", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 1b ACK");
-- 2Byte ACK, then NACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK");
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"34", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK 1");
ApplyCmd(CMD_REC, X"00", '0', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"56", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK 2");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 2b ACK -> NACK");
WaitForCase(I2cCase, 3);
wait for 10 us;
-- *** Test Clock Stretching ***
print(">> Test Clock Stretching");
StimCase <= 4;
wait until rising_edge(Clk);
-- 1Byte Read ACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"67", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop Read 1b ACK");
-- 2Byte ACK, then NACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b Write ACK -> NACK");
ApplyCmd(CMD_SEND, X"12", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b Write ACK -> NACK 1");
ApplyCmd(CMD_SEND, X"34", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b Write ACK -> NACK 2");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 2b Write ACK -> NACK");
-- Write / Read
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b W->R");
ApplyCmd(CMD_SEND, X"12", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Write 2b W->R");
ApplyCmd(CMD_REPSTART, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REPSTART, "X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "RepStart 2b W->R");
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"67", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Read 2b W->R");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 2b W->R");
WaitForCase(I2cCase, 4);
wait for 10 us;
-- *** Test Delayed Command *** (clock is held low until command available)
print(">> Test Delayed Command");
StimCase <= 5;
wait until rising_edge(Clk);
-- 1Byte Read ACK, delay shorter than timeout
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
wait for CmdTimeout_g/2.0*(1 sec);
wait until rising_edge(Clk);
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"67", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
wait for CmdTimeout_g/2.0*(1 sec);
wait until rising_edge(Clk);
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop Read 1b ACK");
-- Command Timeout (Timeout after start, other commands ignored)
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
wait for CmdTimeout_g*2.0*(1 sec);
wait until rising_edge(Clk);
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK", Err => '1');
wait for CmdTimeout_g*2.0*(1 sec);
wait until rising_edge(Clk);
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop Read 1b ACK", Err => '1');
WaitForCase(I2cCase, 5);
wait for 10 us;
-- *** Test Arbitration ***
print(">> Test Arbitration");
StimCase <= 6;
wait until rising_edge(Clk);
-- Multi Master, Same Write
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 1b ACK");
-- Arbitration Lost during Write
wait for 10 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost Write");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost Write");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Lost Write", Err => '1');
-- Arbitration Lost during STOP (other master continues writing)
wait for 10 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost Stop");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost Stop");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop Lost Stop");
-- Arbitration Lost during repeated start (other master continues writing)
wait for 20 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost RepStartA");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost RepStartA");
ApplyCmd(CMD_REPSTART, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REPSTART, "X", 'X', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Repstart Lost RepStartA");
-- Arbitration Lost during repeated start (other master stops)
wait for 20 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost RepStartB");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost RepStartB");
ApplyCmd(CMD_REPSTART, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REPSTART, "X", 'X', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Repstart Lost RepStartB");
-- Arbitration lost due to stop (during first bit of data)
wait for 10 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueStop");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueStop 1");
ApplyCmd(CMD_SEND, X"F0", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueStop 2");
-- Arbitration lost due to rep-start (during first bit of data)
wait for 10 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueRepStart");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueRepStart 1");
ApplyCmd(CMD_SEND, X"F0", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueRepStart 2");
WaitForCase(I2cCase, 6);
wait for 10 us;
-- end of process !DO NOT EDIT!
wait for 1 us;
ProcessDone(TbProcNr_stim_c) <= '1';
wait;
end process;
-- *** i2c slave ***
p_i2c_slave : process
begin
I2cBusFree(I2cScl, I2cSda);
-- start of process !DO NOT EDIT
wait until Rst = '0';
wait until rising_edge(Clk);
-- *** Test Bus Busy ***
WaitForCase(StimCase, 0);
-- Not busy
wait for 1 us;
StdlCompare(0, BusBusy, "Busy 0");
-- A transfer is goiong on
I2cScl <= '0';
wait for 1 us;
StdlCompare(1, BusBusy, "Busy 1");
-- busy is kept
I2cScl <= 'Z';
wait for 10 us;
StdlCompare(1, BusBusy, "Busy 2");
-- released after timeout
wait for BusBusyTimeout_g*(1 sec);
StdlCompare(0, BusBusy, "Busy 3");
-- Asserted on start
I2cMasterSendStart(I2cScl, I2cSda, "Assert Start");
wait for 1 us;
StdlCompare(1, BusBusy, "Busy 4");
-- Released on stop
I2cMasterSendStop(I2cScl, I2cSda, "Assert Start");
wait for 1 us;
StdlCompare(0, BusBusy, "Busy 4");
I2cCase <= 0;
-- *** Test Start / Stop ***
WaitForCase(StimCase, 1);
I2cSlaveWaitStart(I2cScl, I2cSda, "Start");
I2cSlaveWaitRepeatedStart(I2cScl, I2cSda, "RepStart");
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
I2cCase <= 1;
-- *** Test Write ***
WaitForCase(StimCase, 2);
-- 1 Byte Ack
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 1b Ack");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "Data 1b Ack", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
-- 2 Byte Ack, then NACK
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 2b ACK -> NACK");
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "Data 2b ACK -> NACK 1", '0');
I2cSlaveExpectByte(16#34#, I2cScl, I2cSda, "Data 2b ACK -> NACK 2", '1');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
I2cCase <= 2;
-- *** Test Read ***
WaitForCase(StimCase, 3);
-- 1 Byte Ack
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 1b Ack");
I2cSlaveSendByte(16#67#, I2cScl, I2cSda, "Data 1b Ack", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
-- 2 Byte Ack, then NACK
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 2b ACK -> NACK");
I2cSlaveSendByte(16#34#, I2cScl, I2cSda, "Data 2b ACK -> NACK 1", '0');
I2cSlaveSendByte(16#56#, I2cScl, I2cSda, "Data 2b ACK -> NACK 2", '1');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
I2cCase <= 3;
-- *** Test Clock Stretching ***
WaitForCase(StimCase, 4);
-- 1 Byte Read Ack
I2cSlaveWaitStart(I2cScl, I2cSda, "Start Read 1b Ack");
I2cSlaveSendByte(16#67#, I2cScl, I2cSda, "Data Write 1b Ack", '0', ClkStretch => 1 us);
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop", ClkStretch => 1 us);
-- 2 Byte Write Ack, then NACK
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 2b Write ACK -> NACK");
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "Data 2b Write ACK -> NACK 1", '0', ClkStretch => 1 us);
I2cSlaveExpectByte(16#34#, I2cScl, I2cSda, "Data 2b Write ACK -> NACK 2", '1', ClkStretch => 1 us);
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop", ClkStretch => 1 us);
-- Write / Read
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 2b W->R");
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "Write 2b W->R", '0', ClkStretch => 1 us);
I2cSlaveWaitRepeatedStart(I2cScl, I2cSda, "RepStart 2b W->R", ClkStretch => 1 us);
I2cSlaveSendByte(16#67#, I2cScl, I2cSda, "Read 2b W->R", '0', ClkStretch => 1 us);
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop 2b W->R", ClkStretch => 1 us);
I2cCase <= 4;
-- *** Test Delayed Command ***
WaitForCase(StimCase, 5);
-- 1 Byte Ack, delay shorter than timeout
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 1b Ack");
I2cSlaveSendByte(16#67#, I2cScl, I2cSda, "Data 1b Ack", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
-- Command Timeout (Timeout after start, stop generated internally)
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 1b Ack");
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
I2cCase <= 5;
-- *** Test Arbitration ***
WaitForCase(StimCase, 6);
-- Multi Master, Same Write
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start 1b Ack");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data 1b Ack", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop");
-- Arbitration Lost during Write
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost Write");
I2cSlaveExpectByte(16#87#, I2cScl, I2cSda, "S: Stop Lost Write", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Lost Write Stop");
-- Arbitration Lost STOP (other master continues writing)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost Stop");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data Lost Stop 1", '0');
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "S: Data Lost Stop 2", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost Stop");
-- Arbitration Lost during repeated start (other master continues writing)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost RepStartA");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data Lost RepStartA 1", '0');
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "S: Data Lost RepStartA 2", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost RepStartA");
-- Arbitration Lost during repeated start (other master stops)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost RepStartB");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data Lost RepStartB 1", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost RepStartB");
-- Arbitration lost due to stop (during first bit of data)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost DueStop");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data Lost DueStop 1", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost DueStop");
-- Arbitration lost due to rep-start (during first bit of data)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost RepStart");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Write Lost RepStart 1", '0');
I2cSlaveWaitRepeatedStart(I2cScl, I2cSda, "S: Lost RepStart RepStart");
I2cSlaveSendByte(16#34#, I2cScl, I2cSda, "S: Read Lost RepStart RepStart", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost RepStart");
I2cCase <= 6;
-- end of process !DO NOT EDIT!
ProcessDone(TbProcNr_i2c_c) <= '1';
wait;
end process;
-- *** i2c master ***
p_i2c_master : process
begin
I2cBusFree(I2cScl, I2cSda);
-- *** Test Arbitration ***
WaitForCase(StimCase, 6);
-- Multi Master, Same Write
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start 1b Ack");
-- small delay
I2cScl <= '0';
wait for 100 ns;
-- continue
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data 1b Ack");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop");
-- Arbitration Lost during Write
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost Write");
I2cMasterSendByte(16#87#, I2cScl, I2cSda, "M: Data Lost Write");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Loast Read");
-- Arbitration Lost STOP (other master continues writing)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost Stop");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data Lost Stop 1");
I2cMasterSendByte(16#12#, I2cScl, I2cSda, "M: Data Lost Stop 2");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost Stop");
-- Arbitration Lost during repeated start (other master continues writing)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost RepStartA");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data Lost RepStartA 1");
I2cMasterSendByte(16#12#, I2cScl, I2cSda, "M: Data Lost RepStartA 2");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost RepStartA");
-- Arbitration Lost during repeated start (other master stops)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost RepStartB");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data Lost RepStartB 1");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost RepStartB");
-- Arbitration lost due to stop (during first bit of data)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost DueStop");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data Lost DueStop 1");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost DueStop");
-- Arbitration lost due to rep-start (during first bit of data)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost DueRepstart");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: write Lost DueRepstart 1");
I2cMasterSendRepeatedStart(I2cScl, I2cSda, "M: Stop Lost DueRepstart");
I2cMasterExpectByte(16#34#, I2cScl, I2cSda, "M: read Lost DueRepstart 1");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost DueRepstart");
wait;
end process;
end;
| gpl-2.0 | 997496ea0de6ea44862f18198f262468 | 0.623262 | 3.068795 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1273/tb_assert5.vhdl | 1 | 1,184 | entity tb_assert5 is
generic (with_err : boolean := False);
end tb_assert5;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_assert5 is
signal v : std_logic_Vector (7 downto 0);
signal en : std_logic := '0';
signal rst : std_logic;
signal clk : std_logic;
signal res : std_logic;
begin
dut: entity work.assert5
port map (v, en, clk, rst, res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
rst <= '0';
en <= '1';
v <= b"0010_0000";
pulse;
assert res = '0' severity failure;
v <= b"0010_0001";
pulse;
assert res = '1' severity failure;
v <= b"0010_0011";
pulse;
assert res = '0' severity failure;
v <= b"0010_0010";
pulse;
assert res = '1' severity failure;
en <= '0';
v <= x"05";
pulse;
assert res = '1' severity failure;
rst <= '1';
wait for 1 ns;
assert res = '0' severity failure;
-- Trigger an error.
if with_err then
en <= '1';
rst <= '0';
pulse;
end if;
wait;
end process;
end behav;
| gpl-2.0 | 2c176051e31ed98346ed221392db2987 | 0.545608 | 3.261708 | false | false | false | false |
nickg/nvc | test/regress/link3.vhd | 1 | 2,986 | -- From OSVVM
--
use std.textio.all ;
package NamePkg is
type NamePType is protected
procedure Set (NameIn : String) ;
impure function Get (DefaultName : string := "") return string ;
impure function GetOpt return string ;
impure function IsSet return boolean ;
procedure Clear ; -- clear name
procedure Deallocate ; -- effectively alias to clear name
end protected NamePType ;
end package NamePkg ;
package body NamePkg is
type NamePType is protected body
variable NamePtr : line ;
------------------------------------------------------------
procedure Set (NameIn : String) is
------------------------------------------------------------
begin
deallocate(NamePtr) ;
NamePtr := new string'(NameIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (DefaultName : string := "") return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return DefaultName ;
else
return NamePtr.all ;
end if ;
end function Get ;
------------------------------------------------------------
impure function GetOpt return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return NUL & "" ;
else
return NamePtr.all ;
end if ;
end function GetOpt ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return NamePtr /= NULL ;
end function IsSet ;
------------------------------------------------------------
procedure Clear is -- clear name
------------------------------------------------------------
begin
deallocate(NamePtr) ;
end procedure Clear ;
------------------------------------------------------------
procedure Deallocate is -- clear name
------------------------------------------------------------
begin
Clear ;
end procedure Deallocate ;
end protected body NamePType ;
end package body NamePkg ;
-------------------------------------------------------------------------------
use work.namepkg.all;
package other_pkg is
type otherptype is protected
procedure do_clear;
end protected;
end package;
package body other_pkg is
type otherptype is protected body
variable n : nameptype;
procedure do_clear is
begin
n.clear;
end procedure;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity link3 is
end entity;
use work.other_pkg.all;
architecture test of link3 is
shared variable p : otherptype;
begin
p1: process is
begin
p.do_clear;
wait;
end process;
end architecture;
| gpl-3.0 | 4416c1517e2d707af8c1a733b8e304e1 | 0.441393 | 6.093878 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1283/issue1.vhdl | 1 | 352 | library ieee;
use ieee.std_logic_1164.all;
entity issue1 is
end issue1;
architecture beh of issue1 is
type t_rec is
record
elem : std_logic_vector;
end record;
begin
assert t_rec'(elem => "000") = t_rec'(elem => "000");
assert t_rec'(elem => "001") = t_rec'(elem => "000") severity note;
end architecture beh;
| gpl-2.0 | d2e8c92557c28f1130ae8eac1def9374 | 0.610795 | 3.259259 | false | false | false | false |
nickg/nvc | test/regress/issue547.vhd | 1 | 608 | entity sub is
signal x : bit;
end entity;
architecture test of sub is
begin
x <= '1';
process is
begin
assert x = '0';
wait for 0 ns;
assert x = '1';
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity issue547 is
signal s : natural;
end entity;
architecture test of issue547 is
begin
u: entity work.sub;
p1: process is
begin
assert s = 0;
s <= 1;
wait for 1 ns;
assert s = 1;
wait;
end process;
end architecture;
| gpl-3.0 | e27ccdd063625b8fcbd03a6ffe7e6d00 | 0.473684 | 4.164384 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd | 4 | 1,758 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity lessthan is
end entity lessthan;
architecture test of lessthan is
-- code from book
function "<" ( a, b : bit_vector ) return boolean is
variable tmp1 : bit_vector(a'range) := a;
variable tmp2 : bit_vector(b'range) := b;
begin
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return std.standard."<" ( tmp1, tmp2 );
end function "<";
-- end code from book
signal a, b : bit_vector(7 downto 0);
signal result : boolean;
begin
dut : result <= a < b;
stimulus : process is
begin
wait for 10 ns;
a <= X"02"; b <= X"04"; wait for 10 ns;
a <= X"02"; b <= X"02"; wait for 10 ns;
a <= X"02"; b <= X"01"; wait for 10 ns;
a <= X"02"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"02"; wait for 10 ns;
a <= X"FE"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"FC"; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 3d3a99b2004d13f49bbe677387f28c16 | 0.643345 | 3.380769 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1157/ent.vhdl | 1 | 2,156 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
port (
sgn : signed(7 downto 0) := x"f8";
uns : unsigned(7 downto 0) := x"07";
nat : natural := 15;
int : integer := -3;
mul_int_int : out integer;
mul_uns_uns : out unsigned(15 downto 0);
mul_uns_nat : out unsigned(15 downto 0);
mul_nat_uns : out unsigned(15 downto 0);
mul_sgn_sgn : out signed(15 downto 0);
mul_sgn_int : out signed(15 downto 0);
mul_int_sgn : out signed(15 downto 0);
div_int_int : out integer;
div_uns_uns : out unsigned(7 downto 0);
div_uns_nat : out unsigned(7 downto 0);
div_nat_uns : out unsigned(7 downto 0);
div_sgn_sgn : out signed(7 downto 0);
div_sgn_int : out signed(7 downto 0);
div_int_sgn : out signed(7 downto 0);
rem_int_int : out integer;
rem_uns_uns : out unsigned(7 downto 0);
rem_uns_nat : out unsigned(7 downto 0);
rem_nat_uns : out unsigned(7 downto 0);
rem_sgn_sgn : out signed(7 downto 0);
rem_sgn_int : out signed(7 downto 0);
rem_int_sgn : out signed(7 downto 0);
mod_int_int : out integer;
mod_uns_uns : out unsigned(7 downto 0);
mod_uns_nat : out unsigned(7 downto 0);
mod_nat_uns : out unsigned(7 downto 0);
mod_sgn_sgn : out signed(7 downto 0);
mod_sgn_int : out signed(7 downto 0);
mod_int_sgn : out signed(7 downto 0)
);
end;
architecture a of ent is
begin
mul_int_int <= int * int;
mul_uns_uns <= uns * uns;
mul_uns_nat <= uns * nat;
mul_nat_uns <= nat * uns;
mul_sgn_sgn <= sgn * sgn;
mul_sgn_int <= sgn * int;
mul_int_sgn <= int * sgn;
div_int_int <= int / int;
div_uns_uns <= uns / uns;
div_uns_nat <= uns / nat;
div_nat_uns <= nat / uns;
div_sgn_sgn <= sgn / sgn;
div_sgn_int <= sgn / int;
div_int_sgn <= int / sgn;
rem_int_int <= int rem int;
rem_uns_uns <= uns rem uns;
rem_uns_nat <= uns rem nat;
rem_nat_uns <= nat rem uns;
rem_sgn_sgn <= sgn rem sgn;
rem_sgn_int <= sgn rem int;
rem_int_sgn <= int rem sgn;
mod_int_int <= int mod int;
mod_uns_uns <= uns mod uns;
mod_uns_nat <= uns mod nat;
mod_nat_uns <= nat mod uns;
mod_sgn_sgn <= sgn mod sgn;
mod_sgn_int <= sgn mod int;
mod_int_sgn <= int mod sgn;
end;
| gpl-2.0 | c5ef4ebad1a80183bd24ae179ec66047 | 0.628942 | 2.563615 | false | false | false | false |
tgingold/ghdl | testsuite/synth/psl01/cover1.vhdl | 1 | 509 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cover1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end cover1;
architecture behav of cover1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
--psl default clock is rising_edge(clk);
--psl cover {val = 10};
end behav;
| gpl-2.0 | 164dd05a1c5f1f7907ba439185aa8376 | 0.618861 | 3.141975 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/rom.vhd | 1 | 2,018 |
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity rom is
generic (
DATA_WIDTH : natural := 64;
ADDR_WIDTH : natural := 2
);
port (
CLK : in std_logic;
ADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
EN : in std_logic;
DO : out std_logic_vector(DATA_WIDTH-1 downto 0);
VAL : out std_logic
);
end entity rom;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture behavioral of rom is
type mem is array (2**ADDR_WIDTH - 1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
constant my_Rom : mem := (
0 => x"7640_5a81_30fb_0000",
1 => x"30fb_5a81_7640_7fff",
2 => x"89C0_A57F_CF05_0000",
3 => x"CF05_A57F_89C0_8001"
);
--FMC230
--0000
--30fb
--5a81
--7640
--7fff
--7640
--5a81
--30fb
--0000
--CF05
--A57F
--89C0
--8001
--89C0
--A57F
--CF05
--***********************************************************************************
begin
--***********************************************************************************
process (CLK)
begin
if rising_edge(clk) then
VAL <= '0';
if EN = '1' then
DO <= my_Rom(conv_integer(ADDR)) ;
VAL <= '1';
end if;
end if;
end process;
--***********************************************************************************
end architecture behavioral;
--***********************************************************************************
| mit | f715b7c323ba8cde6bbe5b79156914c9 | 0.318137 | 4.248421 | false | false | false | false |
nickg/nvc | lib/synopsys/std_logic_arith.vhd | 1 | 70,558 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
library nvc;
use nvc.sim_pkg.ieee_warnings;
package body std_logic_arith is
constant NO_WARNING : BOOLEAN := not ieee_warnings;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- synopsys subpgm_id 366
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert no_warning
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
-- synopsys subpgm_id 367
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert no_warning
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert no_warning
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert no_warning
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- synopsys subpgm_id 371
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 372
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 373
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 375
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 376
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 377
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 378
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 380
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 381
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 382
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 383
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 384
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 385
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 386
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
| gpl-3.0 | 1efab08aa69b0f7bf63b5aa69a09cc31 | 0.640197 | 3.436489 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd | 4 | 2,127 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity address_decoder is
port ( addr : in work.cpu_types.address;
status : in work.cpu_types.status_value;
mem_sel, int_sel, io_sel : out bit );
end entity address_decoder;
--------------------------------------------------
architecture functional of address_decoder is
constant mem_low : work.cpu_types.address := X"000000";
constant mem_high : work.cpu_types.address := X"EFFFFF";
constant io_low : work.cpu_types.address := X"F00000";
constant io_high : work.cpu_types.address := X"FFFFFF";
begin
mem_decoder :
mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch)
or work.cpu_types."="(status, work.cpu_types.mem_read)
or work.cpu_types."="(status, work.cpu_types.mem_write) )
and addr >= mem_low
and addr <= mem_high else
'0';
int_decoder :
int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else
'0';
io_decoder :
io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read)
or work.cpu_types."="(status, work.cpu_types.io_write) )
and addr >= io_low
and addr <= io_high else
'0';
end architecture functional;
| gpl-2.0 | 40f9bc4e2d3a7010c86e82c4a573ba07 | 0.61213 | 3.953532 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue2/sortnet_BitonicSort.vhdl | 2 | 10,748 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Bug-Reproducer: Sorting Network: Bitonic-Sort
-- Original Source: See https://github.com/VLSI-EDA/PoC
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package packages is
type T_SLM is array(NATURAL range <>, NATURAL range <>) of STD_LOGIC;
function to_sl(Value : BOOLEAN) return STD_LOGIC;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function slm_slice_rows(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM;
function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM;
end package;
package body packages is
function to_sl(Value : BOOLEAN) return STD_LOGIC is
begin
if (Value = TRUE) then
return '1';
else
return '0';
end if;
end function;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel));
end function;
function slm_slice_rows(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM is
variable Result : T_SLM(High - Low downto 0, slm'length(2) - 1 downto 0) := (others => (others => '0'));
begin
for i in 0 to High - Low loop
for j in 0 to slm'length(2) - 1 loop
Result(i, j) := slm(Low + i, slm'low(2) + j);
end loop;
end loop;
return Result;
end function;
-- Matrix concatenation: slm_merge_*
function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is
constant ROWS : POSITIVE := slm1'length(1) + slm2'length(1);
constant COLUMNS : POSITIVE := slm1'length(2);
variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0);
begin
for i in slm1'range(1) loop
for j in slm1'low(2) to slm1'high(2) loop
slm(i, j) := slm1(i, j);
end loop;
end loop;
for i in slm2'range(1) loop
for j in slm2'low(2) to slm2'high(2) loop
slm(slm1'length(1) + i, j) := slm2(i, j);
end loop;
end loop;
return slm;
end function;
end package body;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.packages.all;
entity sortnet_BitonicSort_Merge is
generic (
INPUTS : POSITIVE := 8;
KEY_BITS : POSITIVE := 16;
DATA_BITS : POSITIVE := 16;
INVERSE : BOOLEAN := FALSE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
DataInputs : in T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
DataOutputs : out T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0)
);
end entity;
architecture rtl of sortnet_BitonicSort_Merge is
constant HALF_INPUTS : NATURAL := INPUTS / 2;
subtype T_DATA is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
type T_DATA_VECTOR is array(NATURAL range <>) of T_DATA;
function to_dv(slm : T_SLM) return T_DATA_VECTOR is
variable Result : T_DATA_VECTOR(slm'range(1));
begin
for i in slm'high(1) downto slm'low(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(i)(j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_slm(dv : T_DATA_VECTOR) return T_SLM is
variable Result : T_SLM(dv'range, T_DATA'range);
begin
for i in dv'range loop
for j in T_DATA'range loop
Result(i, j) := dv(i)(j);
end loop;
end loop;
return Result;
end function;
signal DataInputVector : T_DATA_VECTOR(INPUTS - 1 downto 0);
signal IntermediateVector : T_DATA_VECTOR(INPUTS - 1 downto 0);
signal DataInputMatrix1 : T_SLM(HALF_INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataInputMatrix2 : T_SLM(HALF_INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix1 : T_SLM(HALF_INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix2 : T_SLM(HALF_INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputVector : T_DATA_VECTOR(INPUTS - 1 downto 0);
begin
genMergers : if (INPUTS > 1) generate
DataInputVector <= to_dv(DataInputs);
genSwitches : for i in 0 to HALF_INPUTS - 1 generate
signal Smaller : STD_LOGIC;
signal Switch : STD_LOGIC;
begin
Smaller <= to_sl(DataInputVector(i)(KEY_BITS - 1 downto 0) < DataInputVector(i + HALF_INPUTS)(KEY_BITS - 1 downto 0));
Switch <= Smaller xnor to_sl(INVERSE);
IntermediateVector(i) <= mux(Switch, DataInputVector(i), DataInputVector(i + HALF_INPUTS));
IntermediateVector(i + HALF_INPUTS) <= mux(Switch, DataInputVector(i + HALF_INPUTS), DataInputVector(i));
end generate;
DataInputMatrix1 <= to_slm(IntermediateVector(HALF_INPUTS - 1 downto 0));
DataInputMatrix2 <= to_slm(IntermediateVector(INPUTS - 1 downto HALF_INPUTS));
merge1 : entity work.sortnet_BitonicSort_Merge
generic map (
INPUTS => HALF_INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS,
INVERSE => INVERSE
)
port map (
Clock => Clock,
Reset => Reset,
DataInputs => DataInputMatrix1,
DataOutputs => DataOutputMatrix1
);
merge2 : entity work.sortnet_BitonicSort_Merge
generic map (
INPUTS => INPUTS - HALF_INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS,
INVERSE => INVERSE
)
port map (
Clock => Clock,
Reset => Reset,
DataInputs => DataInputMatrix2,
DataOutputs => DataOutputMatrix2
);
DataOutputs <= slm_merge_rows(DataOutputMatrix1, DataOutputMatrix2);
end generate;
genPassThrough : if (INPUTS = 1) generate
DataOutputs <= DataInputs;
end generate;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.packages.all;
entity sortnet_BitonicSort_Sort is
generic (
INPUTS : POSITIVE := 8;
KEY_BITS : POSITIVE := 16;
DATA_BITS : POSITIVE := 16;
INVERSE : BOOLEAN := FALSE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
DataInputs : in T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
DataOutputs : out T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0)
);
end entity;
architecture rtl of sortnet_BitonicSort_Sort is
constant HALF_INPUTS : NATURAL := INPUTS / 2;
signal DataInputMatrix1 : T_SLM(HALF_INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataInputMatrix2 : T_SLM(HALF_INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix1 : T_SLM(HALF_INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix2 : T_SLM(HALF_INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataInputMatrix3 : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix3 : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
begin
genMergers : if (INPUTS > 1) generate
DataInputMatrix1 <= slm_slice_rows(DataInputs, HALF_INPUTS - 1, 0);
DataInputMatrix2 <= slm_slice_rows(DataInputs, INPUTS - 1, HALF_INPUTS);
sort1 : entity work.sortnet_BitonicSort_Sort
generic map (
INPUTS => HALF_INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS,
INVERSE => FALSE
)
port map (
Clock => Clock,
Reset => Reset,
DataInputs => DataInputMatrix1,
DataOutputs => DataOutputMatrix1
);
sort2 : entity work.sortnet_BitonicSort_Sort
generic map (
INPUTS => INPUTS - HALF_INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS,
INVERSE => TRUE
)
port map (
Clock => Clock,
Reset => Reset,
DataInputs => DataInputMatrix2,
DataOutputs => DataOutputMatrix2
);
DataInputMatrix3 <= slm_merge_rows(DataInputMatrix1, DataInputMatrix2);
merge : entity work.sortnet_BitonicSort_Merge
generic map (
INPUTS => INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS,
INVERSE => INVERSE
)
port map (
Clock => Clock,
Reset => Reset,
DataInputs => DataInputMatrix3,
DataOutputs => DataOutputMatrix3
);
DataOutputs <= DataOutputMatrix3;
end generate;
genPassThrough : if (INPUTS = 1) generate
DataOutputs <= DataInputs;
end generate;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.packages.all;
entity sortnet_BitonicSort is
generic (
INPUTS : POSITIVE := 8;
KEY_BITS : POSITIVE := 16;
DATA_BITS : POSITIVE := 16;
ADD_OUTPUT_REGISTERS : BOOLEAN := TRUE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
DataInputs : in T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
DataOutputs : out T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0)
);
end entity;
architecture rtl of sortnet_BitonicSort is
signal DataInputMatrix1 : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix1 : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
begin
DataInputMatrix1 <= DataInputs;
sort : entity work.sortnet_BitonicSort_Sort
generic map (
INPUTS => INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS,
INVERSE => FALSE
)
port map (
Clock => Clock,
Reset => Reset,
DataInputs => DataInputMatrix1,
DataOutputs => DataOutputMatrix1
);
genOutReg : if (ADD_OUTPUT_REGISTERS = TRUE) generate
DataOutputs <= DataOutputMatrix1 when rising_edge(Clock);
end generate;
genNoOutReg : if (ADD_OUTPUT_REGISTERS = FALSE) generate
DataOutputs <= DataOutputMatrix1;
end generate;
end architecture;
| gpl-2.0 | e6cfb03b73c537dd28dd20a59b2651d8 | 0.626907 | 3.175185 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue44/q_one_dot_fp_multiplier.vhdl | 2 | 870 | -- q_one_dot_fp_multiplier.vhd
--TODO: Better way of handling -1 * -1 case?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity q_one_dot_fp_multiplier is
generic (a_word_size, b_word_size:integer);
port(a: in signed(a_word_size-1 downto 0);
b: in signed(b_word_size-1 downto 0);
mult_out: out signed(a_word_size + b_word_size -2 downto 0));
end q_one_dot_fp_multiplier;
architecture mult_arch of q_one_dot_fp_multiplier is
constant a_minus_1: signed(a'range) := ('1', others=>'0');
constant b_minus_1: signed(b'range) := ('1', others => '0');
begin
process(a, b)
variable output_temp:signed(mult_out'length downto 0);
begin
output_temp := a * b;
if (a = a_minus_1) and (b = b_minus_1) then
mult_out <= ('0', others =>'1');
else
mult_out <= output_temp(mult_out'length-1 downto 0);
end if;
end process;
end mult_arch;
| gpl-2.0 | a0eb74cb25d94a18dbff3d1e149936f3 | 0.665517 | 2.581602 | false | false | false | false |
nickg/nvc | test/regress/bounds29.vhd | 1 | 709 | entity bounds29 is
end entity;
architecture test of bounds29 is
subtype my_real is real range 0.0 to 10.0;
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI;
begin
main: process is
variable p1, p2 : principal_value;
variable r : my_real;
begin
p1 := -0.78539815744037; -- OK
wait for 1 ns;
p2 := p1; -- OK
r := 5.0; -- OK
wait for 1 ns;
r := r * 2.0; -- OK
wait for 1 ns;
r := r + 0.00001; -- Error
wait;
end process;
end architecture;
| gpl-3.0 | 3ce0be0e6075f036279be9462313fe82 | 0.480959 | 3.771277 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | CLAH/CLA4bits/16bits/CLAH16bits/CLAH16bits.vhd | 1 | 2,909 | LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH16bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END CLAH16bits;
ARCHITECTURE strc_CLAH16bits of CLAH16bits is
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL P0_sig, P1_sig, P2_sig, P3_sig: STD_LOGIC;
SIGNAL G0_sig, G1_sig, G2_sig, G3_sig: STD_LOGIC;
SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL SomaT1,SomaT2,SomaT3,SomaT4:STD_LOGIC_VECTOR(3 DOWNTO 0);
Component CLA4bits
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
end component;
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg16Bit
PORT (
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end component;
Component CLGB
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
end component;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som1: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(3 DOWNTO 0),
val2(3 DOWNTO 0) => B_sig(3 DOWNTO 0),
CarryIn=>Cin_sig,
P=>P0_sig,
G=>G0_sig,
SomaResult=>SomaT1
);
CLGB1: CLGB PORT MAP(
P0=>P0_sig,
G0=>G0_sig,
P1=>P1_sig,
G1=>G1_sig,
Cin=>Cin_sig,
Cout1=>Cout1_temp_sig,
Cout2=>Cout2_temp_sig
);
Som2: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(7 DOWNTO 4),
val2(3 DOWNTO 0) => B_sig(7 DOWNTO 4),
CarryIn=>Cout1_temp_sig,
P=>P1_sig,
G=>G1_sig,
SomaResult=>SomaT2
);
Som3: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(11 DOWNTO 8),
val2(3 DOWNTO 0) => B_sig(11 DOWNTO 8),
CarryIn=>Cout2_temp_sig,
P=>P2_sig,
G=>G2_sig,
SomaResult=>SomaT3
);
CLGB2: CLGB PORT MAP(
P0=>P2_sig,
G0=>G2_sig,
P1=>P3_sig,
G1=>G3_sig,
Cin=>Cout2_temp_sig,
Cout1=>Cout3_temp_sig,
Cout2=>Cout_sig
);
Som4: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(15 DOWNTO 12),
val2(3 DOWNTO 0) => B_sig(15 DOWNTO 12),
CarryIn=>Cout3_temp_sig,
P=>P3_sig,
G=>G3_sig,
SomaResult=>SomaT4
);
Out_sig <= SomaT4 & SomaT3 & SomaT2 & SomaT1;
END strc_CLAH16bits; | mit | 226f4e55b131f85ae8994dc19c12cdf7 | 0.64352 | 2.338424 | false | false | false | false |
nickg/nvc | test/elab/issue435.vhd | 1 | 1,216 | entity SAMPLE is
generic (
QUEUE_SIZE : integer := 0
);
end entity;
architecture RTL of SAMPLE is
begin
QUEUE_SIZE_VALID: if (QUEUE_SIZE >= 0) generate
end generate;
end RTL;
entity issue435 is
generic (
PORT_DATA_BITS : integer := 32;
POOL_DATA_BITS : integer := 32;
ALIGNMENT_BITS : integer := 8;
QUEUE_SIZE : integer := 1
);
end entity;
architecture RTL of issue435 is
type SETTING_TYPE is record
Q_Q_SIZE : integer;
end record;
function SET_SETTING return SETTING_TYPE is
variable setting : SETTING_TYPE;
constant POOL_WORDS : integer := POOL_DATA_BITS / ALIGNMENT_BITS;
constant PORT_WORDS : integer := PORT_DATA_BITS / ALIGNMENT_BITS;
begin
if (PORT_DATA_BITS /= ALIGNMENT_BITS) or
(POOL_DATA_BITS /= ALIGNMENT_BITS) then
setting.Q_Q_SIZE := POOL_WORDS*(QUEUE_SIZE+1)+PORT_WORDS-1;
else
setting.Q_Q_SIZE := -1;
end if;
return setting;
end function;
constant SET : SETTING_TYPE := SET_SETTING;
begin
Q: entity WORK.SAMPLE generic map (QUEUE_SIZE => SET.Q_Q_SIZE);
end RTL;
| gpl-3.0 | f1d98eb161deaf28a9633720eaf2f3bd | 0.586349 | 3.696049 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/i2c_master.vhd | 1 | 14,852 | --------------------------------------------------------------------------------
--
-- This I2C master has been modified by Kevin Johnson.
-- 05 May 2014
-- Original release information below.
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/1/2012 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 400_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 100_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, restart, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --clock edges for sda
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_req : STD_LOGIC := '0'; --flag to enable scl_ena
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL ena_int : STD_LOGIC; --sampled ena signal
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
BEGIN
ena_int <= ena;
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
IF(count = divider*4-1) THEN --end of timing cycle
IF(stretch = '0') THEN --if clock stretching not detected
count := 0; --reset timer
END IF;
ELSE
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider*2-1 => --first 1/4 cycle of clocking
scl_clk <= '0';
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
scl_clk <= 'Z'; --release scl
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= 'Z';
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
END CASE;
CASE count IS
WHEN 1 TO divider*2 => --first 1/4 cycle of clocking
data_clk <= '1';
WHEN OTHERS => --third 1/4 cycle of clocking
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(data_clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_req <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(RISING_EDGE(data_clk)) THEN
CASE state IS
WHEN ready => --idle state
IF(ena_int = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
scl_req <= '1'; --enable scl output
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN restart => --send start condition without prior stop
scl_req <= '1';
state <= start; --go to start
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(ack_error = '1') THEN
state <= stop; --no ack; stop communication
scl_req <= '0'; --stop scl
ELSIF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF((ena_int = '1') AND ((addr & rw) = addr_rw)) THEN --continuing with another read
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ack_error = '1') THEN --if no ack
scl_req <= '0'; --disable scl
state <= stop; --end communication
ELSIF(addr_rw(7 downto 1) /= addr) THEN
scl_req <= '0'; --disable scl
state <= stop; --different address requested; stop this one
ELSIF(ena_int = '1') THEN --continue transaction
busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(rw = '1') THEN --continue transaction with a read
scl_req <= '0';
sda_int <= '1';
state <= restart; --go to repeated start
ELSE --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
END IF;
ELSE --complete transaction
scl_req <= '0'; --disable scl
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena_int = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr /= addr_rw(7 downto 1)) THEN
scl_req <= '0';
state <= stop; --different address; stop this transaction
ELSIF(rw = '0') THEN --continue transaction with a write
scl_req <= '0';
sda_int <= '1';
state <= restart; --repeated start
ELSE --continue transaction with another read
sda_int <= '1'; --release sda for incoming data
state <= rd; --go to read byte
END IF;
ELSE --complete transaction
scl_req <= '0'; --disable scl
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to ready state
END CASE;
END IF;
--reading from sda during scl high (falling edge of data_clk)
IF(reset_n = '0') THEN --reset asserted
ack_error <= '0';
ELSIF(FALLING_EDGE(data_clk)) THEN
CASE state IS
WHEN start => --starting new transaction
ack_error <= '0'; --reset acknowledge error flag
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF (sda /= '0') OR (ack_error = '1') THEN
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF (sda /= '0') OR (ack_error = '1') THEN
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN OTHERS =>
NULL;
END CASE;
scl_ena <= scl_req; -- enable/disable scl only when safe
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <=
'0' WHEN start, --generate start condition
'1' WHEN restart, -- generate restart condition
'0' WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= scl_clk WHEN scl_ena = '1' ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic;
| mit | 6270c6b87ed77eb2ab62561a3229334a | 0.470509 | 4.664573 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/outdata_comp_buf.vhd | 2 | 1,480 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity outdata_comp_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(14 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(14 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end outdata_comp_buf;
architecture augh of outdata_comp_buf is
-- Embedded RAM
type ram_type is array (0 to 24575) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 24576 else (others => '-');
end architecture;
| gpl-2.0 | e3ddc32e7565d08fdf7cf030598d6352 | 0.673649 | 2.907662 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth111/rams_sp_3d.vhdl | 1 | 1,563 | -- 3-D Ram Inference Example (Single port)
-- Compile this file in VHDL2008 mode
-- File:rams_sp_3d.vhd
library ieee;
use ieee.std_logic_1164.all;
package mypack is
type myarray_t is array(integer range<>) of std_logic_vector;
type mem_t is array(integer range<>) of myarray_t;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mypack.all;
entity rams_sp_3d is generic (
NUM_RAMS : integer := 2;
A_WID : integer := 10;
D_WID : integer := 32
);
port (
clk : in std_logic;
we : in std_logic_vector(NUM_RAMS-1 downto 0);
ena : in std_logic_vector(NUM_RAMS-1 downto 0);
addr : in myarray_t(NUM_RAMS-1 downto 0)(A_WID-1 downto 0);
din : in myarray_t(NUM_RAMS-1 downto 0)(D_WID-1 downto 0);
dout : out myarray_t(NUM_RAMS-1 downto 0)(D_WID-1 downto 0)
);
end rams_sp_3d;
architecture arch of rams_sp_3d is
signal mem : mem_t(NUM_RAMS-1 downto 0)(2**A_WID-1 downto 0)(D_WID-1 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1') then
for i in 0 to NUM_RAMS-1 loop
if(ena(i) = '1') then
if(we(i) = '1') then
mem(i)(to_integer(unsigned(addr(i)))) <= din(i);
end if;
dout(i) <= mem(i)(to_integer(unsigned(addr(i))));
end if;
end loop;
end if;
end process;
end arch;
| gpl-2.0 | 34685cf9f96db9436a4aa99b24bffe34 | 0.53231 | 3.27673 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_toggle_xxbit/tb_toggle.vhd | 1 | 7,036 | -------------------------------------------------------------------------------------
-- FILE NAME : tb_toggle.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
--Library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_toggle is
end tb_toggle;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_toggle is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_10_MHZ : time := 100 ns;
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_368_MHZ : time := 2.7126 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
constant DATA_WIDTH : natural := 8;
constant ADDR_WIDTH : natural := 8;
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
type bus016 is array(natural range <>) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal clk200 : std_logic := '1';
signal clk100 : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal rst_rstin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_clkin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_cmd : std_logic;
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal out_cmd_val : std_logic;
signal out_cmd : std_logic_vector(63 downto 0);
signal host_data_in : std_logic_vector(63 downto 0);
signal host_data_out : std_logic_vector(63 downto 0);
signal host_val_in : std_logic;
signal host_val_out : std_logic;
signal host_stop_out : std_logic;
signal host_stop_in : std_logic;
signal lvds_in_n : std_logic_vector(1 downto 0);
signal lvds_in_p : std_logic_vector(1 downto 0);
signal lvds_out_n : std_logic_vector(1 downto 0);
signal lvds_out_p : std_logic_vector(1 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_25_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
clk200 <= not clk200 after CLK_200_MHZ / 2;
clk100 <= not clk100 after CLK_100_MHZ / 2;
rst <= '0' after CLK_125_MHZ * 10;
rstn <= '1' after CLK_125_MHZ * 10;
rst_rstin <= (0=>rst, 1 => rst, 2=> rst, others =>'0');
clk_clkin <= (13 => clk200, 14 => clk100, others=>clk);
-----------------------------------------------------------------------------------
-- Host Interface
-----------------------------------------------------------------------------------
inst0_generic_host: entity work.generic_host_emu
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"00000FF",
private_start_addr_gen => x"0000000",
private_stop_addr_gen => x"00000FF"
)
port map (
cmdclk_out_cmdclk => clk_cmd, -- out std_logic;
cmd_in_cmdin => out_cmd , -- in std_logic_vector(63 downto 0);
cmd_in_cmdin_val => out_cmd_val, -- in std_logic;
cmd_out_cmdout => in_cmd, -- out std_logic_vector(63 downto 0);
cmd_out_cmdout_val => in_cmd_val, -- out std_logic;
ifpga_rst_out_ifpga_rst => open, -- out std_logic;
clk_clkin => (others=>'0'),-- in std_logic_vector(31 downto 0);
rst_rstin => (others=>'0'),-- in std_logic_vector(31 downto 0);
sys_clk => clk, -- in std_logic;
sys_reset_n => rstn, -- in std_logic;
in_data_in_stop => host_stop_in, -- out std_logic;
in_data_in_dval => host_val_in, -- in std_logic;
in_data_in_data => host_data_in, -- in std_logic_vector(63 downto 0);
out_data_out_stop => host_stop_out,-- in std_logic;
out_data_out_dval => host_val_out, -- out std_logic;
out_data_out_data => host_data_out -- out std_logic_vector(63 downto 0)
);
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => clk200, -- 1-bit input: Reference clock input
RST => '0' -- 1-bit input: Active high reset input
);
-----------------------------------------------------------------------------------
-- Unit under test
-----------------------------------------------------------------------------------
sip_toggle_4lvds_inst0:
entity work.sip_toggle_4lvds
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"0001FFF",
private_start_addr_gen => x"0000100",
private_stop_addr_gen => x"00001FF"
)
port map (
clk_clkin => clk_clkin,
rst_rstin => rst_rstin,
cmdclk_in_cmdclk => clk_cmd,
cmd_in_cmdin => in_cmd,
cmd_in_cmdin_val => in_cmd_val,
cmd_out_cmdout => out_cmd,
cmd_out_cmdout_val => out_cmd_val,
lvds_in_n => lvds_in_n,
lvds_in_p => lvds_in_p,
lvds_out_n => lvds_out_n,
lvds_out_p => lvds_out_p
);
lvds_in_n(0) <= sysclk_n;
lvds_in_p(0) <= sysclk_p;
lvds_in_n(1) <= sysclk_n;
lvds_in_p(1) <= sysclk_p;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | 3d39f5aaa7d67eac560079adc630a45b | 0.425952 | 3.952809 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue328/t5.vhdl | 1 | 426 | entity t5 is
end t5;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of t5 is
signal s : std_logic := '0';
begin
b: block
port (p : out std_logic := 'Z');
port map (p => s);
begin
end block;
b2: block
port (p : out std_logic := '1');
port map (p => s);
begin
end block;
process
begin
wait for 1 ns;
assert s = 'X' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 47437eefeff1fc749727f816527f9b64 | 0.586854 | 3 | false | false | false | false |
tgingold/ghdl | testsuite/synth/cnt01/cnt01.vhdl | 1 | 787 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cnt01 is
port (
clock : in STD_LOGIC;
reset : in STD_LOGIC;
clear_count : in STD_LOGIC;
enable : in STD_LOGIC;
counter_out : out STD_LOGIC_VECTOR (9 downto 0)
);
end cnt01;
architecture behav of cnt01 is
signal s_count : unsigned(9 downto 0); -- := (others => '0');
begin
process(clock, reset)
begin
if reset = '1' then
s_count <= (others => '0');
elsif rising_edge(clock) then
if clear_count = '1' then
s_count <= (others => '0');
elsif enable = '1' then
s_count <= s_count + 1;
end if;
end if;
end process;
-- connect internal signal to output
counter_out <= std_logic_vector(s_count);
end behav;
| gpl-2.0 | 1444f844477462421066fe7715450807 | 0.587039 | 3.279167 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc66.vhd | 4 | 2,750 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc66.vhd,v 1.2 2001-10-26 16:29:58 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p07n01i00066ent IS
END c04s03b01x02p07n01i00066ent;
ARCHITECTURE c04s03b01x02p07n01i00066arch OF c04s03b01x02p07n01i00066ent IS
signal C1 : Boolean := true; -- No_failure_here
signal C2 : bit := '0'; -- No_failure_here
signal C3 : integer := 123; -- No_failure_here
signal C4 : positive := 34; -- No_failure_here
signal C5 : natural := 12; -- No_failure_here
signal C6 : real := 1.20; -- No_failure_here
signal C7 : character := 'C'; -- No_failure_here
signal C8 : time := 0 ns; -- No_failure_here
signal INDEX : INTEGER range 0 to 99 := 0; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( C1 = true and
C2 = '0' and
C3 = 123 and
C4 = 34 and
C5 = 12 and
C6 = 1.20 and
C7 = 'C' and
C8 = 0 ns and
INDEX = 0 )
report "***PASSED TEST: c04s03b01x02p07n01i00066"
severity NOTE;
assert ( C1 = true and
C2 = '0' and
C3 = 123 and
C4 = 34 and
C5 = 12 and
C6 = 1.20 and
C7 = 'C' and
C8 = 0 ns and
INDEX = 0 )
report "***FAILED TEST: c04s03b01x02p07n01i00066 - Signal expression must be as the same type as the signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x02p07n01i00066arch;
| gpl-2.0 | 03291abccd495d7b480878769f4c9a85 | 0.557818 | 3.632761 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc299.vhd | 4 | 1,835 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc299.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n03i00299ent IS
END c03s01b03x01p01n03i00299ent;
ARCHITECTURE c03s01b03x01p01n03i00299arch OF c03s01b03x01p01n03i00299ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (sec = 1000 ms) and
(min = 60 sec) and
(hr = 60 min))
report "***PASSED TEST:c03s01b03x01p01n03i00299"
severity NOTE;
assert ( (sec = 1000 ms) and
(min = 60 sec) and
(hr = 60 min))
report "***FAILED TEST: c03s01b03x01p01n03i00299 - Type TIME is defined with an ascending ragne."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n03i00299arch;
| gpl-2.0 | f68f125c43a5b31916d889d4b11a2d64 | 0.641962 | 3.72211 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd | 4 | 1,793 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07a is
end entity inline_07a;
----------------------------------------------------------------
architecture test of inline_07a is
begin
process is
-- code from book:
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : real_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list : value_ptr;
-- end of code from book
begin
-- code from book:
if value_list /= null then
-- . . . -- do something with the list
-- not in book
report "value_list /= null";
-- end not in book
end if;
value_list := new value_cell'( real_vector'(0.0, 5.0, 0.0, 42.0), value_list );
value_list := new value_cell'( real_vector'(3.3, 2.2, 0.27, 1.9), value_list );
value_list := new value_cell'( real_vector'(2.9, 0.1, 21.12, 8.3), value_list );
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 | 0e4c4f85ffcc140f603c73da8aa3dcbf | 0.635806 | 3.831197 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_08.vhd | 4 | 3,196 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_08.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
package bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
function "-" ( bv : bit_vector ) return bit_vector;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
-- . . .
end package bit_vector_signed_arithmetic;
-- not in book
library bv_utilities;
use bv_utilities.bv_arithmetic;
-- end not in book
package body bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bv_arithmetic."+"(bv1, bv2);
end function "+";
-- end not in book
function "-" ( bv : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bv_arithmetic."-"(bv);
end function "-";
-- end not in book
function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
-- . . .
begin
-- not in book
-- . . .
return bv_arithmetic.bv_multu(bv1, bv2);
-- end not in book
end function mult_unsigned;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
begin
if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
return mult_unsigned(bv1, bv2);
elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
return -mult_unsigned(bv1, -bv2);
elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
return -mult_unsigned(-bv1, bv2);
else
return mult_unsigned(-bv1, -bv2);
end if;
end function "*";
-- . . .
end package body bit_vector_signed_arithmetic;
-- not in book
entity fg_08_08 is
end entity fg_08_08;
library bv_utilities;
use bv_utilities.bit_vector_signed_arithmetic.all;
use std.textio.all;
architecture test of fg_08_08 is
begin
stimulus : process is
variable L : line;
begin
write(L, X"0002" + X"0005");
writeline(output, L);
write(L, X"0002" + X"FFFE");
writeline(output, L);
write(L, - X"0005");
writeline(output, L);
write(L, - X"FFFE");
writeline(output, L);
write(L, X"0002" * X"0005");
writeline(output, L);
write(L, X"0002" * X"FFFD");
writeline(output, L);
wait;
end process stimulus;
end architecture test;
-- end not in book
| gpl-2.0 | cff2b1460d65ba7eff046f8e52894323 | 0.613267 | 3.429185 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_11.vhd | 4 | 3,702 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_11 is
end entity fg_18_11;
architecture test of fg_18_11 is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (natural range <>) of byte;
function resolve_bytes ( drivers : in byte_array ) return byte is
begin
return drivers(drivers'left);
end function resolve_bytes;
function resolve_bits ( drivers : in bit_vector ) return bit is
begin
return drivers(drivers'left);
end function resolve_bits;
-- code from book (in text)
signal address : bit_vector(15 downto 0);
signal data : resolve_bytes byte;
signal rd, wr, io : bit; -- read, write, io/mem select
signal ready : resolve_bits bit;
-- end code from book
begin
-- code from book
bus_monitor : process is
constant header : string(1 to 44)
:= FF & " Time R/W I/M Address Data";
use std.textio.all;
file log : text open write_mode is "buslog";
variable trace_line : line;
variable line_count : natural := 0;
begin
if line_count mod 60 = 0 then
write ( trace_line, header );
writeline ( log, trace_line );
writeline ( log, trace_line ); -- empty line
end if;
wait until (rd = '1' or wr = '1') and ready = '1';
write ( trace_line, now, justified => right, field => 10, unit => us );
write ( trace_line, string'(" ") );
if rd = '1' then
write ( trace_line, 'R' );
else
write ( trace_line, 'W' );
end if;
write ( trace_line, string'(" ") );
if io = '1' then
write ( trace_line, 'I' );
else
write ( trace_line, 'M' );
end if;
write ( trace_line, string'(" ") );
write ( trace_line, address );
write ( trace_line, ' ');
write ( trace_line, data );
writeline ( log, trace_line );
line_count := line_count + 1;
end process bus_monitor;
-- end code from book
stimulus : process is
begin
wait for 0.4 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0000";
data <= B"10011110";
ready <= '1', '0' after 10 ns;
wait for 0.9 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0001";
data <= B"00010010";
ready <= '1', '0' after 10 ns;
wait for 2.0 us - now;
rd <= '1', '0' after 10 ns;
address <= X"0014";
data <= B"11100111";
ready <= '1', '0' after 10 ns;
wait for 2.7 us - now;
wr <= '1', '0' after 10 ns;
io <= '1', '0' after 10 ns;
address <= X"0007";
data <= X"00";
ready <= '1', '0' after 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 75d4443a801e4cb73a24e0333db53314 | 0.563479 | 3.694611 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/sim/vhdl/AESL_axi_slave_CTRL_BUS.vhd | 1 | 27,396 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity AESL_axi_slave_CTRL_BUS is
generic (
constant ADDR_WIDTH : INTEGER := 4;
constant DATA_WIDTH : INTEGER := 32;
constant CTRL_BUS_DEPTH : INTEGER := 1;
constant CTRL_BUS_c_bitwidth : INTEGER := 1;
constant START_ADDR : INTEGER := 0;
constant doHist_continue_addr : INTEGER := 0;
constant doHist_auto_start_addr : INTEGER := 0;
constant STATUS_ADDR : INTEGER := 0;
constant INTERFACE_TYPE : STRING (1 to 8) := "CTRL_BUS"
);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_AWADDR : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
TRAN_s_axi_CTRL_BUS_AWVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_AWREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WDATA : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
TRAN_s_axi_CTRL_BUS_WSTRB : OUT STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0);
TRAN_s_axi_CTRL_BUS_ARADDR : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
TRAN_s_axi_CTRL_BUS_ARVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_ARREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RVALID : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RREADY : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RDATA : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
TRAN_s_axi_CTRL_BUS_RRESP : IN STD_LOGIC_VECTOR(2 - 1 downto 0);
TRAN_s_axi_CTRL_BUS_BVALID : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_BREADY : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_BRESP : IN STD_LOGIC_VECTOR(2 - 1 downto 0);
TRAN_CTRL_BUS_interrupt : IN STD_LOGIC;
TRAN_CTRL_BUS_start_in : IN STD_LOGIC;
TRAN_CTRL_BUS_done_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_ready_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_ready_in : IN STD_LOGIC;
TRAN_CTRL_BUS_idle_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_write_start_in : IN STD_LOGIC;
TRAN_CTRL_BUS_write_start_finish : OUT STD_LOGIC;
TRAN_CTRL_BUS_transaction_done_in : IN STD_LOGIC
);
end AESL_axi_slave_CTRL_BUS;
architecture behav of AESL_axi_slave_CTRL_BUS is
------------------------Local signal-------------------
shared variable CTRL_BUS_OPERATE_DEPTH : INTEGER;
signal AWADDR_reg : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_0_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_1_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal AWVALID_reg : STD_LOGIC := '0';
signal process_0_AWVALID_var : STD_LOGIC := '0';
signal process_1_AWVALID_var : STD_LOGIC := '0';
signal WVALID_reg : STD_LOGIC := '0';
signal process_0_WVALID_var : STD_LOGIC := '0';
signal process_1_WVALID_var : STD_LOGIC := '0';
signal WDATA_reg : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_0_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_1_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal WSTRB_reg : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_0_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_1_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal ARADDR_reg : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_0_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_1_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal ARVALID_reg : STD_LOGIC := '0';
signal process_0_ARVALID_var : STD_LOGIC := '0';
signal process_1_ARVALID_var : STD_LOGIC := '0';
signal RREADY_reg : STD_LOGIC := '0';
signal process_0_RREADY_var : STD_LOGIC := '0';
signal process_1_RREADY_var : STD_LOGIC := '0';
signal RDATA_reg : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_0_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_1_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal BREADY_reg : STD_LOGIC := '0';
signal process_0_BREADY_var : STD_LOGIC := '0';
signal process_1_BREADY_var : STD_LOGIC := '0';
type mem_CTRL_BUS_arr2D is array(0 to CTRL_BUS_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_CTRL_BUS : mem_CTRL_BUS_arr2D;
signal AESL_ready_out_index_reg : STD_LOGIC := '0';
signal AESL_write_start_finish : STD_LOGIC := '0';
signal AESL_ready_reg : STD_LOGIC;
signal ready_initial : STD_LOGIC;
signal AESL_done_index_reg : STD_LOGIC := '0';
signal AESL_idle_index_reg : STD_LOGIC := '0';
signal AESL_auto_restart_index_reg : STD_LOGIC;
signal process_0_finish : STD_LOGIC := '0';
signal process_1_finish : STD_LOGIC := '0';
shared variable write_start_count : INTEGER;
signal write_start_run_flag : STD_LOGIC := '0';
--===================process control=================
signal ongoing_process_number : INTEGER;
-- Process number depends on how much processes needed.
shared variable process_busy : STD_LOGIC := '0';
function esl_icmp_eq(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if v1 = v2 then
res := "1";
else
res := "0";
end if;
return res;
end function;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_icmp_ult(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if unsigned(v1) < unsigned(v2) then
res := "1";
else
res := "0";
end if;
return res;
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
procedure count_c_data_four_byte_num_by_bitwidth (constant bitwidth : IN INTEGER; variable num : OUT INTEGER) is
variable factor : INTEGER;
variable i : INTEGER;
begin
factor := 32;
for i in 1 to 32 loop
if (bitwidth <= factor and bitwidth > factor - 32) then
num := i;
end if;
factor := factor + 32;
end loop;
end procedure;
procedure count_seperate_factor_by_bitwidth(bitwidth : in INTEGER; factor : out INTEGER) is
begin
if (bitwidth <= 8) then
factor := 4;
elsif (bitwidth <= 16 and bitwidth > 8 ) then
factor := 2;
elsif (bitwidth <= 32 and bitwidth > 16 ) then
factor := 1;
elsif (bitwidth <= 1024 and bitwidth > 32 ) then
factor := 1;
end if;
end procedure;
procedure count_operate_depth_by_bitwidth_and_depth(bitwidth : in INTEGER; depth : in INTEGER; operate_depth : out INTEGER) is
variable factor : INTEGER;
variable remain : INTEGER;
variable operate_depth_tmp : INTEGER;
begin
count_seperate_factor_by_bitwidth (bitwidth , factor);
operate_depth_tmp := depth / factor;
remain := depth mod factor;
if (remain > 0) then
operate_depth_tmp := operate_depth_tmp + 1;
end if;
operate_depth := operate_depth_tmp;
end procedure;
begin
--=================== signal connection ==============
TRAN_s_axi_CTRL_BUS_AWADDR <= AWADDR_reg;
TRAN_s_axi_CTRL_BUS_AWVALID <= AWVALID_reg;
TRAN_s_axi_CTRL_BUS_WVALID <= WVALID_reg;
TRAN_s_axi_CTRL_BUS_WDATA <= WDATA_reg;
TRAN_s_axi_CTRL_BUS_WSTRB <= WSTRB_reg;
TRAN_s_axi_CTRL_BUS_ARADDR <= ARADDR_reg;
TRAN_s_axi_CTRL_BUS_ARVALID <= ARVALID_reg;
TRAN_s_axi_CTRL_BUS_RREADY <= RREADY_reg;
TRAN_s_axi_CTRL_BUS_BREADY <= BREADY_reg;
TRAN_CTRL_BUS_done_out <= AESL_done_index_reg;
TRAN_CTRL_BUS_ready_out <= AESL_ready_out_index_reg;
TRAN_CTRL_BUS_write_start_finish <= AESL_write_start_finish;
TRAN_CTRL_BUS_idle_out <= AESL_idle_index_reg;
AESL_ready_reg_proc : process(TRAN_CTRL_BUS_ready_in, ready_initial)
begin
AESL_ready_reg <= TRAN_CTRL_BUS_ready_in or ready_initial;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until reset = '1';
wait until clk'event and clk = '1';
ready_initial <= '1';
wait until clk'event and clk = '1';
ready_initial <= '0';
wait;
end process;
ongoing_process_number_gen : process(reset , process_0_finish , process_1_finish )
begin
if (reset = '0') then
ongoing_process_number <= 0;
elsif (ongoing_process_number = 0 and process_0_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 1 and process_1_finish = '1') then
ongoing_process_number <= 0;
end if;
end process;
output_reg_write_value_function : process
begin
wait until reset = '1';
wait until clk'event and clk = '1';
while (true) loop
if (ongoing_process_number = 0 ) then
AWADDR_reg <= process_0_AWADDR_var;
AWVALID_reg <= process_0_AWVALID_var;
WVALID_reg <= process_0_WVALID_var;
WDATA_reg <= process_0_WDATA_var;
WSTRB_reg <= process_0_WSTRB_var;
ARADDR_reg <= process_0_ARADDR_var;
ARVALID_reg <= process_0_ARVALID_var;
RREADY_reg <= process_0_RREADY_var;
BREADY_reg <= process_0_BREADY_var;
elsif (ongoing_process_number = 1 ) then
AWADDR_reg <= process_1_AWADDR_var;
AWVALID_reg <= process_1_AWVALID_var;
WVALID_reg <= process_1_WVALID_var;
WDATA_reg <= process_1_WDATA_var;
WSTRB_reg <= process_1_WSTRB_var;
ARADDR_reg <= process_1_ARADDR_var;
ARVALID_reg <= process_1_ARVALID_var;
RREADY_reg <= process_1_RREADY_var;
BREADY_reg <= process_1_BREADY_var;
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
update_status_proc : process
variable process_num : INTEGER;
variable read_status_resp : INTEGER;
variable process_0_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
begin
wait until reset = '1';
wait until clk'event and clk = '1';
process_num := 0;
while (true) loop
process_0_finish <= '0';
AESL_done_index_reg <= '0';
AESL_ready_out_index_reg <= '0';
if (ongoing_process_number = process_num and process_busy = '0') then
process_busy := '1';
--=======================one single read operate======================
read_status_resp := 0;
process_0_ARADDR_var <= STD_LOGIC_VECTOR(to_unsigned(STATUS_ADDR, ADDR_WIDTH));
process_0_ARVALID_var <= '1';
while (TRAN_s_axi_CTRL_BUS_ARREADY /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_0_ARVALID_var <= '0';
process_0_RREADY_var <= '1';
while (TRAN_s_axi_CTRL_BUS_RVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_0_RDATA_tmp := TRAN_s_axi_CTRL_BUS_RDATA;
process_0_RREADY_var <= '0';
if (TRAN_s_axi_CTRL_BUS_RRESP = (2 => '0') ) then
read_status_resp := 1;
--output success. in fact RRESP is always 2'b00
end if;
wait until clk'event and clk = '1';
--=======================one single read operate end======================
AESL_done_index_reg <= process_0_RDATA_tmp(1);
AESL_ready_out_index_reg <= process_0_RDATA_tmp(1);
AESL_idle_index_reg <= process_0_RDATA_tmp(2);
process_busy := '0';
process_0_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_start_run_flag : process (reset , clk)
begin
if (reset = '0') then
write_start_run_flag <= '0';
write_start_count := 0;
elsif (clk'event and clk = '1') then
if (write_start_count >= 1) then
write_start_run_flag <= '0';
elsif (TRAN_CTRL_BUS_write_start_in = '1') then
write_start_run_flag <= '1';
end if;
if (AESL_write_start_finish = '1') then
write_start_count := write_start_count + 1;
write_start_run_flag <= '0';
end if;
end if;
end process;
write_start_proc : process
variable process_num : INTEGER;
variable write_start_resp : INTEGER;
variable write_start_tmp : STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0) ;
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
variable i : INTEGER;
begin
wait until reset = '1';
wait until clk'event and clk = '1';
process_num := 1;
while (true) loop
process_1_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
if (write_start_run_flag = '1') then
process_busy := '1';
write_start_tmp := (others => '0');
write_start_tmp(0) := '1';
--=======================one single write operate======================
write_start_resp := 0;
aw_flag := '0';
w_flag := '0';
process_1_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(START_ADDR, ADDR_WIDTH));
process_1_AWVALID_var <= '1';
process_1_WDATA_var <= write_start_tmp;
process_1_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_1_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_CTRL_BUS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_CTRL_BUS_WREADY and WVALID_reg;
end if;
process_1_AWVALID_var <= not aw_flag;
process_1_WVALID_var <= not w_flag;
end loop;
process_1_BREADY_var <= '1';
while (TRAN_s_axi_CTRL_BUS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_1_BREADY_var <= '0';
if (TRAN_s_axi_CTRL_BUS_BRESP = (2 => '0')) then
write_start_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
process_busy := '0';
AESL_write_start_finish <= '1';
wait until clk'event and clk = '1';
AESL_write_start_finish <= '0';
end if;
process_1_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
end behav;
| gpl-3.0 | 71ac77595e2d0a8135d493d18b0e2e9c | 0.47945 | 3.660609 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth109/tb_ram2.vhdl | 1 | 2,066 | entity tb_ram2 is
end tb_ram2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram2 is
signal clkA : std_logic;
signal enA : std_logic;
signal weA : std_logic;
signal addrA : std_logic_vector(5 downto 0);
signal rdatA : std_logic_vector(31 downto 0);
signal wdatA : std_logic_vector(31 downto 0);
signal clkB : std_logic;
signal enB : std_logic;
signal weB : std_logic;
signal addrB : std_logic_vector(5 downto 0);
signal rdatB : std_logic_vector(31 downto 0);
signal wdatB : std_logic_vector(31 downto 0);
begin
dut: entity work.ram2
port map (clkA => clkA, clkB => clkB,
enA => enA, enB => enB,
weA => weA, weB => weB,
addrA => addrA, addrB => addrB,
diA => wdatA, diB => wdatB,
doA => rdatA, doB => rdatB);
process
procedure pulseB is
begin
clkB <= '0';
wait for 1 ns;
clkB <= '1';
wait for 1 ns;
end pulseB;
procedure pulseA is
begin
clkA <= '0';
wait for 1 ns;
clkA <= '1';
wait for 1 ns;
end pulseA;
begin
clkA <= '0';
enA <= '0';
enB <= '1';
weB <= '1';
addrB <= b"00_0000";
wdatB <= x"11_22_33_f0";
pulseB;
assert rdatB = x"11_22_33_f0" severity failure;
addrB <= b"00_0001";
wdatB <= x"11_22_33_f1";
pulseB;
assert rdatB = x"11_22_33_f1" severity failure;
-- Read.
weB <= '0';
addrB <= b"00_0000";
wdatB <= x"ff_22_33_f1";
pulseB;
assert rdatB = x"11_22_33_f0" severity failure;
addrB <= b"00_0001";
wdatB <= x"ff_22_33_f1";
pulseB;
assert rdatB = x"11_22_33_f1" severity failure;
-- Disable.
enB <= '0';
weB <= '1';
addrB <= b"00_0000";
wdatB <= x"11_22_33_f0";
pulseB;
assert rdatB = x"11_22_33_f1" severity failure;
-- Read from A.
enA <= '1';
weA <= '0';
addrA <= b"00_0001";
wdatA <= x"88_22_33_f1";
pulseA;
assert rdatA = x"11_22_33_f1" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 158512bb57f4bcb756b3191494385185 | 0.54453 | 3.097451 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd | 4 | 3,450 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity phase_locked_clock_gen is
port ( ref_clock : in std_ulogic;
phi1, phi2 : out std_ulogic );
end entity phase_locked_clock_gen;
architecture std_cell of phase_locked_clock_gen is
use work.clock_power_pkg.Tpw;
begin
phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(ref_clock);
phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(ref_clock);
end architecture std_cell;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity regulator is
port ( terminal plus_in, minus_in, plus_out, minus_out : electrical );
end entity regulator;
architecture device_level of regulator is
begin
end architecture device_level;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
entity io_controller is
port ( signal ref_clock : in std_ulogic;
terminal ext_supply, ext_ground : electrical; -- . . . );
-- not in book
other_port : in std_ulogic );
-- end not in book
end entity io_controller;
--------------------------------------------------
architecture top_level of io_controller is
-- . . .
-- not in book
signal rd, wr, sel, width, burst : std_ulogic;
signal addr : std_ulogic_vector(3 downto 0);
signal ready : std_ulogic;
signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
other_signal : std_ulogic;
signal analog_out_wr_0 : std_ulogic;
signal internal_data : std_ulogic_vector(7 downto 0);
terminal analog_out_0 : electrical;
-- end not in book
begin
internal_clock_gen : entity work.phase_locked_clock_gen(std_cell)
port map ( ref_clock => ref_clock,
phi1 => work.clock_power_pkg.clock_phase1,
phi2 => work.clock_power_pkg.clock_phase2 );
internal_analog_regulator : entity work.regulator(device_level)
port map ( plus_in => ext_supply, minus_in => ext_ground,
plus_out => work.clock_power_pkg.analog_plus_supply,
minus_out => work.clock_power_pkg.analog_ground );
the_bus_sequencer : entity work.bus_sequencer(fsm)
port map ( rd, wr, sel, width, burst, addr(3 downto 0), ready,
control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
analog_out_wr_0, -- . . . );
-- not in book
other_signal );
-- not in book
analog_output_interface_0 : entity work.analog_output_interface(structural)
port map ( analog_out_wr_0, internal_data(7 downto 0), analog_out_0 );
-- . . .
end architecture top_level;
| gpl-2.0 | 680a0b650d6f6017aefb344b289dd722 | 0.661159 | 3.586279 | false | false | false | false |
tgingold/ghdl | testsuite/synth/psl01/hello.vhdl | 1 | 615 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hello is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end hello;
architecture behav of hello is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
--psl default clock is rising_edge(clk);
--psl restrict {rst; (not rst)[*]};
--psl assert always val /= 5 abort rst;
--psl assume always val < 10;
--psl cover {val = 10};
end behav;
| gpl-2.0 | b376b8f449943d84149ff0c4a5dcdcb0 | 0.61626 | 3.203125 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket32/arith_prefix_and_tb.vhdl | 3 | 2,732 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Testbench for arith_prefix_and.
--
-- Authors: Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- Automated testbench for PoC.arith_prng
-- The Pseudo-Random Number Generator is instanziated for 8 bits. The
-- output sequence is compared to 256 precalculated values.
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity arith_prefix_and_tb is
end arith_prefix_and_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.simulation.ALL;
architecture tb of arith_prefix_and_tb is
-- component arith_prefix_and
-- generic (
-- N : positive
-- );
-- port (
-- x : in std_logic_vector(N-1 downto 0);
-- y : out std_logic_vector(N-1 downto 0)
-- );
-- end component;
-- component generics
constant N : positive := 8;
-- component ports
signal x : std_logic_vector(N-1 downto 0);
signal y : std_logic_vector(N-1 downto 0);
begin -- tb
-- component instantiation
DUT : entity PoC.arith_prefix_and
generic map (
N => N
)
port map (
x => x,
y => y
);
-- Stimuli
process
begin
-- Exhaustive Testing
for i in 0 to 2**N-1 loop
x <= std_logic_vector(to_unsigned(i, N));
wait for 10 ns;
for j in 0 to N-1 loop
tbAssert((y(j) = '1') = (x(j downto 0) = (j downto 0 => '1')),
"Wrong result for "&integer'image(i)&" / "&integer'image(j));
end loop;
end loop;
-- Report overall result
tbPrintResult;
wait; -- forever
end process;
end tb;
| gpl-2.0 | 49da0d62f4cf8bc518c23ff2e9bff62d | 0.561127 | 3.672043 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/w_split0.vhd | 2 | 1,359 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split0 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split0;
architecture augh of w_split0 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 25ee116cdb3f0993a0d97356a762f040 | 0.66961 | 2.843096 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff03/tb_dff03.vhdl | 1 | 1,062 | entity tb_dff03 is
end tb_dff03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff03 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff03
port map (
q => dout,
d => din,
en1 => en1,
en2 => en2,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en1 <= '1';
en2 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
en1 <= '0';
din <= '0';
pulse;
assert dout = '1' severity failure;
en1 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
en2 <= '0';
din <= '1';
pulse;
assert dout = '0' severity failure;
en2 <= '1';
din <= '1';
pulse;
assert dout = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 5199bccfa222856bf83cae5529f5548e | 0.521657 | 3.208459 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue126/seg_fault.vhdl | 2 | 741 | package pa is
type t is range 0 to 3;
end package;
use work.pa.t;
package pb is
function f (a,b:t) return t ;
function "="(a,b:t) return boolean;
end package;
use work.pa."+";
-- This side note is not part of the bug report: with vhdl pre-2008 this use clause should be required (I think) and it is not
-- use work.pa."=";
package body pb is
function f (a,b:t) return t is begin return a+b; end function;
function "="(a,b:t) return boolean is begin return a=b; end function;
end package body;
use work.pa.all; -- fails with and without this use clause
use work.pb.f;
use work.pb."="; -- this causes the problem
entity e is begin
assert f(1,2)=0 severity note;
end entity;
architecture a of e is begin end architecture;
| gpl-2.0 | 4cf2093abdc6b35a69ec17e6363ed9c8 | 0.693657 | 3.235808 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/sub_221.vhd | 2 | 1,730 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_221;
architecture augh of sub_221 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
end architecture;
| gpl-2.0 | 29759f5baf813903304fef2fec489bbe | 0.624277 | 2.578241 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd | 4 | 2,581 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tb_moving_mass is
end tb_moving_mass;
architecture TB_moving_mass of tb_moving_mass is
-- Component declarations
-- Signal declarations
terminal msd_discrete, msd_mdl : translational;
begin
-- Signal assignments
-- Component instances
mass1 : entity work.mass_t(ideal)
generic map(
m => 10.0
)
port map(
trans1 => msd_discrete
);
spring2 : entity work.spring_t(linear)
generic map(
k => 2.0
)
port map(
trans1 => msd_discrete,
trans2 => TRANSLATIONAL_REF
);
damper1 : entity work.damper_t(ideal)
generic map(
d => 5.0
)
port map(
trans1 => msd_discrete,
trans2 => TRANSLATIONAL_REF
);
Force1 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => msd_discrete,
trans_neg => TRANSLATIONAL_REF
);
Force2 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => msd_mdl,
trans_neg => TRANSLATIONAL_REF
);
moving_mass4 : entity work.moving_mass_wa(behavioral)
port map(
external_attachment => msd_mdl
);
end TB_moving_mass;
| gpl-2.0 | f25b49dc8d999beb014aa5aab10373b5 | 0.567609 | 4.096825 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1110.vhd | 4 | 2,055 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1110.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01110ent IS
END c06s05b00x00p03n01i01110ent;
ARCHITECTURE c06s05b00x00p03n01i01110arch OF c06s05b00x00p03n01i01110ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V3 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (2 to 4);
-- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01110 - Prefix of a slice name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01110arch;
| gpl-2.0 | eb165e5fc42614843bbe598efad9fc3b | 0.659854 | 3.663102 | false | true | false | false |
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