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tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc852.vhd | 4 | 10,433 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc852.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00852pkg_2 is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00852pkg_2;
package body c01s03b01x00p12n01i00852pkg_2 is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00852pkg_2;
use work.c01s03b01x00p12n01i00852pkg_2.all;
package c01s03b01x00p12n01i00852pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal dumy : bit_vector(zero to three);
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00852pkg;
use work.c01s03b01x00p12n01i00852pkg.all;
use work.c01s03b01x00p12n01i00852pkg_2.all;
entity c01s03b01x00p12n01i00852ent_a is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture c01s03b01x00p12n01i00852ent_a of c01s03b01x00p12n01i00852ent_a is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration c01s03b01x00p12n01i00852ent_abench of c01s03b01x00p12n01i00852ent_a is
for c01s03b01x00p12n01i00852ent_a
end for;
end;
use work.c01s03b01x00p12n01i00852pkg.all;
use work.c01s03b01x00p12n01i00852pkg_2.all;
ENTITY c01s03b01x00p12n01i00852ent IS
END c01s03b01x00p12n01i00852ent;
ARCHITECTURE c01s03b01x00p12n01i00852arch OF c01s03b01x00p12n01i00852ent IS
component c01s03b01x00p12n01i00852ent_a
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component c01s03b01x00p12n01i00852ent_a
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : c01s03b01x00p12n01i00852ent_a
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:c01s03b01x00p12n01i00852ent_a
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00852"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00852 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00852arch;
configuration c01s03b01x00p12n01i00852cfg of c01s03b01x00p12n01i00852ent is
for c01s03b01x00p12n01i00852arch
for K
for T5:c01s03b01x00p12n01i00852ent_a use configuration work.c01s03b01x00p12n01i00852ent_abench;
end for;
for G(dumy'range)
for T1:c01s03b01x00p12n01i00852ent_a
use configuration work.c01s03b01x00p12n01i00852ent_abench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 | 1c22801debbf9c73b5c24b3e219ff2d6 | 0.611617 | 3.228032 | false | false | false | false |
tgingold/ghdl | testsuite/gna/sr2737/bit_vector_rol_ror.vhdl | 3 | 4,086 | entity bit_vector_rol_ror is
end entity;
architecture ghdl_bug of bit_vector_rol_ror is
function TO_STRING (VALUE : BIT_VECTOR) return STRING is
alias ivalue : BIT_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return "";
else
for i in ivalue'range loop
if iValue(i) = '0' then
result(i) := '0';
else
result(i) := '1';
end if;
end loop;
return result;
end if;
end function to_string;
begin
assert bit_vector'("11100") ror -8 = "00111" report "ror -8 is broken" severity warning;
assert bit_vector'("11100") ror -7 = "10011" report "ror -7 is broken" severity warning;
assert bit_vector'("11100") ror -6 = "11001" report "ror -6 is broken" severity warning;
assert bit_vector'("11100") ror -5 = "11100" report "ror -5 is broken" severity warning;
assert bit_vector'("11100") ror -4 = "01110" report "ror -4 is broken" severity warning;
assert bit_vector'("11100") ror -3 = "00111" report "ror -3 is broken" severity warning;
assert bit_vector'("11100") ror -2 = "10011" report "ror -2 is broken" severity warning;
assert bit_vector'("11100") ror -1 = "11001" report "ror -1 is broken" severity warning;
assert bit_vector'("11100") ror 0 = "11100" report "ror 0 is broken" severity warning;
assert bit_vector'("11100") ror 1 = "01110" report "ror 1 is broken" severity warning;
assert bit_vector'("11100") ror 2 = "00111" report "ror 2 is broken" severity warning;
assert bit_vector'("11100") ror 3 = "10011" report "ror 3 is broken" severity warning;
assert bit_vector'("11100") ror 4 = "11001" report "ror 4 is broken" severity warning;
assert bit_vector'("11100" ror 5) = "11100" report "ror 5 is broken" severity warning;
assert bit_vector'("11100") ror 5 = "11100" report string'("ror 5 is broken " & TO_STRING(bit_vector'("11100"))&" produces "& TO_STRING(bit_vector'("11100") ror 5) &"!") severity warning;
assert bit_vector'("11100") ror 6 = "01110" report "ror 6 is broken" severity warning;
assert bit_vector'("11100") ror 7 = "00111" report "ror 7 is broken" severity warning;
assert bit_vector'("11100") ror 8 = "10011" report "ror 8 is broken" severity warning;
assert bit_vector'("11100") rol -8 = "10011" report "rol -8 is broken" severity warning;
assert bit_vector'("11100") rol -7 = "00111" report "rol -7 is broken" severity warning;
assert bit_vector'("11100") rol -6 = "01110" report "rol -6 is broken" severity warning;
assert bit_vector'("11100" rol -5) = "11100" report "rol -5 is broken" severity warning;
assert bit_vector'("11100") rol -5 = "11100" report string'("rol -5 is broken " & TO_STRING(bit_vector'("11100"))&" produces "& TO_STRING(bit_vector'("11100") rol-5) &"!") severity warning;
assert bit_vector'("11100") rol -4 = "11001" report "rol -4 is broken" severity warning;
assert bit_vector'("11100") rol -3 = "10011" report "rol -3 is broken" severity warning;
assert bit_vector'("11100") rol -2 = "00111" report "rol -2 is broken" severity warning;
assert bit_vector'("11100") rol -1 = "01110" report "rol -1 is broken" severity warning;
assert bit_vector'("11100") rol 0 = "11100" report "rol 0 is broken" severity warning;
assert bit_vector'("11100") rol 1 = "11001" report "rol 1 is broken" severity warning;
assert bit_vector'("11100") rol 2 = "10011" report "rol 2 is broken" severity warning;
assert bit_vector'("11100") rol 3 = "00111" report "rol 3 is broken" severity warning;
assert bit_vector'("11100") rol 4 = "01110" report "rol 4 is broken" severity warning;
assert bit_vector'("11100") rol 5 = "11100" report "rol 5 is broken" severity warning;
assert bit_vector'("11100") rol 6 = "11001" report "rol 6 is broken" severity warning;
assert bit_vector'("11100") rol 7 = "10011" report "rol 7 is broken" severity warning;
assert bit_vector'("11100") rol 8 = "00111" report "rol 8 is broken" severity warning;
end architecture; | gpl-2.0 | e0ae04e31f9aa5e80929ee003512006c | 0.661038 | 3.424979 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/whout_to_axistream.vhd | 1 | 5,469 |
-------------------------------------------------------------------------------------
-- FILE NAME :
--
-- AUTHOR : Luis F Munoz
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity -
-- architecture -
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Conversion between a standard StellarIP wormhole output to an AXI-Stream Master. Use
-- with StellarIP Block that has a WH_OUT interface but we really want AXI-Stream Master.
-- For example an ADC.
--
-- AXI-Stream Slave <- AXI-Stream Master to WH_IN (this entity) <- WH_OUT
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity whout_to_axistream is
port (
-- global
clk : in std_logic;
rst : in std_logic;
--Wormhole 'data_in' of type 'wh_in':
data_in_in_stop : out std_logic;
data_in_in_dval : in std_logic;
data_in_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'data_out' of type 'axis_32b_out':
data_out_tdata : out std_logic_vector(63 downto 0);
data_out_tkeep : in std_logic_vector(3 downto 0);
data_out_tlast : out std_logic;
data_out_tready : in std_logic;
data_out_tstrb : in std_logic;
data_out_tuser : out std_logic_vector(31 downto 0);
data_out_tvalid : out std_logic
);
end entity whout_to_axistream;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture behavioural of whout_to_axistream is
--***********************************************************************************
begin
--***********************************************************************************
inst0_fifo:
entity work.axis2wh_fifo
port map (
rst => rst,
wr_clk => clk,
rd_clk => clk,
din => data_in_in_data,
wr_en => data_in_in_dval,
rd_en => data_out_tready,
dout => data_out_tdata,
full => open,
almost_full => data_in_in_stop,
empty => open,
valid => data_out_tvalid
);
--process(clk, rst)
--begin
-- if rising_edge(clk) then
-- data_out_tdata <= data_in_in_data;
-- data_out_tvalid <= data_in_in_dval;
-- data_in_in_stop <= not data_out_tready;
-- end if;
--end process;
data_out_tuser <= (others=>'0');
data_out_tlast <= '1'; -- This indicates that all transfers are individual packets
--**********************************************************************************
end architecture behavioural;
--**********************************************************************************
| mit | 1bfe0012e13ed272c2639a3a87790f2a | 0.422929 | 4.822751 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue881/t87.vhdl | 2 | 323 | entity t87 is
end;
architecture behav of t87 is
constant t1 : time := 1 ns;
constant t2 : natural := time'pos (t1);
begin
assert t1 = 1000 ps;
process
variable v : natural;
begin
-- Time resolution must be ps
v := time'pos(ps);
assert v = 1 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 2b55ac2b029a84b9d1359f2f9ce9197d | 0.634675 | 3.364583 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_14.vhd | 4 | 1,973 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_14.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_07_14 is
end entity fg_07_14;
architecture test of fg_07_14 is
-- code from book
procedure check_setup ( signal data, clock : in bit;
constant Tsu : in time ) is
begin
if clock'event and clock = '1' then
assert data'last_event >= Tsu
report "setup time violation" severity error;
end if;
end procedure check_setup;
-- end code from book
signal ready, phi2 : bit := '0';
constant Tsu_rdy_clk : delay_length := 4 ns;
begin
-- code from book (in text)
check_ready_setup : check_setup ( data => ready, clock => phi2,
Tsu => Tsu_rdy_clk );
-- end code from book
clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
stimulus : ready <= '1' after 4 ns,
'0' after 56 ns,
'1' after 87 ns,
'0' after 130 ns;
end architecture test;
| gpl-2.0 | 9620e808d4a29677252fd6dc78ed7aba | 0.585403 | 3.969819 | false | false | false | false |
tgingold/ghdl | testsuite/synth/memmux01/memmux01.vhdl | 1 | 725 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux01 is
port (
wen : std_logic;
addr : std_logic_vector (3 downto 0);
wdat : std_logic;
rdat : out std_logic_vector (15 downto 0);
clk : std_logic;
rst : std_logic);
end memmux01;
architecture rtl of memmux01 is
begin
process (clk)
is
variable mem : std_logic_vector (15 downto 0);
variable ad : natural range 0 to 15;
begin
if rising_edge(clk) then
rdat <= mem;
if rst = '1' then
mem := (others => '0');
else
ad := to_integer(unsigned(addr));
if wen = '1' then
mem (ad) := wdat;
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 9675e53f93ecf177263b779583909af8 | 0.576552 | 3.325688 | false | false | false | false |
nickg/nvc | test/sem/murax.vhd | 1 | 10,875 | -- Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
-- Component : Murax
-- Git hash : 68e704f3092be640aa92c876cf78702a83167f94
package pkg_enum is
type BranchCtrlEnum is (INC,B,JAL,JALR);
type ShiftCtrlEnum is (DISABLE_1,SLL_1,SRL_1,SRA_1);
type AluBitwiseCtrlEnum is (XOR_1,OR_1,AND_1);
type AluCtrlEnum is (ADD_SUB,SLT_SLTU,BITWISE);
type EnvCtrlEnum is (NONE,XRET);
type Src2CtrlEnum is (RS,IMI,IMS,PC);
type Src1CtrlEnum is (RS,IMU,PC_INCREMENT,URS1);
type JtagState is (RESET,IDLE,IR_SELECT,IR_CAPTURE,IR_SHIFT,IR_EXIT1,IR_PAUSE,IR_EXIT2,IR_UPDATE,DR_SELECT,DR_CAPTURE,DR_SHIFT,DR_EXIT1,DR_PAUSE,DR_EXIT2,DR_UPDATE);
type UartStopType is (ONE,TWO);
type UartParityType is (NONE,EVEN,ODD);
type UartCtrlTxState is (IDLE,START,DATA,PARITY,STOP);
type UartCtrlRxState is (IDLE,START,DATA,PARITY,STOP);
function pkg_mux (sel : bit; one : BranchCtrlEnum; zero : BranchCtrlEnum) return BranchCtrlEnum;
subtype BranchCtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant BranchCtrlEnum_binary_sequential_INC : BranchCtrlEnum_binary_sequential_type := "00";
constant BranchCtrlEnum_binary_sequential_B : BranchCtrlEnum_binary_sequential_type := "01";
constant BranchCtrlEnum_binary_sequential_JAL : BranchCtrlEnum_binary_sequential_type := "10";
constant BranchCtrlEnum_binary_sequential_JALR : BranchCtrlEnum_binary_sequential_type := "11";
function pkg_mux (sel : bit; one : ShiftCtrlEnum; zero : ShiftCtrlEnum) return ShiftCtrlEnum;
subtype ShiftCtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant ShiftCtrlEnum_binary_sequential_DISABLE_1 : ShiftCtrlEnum_binary_sequential_type := "00";
constant ShiftCtrlEnum_binary_sequential_SLL_1 : ShiftCtrlEnum_binary_sequential_type := "01";
constant ShiftCtrlEnum_binary_sequential_SRL_1 : ShiftCtrlEnum_binary_sequential_type := "10";
constant ShiftCtrlEnum_binary_sequential_SRA_1 : ShiftCtrlEnum_binary_sequential_type := "11";
function pkg_mux (sel : bit; one : AluBitwiseCtrlEnum; zero : AluBitwiseCtrlEnum) return AluBitwiseCtrlEnum;
subtype AluBitwiseCtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant AluBitwiseCtrlEnum_binary_sequential_XOR_1 : AluBitwiseCtrlEnum_binary_sequential_type := "00";
constant AluBitwiseCtrlEnum_binary_sequential_OR_1 : AluBitwiseCtrlEnum_binary_sequential_type := "01";
constant AluBitwiseCtrlEnum_binary_sequential_AND_1 : AluBitwiseCtrlEnum_binary_sequential_type := "10";
function pkg_mux (sel : bit; one : AluCtrlEnum; zero : AluCtrlEnum) return AluCtrlEnum;
subtype AluCtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant AluCtrlEnum_binary_sequential_ADD_SUB : AluCtrlEnum_binary_sequential_type := "00";
constant AluCtrlEnum_binary_sequential_SLT_SLTU : AluCtrlEnum_binary_sequential_type := "01";
constant AluCtrlEnum_binary_sequential_BITWISE : AluCtrlEnum_binary_sequential_type := "10";
function pkg_mux (sel : bit; one : EnvCtrlEnum; zero : EnvCtrlEnum) return EnvCtrlEnum;
subtype EnvCtrlEnum_binary_sequential_type is bit_vector(0 downto 0);
constant EnvCtrlEnum_binary_sequential_NONE : EnvCtrlEnum_binary_sequential_type := "0";
constant EnvCtrlEnum_binary_sequential_XRET : EnvCtrlEnum_binary_sequential_type := "1";
function pkg_mux (sel : bit; one : Src2CtrlEnum; zero : Src2CtrlEnum) return Src2CtrlEnum;
subtype Src2CtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant Src2CtrlEnum_binary_sequential_RS : Src2CtrlEnum_binary_sequential_type := "00";
constant Src2CtrlEnum_binary_sequential_IMI : Src2CtrlEnum_binary_sequential_type := "01";
constant Src2CtrlEnum_binary_sequential_IMS : Src2CtrlEnum_binary_sequential_type := "10";
constant Src2CtrlEnum_binary_sequential_PC : Src2CtrlEnum_binary_sequential_type := "11";
function pkg_mux (sel : bit; one : Src1CtrlEnum; zero : Src1CtrlEnum) return Src1CtrlEnum;
subtype Src1CtrlEnum_binary_sequential_type is bit_vector(1 downto 0);
constant Src1CtrlEnum_binary_sequential_RS : Src1CtrlEnum_binary_sequential_type := "00";
constant Src1CtrlEnum_binary_sequential_IMU : Src1CtrlEnum_binary_sequential_type := "01";
constant Src1CtrlEnum_binary_sequential_PC_INCREMENT : Src1CtrlEnum_binary_sequential_type := "10";
constant Src1CtrlEnum_binary_sequential_URS1 : Src1CtrlEnum_binary_sequential_type := "11";
function pkg_mux (sel : bit; one : JtagState; zero : JtagState) return JtagState;
function pkg_toStdLogicVector_native (value : JtagState) return bit_vector;
function pkg_toJtagState_native (value : bit_vector(3 downto 0)) return JtagState;
function pkg_mux (sel : bit; one : UartStopType; zero : UartStopType) return UartStopType;
subtype UartStopType_binary_sequential_type is bit_vector(0 downto 0);
constant UartStopType_binary_sequential_ONE : UartStopType_binary_sequential_type := "0";
constant UartStopType_binary_sequential_TWO : UartStopType_binary_sequential_type := "1";
function pkg_mux (sel : bit; one : UartParityType; zero : UartParityType) return UartParityType;
subtype UartParityType_binary_sequential_type is bit_vector(1 downto 0);
constant UartParityType_binary_sequential_NONE : UartParityType_binary_sequential_type := "00";
constant UartParityType_binary_sequential_EVEN : UartParityType_binary_sequential_type := "01";
constant UartParityType_binary_sequential_ODD : UartParityType_binary_sequential_type := "10";
function pkg_mux (sel : bit; one : UartCtrlTxState; zero : UartCtrlTxState) return UartCtrlTxState;
function pkg_toStdLogicVector_native (value : UartCtrlTxState) return bit_vector;
function pkg_toUartCtrlTxState_native (value : bit_vector(2 downto 0)) return UartCtrlTxState;
function pkg_mux (sel : bit; one : UartCtrlRxState; zero : UartCtrlRxState) return UartCtrlRxState;
function pkg_toStdLogicVector_native (value : UartCtrlRxState) return bit_vector;
function pkg_toUartCtrlRxState_native (value : bit_vector(2 downto 0)) return UartCtrlRxState;
end pkg_enum;
package pkg_scala2hdl is
function pkg_extract (that : bit_vector; bitId : integer) return bit;
type unsigned is array (natural range <>) of bit;
type signed is array (natural range <>) of bit;
function pkg_cat (a : signed; b : signed) return signed;
function pkg_not (value : signed) return signed;
function pkg_mux (sel : bit; one : bit; zero : bit) return bit;
function pkg_mux (sel : bit; one : bit_vector; zero : bit_vector) return bit_vector;
function pkg_mux (sel : bit; one : unsigned; zero : unsigned) return unsigned;
function pkg_mux (sel : bit; one : signed; zero : signed) return signed;
function pkg_toStdLogic (value : boolean) return bit;
function pkg_toStdLogicVector (value : bit) return bit_vector;
end pkg_scala2hdl;
library work;
use work.pkg_scala2hdl.all;
use work.all;
use work.pkg_enum.all;
entity UartCtrlTx is
port(
io_configFrame_dataLength : in unsigned(2 downto 0);
io_configFrame_stop : in UartStopType_binary_sequential_type;
io_configFrame_parity : in UartParityType_binary_sequential_type;
io_samplingTick : in bit;
io_write_valid : in bit;
io_write_ready : out bit;
io_write_payload : in bit_vector(7 downto 0);
io_cts : in bit;
io_txd : out bit;
io_break : in bit;
io_mainClk : in bit;
resetCtrl_systemReset : in bit
);
end UartCtrlTx;
architecture arch of UartCtrlTx is
signal clockDivider_counter_willIncrement : bit;
signal clockDivider_counter_willClear : bit;
signal clockDivider_counter_valueNext : unsigned(2 downto 0);
signal clockDivider_counter_value : unsigned(2 downto 0);
signal clockDivider_counter_willOverflowIfInc : bit;
signal clockDivider_counter_willOverflow : bit;
signal tickCounter_value : unsigned(2 downto 0);
signal stateMachine_state : UartCtrlTxState;
signal stateMachine_parity : bit;
signal stateMachine_txd : bit;
signal when_UartCtrlTx_l58 : bit;
signal when_UartCtrlTx_l73 : bit;
signal when_UartCtrlTx_l76 : bit;
signal when_UartCtrlTx_l93 : bit;
signal zz_io_txd : bit;
begin
process(io_samplingTick)
begin
clockDivider_counter_willIncrement <= pkg_toStdLogic(false);
if io_samplingTick = '1' then
clockDivider_counter_willIncrement <= pkg_toStdLogic(true);
end if;
end process;
clockDivider_counter_willClear <= pkg_toStdLogic(false);
process(stateMachine_state,io_write_payload,tickCounter_value,stateMachine_parity)
begin
stateMachine_txd <= pkg_toStdLogic(true);
case stateMachine_state is
when pkg_enum.IDLE =>
when pkg_enum.START =>
stateMachine_txd <= pkg_toStdLogic(false);
when pkg_enum.DATA =>
when pkg_enum.PARITY =>
stateMachine_txd <= stateMachine_parity;
when others =>
end case;
end process;
process(io_break,stateMachine_state,clockDivider_counter_willOverflow,when_UartCtrlTx_l73)
begin
io_write_ready <= io_break;
case stateMachine_state is
when pkg_enum.IDLE =>
when pkg_enum.START =>
when pkg_enum.DATA =>
if clockDivider_counter_willOverflow = '1' then
if when_UartCtrlTx_l73 = '1' then
io_write_ready <= pkg_toStdLogic(true);
end if;
end if;
when pkg_enum.PARITY =>
when others =>
end case;
end process;
io_txd <= zz_io_txd;
process(io_mainClk, resetCtrl_systemReset)
begin
if resetCtrl_systemReset = '1' then
stateMachine_state <= pkg_enum.IDLE;
zz_io_txd <= pkg_toStdLogic(true);
elsif io_mainClk'active and io_mainClk = '1' then
clockDivider_counter_value <= clockDivider_counter_valueNext;
case stateMachine_state is
when pkg_enum.IDLE =>
if when_UartCtrlTx_l58 = '1' then
stateMachine_state <= pkg_enum.START;
end if;
when pkg_enum.START =>
if clockDivider_counter_willOverflow = '1' then
stateMachine_state <= pkg_enum.DATA;
end if;
when pkg_enum.DATA =>
if clockDivider_counter_willOverflow = '1' then
if when_UartCtrlTx_l73 = '1' then
if when_UartCtrlTx_l76 = '1' then
stateMachine_state <= pkg_enum.STOP;
else
stateMachine_state <= pkg_enum.PARITY;
end if;
end if;
end if;
when pkg_enum.PARITY =>
if clockDivider_counter_willOverflow = '1' then
stateMachine_state <= pkg_enum.STOP;
end if;
when others =>
if clockDivider_counter_willOverflow = '1' then
if when_UartCtrlTx_l93 = '1' then
stateMachine_state <= pkg_mux(io_write_valid,pkg_enum.START,pkg_enum.IDLE);
end if;
end if;
end case;
zz_io_txd <= (stateMachine_txd and (not io_break));
end if;
end process;
end arch;
| gpl-3.0 | 45ae68705f34145a15f5e09e7a07b82d | 0.721287 | 3.85365 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispout01/tb_rec05.vhdl | 1 | 489 | entity tb_rec05 is
end tb_rec05;
library ieee;
use ieee.std_logic_1164.all;
use work.rec05_pkg.all;
architecture behav of tb_rec05 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec05
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r = (a => "1010", b => '0') severity failure;
inp <= '0';
wait for 1 ns;
assert r = (a => "0101", b => '1') severity failure;
wait;
end process;
end behav;
| gpl-2.0 | e380eb5b7715f231b69b90994599f46a | 0.595092 | 3 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/PoC/tb/sort/sortnet/sortnet_BitonicSort_tb.vhdl | 1 | 7,472 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library OSVVM;
use OSVVM.RandomPkg.all;
library PoC;
use PoC.math.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
-- simulation only packages
use PoC.sim_types.all;
use PoC.simulation.all;
use PoC.waveform.all;
library Test;
entity sortnet_BitonicSort_tb is
end entity;
architecture tb of sortnet_BitonicSort_tb is
constant TAG_BITS : positive := 4;
constant INPUTS : positive := 64;
constant DATA_COLUMNS : positive := 2;
constant KEY_BITS : positive := 32;
constant DATA_BITS : positive := 64;
constant META_BITS : positive := TAG_BITS;
constant PIPELINE_STAGE_AFTER : natural := 2;
constant LOOP_COUNT : positive := 32; -- 1024;
constant STAGES : positive := triangularNumber(log2ceil(INPUTS));
constant DELAY : natural := STAGES / PIPELINE_STAGE_AFTER;
package P_SORTNET_TB is new Test.sortnet_tb
generic map (
META_BITS => META_BITS,
DATA_BITS => DATA_BITS,
INPUTS => INPUTS
);
use P_SORTNET_TB.all;
constant CLOCK_FREQ : FREQ := 100 MHz;
signal Clock : std_logic := '1';
signal Generator_Valid : std_logic := '0';
signal Generator_IsKey : std_logic := '0';
signal Generator_Data : T_DATA_VECTOR(INPUTS - 1 downto 0) := (others => (others => '0'));
signal Generator_Meta : std_logic_vector(META_BITS - 1 downto 0) := (others => '0');
signal Sort_Valid : std_logic;
signal Sort_IsKey : std_logic;
signal Sort_Data : T_DATA_VECTOR(INPUTS - 1 downto 0);
signal Sort_Meta : std_logic_vector(META_BITS - 1 downto 0);
signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
shared variable ScoreBoard : PT_SCOREBOARD;
begin
-- initialize global simulation status
simInitialize;
simWriteMessage("SETTINGS");
simWriteMessage(" INPUTS: " & integer'image(INPUTS));
simWriteMessage(" KEY_BITS: " & integer'image(KEY_BITS));
simWriteMessage(" DATA_BITS: " & integer'image(DATA_BITS));
simWriteMessage(" REG AFTER: " & integer'image(PIPELINE_STAGE_AFTER));
simGenerateClock(Clock, CLOCK_FREQ);
procGenerator : process
constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Generator");
variable RandomVar : RandomPType; -- protected type from RandomPkg
variable KeyInput : std_logic_vector(KEY_BITS - 1 downto 0);
variable DataInput : std_logic_vector(DATA_BITS - KEY_BITS - 1 downto 0);
variable TagInput : std_logic_vector(TAG_BITS - 1 downto 0);
variable Generator_Input : T_DATA_VECTOR(INPUTS - 1 downto 0);
function GreaterThan(L : std_logic_vector; R : std_logic_vector) return boolean is
alias LL is L(KEY_BITS - 1 downto 0);
alias RR is R(KEY_BITS - 1 downto 0);
begin
return unsigned(LL) > unsigned(RR);
end function;
variable ScoreBoardData : T_SCOREBOARD_DATA;
begin
RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds
Generator_Valid <= '0';
Generator_IsKey <= '0';
Generator_Input := (others => (others => '0'));
Generator_Meta <= (others => '0');
wait until rising_edge(Clock);
Generator_Valid <= '1';
for i in 0 to LOOP_COUNT - 1 loop
-- report "Loop: " & integer'image (i) severity note;
TagInput := RandomVar.RandSlv(TAG_BITS);
ScoreBoardData.IsKey := to_sl(i mod DATA_COLUMNS = 0);
ScoreBoardData.Meta := resize(TagInput, META_BITS);
Generator_IsKey <= ScoreBoardData.IsKey;
Generator_Meta <= ScoreBoardData.Meta;
KeyInput := RandomVar.RandSlv(KEY_BITS);
DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS);
Generator_Input(0) := DataInput & KeyInput;
ScoreBoardData.Data(0):= Generator_Input(0);
loop_j: for j in 1 to INPUTS - 1 loop
KeyInput := RandomVar.RandSlv(KEY_BITS);
DataInput := RandomVar.RandSlv(DATA_BITS - KEY_BITS);
Generator_Input(j) := DataInput & KeyInput;
for k in j downto 1 loop
if GreaterThan(ScoreBoardData.Data(k - 1), Generator_Input(j)) then
ScoreBoardData.Data(k) := ScoreBoardData.Data(k - 1);
else
ScoreBoardData.Data(k) := Generator_Input(j);
next loop_j;
end if;
end loop;
ScoreBoardData.Data(0) := Generator_Input(j);
end loop;
Generator_Data <= Generator_Input;
ScoreBoard.Push(ScoreBoardData);
wait until rising_edge(Clock);
end loop;
Generator_Valid <= '0';
wait until rising_edge(Clock);
-- This process is finished
simDeactivateProcess(simProcessID);
wait; -- forever
end process;
DataInputMatrix <= to_slm(Generator_Data);
sort : entity PoC.sortnet_BitonicSort
generic map (
INPUTS => INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS,
META_BITS => META_BITS,
PIPELINE_STAGE_AFTER => PIPELINE_STAGE_AFTER
)
port map (
Clock => Clock,
Reset => '0',
In_Valid => Generator_Valid,
In_IsKey => Generator_IsKey,
In_Data => DataInputMatrix,
In_Meta => Generator_Meta,
Out_Valid => Sort_Valid,
Out_IsKey => Sort_IsKey,
Out_Data => DataOutputMatrix,
Out_Meta => Sort_Meta
);
Sort_Data <= to_dv(DataOutputMatrix);
procChecker : process
constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Checker");
variable Check : boolean;
variable CurValue : unsigned(KEY_BITS - 1 downto 0);
variable LastValue : unsigned(KEY_BITS - 1 downto 0);
variable ScoreBoardData : T_SCOREBOARD_DATA;
begin
wait until rising_edge(Sort_Valid);
for i in 0 to LOOP_COUNT - 1 loop
wait until falling_edge(Clock);
Check := TRUE;
ScoreBoardData.IsKey := Sort_IsKey;
ScoreBoardData.Meta := Sort_Meta;
ScoreBoardData.Data := Sort_Data;
ScoreBoard.Check(ScoreBoardData);
end loop;
-- simAssertion(Check, "Result is not monotonic." & raw_format_slv_hex(std_logic_vector(LastValue)));
-- This process is finished
simDeactivateProcess(simProcessID);
wait; -- forever
end process;
end architecture;
| gpl-2.0 | 30137de5f4d49d85fe806ed2d50af024 | 0.637045 | 3.346171 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source-b.vhd | 4 | 7,041 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_source-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of source is
begin
token_generator : process is
variable source_name : string(1 to name_max_length) := (others => ' ');
variable source_name_length : natural;
variable next_token_id : token_id_type := 0;
variable next_arrival_time : time;
variable number_of_tokens_generated : natural := 0;
variable inter_arrival_time : natural; -- in time_unit
variable sum_of_inter_arrival_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_inter_arrival_times : real := 0.0; --in time_unit**2
variable random_info : random_info_record;
variable random_number : real;
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable measured_mean_inter_arrival_time : real
:= sum_of_inter_arrival_times / real(number_of_tokens_generated);
variable measured_std_dev_of_inter_arrival_times : real
:= sqrt ( ( sum_of_squares_of_inter_arrival_times
- sum_of_inter_arrival_times**2 / real(number_of_tokens_generated) )
/ real( number_of_tokens_generated - 1 ) );
begin
write(L, string'("Summary information for source "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Inter arrival distribution: "));
write(L, distribution_type'image(distribution));
write(L, string'(" with mean inter arrival time of "));
write(L, mean_inter_arrival_time, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens generated = "));
write(L, natural(next_token_id));
writeline(info_file, L);
write(L, string'(" Mean inter arrival time = "));
write(L, measured_mean_inter_arrival_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of inter arrival times = "));
write(L, measured_std_dev_of_inter_arrival_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Source "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" generated token "));
write(L, natural(next_token_id));
writeline(info_file, L);
end procedure write_trace;
begin
if name'length > name_max_length then
source_name := name(1 to name_max_length);
source_name_length := name_max_length;
else
source_name(1 to name'length) := name;
source_name_length := name'length;
end if;
file_open(info_file, info_file_name, write_mode);
case distribution is
when fixed =>
init_fixed(random_info, real(mean_inter_arrival_time / time_unit));
when uniform =>
init_uniform( random_info,
lower_bound => 0.0,
upper_bound => 2.0 * real(mean_inter_arrival_time / time_unit),
seed => seed );
when exponential =>
init_exponential( random_info,
mean => real(mean_inter_arrival_time / time_unit),
seed => seed );
end case;
loop
generate_random(random_info, random_number);
inter_arrival_time := natural(random_number);
next_arrival_time := inter_arrival_time * time_unit + now;
loop
wait on info_detail'transaction for next_arrival_time - now;
if info_detail'active and info_detail = summary then
write_summary;
end if;
exit when next_arrival_time = now;
end loop;
out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
token => token_type'( source_name => source_name,
source_name_length => source_name_length,
id => next_token_id,
creation_time => now ) );
number_of_tokens_generated := number_of_tokens_generated + 1;
sum_of_inter_arrival_times := sum_of_inter_arrival_times
+ real(inter_arrival_time);
sum_of_squares_of_inter_arrival_times := sum_of_squares_of_inter_arrival_times
+ real(inter_arrival_time) ** 2;
if info_detail = trace then
write_trace;
end if;
next_token_id := next_token_id + 1;
end loop;
end process token_generator;
end architecture behavior;
| gpl-2.0 | 9e81bf0933cc3f46ad304d8d34b85c40 | 0.483028 | 4.842503 | false | false | false | false |
cdsteinkuehler/AXI_Reg | AXI_Reg_Rd.vhd | 1 | 10,507 | -- Copyright (C) 2015, Charles Steinkuehler
-- <charles AT steinkuehler DOT net>
-- All rights reserved
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of the copyright holder nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Reg_Pkg.all;
library lpm;
use lpm.lpm_components.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity AXI_Reg_Rd_E is
generic (
latency : integer := 3 );
port (
clk : in std_logic;
rst : in std_logic;
-- Read Address Channel
axi_arid : in std_logic_vector(13 downto 0);
axi_araddr : in std_logic_vector(13 downto 0);
axi_arlen : in std_logic_vector(7 downto 0);
axi_arsize : in std_logic_vector(2 downto 0);
axi_arburst : in std_logic_vector(1 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
-- Read Data Channel
axi_rid : out std_logic_vector(13 downto 0);
axi_rdata : out std_logic_vector(31 downto 0);
axi_rlast : out std_logic;
axi_rvalid : out std_logic;
axi_rready : in std_logic;
-- Register read data
Bank1RegRd : in RegRd_A(255 downto 0);
Bank2RegRd : in RegRd_A(255 downto 0) );
end AXI_Reg_Rd_E;
architecture arch of AXI_Reg_Rd_E is
constant C_PRE_READ_CYCLES : integer := 3;
signal start : std_logic;
signal a_busy : std_logic;
signal p_busy : std_logic;
signal p_done : std_logic;
signal p_cnt : unsigned(numbits(latency+1)-1 downto 0);
signal d_busy : std_logic;
signal d_done : std_logic;
signal tx_id : std_logic_vector(13 downto 0);
signal tx_addr : unsigned(13 downto 0);
signal tx_addr_nxt : unsigned(13 downto 0);
signal addr_inc : unsigned(13 downto 0);
signal addr_wrap : unsigned(13 downto 0);
signal addr_mask : unsigned(13 downto 0);
signal addr_align : unsigned(13 downto 0);
signal tx_len : unsigned(7 downto 0);
signal tx_size : std_logic_vector(2 downto 0);
signal tx_burst : std_logic_vector(1 downto 0);
signal tx_data : std_logic_vector(31 downto 0);
signal num_bytes : unsigned(3 downto 0);
signal lpm_mx_addr : std_logic_vector(9 downto 0);
signal lpm_mx_data : std_logic_2D(1023 downto 0, 31 downto 0);
signal lpm_mx_rden : std_logic;
begin
axi_arready <= '1' when a_busy='0' else '0';
axi_rid <= tx_id;
axi_rdata <= tx_data;
axi_rlast <= d_done;
axi_rvalid <= d_busy;
with tx_burst select
tx_addr_nxt <= tx_addr when b"00", -- Fixed-address burst
addr_inc when b"01", -- Normal sequential memory
addr_wrap when b"10", -- Cache line burst
tx_addr when others; -- Reserved
with tx_size select
num_bytes <= x"1" when b"000",
x"2" when b"001",
x"4" when b"010",
x"4" when others;
with tx_size select
addr_mask <= ( others=>'1') when b"000",
(0 downto 0 => '0', others=>'1') when b"001",
(1 downto 0 => '0', others=>'1') when b"010",
(1 downto 0 => '0', others=>'1') when others;
addr_align <= tx_addr and addr_mask;
addr_inc <= addr_align + num_bytes;
--FIXME: AXI burst wrapping is complex...ignore for now.
addr_wrap <= addr_inc;
start <= '1' when axi_arvalid='1' and a_busy='0' else '0';
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
a_busy <= '0';
p_busy <= '0';
p_done <= '0';
p_cnt <= (others=>'0');
d_busy <= '0';
d_done <= '0';
tx_id <= (others=>'0');
tx_addr <= (others=>'0');
tx_len <= (others=>'0');
tx_size <= (others=>'0');
tx_burst <= (others=>'0');
else
-- Transaction state machine:
-- idle -> pre-read -> data -> idle
if start='1' then
a_busy <= '1';
d_busy <= '0';
elsif p_done='1' then
d_busy <= '1';
elsif d_done='1' and axi_rready='1' then
a_busy <= '0';
d_busy <= '0';
end if;
if start='1' then
p_cnt <= to_unsigned(C_PRE_READ_CYCLES, p_cnt'length);
elsif p_cnt /= 0 then
p_cnt <= p_cnt - 1;
end if;
if start='1' then
p_busy <= '1';
elsif p_done='1' or p_cnt = 0 then
p_busy <= '0';
end if;
if start='1' and C_PRE_READ_CYCLES = 1 then
p_done <= '1';
elsif p_cnt=2 then
p_done <= '1';
else
p_done <= '0';
end if;
if p_done='1' and tx_len=0 then
d_done <= '1';
elsif d_busy='1' and tx_len=1 and axi_rready='1' then
d_done <= '1';
-- Keep d_done set until the last word actually transfers
elsif d_done='1' and axi_rready='0' then
d_done <= '1';
else
d_done <= '0';
end if;
if start='1' then
tx_id <= axi_arid;
tx_size <= axi_arsize;
tx_burst <= axi_arburst;
end if;
if start='1' then
tx_addr <= unsigned(axi_araddr);
tx_len <= unsigned(axi_arlen);
elsif p_busy='1' then
tx_addr <= tx_addr_nxt;
elsif d_busy='1' and axi_rready='1' then
tx_addr <= tx_addr_nxt;
if tx_len /= 0 then
tx_len <= tx_len - 1;
end if;
end if;
end if;
end if;
end process;
-- Map DMA and Register readback channels to 2D LPM input bus
mx_data : for index in 255 downto 0 generate
begin
-- VHDL cannot access a slice of a 2D array, so assign each bit individually
bitsL : for bit in 31 downto 0 generate
begin
lpm_mx_data((index * 2) , bit) <= Bank1RegRd (index)(bit);
lpm_mx_data((index * 2) + 512, bit) <= Bank2RegRd(index)(bit);
end generate;
bitsH : for bit in 31 downto 0 generate
begin
lpm_mx_data((index * 2) + 1, bit) <= Bank1RegRd (index)(bit + 32);
lpm_mx_data((index * 2) + 513, bit) <= Bank2RegRd(index)(bit + 32);
end generate;
end generate;
lpm_mx_addr <= std_logic_vector(resize(tx_addr(tx_addr'left downto 2),lpm_mx_addr'length));
lpm_mx_rden <= '1' when p_busy='1' or (d_busy='1' and axi_rready='1') else '0';
rd_mx : lpm_mux
generic map (
LPM_WIDTH => 32,
LPM_SIZE => 1024,
LPM_WIDTHS => 10,
LPM_PIPELINE => latency )
port map (
clock => clk,
clken => lpm_mx_rden,
data => lpm_mx_data,
sel => lpm_mx_addr,
result => tx_data );
end arch;
| bsd-3-clause | e423836231f9e0e8886b060d3901925e | 0.521557 | 3.888601 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1423.vhd | 4 | 1,963 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1423.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p05n01i01423ent IS
END c08s06b00x00p05n01i01423ent;
ARCHITECTURE c08s06b00x00p05n01i01423arch OF c08s06b00x00p05n01i01423ent IS
procedure check (signal x : in integer;
signal kkk : out integer ) is
begin
if (x = 0) then
kkk <= 5;
wait for 1 ns;
end if;
end check;
signal k : integer := 0;
signal kk : integer := 0;
BEGIN
TESTING : PROCESS
BEGIN
check (k,kk);
assert NOT(kk = 5)
report "***PASSED TEST: c08s06b00x00p05n01i01423"
severity NOTE;
assert (kk = 5)
report "***FAILED TEST: c08s06b00x00p05n01i01423 - No actual parmeter is required for a formal parmeter with a default expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p05n01i01423arch;
| gpl-2.0 | c7fc1009ee7a3660760e92e5487880e2 | 0.654101 | 3.648699 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1095/top.vhdl | 1 | 892 | library ieee;
use ieee.std_logic_1164.all;
entity xor_gate is
generic (
INVERT : boolean
);
port (
a : in std_logic;
b : in std_logic;
q : out std_logic
);
end;
architecture a of xor_gate is
begin
gen: if INVERT generate
q <= not (a xor b);
else generate
q <= a xor b;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
x : in std_logic;
y : in std_logic;
o_custom : out std_logic;
o_and : out std_logic
);
end;
architecture a of top is
component comp is
port (
a : in std_logic;
b : in std_logic;
q : out std_logic
);
end component;
begin
comp_inst: comp
port map (
a => x,
b => y,
q => o_custom
);
o_and <= x and y;
end;
configuration conf of top is
for a
for comp_inst : comp
use entity work.xor_gate
generic map (
INVERT => false
);
end for;
end for;
end configuration;
| gpl-2.0 | d132fcee4d8e99aa04cf59cb22b810ec | 0.615471 | 2.608187 | false | false | false | false |
nickg/nvc | test/regress/gentype1.vhd | 1 | 2,585 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
type T;
DEPTH : positive );
port (
clk : in std_logic;
pop : in std_logic;
push : in std_logic;
full : out std_logic;
valid : out std_logic;
din : in T;
dout : out T );
end entity;
architecture test of fifo is
type fifo_data_t is array (0 to DEPTH - 1) of T;
signal wptr, rptr : natural := 1;
signal data : fifo_data_t;
begin
full <= '1' when (wptr + 1) mod DEPTH = rptr else '0';
valid <= '1' when wptr /= rptr else '0';
dout <= data(rptr);
behav: process (clk) is
begin
if rising_edge(clk) then
if push = '1' then
assert full = '0';
data(wptr) <= din;
wptr <= (wptr + 1) mod DEPTH;
end if;
if pop = '1' then
assert valid = '1';
rptr <= (rptr + 1) mod DEPTH;
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity gentype1 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of gentype1 is
signal clk : std_logic;
signal pop : std_logic;
signal push : std_logic;
signal din : integer;
signal dout : integer;
signal full : std_logic;
signal valid : std_logic;
procedure pulse (signal clk : out std_logic) is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end procedure;
begin
u: entity work.fifo
generic map ( T => integer, depth => 4 )
port map (
clk => clk,
pop => pop,
push => push,
din => din,
dout => dout,
full => full,
valid => valid );
main: process is
begin
wait for 1 ns;
assert full = '0';
assert valid = '0';
din <= 5;
push <= '1';
pulse(clk);
assert full = '0';
assert valid = '1';
assert dout = 5;
din <= 7;
pulse(clk);
assert full = '0';
assert valid = '1';
assert dout = 5;
push <= '0';
pop <= '1';
pulse(clk);
assert full = '0';
assert valid = '1';
assert dout = 7;
pulse(clk);
assert full = '0';
assert valid = '0';
wait;
end process;
end architecture;
| gpl-3.0 | 8db5d54dfd4a7c6cbf96557dde0c86ca | 0.456867 | 3.875562 | false | false | false | false |
nickg/nvc | test/bounds/issue477b.vhd | 1 | 2,410 | package test_pkg is
type t_segment_type is (
TYPE_0,
TYPE_1,
TYPE_2,
TYPE_3,
TYPE_4,
TYPE_5
);
type unsigned is array (natural range <>) of bit;
type t_data_segment is record
data_word : bit_vector(15 downto 0); -- 0: 16
word_idx : unsigned(11 downto 0); -- 16: 12
segment_type : t_segment_type; -- 28: 1+3
word_length : natural range 1 to 2; -- 32: 4
crc_check : boolean; -- 36: 1+3
table : natural range 1 to 2; -- 40: 4
end record;
type t_data_segment_template is array(t_segment_type) of t_data_segment;
constant C_SEGMENT_RECORDS : t_data_segment_template := (
TYPE_0 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_0,
word_length => 1,
crc_check => false,
table => 16#a0#),
TYPE_1 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_1,
word_length => 2,
crc_check => false,
table => 1),
TYPE_2 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_2,
word_length => 1,
crc_check => false,
table => 16#a1#),
TYPE_3 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_3,
word_length => 2,
crc_check => true,
table => 16#a2#),
TYPE_4 => (
data_word => (others => '0'),
word_idx => (others => '0'),
segment_type => TYPE_4,
word_length => 2,
crc_check => true,
table => 16#a3#)
-- Error
);
constant C_DATA_INVALID_VERSION : bit_vector(7 downto 0) := x"FF";
constant C_DATA_VERSION : bit_vector(C_SEGMENT_RECORDS(TYPE_2).word_length*8-1 downto 0) := C_DATA_INVALID_VERSION;
end package;
| gpl-3.0 | b1ea3c399158006db6b61d164847707b | 0.393361 | 3.905997 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/tb_dff08.vhdl | 1 | 821 | entity tb_dff08 is
end tb_dff08;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff08 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff08
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
clk <= '1';
wait for 1 ns;
assert dout = '0' severity failure;
clk <= '0';
wait for 1 ns;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | ed7232a4d6ecaecb86db216dbc94eda2 | 0.559074 | 3.364754 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_19.vhd | 4 | 1,813 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_19 is
end entity fg_07_19;
architecture test of fg_07_19 is
constant Thold_d_clk : delay_length := 3 ns;
signal clk, d : bit := '0';
begin
-- code from book
hold_time_checker : process ( clk, d ) is
variable last_clk_edge_time : time := 0 fs;
begin
if clk'event and clk = '1' then
last_clk_edge_time := now;
end if;
if d'event then
assert now - last_clk_edge_time >= Thold_d_clk
report "hold time violation";
end if;
end process hold_time_checker;
-- end code from book
clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
stimulus : d <= '1' after 15 ns,
'0' after 53 ns,
'1' after 72 ns;
end architecture test;
| gpl-2.0 | 60c4693194ba488c90be5ba2bbcc34a0 | 0.590734 | 3.865672 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/AESL_axi_s_inStream.vhd | 1 | 87,124 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity AESL_axi_s_inStream is
generic (
constant TV_IN_inStream_TDATA : STRING (1 to 62) := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_data_V.dat";
constant INGRESS_STATUS_inStream_TDATA : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_data_V.dat";
constant TV_IN_inStream_TKEEP : STRING (1 to 62) := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_keep_V.dat";
constant INGRESS_STATUS_inStream_TKEEP : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_keep_V.dat";
constant TV_IN_inStream_TSTRB : STRING (1 to 62) := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_strb_V.dat";
constant INGRESS_STATUS_inStream_TSTRB : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_strb_V.dat";
constant TV_IN_inStream_TUSER : STRING (1 to 62) := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_user_V.dat";
constant INGRESS_STATUS_inStream_TUSER : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_user_V.dat";
constant TV_IN_inStream_TLAST : STRING (1 to 62) := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_last_V.dat";
constant INGRESS_STATUS_inStream_TLAST : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_last_V.dat";
constant TV_IN_inStream_TID : STRING (1 to 60) := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_id_V.dat";
constant INGRESS_STATUS_inStream_TID : STRING (1 to 59) := "../tv/stream_size/stream_ingress_status_inStream_V_id_V.dat";
constant TV_IN_inStream_TDEST : STRING (1 to 62) := "../tv/cdatafile/c.doHistStretch.autotvin_inStream_V_dest_V.dat";
constant INGRESS_STATUS_inStream_TDEST : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_dest_V.dat";
constant INTERFACE_TYPE : STRING (1 to 5) := "axi_s";
constant AUTOTB_TRANSACTION_NUM : INTEGER := 1
);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_inStream_TDATA : OUT STD_LOGIC_VECTOR (8 - 1 downto 0);
inStream_TDATA_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TKEEP : OUT STD_LOGIC_VECTOR (1 - 1 downto 0);
inStream_TKEEP_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TSTRB : OUT STD_LOGIC_VECTOR (1 - 1 downto 0);
inStream_TSTRB_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TUSER : OUT STD_LOGIC_VECTOR (2 - 1 downto 0);
inStream_TUSER_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TLAST : OUT STD_LOGIC_VECTOR (1 - 1 downto 0);
inStream_TLAST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TID : OUT STD_LOGIC_VECTOR (5 - 1 downto 0);
inStream_TID_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TDEST : OUT STD_LOGIC_VECTOR (6 - 1 downto 0);
inStream_TDEST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TVALID : OUT STD_LOGIC;
TRAN_inStream_TREADY : IN STD_LOGIC;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_axi_s_inStream;
architecture behav of AESL_axi_s_inStream is
------------------------Local signal-------------------
signal reg_inStream_TVALID : STD_LOGIC;
signal inStream_TDATA_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TDATA_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TDATA_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TDATA_empty_n : STD_LOGIC;
signal inStream_TDATA_full_n : STD_LOGIC;
type inStream_TDATA_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(8 - 1 downto 0);
signal inStream_TDATA_mem : inStream_TDATA_arr2D := (others => (others => '0'));
signal inStream_TDATA_ingress_status : INTEGER;
signal inStream_TDATA_ingress_status_bit : STD_LOGIC;
signal inStream_TDATA_in_i : INTEGER;
signal inStream_TDATA_in_end : STD_LOGIC;
signal inStream_TDATA_in_end_reg : STD_LOGIC;
signal inStream_TDATA_in_size : INTEGER;
signal inStream_TDATA_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TDATA_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TKEEP_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TKEEP_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TKEEP_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TKEEP_empty_n : STD_LOGIC;
signal inStream_TKEEP_full_n : STD_LOGIC;
type inStream_TKEEP_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(1 - 1 downto 0);
signal inStream_TKEEP_mem : inStream_TKEEP_arr2D := (others => (others => '0'));
signal inStream_TKEEP_ingress_status : INTEGER;
signal inStream_TKEEP_ingress_status_bit : STD_LOGIC;
signal inStream_TKEEP_in_i : INTEGER;
signal inStream_TKEEP_in_end : STD_LOGIC;
signal inStream_TKEEP_in_end_reg : STD_LOGIC;
signal inStream_TKEEP_in_size : INTEGER;
signal inStream_TKEEP_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TKEEP_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TSTRB_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TSTRB_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TSTRB_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TSTRB_empty_n : STD_LOGIC;
signal inStream_TSTRB_full_n : STD_LOGIC;
type inStream_TSTRB_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(1 - 1 downto 0);
signal inStream_TSTRB_mem : inStream_TSTRB_arr2D := (others => (others => '0'));
signal inStream_TSTRB_ingress_status : INTEGER;
signal inStream_TSTRB_ingress_status_bit : STD_LOGIC;
signal inStream_TSTRB_in_i : INTEGER;
signal inStream_TSTRB_in_end : STD_LOGIC;
signal inStream_TSTRB_in_end_reg : STD_LOGIC;
signal inStream_TSTRB_in_size : INTEGER;
signal inStream_TSTRB_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TSTRB_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TUSER_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TUSER_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TUSER_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TUSER_empty_n : STD_LOGIC;
signal inStream_TUSER_full_n : STD_LOGIC;
type inStream_TUSER_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(2 - 1 downto 0);
signal inStream_TUSER_mem : inStream_TUSER_arr2D := (others => (others => '0'));
signal inStream_TUSER_ingress_status : INTEGER;
signal inStream_TUSER_ingress_status_bit : STD_LOGIC;
signal inStream_TUSER_in_i : INTEGER;
signal inStream_TUSER_in_end : STD_LOGIC;
signal inStream_TUSER_in_end_reg : STD_LOGIC;
signal inStream_TUSER_in_size : INTEGER;
signal inStream_TUSER_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TUSER_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TLAST_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TLAST_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TLAST_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TLAST_empty_n : STD_LOGIC;
signal inStream_TLAST_full_n : STD_LOGIC;
type inStream_TLAST_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(1 - 1 downto 0);
signal inStream_TLAST_mem : inStream_TLAST_arr2D := (others => (others => '0'));
signal inStream_TLAST_ingress_status : INTEGER;
signal inStream_TLAST_ingress_status_bit : STD_LOGIC;
signal inStream_TLAST_in_i : INTEGER;
signal inStream_TLAST_in_end : STD_LOGIC;
signal inStream_TLAST_in_end_reg : STD_LOGIC;
signal inStream_TLAST_in_size : INTEGER;
signal inStream_TLAST_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TLAST_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TID_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TID_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TID_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TID_empty_n : STD_LOGIC;
signal inStream_TID_full_n : STD_LOGIC;
type inStream_TID_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(5 - 1 downto 0);
signal inStream_TID_mem : inStream_TID_arr2D := (others => (others => '0'));
signal inStream_TID_ingress_status : INTEGER;
signal inStream_TID_ingress_status_bit : STD_LOGIC;
signal inStream_TID_in_i : INTEGER;
signal inStream_TID_in_end : STD_LOGIC;
signal inStream_TID_in_end_reg : STD_LOGIC;
signal inStream_TID_in_size : INTEGER;
signal inStream_TID_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TID_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TDEST_mInPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TDEST_mOutPtr : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
signal inStream_TDEST_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TDEST_empty_n : STD_LOGIC;
signal inStream_TDEST_full_n : STD_LOGIC;
type inStream_TDEST_arr2D is array(0 to 262144) of STD_LOGIC_VECTOR(6 - 1 downto 0);
signal inStream_TDEST_mem : inStream_TDEST_arr2D := (others => (others => '0'));
signal inStream_TDEST_ingress_status : INTEGER;
signal inStream_TDEST_ingress_status_bit : STD_LOGIC;
signal inStream_TDEST_in_i : INTEGER;
signal inStream_TDEST_in_end : STD_LOGIC;
signal inStream_TDEST_in_end_reg : STD_LOGIC;
signal inStream_TDEST_in_size : INTEGER;
signal inStream_TDEST_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TDEST_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal reset_reg : STD_LOGIC;
function esl_icmp_eq(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if v1 = v2 then
res := "1";
else
res := "0";
end if;
return res;
end function;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_icmp_ult(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if unsigned(v1) < unsigned(v2) then
res := "1";
else
res := "0";
end if;
return res;
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if (RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if (i = 1) then
if ((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif ((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif ((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif ((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end esl_str_dec2int;
begin
TRAN_inStream_TVALID_proc : process( inStream_TDATA_empty_n, inStream_TKEEP_empty_n, inStream_TSTRB_empty_n, inStream_TUSER_empty_n, inStream_TLAST_empty_n, inStream_TID_empty_n, inStream_TDEST_empty_n, reset, inStream_TDATA_ingress_status_bit , inStream_TKEEP_ingress_status_bit , inStream_TSTRB_ingress_status_bit , inStream_TUSER_ingress_status_bit , inStream_TLAST_ingress_status_bit , inStream_TID_ingress_status_bit , inStream_TDEST_ingress_status_bit)
begin
if reset = '0' then
TRAN_inStream_TVALID <= '0';
reg_inStream_TVALID <= '0';
else
TRAN_inStream_TVALID <= (inStream_TDATA_ingress_status_bit and inStream_TKEEP_ingress_status_bit and inStream_TSTRB_ingress_status_bit and inStream_TUSER_ingress_status_bit and inStream_TLAST_ingress_status_bit and inStream_TID_ingress_status_bit and inStream_TDEST_ingress_status_bit) or ('1' and inStream_TDATA_empty_n and inStream_TKEEP_empty_n and inStream_TSTRB_empty_n and inStream_TUSER_empty_n and inStream_TLAST_empty_n and inStream_TID_empty_n and inStream_TDEST_empty_n and '1');
reg_inStream_TVALID <= (inStream_TDATA_ingress_status_bit and inStream_TKEEP_ingress_status_bit and inStream_TSTRB_ingress_status_bit and inStream_TUSER_ingress_status_bit and inStream_TLAST_ingress_status_bit and inStream_TID_ingress_status_bit and inStream_TDEST_ingress_status_bit) or ('1' and inStream_TDATA_empty_n and inStream_TKEEP_empty_n and inStream_TSTRB_empty_n and inStream_TUSER_empty_n and inStream_TLAST_empty_n and inStream_TID_empty_n and inStream_TDEST_empty_n and '1');
end if;
end process;
------------------------Read-only axi_s-------------------
-- Write operation for read_only axi_s port
inStream_TDATA_ingress_status_bit <= '1' when inStream_TDATA_ingress_status > 0 else '0';
inStream_TKEEP_ingress_status_bit <= '1' when inStream_TKEEP_ingress_status > 0 else '0';
inStream_TSTRB_ingress_status_bit <= '1' when inStream_TSTRB_ingress_status > 0 else '0';
inStream_TUSER_ingress_status_bit <= '1' when inStream_TUSER_ingress_status > 0 else '0';
inStream_TLAST_ingress_status_bit <= '1' when inStream_TLAST_ingress_status > 0 else '0';
inStream_TID_ingress_status_bit <= '1' when inStream_TID_ingress_status > 0 else '0';
inStream_TDEST_ingress_status_bit <= '1' when inStream_TDEST_ingress_status > 0 else '0';
proc_gen_reset_reg: process(clk)
begin
if(clk'event and clk = '1') then
reset_reg <= reset;
end if;
end process;
------------------------------- inStream_TDATA --------------------------------
inStream_TDATA_empty_n_proc : process(inStream_TDATA_mInPtr, inStream_TDATA_mOutPtr, inStream_TDATA_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TDATA_mInPtr, inStream_TDATA_mOutPtr) = "1" and (inStream_TDATA_mFlag_hint = '0')) then
inStream_TDATA_empty_n <= '0';
else
inStream_TDATA_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TDATA_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_data_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_data_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TDATA_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TDATA_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TDATA_in_end <= '1' when ((inStream_TDATA_in_size = 0) and (reset_reg = '1')) or ((inStream_TDATA_in_i = (inStream_TDATA_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TDATA_trans_num_sig <= inStream_TDATA_trans_num_reg + 1 when ((inStream_TDATA_in_end = '1') and (inStream_TDATA_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TDATA_trans_num_reg;
inStream_TDATA_trans_num <= inStream_TDATA_trans_num_sig;
proc_gen_inStream_TDATA_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TDATA_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TDATA_in_i < inStream_TDATA_in_size - 1) then
inStream_TDATA_in_i <= inStream_TDATA_in_i + 1;
elsif(inStream_TDATA_in_end = '1') then
inStream_TDATA_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TDATA_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TDATA_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TDATA_trans_num_reg <= inStream_TDATA_trans_num_sig;
end if;
end process;
proc_gen_inStream_TDATA_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TDATA_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TDATA_in_end_reg <= inStream_TDATA_in_end;
end if;
end process;
inStream_TDATA_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TDATA_mInPtr_var : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
variable inStream_TDATA_mem_var : inStream_TDATA_arr2D := (others => (others => '0'));
begin
inStream_TDATA_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TDATA, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TDATA & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TDATA, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TDATA & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TDATA_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TDATA_mInPtr_var) > 262144 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TDATA_mem_var(CONV_INTEGER(inStream_TDATA_mInPtr_var)) := esl_str2lv_hex(token, 8);
inStream_TDATA_mInPtr_var := esl_add(inStream_TDATA_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TDATA_mInPtr <= inStream_TDATA_mInPtr_var;
inStream_TDATA_mem <= inStream_TDATA_mem_var;
inStream_TDATA_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TDATA_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TDATA_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TDATA_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TDATA_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TDATA <= inStream_TDATA_mem(CONV_INTEGER(inStream_TDATA_mOutPtr));
inStream_TDATA_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TDATA_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TDATA_mOutPtr,inStream_TDATA_mInPtr) = "1") then
inStream_TDATA_mOutPtr <= esl_add(inStream_TDATA_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TKEEP --------------------------------
inStream_TKEEP_empty_n_proc : process(inStream_TKEEP_mInPtr, inStream_TKEEP_mOutPtr, inStream_TKEEP_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TKEEP_mInPtr, inStream_TKEEP_mOutPtr) = "1" and (inStream_TKEEP_mFlag_hint = '0')) then
inStream_TKEEP_empty_n <= '0';
else
inStream_TKEEP_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TKEEP_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_keep_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_keep_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TKEEP_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TKEEP_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TKEEP_in_end <= '1' when ((inStream_TKEEP_in_size = 0) and (reset_reg = '1')) or ((inStream_TKEEP_in_i = (inStream_TKEEP_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TKEEP_trans_num_sig <= inStream_TKEEP_trans_num_reg + 1 when ((inStream_TKEEP_in_end = '1') and (inStream_TKEEP_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TKEEP_trans_num_reg;
inStream_TKEEP_trans_num <= inStream_TKEEP_trans_num_sig;
proc_gen_inStream_TKEEP_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TKEEP_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TKEEP_in_i < inStream_TKEEP_in_size - 1) then
inStream_TKEEP_in_i <= inStream_TKEEP_in_i + 1;
elsif(inStream_TKEEP_in_end = '1') then
inStream_TKEEP_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TKEEP_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TKEEP_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TKEEP_trans_num_reg <= inStream_TKEEP_trans_num_sig;
end if;
end process;
proc_gen_inStream_TKEEP_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TKEEP_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TKEEP_in_end_reg <= inStream_TKEEP_in_end;
end if;
end process;
inStream_TKEEP_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TKEEP_mInPtr_var : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
variable inStream_TKEEP_mem_var : inStream_TKEEP_arr2D := (others => (others => '0'));
begin
inStream_TKEEP_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TKEEP, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TKEEP & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TKEEP, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TKEEP & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TKEEP_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TKEEP_mInPtr_var) > 262144 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TKEEP_mem_var(CONV_INTEGER(inStream_TKEEP_mInPtr_var)) := esl_str2lv_hex(token, 1);
inStream_TKEEP_mInPtr_var := esl_add(inStream_TKEEP_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TKEEP_mInPtr <= inStream_TKEEP_mInPtr_var;
inStream_TKEEP_mem <= inStream_TKEEP_mem_var;
inStream_TKEEP_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TKEEP_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TKEEP_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TKEEP_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TKEEP_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TKEEP <= inStream_TKEEP_mem(CONV_INTEGER(inStream_TKEEP_mOutPtr));
inStream_TKEEP_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TKEEP_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TKEEP_mOutPtr,inStream_TKEEP_mInPtr) = "1") then
inStream_TKEEP_mOutPtr <= esl_add(inStream_TKEEP_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TSTRB --------------------------------
inStream_TSTRB_empty_n_proc : process(inStream_TSTRB_mInPtr, inStream_TSTRB_mOutPtr, inStream_TSTRB_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TSTRB_mInPtr, inStream_TSTRB_mOutPtr) = "1" and (inStream_TSTRB_mFlag_hint = '0')) then
inStream_TSTRB_empty_n <= '0';
else
inStream_TSTRB_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TSTRB_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_strb_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_strb_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TSTRB_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TSTRB_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TSTRB_in_end <= '1' when ((inStream_TSTRB_in_size = 0) and (reset_reg = '1')) or ((inStream_TSTRB_in_i = (inStream_TSTRB_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TSTRB_trans_num_sig <= inStream_TSTRB_trans_num_reg + 1 when ((inStream_TSTRB_in_end = '1') and (inStream_TSTRB_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TSTRB_trans_num_reg;
inStream_TSTRB_trans_num <= inStream_TSTRB_trans_num_sig;
proc_gen_inStream_TSTRB_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TSTRB_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TSTRB_in_i < inStream_TSTRB_in_size - 1) then
inStream_TSTRB_in_i <= inStream_TSTRB_in_i + 1;
elsif(inStream_TSTRB_in_end = '1') then
inStream_TSTRB_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TSTRB_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TSTRB_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TSTRB_trans_num_reg <= inStream_TSTRB_trans_num_sig;
end if;
end process;
proc_gen_inStream_TSTRB_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TSTRB_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TSTRB_in_end_reg <= inStream_TSTRB_in_end;
end if;
end process;
inStream_TSTRB_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TSTRB_mInPtr_var : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
variable inStream_TSTRB_mem_var : inStream_TSTRB_arr2D := (others => (others => '0'));
begin
inStream_TSTRB_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TSTRB, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TSTRB & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TSTRB, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TSTRB & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TSTRB_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TSTRB_mInPtr_var) > 262144 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TSTRB_mem_var(CONV_INTEGER(inStream_TSTRB_mInPtr_var)) := esl_str2lv_hex(token, 1);
inStream_TSTRB_mInPtr_var := esl_add(inStream_TSTRB_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TSTRB_mInPtr <= inStream_TSTRB_mInPtr_var;
inStream_TSTRB_mem <= inStream_TSTRB_mem_var;
inStream_TSTRB_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TSTRB_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TSTRB_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TSTRB_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TSTRB_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TSTRB <= inStream_TSTRB_mem(CONV_INTEGER(inStream_TSTRB_mOutPtr));
inStream_TSTRB_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TSTRB_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TSTRB_mOutPtr,inStream_TSTRB_mInPtr) = "1") then
inStream_TSTRB_mOutPtr <= esl_add(inStream_TSTRB_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TUSER --------------------------------
inStream_TUSER_empty_n_proc : process(inStream_TUSER_mInPtr, inStream_TUSER_mOutPtr, inStream_TUSER_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TUSER_mInPtr, inStream_TUSER_mOutPtr) = "1" and (inStream_TUSER_mFlag_hint = '0')) then
inStream_TUSER_empty_n <= '0';
else
inStream_TUSER_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TUSER_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_user_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_user_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TUSER_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TUSER_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TUSER_in_end <= '1' when ((inStream_TUSER_in_size = 0) and (reset_reg = '1')) or ((inStream_TUSER_in_i = (inStream_TUSER_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TUSER_trans_num_sig <= inStream_TUSER_trans_num_reg + 1 when ((inStream_TUSER_in_end = '1') and (inStream_TUSER_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TUSER_trans_num_reg;
inStream_TUSER_trans_num <= inStream_TUSER_trans_num_sig;
proc_gen_inStream_TUSER_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TUSER_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TUSER_in_i < inStream_TUSER_in_size - 1) then
inStream_TUSER_in_i <= inStream_TUSER_in_i + 1;
elsif(inStream_TUSER_in_end = '1') then
inStream_TUSER_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TUSER_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TUSER_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TUSER_trans_num_reg <= inStream_TUSER_trans_num_sig;
end if;
end process;
proc_gen_inStream_TUSER_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TUSER_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TUSER_in_end_reg <= inStream_TUSER_in_end;
end if;
end process;
inStream_TUSER_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TUSER_mInPtr_var : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
variable inStream_TUSER_mem_var : inStream_TUSER_arr2D := (others => (others => '0'));
begin
inStream_TUSER_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TUSER, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TUSER & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TUSER, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TUSER & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TUSER_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TUSER_mInPtr_var) > 262144 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TUSER_mem_var(CONV_INTEGER(inStream_TUSER_mInPtr_var)) := esl_str2lv_hex(token, 2);
inStream_TUSER_mInPtr_var := esl_add(inStream_TUSER_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TUSER_mInPtr <= inStream_TUSER_mInPtr_var;
inStream_TUSER_mem <= inStream_TUSER_mem_var;
inStream_TUSER_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TUSER_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TUSER_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TUSER_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TUSER_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TUSER <= inStream_TUSER_mem(CONV_INTEGER(inStream_TUSER_mOutPtr));
inStream_TUSER_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TUSER_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TUSER_mOutPtr,inStream_TUSER_mInPtr) = "1") then
inStream_TUSER_mOutPtr <= esl_add(inStream_TUSER_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TLAST --------------------------------
inStream_TLAST_empty_n_proc : process(inStream_TLAST_mInPtr, inStream_TLAST_mOutPtr, inStream_TLAST_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TLAST_mInPtr, inStream_TLAST_mOutPtr) = "1" and (inStream_TLAST_mFlag_hint = '0')) then
inStream_TLAST_empty_n <= '0';
else
inStream_TLAST_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TLAST_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_last_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_last_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TLAST_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TLAST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TLAST_in_end <= '1' when ((inStream_TLAST_in_size = 0) and (reset_reg = '1')) or ((inStream_TLAST_in_i = (inStream_TLAST_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TLAST_trans_num_sig <= inStream_TLAST_trans_num_reg + 1 when ((inStream_TLAST_in_end = '1') and (inStream_TLAST_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TLAST_trans_num_reg;
inStream_TLAST_trans_num <= inStream_TLAST_trans_num_sig;
proc_gen_inStream_TLAST_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TLAST_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TLAST_in_i < inStream_TLAST_in_size - 1) then
inStream_TLAST_in_i <= inStream_TLAST_in_i + 1;
elsif(inStream_TLAST_in_end = '1') then
inStream_TLAST_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TLAST_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TLAST_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TLAST_trans_num_reg <= inStream_TLAST_trans_num_sig;
end if;
end process;
proc_gen_inStream_TLAST_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TLAST_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TLAST_in_end_reg <= inStream_TLAST_in_end;
end if;
end process;
inStream_TLAST_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TLAST_mInPtr_var : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
variable inStream_TLAST_mem_var : inStream_TLAST_arr2D := (others => (others => '0'));
begin
inStream_TLAST_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TLAST, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TLAST & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TLAST, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TLAST & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TLAST_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TLAST_mInPtr_var) > 262144 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TLAST_mem_var(CONV_INTEGER(inStream_TLAST_mInPtr_var)) := esl_str2lv_hex(token, 1);
inStream_TLAST_mInPtr_var := esl_add(inStream_TLAST_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TLAST_mInPtr <= inStream_TLAST_mInPtr_var;
inStream_TLAST_mem <= inStream_TLAST_mem_var;
inStream_TLAST_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TLAST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TLAST_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TLAST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TLAST_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TLAST <= inStream_TLAST_mem(CONV_INTEGER(inStream_TLAST_mOutPtr));
inStream_TLAST_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TLAST_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TLAST_mOutPtr,inStream_TLAST_mInPtr) = "1") then
inStream_TLAST_mOutPtr <= esl_add(inStream_TLAST_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TID --------------------------------
inStream_TID_empty_n_proc : process(inStream_TID_mInPtr, inStream_TID_mOutPtr, inStream_TID_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TID_mInPtr, inStream_TID_mOutPtr) = "1" and (inStream_TID_mFlag_hint = '0')) then
inStream_TID_empty_n <= '0';
else
inStream_TID_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TID_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_id_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_id_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TID_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TID_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TID_in_end <= '1' when ((inStream_TID_in_size = 0) and (reset_reg = '1')) or ((inStream_TID_in_i = (inStream_TID_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TID_trans_num_sig <= inStream_TID_trans_num_reg + 1 when ((inStream_TID_in_end = '1') and (inStream_TID_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TID_trans_num_reg;
inStream_TID_trans_num <= inStream_TID_trans_num_sig;
proc_gen_inStream_TID_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TID_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TID_in_i < inStream_TID_in_size - 1) then
inStream_TID_in_i <= inStream_TID_in_i + 1;
elsif(inStream_TID_in_end = '1') then
inStream_TID_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TID_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TID_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TID_trans_num_reg <= inStream_TID_trans_num_sig;
end if;
end process;
proc_gen_inStream_TID_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TID_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TID_in_end_reg <= inStream_TID_in_end;
end if;
end process;
inStream_TID_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TID_mInPtr_var : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
variable inStream_TID_mem_var : inStream_TID_arr2D := (others => (others => '0'));
begin
inStream_TID_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TID, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TID & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TID, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TID & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TID_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TID_mInPtr_var) > 262144 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TID_mem_var(CONV_INTEGER(inStream_TID_mInPtr_var)) := esl_str2lv_hex(token, 5);
inStream_TID_mInPtr_var := esl_add(inStream_TID_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TID_mInPtr <= inStream_TID_mInPtr_var;
inStream_TID_mem <= inStream_TID_mem_var;
inStream_TID_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TID_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TID_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TID_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TID_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TID <= inStream_TID_mem(CONV_INTEGER(inStream_TID_mOutPtr));
inStream_TID_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TID_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TID_mOutPtr,inStream_TID_mInPtr) = "1") then
inStream_TID_mOutPtr <= esl_add(inStream_TID_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TDEST --------------------------------
inStream_TDEST_empty_n_proc : process(inStream_TDEST_mInPtr, inStream_TDEST_mOutPtr, inStream_TDEST_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TDEST_mInPtr, inStream_TDEST_mOutPtr) = "1" and (inStream_TDEST_mFlag_hint = '0')) then
inStream_TDEST_empty_n <= '0';
else
inStream_TDEST_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TDEST_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_dest_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_dest_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TDEST_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TDEST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TDEST_in_end <= '1' when ((inStream_TDEST_in_size = 0) and (reset_reg = '1')) or ((inStream_TDEST_in_i = (inStream_TDEST_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TDEST_trans_num_sig <= inStream_TDEST_trans_num_reg + 1 when ((inStream_TDEST_in_end = '1') and (inStream_TDEST_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TDEST_trans_num_reg;
inStream_TDEST_trans_num <= inStream_TDEST_trans_num_sig;
proc_gen_inStream_TDEST_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TDEST_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TDEST_in_i < inStream_TDEST_in_size - 1) then
inStream_TDEST_in_i <= inStream_TDEST_in_i + 1;
elsif(inStream_TDEST_in_end = '1') then
inStream_TDEST_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TDEST_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TDEST_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TDEST_trans_num_reg <= inStream_TDEST_trans_num_sig;
end if;
end process;
proc_gen_inStream_TDEST_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TDEST_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TDEST_in_end_reg <= inStream_TDEST_in_end;
end if;
end process;
inStream_TDEST_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TDEST_mInPtr_var : STD_LOGIC_VECTOR (19 downto 0) := (others => '0');
variable inStream_TDEST_mem_var : inStream_TDEST_arr2D := (others => (others => '0'));
begin
inStream_TDEST_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TDEST, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TDEST & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TDEST, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TDEST & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TDEST_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TDEST_mInPtr_var) > 262144 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TDEST_mem_var(CONV_INTEGER(inStream_TDEST_mInPtr_var)) := esl_str2lv_hex(token, 6);
inStream_TDEST_mInPtr_var := esl_add(inStream_TDEST_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TDEST_mInPtr <= inStream_TDEST_mInPtr_var;
inStream_TDEST_mem <= inStream_TDEST_mem_var;
inStream_TDEST_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TDEST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TDEST_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TDEST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TDEST_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TDEST <= inStream_TDEST_mem(CONV_INTEGER(inStream_TDEST_mOutPtr));
inStream_TDEST_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TDEST_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TDEST_mOutPtr,inStream_TDEST_mInPtr) = "1") then
inStream_TDEST_mOutPtr <= esl_add(inStream_TDEST_mOutPtr, "1");
end if;
end if;
end if;
end process;
end behav;
| gpl-3.0 | 606f7844417fd756980cd6e60a686dcb | 0.574354 | 3.588008 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | RCA/32bits/RCA/RCA.vhd | 1 | 1,806 | -- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (31 downto 0);
SomaResult: out std_logic_vector (31 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (31 downto 1);
signal CarryInTemp: std_logic;
signal CarryOutTemp0,CarryOutTemp1: std_logic;
signal A, B, Ssoma: std_logic_vector(31 downto 0);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg32Bit
port(
valIn: in std_logic_vector(31 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(31 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>CarryInTemp
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>CarryOutTemp0,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_A: Reg32Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A
);
Reg_B: Reg32Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B
);
Reg_Ssoma: Reg32Bit PORT MAP (
valIn=>Ssoma,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
--somador--
Som0: Soma1 PORT MAP (
CarryInTemp,
A(0),
B(0),
Ssoma(0),
carry(1)
);
SOM: FOR i IN 1 TO 30 GENERATE
Som1: Soma1 PORT MAP (
carry(i),
A(i),
B(i),
Ssoma(i),
carry(i+1)
);
END GENERATE;
Som7: Soma1 PORT MAP (
carry(31),
A(31),
B(31),
Ssoma(31),
CarryOutTemp0
);
END strc_RCA ; | mit | 065a063758dd600fb42dc3ee24e6a5a3 | 0.631783 | 2.57265 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/float_generic_pkg-body.vhdl | 2 | 230,768 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Floating-point package (Generic package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body float_generic_pkg is
-- Author David Bishop ([email protected])
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report float_generic_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED
is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN
is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert no_warning
report float_generic_pkg'instance_name
& "BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC
is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR
is
variable intermediate_result : UNRESOLVED_float(arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
intermediate_result := arg;
return STD_ULOGIC_VECTOR (intermediate_result);
end function to_sulv;
-- Converts an fp into an SULV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or (fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNRESOLVED_UNSIGNED; -- unsigned
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate
is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report float_generic_pkg'instance_name
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_UNSIGNED;
expon : out UNRESOLVED_SIGNED;
sign : out STD_ULOGIC) is
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width
expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r; -- r := -r
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED
is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED
is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := Classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report float_generic_pkg'instance_name
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_generic_pkg'instance_name
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize (exponl, rexpon'length) - exponr - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_generic_pkg'instance_name
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or (urfract (fraction_width-1 downto 0)) = '0')
report float_generic_pkg'instance_name
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
cfptype := Classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_X01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := Classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := Classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := Classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (Is_Negative (l)) then
remres := - remres;
end if;
if (Is_Negative (l) = Is_Negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_X01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_X01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := Classfp (l, check_error);
rfptype := Classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
lfptype := Classfp (L, float_check_error);
rfptype := Classfp (R, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => L,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => R,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := to_sulv(lresize) ?= to_sulv(rresize);
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function "?=";
function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
lfptype := Classfp (L, float_check_error);
rfptype := Classfp (R, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => L,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => R,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := to_sulv(lresize) ?= to_sulv(rresize);
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function "?/=";
function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(L'low, R'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or L'length < 7 or R'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif Is_X(L) or Is_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report float_generic_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (L, exponent_width, fraction_width);
rresize := resize (R, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(L'low, R'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(L'high, R'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (L, exponent_width, fraction_width);
rresize := resize (R, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
begin
fptype := Classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and(fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNRESOLVED_UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is arg;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : UNRESOLVED_SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := arg'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is arg;
variable arg_int : UNSIGNED(XARG'range); -- Real version of argument
variable argb2 : UNSIGNED(XARG'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (XARG) then
result := (others => 'X');
elsif (XARG = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(XARG (XARG'high));
arg_int := UNSIGNED(abs (to_01(XARG)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float
is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float
is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float
is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- unsigned version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width + 1 downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement
else
result (exponent_width) := '0';
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned
end if;
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER
is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED
is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED
is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction
variable result : UNRESOLVED_SIGNED (size-1 downto 0);
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED
is
variable result : UNRESOLVED_UNSIGNED (size_res'range);
begin
if (size_res'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED
is
variable result : UNRESOLVED_SIGNED (size_res'range);
begin
if (size_res'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := Classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert no_warning
report float_generic_pkg'instance_name
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?= r_float;
end function "?=";
function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?/= r_float;
end function "?/=";
function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?> r_float;
end function "?>";
function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?>= r_float;
end function "?>=";
function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?< r_float;
end function "?<";
function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?<= r_float;
end function "?<=";
-- real and float
function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?= r;
end function "?=";
function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?/= r;
end function "?/=";
function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?> r;
end function "?>";
function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?>= r;
end function "?>=";
function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?< r;
end function "?<";
function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?<= r;
end function "?<=";
-- ?= overloads
function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?= r_float;
end function "?=";
function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?/= r_float;
end function "?/=";
function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?> r_float;
end function "?>";
function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?>= r_float;
end function "?>=";
function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?< r_float;
end function "?<";
function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?<= r_float;
end function "?<=";
-- integer and float
function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?= r;
end function "?=";
function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?/= r;
end function "?/=";
function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?> r;
end function "?>";
function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?>= r;
end function "?>=";
function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?< r;
end function "?<";
function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?<= r;
end function "?<=";
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert no_warning
report float_generic_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L and to_sulv(R));
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) and R);
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L or to_sulv(R));
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) or R);
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L nand to_sulv(R));
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) nand R);
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L nor to_sulv(R));
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) nor R);
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L xor to_sulv(R));
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) xor R);
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L xnor to_sulv(R));
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) xnor R);
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := Classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : UNRESOLVED_SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER
is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := Classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return UNRESOLVED_SIGNED
is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := Classfp (x, check_error);
validfpy := Classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and (fract) = '1' then -- fraction is all "1".
if and (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert no_warning
report float_generic_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or (fract) = '0' then -- fraction is all "0".
if or (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or Classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and (fract) = '1' then -- fraction is all "1".
if and (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert no_warning
report float_generic_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or (fract) = '0' then -- fraction is all "0".
if or (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN
is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := Classfp (x);
rfptype := Classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN
is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN
is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable c : CHARACTER;
variable left : positive;
begin
while L /= null and L.all'length /= 0 loop
left := L.all'left;
c := L.all(left);
if (c = ' ' or c = NBSP or c = HT) then
read (L, c);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'high - VALUE'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
READ (L, c, readOk);
if VALUE'length > 0 then
i := VALUE'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report float_generic_pkg'instance_name
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= VALUE'low) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = VALUE'high then -- Begins with an "_"
report float_generic_pkg'instance_name
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report float_generic_pkg'instance_name
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = VALUE'high-1) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < VALUE'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (L, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
READ (L, c, readOk);
if VALUE'length > 0 then
i := VALUE'high;
GOOD := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < VALUE'low then
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (L, c, readOk);
end loop readloop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((VALUE'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report float_generic_pkg'instance_name & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_generic_pkg'instance_name & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((VALUE'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((VALUE'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report float_generic_pkg'instance_name & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_generic_pkg'instance_name & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((VALUE'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (L, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(value(value'high)));
s(2) := ':';
sindx := 3;
for i in value'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto value'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report float_generic_pkg'instance_name
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report float_generic_pkg'instance_name
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report float_generic_pkg'instance_name
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
end package body float_generic_pkg;
| gpl-2.0 | 69ca4e4bd16b3403f37b754b2f5c50f5 | 0.545587 | 4.250419 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd | 1 | 3,455 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016
--Date : Thu Jun 23 02:18:07 2016
--Host : darkin-UX303LN running 64-bit elementary OS Freya
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component design_1;
begin
design_1_i: component design_1
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
| gpl-3.0 | 575cb7d6c57517565fb93d65d4ce08f0 | 0.589001 | 3.065661 | false | false | false | false |
tgingold/ghdl | testsuite/vpi/vpi002/mydesign.vhdl | 1 | 1,307 | library ieee ;
use ieee.std_logic_1164.all;
package mypackage is
type myenum is (ONE, TWO, THREE);
subtype myarray is bit_vector(2 downto 0);
type myarray5 is array(1 downto 0) of bit;
end package;
library ieee ;
use ieee.std_logic_1164.all;
use work.mypackage.all;
entity myentity is
generic (
width: integer := 2;
genenum: myenum := ONE;
genarray1: bit_vector(1 downto 0) := "01";
genarray3: myarray := "010";
genarray5: myarray5 := ('1', '0')
);
port (
portenum: in myenum;
portarray1: in bit_vector(1 downto 0);
portarray2: in bit_vector(width downto 0);
portarray3: in myarray;
portarray5: in myarray5
);
end myentity;
architecture arch of myentity is
subtype myarray4 is bit_vector(width downto 0);
signal sigenum: myenum;
constant constenum: myenum := ONE;
signal sigarray1: bit_vector(1 downto 0);
constant constarray1: bit_vector(1 downto 0) := "10";
signal sigarray2: bit_vector(width downto 0);
constant constarray2: bit_vector(width downto 0) := (others => '1');
signal sigarray3: myarray;
constant constarray3: myarray := "101";
signal sigarray4: myarray4;
constant constarray4: myarray4:= (others => '1');
signal sigarray5: myarray5;
constant constarray5: myarray5:= (others => '1');
begin
end arch;
| gpl-2.0 | b352bb7d48e1cbcbb05fa77a35160033 | 0.682479 | 3.300505 | false | false | false | false |
nickg/nvc | test/parse/expr.vhd | 1 | 947 | entity e is end entity;
package foo is
function "and"(x, y : integer) return bit;
end package;
architecture a of e is
signal v : bit_vector(1 to 3);
type rec is record
z : integer;
end record;
function f(x : integer) return rec;
begin
process is
variable x, y, z : integer; variable b : boolean; variable q : bit_vector(1 to 3);
begin
b := not (x > y);
x := abs (-5);
x := y ** z;
x := f(4).z;
q := q sll 1;
q := q srl 1;
q := q sla 1;
q := q sra 1;
q := q rol 1;
q := q ror 1;
q(1) := work.foo."and"(1, 2);
q(q'range) := q;
q := (1 => '1', v'range => '0');
x := -3 * 4 + 2;
end process;
process is
variable x, y, z : integer;
begin
x := y/+z; -- Error
x := y**-z; -- Error
end process;
end architecture;
| gpl-3.0 | 8d14a5e10f99ae819e357638a2487b2c | 0.436114 | 3.370107 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_check_data/shift_bytes.vhd | 1 | 7,028 | -------------------------------------------------------------------------------------
-- FILE NAME : shift_bytes.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Accept an input data stream and shifts the bytes
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- non-IEEE packages
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity shift_bytes is
port (
clk_in : in std_logic;
rst_in : in std_logic;
data_in : in std_logic_vector(63 downto 0);
valid_in : in std_logic;
data_out : out std_logic_vector(63 downto 0);
valid_out : out std_logic;
shift_amount_in : in std_logic_vector(2 downto 0)
);
end shift_bytes;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of shift_bytes is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type bus008 is array(natural range <>) of std_logic_vector( 7 downto 0);
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal valid_pipe : std_logic_vector(2 downto 0);
signal data_pipe : bus064(2 downto 0);
signal data_pipe_byte : bus008(23 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
-- buffer 3 cycles
process(clk_in)
begin
if rising_edge(clk_in) then
valid_pipe(2) <= valid_in;
valid_pipe(1) <= valid_pipe(2);
valid_pipe(0) <= valid_pipe(1);
if valid_in = '1' then
data_pipe(2) <= data_in;
data_pipe(1) <= data_pipe(2);
data_pipe(0) <= data_pipe(1);
end if;
end if;
end process;
-- Remap
data_pipe_byte(23) <= data_pipe(2)(63 downto 56);
data_pipe_byte(22) <= data_pipe(2)(55 downto 48);
data_pipe_byte(21) <= data_pipe(2)(47 downto 40);
data_pipe_byte(20) <= data_pipe(2)(39 downto 32);
data_pipe_byte(19) <= data_pipe(2)(31 downto 24);
data_pipe_byte(18) <= data_pipe(2)(23 downto 16);
data_pipe_byte(17) <= data_pipe(2)(15 downto 8);
data_pipe_byte(16) <= data_pipe(2)( 7 downto 0);
data_pipe_byte(15) <= data_pipe(1)(63 downto 56);
data_pipe_byte(14) <= data_pipe(1)(55 downto 48);
data_pipe_byte(13) <= data_pipe(1)(47 downto 40);
data_pipe_byte(12) <= data_pipe(1)(39 downto 32);
data_pipe_byte(11) <= data_pipe(1)(31 downto 24);
data_pipe_byte(10) <= data_pipe(1)(23 downto 16);
data_pipe_byte(9) <= data_pipe(1)(15 downto 8);
data_pipe_byte(8) <= data_pipe(1)( 7 downto 0);
data_pipe_byte(7) <= data_pipe(0)(63 downto 56);
data_pipe_byte(6) <= data_pipe(0)(55 downto 48);
data_pipe_byte(5) <= data_pipe(0)(47 downto 40);
data_pipe_byte(4) <= data_pipe(0)(39 downto 32);
data_pipe_byte(3) <= data_pipe(0)(31 downto 24);
data_pipe_byte(2) <= data_pipe(0)(23 downto 16);
data_pipe_byte(1) <= data_pipe(0)(15 downto 8);
data_pipe_byte(0) <= data_pipe(0)( 7 downto 0);
process(clk_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
data_out <= (others=>'0');
valid_out <= '0';
else
case shift_amount_in is
when "000" =>
data_out <= data_pipe_byte(15) & data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) &
data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8);
valid_out <= valid_in;
when "001" =>
data_out <= data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) &
data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7);
valid_out <= valid_in;
when "010" =>
data_out <= data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) &
data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6);
valid_out <= valid_in;
when "011" =>
data_out <= data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) &
data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6) & data_pipe_byte(5);
valid_out <= valid_in;
when "100" =>
data_out <= data_pipe_byte(15) & data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) &
data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8);
valid_out <= valid_in;
when "101" =>
data_out <= data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) &
data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7);
valid_out <= valid_in;
when "110" =>
data_out <= data_pipe_byte(13) & data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) &
data_pipe_byte(9) & data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6);
valid_out <= valid_in;
when "111" =>
data_out <= data_pipe_byte(12) & data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) &
data_pipe_byte(8) & data_pipe_byte(7) & data_pipe_byte(6) & data_pipe_byte(5);
valid_out <= valid_in;
when others =>
data_out <= data_pipe_byte(15) & data_pipe_byte(14) & data_pipe_byte(13) & data_pipe_byte(12) &
data_pipe_byte(11) & data_pipe_byte(10) & data_pipe_byte(9) & data_pipe_byte(8);
valid_out <= valid_in;
end case;
end if;
end if;
end process;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | f30ba799f07524e7874e6f91b9fd4a51 | 0.443654 | 3.538771 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_03.vhd | 4 | 2,064 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_ch_17_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_17_03 is
end entity ch_17_03;
----------------------------------------------------------------
architecture test of ch_17_03 is
begin
process is
type natural_ptr is access natural;
-- code from book:
variable count1, count2 : natural_ptr;
-- end of code from book
begin
-- code from book:
count1 := new natural'(5);
count2 := new natural'(10);
count2 := count1;
count1.all := 20;
-- end of code from book
assert
-- code from book:
count1 = count2
-- end of code from book
;
-- code from book:
count1 := new natural'(30);
count2 := new natural'(30);
-- end of code from book
assert count1 = count2;
assert
-- code from book:
count1.all = count2.all
-- end of code from book
;
-- code from book:
if count1 /= null then
count1.all := count1.all + 1;
end if;
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 | 4a171bed92c1d29fa89711b34d827abc | 0.568314 | 4.144578 | false | false | false | false |
tgingold/ghdl | testsuite/synth/uassoc01/uassoc03.vhdl | 1 | 821 | library ieee;
use ieee.std_logic_1164.all;
entity uassoc03_sub is
port (i : std_logic_vector;
o : out std_logic_vector);
end uassoc03_sub;
architecture behav of uassoc03_sub is
begin
o <= not i;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity uassoc03 is
port (i1 : std_logic_vector(3 downto 0);
i2 : std_logic_vector(7 downto 0);
o : out std_logic_vector(3 downto 0));
end uassoc03;
architecture rtl of uassoc03 is
component uassoc03_sub is
port (i : std_logic_vector;
o : out std_logic_vector);
end component;
signal o1: std_logic_vector(3 downto 0);
signal o2: std_logic_vector(3 downto 0);
begin
dut1: uassoc03_sub
port map (i => i1, o => o1);
dut2: uassoc03_sub
port map (i => i2 (3 downto 0), o => o2);
o <= o1 xor o2;
end rtl;
| gpl-2.0 | 08a5ae2d74a63b14fab148fb832340b7 | 0.64799 | 2.942652 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-pl.vhd | 4 | 5,797 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_mem-pl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture preloaded of memory is
begin
mem_behavior : process is
constant high_address : natural := mem_size - 1;
type memory_array is
array (natural range 0 to high_address / 4) of dlx_bv_word;
variable mem : memory_array
:= ( X"20020000", -- addi r2, r0, 0
X"ac020018", -- loop: sw counter(r0), r2
X"20420001", -- addi r2, r2, 1
X"6441000a", -- snei r1, r2, 10
X"1420fff0", -- bnez r1, loop
X"44000000", -- trap 0
X"00000000", -- counter: .word 0
others => X"00000000" );
variable byte_address, word_address : natural;
variable write_access : boolean;
procedure do_write is
subtype ls_2_bits is bit_vector(1 downto 0);
begin
case width is
when dlx_mem_width_word =>
mem(word_address) := to_bitvector(d);
when dlx_mem_width_halfword =>
if To_bit(a(1)) = '0' then -- ms half word
mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
else -- ls half word
mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
end if;
when dlx_mem_width_byte =>
case ls_2_bits'(To_bitvector(a(1 downto 0))) is
when b"00" =>
mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
when b"01" =>
mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
when b"10" =>
mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
when b"11" =>
mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
end case;
when others =>
report "illegal width indicator in write" severity error;
end case;
end do_write;
procedure do_read is
begin
d <= To_X01( mem(word_address) );
end do_read;
begin
-- initialize outputs
d <= disabled_dlx_word;
ready <= '0';
-- process memory cycles
loop
-- wait for a command, valid on leading edge of phi2
wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
-- decode address and perform command if selected
byte_address := bv_to_natural(To_bitvector(a));
write_access := To_bit(write_enable) = '1';
if byte_address <= high_address then
word_address := byte_address / 4;
if write_access then -- write cycle
do_write;
wait for Tac_first; -- write access time, 1st cycle
else -- read cycle
wait for Tac_first; -- read access time, 1st cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
-- do subsequent cycles in burst
while To_bit(burst) = '1' loop
word_address := (word_address + 1) mod (mem_size / 4);
wait until rising_edge(phi2);
if write_access then -- write cycle
do_write;
wait for Tac_burst; -- write access time, burst cycle
else -- read cycle
wait for Tac_burst; -- read access time, burst cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
end loop;
if not write_access then -- was read
d <= disabled_dlx_word after Tpd_clk_out;
end if;
end if;
end loop;
end process mem_behavior;
end architecture preloaded;
| gpl-2.0 | 4e1e93a3d3783e915515fbe58e2d8ab0 | 0.466793 | 4.532447 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0110/tb5.vhdl | 1 | 572 | package pkg_5 is
type my_arr is array (natural range <>) of bit_vector (7 downto 0);
end pkg_5;
use work.pkg_5.all;
entity ent_5 is
port (v : out my_arr;
b : in bit);
end ent_5;
architecture behav of ent_5 is
begin
v (1) <= (others => b);
end behav;
entity top_5 is
end top_5;
use work.pkg_5.all;
architecture behav of top_5 is
signal s : bit_vector (7 downto 0);
signal b : bit;
begin
dut : entity work.ent_5
port map (
v(1)(3 downto 2) => s (3 downto 2),
v(2)(7 downto 6) => s (7 downto 6),
b => b);
b <= '0';
end behav;
| gpl-2.0 | fd87f1426286aeffa21c793c414dabe9 | 0.589161 | 2.72381 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/syn/vhdl/doHist_CTRL_BUS_s_axi.vhd | 5 | 11,600 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doHist_CTRL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity doHist_CTRL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doHist_CTRL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 | a93cdfef142550698c2084f91874918f | 0.443879 | 3.860233 | false | false | false | false |
tgingold/ghdl | testsuite/synth/case01/case01.vhdl | 1 | 514 | library ieee;
use ieee.std_logic_1164.all;
entity case01 is
port (a : std_logic_vector (4 downto 0);
o : out std_logic);
end case01;
architecture behav of case01 is
begin
process (a)
begin
o <= '0';
case a is
when "00011" =>
o <= '1';
when "00110" | "00111" | "10001" =>
o <= '1';
when "00100" =>
when "01100" =>
o <= '1';
when "10000" =>
o <= '1';
when others =>
o <= '0';
end case;
end process;
end behav;
| gpl-2.0 | 8ba80e22a0eb91447cc73974b1fca507 | 0.484436 | 3.192547 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1307/pixel_processing.vhd | 1 | 4,817 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pixel_processing is
Port ( clk : in STD_LOGIC;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_blank : in std_logic;
in_hsync : in std_logic;
in_vsync : in std_logic;
in_red : in std_logic_vector(7 downto 0);
in_green : in std_logic_vector(7 downto 0);
in_blue : in std_logic_vector(7 downto 0);
is_interlaced : in std_logic;
is_second_field : in std_logic;
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank : out std_logic;
out_hsync : out std_logic;
out_vsync : out std_logic;
out_red : out std_logic_vector(7 downto 0);
out_green : out std_logic_vector(7 downto 0);
out_blue : out std_logic_vector(7 downto 0);
------------------------------------
-- Audio only comes in..
------------------------------------
audio_channel : in std_logic_vector(2 downto 0);
audio_de : in std_logic;
audio_sample : in std_logic_vector(23 downto 0);
----------------------------------
-- Controls
----------------------------------
switches : in std_logic_vector(7 downto 0)
);
end pixel_processing;
architecture Behavioral of pixel_processing is
component edge_enhance is
Port ( clk : in STD_LOGIC;
enable_feature : in std_logic;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_blank : in std_logic;
in_hsync : in std_logic;
in_vsync : in std_logic;
in_red : in std_logic_vector(7 downto 0);
in_green : in std_logic_vector(7 downto 0);
in_blue : in std_logic_vector(7 downto 0);
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank : out std_logic;
out_hsync : out std_logic;
out_vsync : out std_logic;
out_red : out std_logic_vector(7 downto 0);
out_green : out std_logic_vector(7 downto 0);
out_blue : out std_logic_vector(7 downto 0)
);
end component;
component guidelines is
Port ( clk : in STD_LOGIC;
enable_feature : in std_logic;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_blank : in std_logic;
in_hsync : in std_logic;
in_vsync : in std_logic;
in_red : in std_logic_vector(7 downto 0);
in_green : in std_logic_vector(7 downto 0);
in_blue : in std_logic_vector(7 downto 0);
is_interlaced : in std_logic;
is_second_field : in std_logic;
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank : out std_logic;
out_hsync : out std_logic;
out_vsync : out std_logic;
out_red : out std_logic_vector(7 downto 0);
out_green : out std_logic_vector(7 downto 0);
out_blue : out std_logic_vector(7 downto 0)
);
end component;
signal b_blank : std_logic;
signal b_hsync : std_logic;
signal b_vsync : std_logic;
signal b_red : std_logic_vector(7 downto 0);
signal b_green : std_logic_vector(7 downto 0);
signal b_blue : std_logic_vector(7 downto 0);
signal c_blank : std_logic;
signal c_hsync : std_logic;
signal c_vsync : std_logic;
signal c_red : std_logic_vector(7 downto 0);
signal c_green : std_logic_vector(7 downto 0);
signal c_blue : std_logic_vector(7 downto 0);
begin
i_edge_enhance: edge_enhance Port map (
clk => clk,
enable_feature => switches(0),
in_blank => in_blank,
in_hsync => in_hsync,
in_vsync => in_vsync,
in_red => in_red,
in_green => in_green,
in_blue => in_blue,
out_blank => b_blank,
out_hsync => b_hsync,
out_vsync => b_vsync,
out_red => b_red,
out_green => b_green,
out_blue => b_blue
);
end Behavioral;
| gpl-2.0 | adc319292b3d9634ae657c0f5d401823 | 0.439278 | 4.2553 | false | false | false | false |
nickg/nvc | test/eopt/issue72.vhd | 1 | 551 | package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
s2(1 downto 1) <= ( 1 => par1(3 downto 2) );
s2(0 downto 0) <= ( 0 => par1(1 downto 0) );
process is
begin
wait for 1 ns;
assert s1 = ( "11", "11" );
wait;
end process;
end architecture;
| gpl-3.0 | 14659152f67bc4136431c3a1db553443 | 0.584392 | 2.915344 | false | false | false | false |
tgingold/ghdl | testsuite/synth/var01/var04.vhdl | 1 | 595 | library ieee;
use ieee.std_logic_1164.all;
entity var04 is
port (mask : std_logic_vector (1 downto 0);
val : std_logic_vector (15 downto 0);
res : out std_logic_vector (15 downto 0));
end var04;
architecture behav of var04 is
begin
process (all)
variable t : std_logic_vector (15 downto 0);
variable hi, lo : integer;
begin
t := (others => '0');
for i in 0 to 1 loop
if mask (i) = '1' then
lo := i * 8;
hi := lo + 7;
t (hi downto lo) := val (hi downto lo);
end if;
end loop;
res <= t;
end process;
end behav;
| gpl-2.0 | 0e9abfd867af39f0e1a517ad325c4bd9 | 0.566387 | 3.216216 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue123/adder.vhdl | 2 | 1,858 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ADDER is
generic( WIDTH : positive := 8 );
port( CIN : in std_logic;
A : in std_logic_vector(WIDTH-1 downto 0);
B : in std_logic_vector(WIDTH-1 downto 0);
F : out std_logic_vector(WIDTH-1 downto 0);
COUT : out std_logic);
end entity ADDER;
-- Ripple Carry Adder
architecture RCA of ADDER is
signal CIN0 : unsigned(0 downto 0);
signal FIN : unsigned(WIDTH downto 0);
begin
CIN0(0) <= CIN;
FIN <= resize(unsigned(A), WIDTH+1) + resize(unsigned(B), WIDTH+1) + CIN0; -- yes, I know it's not a ripple carry adder
F <= std_logic_vector(FIN(WIDTH-1 downto 0));
COUT <= FIN(WIDTH);
end architecture RCA;
-- Carry Select Adder
architecture CSA of ADDER is
component ADDER is
generic( WIDTH : positive );
port( CIN : in std_logic;
A : in std_logic_vector(WIDTH-1 downto 0);
B : in std_logic_vector(WIDTH-1 downto 0);
F : out std_logic_vector(WIDTH-1 downto 0);
COUT : out std_logic);
end component ADDER;
signal F0, F1 : std_logic_vector(WIDTH-1 downto 0);
signal COUT0, COUT1 : std_logic;
begin
ADD0: ADDER generic map( WIDTH => WIDTH)
port map (
CIN => '0' ,
A => A ,
B => B ,
F => F0 ,
COUT => COUT0 );
ADD1: ADDER generic map( WIDTH => WIDTH)
port map (
CIN => '1' ,
A => A ,
B => B ,
F => F1 ,
COUT => COUT1 );
COUT <= COUT1 when CIN = '1' else COUT0;
F <= F1 when CIN = '1' else F0;
end architecture CSA;
-- here's the configuration
configuration CSAC of ADDER is
for CSA
for all: ADDER
use entity work.ADDER(RCA);
end for;
end for;
end configuration CSAC;
| gpl-2.0 | 23c920b142f50dfceec4f5e14359309a | 0.562433 | 3.335727 | false | false | false | false |
nickg/nvc | test/regress/access4.vhd | 1 | 556 | entity access4 is
end entity;
architecture test of access4 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
begin
process is
variable p : int_vec_ptr;
begin
p := new int_vec(1 to 10);
p(1 to 3) := (1, 2, 3);
assert p(1 to 3) = (1, 2, 3);
assert p(2) = 2;
p.all(4 to 6) := (4, 5, 6);
assert p.all(4) = 4;
assert p'length = 10;
assert p.all'low = 1;
deallocate(p);
wait;
end process;
end architecture;
| gpl-3.0 | 88024cdcba96bcc44c059989c8b524f0 | 0.523381 | 3.141243 | false | false | false | false |
tgingold/ghdl | testsuite/synth/memmux01/memmux05.vhdl | 1 | 670 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux05 is
port (ad : std_logic;
val : std_logic_vector (1 downto 0);
dat : std_logic_vector (2 downto 0);
res : out std_logic_vector (2 downto 0));
end memmux05;
architecture behav of memmux05 is
begin
process (ad, val)
variable lo : natural;
variable t : std_logic_vector(2 downto 0);
begin
lo := to_integer(unsigned'(0 => ad));
t := dat;
t (lo + 1 downto lo) := val;
res <= t;
end process;
end behav;
-- Expected synthesis:
-- v15 := ad == 0 ? val : dat[1:0]
-- res[2:1] := ad == 1 ? val : {dat[2], v15[1]}
-- res[0] := v15[0]
| gpl-2.0 | 7329091977eaba96598a600f1ae48b95 | 0.585075 | 2.887931 | false | false | false | false |
nickg/nvc | test/sem/agg2008.vhd | 1 | 2,587 | entity agg2008 is
end entity;
architecture test of agg2008 is
begin
p1: process is
variable x : integer_vector(1 to 4);
variable y, z : integer_vector(1 to 2);
begin
x := ( integer_vector'(1, 2), integer_vector'(3, 4) ); -- OK
y := ( 5, 6 ); -- OK
z := ( 7, 8 ); -- OK
x := ( y, z ); -- OK
x := ( 1, 2, y, 3 ); -- OK
z := ( 1, 2, 1.2 ); -- Error
z := ( 1 => true, 2 => 5 ); -- Error
x := ( (1, 2), z ); -- OK
x := ( 1 => y, 2 => z ); -- Error
x := ( 1 to 4 => x ); -- OK
x := ( 1 to 2 => y, 3 to 4 => z ); -- OK
wait;
end process;
p2: process is
type int2d is array (natural range <>, natural range <>) of integer;
variable x : int2d(1 to 2, 1 to 2);
begin
x := ( (1, 2), (3, 4) ); -- OK
x := ( x, x ); -- Error
end process;
b2: block is
signal vec : bit_vector(7 downto 0);
begin
vec <= (3 downto 0 => "111", others => '0'); -- OK (at parse time)
end block;
p3: process is
type int_ptr is access integer;
type int_ptr_array is array (integer range <>) of int_ptr;
type int_ptr_array_ptr is access int_ptr_array;
variable x : int_ptr_array_ptr;
begin
x.all := (null, null, null); -- OK
end process;
p4: process is
type int_vec2 is array (natural range <>) of integer_vector; -- OK
constant a : int_vec2(1 to 2)(1 to 2) := ( -- OK
((1, 2), (3, 4)), ((5, 6), (7, 8)) );
begin
end process;
p5: process is
type unit_spec_t is record
name : string(1 to 3);
length : positive;
unit : time;
end record;
type unit_map_t is array (natural range <>) of unit_spec_t;
constant unit_map : unit_map_t := (
( "fs ", 2, fs ),
( "ps ", 2, ps ) ); -- OK
begin
end process;
p6: process is
type t_bv_array is array (natural range <>) of bit_vector;
subtype t_byte_array is t_bv_array(open)(7 downto 0); -- OK
variable v1 : t_byte_array; -- Error
variable v2 : t_byte_array(1 to 3); -- OK
variable b3 : integer(open); -- Error
variable v3 : t_byte_array(1 to 3)(4 to 5); -- Error
subtype t_error1 is t_byte_array(1 to 3)(4 to 5); -- Error
begin
end process;
end architecture;
| gpl-3.0 | e5e0a3be95ce9aab2982ba7a015b4015 | 0.451488 | 3.435591 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue301/src/reorder.vhd | 7 | 3,970 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Reorder twisted output due to windowing
--! @author Markus Fehrenz
--! @date 2011/05/12
--!
--! @details The windowing output is twisted.
--! The correct order is simply rebuilt by reversing
--! the output of each traceback unit.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
entity reorder is
port(
clk : in std_logic;
rst : in std_logic;
--
-- Traceback unit output, twisted order
--
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic;
s_axis_input_tlast : in std_logic;
s_axis_input_last_tuser : in std_logic;
s_axis_input_tready : out std_logic;
--
-- Viterbi decoder output, original (input) order.
--
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic;
m_axis_output_tlast : out std_logic;
m_axis_output_last_tuser : out std_logic; -- Last bit of one traceback window
m_axis_output_tready : in std_logic
);
end entity reorder;
architecture rtl of reorder is
-- used to store one reversed output of a traceback unit
signal buffer_sreg : unsigned(MAX_WINDOW_LENGTH - 1 downto 0);
signal buffer_cnt : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
signal buffer_end : integer range ENCODER_MEMORY_DEPTH downto 0;
signal send_output, last_window : boolean;
signal s_axis_input_tready_int : std_logic;
begin
s_axis_input_tready <= s_axis_input_tready_int;
s_axis_input_tready_int <= '1' when not(send_output) else
'0';
-- m_axis_output_tvalid <= '1' when send_output and m_axis_output_tready= '1' else
m_axis_output_tvalid <= '1' when send_output else
'0';
m_axis_output_tdata <= buffer_sreg(0);
m_axis_output_tlast <= '1' when buffer_cnt = ENCODER_MEMORY_DEPTH and last_window else
'0';
-- Reorder the global path given from an traceback unit with the help of a shift register.
pr_reorder : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
buffer_sreg <= (others => '0');
buffer_cnt <= (others => '0');
send_output <= false;
last_window <= false;
buffer_end <= 0;
m_axis_output_last_tuser <= '0';
else
-- store output of traceback unit
if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
if s_axis_input_tlast = '1' then
last_window <= true;
buffer_end <= ENCODER_MEMORY_DEPTH;
end if;
if s_axis_input_last_tuser = '1' then
send_output <= true;
buffer_sreg <= buffer_sreg(MAX_WINDOW_LENGTH - 2 downto 0) & s_axis_input_tdata;
else
buffer_sreg <= buffer_sreg(MAX_WINDOW_LENGTH - 2 downto 0) & s_axis_input_tdata;
buffer_cnt <= buffer_cnt + 1;
end if;
end if;
-- send reordered data to the output
if m_axis_output_tready = '1' and send_output then
buffer_sreg <= '0' & buffer_sreg(MAX_WINDOW_LENGTH - 1 downto 1);
-- Next transfer will be the last one of this window.
if buffer_cnt = 1 then
m_axis_output_last_tuser <= '1';
end if;
-- This was the last data transfer. Tailbits are cut off
if buffer_cnt = buffer_end then
send_output <= false;
last_window <= false;
buffer_end <= 0;
buffer_cnt <= (others => '0');
m_axis_output_last_tuser <= '0';
else
buffer_cnt <= buffer_cnt - 1;
end if;
end if;
end if;
end if;
end process pr_reorder;
end architecture rtl;
| gpl-2.0 | 1cd3aa42d19eb1ed9ddeb3d3021ee882 | 0.607305 | 3.206785 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_06.vhd | 4 | 2,586 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_06.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity multiprocessor is
end entity multiprocessor;
-- code from book
architecture instrumented of multiprocessor is
-- not in book
constant num_processors : positive := 2;
-- end not in book
shared variable bus_ifetch_count,
bus_read_count,
bus_write_count : natural := 0;
signal bus_request, bus_grant : bit_vector(0 to num_processors - 1);
-- . . . -- other signal declarations
begin
processor_array :
for processor_id in 0 to num_processors - 1 generate
processor : process is
-- . . .
begin
-- . . . -- initialize
loop
bus_request(processor_id) <= '1';
wait until bus_grant(processor_id) = '1';
bus_ifetch_count := bus_ifetch_count + 1;
-- . . . -- fetch instruction
bus_request(processor_id) <= '0';
-- . . . -- decode and execute instruction
-- not in book
wait until bus_grant(processor_id) = '0';
-- end not in book
end loop;
end process processor;
end generate processor_array;
arbiter : process is
begin
-- . . .
-- not in book
loop
for i in bus_request'range loop
if bus_request(i) = '1' then
bus_grant(i) <= '1' after 5 ns;
wait until bus_request(i) = '0';
bus_grant(i) <= '0' after 5 ns;
end if;
end loop;
wait for 5 ns;
end loop;
-- end not in book
end process arbiter;
-- . . . -- other processes for memory, etc
end architecture instrumented;
-- end code from book
| gpl-2.0 | d2121902c5733bfa8519b1d0539957fd | 0.590101 | 3.942073 | false | false | false | false |
nickg/nvc | test/regress/gensub4.vhd | 1 | 1,540 | package genfact is
function fact generic (type t;
function "*"(l, r : t) return t is <>;
function "-"(l, r : t) return t is <>;
function "<"(l, r : t) return boolean is <>;
one : t) (n : t) return t;
end package;
package body genfact is
function fact generic (type t;
function "*"(l, r : t) return t is <>;
function "-"(l, r : t) return t is <>;
function "<"(l, r : t) return boolean is <>;
one : t) (n : t) return t is
begin
if n < one then
return one;
else
return n * fact(n - ONE);
end if;
end function;
end package body;
-------------------------------------------------------------------------------
entity gensub4 is
end entity;
architecture test of gensub4 is
function fact_int is new work.genfact.fact
generic map (t => integer, one => 1);
function fact_real is new work.genfact.fact
generic map (t => real, one => 1.0);
signal s : integer;
signal r : real;
begin
p1: process is
begin
assert fact_int(1) = 1;
assert fact_int(5) = 120;
assert fact_real(1.0) = 1.0;
assert fact_real(4.0) = 24.0;
s <= 4;
r <= 2.0;
wait for 1 ns;
assert fact_int(s) = 24;
assert fact_real(r) = 2.0;
wait;
end process;
end architecture;
| gpl-3.0 | 0f5f56367ededd4347addba3986d239f | 0.443506 | 4.106667 | false | false | false | false |
tgingold/ghdl | testsuite/synth/fsm01/fsm_4s.vhdl | 1 | 953 | library ieee;
use ieee.std_logic_1164.all;
entity fsm_4s is
port (clk : std_logic;
rst : std_logic;
d : std_logic;
done : out std_logic);
end fsm_4s;
architecture behav of fsm_4s is
type state_t is (S0_1, S1_0, S2_0, S3_1);
signal s : state_t;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
s <= S0_1;
done <= '0';
else
-- Reset by default
s <= S0_1;
done <= '0';
case s is
when S0_1 =>
if d = '1' then
s <= S1_0;
end if;
when S1_0 =>
if d = '0' then
s <= S2_0;
end if;
when S2_0 =>
if d = '0' then
s <= S3_1;
end if;
when S3_1 =>
if d = '1' then
done <= '1';
end if;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 5b540fc0c0a0e3297654f143548ff168 | 0.410283 | 3.187291 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue418/tc749-3.vhdl | 1 | 2,667 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY tc749 IS
generic(
zero : integer := 0;
seven: integer := 7;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1
);
END tc749;
ARCHITECTURE arch OF tc749 IS
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C51 : record_cons_array := (C19,C20,C21);
constant C86: array_rec_cons (0 to 7) :=(others => C51);
signal V49 : array_rec_cons(zero to seven) ;
BEGIN
V49 <= C86;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert V49= C86 report " error in initializing S49" severity error;
wait;
END PROCESS TESTING;
END arch;
| gpl-2.0 | 7f190d510de98f120125bd7d34cd4953 | 0.6003 | 3.870827 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1319/repro2.vhdl | 1 | 638 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity repro2 is
port (
i : in std_ulogic_vector(1 downto 0);
o : out std_ulogic_vector (3 downto 0)
);
end entity repro2;
architecture behav of repro2 is
function func (v : std_ulogic_vector (1 downto 0)) return std_ulogic_vector is
variable res : std_ulogic_vector (3 downto 0);
begin
case v is
when "01" =>
res := "1111";
when others =>
res := "0000";
return "0000";
end case;
return res;
end;
begin
o <= func (i);
end architecture behav;
| gpl-2.0 | 46f12205d011dad16439afd35c5f2649 | 0.583072 | 3.486339 | false | false | false | false |
nickg/nvc | test/lower/cover.vhd | 1 | 729 | Library ieee;
use ieee.std_logic_1164.all;
entity cover is
end entity;
architecture test of cover is
signal s : integer;
signal l : std_logic;
signal l_vect : std_logic_vector(7 downto 0);
begin
p1: process is
variable v : integer;
begin
v := 1;
if s = 1 or s > 10 then
v := 2;
end if;
-- coverage off
s <= 1;
-- coverage on
wait;
end process;
p2: process
begin
l <= '0';
l_vect <= (others => '0');
wait for 1 ns;
l <= '1';
l_vect <= (others => '1');
wait for 1 ns;
l <= '0';
l_vect <= (others => '0');
wait;
end process;
end architecture;
| gpl-3.0 | 21e4c1bad9e2733783f2e7f6fbee5d33 | 0.470508 | 3.573529 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_04.vhd | 4 | 2,115 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_04.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_04 is
end entity ch_04_04;
----------------------------------------------------------------
architecture test of ch_04_04 is
begin
process_04_1_i : process is
-- code from book:
type A is array (1 to 4, 31 downto 0) of boolean;
-- end of code from book
variable free_map : bit_vector(1 to 10) := "0011010110";
variable count : natural;
begin
-- code from book (just the conditions):
assert A'left(1) = 1; assert A'low(1) = 1;
assert A'right(2) = 0 ; assert A'high(2) = 31;
assert A'length(1) = 4; assert A'length(2) = 32;
assert A'ascending(1) = true; assert A'ascending(2) = false;
assert A'low = 1; assert A'length = 4;
--
count := 0;
for index in free_map'range loop
if free_map(index) = '1' then
count := count + 1;
end if;
end loop;
-- end of code from book
wait;
end process process_04_1_i;
end architecture test;
| gpl-2.0 | 3a24e57cc929da743343040feecc16a0 | 0.549409 | 4.013283 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/lpm_counter_oe0.vhd | 1 | 4,811 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter_oe0.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter_oe0 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
updown : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_counter_oe0;
ARCHITECTURE SYN OF lpm_counter_oe0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
updown : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UNUSED",
lpm_port_updown => "PORT_USED",
lpm_type => "LPM_COUNTER",
lpm_width => 32
)
PORT MAP (
aclr => aclr,
clock => clock,
updown => updown,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "2"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_USED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: updown 0 0 0 0 INPUT NODEFVAL updown
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-- Retrieval info: CONNECT: @updown 0 0 0 0 updown 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter_oe0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| mit | 8c2963aaf5fabe5d4152c5946396c5e0 | 0.637913 | 3.590299 | false | false | false | false |
tgingold/ghdl | testsuite/synth/stmt01/forloop2.vhdl | 1 | 581 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity forloop2 is
port (vin: in STD_LOGIC_VECTOR (7 downto 0);
vout: out STD_LOGIC_VECTOR (3 downto 0);
clk: in STD_LOGIC);
end forloop2;
architecture behav of forloop2 is
begin
process (clk, vin)
variable count: unsigned (vout'range);
begin
if rising_edge (clk)
then
count := (others => '0');
for I in vin'range loop
count := count + unsigned'(0 => vin (i));
end loop;
vout <= std_logic_vector (count);
end if;
end process;
end behav;
| gpl-2.0 | 53581259ee9e270376e5ea2dd09d13f7 | 0.619621 | 3.397661 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue881/t87io.vhdl | 1 | 348 | entity t87io is
end;
use std.textio.all;
architecture behav of t87io is
constant t1 : time := 1 ns;
constant t2 : natural := time'pos (t1);
begin
assert t1 = 1000 ps;
process
variable v : natural;
begin
-- Time resolution must be ps
v := time'pos(ps);
assert v = 1 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | b62c522fc6b844f617c137f3dabe8168 | 0.643678 | 3.252336 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket20/morten1.vhdl | 3 | 2,164 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten is
end entity;
architecture foo of morten is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);
function to_bstring(sl : std_logic) return string is
begin
return "" & std_logic'image(sl)(2); -- "" & character to get string
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
begin
if slv_norm'length = 0 then
return "";
elsif slv_norm'length = 1 then
return to_bstring(slv_norm(1));
else -- slv_norm'length > 0
return to_bstring(slv_norm(1)) & to_bstring(slv_norm(2 to slv_norm'length));
end if;
end function;
begin
PRINT:
process (clk) is
variable line_v : line;
file out_file : text open write_mode is "out.txt";
begin
if rising_edge(clk) then
write(line_v, to_bstring(rst) & " " &
to_bstring(std_logic_vector(cnt_1)) & " " &
to_bstring(std_logic_vector(cnt_3))
);
writeline(out_file, line_v);
end if;
end process;
COUNTER1:
process (clk,rst)
begin
if rst = '1' then
cnt_1 <= (others => '0');
elsif rising_edge(clk) then
cnt_1 <= cnt_1 + 1;
end if;
end process;
COUNTER3:
process (clk,rst)
begin
if rst = '1' then
cnt_3 <= (others => '0');
elsif rising_edge(clk) then
cnt_3 <= cnt_3 + 3;
end if;
end process;
RESET:
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 210 ns then
wait;
end if;
end process;
end architecture; | gpl-2.0 | b47a62df67e5bd502ce7019ff1ea062b | 0.53281 | 3.582781 | false | false | false | false |
nickg/nvc | test/regress/array10.vhd | 1 | 855 | entity array10 is
end entity;
architecture test of array10 is
type int_vec is array (natural range <>) of integer;
type int_vec_ptr is access int_vec;
procedure do_stuff (variable p : inout int_vec_ptr;
variable r : inout integer) is
constant orig : int_vec(1 to p'length) := p.all;
constant len : integer := p'length;
begin
deallocate(p);
p := new int_vec'(1, 2, 3); -- Changes p'length
r := 0;
for i in 1 to len loop
r := r + orig(i);
end loop;
end procedure;
begin
p1: process is
variable p : int_vec_ptr;
variable r : integer;
begin
p := new int_vec'(1, 2, 3, 4, 5);
do_stuff(p, r);
assert r = 15;
assert p.all = (1, 2, 3);
wait;
end process;
end architecture;
| gpl-3.0 | 43c9dd5340487a0785eb2f5faa01854c | 0.528655 | 3.577406 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug074/repro.vhdl | 1 | 559 | package pkg is
procedure proc (a : bit_vector; r : out bit);
end pkg;
package body pkg is
procedure proc (a : bit_vector; r : out bit)
is
variable v1, v2 : bit_vector (1 to 2 * a'length);
begin
v1 := a & a;
v2 := a & a;
r := '0';
end proc;
end pkg;
entity repro is
end repro;
architecture behav of repro is
begin
process
variable v : bit;
constant c : bit_vector (1 to 1024) := (1 => '1', others => '0');
begin
loop
work.pkg.proc (c, v);
wait for 1 ns;
end loop;
end process;
end behav;
| gpl-2.0 | bd8bcac87334852c114618023b00e570 | 0.568873 | 3.088398 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue626/top.vhdl | 1 | 774 | library ieee;
use ieee.std_logic_1164.all;
entity inc_ent is
generic (
works : integer;
vec : std_logic_vector);
end entity;
architecture default of inc_ent is
begin
assert false report integer'image(works) & " " & integer'image(vec'length);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity top_ent is end entity;
architecture default of top_ent is
constant foo_v : std_logic_vector(0 to 12) := (others => '1');
begin
g : for ix in 0 to 4 generate
constant foo_v : std_logic_vector(0 to ix) := (others => '1');
begin
inst : entity work.inc_ent
generic map (
works => 0,
vec => (0 to ix => '1')
);
inst2 : entity work.inc_ent
generic map (
works => 1,
vec => foo_v
);
end generate;
end architecture;
| gpl-2.0 | fe7def2e542202c346c48f40b53edb89 | 0.648579 | 2.942966 | false | false | false | false |
nickg/nvc | test/regress/signal15.vhd | 1 | 1,449 | -- VHDL 2008 element resolution
entity signal15 is
end entity;
architecture test of signal15 is
type my_utype is (a, b, c);
type my_utype_vector is array (natural range <>) of my_utype;
type my_utype_vector_vector is array (natural range <>) of my_utype_vector(1 to 3);
function resolved (s : my_utype_vector) return my_utype;
subtype my_type is resolved my_utype;
subtype my_type_vector is (resolved) my_utype_vector;
subtype my_type_vector_vector is ((resolved)) my_utype_vector_vector;
function resolved (s : my_utype_vector) return my_utype is
variable result : my_utype := s(s'low);
begin
for i in s'range loop
if my_utype'pos(s(i)) > my_utype'pos(result) then
result := s(i);
end if;
end loop;
return result;
end function;
signal x : my_type;
signal y : my_type_vector(1 to 3);
signal z : my_type_vector_vector(1 to 3);
begin
x <= b;
y <= (a, b, c);
z <= (others => (a, b, c));
process is
begin
x <= a;
wait for 1 ns;
assert x = b;
x <= c;
wait for 1 ns;
assert x = c;
y <= (b, b, b);
wait for 1 ns;
assert y = (b, b, c);
z <= ((a, a, a), (b, b, b), (c, c, c));
wait for 1 ns;
assert z = ((a, b, c), (b, b, c), (c, c, c));
wait for 1 ns;
wait;
end process;
end architecture;
| gpl-3.0 | 3c12a0836211df176b99988cb23224be | 0.536232 | 3.300683 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue155/failure.vhdl | 2 | 2,801 | library ieee;
use ieee.std_logic_1164.all;
package stream is
constant SYNC_RESET : boolean:=true;
subtype valid_t is std_logic;
subtype ready_t is std_logic;
function state_log2(x : positive) return integer;
pure function ceil_log2(x : positive) return integer;
function get(str : valid_t) return std_logic;
function b2std(x:boolean) return std_logic;
end package;
package body stream is
function b2std(x:boolean) return std_logic is
begin
if x then return '1';
else return '0';
end if;
end function;
function get(str : valid_t) return std_logic is
begin
return std_logic(str);
end get;
function state_log2(x : positive) return integer is
variable r : integer;
begin
if x=1 then
r := 1;
else
r := ceil_log2(x);
end if;
return r;
end state_log2;
pure function ceil_log(x : positive; b : positive) return integer is
begin
for r in 0 to 30 loop
if (x <=b**r) then
return r;
end if;
end loop;
return -1;
end ceil_log;
pure function ceil_log2(x : positive) return integer is
begin
return ceil_log(x,2);
end ceil_log2;
end package body stream;
library ieee;
use ieee.std_logic_1164.all;
use work.stream.all;
use ieee.numeric_std.all;
entity tdm_counter is
generic
(
TDM : positive := 1
);
port
(reset : in std_logic;
clock : in std_logic;
clock_en : in std_logic;
valid : in valid_t;
ready : in ready_t;
counter : out std_logic_vector(state_log2(TDM)-1 downto 0)
);
end tdm_counter;
architecture rtl of tdm_counter is
-- just declaring the counter here works
--signal counter_u: unsigned(ceil_log2(TDM)-1 downto 0);
begin -- rtl
U_SIMPLE: if TDM = 1 generate
counter <= (others=>'0');
end generate U_SIMPLE;
U_COMPLEX: if TDM /= 1 generate
signal enable_i : std_logic;
signal counter_u: unsigned(ceil_log2(TDM)-1 downto 0);
begin
process(reset,clock)
-- also expanding do_reset and removing the procedure works
procedure do_reset is
begin
counter_u <= to_unsigned(0, counter_u'length);
end procedure;
begin
if not(SYNC_RESET) and reset='1' then
do_reset;
elsif rising_edge(clock) then
if SYNC_RESET and reset='1' then
do_reset;
elsif clock_en='1' then
if get(valid)='1' and get(ready)='1' then
if enable_i='1' then
counter_u <= to_unsigned(0, counter_u'length);
else
counter_u <= counter_u+1;
end if;
end if;
end if;
end if;
end process;
counter <= std_logic_vector(counter_u);
enable_i <= b2std(counter_u = TDM-1) and get(valid) and get(ready);
end generate U_COMPLEX;
end rtl;
| gpl-2.0 | 2b8284eaa02d939d7708521ab13da979 | 0.617994 | 3.391041 | false | false | false | false |
nickg/nvc | test/regress/record29.vhd | 1 | 526 | entity record29 is
end entity;
architecture test of record29 is
type rec is record
x : bit_vector;
end record;
signal s : rec(x(1 to 3));
begin
main: process is
begin
assert s.x = "000";
assert s = (x => "000");
s.x <= "101";
wait for 1 ns;
assert s.x = "101";
assert s = (x => "101");
s <= (x => "111");
wait for 1 ns;
assert s.x = "111";
assert s = (x => "111");
wait;
end process;
end architecture;
| gpl-3.0 | 86532a632859b2b19c4d57f037a2c7a4 | 0.475285 | 3.460526 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1988.vhd | 4 | 6,771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1988.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01988ent IS
END c07s02b02x00p02n01i01988ent;
ARCHITECTURE c07s02b02x00p02n01i01988arch OF c07s02b02x00p02n01i01988ent IS
BEGIN
TESTING: PROCESS
variable A : bit_vector (1 to 32);
variable B : bit_vector (32 downto 1);
variable C : bit_vector (15 downto 0);
variable D : bit_vector (0 to 15);
variable E : bit_vector (0 to 47);
variable F : bit_vector (47 downto 0);
BEGIN
A := x"ffffffff";
B := x"00000000";
C := x"ffff";
D := x"0000";
E := x"ffffffffffff";
F := x"000000000000";
assert NOT( A = A and
A /= B and
A /= C and
A /= D and
A /= E and
A /= F and
B /= A and
B = B and
B /= C and
B /= D and
B /= E and
B /= F and
C /= A and
C /= B and
C = C and
C /= D and
C /= E and
C /= F and
D /= A and
D /= B and
D /= C and
D = D and
D /= E and
D /= F and
E /= A and
E /= B and
E /= C and
E /= D and
E = E and
E /= F and
F /= A and
F /= B and
F /= C and
F /= D and
F /= E and
F = F and
A <= A and
A > B and
A > C and
A > D and
A < E and
A > F and
B < A and
B <= B and
B < C and
B > D and
B < E and
B < F and
C < A and
C > B and
C <= C and
C > D and
C < E and
C > F and
D < A and
D < B and
D < C and
D <= D and
D < E and
D < F and
E > A and
E > B and
E > C and
E > D and
E <= E and
E > F and
F < A and
F > B and
F < C and
F > D and
F < E and
F <= F)
report "***PASSED TEST: c07s02b02x00p02n01i01988"
severity NOTE;
assert ( A = A and
A /= B and
A /= C and
A /= D and
A /= E and
A /= F and
B /= A and
B = B and
B /= C and
B /= D and
B /= E and
B /= F and
C /= A and
C /= B and
C = C and
C /= D and
C /= E and
C /= F and
D /= A and
D /= B and
D /= C and
D = D and
D /= E and
D /= F and
E /= A and
E /= B and
E /= C and
E /= D and
E = E and
E /= F and
F /= A and
F /= B and
F /= C and
F /= D and
F /= E and
F = F and
A <= A and
A > B and
A > C and
A > D and
A < E and
A > F and
B < A and
B <= B and
B < C and
B > D and
B < E and
B < F and
C < A and
C > B and
C <= C and
C > D and
C < E and
C > F and
D < A and
D < B and
D < C and
D <= D and
D < E and
D < F and
E > A and
E > B and
E > C and
E > D and
E <= E and
E > F and
F < A and
F > B and
F < C and
F > D and
F < E and
F <= F)
report "***FAILED TEST: c07s02b02x00p02n01i01988 - Relational operators truth table test for data type of Bit_vector failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01988arch;
| gpl-2.0 | aa5b58184789d6b7abef67ad2580cf7f | 0.305272 | 4.734965 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_03.vhd | 4 | 3,385 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_03.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_03 is
end entity ch_04_03;
----------------------------------------------------------------
architecture test of ch_04_03 is
subtype coeff_ram_address is integer range 0 to 63;
-- code from book:
type coeff_array is array (coeff_ram_address) of real;
-- end of code from book
begin
process_04_1_c : process is
-- code from book:
type point is array (1 to 3) of real;
constant origin : point := (0.0, 0.0, 0.0);
variable view_point : point := (10.0, 20.0, 0.0);
-- end of code from book
begin
wait;
end process process_04_1_c;
process_04_1_d : process is
type point is array (1 to 3) of real;
-- code from book:
variable view_point : point := (1 => 10.0, 2 => 20.0, 3 => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_d;
process_04_1_e : process is
-- code from book:
variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, 3 to 63 => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_e;
process_04_1_f : process is
-- code from book:
variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, others => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_f;
process_04_1_g : process is
-- code from book:
variable coeff : coeff_array := (0 | 2 => 1.6, 1 => 2.3, others => 0.0);
-- end of code from book
begin
wait;
end process process_04_1_g;
process_04_1_h : process is
-- code from book:
-- error: Associations in array aggregate must be all named or all positional
-- variable coeff : coeff_array := (1.6, 2.3, 2 => 1.6, others => 0.0); -- illegal
-- end of code from book
begin
wait;
end process process_04_1_h;
end architecture test;
| gpl-2.0 | 0aa423f6053c2604d10ad40b4252e73d | 0.492762 | 4.204969 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug098/loopy.vhdl | 1 | 755 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity loopy is
end loopy;
architecture foo of loopy is
constant R: integer := 4;
constant L: integer := 16;
constant W: integer := 16;
constant M: integer := 4;
type t_reg_x is array ( 0 to L-1 ) of signed( W-1 downto 0 );
signal reg_x : t_reg_x := ( others => ( others => '0' ) );
type t_mux_in_x is array ( 0 to L - 1 ) of signed( W - 1 downto 0 );
signal mux_in_x: t_mux_in_x := ( others => ( others => '0') );
begin
process (reg_x)
begin
for r in 0 to R-1 loop
for m in 0 to M-1 loop
mux_in_x(r * M + m) <= reg_x(m * R + r);
end loop;
end loop;
end process;
end architecture;
| gpl-2.0 | 174eddd063e54242965ffa4b7057774f | 0.545695 | 2.996032 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd | 4 | 2,010 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity timer is
port ( signal trigger_n, reset : in std_ulogic; signal q : out std_ulogic;
terminal rc_ext : electrical );
end entity timer;
----------------------------------------------------------------
architecture behavioral of timer is
constant half_vdd : real := 2.5;
constant clamp_on_resistance : real := 0.01;
constant clamp_off_resistance : real := 10.0E6;
quantity v_rc_ext across i_clamp through rc_ext to electrical_ref;
signal q_n : std_ulogic := '1';
begin
if q_n = '1' use
i_clamp == v_rc_ext / clamp_on_resistance;
else
i_clamp == v_rc_ext / clamp_off_resistance;
end use;
timer_state : process ( trigger_n, reset, v_rc_ext'above(half_vdd) ) is
begin
if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
q <= '0'; q_n <= '1';
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
end if;
end process timer_state;
clamp_change : process ( q_n ) is
begin
break;
end process clamp_change;
end architecture behavioral;
| gpl-2.0 | ab96469fb17193c6c6098941738d6045 | 0.639303 | 3.722222 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1125/etest.vhdl | 1 | 580 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity etest is
end;
architecture atest of etest is
function foo(a : std_logic_vector) return unsigned is
variable v : unsigned(3 downto 0):=(others=>'0') ;
begin
v := v + unsigned(a(1 downto 1));
return v;
end;
begin
test : process
variable v : std_logic_vector(3 downto 0) ;
variable w : std_logic_vector(0 to 3);
variable x : unsigned(3 downto 0) ;
begin
x := foo(w);
-- x := x + unsigned(w(0 downto 0)) ;
wait;
end process ; -- test
end;
| gpl-2.0 | 44e77879e2571035097c55df3f15bd90 | 0.606897 | 3.20442 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1044/ent.vhdl | 1 | 384 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
generic (
VAL : real := 1.5
);
port (
lt : out std_logic
);
end;
architecture a of ent is
constant fmul : real := val * 5.0;
constant fneg : real := -val;
constant fid : real := +val;
constant fabs : real := abs val;
constant fexp : real := val ** 2;
begin
lt <= '1' when VAL < 1.5 else '0';
end;
| gpl-2.0 | 25728b825e96a1bb5e14cb65172f6183 | 0.585938 | 2.742857 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_dc_xhuff_tbl_bits.vhd | 2 | 1,451 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_xhuff_tbl_bits;
architecture augh of p_jinfo_dc_xhuff_tbl_bits is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 8c5074d137f55ad76422f466ea37b8fd | 0.674707 | 2.856299 | false | false | false | false |
nickg/nvc | test/regress/default1.vhd | 5 | 908 | entity default1 is
end entity;
architecture test of default1 is
signal s : positive;
begin
process is
type mat2x2 is array (1 to 2, 1 to 2) of natural;
type int_array10 is array (1 to 10) of positive;
type int_array5 is array (5 to 7) of positive;
variable x : integer;
variable v : bit_vector(1 to 3);
variable m : mat2x2;
variable p : int_array10;
variable q : int_array5;
begin
assert s = 1;
assert x = integer'left;
assert v = ('0', '0', '0');
assert m = ((0, 0), (0, 0));
assert p = (1 to 10 => 1);
assert q = (5 to 7 => 1);
assert p'left = 1;
assert p'right = 10;
assert q'left = 5;
assert q'right = 7;
assert q'length = 3;
s <= 4; -- FIXME
wait;
end process;
end architecture;
| gpl-3.0 | 54edc8ab77014be10af683d0ba6e2c80 | 0.5 | 3.632 | false | false | false | false |
nickg/nvc | test/regress/issue420.vhd | 1 | 923 | package globals is
signal COMMAND_FILE_ENDIAN : bit;
signal COMMAND_FILE_NAME : string(1 to 1024);
signal COMMAND_FILE_NAMELEN : integer;
signal COMMAND_FILE_TARGET : integer;
signal COMMAND_FILE_START : bit;
signal COMMAND_FILE_ACK : bit;
procedure change (signal what : out bit);
end package globals;
package body globals is
procedure change (signal what : out bit) is
begin
what <= '1';
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue420 is
end entity;
use work.globals.all;
architecture test of issue420 is
begin
check: process is
begin
assert COMMAND_FILE_ACK = '0';
assert COMMAND_FILE_NAME = (1 to 1024 => NUL);
change(COMMAND_FILE_ACK);
wait for 1 ns;
assert COMMAND_FILE_ACK = '1';
wait;
end process;
end architecture;
| gpl-3.0 | 2115df8319571fb2444a668c79c1421a | 0.593716 | 4.030568 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1277/issue.vhdl | 1 | 678 | library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (lo_1 : out std_logic_vector (1 downto 0);
lo_2 : out std_logic_vector (1 downto 0));
end entity issue;
architecture beh of issue is
function fun (arg : integer) return integer is
begin
return arg - 1;
end function;
signal hi_c : std_logic_vector (15-1 downto 1);
signal hi_f : std_logic_vector (fun(15) downto 1);
signal foobar_c : std_logic_vector (15 downto 0) := (others => '0');
signal foobar_f : std_logic_vector (fun(16) downto 0) := (others=>'0');
begin
(hi_c, lo_1) <= foobar_f; -- works
(hi_f, lo_2) <= foobar_c; -- crashes
end architecture;
| gpl-2.0 | fec09da06a20985d861a6ac22170e558 | 0.620944 | 3.153488 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue14/repro.vhdl | 2 | 372 | library ieee;
use ieee.std_logic_1164.all;
entity repro is
end repro;
architecture behav of repro is
begin
process
variable z : std_ulogic_vector (1 to 2) := "00";
variable r : std_ulogic;
begin
r := z ?= "LL";
assert r = '1';
z := "--";
r := z ?= "00"; -- One warning
r := z ?= "--"; -- Two warning
wait;
end process;
end behav;
| gpl-2.0 | e39c854b05ed1779f7ae6b9c206e2370 | 0.553763 | 3.206897 | false | false | false | false |
tgingold/ghdl | testsuite/synth/fsm01/tb_fsm_6s.vhdl | 1 | 903 | entity tb_fsm_6s is
end tb_fsm_6s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_6s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_6s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"100101_100101_110001";
constant res : std_logic_vector := b"000001_000001_000000";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | 3942f6b58b1be2a9fadf0081da207fc0 | 0.572536 | 3.319853 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue238/assign1.vhdl | 2 | 354 | entity assign1 is
end;
use work.pkg.all;
architecture behav of assign1 is
begin
process
variable v : rec_4;
begin
v.a := 5;
assert v.a = 5 severity failure;
v.s := "Good";
assert v.a = 5 severity failure;
assert v.s = "Good" severity failure;
assert false report "ok" severity note;
wait;
end process;
end behav;
| gpl-2.0 | e11995dbca223e5ab04672f81e15e7be | 0.638418 | 3.308411 | false | false | false | false |
tgingold/ghdl | testsuite/synth/case01/case06.vhdl | 1 | 325 | library ieee;
use ieee.std_logic_1164.all;
entity case06 is
port (
a : in std_logic;
b : out std_logic
);
end entity;
architecture a of case06 is
begin
process(a)
begin
case a is
when '0' =>
b <= '0';
when 'L' =>
b <= '1';
when others =>
b <= 'Z';
end case;
end process;
end architecture;
| gpl-2.0 | 6cce3ed66181e264bd0b1417f271345f | 0.581538 | 2.539063 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_comps_info_quant_tbl_no.vhd | 2 | 1,515 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_quant_tbl_no is
port (
wa0_data : in std_logic_vector(1 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(1 downto 0);
wa0_en : in std_logic
);
end p_jinfo_comps_info_quant_tbl_no;
architecture augh of p_jinfo_comps_info_quant_tbl_no is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic_vector(1 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-');
end architecture;
| gpl-2.0 | 0efa982f7fdac67e12e0636bfb6b531e | 0.673267 | 2.853107 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/arr04.vhdl | 1 | 522 | library ieee;
use ieee.std_logic_1164.all;
entity arr04 is
port (clk : in std_logic;
rst : std_logic;
sel_i : std_logic;
v : std_logic;
res : out std_logic_vector(0 to 1));
end arr04;
architecture behav of arr04 is
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
res <= "00";
else
if sel_i = '0' then
res (0) <= v;
else
res (1) <= v;
end if;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 24661c20388f8077789f3194f6c4ec8f | 0.515326 | 3.182927 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue626/repro.vhdl | 1 | 517 | entity inc is
generic (v : natural; vec : bit_vector);
end entity;
architecture default of inc is
begin
assert vec'left = 0 severity failure;
assert vec'right = v severity failure;
assert false report integer'image(vec'right);
end architecture;
entity repro is end entity;
architecture default of repro is
begin
g : for ix in 0 to 4 generate
begin
inst : entity work.inc
generic map (v => ix,
vec => (0 to ix => '1'));
end generate;
end architecture;
| gpl-2.0 | 2ec2686f6a78a13c23d6509068913b73 | 0.646035 | 3.82963 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-frk.vhd | 4 | 3,247 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-frk.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
architecture fork of test_bench is
use qsim.qsim_types.all;
use random.random.all;
constant num_outputs : positive := 4;
constant probabilities : probability_vector(1 to num_outputs - 1)
:= ( 0.2, 0.4, 0.1 );
signal source_arc : arc_type;
signal fork_arc : arc_vector(1 to num_outputs);
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(1),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => source_arc,
info_detail => info_detail );
fork1 : entity qsim.fork(behavior)
generic map ( name => "fork1",
probabilities => probabilities,
seed => sample_seeds(2),
time_unit => ns,
info_file_name => "fork1.dat" )
port map ( in_arc => source_arc,
out_arc => fork_arc,
info_detail => info_detail );
source_monitor : process is
variable L : line;
begin
wait on source_arc;
write(L, string'("source_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, source_arc.token, ns);
writeline(output, L);
end process source_monitor;
sinks : for index in 1 to num_outputs generate
constant index_string : string := integer'image(index);
begin
sink : entity qsim.sink(behavior)
generic map ( name => "sink" & index_string,
time_unit => ns,
info_file_name => "sink" & index_string & ".dat" )
port map ( in_arc => fork_arc(index),
info_detail => info_detail );
sink_monitor : process
variable L : line;
begin
wait on fork_arc(index);
write(L, string'("sink_monitor(" & index_string & "): at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, fork_arc(index).token, ns);
writeline(output, L);
end process sink_monitor;
end generate sinks;
end architecture fork;
| gpl-2.0 | 2deee0e1b28e376647cb09c5663af818 | 0.581152 | 3.930993 | false | false | false | false |
nickg/nvc | test/regress/array13.vhd | 1 | 1,561 | package pack is
constant LENGTH : natural;
constant C_MAX_VVC_INSTANCE_NUM : natural;
end package;
package body pack is
constant LENGTH : natural := 8;
constant C_MAX_VVC_INSTANCE_NUM : natural := 8;
end package body;
-------------------------------------------------------------------------------
entity array13 is
end entity;
use work.pack.all;
architecture a of array13 is
-- Reduced from crash in UVVM
type t_channel is (
NA,
ALL_CHANNELS,
RX, TX );
subtype t_sub_channel is t_channel range RX to TX;
type t_base_transaction is record
x : integer;
y : bit_vector(1 to LENGTH);
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
x => 1, y => (others => '0') );
type t_transaction_group is record
bt : t_base_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT );
type t_uart_transaction_group_array is array (t_sub_channel range <>, natural range <>) of t_transaction_group;
shared variable sv : t_uart_transaction_group_array(t_sub_channel'left to t_sub_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => (others => C_TRANSACTION_GROUP_DEFAULT));
begin
check: process is
begin
assert sv(RX, 1).bt.x = 1;
sv(RX, 1).bt.y := X"ab";
wait for 1 ns;
assert sv(RX, 1).bt.x = 1;
assert sv(RX, 1).bt.y = X"ab";
wait;
end process;
end architecture;
| gpl-3.0 | 87bc278284fa22e7546f50ba78063581 | 0.584881 | 3.638695 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1211/delay_ul.vhdl | 1 | 878 | library ieee;
use ieee.std_logic_1164.all;
entity delay_ul is
generic (
STAGES : natural := 4;
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic;
Enable : in std_ulogic;
Sig_in : in std_ulogic;
Sig_out : out std_ulogic
);
end entity;
architecture rtl of delay_ul is
begin
gt: if STAGES > 0 generate
reg: process(Clock, Reset, Enable)
variable pl_regs : std_ulogic_vector(1 to STAGES);
begin
if Reset = RESET_ACTIVE_LEVEL then
pl_regs := (others => '0');
elsif rising_edge(Clock) and Enable = '1' then
if STAGES = 1 then
pl_regs(1) := Sig_in;
else
pl_regs := Sig_in & pl_regs(1 to pl_regs'high-1);
end if;
end if;
Sig_out <= pl_regs(pl_regs'high);
end process;
end generate;
gf: if STAGES = 0 generate
Sig_out <= Sig_in;
end generate;
end architecture;
| gpl-2.0 | 27cc9680d1626a627123dc49e3e35e47 | 0.629841 | 2.752351 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc758.vhd | 4 | 7,999 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc758.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00758pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector:= (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector:= (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector:= (1,2,3,4);
constant C18 : positive_vector:= (1,2,3,4);
end c01s01b01x01p05n02i00758pkg;
use work.c01s01b01x01p05n02i00758pkg.ALL;
ENTITY c01s01b01x01p05n02i00758ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen : integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen10 : string := "shishir";
Cgen11 : bit_vector := B"0011";
Cgen12 : boolean_vector := (true,false);
Cgen13 : severity_level_vector := (note,error);
Cgen14 : integer_vector := (1,2,3,4);
Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Cgen17 : natural_vector := (1,2,3,4);
Cgen18 : positive_vector := (1,2,3,4) );
port(
Vgen1 : boolean := true;
Vgen2 : bit := '1';
Vgen3 : character := 's';
Vgen4 : severity_level:= note;
Vgen5 : integer := 3;
Vgen6 : real := 3.0;
Vgen7 : time := 3 ns;
Vgen8 : natural := 1;
Vgen9 : positive := 1;
Vgen10 : string := "shishir";
Vgen11 : bit_vector := B"0011";
Vgen12 : boolean_vector:= (true,false);
Vgen13 : severity_level_vector := (note,error);
Vgen14 : integer_vector:= (1,2,3,4);
Vgen15 : real_vector := (1.0,2.0,3.0,4.0);
Vgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Vgen17 : natural_vector:= (1,2,3,4);
Vgen18 : positive_vector:= (1,2,3,4)
);
END c01s01b01x01p05n02i00758ent;
ARCHITECTURE c01s01b01x01p05n02i00758arch OF c01s01b01x01p05n02i00758ent IS
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error;
assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error;
assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error;
assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error;
assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error;
assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error;
assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error;
assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error;
assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***PASSED TEST: c01s01b01x01p05n02i00758"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***FAILED TEST: c01s01b01x01p05n02i00758 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00758arch;
| gpl-2.0 | 4d5985a7e3f95c51bebb2e25d18bef9d | 0.585823 | 3.7274 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue328/repro_irqc.vhdl | 1 | 1,551 | entity irqc_tb is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Test case architecture
architecture func of irqc_tb is
type t_sbi_if is record
cs : std_logic; -- to dut
addr : unsigned; -- to dut
rena : std_logic; -- to dut
wena : std_logic; -- to dut
wdata : std_logic_vector; -- to dut
ready : std_logic; -- from dut
rdata : std_logic_vector; -- from dut
end record;
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if is
variable result : t_sbi_if( addr(addr_width - 1 downto 0),
wdata(data_width - 1 downto 0),
rdata(data_width - 1 downto 0));
begin
result.cs := '0';
result.rena := '0';
result.wena := '0';
result.addr := (others => '0');
result.wdata := (others => '0');
result.ready := 'Z';
result.rdata := (others => 'Z');
return result;
end function;
signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
procedure write (signal s : inout t_sbi_if) is
begin
s.cs <= '1';
end write;
begin
process
begin
write(sbi_if);
wait for 1 ns;
assert sbi_if.rdata = (7 downto 0 => 'Z');
assert sbi_if.addr = (2 downto 0 => '0');
assert sbi_if.wdata = (7 downto 0 => '0');
wait;
end process;
sbi_if.rdata <= (others => '0');
end func;
| gpl-2.0 | bb95140c530286724ec6be4bff73da79 | 0.539652 | 3.307036 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/util/src_sine.vhd | 4 | 1,999 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.MATH_REAL.all;
library IEEE_proposed; use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity src_sine is
generic ( freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port ( quantity output : out real );
end entity src_sine;
architecture ideal of src_sine is
-- Declare quantity for phase in radians (calculated below)
quantity phase_rad : real;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi * ac_phase / 360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * now + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
output == offset + amplitude * sin(phase_rad) * exp(-now * df);
else
output == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
| gpl-2.0 | 28943fbd1ddc254eb03c282bc682ced9 | 0.664832 | 3.927308 | false | false | false | false |
nickg/nvc | test/parse/array.vhd | 1 | 1,127 | package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
type chars is (A, B, C);
type char_counts is array (chars) of integer;
type two_d is array (1 to 3, 4 to 6) of integer;
type ab_chars is array (chars range A to B) of integer;
type it is array (integer range ten_ints'range) of bit;
end package;
entity e is end entity;
use work.p.all;
architecture a of e is
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
signal c : char_counts;
signal t : two_d;
signal u : ten_ints := ( 1 | 2 | 3 => 4, others => 2);
signal v : ten_ints := ( 1 ! 2 ! 3 => 4, others => 2);
begin
process is
variable k : int_array(1 to 5);
begin
x(0) <= 1;
y(2) <= n(2);
y(3)(5) <= n(2)(1);
x(1 to 3) <= z(1 to 3);
k := (x'range => 5);
k := (x'reverse_range => 3);
end process;
end architecture;
| gpl-3.0 | ad2bdd06938bf52604829791ae046c9d | 0.532387 | 2.98939 | false | false | false | false |
nickg/nvc | test/regress/ieee6.vhd | 1 | 1,078 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sub is
port (
result : out std_ulogic_vector(3 downto 0);
in1 : in std_ulogic_vector(3 downto 0) );
end entity;
architecture test of sub is
signal in2 : std_ulogic_vector(2 downto 0);
begin
assert in1(1 downto 0) = "00";
in2 <= "001";
result <= std_ulogic_vector(unsigned(in1) + unsigned(in2));
end architecture;
-------------------------------------------------------------------------------
entity ieee6 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of ieee6 is
signal result : std_ulogic_vector(3 downto 0);
signal in1 : std_ulogic_vector(1 downto 0);
begin
uut: entity work.sub
port map (
result => result,
in1(3 downto 2) => std_ulogic_vector(in1),
in1(1 downto 0) => "00" );
stim: process is
begin
in1 <= "01";
wait for 1 ns;
assert result = X"5";
wait;
end process;
end architecture;
| gpl-3.0 | de3984418ff5a7fba6110d33d24c1250 | 0.561224 | 3.522876 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth34/tb_repro_nat.vhdl | 1 | 587 | entity tb_repro_nat is
end tb_repro_nat;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_repro_nat is
signal clk : std_logic;
signal a : natural;
signal b : natural;
begin
dut: entity work.repro_nat
port map (
clk => clk, a => a, b => b);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= 125;
pulse;
assert b = 125 severity failure;
a <= 7689;
pulse;
assert b = 7689 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | ba50e08c2f911035ad23b590d7c90fcf | 0.586031 | 3.354286 | false | false | false | false |
nickg/nvc | test/regress/issue544.vhd | 1 | 8,696 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package test_pkg is
type t_axi_wr_slave_in_if is record
awid : std_logic_vector;
awaddr : std_logic_vector;
awlen : std_logic_vector(7 downto 0);
awsize : std_logic_vector(2 downto 0);
awburst : std_logic_vector(1 downto 0);
awlock : std_logic;
awcache : std_logic_vector(3 downto 0);
awprot : std_logic_vector(2 downto 0);
awqos : std_logic_vector(3 downto 0);
awregion : std_logic_vector(3 downto 0);
awuser : std_logic_vector;
awvalid : std_logic;
wdata : std_logic_vector;
wstrb : std_logic_vector;
wlast : std_logic;
wuser : std_logic_vector;
wvalid : std_logic;
bready : std_logic;
end record;
type t_axi_wr_slave_out_if is record
awready : std_logic;
wready : std_logic;
bid : std_logic_vector;
bresp : std_logic_vector(1 downto 0);
buser : std_logic_vector;
bvalid : std_logic;
end record;
type t_axi_rd_slave_in_if is record
arid : std_logic_vector;
araddr : std_logic_vector;
arlen : std_logic_vector(7 downto 0);
arsize : std_logic_vector(2 downto 0);
arburst : std_logic_vector(1 downto 0);
arlock : std_logic;
arcache : std_logic_vector(3 downto 0);
arprot : std_logic_vector(2 downto 0);
arqos : std_logic_vector(3 downto 0);
arregion : std_logic_vector(3 downto 0);
aruser : std_logic_vector;
arvalid : std_logic;
rready : std_logic;
end record;
type t_axi_rd_slave_out_if is record
arready : std_logic;
rid : std_logic_vector;
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rlast : std_logic;
ruser : std_logic_vector;
rvalid : std_logic;
end record;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_pkg.all;
entity test2 is
port (
wr_port_in : in t_axi_wr_slave_in_if;
wr_port_out : out t_axi_wr_slave_out_if;
rd_port_in : in t_axi_rd_slave_in_if;
rd_port_out : out t_axi_rd_slave_out_if
);
end entity test2;
architecture beh of test2 is
begin
end architecture beh;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_pkg.all;
entity issue544 is
end entity;
architecture beh of issue544 is
type t_axi_write_address_channel is record
awid : std_logic_vector;
awaddr : std_logic_vector;
awlen : std_logic_vector(7 downto 0);
awsize : std_logic_vector(2 downto 0);
awburst : std_logic_vector(1 downto 0);
awlock : std_logic;
awcache : std_logic_vector(3 downto 0);
awprot : std_logic_vector(2 downto 0);
awqos : std_logic_vector(3 downto 0);
awregion : std_logic_vector(3 downto 0);
awuser : std_logic_vector;
awvalid : std_logic;
awready : std_logic;
end record;
type t_axi_write_data_channel is record
wdata : std_logic_vector;
wstrb : std_logic_vector;
wlast : std_logic;
wuser : std_logic_vector;
wvalid : std_logic;
wready : std_logic;
end record;
type t_axi_write_response_channel is record
bid : std_logic_vector;
bresp : std_logic_vector(1 downto 0);
buser : std_logic_vector;
bvalid : std_logic;
bready : std_logic;
end record;
type t_axi_read_address_channel is record
-- Source: Master
arid : std_logic_vector;
araddr : std_logic_vector;
arlen : std_logic_vector(7 downto 0);
arsize : std_logic_vector(2 downto 0);
arburst : std_logic_vector(1 downto 0);
arlock : std_logic;
arcache : std_logic_vector(3 downto 0);
arprot : std_logic_vector(2 downto 0);
arqos : std_logic_vector(3 downto 0);
arregion : std_logic_vector(3 downto 0);
aruser : std_logic_vector;
arvalid : std_logic;
-- Source: Slave
arready : std_logic;
end record;
type t_axi_read_data_channel is record
-- Source: Slave
rid : std_logic_vector;
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rlast : std_logic;
ruser : std_logic_vector;
rvalid : std_logic;
-- Source: Master
rready : std_logic;
end record;
type t_axi_if is record
write_address_channel : t_axi_write_address_channel;
write_data_channel : t_axi_write_data_channel;
write_response_channel : t_axi_write_response_channel;
read_address_channel : t_axi_read_address_channel;
read_data_channel : t_axi_read_data_channel;
end record;
signal axi_if : t_axi_if( write_address_channel( awid( 8 -1 downto 0),
awaddr( 32-1 downto 0),
awuser( 8 -1 downto 0)),
write_data_channel( wdata( 32-1 downto 0),
wstrb( 4 -1 downto 0),
wuser( 8 -1 downto 0)),
write_response_channel(bid( 8 -1 downto 0),
buser( 8 -1 downto 0)),
read_address_channel( arid( 8 -1 downto 0),
araddr( 32-1 downto 0),
aruser( 8-1 downto 0)),
read_data_channel( rid( 8-1 downto 0),
rdata( 32-1 downto 0),
ruser( 8-1 downto 0)));
begin
i_test : entity work.test2
port map (
wr_port_in.awid => axi_if.write_address_channel.awid,
wr_port_in.awaddr => axi_if.write_address_channel.awaddr,
wr_port_in.awlen => axi_if.write_address_channel.awlen,
wr_port_in.awsize => axi_if.write_address_channel.awsize,
wr_port_in.awburst => axi_if.write_address_channel.awburst,
wr_port_in.awlock => axi_if.write_address_channel.awlock,
wr_port_in.awcache => axi_if.write_address_channel.awcache,
wr_port_in.awprot => axi_if.write_address_channel.awprot,
wr_port_in.awqos => axi_if.write_address_channel.awqos,
wr_port_in.awregion => axi_if.write_address_channel.awregion,
wr_port_in.awuser => axi_if.write_address_channel.awuser,
wr_port_in.awvalid => axi_if.write_address_channel.awvalid,
wr_port_in.wdata => axi_if.write_data_channel.wdata,
wr_port_in.wstrb => axi_if.write_data_channel.wstrb,
wr_port_in.wlast => axi_if.write_data_channel.wlast,
wr_port_in.wuser => axi_if.write_data_channel.wuser,
wr_port_in.wvalid => axi_if.write_data_channel.wvalid,
wr_port_in.bready => axi_if.write_response_channel.bready,
rd_port_in.arid => axi_if.read_address_channel.arid,
rd_port_in.araddr => axi_if.read_address_channel.araddr,
rd_port_in.arlen => axi_if.read_address_channel.arlen,
rd_port_in.arsize => axi_if.read_address_channel.arsize,
rd_port_in.arburst => axi_if.read_address_channel.arburst,
rd_port_in.arlock => axi_if.read_address_channel.arlock,
rd_port_in.arcache => axi_if.read_address_channel.arcache,
rd_port_in.arprot => axi_if.read_address_channel.arprot,
rd_port_in.arqos => axi_if.read_address_channel.arqos,
rd_port_in.arregion => axi_if.read_address_channel.arregion,
rd_port_in.aruser => axi_if.read_address_channel.aruser,
rd_port_in.arvalid => axi_if.read_address_channel.arvalid,
rd_port_in.rready => axi_if.read_data_channel.rready,
wr_port_out.awready => axi_if.write_address_channel.awready,
wr_port_out.wready => axi_if.write_data_channel.wready,
wr_port_out.bid => axi_if.write_response_channel.bid,
wr_port_out.bresp => axi_if.write_response_channel.bresp,
wr_port_out.buser => axi_if.write_response_channel.buser,
wr_port_out.bvalid => axi_if.write_response_channel.bvalid,
rd_port_out.arready => axi_if.read_address_channel.arready,
rd_port_out.rid => axi_if.read_data_channel.rid,
rd_port_out.rdata => axi_if.read_data_channel.rdata,
rd_port_out.rresp => axi_if.read_data_channel.rresp,
rd_port_out.rlast => axi_if.read_data_channel.rlast,
rd_port_out.ruser => axi_if.read_data_channel.ruser,
rd_port_out.rvalid => axi_if.read_data_channel.rvalid
);
process
begin
report "OK";
wait;
end process;
end architecture beh;
| gpl-3.0 | f685938c2dace042c6fdfb11011dc5ee | 0.593951 | 3.266717 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random-b.vhd | 4 | 5,629 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_random-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library math;
package body random is
use math.math_real;
constant sample_seeds : seed_array(0 to 50)
:= ( 0 => (1, 1),
1 => (1919456777, 2006618587),
2 => (928906921, 476680813),
3 => (715788085, 762347824),
4 => (366002668, 1804336679),
5 => (1866585254, 247488051),
6 => (1342990589, 1539624735),
7 => (677313287, 1675609237),
8 => (644816519, 2026475269),
9 => (1654953611, 564421524),
10 => (1020104619, 712556314),
11 => (609798541, 1592526288),
12 => (1106087470, 1468242308),
13 => (1378844312, 646793513),
14 => (966261604, 481733031),
15 => (1407842093, 1316990206),
16 => (1705378215, 1930221363),
17 => (206887499, 1810320799),
18 => (1681633030, 2114795480),
19 => (71194926, 1642522201),
20 => (663275331, 1947299255),
21 => (224432387, 944962866),
22 => (1156075861, 1866435087),
23 => (1670357576, 1247152991),
24 => (846934138, 1673364736),
25 => (1972636955, 1404522710),
26 => (533484185, 592078395),
27 => (1989468008, 1409246301),
28 => (697086615, 1975145057),
29 => (111393259, 1673620688),
30 => (1352201163, 872947497),
31 => (1342844190, 877696585),
32 => (938770066, 1222894811),
33 => (1144599578, 661919919),
34 => (1750521407, 269946538),
35 => (457892500, 1256953520),
36 => (1678589945, 356027520),
37 => (1484458924, 2103068828),
38 => (1296978761, 2124096638),
39 => (1702642440, 1161000593),
40 => (1244690090, 2016422304),
41 => (1858682943, 1053836731),
42 => (1496964676, 701079294),
43 => (432696952, 602526767),
44 => (2097684438, 1264032473),
45 => (2115456834, 298917738),
46 => (432301768, 232430346),
47 => (1929812456, 758157910),
48 => (1655564027, 1062345086),
49 => (1116121051, 538424126),
50 => (844396720, 821616997) );
procedure init_fixed ( random_info : out random_info_record;
mean : in real ) is
begin
random_info.distribution := fixed;
random_info.mean := mean;
end procedure init_fixed;
procedure init_uniform ( random_info : out random_info_record;
lower_bound, upper_bound : in real;
seed : in seed_type ) is
begin
assert lower_bound <= upper_bound
report "init_uniform: lower_bound > upper_bound" severity failure;
random_info.distribution := uniform;
random_info.lower_bound := lower_bound;
random_info.upper_bound := upper_bound;
random_info.seed := seed;
end procedure init_uniform;
procedure init_exponential ( random_info : out random_info_record;
mean : in real;
seed : in seed_type ) is
begin
assert mean > 0.0
report "init_exponential: mean not positive" severity failure;
random_info.distribution := exponential;
random_info.mean := mean;
random_info.seed := seed;
end procedure init_exponential;
procedure generate_uniform ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
random_number := random_info.lower_bound
+ tmp * (random_info.upper_bound - random_info.lower_bound);
end procedure generate_uniform;
procedure generate_exponential ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
loop
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
exit when tmp /= 0.0;
end loop;
random_number := - random_info.mean * math_real.log(tmp);
end procedure generate_exponential;
procedure generate_random ( random_info : inout random_info_record;
random_number : out real ) is
begin
case random_info.distribution is
when fixed =>
random_number := random_info.mean;
when uniform =>
generate_uniform(random_info, random_number);
when exponential =>
generate_exponential(random_info, random_number);
end case;
end procedure generate_random;
end package body random;
| gpl-2.0 | 883386dc689f504c8e1cca0036e23bc6 | 0.577723 | 3.798246 | false | false | false | false |
nickg/nvc | test/regress/record33.vhd | 1 | 1,835 | entity record33 is
end entity;
architecture test of record33 is
type t_list;
type t_list_ptr is access t_list;
type t_data is record
msg : string;
end record;
type t_list is record
seq : natural;
data : t_data;
chain : t_list_ptr;
end record;
type t_shared_queue is protected
procedure push (data : in t_data);
procedure pop (data : out t_data; seq : out natural);
end protected;
type t_shared_queue is protected body
variable head, tail : t_list_ptr;
variable next_seq : natural;
procedure push (data : in t_data) is
variable elt : t_list_ptr;
begin
elt := new t_list'(seq => next_seq, data => data, chain => null);
next_seq := next_seq + 1;
if head = null then
head := elt;
tail := elt;
else
tail.chain := elt;
tail := elt;
end if;
end procedure;
procedure pop (data : out t_data; seq : out natural) is
begin
assert head /= null;
data := head.data;
seq := head.seq;
head := head.chain;
end procedure;
end protected body;
shared variable queue : t_shared_queue;
begin
p1: process is
variable data : t_data(msg(1 to 5));
variable seq : natural;
variable msg : string(1 to 5);
begin
data.msg := "hello";
queue.push(data);
data.msg := "world";
queue.push(data);
wait for 1 ns;
queue.pop(data, seq);
assert seq = 0;
assert data.msg = "hello";
queue.pop(data, seq);
assert seq = 1;
assert data.msg = "world";
wait;
end process;
end architecture;
| gpl-3.0 | fff6ff3305c8e15e08eb13b58bbe1711 | 0.511717 | 3.971861 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2082.vhd | 4 | 2,074 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2082.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02082ent IS
END c07s02b04x00p20n01i02082ent;
ARCHITECTURE c07s02b04x00p20n01i02082arch OF c07s02b04x00p20n01i02082ent IS
TYPE real_vector is array (INTEGER range <>) of REAL;
BEGIN
TESTING: PROCESS
VARIABLE target : real_vector (1 to 7) ;
VARIABLE slice_1 : real_vector (1 to 4) := (1.0,2.0,3.0,4.0);
VARIABLE slice_2 : real_vector (-2 to 4) :=
(5.0,6.0,7.0,8.0,9.0,10.0,11.0);
BEGIN
target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
assert NOT(target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***PASSED TEST: c07s02b04x00p20n01i02082"
severity NOTE;
assert (target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***FAILED TEST: c07s02b04x00p20n01i02082 - One dimensional array of REAL type concatenation into a larger ARRAY failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02082arch;
| gpl-2.0 | 01996f8c138d4178d614dc37be501118 | 0.655256 | 3.255887 | false | true | false | false |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/tb_axi_to_stellarip.vhd | 1 | 9,049 | -------------------------------------------------------------------------------------
-- FILE NAME :
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_axi_to_stellarip is
end tb_axi_to_stellarip;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_axi_to_stellarip is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_10_MHZ : time := 100 ns;
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_368_MHZ : time := 2.7126 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
constant DATA_WIDTH : natural := 8;
constant ADDR_WIDTH : natural := 8;
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
type bus016 is array(natural range <>) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal clk200 : std_logic := '1';
signal clk100 : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal rst_rstin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_clkin : std_logic_vector(31 downto 0) := (others=>'1');
--AXI-Lite to 4DSP Stellar Cmds Signals
signal axi_aclk : std_logic;
signal axi_aresetn : std_logic;
signal axi_awaddr : std_logic_vector(32-1 downto 0);
signal axi_awvalid : std_logic;
signal axi_awready : std_logic;
signal axi_wdata : std_logic_vector(31 downto 0);
signal axi_wstrb : std_logic_vector(3 downto 0);
signal axi_wvalid : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_bready : std_logic;
signal axi_araddr : std_logic_vector(31 downto 0);
signal axi_arvalid : std_logic;
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(31 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
signal axi_rready : std_logic;
signal done : std_logic;
signal status : std_logic_vector(31 downto 0);
signal cmdclk_out : std_logic;
signal cmd_in : std_logic_vector(63 downto 0);
signal cmd_in_val : std_logic;
signal cmd_out : std_logic_vector(63 downto 0);
signal cmd_out_val : std_logic;
signal dac0_tdata : std_logic_vector(63 downto 0);
signal dac0_tkeep : std_logic_vector(3 downto 0);
signal dac0_tlast : std_logic;
signal dac0_tready : std_logic;
signal dac0_tstrb : std_logic;
signal dac0_tuser : std_logic_vector(31 downto 0);
signal dac0_tvalid : std_logic;
signal dac0_in_dval : std_logic;
signal dac0_in_data : std_logic_vector(63 downto 0);
signal dac0_in_stop : std_logic;
signal dac0_enable : std_logic;
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_100_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
clk200 <= not clk200 after CLK_200_MHZ / 2;
clk100 <= not clk100 after CLK_100_MHZ / 2;
rst <= '0' after CLK_125_MHZ * 10;
rstn <= '1' after CLK_125_MHZ * 40;
rst_rstin <= (0=>rst, 1 => rst, 2=> rst, others =>'0');
clk_clkin <= (13 => clk200, 14 => clk100, others=>clk);
axi_aclk <= clk;
axi_aresetn <= rstn; -- delayed from rst
-----------------------------------------------------------------------------------
-- StellarIP Command to AXI-Lite Interface
-----------------------------------------------------------------------------------
inst_stellarcmd_to_axilite:
entity xil_defaultlib.stellarcmd_to_axilite
port map(
s_axi_aclk => axi_aclk,
--s_axi_aresetn => axi_aresetn,
rst => rst,
-- axi-lite: write address channel
s_axi_awaddr => axi_awaddr,
s_axi_awvalid => axi_awvalid,
s_axi_awready => axi_awready,
-- axi-lite: write data channel
s_axi_wdata => axi_wdata,
s_axi_wstrb => axi_wstrb,
s_axi_wvalid => axi_wvalid,
s_axi_wready => axi_wready,
-- axi-lite: write response channel
s_axi_bresp => axi_bresp,
s_axi_bvalid => axi_bvalid,
s_axi_bready => axi_bready,
-- axi-lite: read address channel
s_axi_araddr => axi_araddr,
s_axi_arvalid => axi_arvalid,
s_axi_arready => axi_arready,
-- axi-lite: read channel
s_axi_rdata => axi_rdata,
s_axi_rresp => axi_rresp,
s_axi_rvalid => axi_rvalid,
s_axi_rready => axi_rready,
-- command interface
cmd_clk => cmdclk_out,
cmd_out => cmd_out,
cmd_out_val => cmd_out_val,
cmd_in => cmd_in,
cmd_in_val => cmd_in_val
);
cmd_in <= (others=>'0');
cmd_in_val <= '0';
axi_arvalid <= '0';
axi_araddr <= (others=>'0');
axi_rready <= '0';
-------------------------------------------------------------------------
-- AXI-Lite Traffic Generator
-- Mode: System Init
-- Transasction Depth: 16
-- Number of AXI Channels: 1
---------------------------------------------------------------------------
inst_traffic_gen:
entity xil_defaultlib.axi_traffic_gen_0
PORT MAP (
s_axi_aclk => axi_aclk,
s_axi_aresetn => axi_aresetn,
m_axi_lite_ch1_awaddr => axi_awaddr,
m_axi_lite_ch1_awprot => open,
m_axi_lite_ch1_awvalid => axi_awvalid,
m_axi_lite_ch1_awready => axi_awready,
m_axi_lite_ch1_wdata => axi_wdata,
m_axi_lite_ch1_wstrb => axi_wstrb,
m_axi_lite_ch1_wvalid => axi_wvalid,
m_axi_lite_ch1_wready => axi_wready,
m_axi_lite_ch1_bresp => axi_bresp,
m_axi_lite_ch1_bvalid => axi_bvalid,
m_axi_lite_ch1_bready => axi_bready,
--m_axi_lite_ch1_araddr => axi_araddr,
--m_axi_lite_ch1_arvalid => axi_arvalid,
--m_axi_lite_ch1_arready => axi_arready,
--m_axi_lite_ch1_rdata => axi_rdata,
--m_axi_lite_ch1_rvalid => axi_rvalid,
--m_axi_lite_ch1_rresp => axi_rresp,
--m_axi_lite_ch1_rready => axi_rready,
done => done,
status => status
);
-----------------------------------------------------------------------------------
-- AXI-Stream to StellarIP Wormhole Output
-----------------------------------------------------------------------------------
inst_axistream_to_whin:
entity xil_defaultlib.axistream_to_whin
port map (
clk => axi_aclk,
rst => rst,
data_in_tdata => dac0_tdata,
data_in_tkeep => dac0_tkeep,
data_in_tlast => dac0_tlast,
data_in_tready => dac0_tready,
data_in_tstrb => dac0_tstrb,
data_in_tuser => dac0_tuser,
data_in_tvalid => dac0_tvalid,
data_out_out_stop => dac0_in_stop,
data_out_out_dval => dac0_in_dval,
data_out_out_data => dac0_in_data
);
dac0_in_stop <= '0';
-- dac data generation
inst0_axi_stream_send:
entity xil_defaultlib.axi_stream_send
generic map(
COUNT => x"00000040"
)
port map (
clk => axi_aclk,
rstn => axi_aresetn,
tdata => dac0_tdata,
tvalid => dac0_tvalid,
enable => dac0_enable
);
dac0_enable <= '1';
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | eb26cf7ef6c3a7f14dc3714a11914192 | 0.471212 | 3.759452 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1211/tb_repro1.vhdl | 1 | 900 | entity tb_repro1 is
end tb_repro1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_repro1 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.repro1
port map (
sig_out => dout,
sig_in => din,
clock => clk,
reset => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
wait for 1 ns;
assert dout = '0' severity failure;
rst <= '0';
din <= '1';
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
rst <= '1';
wait for 1 ns;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 8cd150cbf6e40e133f60d1aa769d1547 | 0.558889 | 3.370787 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_15.vhd | 4 | 2,279 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_15.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_15 is
generic ( extended_reset : boolean := false );
end entity ch_05_15;
----------------------------------------------------------------
architecture test of ch_05_15 is
signal functional_reset, equivalent_reset : bit := '0';
begin
block_05_3_r : block is
port ( reset : out bit );
port map ( reset => functional_reset );
begin
-- code from book:
reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
'1', '0' after 50 ns;
-- end of code from book
end block block_05_3_r;
----------------
block_05_3_s : block is
port ( reset : out bit );
port map ( reset => equivalent_reset );
begin
-- code from book:
reset_gen : process is
begin
if extended_reset then
reset <= '1', '0' after 200 ns;
else
reset <= '1', '0' after 50 ns;
end if;
wait;
end process reset_gen;
-- end of code from book
end block block_05_3_s;
----------------
verifier :
assert functional_reset = equivalent_reset
report "Functional and equivalent models give different results";
end architecture test;
| gpl-2.0 | 49f28e8d30197bbd069ed3103ec5720a | 0.556823 | 4.283835 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/sim/design_1_axi_dma_0_0.vhd | 3 | 24,803 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_9;
USE axi_dma_v7_1_9.axi_dma;
ENTITY design_1_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_dma_0_0;
ARCHITECTURE design_1_axi_dma_0_0_arch OF design_1_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 8,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 8,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_1_axi_dma_0_0_arch;
| gpl-3.0 | 00d6af02008a633407c52deaa7ffddcc | 0.673749 | 2.779671 | false | false | false | false |
nickg/nvc | test/eopt/partial1.vhd | 1 | 883 | entity sub is
port (
result : out bit_vector(3 downto 0);
in1 : in bit_vector(3 downto 0) );
end entity;
architecture test of sub is
signal in2 : bit_vector(2 downto 0);
begin
assert in1(1 downto 0) = "00";
in2 <= "001";
result <= '0' & bit_vector(in1 and in2);
end architecture;
-------------------------------------------------------------------------------
entity partial1 is
end entity;
architecture test of partial1 is
signal result : bit_vector(3 downto 0);
signal in1 : bit_vector(1 downto 0);
begin
uut: entity work.sub
port map (
result => result,
in1(3 downto 2) => bit_vector(in1),
in1(1 downto 0) => "00" );
stim: process is
begin
in1 <= "01";
wait for 1 ns;
assert result = X"5";
wait;
end process;
end architecture;
| gpl-3.0 | 9cbe1d277038078d9972c72db9dcb345 | 0.510759 | 3.725738 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_05.vhd | 4 | 2,164 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_05 is
end entity tb_05_05;
library ieee; use ieee.std_logic_1164.all;
architecture test of tb_05_05 is
signal a, b : std_ulogic := '0';
signal y : std_ulogic;
begin
dut : entity work.and2(detailed_delay)
port map ( a => a, b => b, y => y );
stimulus : process is
begin
wait for 10 ns;
a <= '1'; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= '1', '0' after 250 ps; wait for 10 ns;
b <= '1', '0' after 350 ps; wait for 10 ns;
b <= '1', '0' after 450 ps; wait for 10 ns;
b <= '1', '0' after 550 ps; wait for 10 ns;
b <= '1', '0' after 650 ps; wait for 10 ns;
b <= '1', '0' after 750 ps; wait for 10 ns;
b <= '1', '0' after 850 ps; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0', '1' after 250 ps; wait for 10 ns;
b <= '0', '1' after 350 ps; wait for 10 ns;
b <= '0', '1' after 450 ps; wait for 10 ns;
b <= 'X'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= 'X', '0' after 250 ps; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | ce08eef11021f7bcc58806a03878017c | 0.56793 | 3.254135 | false | false | false | false |
tgingold/ghdl | testsuite/synth/var01/tb_var01a.vhdl | 1 | 976 | entity tb_var01a is
end tb_var01a;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var01a is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal val : std_logic_vector (7 downto 0);
signal res : std_logic_vector (7 downto 0);
begin
dut: entity work.var01a
port map (
clk => clk,
mask => mask,
val => val,
res => res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
mask <= "11";
val <= x"12";
pulse;
assert res = x"12" report "res=" & to_hstring (res) severity failure;
mask <= "10";
val <= x"9a";
pulse;
assert res = x"92" severity failure;
mask <= "00";
val <= x"00";
pulse;
assert res = x"92" severity failure;
mask <= "01";
val <= x"de";
pulse;
assert res = x"9e" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 7e1fda8ab501dcf4a6113c9644be2d67 | 0.558402 | 3.264214 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/tb.vhd | 2 | 158,618 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity tb is
end tb;
architecture augh of tb is
constant simu_max_cycles : natural := 1000000;
constant simu_disp_cycles : std_logic := '0';
constant simu_err_end_in : std_logic := '0';
constant reset_cycles : natural := 4;
component top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(7 downto 0);
stdin_data : in std_logic_vector(7 downto 0);
stdin_rdy : out std_logic
);
end component;
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal start : std_logic := '0';
signal clock_next : std_logic := '0';
-- Access 'clock' model 'clock'
-- Access 'reset' model 'reset'
-- Access 'start' model 'start'
-- Access 'stdin' model 'fifo_in'
signal stdin_data : std_logic_vector(7 downto 0) := (others => '0');
signal stdin_rdy : std_logic := '0';
signal stdin_ack : std_logic := '0';
signal stdin_vector_idx : natural := 0;
signal stdin_vector : std_logic_vector(7 downto 0) := (others => '0');
-- Test vectors
constant stdin_vectors_nb : natural := 5207;
type stdin_vec_type is array (0 to stdin_vectors_nb-1) of std_logic_vector(7 downto 0);
constant stdin_vectors : stdin_vec_type := (
X"ff", X"d8", X"ff", X"e0", X"00", X"10", X"4a", X"46", X"49", X"46", X"00", X"01", X"01", X"00", X"00",
X"01", X"00", X"01", X"00", X"00", X"ff", X"db", X"00", X"43", X"00", X"03", X"02", X"02", X"02", X"02",
X"02", X"03", X"02", X"02", X"02", X"03", X"03", X"03", X"03", X"04", X"06", X"04", X"04", X"04", X"04",
X"04", X"08", X"06", X"06", X"05", X"06", X"09", X"08", X"0a", X"0a", X"09", X"08", X"09", X"09", X"0a",
X"0c", X"0f", X"0c", X"0a", X"0b", X"0e", X"0b", X"09", X"09", X"0d", X"11", X"0d", X"0e", X"0f", X"10",
X"10", X"11", X"10", X"0a", X"0c", X"12", X"13", X"12", X"10", X"13", X"0f", X"10", X"10", X"10", X"ff",
X"db", X"00", X"43", X"01", X"03", X"03", X"03", X"04", X"03", X"04", X"08", X"04", X"04", X"08", X"10",
X"0b", X"09", X"0b", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10",
X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10",
X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10",
X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"ff", X"c0", X"00", X"11", X"08", X"00", X"3b",
X"00", X"5a", X"03", X"01", X"22", X"00", X"02", X"11", X"01", X"03", X"11", X"01", X"ff", X"c4", X"00",
X"1f", X"00", X"00", X"01", X"05", X"01", X"01", X"01", X"01", X"01", X"01", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07", X"08", X"09", X"0a", X"0b",
X"ff", X"c4", X"00", X"b5", X"10", X"00", X"02", X"01", X"03", X"03", X"02", X"04", X"03", X"05", X"05",
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X"6d", X"cd", X"49", X"34", X"70", X"9f", X"b4", X"4c", X"d6", X"df", X"1a", X"34", X"4b", X"7f", X"1d",
X"f8", X"1e", X"74", X"d5", X"2d", X"34", X"3d", X"3a", X"db", X"51", X"bb", X"8a", X"56", X"8a", X"19",
X"ed", X"1e", X"67", X"9a", X"27", X"b5", X"44", X"00", X"4f", X"2a", X"2c", X"50", X"a4", X"8e", X"8f",
X"26", X"e8", X"fc", X"e8", X"88", X"2f", X"92", X"aa", X"9f", X"06", X"ff", X"00", X"69", X"ef", X"86",
X"f3", X"e9", X"93", X"fc", X"21", X"f8", X"89", X"e1", X"8b", X"58", X"bc", X"3f", X"ac", X"a2", X"5b",
X"4c", X"ed", X"71", X"04", X"56", X"b0", X"ca", X"54", X"01", X"28", X"8a", X"0b", X"78", X"8c", X"65",
X"9d", X"e4", X"62", X"e6", X"46", X"23", X"e5", X"0b", X"b7", X"15", X"85", X"f0", X"57", X"c0", X"7a",
X"cd", X"ff", X"00", X"c4", X"ab", X"9d", X"4d", X"f5", X"4b", X"5b", X"bd", X"17", X"4e", X"bc", X"d4",
X"34", X"d5", X"8f", X"56", X"bd", X"7b", X"08", X"b5", X"3b", X"74", X"9c", X"c2", X"54", X"4f", X"83",
X"24", X"8c", X"40", X"24", X"ab", X"23", X"2c", X"60", X"b0", X"28", X"77", X"15", X"af", X"a0", X"fe",
X"2a", X"7c", X"19", X"f0", X"36", X"a1", X"e2", X"4f", X"16", X"78", X"97", X"c2", X"16", X"da", X"65",
X"96", X"8f", X"a5", X"68", X"10", X"6a", X"57", X"1a", X"b4", X"d6", X"90", X"b6", X"9f", X"72", X"26",
X"33", X"ab", X"b5", X"ac", X"fb", X"85", X"bf", X"96", X"be", X"53", X"2c", X"9f", X"bd", X"01", X"1d",
X"19", X"49", X"db", X"90", X"6a", X"8f", X"b6", X"c5", X"4d", X"d4", X"83", X"49", X"fc", X"2d", X"3d",
X"53", X"b7", X"45", X"75", X"b7", X"4d", X"cb", X"a7", X"34", X"9d", X"e4", X"ae", X"7c", X"69", X"a2",
X"d9", X"68", X"3e", X"1f", X"f1", X"c6", X"a3", X"e1", X"9d", X"4b", X"4e", X"b9", X"bc", X"f0", X"a4",
X"b7", X"93", X"c0", X"93", X"99", X"95", X"84", X"a0", X"33", X"18", X"d0", X"48", X"bc", X"36", X"55",
X"7d", X"89", X"eb", X"c5", X"74", X"d2", X"f8", X"ab", X"c1", X"91", X"4a", X"f1", X"da", X"7c", X"39",
X"f0", X"42", X"c0", X"8c", X"56", X"25", X"97", X"51", X"88", X"38", X"40", X"78", X"0c", X"33", X"d7",
X"18", X"cd", X"72", X"77", X"53", X"68", X"76", X"da", X"65", X"ad", X"87", X"87", X"b5", X"18", X"6f",
X"d2", X"3d", X"6a", X"62", X"f7", X"a2", X"dd", X"62", X"46", X"90", X"a3", X"32", X"c4", X"02", X"49",
X"22", X"32", X"8c", X"2a", X"ef", X"56", X"20", X"ef", X"3f", X"dd", X"39", X"e6", X"57", X"e0", X"ac",
X"5a", X"8a", X"8d", X"41", X"24", X"d5", X"51", X"6e", X"87", X"9c", X"15", X"6c", X"72", X"00", X"6e",
X"70", X"0e", X"79", X"1c", X"d7", X"cb", X"d5", X"a3", X"05", X"5e", X"71", X"c4", X"3e", X"46", X"9f",
X"47", X"75", X"bf", X"93", X"35", X"e5", X"e4", X"76", X"86", X"d6", X"4f", X"6b", X"ee", X"77", X"5a",
X"7f", X"ed", X"43", X"e2", X"cf", X"0e", X"fd", X"a2", X"fb", X"c2", X"7a", X"80", X"d3", X"75", X"3b",
X"39", X"a3", X"b3", X"5b", X"78", X"96", X"48", X"a1", X"d4", X"34", X"ff", X"00", X"3a", X"39", X"36",
X"f9", X"8a", X"de", X"6e", X"4c", X"b0", X"a7", X"98", X"85", X"d7", X"7a", X"48", X"fb", X"b7", X"7c",
X"cb", X"5f", X"5b", X"78", X"eb", X"e2", X"b6", X"bb", X"fb", X"41", X"fc", X"39", X"f1", X"f7", X"86",
X"24", X"36", X"3e", X"1e", X"d3", X"a7", X"d2", X"b4", X"f5", X"86", X"3b", X"6d", X"5c", X"bd", X"e2",
X"34", X"86", X"32", X"c8", X"62", X"24", X"33", X"c4", X"b3", X"47", X"2a", X"17", X"09", X"1a", X"6c",
X"94", X"a9", X"46", X"12", X"b9", X"87", X"f3", X"57", X"c5", X"96", X"d0", X"e9", X"1e", X"28", X"d5",
X"ec", X"f4", X"e0", X"f1", X"45", X"69", X"ab", X"5c", X"c1", X"0f", X"ce", X"cc", X"ca", X"91", X"ca",
X"e1", X"06", X"e2", X"49", X"38", X"00", X"72", X"4e", X"78", X"af", X"47", X"f1", X"57", X"8e", X"3c",
X"4b", X"a3", X"7c", X"28", X"f8", X"69", X"e2", X"cd", X"3e", X"f6", X"14", X"d5", X"a7", X"5d", X"47",
X"7d", X"d3", X"d9", X"c3", X"23", X"16", X"8e", X"f2", X"e1", X"51", X"f0", X"e8", X"40", X"75", X"12",
X"30", X"0e", X"06", X"e1", X"c6", X"0f", X"ca", X"b8", X"fa", X"dc", X"1c", X"1e", X"1e", X"94", X"a9",
X"d3", X"d9", X"6b", X"6e", X"8f", X"a3", X"5b", X"37", X"67", X"73", X"99", X"46", X"d7", X"47", X"0e",
X"f7", X"ef", X"a7", X"b2", X"88", X"6c", X"a0", X"86", X"e2", X"13", X"22", X"3b", X"a4", X"8c", X"58",
X"1f", X"99", X"4a", X"19", X"14", X"ed", X"60", X"46", X"ff", X"00", X"bb", X"f2", X"b2", X"b7", X"19",
X"19", X"07", X"dc", X"b4", X"9f", X"8a", X"5f", X"19", X"fc", X"23", X"e1", X"8f", X"0c", X"6a", X"b3",
X"69", X"d7", X"76", X"9a", X"35", X"95", X"c4", X"70", X"68", X"53", X"cb", X"a0", X"bc", X"16", X"f2",
X"db", X"b2", X"cf", X"89", X"8c", X"b1", X"2a", X"34", X"db", X"d5", X"ae", X"42", X"e6", X"42", X"59",
X"bc", X"d2", X"8a", X"5b", X"cc", X"6a", X"f1", X"ed", X"2a", X"ca", X"db", X"56", X"f0", X"37", X"89",
X"7c", X"41", X"a9", X"c6", X"6e", X"b5", X"2f", X"ed", X"0b", X"34", X"37", X"52", X"b1", X"69", X"08",
X"9a", X"57", X"32", X"fc", X"c4", X"e7", X"2c", X"46", X"49", X"eb", X"c9", X"f5", X"35", X"fa", X"f1",
X"fb", X"2e", X"78", X"33", X"c2", X"9f", X"13", X"7f", X"64", X"af", X"87", X"3a", X"27", X"8e", X"f4",
X"0b", X"3d", X"5f", X"4f", X"f8", X"85", X"15", X"fe", X"99", X"e2", X"3b", X"69", X"63", X"0b", X"1d",
X"f4", X"36", X"52", X"5c", X"c3", X"68", X"db", X"53", X"02", X"29", X"a2", X"8e", X"de", X"dd", X"52",
X"78", X"f6", X"ca", X"3c", X"88", X"8e", X"fc", X"c6", X"a4", X"70", X"50", X"9d", X"45", X"37", X"1a",
X"4e", X"dd", X"1f", X"e0", X"d7", X"ae", X"b6", X"2a", X"14", X"d4", X"93", X"67", X"8b", X"7c", X"33",
X"f8", X"bb", X"f0", X"3f", X"c4", X"bf", X"b3", X"de", X"8d", X"1f", X"8f", X"3c", X"4f", X"06", X"90",
X"da", X"95", X"ee", X"ff", X"00", X"14", X"e9", X"ba", X"4e", X"9d", X"73", X"15", X"c6", X"9b", X"22",
X"6a", X"29", X"9b", X"d9", X"ee", X"6d", X"22", X"4f", X"2e", X"3c", X"cb", X"04", X"d2", X"cb", X"88",
X"f7", X"3c", X"fb", X"51", X"bc", X"c2", X"ae", X"9b", X"5a", X"bf", X"8d", X"3e", X"35", X"6b", X"3e",
X"3f", X"f1", X"3e", X"b7", X"f0", X"e7", X"c4", X"5a", X"34", X"7a", X"4d", X"96", X"9b", X"6d", X"e2",
X"1b", X"0d", X"52", X"47", X"7b", X"8d", X"3f", X"c4", X"17", X"82", X"26", X"68", X"ad", X"c4", X"f7",
X"12", X"c7", X"6f", X"1c", X"2f", X"14", X"52", X"2c", X"d7", X"5e", X"63", X"15", X"f3", X"90", X"0c",
X"6f", X"62", X"3c", X"07", X"f6", X"8f", X"f0", X"ae", X"8d", X"f0", X"43", X"5e", X"f1", X"85", X"9f",
X"c2", X"a8", X"ee", X"fc", X"3b", X"0d", X"b7", X"c2", X"fd", X"2a", X"28", X"d6", X"da", X"fa", X"76",
X"f9", X"35", X"0d", X"53", X"ec", X"97", X"aa", X"db", X"dd", X"b7", X"89", X"61", X"66", X"52", X"1b",
X"38", X"63", X"bc", X"61", X"c0", X"6a", X"fa", X"4f", X"e0", X"35", X"85", X"be", X"8d", X"e0", X"2d",
X"25", X"34", X"ff", X"00", X"35", X"21", X"b7", X"d3", X"7c", X"6f", X"61", X"15", X"bc", X"93", X"3c",
X"b0", X"2c", X"1a", X"6e", X"bf", X"67", X"05", X"92", X"f9", X"4e", X"4a", X"66", X"38", X"de", X"41",
X"bb", X"1b", X"98", X"bb", X"b3", X"96", X"66", X"24", X"fb", X"38", X"3a", X"8e", X"a5", X"47", X"2a",
X"9b", X"ab", X"27", X"6e", X"ba", X"ff", X"00", X"c1", X"b9", X"4a", X"2d", X"fb", X"b7", X"d8", X"f9",
X"cb", X"45", X"d6", X"fe", X"23", X"7c", X"24", X"f1", X"b7", X"8b", X"7e", X"28", X"7c", X"3d", X"f8",
X"71", X"69", X"37", X"87", X"64", X"b0", X"d5", X"af", X"f4", X"6d", X"2a", X"eb", X"51", X"8a", X"58",
X"f4", X"dd", X"08", X"24", X"91", X"a3", X"c3", X"e5", X"b1", X"77", X"8e", X"19", X"64", X"59", X"66",
X"b6", X"8f", X"27", X"6d", X"bb", X"45", X"21", X"1e", X"5a", X"c8", X"bc", X"b7", X"ec", X"e7", X"f1",
X"c3", X"c4", X"b6", X"9e", X"39", X"4f", X"16", X"fc", X"4b", X"8e", X"4d", X"6b", X"45", X"d5", X"64",
X"6b", X"4b", X"61", X"2d", X"9d", X"b4", X"70", X"c7", X"2a", X"5c", X"5b", X"4c", X"d3", X"c4", X"1b",
X"08", X"b2", X"a9", X"b5", X"85", X"9a", X"73", X"ca", X"3c", X"30", X"b1", X"93", X"78", X"dd", X"5f",
X"a1", X"ba", X"bf", X"86", X"b4", X"2b", X"4f", X"8c", X"56", X"da", X"ad", X"be", X"9b", X"12", X"5c",
X"e9", X"de", X"0d", X"d4", X"2d", X"6d", X"9b", X"92", X"ab", X"14", X"77", X"5a", X"64", X"88", X"85",
X"4f", X"ca", X"c1", X"5d", X"98", X"8d", X"c0", X"e3", X"73", X"0e", X"84", X"8a", X"f8", X"03", X"fe",
X"0a", X"0f", X"69", X"6b", X"63", X"fb", X"54", X"6a", X"90", X"58", X"c0", X"96", X"c9", X"a8", X"59",
X"69", X"33", X"5c", X"88", X"46", X"cf", X"32", X"47", X"0f", X"0b", X"b1", X"c7", X"73", X"1c", X"31",
X"a9", X"3d", X"4e", X"df", X"52", X"49", X"bc", X"6d", X"39", X"65", X"eb", X"da", X"d2", X"77", X"8a",
X"96", X"cf", X"d3", X"ca", X"dd", X"cc", X"b9", X"a4", X"9d", X"ae", X"56", X"f1", X"2f", X"c4", X"2d",
X"2f", X"5b", X"f0", X"dd", X"f7", X"89", X"a5", X"bc", X"36", X"de", X"22", X"d5", X"24", X"7d", X"43",
X"52", X"98", X"ee", X"9e", X"df", X"4d", X"69", X"54", X"ec", X"58", X"d5", X"db", X"6a", X"dd", X"4a",
X"c0", X"05", X"6e", X"91", X"a8", X"df", X"21", X"dd", X"b1", X"59", X"3e", X"1d", X"7c", X"7e", X"f8",
X"a1", X"a3", X"f8", X"07", X"c3", X"7e", X"1f", X"f0", X"d4", X"5e", X"1a", X"b7", X"f0", X"7f", X"84",
X"6f", X"ae", X"be", X"dd", X"1d", X"fc", X"b6", X"b6", X"f6", X"ba", X"a4", X"57", X"1b", X"d9", X"ac",
X"24", X"86", X"77", X"df", X"75", X"0e", X"c9", X"6e", X"01", X"11", X"24", X"b2", X"37", X"da", X"30",
X"e1", X"d9", X"93", X"77", X"85", X"f8", X"8f", X"52", X"d4", X"34", X"2d", X"5a", X"da", X"1d", X"1e",
X"fa", X"e2", X"ce", X"38", X"d4", X"00", X"b0", X"c8", X"54", X"73", X"c9", X"27", X"d4", X"9c", X"9c",
X"93", X"c9", X"ef", X"57", X"ee", X"2f", X"26", X"d7", X"74", X"3d", X"6b", X"52", X"d4", X"84", X"6f",
X"75", X"61", X"30", X"48", X"25", X"8e", X"25", X"84", X"80", X"66", X"2a", X"77", X"6c", X"03", X"7f",
X"03", X"f8", X"b3", X"dc", X"f5", X"26", X"be", X"52", X"38", X"ba", X"91", X"93", X"c4", X"c5", X"d9",
X"cf", X"7b", X"69", X"be", X"bf", X"99", X"97", X"33", X"56", X"48", X"b5", X"e2", X"1b", X"9f", X"09",
X"3d", X"ed", X"cd", X"8f", X"86", X"74", X"d3", X"a5", X"e8", X"e6", X"f1", X"ee", X"ed", X"ac", X"2d",
X"e7", X"33", X"2d", X"b9", X"6e", X"06", X"e7", X"20", X"09", X"25", X"55", X"c2", X"b1", X"8c", X"79",
X"65", X"95", X"ca", X"6e", X"52", X"09", X"f5", X"1b", X"1f", X"da", X"3f", X"c4", X"96", X"56", X"56",
X"f6", X"76", X"ff", X"00", X"0d", X"b4", X"c6", X"8a", X"08", X"92", X"24", X"3b", X"e3", X"5c", X"aa",
X"80", X"07", X"1b", X"b8", X"e0", X"74", X"ae", X"37", X"e2", X"2f", X"86", X"74", X"1d", X"1f", X"41",
X"b4", X"9b", X"4c", X"d3", X"22", X"b7", X"70", X"96", X"e8", X"59", X"33", X"96", X"04", X"39", X"cb",
X"73", X"f3", X"1c", X"a8", X"e4", X"e4", X"f5", X"e7", X"93", X"5e", X"cd", X"e1", X"8f", X"02", X"78",
X"5a", X"f3", X"c3", X"7a", X"4d", X"dd", X"ce", X"9a", X"ef", X"34", X"f6", X"30", X"49", X"23", X"7d",
X"a6", X"51", X"b9", X"9a", X"35", X"24", X"e0", X"36", X"3a", X"9a", X"f0", X"31", X"52", X"85", X"47",
X"cd", X"35", X"7d", X"5e", X"f7", X"fd", X"19", X"dd", X"4a", X"b5", X"58", X"d4", X"92", X"52", X"3f",
X"ff", X"d9"
);
-- Access 'stdout' model 'fifo_out'
signal stdout_data : std_logic_vector(7 downto 0) := (others => '0');
signal stdout_rdy : std_logic := '0';
signal stdout_ack : std_logic := '0';
signal stdout_vector_idx : natural := 0;
signal stdout_vector : std_logic_vector(7 downto 0) := (others => '0');
-- Test vectors
constant stdout_vectors_nb : natural := 15932;
type stdout_vec_type is array (0 to stdout_vectors_nb-1) of std_logic_vector(7 downto 0);
constant stdout_vectors : stdout_vec_type := (
X"bc", X"d1", X"be", X"99", X"8f", X"67", X"95", X"c0", X"ac", X"9d", X"bd", X"c0", X"a4", X"c3", X"bc",
X"b5", X"c1", X"a7", X"bc", X"d2", X"b1", X"8e", X"25", X"0a", X"1f", X"28", X"27", X"34", X"20", X"1d",
X"22", X"0e", X"0a", X"12", X"0e", X"1a", X"07", X"6c", X"b5", X"be", X"b5", X"7f", X"5b", X"63", X"49",
X"24", X"0b", X"24", X"42", X"5d", X"5a", X"41", X"33", X"20", X"24", X"23", X"26", X"35", X"38", X"23",
X"19", X"19", X"20", X"31", X"29", X"36", X"20", X"1f", X"1f", X"22", X"18", X"19", X"26", X"2b", X"20",
X"0b", X"09", X"0d", X"14", X"19", X"17", X"11", X"10", X"12", X"1e", X"19", X"21", X"2d", X"24", X"1d",
X"a6", X"c1", X"65", X"5a", X"aa", X"81", X"92", X"d5", X"a9", X"58", X"91", X"c7", X"cf", X"a5", X"89",
X"71", X"c9", X"9b", X"8b", X"d1", X"bf", X"c9", X"ab", X"67", X"33", X"1d", X"11", X"09", X"1d", X"2b",
X"21", X"24", X"18", X"0e", X"18", X"18", X"04", X"6c", X"b9", X"b4", X"ba", X"bc", X"b7", X"c3", X"c0",
X"6c", X"30", X"4b", X"67", X"55", X"45", X"31", X"2e", X"37", X"2c", X"2a", X"32", X"33", X"29", X"1e",
X"12", X"0e", X"1e", X"30", X"30", X"36", X"22", X"28", X"26", X"24", X"1f", X"1c", X"34", X"37", X"2d",
X"0f", X"0e", X"10", X"17", X"15", X"0f", X"0b", X"11", X"19", X"1f", X"1a", X"2c", X"49", X"22", X"27",
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X"84", X"e1", X"3e", X"00", X"1f", X"0e", X"15", X"29", X"49", X"19", X"c9", X"a8", X"92", X"8a", X"fd",
X"9d", X"b6", X"62", X"6d", X"7b", X"43", X"00", X"5d", X"30", X"17", X"ac", X"90", X"4b", X"07", X"01",
X"3c", X"d2", X"8c", X"7c", X"21", X"a8", X"db", X"d1", X"c1", X"47", X"14", X"2e", X"51", X"3c", X"5d",
X"4f", X"1e", X"2d", X"6b", X"b5", X"22", X"58", X"06", X"00", X"67", X"46", X"53", X"15", X"45", X"2b",
X"21", X"2e", X"4a", X"36", X"4e", X"77", X"47", X"00", X"34", X"71", X"a7", X"25", X"5e", X"75", X"40",
X"0f", X"1c", X"40", X"68", X"0c", X"0c", X"00", X"01", X"21", X"25", X"01", X"0a", X"1e", X"00", X"00",
X"4d", X"72", X"a8", X"00", X"57", X"5d", X"00", X"07", X"8a", X"aa", X"b1", X"be", X"35", X"3b", X"46",
X"d1", X"a3", X"3d", X"25", X"4d", X"50", X"08", X"2d", X"66", X"00", X"43", X"c6", X"b6", X"87", X"00",
X"93", X"93", X"a3", X"99", X"0c", X"c5", X"d8", X"c3", X"ba", X"68", X"30", X"2c", X"33", X"40", X"56",
X"91", X"69", X"39", X"11", X"5d", X"15", X"59", X"00", X"3e", X"44", X"3e", X"44", X"14", X"51", X"2e",
X"0e", X"31", X"0d", X"2e", X"24", X"1e", X"31", X"42", X"0a", X"4a", X"64", X"94", X"c8", X"87", X"52",
X"36", X"5a", X"99", X"7d", X"7b", X"32", X"00", X"05", X"20", X"0e", X"00", X"00", X"19", X"00", X"00",
X"56", X"25", X"6c", X"00", X"a6", X"c0", X"bc", X"9a", X"9b", X"8e", X"a2", X"d8", X"69", X"66", X"a6",
X"ce", X"e4", X"6f", X"56", X"1c", X"24", X"29", X"1a", X"5c", X"29", X"00", X"76", X"cf", X"af", X"b0",
X"a2", X"56", X"dc", X"3a", X"2d", X"99", X"85", X"ca", X"d7", X"b5", X"0f", X"33", X"28", X"2c", X"22",
X"45", X"68", X"40", X"59", X"25", X"15", X"2d", X"00", X"33", X"91", X"c0", X"e4", X"20", X"22", X"12",
X"00", X"00", X"57", X"59", X"45", X"36", X"18", X"00", X"00", X"38", X"8b", X"ad", X"d4", X"c0", X"79",
X"38", X"5a", X"3a", X"61", X"58", X"3d", X"00", X"23", X"4d", X"2a", X"03", X"00", X"1e", X"00", X"00",
X"1b", X"0f", X"00", X"00", X"2b", X"9d", X"c8", X"f7", X"e3", X"83", X"54", X"b4", X"fa", X"ff", X"a6",
X"ec", X"8b", X"37", X"07", X"18", X"12", X"1d", X"09", X"1f", X"33", X"ae", X"a4", X"a4", X"de", X"b7",
X"d0", X"f2", X"2d", X"17", X"08", X"1a", X"9a", X"a0", X"8b", X"00", X"44", X"06", X"3d", X"23", X"31",
X"62", X"0e", X"23", X"1d", X"18", X"4e", X"00", X"00", X"52", X"ff", X"c6", X"65", X"70", X"ba", X"a7",
X"3a", X"41", X"bf", X"8f", X"4d", X"1a", X"28", X"13", X"1c", X"15", X"48", X"c5", X"a4", X"cc", X"e4",
X"63", X"4e", X"5a", X"36", X"2b", X"11", X"00", X"05", X"4d", X"23", X"0c", X"00", X"0e", X"00", X"00",
X"30", X"72", X"0d", X"33", X"00", X"0b", X"84", X"c2", X"f4", X"d3", X"be", X"c5", X"e2", X"cd", X"72",
X"c7", X"c2", X"21", X"20", X"0c", X"11", X"4a", X"2c", X"24", X"8f", X"a9", X"95", X"9f", X"c4", X"78",
X"a5", X"e7", X"20", X"21", X"17", X"69", X"65", X"80", X"75", X"00", X"41", X"ac", X"7a", X"4f", X"6e",
X"00", X"00", X"4c", X"20", X"19", X"3f", X"1f", X"99", X"e3", X"24", X"00", X"09", X"43", X"9a", X"61",
X"df", X"46", X"c0", X"94", X"59", X"00", X"22", X"50", X"1c", X"37", X"51", X"28", X"c2", X"ba", X"c0",
X"54", X"5e", X"86", X"97", X"79", X"65", X"40", X"4b", X"1b", X"3c", X"0e", X"3c", X"21", X"14", X"00",
X"68", X"55", X"46", X"69", X"4f", X"8e", X"58", X"d7", X"c4", X"90", X"be", X"f6", X"d9", X"6d", X"7d",
X"7c", X"f3", X"00", X"25", X"00", X"08", X"2f", X"36", X"37", X"3a", X"40", X"75", X"a5", X"c8", X"cb",
X"a2", X"fa", X"d4", X"33", X"1b", X"89", X"51", X"47", X"7b", X"26", X"9d", X"73", X"83", X"a3", X"85",
X"00", X"60", X"84", X"6c", X"24", X"a4", X"ba", X"76", X"12", X"06", X"81", X"b2", X"00", X"c2", X"a0",
X"97", X"d8", X"94", X"ff", X"a5", X"00", X"1a", X"43", X"66", X"ae", X"ad", X"b4", X"b9", X"cc", X"58",
X"59", X"db", X"db", X"b0", X"4f", X"24", X"0e", X"10", X"0c", X"25", X"02", X"36", X"35", X"00", X"00",
X"38", X"14", X"53", X"9b", X"df", X"e1", X"cd", X"9f", X"e7", X"4e", X"99", X"a1", X"dd", X"d7", X"7a",
X"70", X"9b", X"00", X"33", X"15", X"1f", X"3f", X"14", X"31", X"28", X"04", X"25", X"53", X"86", X"c8",
X"de", X"d0", X"ee", X"ce", X"0c", X"36", X"cf", X"c1", X"b4", X"ee", X"66", X"54", X"93", X"3d", X"b2",
X"ca", X"95", X"b8", X"3d", X"21", X"4d", X"23", X"23", X"51", X"73", X"ff", X"55", X"9a", X"b3", X"dc",
X"e3", X"f9", X"dd", X"ff", X"5e", X"00", X"0d", X"42", X"91", X"c1", X"c1", X"d6", X"ef", X"ce", X"44",
X"0b", X"be", X"cc", X"c4", X"c4", X"98", X"2f", X"00", X"26", X"1f", X"00", X"00", X"1e", X"00", X"00",
X"38", X"00", X"af", X"7b", X"ca", X"d9", X"e9", X"d5", X"ce", X"00", X"81", X"fc", X"bc", X"df", X"de",
X"31", X"16", X"00", X"00", X"05", X"00", X"29", X"65", X"2f", X"33", X"00", X"60", X"3f", X"7b", X"88",
X"ef", X"d6", X"b8", X"b8", X"52", X"14", X"ff", X"df", X"ed", X"ff", X"be", X"9a", X"9c", X"61", X"35",
X"f1", X"e7", X"ec", X"0e", X"3e", X"23", X"53", X"80", X"5b", X"51", X"ee", X"7e", X"2f", X"76", X"66",
X"ca", X"f6", X"15", X"7f", X"6c", X"00", X"63", X"96", X"5c", X"5d", X"76", X"9b", X"53", X"43", X"f1",
X"90", X"d4", X"d6", X"a2", X"19", X"10", X"00", X"00", X"16", X"1e", X"00", X"00", X"08", X"00", X"00",
X"32", X"24", X"76", X"6f", X"64", X"ef", X"ff", X"a3", X"91", X"af", X"dd", X"c1", X"fb", X"d2", X"b0",
X"00", X"00", X"04", X"05", X"00", X"0e", X"38", X"56", X"2e", X"16", X"26", X"a5", X"47", X"9c", X"75",
X"a7", X"b7", X"a2", X"07", X"97", X"8d", X"c9", X"e9", X"58", X"a6", X"ff", X"ca", X"96", X"96", X"f9",
X"be", X"e9", X"e7", X"00", X"4c", X"75", X"6a", X"37", X"9b", X"f1", X"be", X"94", X"58", X"55", X"d2",
X"47", X"c4", X"14", X"e7", X"e1", X"3d", X"2a", X"5d", X"4a", X"65", X"57", X"7f", X"27", X"00", X"b5",
X"8d", X"c7", X"c2", X"ff", X"3b", X"00", X"00", X"00", X"36", X"1f", X"00", X"00", X"00", X"30", X"5f",
X"1c", X"61", X"5c", X"72", X"82", X"bc", X"29", X"ad", X"b6", X"9d", X"95", X"cb", X"cb", X"d4", X"14",
X"29", X"05", X"02", X"17", X"16", X"0d", X"28", X"00", X"2d", X"07", X"88", X"a7", X"b8", X"5f", X"40",
X"79", X"88", X"a4", X"c9", X"cd", X"b2", X"ed", X"b1", X"54", X"1b", X"b9", X"d6", X"84", X"6d", X"93",
X"bc", X"b8", X"f6", X"8b", X"25", X"35", X"0a", X"b1", X"7b", X"c7", X"e1", X"77", X"ab", X"53", X"45",
X"49", X"be", X"f4", X"c0", X"c4", X"5a", X"19", X"0f", X"3a", X"6c", X"7f", X"2c", X"37", X"50", X"b5",
X"a4", X"98", X"60", X"a0", X"e9", X"24", X"00", X"00", X"20", X"00", X"00", X"00", X"00", X"56", X"53",
X"6c", X"66", X"41", X"4a", X"20", X"2e", X"39", X"b8", X"c2", X"d9", X"a8", X"c9", X"91", X"b0", X"2c",
X"1e", X"06", X"1a", X"28", X"25", X"18", X"13", X"1d", X"11", X"11", X"20", X"3e", X"00", X"25", X"48",
X"53", X"7b", X"2d", X"9d", X"b6", X"bb", X"b3", X"ce", X"6f", X"e6", X"c2", X"da", X"99", X"7d", X"a4",
X"66", X"3a", X"e4", X"f2", X"35", X"00", X"24", X"53", X"6f", X"ff", X"d0", X"3d", X"00", X"07", X"00",
X"4a", X"a0", X"b7", X"e7", X"a3", X"4f", X"4d", X"50", X"50", X"70", X"41", X"00", X"66", X"00", X"69",
X"d0", X"22", X"06", X"35", X"b3", X"5e", X"48", X"2b", X"16", X"03", X"0c", X"1b", X"09", X"42", X"3b",
X"1b", X"22", X"25", X"5d", X"60", X"32", X"17", X"28", X"ba", X"c2", X"43", X"56", X"e2", X"9d", X"74",
X"2c", X"21", X"0d", X"00", X"12", X"00", X"06", X"0b", X"00", X"1b", X"03", X"00", X"20", X"29", X"0e",
X"04", X"00", X"4b", X"65", X"b9", X"a2", X"a6", X"a1", X"ff", X"d7", X"8a", X"86", X"76", X"63", X"22",
X"36", X"3a", X"50", X"ff", X"96", X"0a", X"3e", X"44", X"00", X"e4", X"00", X"39", X"2f", X"0d", X"20",
X"27", X"6f", X"85", X"ce", X"26", X"40", X"45", X"6c", X"89", X"2f", X"00", X"2b", X"00", X"0e", X"1e",
X"53", X"05", X"02", X"16", X"5d", X"be", X"0f", X"12", X"09", X"0f", X"00", X"00", X"00", X"3b", X"37",
X"30", X"1b", X"0c", X"54", X"73", X"12", X"0f", X"00", X"0f", X"a6", X"29", X"56", X"36", X"d1", X"6e",
X"30", X"00", X"03", X"09", X"11", X"00", X"00", X"14", X"00", X"1f", X"09", X"0f", X"29", X"19", X"08",
X"19", X"30", X"00", X"00", X"fa", X"e3", X"c3", X"ec", X"a0", X"ff", X"98", X"7d", X"4f", X"02", X"0f",
X"ff", X"d6", X"29", X"e6", X"1e", X"33", X"58", X"45", X"03", X"00", X"0f", X"5b", X"25", X"1c", X"54",
X"2d", X"5c", X"68", X"ac", X"00", X"38", X"49", X"95", X"75", X"00", X"67", X"27", X"00", X"1d", X"2a",
X"0c", X"05", X"10", X"1d", X"00", X"4d", X"00", X"16", X"20", X"10", X"00", X"04", X"05", X"52", X"69",
X"4f", X"00", X"00", X"00", X"5a", X"63", X"1c", X"0d", X"56", X"6d", X"43", X"15", X"c6", X"b1", X"a2",
X"66", X"00", X"02", X"17", X"05", X"04", X"03", X"0f", X"12", X"1e", X"02", X"00", X"35", X"47", X"00",
X"14", X"46", X"14", X"29", X"e5", X"d5", X"ff", X"df", X"63", X"ff", X"d5", X"b2", X"74", X"05", X"ab",
X"c2", X"aa", X"28", X"70", X"44", X"31", X"7a", X"36", X"2f", X"00", X"1b", X"31", X"2e", X"23", X"32",
X"37", X"3b", X"38", X"42", X"00", X"2b", X"77", X"74", X"00", X"42", X"52", X"00", X"05", X"18", X"12",
X"18", X"00", X"00", X"00", X"52", X"00", X"57", X"03", X"08", X"00", X"00", X"00", X"0b", X"60", X"67",
X"17", X"0e", X"05", X"06", X"01", X"48", X"03", X"0a", X"49", X"4e", X"61", X"8c", X"da", X"e0", X"60",
X"6b", X"53", X"00", X"00", X"04", X"00", X"13", X"13", X"0e", X"0e", X"05", X"00", X"35", X"00", X"0b",
X"27", X"0b", X"20", X"0b", X"40", X"ac", X"5d", X"2c", X"10", X"73", X"cb", X"b3", X"3e", X"13", X"b9",
X"a2", X"d1", X"ff", X"7e", X"da", X"8f", X"86", X"8c", X"e0", X"4e", X"00", X"33", X"2e", X"1a", X"6a",
X"76", X"1a", X"27", X"80", X"00", X"45", X"46", X"00", X"54", X"28", X"09", X"20", X"00", X"00", X"00",
X"1f", X"c4", X"89", X"91", X"11", X"3b", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"5a", X"52",
X"15", X"0a", X"13", X"0e", X"08", X"2a", X"14", X"27", X"4b", X"4f", X"51", X"1f", X"5b", X"bf", X"7d",
X"76", X"10", X"0e", X"00", X"04", X"18", X"0c", X"00", X"19", X"00", X"70", X"b1", X"62", X"b0", X"1f",
X"0b", X"43", X"2c", X"18", X"00", X"55", X"29", X"ef", X"42", X"22", X"04", X"8c", X"93", X"a6", X"b5",
X"c3", X"b7", X"6f", X"78", X"60", X"dc", X"a8", X"55", X"92", X"c5", X"00", X"31", X"1f", X"5c", X"a8",
X"40", X"30", X"3f", X"21", X"05", X"23", X"04", X"1d", X"55", X"31", X"00", X"00", X"00", X"05", X"0c",
X"5d", X"39", X"0a", X"00", X"0f", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"50", X"55",
X"00", X"00", X"00", X"13", X"28", X"1d", X"2c", X"16", X"19", X"11", X"5b", X"4e", X"63", X"17", X"4f",
X"6c", X"62", X"00", X"06", X"00", X"00", X"40", X"11", X"13", X"14", X"b5", X"1e", X"c6", X"f4", X"ff",
X"00", X"1b", X"2b", X"1b", X"6a", X"10", X"21", X"d4", X"ff", X"3f", X"23", X"5d", X"e6", X"77", X"bc",
X"f0", X"b4", X"b6", X"85", X"c3", X"d6", X"5b", X"48", X"c1", X"b7", X"d4", X"ce", X"a5", X"0b", X"45",
X"44", X"1d", X"49", X"34", X"42", X"00", X"16", X"1b", X"28", X"61", X"6f", X"68", X"69", X"0f", X"15",
X"00", X"11", X"48", X"3b", X"35", X"16", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"33", X"27",
X"00", X"00", X"00", X"15", X"2e", X"0b", X"19", X"1f", X"12", X"08", X"9f", X"45", X"6f", X"3d", X"a4",
X"6c", X"00", X"00", X"02", X"0c", X"13", X"4f", X"00", X"09", X"2b", X"a9", X"c7", X"65", X"d4", X"ff",
X"ed", X"09", X"0f", X"67", X"54", X"0c", X"16", X"3a", X"b4", X"13", X"13", X"98", X"84", X"62", X"4e",
X"e4", X"cf", X"e0", X"bb", X"c8", X"d1", X"93", X"10", X"c2", X"bb", X"ff", X"df", X"f1", X"3b", X"2d",
X"2b", X"15", X"25", X"2a", X"38", X"30", X"2b", X"00", X"01", X"20", X"15", X"21", X"6e", X"56", X"3e",
X"39", X"09", X"1a", X"0d", X"10", X"00", X"26", X"25", X"10", X"00", X"00", X"00", X"00", X"22", X"23",
X"5a", X"00", X"00", X"00", X"1c", X"00", X"00", X"28", X"00", X"00", X"6d", X"59", X"24", X"00", X"00",
X"1f", X"00", X"00", X"00", X"12", X"4c", X"38", X"00", X"0a", X"17", X"17", X"f3", X"ef", X"bd", X"9e",
X"e6", X"e3", X"a5", X"e0", X"bf", X"04", X"4b", X"ac", X"10", X"26", X"8d", X"12", X"d2", X"ec", X"3b",
X"de", X"cf", X"b6", X"d7", X"d3", X"a1", X"bc", X"56", X"d9", X"e8", X"d7", X"e8", X"c8", X"74", X"00",
X"32", X"11", X"20", X"59", X"40", X"2a", X"17", X"00", X"00", X"00", X"01", X"01", X"36", X"00", X"0c",
X"0a", X"28", X"39", X"10", X"00", X"37", X"35", X"3d", X"36", X"38", X"12", X"0e", X"10", X"12", X"09",
X"5a", X"3b"
);
signal clock_counter : natural := 0;
signal clock_counter_stop : natural := 0;
signal errors_nb : natural := 0;
-- Defined in VHDL 2008, not handled by GHDL
function to_string(sv: std_logic_vector) return string is
variable bv: bit_vector(sv'range) := to_bitvector(sv);
variable lp: line;
begin
write(lp, bv);
return lp.all;
end;
begin
-- Instantiation of the main component
top_i : top port map (
-- Access 'clock' model 'clock'
clock => clock,
-- Access 'reset' model 'reset'
reset => reset,
-- Access 'start' model 'start'
start => start,
-- Access 'stdin' model 'fifo_in'
stdin_data => stdin_data,
stdin_rdy => stdin_rdy,
stdin_ack => stdin_ack,
-- Access 'stdout' model 'fifo_out'
stdout_data => stdout_data,
stdout_rdy => stdout_rdy,
stdout_ack => stdout_ack
);
-- Functionality for top-level access 'clock' model 'clock'
-- Generation of clock: 100MHz (note: arbitrary value)
clock <= clock_next after 5 ns;
clock_next <= not clock when clock_counter_stop = 0 or clock_counter <= clock_counter_stop else '0';
-- Clock counter and global messages
process (clock)
-- To print simulation messages
variable l : line;
begin
-- Increment clock counter
if rising_edge(clock) then
clock_counter <= clock_counter + 1;
if simu_disp_cycles = '1' then
-- Write simulation message
write(l, string'("INFO clock cycle "));
write(l, clock_counter);
writeline(output, l);
end if;
end if;
-- Messages
if falling_edge(clock) then
if clock_counter > simu_max_cycles then
report "ERROR Too many cycles simulated. Stopping simulation." severity failure;
end if;
if clock_counter < reset_cycles then
report "INFO Reset" severity note;
end if;
if clock_counter = reset_cycles then
report "INFO Start" severity note;
end if;
end if;
end process;
-- Functionality for top-level access 'reset' model 'reset'
-- Generation of reset
reset <= '1' when clock_counter < reset_cycles else '0';
-- Functionality for top-level access 'start' model 'start'
-- Generation of start
start <= '1';
-- Functionality for top-level access 'stdin' model 'fifo_in'
-- FIFO stdin
-- Sending inputs
stdin_vector <= stdin_vectors(stdin_vector_idx) when stdin_vector_idx < stdin_vectors_nb else (others => '0');
stdin_data <= stdin_vector(7 downto 0);
stdin_ack <= '1' when reset = '0' and stdin_vector_idx < stdin_vectors_nb else '0';
process (clock)
-- To print simulation messages
variable l : line;
begin
if rising_edge(clock) then
if stdin_vector_idx < stdin_vectors_nb then
if stdin_rdy = '1' and stdin_ack = '1' and reset = '0' then
-- Write simulation message
write(l, string'("INFO Input vector "));
write(l, stdin_vector_idx);
write(l, string'(" at cycle "));
write(l, clock_counter);
writeline(output, l);
if stdin_vector_idx = 0 then
write(l, string'("INFO First input vector sent at clock cycle "));
write(l, clock_counter);
writeline(output, l);
end if;
if stdin_vector_idx = stdin_vectors_nb - 1 then
write(l, string'("INFO Last input vector sent at clock cycle "));
write(l, clock_counter);
writeline(output, l);
end if;
-- Increase vector index
stdin_vector_idx <= stdin_vector_idx + 1;
end if; -- Handshake
else
if stdin_rdy = '1' and reset = '0' then
if simu_err_end_in = '1' then
report "ERROR Out of input vectors. Stopping simulation." severity failure;
end if;
end if; -- Handshake
end if;
end if;
end process;
-- Functionality for top-level access 'stdout' model 'fifo_out'
-- FIFO stdout
-- Checking outputs
-- Always enable output FIFO
stdout_ack <= '1' when stdout_vector_idx < stdout_vectors_nb and reset = '0' else '0';
stdout_vector <= stdout_vectors(stdout_vector_idx) when stdout_vector_idx < stdout_vectors_nb else (others => '0');
-- Check outputs
process (clock)
variable l : line;
begin
if rising_edge(clock) then
if stdout_vector_idx < stdout_vectors_nb then
if stdout_rdy = '1' and stdout_ack = '1' and reset = '0' then
if stdout_data = stdout_vector(7 downto 0) then
-- The vector is verified
write(l, string'("INFO Output nb "));
write(l, stdout_vector_idx);
write(l, string'(" at cycle "));
write(l, clock_counter);
write(l, string'(" (check OK)"));
write(l, string'(" Obtained "));
write(l, to_string(stdout_data));
writeline(output, l);
else
-- An error is detected
write(l, string'("ERROR Output nb "));
write(l, stdout_vector_idx);
write(l, string'(" at cycle "));
write(l, clock_counter);
writeline(output, l);
write(l, string'(" Obtained "));
write(l, to_string(stdout_data));
writeline(output, l);
write(l, string'(" Expected "));
write(l, to_string(stdout_vector(7 downto 0)));
writeline(output, l);
errors_nb <= errors_nb + 1;
--report "ERROR A simulation error was found." severity failure;
end if;
if stdout_vector_idx = stdout_vectors_nb - 1 then
write(l, string'("INFO Last output vector read at cycle "));
write(l, clock_counter);
writeline(output, l);
report "INFO Stopping simulation." severity note;
clock_counter_stop <= clock_counter + 3;
end if;
-- Increase vector index
stdout_vector_idx <= stdout_vector_idx + 1;
end if; -- FIFO handshake
else
-- All vectors have been read
if errors_nb > 0 then
write(l, string'("ERROR Number of errors found : "));
write(l, errors_nb);
writeline(output, l);
report "ERROR Simulation errors were found." severity failure;
end if;
end if; -- Check all vectors read
end if; -- Clock
end process;
end augh;
| gpl-2.0 | 7f0d238ae315f85fd048a36ca45687df | 0.431363 | 1.603222 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth8/test4.vhdl | 1 | 570 | library ieee;
use ieee.std_logic_1164.all;
entity test4 is
port (led: out std_logic_vector (7 downto 0);
rst : std_logic;
clk : std_logic);
end test4;
architecture synth of test4 is
signal int : std_logic_vector(1 downto 0);
begin
-- led(7) <= '0';
-- led(6) <= '1';
-- led(5) <= '0';
-- led(3 downto 0) <= x"9";
-- int(0) <= '0';
process (clk) is
begin
if rst = '1' then
int(1) <= '0';
elsif rising_edge (clk) then
int(1) <= not int(1);
end if;
end process;
led(5) <= int (1);
-- led(4) <= int(0);
end synth;
| gpl-2.0 | 52b8e89c6d34210fa2dbede136632993 | 0.538596 | 2.614679 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc441.vhd | 4 | 5,599 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc441.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00441ent IS
END c03s02b01x01p19n01i00441ent;
ARCHITECTURE c03s02b01x01p19n01i00441arch OF c03s02b01x01p19n01i00441ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
function complex_scalar(s : record_cons_arrayofarray) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_cons_arrayofarray is
begin
return C53;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_cons_arrayofarray;
signal S2 : record_cons_arrayofarray;
signal S3 : record_cons_arrayofarray := C53;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C53) and (S2 = C53))
report "***PASSED TEST: c03s02b01x01p19n01i00441"
severity NOTE;
assert ((S1 = C53) and (S2 = C53))
report "***FAILED TEST: c03s02b01x01p19n01i00441 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00441arch;
| gpl-2.0 | 1cb3f47e8073764842489b87d3dab2e3 | 0.635471 | 3.808844 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_08.vhd | 4 | 2,719 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_08.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_08 is
end entity ch_03_08;
architecture test of ch_03_08 is
begin
process_03_2_c : process is
-- code from book:
type opcodes is
(nop, add, subtract, load, store, jump, jumpsub, branch, halt);
subtype control_transfer_opcodes is opcodes range jump to branch;
-- end of code from book
variable opcode : opcodes;
variable operand : integer;
constant memory_operand : integer := 1;
constant address_operand : integer := 2;
begin
for i in opcodes loop
opcode := i;
-- code from book:
case opcode is
when load | add | subtract =>
operand := memory_operand;
when store | jump | jumpsub | branch =>
operand := address_operand;
when others =>
operand := 0;
end case;
--
case opcode is
when add to load =>
operand := memory_operand;
when branch downto store =>
operand := address_operand;
when others =>
operand := 0;
end case;
-- end of code from book
case opcode is
when add to load =>
operand := memory_operand;
-- code from book: (MTI bug mt011)
-- when control_transfer_opcodes | store =>
-- operand := address_operand;
-- end of code from book
when others =>
operand := 0;
end case;
end loop;
wait;
end process process_03_2_c;
end architecture test;
| gpl-2.0 | 369bf2b8b66930744fd87d05559d1e68 | 0.539904 | 4.696028 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/w_split2.vhd | 2 | 1,359 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split2 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split2;
architecture augh of w_split2 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 0b9839d67fa435bc836dfb8d09d03fb9 | 0.66961 | 2.843096 | false | false | false | false |
tgingold/ghdl | testsuite/synth/case01/case05.vhdl | 1 | 438 | library ieee;
use ieee.std_logic_1164.all;
entity case05 is
port (
in_en : std_logic;
in_v : std_logic_vector(3 downto 0)
);
end entity case05;
architecture behav of case05 is
begin
process(in_en, in_v)
variable l : boolean;
begin
if in_en = '1' then
case in_v is
when "0010" =>
l := in_v = "0000";
when others =>
report "illegal";
end case;
end if;
end process;
end architecture behav;
| gpl-2.0 | 2b26b0fe43c0703874ed6d72d2446088 | 0.618721 | 2.844156 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0105/econcat2.vhdl | 1 | 355 | entity econcat2 is
end econcat2;
architecture behav of econcat2 is
constant c1 : string (1 to 5) := "hello";
constant c2 : string (6 downto 1) := " world";
constant r : string := c1 & c2;
begin
process
begin
case True is
when "&" (c1, c2) = "hello world" => null;
when false => null;
end case;
wait;
end process;
end;
| gpl-2.0 | 6efe4087cebe90b53e28944245ca6b8a | 0.605634 | 3.287037 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr-b.vhd | 4 | 1,632 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_regmpr-b.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
architecture behavior of reg_multiple_plus_one_out_reset is
begin
reg: process ( d, latch_en, out_en, reset )
is
variable latched_value : dlx_word;
begin
if To_bit(reset) = '1' then
latched_value := X"0000_0000";
elsif To_bit(latch_en) = '1' then
latched_value := To_X01(d);
end if;
q0 <= latched_value after Tpd;
for index in out_en'range loop
if To_bit(out_en(index)) = '1' then
q(index) <= latched_value after Tpd;
else
q(index) <= disabled_dlx_word after Tpd;
end if;
end loop;
end process reg;
end architecture behavior;
| gpl-2.0 | 3cf6e436a229cb8707c55295bbb039aa | 0.621936 | 3.795349 | false | false | false | false |
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