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tgingold/ghdl | testsuite/gna/issue50/vector.d/cp3_test.vhd | 4 | 7,118 | -- written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity cp3_test is
port(
clock : in std_logic;
reset : in std_logic;
n_error : out std_logic;
stopped : out std_logic
);
end cp3_test;
architecture rtl of cp3_test is
--TOP signals
signal reset_top : std_logic := '0';
signal stdin_data : stdin_vector;
signal stdin_rdy : std_logic;
signal stdin_ack : std_logic;
signal stdout_data : stdout_vector;
signal stdout_rdy : std_logic;
signal stdout_ack : std_logic;
--ASSERT_UNIT signals
signal context_uut : context_t;
signal en_feed : std_logic;
signal en_check : std_logic;
signal n_error_s : std_logic;
signal vecs_found : std_logic;
signal vec_read : std_logic;
--PROG unit signals
signal instr_next : instruction;
-- FSM unit signals
signal step : std_logic;
signal start : std_logic;
-- FSM signals
signal reset_fsm : std_logic;
signal stopped_s : std_logic;
--------------------------------------
-- PART OF ARCHITECTURE WITH CP3 --
--TOP signals
signal cp_en : std_logic := '0';
signal cp_rest : std_logic := '0';
signal cp_ok : std_logic;
signal cp_din : cp_vector := (others => '0');
signal cp_dout : cp_vector;
--RAM signals
signal ram_1 : ram_instruction;
signal ram_2 : ram_instruction;
signal address1 : std_logic_vector(12 downto 0) := (others => '0');
signal address2 : std_logic_vector(12 downto 0) := (others => '0');
signal datain : cp_vector := (others => '0');
signal dout1 : cp_vector;
signal dout2 : cp_vector;
--dut component declaration
component top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdin_data : in stdin_vector;
stdin_rdy : out std_logic;
stdin_ack : in std_logic;
stdout_data : out stdout_vector;
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
cp_en : in std_logic;
cp_rest : in std_logic;
cp_din : in cp_vector;
cp_dout : out cp_vector;
cp_ok : out std_logic
);
end component top;
begin
uut : entity work.top(augh)
port map(
clock => clock,
reset => reset_top,
start => start,
stdin_data => stdin_data,
stdin_rdy => stdin_rdy,
stdin_ack => stdin_ack,
cp_en => cp_en,
cp_rest => cp_rest,
cp_ok => cp_ok,
cp_din => cp_din,
cp_dout => cp_dout,
stdout_data => stdout_data,
stdout_rdy => stdout_rdy,
stdout_ack => stdout_ack
);
ram1 : entity work.sync_ram(rtl)
port map(
clock => clock,
we => ram_1.we,
address => address1,
datain => datain,
dataout => dout1
);
ram2 : entity work.sync_ram(rtl)
port map(
clock => clock,
we => ram_2.we,
address => address2,
datain => datain,
dataout => dout2
);
fsm_unit : entity work.fsm(rtl)
port map(
clock => clock,
reset => reset,
--prog interface
instr_next => instr_next,
step => step,
--uut interface
cp_ok => cp_ok,
stdin_rdy => stdin_rdy,
stdin_ack => stdin_ack,
reset_fsm => reset_fsm,
start => start,
cp_en => cp_en,
cp_rest => cp_rest,
--ram interface
ram_1 => ram_1,
ram_2 => ram_2,
--assert_uut interface
context_uut => context_uut,
en_feed => en_feed,
en_check => en_check,
vecs_found => vecs_found,
vec_read => vec_read,
--tb interface
stopped => stopped_s
);
--RAM ADDRESS controller 1
ram_ctrl1 : process(clock, reset)
begin
if (reset = '1') then
address1 <= (others => '0');
elsif rising_edge(clock) then
if (ram_1.addr_z = '1') then
address1 <= (others => '0');
elsif (ram_1.addr_up = '1') then
address1 <= std_logic_vector(unsigned(address1) + 1);
end if;
end if;
end process ram_ctrl1;
--RAM ADDRESS controller 2
ram_ctrl2 : process(clock, reset)
begin
if (reset = '1') then
address2 <= (others => '0');
elsif rising_edge(clock) then
if (ram_2.addr_z = '1') then
address2 <= (others => '0');
elsif (ram_2.addr_up = '1') then
address2 <= std_logic_vector(unsigned(address2) + 1);
end if;
end if;
end process ram_ctrl2;
--other comb signals
datain <= cp_dout;
cp_din <= dout2 when ram_2.sel = '1' else dout1;
-- END OF ARCHITECTURE WITH CP3 --
--------------------------------------
--------------------------------------
-- PART OF ARCHITECTURE WITHOUT CP3 --
--
-- --dut component declaration
-- component top is
-- port (
-- clock : in std_logic;
-- reset : in std_logic;
-- start : in std_logic;
-- stdin_data : in stdin_vector;
-- stdin_rdy : out std_logic;
-- stdin_ack : in std_logic;
-- stdout_data : out stdout_vector;
-- stdout_rdy : out std_logic;
-- stdout_ack : in std_logic
-- );
-- end component top;
--
--begin
--
-- uut : entity work.top(augh)
-- port map(
-- clock => clock,
-- reset => reset_top,
-- start => start,
-- stdin_data => stdin_data,
-- stdin_rdy => stdin_rdy,
-- stdin_ack => stdin_ack,
-- stdout_data => stdout_data,
-- stdout_rdy => stdout_rdy,
-- stdout_ack => stdout_ack
-- );
--
-- fsm_unit : entity work.fsm(rtl)
-- port map(
-- clock => clock,
-- reset => reset,
-- --prog interface
-- instr_next => instr_next,
-- step => step,
-- --uut interface
-- cp_ok => '0',
-- stdin_rdy => stdin_rdy,
-- stdin_ack => stdin_ack,
-- reset_fsm => reset_fsm,
-- start => start,
-- cp_en => open,
-- cp_rest => open,
-- --ram interface
-- ram_1 => open,
-- ram_2 => open,
-- --assert_uut interface
-- context_uut => context_uut,
-- en_feed => en_feed,
-- en_check => en_check,
-- vecs_found => vecs_found,
-- vec_read => vec_read,
-- --tb interface
-- stopped => stopped_s
-- );
--
-- END OF ARCHITECTURE WITHOUT CP3 --
--------------------------------------
assert_unit : entity work.assert_uut(rtl)
port map(
clock => clock,
reset => reset,
context_uut => context_uut,
en_feed => en_feed,
stdin_rdy => stdin_rdy,
stdin_ack => stdin_ack,
stdin_data => stdin_data,
en_check => en_check,
stdout_rdy => stdout_rdy,
stdout_ack => stdout_ack,
stdout_data => stdout_data,
vecs_found => vecs_found,
vec_read => vec_read,
n_error => n_error_s
);
prog_unit : entity work.prog(rtl)
port map(
clock => clock,
reset => reset,
step => step,
instr_next => instr_next
);
--other comb signals
reset_top <= reset or reset_fsm;
--outputs
n_error <= n_error_s;
stopped <= stopped_s;
end rtl;
| gpl-2.0 | 9882cd55fa9dadc094efa9d3c15b262a | 0.533436 | 2.90768 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket94/tb4.vhd | 2 | 586 |
library ieee;
use ieee.std_logic_1164.all;
library alib;
entity tb4 is
end;
architecture arch of tb4 is
signal a, b : std_logic := '0';
component acomp is
port (x: in std_ulogic; y: out std_ulogic);
end component;
begin
ainst: acomp
port map (a, b);
process is
begin
a <= '0';
wait for 1 ns;
assert b = '0' report "component is missing" severity failure;
a <= '1';
wait for 1 ns;
assert b = '1' report "component is missing" severity failure;
wait;
end process;
end architecture;
| gpl-2.0 | 7f60c5ba49b468c6fcdb393d262fb6ab | 0.580205 | 3.551515 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug04/std_logic_warning.vhdl | 2 | 1,437 | library ieee;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.to_x01;
use ieee.std_logic_1164.is_x;
package std_logic_warning is
function "="(l, r : std_logic) return boolean;
end package;
package body std_logic_warning is
use ieee.std_logic_1164."=";
function "="(l, r : std_logic) return boolean is
begin
if is_x(l) or is_x(r) then
report "std_logic_warning.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return l = r; -- std_logic_1164."="(l, r);
end function;
end package body;
library ieee;
use ieee.std_logic_1164.std_ulogic;
use ieee.std_logic_1164.std_logic;
-- use ieee.std_logic_1164.all;
use work.std_logic_warning.all;
entity warning_test is
end entity;
architecture foo of warning_test is
signal a: std_logic;
signal b: std_logic;
begin
UNLABELLED:
process
begin
wait for 1 ns;
a <= ieee.std_logic_1164.'X';
wait for 1 ns;
b <= ieee.std_logic_1164.'1';
wait for 1 ns;
a <= ieee.std_logic_1164.'0';
wait for 1 ns;
b <= ieee.std_logic_1164.'0';
wait;
end process;
MONITOR:
process (a,b)
begin
assert a = b
report "a = b " & "( " & std_logic'image(a)
& "=" & std_logic'image(b) & " )"
severity NOTE;
end process;
end architecture;
| gpl-2.0 | 23036bf08127d83a2e5e0a0ba1ea5d98 | 0.581768 | 3.31106 | false | false | false | false |
nickg/nvc | test/sem/error1.vhd | 1 | 599 | entity sub is
port (
x, y : in bit_vector(3 downto 0);
z : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
z <= x & y;
end architecture;
-------------------------------------------------------------------------------
entity elab11 is
end entity;
architecture test of elab11 is
signal a, b : bit_vector(7 downto 0);
begin
sub_i: entity work.sub
port map (
x(0) => '0'; -- Error
x(3 downto 1) => a(7 downto 5),
y => a(5 downto 2),
z => b );
end architecture;
| gpl-3.0 | 3bdace16958e978f6ba68a9002963019 | 0.447412 | 3.864516 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd | 4 | 1,428 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.thermal_systems.all;
entity temperature_dependent_resistor is
port ( terminal n1, n2 : electrical;
quantity temp : in temperature );
end entity temperature_dependent_resistor;
architecture linear_approx of temperature_dependent_resistor is
constant resistance_at_0 : real := 1.0E6;
constant resistance_drop_per_kelvin : real := 100.0;
quantity resistance : real;
quantity V across I through n1 to n2;
begin
resistance == resistance_at_0 - temp * resistance_drop_per_kelvin;
V == I * resistance;
end architecture linear_approx;
| gpl-2.0 | 5d9b6febacd149f1a8744763b2dea733 | 0.7493 | 4.045326 | false | false | false | false |
nickg/nvc | test/regress/issue432.vhd | 1 | 1,809 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity SYNC_DRIVER is
generic (NAME : STRING := ""; DELAY : time := 10 ns; EOT : time := 10 ns);
port (SYNC : inout std_logic);
end SYNC_DRIVER;
architecture MODEL of SYNC_DRIVER is
begin
process begin
SYNC <= 'Z';
wait for 0 ns;
SYNC <= '0';
wait for DELAY;
SYNC <= 'H';
assert FALSE report NAME & " WAIT SYNC START" severity NOTE;
wait until (SYNC = '1' or SYNC = 'H');
SYNC <= '0';
assert FALSE report NAME & " WAIT SYNC DONE " severity NOTE;
assert (Now = EOT) report NAME & " SYNC TIME ERROR" severity ERROR;
wait;
end process;
end MODEL;
library ieee;
use ieee.std_logic_1164.all;
entity SYNC_A is port(SYNC: inout std_logic); end entity;
architecture MODEL of SYNC_A is
begin
U: entity WORK.SYNC_DRIVER generic map (string'("SYNC_A"), 10 ns, 30 ns) port map(SYNC);
end MODEL;
library ieee;
use ieee.std_logic_1164.all;
entity SYNC_B is port(SYNC: inout std_logic); end entity;
architecture MODEL of SYNC_B is
begin
U: entity WORK.SYNC_DRIVER generic map (string'("SYNC_B"), 20 ns, 30 ns) port map(SYNC);
end MODEL;
library ieee;
use ieee.std_logic_1164.all;
entity SYNC_C is port(SYNC: inout std_logic); end entity;
architecture MODEL of SYNC_C is
begin
U: entity WORK.SYNC_DRIVER generic map (string'("SYNC_C"), 30 ns, 30 ns) port map(SYNC);
end MODEL;
library ieee;
use ieee.std_logic_1164.all;
entity issue432 is
end issue432;
architecture MODEL of issue432 is
signal SYNC : std_logic;
begin
U_SYNC_A: entity WORK.SYNC_A port map(SYNC);
U_SYNC_B: entity WORK.SYNC_B port map(SYNC);
U_SYNC_C: entity WORK.SYNC_C port map(SYNC);
end MODEL;
| gpl-3.0 | 7ddc4c1b9862785bb933d0e73b8958dc | 0.63958 | 3.313187 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispout01/rec06.vhdl | 1 | 319 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rec06_pkg.all;
entity rec06 is
port (inp : std_logic;
o : out myrec);
end rec06;
architecture behav of rec06 is
begin
o.b <= not inp;
o.a.c <= 2 when inp = '1' else 3;
o.a.d <= "0000" when inp = '0' else "1000";
end behav;
| gpl-2.0 | c221ffb1e903fd9ea61c36e8fecf60c2 | 0.636364 | 2.614754 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue2/sortnet_BitonicSort_tb.vhdl | 2 | 3,680 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: Sorting Network: Bitonic-Sort
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.packages.all;
entity sortnet_BitonicSort_tb is
end entity;
architecture tb of sortnet_BitonicSort_tb is
constant INPUTS : POSITIVE := 8;
constant KEY_BITS : POSITIVE := 8;
constant DATA_BITS : POSITIVE := 8;
subtype T_KEY is STD_LOGIC_VECTOR(KEY_BITS - 1 downto 0);
type T_KEY_VECTOR is array(NATURAL range <>) of T_KEY;
function to_kv(slm : T_SLM) return T_KEY_VECTOR is
variable Result : T_KEY_VECTOR(slm'range(1));
begin
for i in slm'high(1) downto slm'low(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(i)(j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_slm(kv : T_KEY_VECTOR) return T_SLM is
variable Result : T_SLM(kv'range, T_KEY'range);
begin
for i in kv'range loop
for j in T_KEY'range loop
Result(i, j) := kv(i)(j);
end loop;
end loop;
return Result;
end function;
constant CLOCK_PERIOD : TIME := 10 ns;
signal Clock : STD_LOGIC := '1';
signal KeyInputVector : T_KEY_VECTOR(INPUTS - 1 downto 0) := (others => (others => '0'));
signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal KeyOutputVector : T_KEY_VECTOR(INPUTS - 1 downto 0);
signal StopSimulation : STD_LOGIC := '0';
begin
Clock <= Clock xnor StopSimulation after CLOCK_PERIOD;
process
begin
wait until rising_edge(Clock);
for i in 0 to 63 loop
wait until rising_edge(Clock);
for j in 0 to INPUTS - 1 loop
KeyInputVector(j) <= std_logic_vector(unsigned(KeyInputVector(j)) + i + j);
end loop;
end loop;
for i in 0 to 7 loop
wait until rising_edge(Clock);
end loop;
StopSimulation <= '1';
wait;
end process;
DataInputMatrix <= to_slm(KeyInputVector);
sort : entity work.sortnet_BitonicSort
generic map (
INPUTS => INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS
)
port map (
Clock => Clock,
Reset => '0',
DataInputs => DataInputMatrix,
DataOutputs => DataOutputMatrix
);
KeyOutputVector <= to_kv(DataOutputMatrix);
process
begin
wait;
end process;
end architecture;
| gpl-2.0 | 045a4417ad6534a53444c2337284da1e | 0.595109 | 3.391705 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket94/tb3.vhd | 2 | 502 |
library ieee;
use ieee.std_logic_1164.all;
library alib;
entity tb3 is
end;
architecture arch of tb3 is
signal a, b : std_logic := '0';
begin
ainst: alib.apkg.acomp
port map (a, b);
process is
begin
a <= '0';
wait for 1 ns;
assert b = '0' report "component is missing" severity failure;
a <= '1';
wait for 1 ns;
assert b = '1' report "component is missing" severity failure;
wait;
end process;
end architecture;
| gpl-2.0 | 90909d2ce4906fbc70c39c72a399de44 | 0.579681 | 3.462069 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug090/crash5.vhdl | 1 | 1,216 | library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
rst_n : in std_logic;
d : std_logic_vector (len - 1 downto 0);
q : out std_logic_vector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process p;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : s;
signal rst_n : std_logic;
signal din, dout : std_logic_vector (7 downto 0);
begin
mydff : entity wor{.dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout);
rst_n <= '0' after 0 ns, '1' after 4 ns;
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report "start of tb" severity note;
for i in din'range loop
din(i) <= '0';
end loop;
wait until clk = '0';
end process;
assert false report "Hello world" severity note;
end behav;
| gpl-2.0 | 03e5c2f701ed4fa45a96a83f5bd9d050 | 0.569901 | 3.208443 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc546.vhd | 4 | 3,386 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc546.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n01i00546ent IS
END c03s04b00x00p03n01i00546ent;
ARCHITECTURE c03s04b00x00p03n01i00546arch OF c03s04b00x00p03n01i00546ent IS
BEGIN
TESTING: PROCESS
-- Enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
type FT1 is file of SWITCH_LEVEL;
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
type FT2 is file of SWITCH_LEVEL;
-- array types. Unconstrained.
type MEMORY is array(INTEGER range <>) of BIT;
type FT3 is file of MEMORY;
-- array types. Constrained.
type WORD is array(0 to 31) of BIT;
type FT4 is file of WORD;
-- record types.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
type FT5 is file of DATE;
-- INTEGER types.
type FT6 is file of INTEGER;
type POSITIVE is range 0 to INTEGER'HIGH;
type FT7 is file of POSITIVE;
-- Physical types.
type FT8 is file of TIME;
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
type FT10 is file of DISTANCE;
-- floating point types.
type FT11 is file of REAL;
type POSITIVE_R is range 0.0 to REAL'HIGH;
type FT12 is file of POSITIVE_R;
-- Predefined enumerated types.
type FT13 is file of BIT;
type FT14 is file of SEVERITY_LEVEL;
type FT15 is file of BOOLEAN;
type FT16 is file of CHARACTER;
-- Other predefined types.
type FT17 is file of NATURAL;
type FT18 is file of STRING;
type FT19 is file of BIT_VECTOR;
BEGIN
assert FALSE
report "***PASSED TEST: c03s04b00x00p03n01i00546"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n01i00546arch;
| gpl-2.0 | 86fee6ccc4bdb77e89ed587ff4bd51bb | 0.606911 | 3.900922 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd | 4 | 1,975 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
begin
process_1_c : process is
type mode_type is (immediate, other_mode);
type opcode_type is (load, add, subtract, other_opcode);
variable mode : mode_type;
variable opcode : opcode_type;
constant immed_operand : integer := 1;
constant memory_operand : integer := 2;
constant address_operand : integer := 3;
variable operand : integer;
procedure procedure_1_c is
begin
-- code from book:
if mode = immediate then
operand := immed_operand;
elsif opcode = load or opcode = add or opcode = subtract then
operand := memory_operand;
else
operand := address_operand;
end if;
-- end of code from book
end procedure_1_c;
begin
mode := immediate;
procedure_1_c;
mode := other_mode;
opcode := load;
procedure_1_c;
opcode := add;
procedure_1_c;
opcode := subtract;
procedure_1_c;
opcode := other_opcode;
procedure_1_c;
wait;
end process process_1_c;
end architecture test;
| gpl-2.0 | 262868f083ef2fb69becb8289d9bfe88 | 0.650127 | 4.184322 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0109/err.vhdl | 1 | 852 | library ieee;
use ieee.std_logic_1164.all;
use ieee.fixed_pkg.all;
entity phz_calc is
end entity phz_calc;
architecture behavioral of phz_calc is
function to_string (inp: sfixed) return string is
variable image_str: string (1 to inp'length + 1);
variable j: integer range 1 to image_str'length + 1;
begin
j := 1;
for i in inp'range loop
if i = -1 then
image_str(j) := '.';
j := j + 1;
end if;
image_str(j) := character'VALUE(std_ulogic'IMAGE(inp(i)));
j := j + 1;
end loop;
return image_str;
end function;
begin
process
variable z: sfixed (3 downto -3);
begin
z := to_sfixed(3.2,3,-3);
report "z = " & to_string (z);
wait;
end process;
end architecture behavioral;
| gpl-2.0 | b8fcb5cec609cc3f7922dcfb5d5a4f7d | 0.542254 | 3.564854 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1944.vhd | 4 | 4,992 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1944.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01944ent IS
END c07s02b01x00p01n04i01944ent;
ARCHITECTURE c07s02b01x00p01n04i01944arch OF c07s02b01x00p01n04i01944ent IS
BEGIN
TESTING: PROCESS
variable A : bit_vector (1 to 32);
variable B : bit_vector (32 downto 1);
constant AA : bit_vector (1 to 32) := x"0000ffff";
variable C : bit_vector (15 downto 0);
variable D, DD : bit_vector (0 to 15);
variable E : bit_vector (0 to 47);
variable F : bit_vector (47 downto 0);
alias FF : bit_vector (47 downto 0) is F;
BEGIN
A := x"0000ffff";
B := x"00ff00ff";
C := x"00ff";
D := x"0f0f";
E := x"000000ffffff";
F := x"000fff000fff";
assert NOT( (A and B ) = x"000000ff" and
(A or B ) = x"00ffffff" and
(A xor B ) = x"00ffff00" and
(A nand B) = x"ffffff00" and
(A nor B ) = x"ff000000" and
(not A ) = x"ffff0000" and
(AA and B ) = x"000000ff" and
(AA or B ) = x"00ffffff" and
(AA xor B ) = x"00ffff00" and
(AA nand B) = x"ffffff00" and
(AA nor B ) = x"ff000000" and
(not AA ) = x"ffff0000" and
(C and D ) = x"000f" and
(C or D ) = x"0fff" and
(C xor D ) = x"0ff0" and
(C nand D) = x"fff0" and
(C nor D ) = x"f000" and
(not C ) = x"ff00" and
(E and F ) = x"000000000fff" and
(E or F ) = x"000fffffffff" and
(E xor F ) = x"000ffffff000" and
(E nand F) = x"fffffffff000" and
(E nor F ) = x"fff000000000" and
(E and FF ) = x"000000000fff" and
(E or FF ) = x"000fffffffff" and
(E xor FF ) = x"000ffffff000" and
(E nand FF) = x"fffffffff000" and
(E nor FF ) = x"fff000000000" and
(not E ) = x"ffffff000000")
report "***PASSED TEST: c07s02b01x00p01n04i01944"
severity NOTE;
assert ( (A and B ) = x"000000ff" and
(A or B ) = x"00ffffff" and
(A xor B ) = x"00ffff00" and
(A nand B) = x"ffffff00" and
(A nor B ) = x"ff000000" and
(not A ) = x"ffff0000" and
(AA and B ) = x"000000ff" and
(AA or B ) = x"00ffffff" and
(AA xor B ) = x"00ffff00" and
(AA nand B) = x"ffffff00" and
(AA nor B ) = x"ff000000" and
(not AA ) = x"ffff0000" and
(C and D ) = x"000f" and
(C or D ) = x"0fff" and
(C xor D ) = x"0ff0" and
(C nand D) = x"fff0" and
(C nor D ) = x"f000" and
(not C ) = x"ff00" and
(E and F ) = x"000000000fff" and
(E or F ) = x"000fffffffff" and
(E xor F ) = x"000ffffff000" and
(E nand F) = x"fffffffff000" and
(E nor F ) = x"fff000000000" and
(E and FF ) = x"000000000fff" and
(E or FF ) = x"000fffffffff" and
(E xor FF ) = x"000ffffff000" and
(E nand FF) = x"fffffffff000" and
(E nor FF ) = x"fff000000000" and
(not E ) = x"ffffff000000")
report "***FAILED TEST: c07s02b01x00p01n04i01944 - One dimensional array type logical operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01944arch;
| gpl-2.0 | cd775c92d9a8c0add0c9b3b64cfde406 | 0.48758 | 3.457064 | false | false | false | false |
tgingold/ghdl | testsuite/synth/psl02/assert1.vhdl | 1 | 545 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity assert1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end assert1;
architecture behav of assert1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
end behav;
vunit verif1 (assert1)
{
default clock is rising_edge(clk);
assert always cnt /= 5 abort rst;
}
| gpl-2.0 | dcc45e6125a0080d322da634a2b1c091 | 0.631193 | 3.150289 | false | false | false | false |
makestuff/comm-fpga | fx2/vhdl/tb_unit/comm_fpga_fx2_tb.vhdl | 1 | 6,350 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity comm_fpga_fx2_tb is
end entity;
architecture behavioural of comm_fpga_fx2_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns
-- External interface ---------------------------------------------------------------------------
signal fx2FifoSel : std_logic; -- comm_fpga_fx2 drives fx2FifoSel='0' to read from EP6OUT, and fx2FifoSel='1' to write to EP8IN
signal fx2Data : std_logic_vector(7 downto 0); -- data to/from the FX2
-- When EP6OUT selected:
signal fx2Read : std_logic; -- comm_fpga_fx2 drives fx2Read='1' telling FX2 to commit data out of the EP6OUT FIFO
signal fx2GotData : std_logic; -- FX2 drives '1' when fx2FifoSel='0' and there is some data in the EP6OUT FIFO
-- When EP8IN selected:
signal fx2Write : std_logic; -- comm_fpga_fx2 drives fx2Write='1' telling FX2 to commit data into the EP8IN FIFO
signal fx2GotRoom : std_logic; -- FX2 drives '1' when fx2FifoSel='1' and there is room in the EP8IN FIFO
signal fx2PktEnd : std_logic; -- comm_fpga_fx2 drives fx2PktEnd='1' to commit an EP8IN packet early
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- comm_fpga_fx2 selects one of 128 channels to access
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data to be read from the selected channel
signal h2fValid : std_logic; -- comm_fpga_fx2 drives h2fValid='1' when it wants to write to the selected channel
signal h2fReady : std_logic; -- this must be driven high if the selected channel has room for data to be written to it
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data to be written to the selected channel
signal f2hValid : std_logic; -- this must be asserted if the selected channel has data available for reading
signal f2hReady : std_logic; -- comm_fpga_fx2 drives f2hReady='1' when it wants to read from the selected channel
begin
-- Instantiate comm_fpga_fx2 for testing
uut: entity work.comm_fpga_fx2
port map(
clk_in => sysClk,
reset_in => '0',
reset_out => open,
-- FX2 interface --------------------------------------------------------------------------
fx2FifoSel_out => fx2FifoSel,
fx2Data_io => fx2Data,
fx2Read_out => fx2Read, -- when EP6OUT selected
fx2GotRoom_in => fx2GotRoom, -- /
fx2Write_out => fx2Write, -- \
fx2GotData_in => fx2GotData, -- when EP8IN selected
fx2PktEnd_out => fx2PktEnd, -- /
-- Channel read/write interface -----------------------------------------------------------
chanAddr_out => chanAddr, -- which channel to connect the pipes to
f2hData_in => f2hData, -- \
f2hValid_in => f2hValid, -- Host >> FPGA pipe
f2hReady_out => f2hReady, -- /
h2fData_out => h2fData, -- \
h2fValid_out => h2fValid, -- Host << FPGA pipe
h2fReady_in => h2fReady -- /
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time for
-- signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '1';
wait for 10 ns;
dispClk <= '0';
wait for 10 ns;
loop
dispClk <= '1';
wait for 4 ns;
sysClk <= '1';
wait for 6 ns;
dispClk <= '0';
wait for 4 ns;
sysClk <= '0';
wait for 6 ns;
end loop;
end process;
-- Drive the FX2 side
process
begin
fx2Data <= (others => 'Z');
fx2GotData <= '0';
fx2GotRoom <= '1';
wait until sysClk = '1';
wait until sysClk = '0';
wait until sysClk = '1';
fx2Data <= x"55";
fx2GotData <= '1';
wait until rising_edge(sysClk);
fx2Data <= x"00";
wait until rising_edge(sysClk);
fx2Data <= x"04";
wait until rising_edge(sysClk);
fx2Data <= x"12";
wait until rising_edge(sysClk);
fx2Data <= x"34";
wait until rising_edge(sysClk);
fx2Data <= (others => 'Z');
wait until rising_edge(sysClk);
fx2Data <= x"56";
wait until rising_edge(sysClk);
fx2Data <= x"78";
wait until rising_edge(sysClk);
fx2Data <= (others => 'Z');
fx2GotData <= '0';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
fx2Data <= x"AA";
fx2GotData <= '1';
wait until rising_edge(sysClk);
fx2Data <= x"00";
wait until rising_edge(sysClk);
fx2Data <= x"04";
wait until rising_edge(sysClk);
fx2GotData <= '0';
fx2Data <= (others => 'Z');
wait;
end process;
-- Drive the internal side
process
begin
-- Host << FPGA data is invalid for now
f2hData <= (others => '0');
f2hValid <= '0';
-- We're ready for Host >> FPGA data
h2fReady <= '1';
-- Wait until some Host >> FPGA data arrives, then deassert h2fReady to test throttling
wait until h2fValid = '1';
wait for 40 ns;
h2fReady <= '0';
wait for 20 ns;
h2fReady <= '1';
-- Wait for the Host << FPGA pipe to become ready, then drive some data, with a hole in the
-- middle again to test the throttling.
wait until f2hReady = '1';
f2hData <= x"87";
f2hValid <= '1';
wait for 20 ns;
f2hData <= x"65";
wait for 20 ns;
f2hData <= (others => 'Z');
f2hValid <= '0';
wait for 20 ns;
f2hData <= x"43";
f2hValid <= '1';
wait for 20 ns;
f2hData <= x"21";
wait for 20 ns;
f2hData <= (others => '0');
f2hValid <= '0';
wait;
end process;
end architecture;
| gpl-3.0 | afd304e7f97cbce7cf35703668dd9bd2 | 0.627244 | 3.182957 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd | 4 | 2,150 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity bulk_cmos_nfet is
generic ( Vt : real;
transconductance : real );
port ( terminal gate, drain, source : electrical );
end entity bulk_cmos_nfet;
architecture basic of bulk_cmos_nfet is
begin
end architecture basic;
architecture detailed of bulk_cmos_nfet is
begin
end architecture detailed;
-- code from book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp is
port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
end entity opamp;
----------------------------------------------------------------
architecture struct of opamp is
component nfet is
generic ( Vt : real;
transconductance : real );
port ( terminal gate, drain, source : electrical );
end component nfet;
terminal int_1, int_2, int_3, -- ...
-- not in book
other_terminal
-- end not in book
: electrical;
begin
m1 : component nfet
generic map ( Vt => 0.026, transconductance => 1.0 )
port map ( gate => plus_in, drain => int_1, source => int_2 );
m2 : component nfet
generic map ( Vt => 0.026, transconductance => 1.0 )
port map ( gate => minus_in, drain => int_1, source => int_3 );
-- other component instances
-- ...
end architecture struct;
-- end code from book
| gpl-2.0 | 62ed0eb86fcc32dea2cbcd484a16da34 | 0.673488 | 3.974122 | false | false | false | false |
nickg/nvc | test/regress/record27.vhd | 1 | 1,135 | package config is
constant width : integer;
end package;
-------------------------------------------------------------------------------
use work.config.all;
package types is
type pair is record
x, y : integer;
end record;
type pair_vec is array (natural range <>) of pair;
type rec is record
v : pair_vec(1 to width); -- OK
end record;
end package;
-------------------------------------------------------------------------------
package body config is
constant width : integer := 2;
end package body;
-------------------------------------------------------------------------------
entity record27 is
end entity;
use work.types.all;
architecture test of record27 is
signal r : rec;
begin
main: process is
begin
assert r.v'length = 2;
assert r = ( v => (others => (integer'left, integer'left) ) );
r.v <= ( (1, 2), (3, 4) );
wait for 1 ns;
assert r = ( v => ( (1, 2), (3, 4) ) );
r.v(2).x <= 7;
wait for 1 ns;
assert r = ( v => ( (1, 2), (7, 4) ) );
wait;
end process;
end architecture;
| gpl-3.0 | 8ee2c7eaca3e1532597718f43c6015ca | 0.429075 | 4.082734 | false | true | false | false |
snow4life/PipelinedDLX | WB_SIGN_EXT_16.vhd | 1 | 675 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity WB_SIGN_EXT_16 is
port( INPUT: in std_logic_vector(15 downto 0);
SIGN_EXT_CONTROL: in std_logic;
OUTPUT: out std_logic_vector(31 downto 0));
end WB_SIGN_EXT_16;
architecture BEHAVIORAL of WB_SIGN_EXT_16 is
begin
SIGN_EXTENSION_PROCESS: process(INPUT, SIGN_EXT_CONTROL)
begin
if SIGN_EXT_CONTROL = '0' then
-- LHI instruction support
OUTPUT(15 downto 0) <= (others => '0');
OUTPUT(31 downto 16) <= INPUT;
else
-- sign extension
OUTPUT(31 downto 16) <= (31 downto 16 => INPUT(15));
OUTPUT(15 downto 0) <= INPUT;
end if;
end process;
end BEHAVIORAL;
| lgpl-2.1 | e44ac414600d6fdf3874185ecd528fb4 | 0.674074 | 2.860169 | false | false | false | false |
nickg/nvc | test/regress/attr9.vhd | 1 | 1,484 | entity attr9 is
end entity;
architecture test of attr9 is
begin
process is
type my_small_int is range 1 to 10;
type my_enum is (A, B, C, D);
type my_real is range -5.0 to 5.0;
subtype my_sub is my_enum range B to C;
type resistance is range 0 to 10000000
units
ohm;
kohm = 1000 ohm;
mohm = 1000 kohm;
end units;
function "="(l, r : my_real) return boolean is
begin
return l > r - 0.0001 and l < r + 0.0001;
end function;
begin
assert integer'value("1") = 1;
assert integer'value("-1") = -1;
assert natural'value(" 12_3") = 123;
assert my_small_int'value("5 ") = 5;
assert boolean'value("true") = true;
assert boolean'value("FALSE") = false;
assert character'value("'x' ") = 'x';
assert integer'value(integer'image(integer'high)) = integer'high;
assert integer'value(integer'image(integer'low)) = integer'low;
assert my_enum'value("A") = A;
assert my_sub'value(" B ") = B;
assert resistance'value("1 ohm") = 1 ohm;
assert resistance'value("5 ohm") = 5 ohm;
assert resistance'value("1 kohm") = 1000 ohm;
assert resistance'value(" 25 kohm ") = 25_000 ohm;
assert my_real'value("1.23") = 1.23;
assert my_real'value(" 4.2 ") = 4.2;
wait;
end process;
end architecture;
| gpl-3.0 | 6174ef97c3552d6181589f9fe1812023 | 0.540431 | 3.655172 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1180/bug.vhdl | 1 | 563 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
generic(
C_HIGH : natural := 5
);
port(
reset_n : in std_ulogic;
clk : in std_ulogic;
res : out natural
);
end bug;
architecture behav of bug is
subtype st is natural range 0 to C_HIGH;
signal c : st;
begin
process(clk, reset_n)
begin
if reset_n = '0' then
c <= st'low;
elsif rising_edge(clk) then
if c = st'high then
c <= st'low;
else
c <= c + 1;
end if;
end if;
end process;
res <= c;
end architecture;
| gpl-2.0 | b7553227dac4b38a6ac2011a3ed19b07 | 0.59325 | 2.706731 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc440.vhd | 4 | 5,292 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc440.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00440ent IS
END c03s02b01x01p19n01i00440ent;
ARCHITECTURE c03s02b01x01p19n01i00440arch OF c03s02b01x01p19n01i00440ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
function complex_scalar(s : record_2cons_array) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_2cons_array is
begin
return C52;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_2cons_array;
signal S2 : record_2cons_array;
signal S3 : record_2cons_array := C52;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C52) and (S2 = C52))
report "***PASSED TEST: c03s02b01x01p19n01i00440"
severity NOTE;
assert ((S1 = C52) and (S2 = C52))
report "***FAILED TEST: c03s02b01x01p19n01i00440 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00440arch;
| gpl-2.0 | 7f12a8c0a8e1275283541aa52f90b8d0 | 0.617914 | 3.556452 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1140/ent.vhdl | 1 | 1,003 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
generic (NUM_CHANNELS : natural := 4);
port (
iar : in unsigned(15 downto 0);
ipend : in unsigned(NUM_CHANNELS-1 downto 0);
irq : out unsigned(3 downto 0);
clk : in std_logic
);
end;
architecture a of ent is
type irq_t is
array (integer range 0 to 4-1) of unsigned(NUM_CHANNELS-1 downto 0);
signal imap : irq_t;
function or_reduce (v: in unsigned) return std_logic is
variable rv : std_logic := '0';
begin
for i in v'range loop
rv := rv or v(i);
end loop;
return rv;
end function;
begin
gen_irqmap:
for i in 0 to 4-1 generate
irq(i) <= or_reduce(imap(i));
end generate;
irq_map:
process (clk)
variable itmp : irq_t := (others => (others => '0'));
begin
-- IRQ channel assignment:
if rising_edge(clk) then
for i in 0 to NUM_CHANNELS-1 loop
itmp(to_integer(iar(i*2+1 downto i*2)))(i) := ipend(i);
end loop;
imap <= itmp;
end if;
end process;
end;
| gpl-2.0 | 4cbda0685c459b74434ab82fe283e388 | 0.64008 | 2.703504 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue960/tb_ent2.vhdl | 1 | 640 | entity tb_ent2 is
end tb_ent2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent2 is
signal clk : std_logic;
signal dout : std_logic;
begin
dut: entity work.ent2
port map (
o => dout,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wait for 1 ns;
assert dout = '0' severity failure;
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '0' severity failure;
pulse;
assert dout = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | dc512e64595e22baa19a3ac337799d7d | 0.590625 | 3.459459 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue38/bugreport_aliasprotected.vhdl | 1 | 6,351 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Reproducer: Using aliases to protected type methods cause an exception.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
-- Issue 1:
-- When analyzed in VHDL-93 mode an error is reported:
-- .\bugreport_aliasprotected.vhdl:4:26: protected type not allowed in vhdl87/93
-- .\bugreport_aliasprotected.vhdl:9:12: 'protected' is expected instead of 'protected'
-- Line 1 is perfectly clear, but what is the intension of line 2?
-- Is this follow up error necessary or should it have another message text?
--
-- Issue 2:
-- Calling an aliases to a shared variable's method causes an exception in GHDL:
-- ******************** GHDL Bug occurred ****************************
-- Please report this bug on https://github.com/tgingold/ghdl/issues
-- GHDL release: GHDL 0.34dev (commit: 2016-01-27; git branch: paebbels/master'; hash: d424eb8) [Dunoon edition]
-- Compiled with GNAT Version: GPL 2015 (20150428-49)
-- In directory: H:\Austausch\PoC\temp\ghdl\
-- Command line:
-- C:\Tools\GHDL.new\bin\ghdl.exe -r --std=08 test
-- Exception TYPES.INTERNAL_ERROR raised
-- Exception information:
-- Exception name: TYPES.INTERNAL_ERROR
-- Message: trans.adb:487
-- ******************************************************************
-- The alias definition by itself is not causing any errors. In my big example, I
-- could at least use an alias to a procedure without parameters. This short example
-- throws exceptions on all 4 variants (with/without parameter; with/without return value).
--
-- You can comment/uncomment the alias/wrapping function/procedure to cause the error.
--
-- GHDL calls:
-- PS> ghdl.exe -a --std=08 .\bugreport_aliasprotected.vhdl
-- PS> ghdl.exe -r --std=08 test
--
-- Expected output:
-- .\bugreport_aliasprotected.vhdl:163:16:@0ms:(report note): wrapGet: 7 expected: 7
-- .\bugreport_aliasprotected.vhdl:165:16:@0ms:(report note): wrapGet: 5 expected: 5
-- .\bugreport_aliasprotected.vhdl:166:16:@0ms:(report note): wrapExcahnge: 5 expected: 5
-- .\bugreport_aliasprotected.vhdl:167:16:@0ms:(report note): wrapGet: 3 expected: 3
-- .\bugreport_aliasprotected.vhdl:169:16:@0ms:(report note): wrapGet: 0 expected: 0
--
-- =============================================================================
-- Protected type package
-- =============================================================================
package pkg is
type T_INTEGER is protected
procedure Clear;
procedure Set(Value : INTEGER);
impure function Get return INTEGER;
impure function Exchange(Value : INTEGER) return INTEGER;
end protected;
end package;
package body pkg is
type T_INTEGER is protected body
variable LocalVariable : INTEGER := 7;
procedure Clear is
begin
LocalVariable := 0;
end procedure;
procedure Set(Value : INTEGER) is
begin
LocalVariable := Value;
end procedure;
impure function Get return INTEGER is
begin
return LocalVariable;
end function;
impure function Exchange(Value : INTEGER) return INTEGER is
variable Result : INTEGER;
begin
Result := LocalVariable;
LocalVariable := Value;
return Result;
end function;
end protected body;
end package body;
-- =============================================================================
-- Wrapper package
-- =============================================================================
use work.pkg.all;
package wrapper is
shared variable MyBoolean : T_INTEGER;
-- alias wrapClear is MyBoolean.Clear[]; -- if this alias is used, GHDL crashes
alias wrapperClear is MyBoolean.Clear[]; -- unused alias => no crash
procedure wrapClear; -- wrapped by a call chain => no crash
-- alias wrapSet is MyBoolean.Set[INTEGER];
procedure wrapSet(Value : INTEGER);
-- alias wrapGet is MyBoolean.Get[return INTEGER];
impure function wrapGet return INTEGER;
-- alias wrapExchange is MyBoolean.Exchange[INTEGER return INTEGER];
impure function wrapExchange(Value : INTEGER) return INTEGER;
end package;
package body wrapper is
procedure wrapClear is
begin
MyBoolean.Clear;
end procedure;
procedure wrapSet(Value : INTEGER) is
begin
MyBoolean.Set(Value);
end procedure;
impure function wrapGet return INTEGER is
begin
return MyBoolean.Get;
end function;
impure function wrapExchange(Value : INTEGER) return INTEGER is
begin
return MyBoolean.Exchange(Value);
end function;
end package body;
-- =============================================================================
-- Testbench
-- =============================================================================
use work.wrapper.all;
entity test is
end entity;
architecture tb of test is
begin
process
begin
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 7" severity NOTE;
wrapSet(5);
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 5" severity NOTE;
report "wrapExcahnge: " & INTEGER'image(wrapExchange(3)) & " expected: 5" severity NOTE;
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 3" severity NOTE;
wrapperClear;
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 0" severity NOTE;
wait;
end process;
end architecture;
| gpl-2.0 | 33f490dadc79cd2203683c6764fca2ff | 0.615966 | 3.882029 | false | false | false | false |
tgingold/ghdl | libraries/synopsys/std_logic_arith.vhdl | 1 | 70,557 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- --synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- --synopsys synthesis_on
-- --synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- --synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- --synopsys built_in SYN_FEED_THRU
begin
-- --synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- --synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- --synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- --synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- --synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- --synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- --synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- --synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- --synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- --synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- --synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- --synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- --synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- --synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- --synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- --synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- --synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- --synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- --synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- --synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- --synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- --synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- --synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in integer range 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in integer range 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- --synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- --synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- --synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- --synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- --synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- --synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- --synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- --synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- --synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- --synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- --synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- --synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- --synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- --synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- --synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- --synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- --synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- --synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- --synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- --synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- --synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- --synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- --synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- --synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- --synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- --synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- --synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- --synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- --synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- --synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- --synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- --synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- --synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- --synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- --synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- --synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- --synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- --synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- --synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- --synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- --synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- --synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- --synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- --synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- --synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- --synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- --synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- --synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- --synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- --synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- --synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- --synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- --synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- --synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- --synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- --synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- --synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- --synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- --synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- --synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- --synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- --synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- --synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- --synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- --synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- --synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- --synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- --synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- --synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- --synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- --synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- --synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- --synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- --synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- --synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- --synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- --synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- --synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- --synopsys subpgm_id 366
begin
-- --synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end loop;
return result;
-- --synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- --synopsys built_in SYN_SIGNED_TO_INTEGER
-- --synopsys subpgm_id 367
begin
-- --synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- --synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- --synopsys built_in SYN_FEED_THRU
-- --synopsys subpgm_id 370
begin
-- --synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- --synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- --synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- --synopsys subpgm_id 371
begin
-- --synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- --synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_ZERO_EXTEND
-- --synopsys subpgm_id 372
begin
-- --synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- --synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_SIGN_EXTEND
-- --synopsys subpgm_id 373
begin
-- --synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- --synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_ZERO_EXTEND
-- --synopsys subpgm_id 375
begin
-- --synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- --synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- --synopsys built_in SYN_INTEGER_TO_SIGNED
-- --synopsys subpgm_id 376
begin
-- --synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- --synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_ZERO_EXTEND
-- --synopsys subpgm_id 377
begin
-- --synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- --synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_SIGN_EXTEND
-- --synopsys subpgm_id 378
begin
-- --synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- --synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_ZERO_EXTEND
-- --synopsys subpgm_id 380
begin
-- --synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- --synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- --synopsys built_in SYN_INTEGER_TO_SIGNED
-- --synopsys subpgm_id 381
begin
-- --synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- --synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_ZERO_EXTEND
-- --synopsys subpgm_id 382
begin
-- --synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- --synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_SIGN_EXTEND
-- --synopsys subpgm_id 383
begin
-- --synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- --synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_ZERO_EXTEND
-- --synopsys subpgm_id 384
begin
-- --synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- --synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_ZERO_EXTEND
-- --synopsys subpgm_id 385
begin
-- --synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- --synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- --synopsys built_in SYN_SIGN_EXTEND
-- --synopsys subpgm_id 386
begin
-- --synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- --synopsys synthesis_on
end;
end std_logic_arith;
| gpl-2.0 | 69e37beab3255c428072ec41d54a83f8 | 0.636195 | 3.422273 | false | false | false | false |
nickg/nvc | test/regress/signal16.vhd | 1 | 643 | entity signal16 is
end entity;
architecture test of signal16 is
signal x : bit_vector(15 downto 0);
signal y : natural range 0 to 14;
signal z : bit_vector(3 downto 0);
begin
p1: process (y, z) is
begin
x(y+1 downto y) <= z(1 downto 0);
end process;
p2: process is
begin
assert x = "0000000000000000";
y <= 14;
z <= "1111";
wait for 0 ns;
assert x = "0000000000000000";
y <= 1;
wait for 0 ns;
assert x = "1100000000000000";
wait for 0 ns;
assert x = "1100000000000110";
wait;
end process;
end architecture;
| gpl-3.0 | 81e6544f99ad08f680a13868ea590935 | 0.5521 | 3.782353 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1307/line_delay.vhd | 1 | 1,663 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity line_delay is
Port ( clk : in STD_LOGIC;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_blank : in std_logic;
in_hsync : in std_logic;
in_vsync : in std_logic;
in_red : in std_logic_vector(7 downto 0);
in_green : in std_logic_vector(7 downto 0);
in_blue : in std_logic_vector(7 downto 0);
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank : out std_logic;
out_hsync : out std_logic;
out_vsync : out std_logic;
out_red : out std_logic_vector(7 downto 0);
out_green : out std_logic_vector(7 downto 0);
out_blue : out std_logic_vector(7 downto 0));
end line_delay;
architecture Behavioral of line_delay is
type mem_block is array (0 to 511) of std_logic_vector(26 downto 0);
signal mem_4 : mem_block := (others => (others => '0'));
signal wr_addr : unsigned(8 downto 0) := (others =>'1');
signal mid_3 : std_logic_vector(26 downto 0) := (others =>'0');
begin
process(clk)
variable mem_4_out : std_logic_vector(26 downto 0);
begin
if rising_edge(clk) then
mem_4_out := mem_4(to_integer(wr_addr));
out_green <= mem_4_out(18 downto 11);
out_blue <= mem_4_out(10 downto 3);
mem_4(to_integer(wr_addr)) <= mid_3;
end if;
end process;
end Behavioral;
| gpl-2.0 | d00200977d618681efb776a8d8a316ce | 0.502706 | 3.703786 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc474.vhd | 4 | 12,120 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc474.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00474ent IS
END c03s02b01x01p19n01i00474ent;
ARCHITECTURE c03s02b01x01p19n01i00474arch OF c03s02b01x01p19n01i00474ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type s2boolean_vector is array (natural range <>,natural range <>) of boolean;
type s2bit_vector is array (natural range<>,natural range <>) of bit;
type s2char_vector is array (natural range<>,natural range <>) of character;
type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
type s2integer_vector is array (natural range <>,natural range <>) of integer;
type s2real_vector is array (natural range <>,natural range <>) of real;
type s2time_vector is array (natural range <>,natural range <>) of time;
type s2natural_vector is array (natural range <>,natural range <>) of natural;
type s2positive_vector is array (natural range <>,natural range <>) of positive;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
end record;
type array_rec_rec is array (integer range <>) of record_of_records;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st := (others => C1);
constant C71 : severity_level_vector_st := (others => C4);
constant C72 : integer_vector_st := (others => C5);
constant C73 : real_vector_st := (others => C6);
constant C74 : time_vector_st := (others => C7);
constant C75 : natural_vector_st := (others => C8);
constant C76 : positive_vector_st := (others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C52,C53,C77);
constant C66 : array_rec_rec(0 to 7) := (others => C55);
function complex_scalar(s : array_rec_rec(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_rec is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_rec(0 to 7);
signal S2 : array_rec_rec(0 to 7);
signal S3 : array_rec_rec(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00474"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00474 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00474arch;
| gpl-2.0 | dc9511b92ef3e263fda778cff8fb92ad | 0.583498 | 3.801757 | false | false | false | false |
tgingold/ghdl | testsuite/sanity/004all08/all08.vhdl | 1 | 10,835 | -- Files containing most (if not all) features of vhdl08.
-- Like a comment.
-- TODO: at specifications.
context ctxt_ieee is
library ieee;
use ieee.std_logic_1164.all;
end ctxt_ieee;
context work.ctxt_ieee;
package pkg is
-- TODO: file param,
procedure clear (v : out std_logic_vector);
type my_enum is
(lit_a, lit_b, lit_c, 'e');
subtype my_enum_lit is my_enum range lit_b to 'e';
pure function "+" (v : my_enum) return my_enum;
type my_short is range -2**15 to 2**15 - 1;
type DISTANCE is range 0 to 1E16 units
-- primary unit:
angstrom;
-- metric lengths:
nm = 10 angstrom;
um = 1000 nm;
mm = 1000 um;
cm = 10 mm; -- Large unit.
end units;
type my_float is range 0.0 to 1.0e20;
type my_array1d is array (my_short range <>) of boolean;
subtype my_array1d10 is my_array1d (1 to 10);
type my_array2d is array (natural range <>, natural range <>) of boolean;
subtype my_array2d_8x8 is my_array2d (1 to 8, 1 to 8);
type d2c_type is array (0 to 9) of character;
type chess_type is array (1 to 8, 1 to 8) of std_logic_vector;
attribute user_attr : boolean;
attribute user_attr of clear [std_logic_vector]: procedure is True;
type cell;
type cell_acc is access cell;
type cell is record
chain : cell_acc;
val : natural;
b0, b1 : bit;
end record;
procedure prepend (variable ch : inout cell_acc; val : natural);
type text_file is file of string;
function is_eof (file t : text_file; fake : boolean) return boolean;
alias iseof is is_eof [text_file, boolean return boolean];
type sharedcounter is protected
procedure increment (n : natural);
procedure decrement (constant n : natural);
impure function get return natural;
end protected;
type my_urec is record
l : std_ulogic;
adr : std_ulogic_vector;
dat : std_ulogic_vector;
end record;
subtype my_urec8 is my_urec (adr (1 downto 0), dat (7 downto 0));
subtype my_slv is (resolved) std_ulogic_vector;
end pkg;
package body pkg is
pure function "+" (v : my_enum) return my_enum is
begin
return v;
end "+";
procedure clear (v : out std_logic_vector) is
begin
v := (v'range => '0');
end clear;
procedure prepend (variable ch : inout cell_acc; val : natural)
is
variable res : cell_acc;
variable len : natural;
begin
-- Check if already in the list.
res := ch;
while res /= null loop
if res.val = val then
return;
end if;
res := res.all.chain;
null;
end loop;
len := 0;
res := ch;
L1: loop
exit L1 when res = null;
len := len + 1;
res := res.chain;
next when res.val = val;
end loop;
res := new cell'(chain => ch, val => val, b0 | b1 => '0');
ch := res;
end prepend;
function is_eof (file t : text_file; fake : boolean) return boolean is
begin
s: if fake then
return false;
else
return endfile (t);
end if s;
end is_eof;
procedure check_is_eof parameter (filename : string)
is
file f : text_file open read_mode is filename;
file f2, f3 : text_file;
begin
null;
end check_is_eof;
type sharedcounter is protected body
variable val : natural := 0;
procedure increment (n : natural) is
begin
val := val + n;
end increment;
procedure decrement (constant n : natural) is
begin
val := val - n;
end procedure decrement;
impure function get return natural is
begin
return val;
end function get;
end protected body;
end pkg;
package genpkg is
generic (val : natural := 5;
function plus (l, r : integer) return integer);
procedure add (l : inout integer);
end genpkg;
package body genpkg is
procedure add (l : inout integer) is
begin
l := plus (l, val);
end add;
end genpkg;
package genpkg2 is
generic (v : natural;
type t1;
package subgenpkg is new work.genpkg generic map (<>));
end genpkg2;
package my_adder_pkg is new work.genpkg generic map (val => open, plus => "+");
library ieee, work;
use ieee.std_logic_1164.all;
entity reg is
generic (width : natural);
port (clk : std_logic;
signal rst_n : std_logic;
d : in std_logic_vector (width - 1 downto 0);
q : out std_logic_vector (width - 1 downto 0));
subtype bus_type is std_logic_vector (width - 1 downto 0);
begin
ass1: postponed assert width < 128 report "large width" severity warning;
end reg;
library ieee;
use work.pkg.sharedcounter, ieee.std_logic_1164.all;
architecture behav of reg
is
shared variable counter : sharedcounter;
begin
process (clk, rst_n)
begin
if rising_edge(clk) then
if rst_n = '0' then
q <= (others => '0');
counter.increment (1);
else
q <= d;
end if;
end if;
end process;
end behav;
configuration reg_conf1 of reg is
for behav
end for;
end reg_conf1;
library ieee, work;
use ieee.std_logic_1164.all;
entity check_zero is
port (i0 : in std_logic);
end check_zero;
architecture behav of check_zero is
begin
assert (i0 = '0');
end behav;
entity reg_tb is
generic (conf : natural := 2);
end reg_tb;
library ieee;
use ieee.std_logic_1164.all;
use work.pkg.all;
architecture behav of reg_tb is
component reg is
generic (width : natural);
port (clk : std_logic;
rst_n : std_logic;
d : in std_logic_vector (width - 1 downto 0);
q : out std_logic_vector (width - 1 downto 0));
end component reg;
component check_zero is
port (i0 : in std_logic);
end component check_zero;
subtype data_type is std_logic_vector (31 downto 0);
function get_vector (n : natural) return data_type is
begin
case n is
when 0 =>
return x"0000_0000";
when 1 =>
return x"0000_0001";
when 2 =>
return x"1111_1111";
when 3 | 4 =>
return data_type'(x"3333_4444");
when 5 to 7 =>
return (0 to 5 => '1', 6 | 7 => '0', others => '1');
when 8 =>
return ('0', '1', '0', others => '0');
when others =>
return x"ffff_ffff";
end case;
end get_vector;
signal clk : std_logic bus;
signal rst_n : std_logic := '0';
signal din, dout : data_type;
signal s1 : std_logic;
signal si : integer;
signal si2 : integer;
alias my_clk : std_logic is clk;
group syn is (subtype, signal <>);
group sig_syn : syn (data_type, clk, rst_n);
type data_array_type is array (natural range <>) of data_type;
constant zero : natural := 0;
procedure disp_msg (msg : string) is
begin
if msg'left (1) /= 1 then
report "strange start" severity note;
elsif msg'length > 20 then
report "long message";
else
report msg
severity note;
end if;
end disp_msg;
for cmpz0 : check_zero use entity work.check_zero port map (i0 => i0);
for cmpz1 : check_zero use open;
for others : check_zero use entity work.check_zero;
begin
process
begin
clk <= '0', '1' after 10 ns;
wait for 20 ns;
end process;
rst_n <= '0', '1' after 25 ns;
si2 <= 1 when rst_n = '0' else
2 when rst_n = '1';
cmpz0 : check_zero port map (i0 => din (0));
cmpz1 : check_zero port map (i0 => din (1));
cmpz2 : check_zero port map (i0 => din (2));
disp_msg ("start of design");
process (all)
begin
s1 <= not rst_n;
assert s1'driving and s1'driving_value /= '0';
end process;
si <= integer'(1) when clk = '0' else 2;
assert si'event or si'active or si'last_value < 3;
assert si'last_active < 10 ns and si'last_event < 10 ns;
assert si'transaction = '0';
postponed process is
begin
disp_msg (msg => "test is starting """ & reg_tb'simple_name & '"');
for i in 1 to 10 loop
din <= get_vector(i);
wait on my_clk until rising_edge(my_clk);
end loop;
wait;
end process;
compute: process
subtype byte_idx is natural range 0 to 7;
variable v : integer;
variable b1, b2, b3 : boolean;
variable bv1, bv2 : bit_vector (byte_idx);
variable d : distance;
begin
b2 := true;
b1 := (b2 and b3) or b1;
b3 := (b1 xor b2) nand b3;
b2 := (b1 nor b2) xnor b3;
assert byte_idx'left = 0 and byte_idx'low = 0;
assert byte_idx'right = 7 and byte_idx'high = 7;
assert byte_idx'ascending;
assert boolean'pos(b1) = 1;
bv1 := bv2 sll v;
bv2 := (bv1 rol v) and 8x"f0";
bv1 := not(bv2 sra (v rem 3));
v := -2;
v := ((3 * v) / 4) ** 2;
v := (v + 4) - 1;
v := natural (v mod 128);
b1 := v >= 3;
b2 := v /= 4;
b3 := b2 or (v = 5);
d := 1.5 cm when v >= 0 else mm;
report "v = " & integer'image (v) severity note;
wait;
end process compute;
cmp_reg : reg
generic map (width => 32)
port map (clk => clk,
rst_n => rst_n,
d => din,
q => dout);
blk1: block (clk)
signal dout2 : data_type register;
disconnect dout2 : data_type after 1 ns;
signal dout3 : data_type;
signal dout4 : data_type;
for cmpz1_0, cmpz1_1 : check_zero use entity work.check_zero;
begin
assert dout (7 downto 0) = din (7 downto 0);
assert dout'right = 0;
cmpz1_0 : check_zero port map (i0 => din (0));
cmpz1_1 : check_zero port map (i0 => din (1));
dout2 <= guarded din;
with dout(0) select
dout4 <= din when '0',
(others => '1') when others;
g1: for i in 0 to 40 generate
g2: if i <= data_type'left generate
cmp: entity work.reg
generic map (width => 1)
port map (clk => clk,
rst_n => rst_n,
d(0) => din (i),
q(0) => dout3 (i));
end generate g2;
end generate g1;
end block;
blk2: block is
generic (w : natural);
generic map (w => 1);
port (di : std_logic_vector (w - 1 downto 0);
do : out std_logic_vector (w - 1 downto 0));
port map (di => din (0 downto 0),
do => dout (0 downto 0));
for all : check_zero use entity work.check_zero;
begin
cmpz1_0 : check_zero port map (i0 => din (0));
g4: case conf generate
when g4_1: 1 | 2 =>
begin
cmp : configuration work.reg_conf1
generic map (width => 1)
port map (clk => clk,
rst_n => std_logic (rst_n),
d => di,
q => do);
end g4_1;
when others =>
end generate g4;
end block blk2;
end behav;
configuration cfg of reg_tb is
for behav
-- component configuration.
for cmp_reg : reg
use entity work.reg (behav);
end for;
for blk1
for g1(1)
end for;
for g1(2 to 3)
for g2
end for;
end for;
end for;
end for;
end cfg;
| gpl-2.0 | 1dfd4add0c1b14915ff322ede6e1102d | 0.585879 | 3.327703 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/PoC/src/sort/sortnet/sortnet_BitonicSort.vhdl | 2 | 7,916 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: Sorting network: bitonic sort
--
-- Description:
-- -------------------------------------
-- This sorting network uses the *bitonic sort* algorithm.
--
-- .. image:: /_static/sort/sortnet/sortnet_BitonicSort.*
-- :target: ../../../_static/sort/sortnet/sortnet_BitonicSort.svg
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.math.all;
use PoC.vectors.all;
use PoC.components.all;
entity sortnet_BitonicSort is
generic (
INPUTS : positive := 32; -- input count
KEY_BITS : positive := 32; -- the first KEY_BITS of In_Data are used as a sorting critera (key)
DATA_BITS : positive := 64; -- inclusive KEY_BITS
META_BITS : natural := 2; -- additional bits, not sorted but delayed as long as In_Data
PIPELINE_STAGE_AFTER : natural := 2; -- add a pipline stage after n sorting stages
ADD_INPUT_REGISTERS : boolean := FALSE; --
ADD_OUTPUT_REGISTERS : boolean := TRUE --
);
port (
Clock : in std_logic;
Reset : in std_logic;
Inverse : in std_logic := '0';
In_Valid : in std_logic;
In_IsKey : in std_logic;
In_Data : in T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
In_Meta : in std_logic_vector(META_BITS - 1 downto 0);
Out_Valid : out std_logic;
Out_IsKey : out std_logic;
Out_Data : out T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
Out_Meta : out std_logic_vector(META_BITS - 1 downto 0)
);
end entity;
architecture rtl of sortnet_BitonicSort is
constant C_VERBOSE : boolean := POC_VERBOSE;
constant BLOCKS : positive := log2ceil(INPUTS);
constant STAGES : positive := triangularNumber(BLOCKS);
constant COMPARATORS : positive := STAGES * (INPUTS / 2);
constant META_VALID_BIT : natural := 0;
constant META_ISKEY_BIT : natural := 1;
constant META_VECTOR_BITS : positive := META_BITS + 2;
subtype T_META is std_logic_vector(META_VECTOR_BITS - 1 downto 0);
type T_META_VECTOR is array(natural range <>) of T_META;
subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
type T_DATA_MATRIX is array(natural range <>) of T_DATA_VECTOR(INPUTS - 1 downto 0);
function to_dv(slm : T_SLM) return T_DATA_VECTOR is
variable Result : T_DATA_VECTOR(slm'range(1));
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(i)(j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_slm(dv : T_DATA_VECTOR) return T_SLM is
variable Result : T_SLM(dv'range, T_DATA'range);
begin
for i in dv'range loop
for j in T_DATA'range loop
Result(i, j) := dv(i)(j);
end loop;
end loop;
return Result;
end function;
signal In_Valid_d : std_logic := '0';
signal In_IsKey_d : std_logic := '0';
signal In_Data_d : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => '0'));
signal In_Meta_d : std_logic_vector(META_BITS - 1 downto 0) := (others => '0');
signal MetaVector : T_META_VECTOR(STAGES downto 0) := (others => (others => '0'));
signal DataMatrix : T_DATA_MATRIX(STAGES downto 0) := (others => (others => (others => '0')));
signal MetaOutputs_d : T_META := (others => '0');
signal DataOutputs_d : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => '0'));
begin
assert (not C_VERBOSE)
report "sortnet_BitonicSort:" & LF &
" DATA_BITS=" & integer'image(DATA_BITS) &
" KEY_BITS=" & integer'image(KEY_BITS) &
" META_BITS=" & integer'image(META_BITS)
severity NOTE;
In_Valid_d <= In_Valid when registered(Clock, ADD_INPUT_REGISTERS);
In_IsKey_d <= In_IsKey when registered(Clock, ADD_INPUT_REGISTERS);
In_Data_d <= In_Data when registered(Clock, ADD_INPUT_REGISTERS);
In_Meta_d <= In_Meta when registered(Clock, ADD_INPUT_REGISTERS);
DataMatrix(0) <= to_dv(In_Data_d);
MetaVector(0)(META_VALID_BIT) <= In_Valid_d;
MetaVector(0)(META_ISKEY_BIT) <= In_IsKey_d;
MetaVector(0)(META_VECTOR_BITS - 1 downto META_VECTOR_BITS - META_BITS) <= In_Meta_d;
genBlocks : for b in 0 to BLOCKS - 1 generate
constant START_DISTANCE : positive := 2**b;
begin
genStage : for s in 0 to b generate
constant STAGE_INDEX : natural := triangularNumber(b) + s;
constant DISTANCE : positive := 2**(b - s);
constant GROUPS : positive := INPUTS / (DISTANCE * 2);
constant INSERT_PIPELINE_REGISTER : boolean := (PIPELINE_STAGE_AFTER /= 0) and (STAGE_INDEX mod PIPELINE_STAGE_AFTER = 0);
begin
MetaVector(STAGE_INDEX + 1) <= MetaVector(STAGE_INDEX) when registered(Clock, INSERT_PIPELINE_REGISTER);
genGroups : for g in 0 to GROUPS - 1 generate
constant INV : std_logic := to_sl((g / (2 ** s) mod 2 = 1));
begin
genLoop : for l in 0 to DISTANCE - 1 generate
constant SRC0 : natural := g * (DISTANCE * 2) + l;
constant SRC1 : natural := SRC0 + DISTANCE;
signal Greater : std_logic;
signal Switch_d : std_logic;
signal Switch_en : std_logic;
signal Switch_r : std_logic := '0';
signal Switch : std_logic;
signal NewData0 : T_DATA;
signal NewData1 : T_DATA;
begin
Greater <= to_sl(unsigned(DataMatrix(STAGE_INDEX)(SRC0)(KEY_BITS - 1 downto 0)) > unsigned(DataMatrix(STAGE_INDEX)(SRC1)(KEY_BITS - 1 downto 0)));
Switch_d <= Greater xor Inverse xor INV;
Switch_en <= MetaVector(STAGE_INDEX)(META_ISKEY_BIT) and MetaVector(STAGE_INDEX)(META_VALID_BIT);
Switch_r <= ffdre(q => Switch_r, d => Switch_d, en => Switch_en) when rising_edge(Clock);
Switch <= mux(Switch_en, Switch_r, Switch_d);
NewData0 <= mux(Switch, DataMatrix(STAGE_INDEX)(SRC0), DataMatrix(STAGE_INDEX)(SRC1));
NewData1 <= mux(Switch, DataMatrix(STAGE_INDEX)(SRC1), DataMatrix(STAGE_INDEX)(SRC0));
DataMatrix(STAGE_INDEX + 1)(SRC0) <= NewData0 when registered(Clock, INSERT_PIPELINE_REGISTER);
DataMatrix(STAGE_INDEX + 1)(SRC1) <= NewData1 when registered(Clock, INSERT_PIPELINE_REGISTER);
end generate;
end generate;
end generate;
end generate;
MetaOutputs_d <= MetaVector(STAGES) when registered(Clock, ADD_OUTPUT_REGISTERS);
DataOutputs_d <= to_slm(DataMatrix(STAGES)) when registered(Clock, ADD_OUTPUT_REGISTERS);
Out_Valid <= MetaOutputs_d(META_VALID_BIT);
Out_IsKey <= MetaOutputs_d(META_ISKEY_BIT);
Out_Data <= DataOutputs_d;
Out_Meta <= MetaOutputs_d(META_VECTOR_BITS - 1 downto META_VECTOR_BITS - META_BITS);
end architecture;
| gpl-2.0 | 004774c1e38bb9015b6458fb1fa776f2 | 0.6214 | 3.084957 | false | false | false | false |
nickg/nvc | test/regress/func9.vhd | 1 | 643 | entity func9 is
end entity;
architecture test of func9 is
constant msg0 : string := "zero";
constant msg1 : string := "one";
function get_message(x : in bit) return string is
begin
case x is
when '0' => return msg0;
when '1' => return msg1;
end case;
end function;
begin
process is
variable x : bit;
begin
x := '1';
wait for 1 ns; -- Prevent constant folding
assert get_message(x) = "one";
x := '0';
wait for 1 ns;
assert get_message(x) = "zero";
wait;
end process;
end architecture;
| gpl-3.0 | 595eac63ceb0c5fbfd38dbfe2b3c732b | 0.520995 | 3.89697 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2169.vhd | 4 | 2,415 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2169.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02169ent IS
END c07s02b04x00p22n01i02169ent;
ARCHITECTURE c07s02b04x00p22n01i02169arch OF c07s02b04x00p22n01i02169ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_8 is severity_level_v (1 to 8);
SUBTYPE severity_level_4 is severity_level_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : severity_level_4;
variable l_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
variable r_operand : severity_level_4 := ( FAILURE , FAILURE , NOTE , NOTE );
alias l_alias : severity_level_v (1 to 2) is l_operand (2 to 3);
alias r_alias : severity_level_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 5 ns;
assert NOT(( result = ( FAILURE , NOTE , NOTE , NOTE )) and ( result(1) = FAILURE ))
report "***PASSED TEST: c07s02b04x00p22n01i02169"
severity NOTE;
assert (( result = ( FAILURE , NOTE , NOTE , NOTE )) and ( result(1) = FAILURE ))
report "***FAILED TEST: c07s02b04x00p22n01i02169 - Concatenation of two SEVERITY_LEVEL aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02169arch;
| gpl-2.0 | 5d55d2fc801f8dab2810c40e22f300ed | 0.658385 | 3.58841 | false | true | false | false |
nickg/nvc | test/regress/signal26.vhd | 1 | 583 | entity signal26 is
end entity;
architecture test of signal26 is
function func (x : integer) return integer is
begin
return x / 2;
end function;
constant w : integer := 4;
type rec is record
f : bit_vector(func(w) - 1 downto 0);
end record;
signal v : bit_vector(w - 1 downto 0);
signal r : rec;
begin
v(w-1 downto r.f'left + 1) <= (others => '1');
v(r.f'left downto 0) <= (others => '0');
check: process is
begin
wait for 1 ns;
assert v = "1100";
wait;
end process;
end architecture;
| gpl-3.0 | 6fe298906fe727ca37fb5f7bb879d7dd | 0.564322 | 3.491018 | false | false | false | false |
tgingold/ghdl | testsuite/synth/fsm01/tb_fsm_2s.vhdl | 1 | 873 | entity tb_fsm_2s is
end tb_fsm_2s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_2s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_2s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"10010";
constant res : std_logic_vector := b"01001";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | fa7f6984220389501fe4cfa38352c451 | 0.562428 | 3.306818 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma.vhd | 3 | 126,890 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma.vhd
-- Description: This entity is the top level entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_dma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 10;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
-- C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_MM2S_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_S2MM_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
-- Enable CACHE support, primarily for MCDMA
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
-- Number of S2MM channels, primarily for MCDMA
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
-- Number of MM2S channels, primarily for MCDMA
C_FAMILY : string := "virtex7";
C_MICRO_DMA : integer range 0 to 1 := 0;
-- Target FPGA Device Family
C_INSTANCE : string := "axi_dma"
);
port (
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axi_s2mm_aclk : in std_logic := '0' ; --
-----------------------------------------------------------------------
-- Primary Clock CDMA
-----------------------------------------------------------------------
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
-- s_axi_lite_awaddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_awaddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
-- s_axi_lite_araddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_araddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic := '0' ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic := '0' ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := "00" ; --
m_axi_sg_bvalid : in std_logic := '0' ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0' ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
m_axis_mm2s_tuser : out std_logic_vector (3 downto 0) ; --
m_axis_mm2s_tid : out std_logic_vector (4 downto 0) ; --
m_axis_mm2s_tdest : out std_logic_vector (4 downto 0) ; --
--
-- Memory Map to Stream Control Stream Interface --
mm2s_cntrl_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
s_axis_s2mm_tuser : in std_logic_vector (3 downto 0) := "0000" ; --
s_axis_s2mm_tid : in std_logic_vector (4 downto 0) := "00000" ; --
s_axis_s2mm_tdest : in std_logic_vector (4 downto 0) := "00000" ; --
--
-- Stream to Memory Map Status Steam Interface --
s2mm_sts_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_sts_tvalid : in std_logic := '0'; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic := '0'; --
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_dma_tstvec : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
);
end axi_dma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- The FREQ are needed only for ASYNC mode, for SYNC mode these are irrelevant
-- For Async, mm2s or s2mm >= sg >= lite
constant C_S_AXI_LITE_ACLK_FREQ_HZ : integer := 100000000;
-- AXI Lite clock frequency in hertz
constant C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- AXI MM2S clock frequency in hertz
constant C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- AXI S2MM clock frequency in hertz
constant C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000;
-- Scatter Gather clock frequency in hertz
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_string (value_in_1 : integer)
return string is
Variable max_value : string (1 to 5) := "00000";
begin
If (value_in_1 = 1) Then
-- coverage off
max_value := "11100";
-- coverage on
else
max_value := "11111";
End if;
Return (max_value);
end function funct_get_string;
function width_calc (value_in : integer)
return integer is
variable addr_value : integer := 32;
begin
if (value_in > 32) then
addr_value := 64;
else
addr_value := 32;
end if;
return(addr_value);
end function width_calc;
-- -------------------------------------------------------------------
--
--
--
-- -------------------------------------------------------------------
-- -- Function
-- --
-- -- Function Name: funct_rnd2pwr_of_2
-- --
-- -- Function Description:
-- -- Rounds the input value up to the nearest power of 2 between
-- -- 128 and 8192.
-- --
-- -------------------------------------------------------------------
-- function funct_rnd2pwr_of_2 (input_value : integer) return integer is
--
-- Variable temp_pwr2 : Integer := 128;
--
-- begin
--
-- if (input_value <= 128) then
--
-- temp_pwr2 := 128;
--
-- elsif (input_value <= 256) then
--
-- temp_pwr2 := 256;
--
-- elsif (input_value <= 512) then
--
-- temp_pwr2 := 512;
--
-- elsif (input_value <= 1024) then
--
-- temp_pwr2 := 1024;
--
-- elsif (input_value <= 2048) then
--
-- temp_pwr2 := 2048;
--
-- elsif (input_value <= 4096) then
--
-- temp_pwr2 := 4096;
--
-- else
--
-- temp_pwr2 := 8192;
--
-- end if;
--
--
-- Return (temp_pwr2);
--
-- end function funct_rnd2pwr_of_2;
-- -------------------------------------------------------------------
--
--
--
--
--
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
constant skid_enable : string := (funct_get_string(0));
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
-- Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
-- (funct_get_max(4, 4)+2)
-- * C_M_AXI_MAX_BURST_LEN;
--
-- -- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- -- power of 2
-- Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
-- funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Scatter Gather Engine Configuration
-- Number of Fetch Descriptors to Queue
constant ADDR_WIDTH : integer := width_calc (C_M_AXI_SG_ADDR_WIDTH);
constant MCDMA : integer := (1 - C_ENABLE_MULTI_CHANNEL);
constant DESC_QUEUE : integer := (1*MCDMA);
constant STSCNTRL_ENABLE : integer := (C_SG_INCLUDE_STSCNTRL_STRM*MCDMA);
constant APPLENGTH_ENABLE : integer := (C_SG_USE_STSAPP_LENGTH*MCDMA);
constant C_SG_LENGTH_WIDTH_INT : integer := (C_SG_LENGTH_WIDTH*MCDMA + 23*C_ENABLE_MULTI_CHANNEL);
-- Comment the foll 2 line to disable queuing for McDMA and uncomment the 3rd and 4th lines
--constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
-- Number of Update Descriptors to Queue
--constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 8 + (5 * STSCNTRL_ENABLE);
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 8; -- Only need to fetch 1st 8wrds for s2mm
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- Only status needs update for mm2s
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1 + (5 * STSCNTRL_ENABLE);
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERROR : integer := 1;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor update pointer bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor update status bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33; -- IOC (1 bit) & DescStatus (32 bits)
-- Include SG Descriptor Updates
constant INCLUDE_DESC_UPDATE : integer := 1;
-- Include SG Interrupt Logic
constant INCLUDE_INTRPT : integer := 1;
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
--constant DM_CMDSTS_FIFO_DEPTH : integer := 1*C_ENABLE_MULTI_CHANNEL + (max2(1,SG_UPDT_DESC2QUEUE))*MCDMA;
constant DM_CMDSTS_FIFO_DEPTH : integer := max2(1,SG_UPDT_DESC2QUEUE);
constant DM_CMDSTS_FIFO_DEPTH_1 : integer := ((1-C_PRMRY_IS_ACLK_ASYNC)+C_PRMRY_IS_ACLK_ASYNC*DM_CMDSTS_FIFO_DEPTH);
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- Enable indeterminate BTT on datamover when stscntrl stream not included or
-- when use status app rx length is not enable or when in Simple DMA mode.
constant DM_SUPPORT_INDET_BTT : integer := 1 - (STSCNTRL_ENABLE
* APPLENGTH_ENABLE
* C_INCLUDE_SG) - C_MICRO_DMA;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- DataMover status width - is based on mode of operation
constant DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 4;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := (C_INCLUDE_MM2S) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_MM2S;
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := (C_INCLUDE_S2MM) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_S2MM;
-- Minimum value required for length width based on burst size and stream dwidth
-- If user sets c_sg_length_width too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant DM_BTT_LENGTH_WIDTH : integer := max2((required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH,
C_MM2S_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_MM2S),
(required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH,
C_S2MM_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_S2MM));
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH);
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- Return correct freq_hz parameter depending on if sg engine is included
constant M_AXI_SG_ACLK_FREQ_HZ :integer := hertz_prmtr_select(C_INCLUDE_SG,
C_S_AXI_LITE_ACLK_FREQ_HZ,
C_M_AXI_SG_ACLK_FREQ_HZ);
-- Scatter / Gather is always configure for synchronous operation for AXI DMA
constant SG_IS_SYNCHRONOUS : integer := 0;
constant CMD_WIDTH : integer := ((8*C_ENABLE_MULTI_CHANNEL)+ ADDR_WIDTH+ CMD_BASE_WIDTH) ;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi_lite_aclk : std_logic := '1';
signal axi_sg_aclk : std_logic := '1';
signal m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard)
signal dm_m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard) (Raw)
signal m_axi_mm2s_aresetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal m_axi_s2mm_aresetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg aclk domain (Soft/Hard)
signal s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg aclk domain (Soft/Hard)
signal mm2s_prmry_resetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)
signal s2mm_prmry_resetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)
signal axi_lite_reset_n : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_hrdresetn : std_logic := '1'; -- AXI Lite Interface Reset on SG clock domain (Hard Only)
signal dm_mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg domain (Soft/Hard)(Raw)
signal dm_s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg domain (Soft/Hard)(Raw)
-- Register Module Signals
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); --(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal mm2s_length_wren : std_logic := '0';
signal mm2s_smpl_interr_set : std_logic := '0';
signal mm2s_smpl_slverr_set : std_logic := '0';
signal mm2s_smpl_decerr_set : std_logic := '0';
signal mm2s_smpl_done : std_logic := '0';
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_packet_eof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal mm2s_dlyirq_dsble : std_logic := '0'; -- CR605888
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); --(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_length_wren : std_logic := '0';
signal s2mm_bytes_rcvd : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_bytes_rcvd_wren : std_logic := '0';
signal s2mm_smpl_interr_set : std_logic := '0';
signal s2mm_smpl_slverr_set : std_logic := '0';
signal s2mm_smpl_decerr_set : std_logic := '0';
signal s2mm_smpl_done : std_logic := '0';
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_error : std_logic := '0';
signal s2mm_dlyirq_dsble : std_logic := '0'; -- CR605888
signal mm2s_stop : std_logic := '0';
signal s2mm_stop : std_logic := '0';
signal ftch_error : std_logic := '0';
signal ftch_error_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_error : std_logic := '0';
signal updt_error_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
--*********************************
-- MM2S Signals
--*********************************
-- MM2S DMA Controller Signals
signal mm2s_desc_flush : std_logic := '0';
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata_new : std_logic_vector(96+31*0+(0+2)*(ADDR_WIDTH-32) downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid_new : std_logic := '0';
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- SG MM2S Descriptor Update AXI Stream Out
signal s_axis_mm2s_updtptr_tdata : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtptr_tvalid : std_logic := '0';
signal s_axis_mm2s_updtptr_tready : std_logic := '0';
signal s_axis_mm2s_updtptr_tlast : std_logic := '0';
signal s_axis_mm2s_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtsts_tvalid : std_logic := '0';
signal s_axis_mm2s_updtsts_tready : std_logic := '0';
signal s_axis_mm2s_updtsts_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid_split : std_logic := '0';
signal s_axis_mm2s_cmd_tready_split : std_logic := '0';
signal s_axis_mm2s_cmd_tdata_split : std_logic_vector
((ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_s2mm_cmd_tvalid_split : std_logic := '0';
signal s_axis_s2mm_cmd_tready_split : std_logic := '0';
signal s_axis_s2mm_cmd_tdata_split : std_logic_vector
((ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tvalid_int : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_updt_idle : std_logic := '0';
signal s2mm_updt_ioc_irq_set : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata_new : std_logic_vector(96+31*0+(0+2)*(ADDR_WIDTH-32) downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_nxt : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid_new : std_logic := '0';
signal m_axis_ftch2_desc_available, m_axis_ftch1_desc_available : std_logic;
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
signal mm2s_axis_info : std_logic_vector(13 downto 0) := (others => '0');
-- SG S2MM Descriptor Update AXI Stream Out
signal s_axis_s2mm_updtptr_tdata : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtptr_tvalid : std_logic := '0';
signal s_axis_s2mm_updtptr_tready : std_logic := '0';
signal s_axis_s2mm_updtptr_tlast : std_logic := '0';
signal s_axis_s2mm_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtsts_tvalid : std_logic := '0';
signal s_axis_s2mm_updtsts_tready : std_logic := '0';
signal s_axis_s2mm_updtsts_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tvalid_int : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tdata_int : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tkeep : std_logic_vector((DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
signal mm2s_updt_interr_set : std_logic := '0';
signal mm2s_updt_slverr_set : std_logic := '0';
signal mm2s_updt_decerr_set : std_logic := '0';
signal mm2s_ftch_err_early : std_logic := '0';
signal mm2s_ftch_stale_desc : std_logic := '0';
signal s2mm_updt_interr_set : std_logic := '0';
signal s2mm_updt_slverr_set : std_logic := '0';
signal s2mm_updt_decerr_set : std_logic := '0';
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
signal s2mm_ftch_err_early : std_logic := '0';
signal s2mm_ftch_stale_desc : std_logic := '0';
signal soft_reset_clr : std_logic := '0';
signal soft_reset : std_logic := '0';
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_int : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_user : std_logic := '0';
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal sg_ctl : std_logic_vector (7 downto 0);
signal s_axis_s2mm_tvalid_int : std_logic;
signal s_axis_s2mm_tlast_int : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal same_tdest : std_logic;
signal s2mm_eof_s2mm : std_logic;
signal ch2_update_active : std_logic;
signal s2mm_desc_info_in : std_logic_vector (13 downto 0);
signal m_axis_mm2s_tlast_i_mcdma : std_logic;
signal s2mm_run_stop_del : std_logic;
signal s2mm_desc_flush_del : std_logic;
signal s2mm_tvalid_latch : std_logic;
signal s2mm_tvalid_latch_del : std_logic;
signal clock_splt : std_logic;
signal clock_splt_s2mm : std_logic;
signal updt_cmpt : std_logic;
signal cmpt_updt : std_logic_vector (1 downto 0);
signal reset1, reset2 : std_logic;
signal mm2s_cntrl_strm_stop : std_logic;
signal bd_eq : std_logic;
signal m_axi_sg_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_sg_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_mm2s_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_s2mm_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_dma_tstvec(31 downto 6) <= (others => '0');
axi_dma_tstvec(5) <= s2mm_updt_ioc_irq_set;
axi_dma_tstvec(4) <= mm2s_updt_ioc_irq_set;
axi_dma_tstvec(3) <= s2mm_packet_eof;
axi_dma_tstvec(2) <= s2mm_packet_sof;
axi_dma_tstvec(1) <= mm2s_packet_eof;
axi_dma_tstvec(0) <= mm2s_packet_sof;
-- Primary MM2S Stream outputs (used internally to gen eof and sof for
-- interrupt coalescing
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i;
-- Primary S2MM Stream output (used internally to gen eof and sof for
-- interrupt coalescing
s_axis_s2mm_tready <= s_axis_s2mm_tready_i;
GEN_INCLUDE_SG : if C_INCLUDE_SG = 1 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= m_axi_sg_aclk;
end generate GEN_INCLUDE_SG;
GEN_EXCLUDE_SG : if C_INCLUDE_SG = 0 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= s_axi_lite_aclk;
end generate GEN_EXCLUDE_SG;
-------------------------------------------------------------------------------
-- AXI DMA Reset Module
-------------------------------------------------------------------------------
I_RST_MODULE : entity axi_dma_v7_1_9.axi_dma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_MM2S_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_M_AXI_S2MM_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_M_AXI_SG_ACLK_FREQ_HZ => M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
s_axi_lite_aclk => axi_lite_aclk ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- Soft Reset
-----------------------------------------------------------------------
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out (m_axi_mm2s_aclk)
-----------------------------------------------------------------------
dm_mm2s_prmry_resetn => m_axi_mm2s_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_mm2s_scndry_resetn => dm_mm2s_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n , -- AXI Stream Control Reset Outputs
mm2s_scndry_resetn => mm2s_scndry_resetn , -- AXI Secondary Reset
mm2s_prmry_resetn => mm2s_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out (m_axi_s2mm_aclk)
-----------------------------------------------------------------------
dm_s2mm_prmry_resetn => m_axi_s2mm_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_s2mm_scndry_resetn => dm_s2mm_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n , -- AXI Stream Control Reset Outputs
s2mm_scndry_resetn => s2mm_scndry_resetn , -- AXI Secondary Reset
s2mm_prmry_resetn => s2mm_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out (m_axi_sg_aclk)
-----------------------------------------------------------------------
m_axi_sg_aresetn => m_axi_sg_aresetn , -- AXI Scatter Gather Reset Out
dm_m_axi_sg_aresetn => dm_m_axi_sg_aresetn , -- AXI Scatter Gather Datamover Reset Out
-----------------------------------------------------------------------
-- Hard Reset Out (s_axi_lite_aclk)
-----------------------------------------------------------------------
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn , -- AXI Lite Ingerface (sg aclk) (Hard Only)
s_axi_lite_resetn => axi_lite_reset_n -- AXI Lite Interface reset (Hard Only)
);
-------------------------------------------------------------------------------
-- AXI DMA Register Module
-------------------------------------------------------------------------------
I_AXI_DMA_REG_MODULE : entity axi_dma_v7_1_9.axi_dma_reg_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_AXI_LITE_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset_n => axi_lite_reset_n ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S DMASR Status
mm2s_stop => mm2s_stop ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_dma_interr_set => mm2s_dma_interr_set ,
mm2s_dma_slverr_set => mm2s_dma_slverr_set ,
mm2s_dma_decerr_set => mm2s_dma_decerr_set ,
mm2s_ioc_irq_set => mm2s_ioc_irq_set ,
mm2s_dly_irq_set => mm2s_dly_irq_set ,
mm2s_irqthresh_wren => mm2s_irqthresh_wren ,
mm2s_irqdelay_wren => mm2s_irqdelay_wren ,
mm2s_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
mm2s_irqdelay_status => mm2s_irqdelay_status ,
mm2s_irqthresh_status => mm2s_irqthresh_status ,
mm2s_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
mm2s_ftch_interr_set => mm2s_ftch_interr_set ,
mm2s_ftch_slverr_set => mm2s_ftch_slverr_set ,
mm2s_ftch_decerr_set => mm2s_ftch_decerr_set ,
mm2s_updt_interr_set => mm2s_updt_interr_set ,
mm2s_updt_slverr_set => mm2s_updt_slverr_set ,
mm2s_updt_decerr_set => mm2s_updt_decerr_set ,
-- MM2S CURDESC Update
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_new_curdesc => mm2s_new_curdesc ,
-- MM2S TAILDESC Update
mm2s_tailpntr_updated => mm2s_tailpntr_updated ,
-- MM2S Registers
mm2s_dmacr => mm2s_dmacr ,
mm2s_dmasr => mm2s_dmasr ,
mm2s_curdesc => mm2s_curdesc ,
mm2s_taildesc => mm2s_taildesc ,
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
s2mm_sof => s2mm_packet_sof ,
s2mm_eof => s2mm_packet_eof ,
-- S2MM DMASR Status
s2mm_stop => s2mm_stop ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_dma_interr_set => s2mm_dma_interr_set ,
s2mm_dma_slverr_set => s2mm_dma_slverr_set ,
s2mm_dma_decerr_set => s2mm_dma_decerr_set ,
s2mm_ioc_irq_set => s2mm_ioc_irq_set ,
s2mm_dly_irq_set => s2mm_dly_irq_set ,
s2mm_irqthresh_wren => s2mm_irqthresh_wren ,
s2mm_irqdelay_wren => s2mm_irqdelay_wren ,
s2mm_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
s2mm_irqdelay_status => s2mm_irqdelay_status ,
s2mm_irqthresh_status => s2mm_irqthresh_status ,
s2mm_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
s2mm_ftch_interr_set => s2mm_ftch_interr_set ,
s2mm_ftch_slverr_set => s2mm_ftch_slverr_set ,
s2mm_ftch_decerr_set => s2mm_ftch_decerr_set ,
s2mm_updt_interr_set => s2mm_updt_interr_set ,
s2mm_updt_slverr_set => s2mm_updt_slverr_set ,
s2mm_updt_decerr_set => s2mm_updt_decerr_set ,
-- MM2S CURDESC Update
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_tvalid => s_axis_s2mm_tvalid ,
s2mm_tvalid_latch => s2mm_tvalid_latch ,
s2mm_tvalid_latch_del => s2mm_tvalid_latch_del ,
-- MM2S TAILDESC Update
s2mm_tailpntr_updated => s2mm_tailpntr_updated ,
-- S2MM Registers
s2mm_dmacr => s2mm_dmacr ,
s2mm_dmasr => s2mm_dmasr ,
s2mm_curdesc => s2mm_curdesc ,
s2mm_taildesc => s2mm_taildesc ,
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
tdest_in => tdest_out_int, --s_axis_s2mm_tdest ,
same_tdest_in => same_tdest,
sg_ctl => sg_ctl ,
-- Soft reset and clear
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
-- Fetch/Update error addresses
ftch_error_addr => ftch_error_addr ,
updt_error_addr => updt_error_addr ,
-- DMA Interrupt Outputs
mm2s_introut => mm2s_introut ,
s2mm_introut => s2mm_introut ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Mode (C_INCLUDE_SG = 1)
-------------------------------------------------------------------------------
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
begin
-- reset1 <= dm_m_axi_sg_aresetn and s2mm_tvalid_latch;
-- reset2 <= m_axi_sg_aresetn and s2mm_tvalid_latch;
s2mm_run_stop_del <= s2mm_tvalid_latch_del and s2mm_dmacr(DMACR_RS_BIT);
-- s2mm_run_stop_del <= (not (updt_cmpt)) and s2mm_dmacr(DMACR_RS_BIT);
s2mm_desc_flush_del <= s2mm_desc_flush or (not s2mm_tvalid_latch);
-- Scatter Gather Engine
I_SG_ENGINE : entity axi_sg_v4_1_2.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_AXIS_IS_ASYNC => SG_IS_SYNCHRONOUS ,
C_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => INCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => INCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => STSCNTRL_ENABLE ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_NUM_MM2S_CHANNELS => C_NUM_MM2S_CHANNELS ,
C_ACTUAL_ADDR => C_M_AXI_SG_ADDR_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
dm_resetn => dm_m_axi_sg_aresetn ,
p_reset_n => mm2s_prmry_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr_internal ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => m_axi_sg_awuser ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr_internal ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => m_axi_sg_aruser ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
sg_ctl => sg_ctl ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
ch1_cyclic => mm2s_dmacr(CYCLIC_BIT) ,
ch1_desc_flush => mm2s_desc_flush ,
ch1_cntrl_strm_stop => mm2s_cntrl_strm_stop ,
ch1_ftch_idle => mm2s_ftch_idle ,
ch1_ftch_interr_set => mm2s_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_ftch_decerr_set ,
ch1_ftch_err_early => mm2s_ftch_err_early ,
ch1_ftch_stale_desc => mm2s_ftch_stale_desc ,
ch1_updt_idle => mm2s_updt_idle ,
ch1_updt_ioc_irq_set => mm2s_updt_ioc_irq_set ,
ch1_updt_interr_set => mm2s_updt_interr_set ,
ch1_updt_slverr_set => mm2s_updt_slverr_set ,
ch1_updt_decerr_set => mm2s_updt_decerr_set ,
ch1_dma_interr_set => mm2s_dma_interr_set ,
ch1_dma_slverr_set => mm2s_dma_slverr_set ,
ch1_dma_decerr_set => mm2s_dma_decerr_set ,
ch1_tailpntr_enabled => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => mm2s_tailpntr_updated ,
ch1_taildesc => mm2s_taildesc ,
ch1_curdesc => mm2s_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
--ch1_dlyirq_dsble => mm2s_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch1_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_packet_eof ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_sg_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => axi_sg_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_run_stop_del , --s2mm_dmacr(DMACR_RS_BIT) ,
ch2_cyclic => s2mm_dmacr(CYCLIC_BIT) ,
ch2_desc_flush => s2mm_desc_flush_del, --s2mm_desc_flush ,
ch2_ftch_idle => s2mm_ftch_idle ,
ch2_ftch_interr_set => s2mm_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_ftch_decerr_set ,
ch2_ftch_err_early => s2mm_ftch_err_early ,
ch2_ftch_stale_desc => s2mm_ftch_stale_desc ,
ch2_updt_idle => s2mm_updt_idle ,
ch2_updt_ioc_irq_set => s2mm_updt_ioc_irq_set , -- For TestVector
ch2_updt_interr_set => s2mm_updt_interr_set ,
ch2_updt_slverr_set => s2mm_updt_slverr_set ,
ch2_updt_decerr_set => s2mm_updt_decerr_set ,
ch2_dma_interr_set => s2mm_dma_interr_set ,
ch2_dma_slverr_set => s2mm_dma_slverr_set ,
ch2_dma_decerr_set => s2mm_dma_decerr_set ,
ch2_tailpntr_enabled => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
ch2_taildesc_wren => s2mm_tailpntr_updated ,
ch2_taildesc => s2mm_taildesc ,
ch2_curdesc => s2mm_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
--ch2_dlyirq_dsble => s2mm_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch2_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_packet_eof ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status ,
ch2_update_active => ch2_update_active ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_sg_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_ch2_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => axi_sg_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Error addresses
ftch_error => ftch_error ,
ftch_error_addr => ftch_error_addr ,
updt_error => updt_error ,
updt_error_addr => updt_error_addr ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ,
bd_eq => bd_eq
);
m_axi_sg_awaddr <= m_axi_sg_awaddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_araddr <= m_axi_sg_araddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
end generate GEN_SG_ENGINE;
-------------------------------------------------------------------------------
-- Exclude Scatter Gather Engine (Simple DMA Mode Enabled)
-------------------------------------------------------------------------------
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather AXI Master Interface Tie-Off
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
m_axi_sg_awvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0';
m_axi_sg_wvalid <= '0';
m_axi_sg_bready <= '0';
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
-- MM2S Signal Remapping/Tie Off for Simple DMA Mode
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s_axis_mm2s_updtptr_tready <= '0';
s_axis_mm2s_updtsts_tready <= '0';
mm2s_ftch_idle <= '1';
mm2s_updt_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
mm2s_ftch_err_early <= '0';
mm2s_ftch_stale_desc <= '0';
mm2s_updt_interr_set <= '0';
mm2s_updt_slverr_set <= '0';
mm2s_updt_decerr_set <= '0';
mm2s_updt_ioc_irq_set <= mm2s_smpl_done; -- For TestVector
mm2s_dma_interr_set <= mm2s_smpl_interr_set; -- To DMASR
mm2s_dma_slverr_set <= mm2s_smpl_slverr_set; -- To DMASR
mm2s_dma_decerr_set <= mm2s_smpl_decerr_set; -- To DMASR
-- S2MM Signal Remapping/Tie Off for Simple DMA Mode
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
s_axis_s2mm_updtptr_tready <= '0';
s_axis_s2mm_updtsts_tready <= '0';
s2mm_ftch_idle <= '1';
s2mm_updt_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
s2mm_ftch_err_early <= '0';
s2mm_ftch_stale_desc <= '0';
s2mm_updt_interr_set <= '0';
s2mm_updt_slverr_set <= '0';
s2mm_updt_decerr_set <= '0';
s2mm_updt_ioc_irq_set <= s2mm_smpl_done; -- For TestVector
s2mm_dma_interr_set <= s2mm_smpl_interr_set; -- To DMASR
s2mm_dma_slverr_set <= s2mm_smpl_slverr_set; -- To DMASR
s2mm_dma_decerr_set <= s2mm_smpl_decerr_set; -- To DMASR
ftch_error <= '0';
ftch_error_addr <= (others => '0');
updt_error <= '0';
updt_error_addr <= (others=> '0');
-- CR595462 - Removed interrupt coalescing logic for Simple DMA mode and replaced
-- with interrupt complete.
mm2s_ioc_irq_set <= mm2s_smpl_done;
mm2s_dly_irq_set <= '0';
mm2s_irqdelay_status <= (others => '0');
mm2s_irqthresh_status <= (others => '0');
s2mm_ioc_irq_set <= s2mm_smpl_done;
s2mm_dly_irq_set <= '0';
s2mm_irqdelay_status <= (others => '0');
s2mm_irqthresh_status <= (others => '0');
end generate GEN_NO_SG_ENGINE;
INCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 1 generate
begin
-------------------------------------------------------------------------------
-- MM2S DMA Controller
-------------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_dma_v7_1_9.axi_dma_mm2s_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH, --C_M_AXI_MM2S_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
soft_reset => soft_reset ,
-- MM2S Control and Status
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
mm2s_keyhole => mm2s_dmacr(DMACR_KH_BIT) ,
mm2s_halted => mm2s_dmasr(DMASR_HALTED_BIT) ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_stop => mm2s_stop ,
mm2s_ftch_err_early => mm2s_ftch_err_early ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_desc_flush => mm2s_desc_flush ,
cntrl_strm_stop => mm2s_cntrl_strm_stop ,
mm2s_tailpntr_enble => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_error => mm2s_error ,
s2mm_error => s2mm_error ,
-- Simple DMA Mode Signals
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
mm2s_smple_done => mm2s_smpl_done ,
mm2s_interr_set => mm2s_smpl_interr_set ,
mm2s_slverr_set => mm2s_smpl_slverr_set ,
mm2s_decerr_set => mm2s_smpl_decerr_set ,
m_axis_mm2s_aclk => m_axi_mm2s_aclk,
mm2s_strm_tlast => m_axis_mm2s_tlast_i_user,
mm2s_strm_tready => m_axis_mm2s_tready,
mm2s_axis_info => mm2s_axis_info,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Currently Being Processed Descriptor
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready_split ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
mm2s_err => mm2s_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => open, --m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => open, --m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => open, --m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => '0', --m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => open --m_axis_mm2s_cntrl_tlast
);
m_axis_mm2s_tuser <= mm2s_axis_info (13 downto 10);
m_axis_mm2s_tid <= mm2s_axis_info (9 downto 5); --
m_axis_mm2s_tdest <= mm2s_axis_info (4 downto 0) ; --
-- If MM2S channel included then include sof/eof generator
-------------------------------------------------------------------------------
-- MM2S SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_MM2S_SOFEOF_GEN : entity axi_dma_v7_1_9.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
axis_tready => m_axis_mm2s_tready ,
axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tlast => m_axis_mm2s_tlast_i ,
packet_sof => mm2s_packet_sof ,
packet_eof => mm2s_packet_eof
);
end generate INCLUDE_MM2S_SOF_EOF_GENERATOR;
-- If MM2S channel not included then exclude sof/eof generator
EXCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_packet_sof <= '0';
mm2s_packet_eof <= '0';
end generate EXCLUDE_MM2S_SOF_EOF_GENERATOR;
INCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 1 generate
begin
-------------------------------------------------------------------------------
-- S2MM DMA Controller
-------------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_dma_v7_1_9.axi_dma_s2mm_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => APPLENGTH_ENABLE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
soft_reset => soft_reset ,
-- S2MM Control and Status
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
s2mm_keyhole => s2mm_dmacr(DMACR_KH_BIT) ,
s2mm_halted => s2mm_dmasr(DMASR_HALTED_BIT) ,
s2mm_packet_eof_out => s2mm_eof_s2mm ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_stop => s2mm_stop ,
s2mm_ftch_err_early => s2mm_ftch_err_early ,
s2mm_ftch_stale_desc => s2mm_ftch_stale_desc ,
s2mm_desc_flush => s2mm_desc_flush ,
s2mm_tailpntr_enble => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_error => s2mm_error ,
mm2s_error => mm2s_error ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- Simple DMA Mode Signals
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_smple_done => s2mm_smpl_done ,
s2mm_interr_set => s2mm_smpl_interr_set ,
s2mm_slverr_set => s2mm_smpl_slverr_set ,
s2mm_decerr_set => s2mm_smpl_decerr_set ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Currently Being Processed Descriptor
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
-- s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
-- s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
-- s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
s2mm_err => s2mm_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Stream to Memory Map Status Stream Interface
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
-- If S2MM channel included then include sof/eof generator
-------------------------------------------------------------------------------
-- S2MM SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_S2MM_SOFEOF_GEN : entity axi_dma_v7_1_9.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid ,
axis_tlast => s_axis_s2mm_tlast ,
packet_sof => s2mm_packet_sof ,
packet_eof => s2mm_packet_eof
);
end generate INCLUDE_S2MM_SOF_EOF_GENERATOR;
-- If S2MM channel not included then exclude sof/eof generator
EXCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_packet_sof <= '0';
s2mm_packet_eof <= '0';
end generate EXCLUDE_S2MM_SOF_EOF_GENERATOR;
INCLUDE_S2MM_GATE : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
cmpt_updt <= m_axis_s2mm_sts_tvalid & s2mm_eof_s2mm;
I_S2MM_GATE_GEN : entity axi_dma_v7_1_9.axi_dma_s2mm
generic map (
C_FAMILY => C_FAMILY
)
port map (
clk_in => m_axi_s2mm_aclk,
sg_clk => axi_sg_aclk,
resetn => s2mm_prmry_resetn,
reset_sg => m_axi_sg_aresetn,
s2mm_tvalid => s_axis_s2mm_tvalid,
s2mm_tready => s_axis_s2mm_tready_i,
s2mm_tlast => s_axis_s2mm_tlast,
s2mm_tdest => s_axis_s2mm_tdest,
s2mm_tuser => s_axis_s2mm_tuser,
s2mm_tid => s_axis_s2mm_tid,
desc_available => s_axis_s2mm_cmd_tvalid_split,
-- s2mm_eof => s2mm_eof_s2mm,
s2mm_eof_det => cmpt_updt, --m_axis_s2mm_sts_tvalid, --s2mm_eof_s2mm,
ch2_update_active => ch2_update_active,
tdest_out => tdest_out_int,
same_tdest => same_tdest,
-- to DM
-- updt_cmpt => updt_cmpt,
s2mm_desc_info => s2mm_desc_info_in,
s2mm_tvalid_out => open, --s_axis_s2mm_tvalid_int,
s2mm_tready_out => open, --s_axis_s2mm_tready_i,
s2mm_tlast_out => open, --s_axis_s2mm_tlast_int,
s2mm_tdest_out => open
);
end generate INCLUDE_S2MM_GATE;
INCLUDE_S2MM_NOGATE : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
updt_cmpt <= '0';
tdest_out_int <= (others => '0');
same_tdest <= '0';
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid;
s_axis_s2mm_tlast_int <= s_axis_s2mm_tlast;
end generate INCLUDE_S2MM_NOGATE;
MM2S_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_MM2S = 1) generate
begin
CLOCKS : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt <= axi_sg_aclk;
end generate CLOCKS;
CLOCKS_SYNC : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt <= m_axi_mm2s_aclk;
end generate CLOCKS_SYNC;
I_COMMAND_MM2S_SPLITTER : entity axi_dma_v7_1_9.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => ADDR_WIDTH,
C_INCLUDE_S2MM => 0,
C_DM_STATUS_WIDTH => 8
)
port map (
clock => clock_splt, --axi_sg_aclk,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_mm2s_aclk, --axi_sg_aclk,
aresetn => m_axi_mm2s_aresetn,
-- MM2S command coming from MM2S_MNGR
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready_split,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata_split,
-- MM2S split command to DM
s_axis_cmd_tvalid_s => s_axis_mm2s_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_mm2s_cmd_tready,
s_axis_cmd_tdata_s => s_axis_mm2s_cmd_tdata,
tvalid_from_datamover => m_axis_mm2s_sts_tvalid_int,
status_in => m_axis_mm2s_sts_tdata_int,
tvalid_unsplit => m_axis_mm2s_sts_tvalid,
status_out => m_axis_mm2s_sts_tdata,
tlast_stream_data => m_axis_mm2s_tlast_i_mcdma,
tready_stream_data => m_axis_mm2s_tready,
tlast_unsplit => m_axis_mm2s_tlast_i,
tlast_unsplit_user => m_axis_mm2s_tlast_i_user
);
end generate MM2S_SPLIT;
MM2S_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_MM2S = 1) generate
begin
s_axis_mm2s_cmd_tvalid <= s_axis_mm2s_cmd_tvalid_split;
s_axis_mm2s_cmd_tready_split <= s_axis_mm2s_cmd_tready;
s_axis_mm2s_cmd_tdata <= s_axis_mm2s_cmd_tdata_split ((ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_mm2s_sts_tvalid <= m_axis_mm2s_sts_tvalid_int;
m_axis_mm2s_sts_tdata <= m_axis_mm2s_sts_tdata_int;
m_axis_mm2s_tlast_i <= m_axis_mm2s_tlast_i_mcdma;
m_axis_mm2s_tlast_i_user <= '0';
end generate MM2S_SPLIT_NOMCDMA;
S2MM_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
CLOCKS_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt_s2mm <= axi_sg_aclk;
end generate CLOCKS_S2MM;
CLOCKS_SYNC_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt_s2mm <= m_axi_s2mm_aclk;
end generate CLOCKS_SYNC_S2MM;
I_COMMAND_S2MM_SPLITTER : entity axi_dma_v7_1_9.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => ADDR_WIDTH,
C_INCLUDE_S2MM => C_INCLUDE_S2MM,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH
)
port map (
clock => clock_splt_s2mm,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_s2mm_aclk, --axi_sg_aclk, --m_axi_s2mm_aclk,
aresetn => m_axi_s2mm_aresetn,
-- S2MM command coming from S2MM_MNGR
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready_split,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata_split,
-- S2MM split command to DM
s_axis_cmd_tvalid_s => s_axis_s2mm_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_s2mm_cmd_tready,
s_axis_cmd_tdata_s => s_axis_s2mm_cmd_tdata,
tvalid_from_datamover => m_axis_s2mm_sts_tvalid_int,
status_in => m_axis_s2mm_sts_tdata_int,
tvalid_unsplit => m_axis_s2mm_sts_tvalid,
status_out => m_axis_s2mm_sts_tdata,
tlast_stream_data => '0',
tready_stream_data => '0',
tlast_unsplit => open,
tlast_unsplit_user => open
);
end generate S2MM_SPLIT;
S2MM_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
s_axis_s2mm_cmd_tvalid <= s_axis_s2mm_cmd_tvalid_split;
s_axis_s2mm_cmd_tready_split <= s_axis_s2mm_cmd_tready;
s_axis_s2mm_cmd_tdata <= s_axis_s2mm_cmd_tdata_split ((ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_s2mm_sts_tvalid <= m_axis_s2mm_sts_tvalid_int;
m_axis_s2mm_sts_tdata <= m_axis_s2mm_sts_tdata_int;
end generate S2MM_SPLIT_NOMCDMA;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1_10.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_MM2S_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE,
C_MM2S_BURST_SIZE => C_MM2S_BURST_SIZE,
C_MM2S_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF,
C_ENABLE_CACHE_USER => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_SKID_BUF => skid_enable, --"11111",
C_MICRO_DMA => C_MICRO_DMA,
C_CMD_WIDTH => CMD_WIDTH,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_S2MM_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE,
C_S2MM_BURST_SIZE => C_S2MM_BURST_SIZE,
C_S2MM_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_mm2s_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata
(((8*C_ENABLE_MULTI_CHANNEL)+
ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid_int ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata_int ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr_internal ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_aruser => m_axi_mm2s_aruser ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast_i_mcdma ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_s2mm_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata (
((8*C_ENABLE_MULTI_CHANNEL)+
ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid_int ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata_int ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr_internal ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awuser => m_axi_s2mm_awuser ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready_i ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
| gpl-3.0 | 734da1f136cb2c12ebc11ef008eb30f5 | 0.438506 | 3.785162 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_scatter.vhd | 3 | 69,152 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_strb_gen2;
use axi_datamover_v5_1_10.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_10.axi_datamover_fifo;
use axi_datamover_v5_1_10.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_10.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
| gpl-3.0 | 8ba5330c3eb8f1a989888240d6139000 | 0.437023 | 4.719951 | false | false | false | false |
snow4life/PipelinedDLX | DLX.vhd | 1 | 131,972 | -- Reset at least for more than one Tck
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity DLX is
port( CLOCK: in std_logic;
RESET: in std_logic;
PORT_PC: out std_logic_vector(31 downto 0);
PORT_INSTR_IRAM:in std_logic_vector(31 downto 0);
PORT_REGB: out std_logic_vector(31 downto 0);
PORT_ALU: out std_logic_vector(31 downto 0);
PORT_DATA_RAM: in std_logic_vector(31 downto 0);
PORT_SIZE: out std_logic_vector(1 downto 0);
PORT_R_W: out std_logic;
PORT_EN: out std_logic;
RF_ENABLE: out std_logic;
RF_RD1: out std_logic;
RF_RD2: out std_logic;
RF_WR: out std_logic;
RF_ADD_WR: out std_logic_vector(4 downto 0);
RF_ADD_RD1: out std_logic_vector(4 downto 0);
RF_ADD_RD2: out std_logic_vector(4 downto 0);
RF_DATAIN: out std_logic_vector(31 downto 0);
RF_OUT1: in std_logic_vector(31 downto 0);
RF_OUT2: in std_logic_vector(31 downto 0));
end DLX;
architecture RTL of DLX is
constant ARCH: integer:=32;
constant RF_MODULE: integer:=5;
constant RAM_MODULE:integer:=6;
----------------------------------------------------------------
-- Instruction fetch stage signals
----------------------------------------------------------------
signal IF_PC_EN: std_logic;
signal IF_STALL: std_logic;
signal IF_STALL_SEL: std_logic;
signal IF_NOT_RESET: std_logic;
signal IF_PC: std_logic_vector(ARCH-1 downto 0);
signal IF_NEXT_PC: std_logic_vector(ARCH-1 downto 0);
signal IF_PC_INC: std_logic_vector(ARCH-1 downto 0);
signal IF_INSTR: std_logic_vector(ARCH-1 downto 0);
signal IF_INSTR_IRAM: std_logic_vector(ARCH-1 downto 0);
----------------------------------------------------------------
-- Instruction decode stage signals
----------------------------------------------------------------
signal ID_SIGN_EXT_CONTROL: std_logic;
signal ID_REGA_ZERO: std_logic;
signal ID_PC_SRC: std_logic;
signal ID_EN_RD1: std_logic;
signal ID_EN_RD2: std_logic;
signal ID_RF_ENABLE: std_logic;
signal ID_STALL: std_logic;
signal ID_HAZARD_EX: std_logic;
signal ID_HAZARD_MEM: std_logic;
signal ID_HAZARD_WB: std_logic;
signal ID_ADD1: std_logic_vector(4 downto 0);
signal ID_ADD2: std_logic_vector(4 downto 0);
signal ID_JUMP: std_logic_vector(1 downto 0);
signal ID_IMM16: std_logic_vector(((ARCH/2)-1) downto 0);
signal ID_IMM26_SHL2: std_logic_vector(25 downto 0);
signal ID_PC: std_logic_vector(ARCH-1 downto 0);
signal ID_PC_INC: std_logic_vector(ARCH-1 downto 0);
signal ID_PC_CONC: std_logic_vector(ARCH-1 downto 0);
signal ID_PC_SUM: std_logic_vector(ARCH-1 downto 0);
signal ID_IMM16_EXT: std_logic_vector(ARCH-1 downto 0);
signal ID_IMM16_SHL2: std_logic_vector(ARCH-1 downto 0);
signal ID_INSTR: std_logic_vector(ARCH-1 downto 0);
signal ID_INSTR_AFTER_CU: std_logic_vector(ARCH-1 downto 0);
signal ID_REGA: std_logic_vector(ARCH-1 downto 0);
signal ID_REGB: std_logic_vector(ARCH-1 downto 0);
signal ID_JUMP_PC_SRC: std_logic_vector(ARCH-1 downto 0);
----------------------------------------------------------------
-- Execution stage signals
----------------------------------------------------------------
signal EX_A_SEL: std_logic;
signal EX_ADD_SUB: std_logic;
signal EX_SEL: std_logic;
signal EX_ZERO: std_logic;
signal EX_OVERFLOW: std_logic;
signal EX_STALL: std_logic;
signal EX_COMPARATOR_CW: std_logic_vector(5 downto 0);
signal EX_SHIFTER_CW: std_logic_vector(2 downto 0);
signal EX_LOGIC_CW: std_logic_vector(3 downto 0);
signal EX_ALU_SEL: std_logic_vector(1 downto 0);
signal EX_B_SEL: std_logic_vector(1 downto 0);
signal EX_REGA: std_logic_vector(ARCH-1 downto 0);
signal EX_REGB: std_logic_vector(ARCH-1 downto 0);
signal EX_IMM16_EXT: std_logic_vector(ARCH-1 downto 0);
signal EX_PC: std_logic_vector(ARCH-1 downto 0);
signal EX_ALU_A: std_logic_vector(ARCH-1 downto 0);
signal EX_ALU_B: std_logic_vector(ARCH-1 downto 0);
signal EX_ALU_OUT: std_logic_vector(ARCH-1 downto 0);
signal EX_MULT_OUT: std_logic_vector(ARCH-1 downto 0);
signal EX_OUT: std_logic_vector(ARCH-1 downto 0);
signal EX_INSTR: std_logic_vector(ARCH-1 downto 0);
----------------------------------------------------------------
-- Memory stage signals
----------------------------------------------------------------
signal MEM_R_W: std_logic;
signal MEM_EN: std_logic;
signal MEM_STALL: std_logic;
signal MEM_SIZE: std_logic_vector(1 downto 0);
signal MEM_REGB: std_logic_vector(ARCH-1 downto 0);
signal MEM_ALU: std_logic_vector(ARCH-1 downto 0);
signal MEM_DATA_RAM: std_logic_vector(ARCH-1 downto 0);
signal MEM_INSTR: std_logic_vector(ARCH-1 downto 0);
----------------------------------------------------------------
-- Write-back stage signals
----------------------------------------------------------------
signal WB_DATA_SEL: std_logic;
signal WB_SIGN_EXT_16_CONTROL: std_logic;
signal WB_EN_WR: std_logic;
signal WB_STALL: std_logic;
signal WB_EXT_SEL: std_logic_vector(1 downto 0);
signal WB_ADD_WR: std_logic_vector(4 downto 0);
signal WB_DATA_RAM: std_logic_vector(ARCH-1 downto 0);
signal WB_ALU: std_logic_vector(ARCH-1 downto 0);
signal WB_INSTR: std_logic_vector(ARCH-1 downto 0);
signal WB_DATA: std_logic_vector(ARCH-1 downto 0);
signal WB_DATA_EXT_8: std_logic_vector(ARCH-1 downto 0);
signal WB_DATA_EXT_16: std_logic_vector(ARCH-1 downto 0);
signal WB_DATA_WR: std_logic_vector(ARCH-1 downto 0);
----------------------------------------------------------------
-- Pipeline register enable signals
----------------------------------------------------------------
signal IF_ID_PC_INC_EN: std_logic;
signal IF_ID_INSTR_EN: std_logic;
signal IF_ID_PC_EN: std_logic;
signal ID_EX_REGA_EN: std_logic;
signal ID_EX_REGB_EN: std_logic;
signal ID_EX_IMM16_EXT_EN: std_logic;
signal ID_EX_PC_EN: std_logic;
signal ID_EX_INSTR_EN: std_logic;
signal EX_MEM_REGB_EN: std_logic;
signal EX_MEM_OUT_EN: std_logic;
signal EX_MEM_INSTR_EN: std_logic;
signal MEM_WB_DATA_RAM_EN: std_logic;
signal MEM_WB_ALU_EN: std_logic;
signal MEM_WB_INSTR_EN: std_logic;
----------------------------------------------------------------
-- Components
----------------------------------------------------------------
component ALU
port( A: in std_logic_vector(31 downto 0);
B: in std_logic_vector(31 downto 0);
ALU_SEL: in std_logic_vector(1 downto 0);
COMPARATOR_CW: in std_logic_vector(5 downto 0);
LOGIC_CW: in std_logic_vector(3 downto 0);
SHIFTER_CW: in std_logic_vector(2 downto 0);
ADD_SUB: in std_logic;
ALU_OUT: out std_logic_vector(31 downto 0);
ZERO: out std_logic;
OVERFLOW: out std_logic);
end component;
component BOOTH
generic(N: integer);
port( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
P: out std_logic_vector((2*N)-1 downto 0));
end component;
component register_generic
generic(N: integer);
port( CK: in std_logic;
RESET: in std_logic;
ENABLE: in std_logic;
D: in std_logic_vector(N-1 downto 0);
Q: out std_logic_vector(N-1 downto 0));
end component;
component flip_flop
port( CK: in std_logic;
RESET: in std_logic;
ENABLE: in std_logic;
D: in std_logic;
Q: out std_logic);
end component;
component ID_SIGN_EXT
port( INPUT: in std_logic_vector(15 downto 0);
SIGN_EXT_CONTROL: in std_logic;
OUTPUT: out std_logic_vector(31 downto 0));
end component;
component ID_IMM16_SIGN_EXT
port( INPUT: in std_logic_vector(15 downto 0);
OUTPUT: out std_logic_vector(31 downto 0));
end component;
component WB_SIGN_EXT_16
port( INPUT: in std_logic_vector(15 downto 0);
SIGN_EXT_CONTROL: in std_logic;
OUTPUT: out std_logic_vector(31 downto 0));
end component;
component WB_SIGN_EXT_8
port( INPUT: in std_logic_vector(7 downto 0);
OUTPUT: out std_logic_vector(31 downto 0));
end component;
component zero
generic(N: integer);
port( INPUT: in std_logic_vector(N-1 downto 0);
ZERO: out std_logic);
end component;
begin
----------------------------------------------------------------
-- Component instances
----------------------------------------------------------------
ALU_instance: ALU
port map( A => EX_ALU_A,
B => EX_ALU_B,
ALU_SEL => EX_ALU_SEL,
COMPARATOR_CW => EX_COMPARATOR_CW,
LOGIC_CW => EX_LOGIC_CW,
SHIFTER_CW => EX_SHIFTER_CW,
ADD_SUB => EX_ADD_SUB,
ALU_OUT => EX_ALU_OUT,
ZERO => EX_ZERO,
OVERFLOW => EX_OVERFLOW);
BOOTH_instance: BOOTH
generic map(N => (ARCH/2))
port map( A => EX_ALU_A(((ARCH/2)-1) downto 0), -- lower half of A
B => EX_ALU_B(((ARCH/2)-1) downto 0), -- lower half of B
P => EX_MULT_OUT);
PC_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => IF_PC_EN,
D => IF_NEXT_PC,
Q => IF_PC);
ID_SIGN_EXT_instance: ID_SIGN_EXT
port map ( INPUT => ID_IMM16,
SIGN_EXT_CONTROL=> ID_SIGN_EXT_CONTROL,
OUTPUT => ID_IMM16_EXT);
ID_IMM16_SIGN_EXT_instance: ID_IMM16_SIGN_EXT
port map ( INPUT => ID_IMM16,
OUTPUT => ID_IMM16_SHL2);
WB_SIGN_EXT_16_instance: WB_SIGN_EXT_16
port map ( INPUT => WB_DATA((ARCH/2)-1 downto 0),
SIGN_EXT_CONTROL=> WB_SIGN_EXT_16_CONTROL,
OUTPUT => WB_DATA_EXT_16);
WB_SIGN_EXT_8_instance: WB_SIGN_EXT_8
port map ( INPUT => WB_DATA(7 downto 0),
OUTPUT => WB_DATA_EXT_8);
zero_instance: zero
generic map(N => ARCH)
port map( INPUT => ID_REGA,
ZERO => ID_REGA_ZERO);
IF_STALL_REG_instance: flip_flop
port map( CK => CLOCK,
RESET => RESET,
ENABLE => '1',
D => IF_NOT_RESET,
Q => IF_STALL_SEL);
----------------------------------------------------------------
-- Pipeline register instances
----------------------------------------------------------------
-- IF/ID
IF_ID_PC_INC_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => IF_ID_PC_INC_EN,
D => IF_PC_INC,
Q => ID_PC_INC);
IF_ID_INSTR_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => IF_ID_INSTR_EN,
D => IF_INSTR,
Q => ID_INSTR);
IF_ID_PC_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => IF_ID_PC_EN,
D => IF_PC,
Q => ID_PC);
-- ID/EX
ID_EX_REGA_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => ID_EX_REGA_EN,
D => ID_REGA,
Q => EX_REGA);
ID_EX_REGB_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => ID_EX_REGB_EN,
D => ID_REGB,
Q => EX_REGB);
ID_EX_IMM16_EXT_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => ID_EX_IMM16_EXT_EN,
D => ID_IMM16_EXT,
Q => EX_IMM16_EXT);
ID_EX_PC_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => ID_EX_PC_EN,
D => ID_PC,
Q => EX_PC);
ID_EX_INSTR_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => ID_EX_INSTR_EN,
D => ID_INSTR_AFTER_CU,
Q => EX_INSTR);
-- EX/MEM
EX_MEM_REGB_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => EX_MEM_REGB_EN,
D => EX_REGB,
Q => MEM_REGB);
EX_MEM_OUT_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => EX_MEM_OUT_EN,
D => EX_OUT,
Q => MEM_ALU);
EX_MEM_INSTR_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => EX_MEM_INSTR_EN,
D => EX_INSTR,
Q => MEM_INSTR);
-- MEM/WB
MEM_WB_DATA_RAM_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => MEM_WB_DATA_RAM_EN,
D => MEM_DATA_RAM,
Q => WB_DATA_RAM);
MEM_WB_ALU_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => MEM_WB_ALU_EN,
D => MEM_ALU,
Q => WB_ALU);
MEM_WB_INSTR_REG_instance: register_generic
generic map(N => ARCH)
port map( CK => CLOCK,
RESET => RESET,
ENABLE => MEM_WB_INSTR_EN,
D => MEM_INSTR,
Q => WB_INSTR);
----------------------------------------------------------------
-- Instruction fetch stage
----------------------------------------------------------------
IF_NEXT_PC <= IF_PC_INC when ID_PC_SRC = '0' else
ID_JUMP_PC_SRC when ID_PC_SRC = '1';
IF_STALL <= ID_STALL when IF_STALL_SEL = '1' else
'0' when IF_STALL_SEL = '0';
IF_INSTR <= IF_INSTR_IRAM when IF_STALL = '0' else
"01010100000000000000000000000000" when IF_STALL = '1'; -- nop
IF_PC_INC <= IF_PC + conv_std_logic_vector(4, ARCH);
IF_NOT_RESET<= not RESET;
PORT_PC <= IF_PC;
IF_INSTR_IRAM <= PORT_INSTR_IRAM;
-- Control unit
IF_control_unit_process: process(IF_STALL)
begin
if IF_STALL = '0' then
-- Next stage stalled
IF_PC_EN <= '1';
else
IF_PC_EN <= '0';
end if;
end process;
----------------------------------------------------------------
-- Instruction decode stage
----------------------------------------------------------------
ID_JUMP_PC_SRC <= ID_REGA when ID_JUMP = "00" else
ID_PC_SUM when ID_JUMP = "01" else
ID_PC_CONC when ID_JUMP = "10" else
ID_REGA when ID_JUMP = "11";
RF_ENABLE <= ID_RF_ENABLE;
RF_RD1 <= ID_EN_RD1;
RF_RD2 <= ID_EN_RD2;
RF_WR <= WB_EN_WR;
RF_ADD_WR <= WB_ADD_WR;
RF_ADD_RD1 <= ID_ADD1;
RF_ADD_RD2 <= ID_ADD2;
RF_DATAIN <= WB_DATA_WR;
ID_REGA <= RF_OUT1;
ID_REGB <= RF_OUT2;
ID_IMM26_SHL2 <= ID_INSTR(25 downto 0);
ID_IMM16 <= ID_INSTR(15 downto 0);
ID_PC_CONC <= ID_PC(31 downto 26) & ID_IMM26_SHL2(25 downto 0);
ID_PC_SUM <= ID_PC + ID_IMM16_SHL2;
ID_ADD1 <= ID_INSTR(25 downto 21);
ID_ADD2 <= ID_INSTR(20 downto 16);
IF_ID_PC_INC_EN <= not IF_STALL;
IF_ID_INSTR_EN <= not IF_STALL;
IF_ID_PC_EN <= not IF_STALL;
-- Control unit
ID_control_unit_process: process(EX_STALL, ID_INSTR, ID_ADD1, ID_ADD2, WB_ADD_WR, WB_EN_WR, ID_REGA_ZERO, EX_INSTR, MEM_INSTR, WB_INSTR, WB_DATA, ID_HAZARD_EX, ID_HAZARD_MEM, ID_HAZARD_WB, ID_REGA, ID_REGB)
begin
ID_RF_ENABLE <= '1';
if EX_STALL = '1' then
-- Next stage stalled
ID_STALL <= '1';
ID_INSTR_AFTER_CU <= "01010100000000000000000000000000"; -- nop ID_INSTR;--
ID_EN_RD1 <= '0';
ID_EN_RD2 <= '0';
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
else
if ((ID_HAZARD_EX = '1') or (ID_HAZARD_MEM = '1') or (ID_HAZARD_WB = '1')) then
-- Stage stall
ID_STALL <= '1';
ID_INSTR_AFTER_CU <= "01010100000000000000000000000000"; -- nop ID_INSTR;--
else
-- No stall
ID_STALL <= '0';
ID_INSTR_AFTER_CU <= ID_INSTR;
end if;
if ID_INSTR(31 downto 26) = "000000" then
-- R-Type instruction
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
-- WB data hazard
if ((WB_ADD_WR = ID_ADD1) or (WB_ADD_WR = ID_ADD2)) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011") or (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000")) then
-- j, jal, sw, sb instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if ((MEM_INSTR(20 downto 16) = ID_ADD1) or (MEM_INSTR(20 downto 16) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011") or (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000")) then
-- j, jal, sw, sb instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if ((EX_INSTR(20 downto 16) = ID_ADD1) or (EX_INSTR(20 downto 16) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
if ID_INSTR(10 downto 0) = "00000100000" then
-- add
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000100100" then
-- and
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000100101" then
-- or
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000101101" then
-- sge
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000101100" then
-- sle
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000000100" then
-- sll
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000101001" then
-- sne
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000000110" then
-- srl
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000100010" then
-- sub
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000100110" then
-- xor
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000100001" then
-- addu
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000101000" then
-- seq
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000111101" then
-- sgeu
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000101011" then
-- sgt
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000111011" then
-- sgtu
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000101010" then
-- slt
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000111010" then
-- sltu
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000000111" then
-- sra
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
elsif ID_INSTR(10 downto 0) = "00000100011" then
-- subu
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
else
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
end if;
elsif ID_INSTR(31 downto 26) = "000001" then
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
if ID_INSTR(10 downto 0) = "00000001110" then
-- mult
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
else
ID_EN_RD1 <= '0';
ID_EN_RD2 <= '0';
end if;
-- I-Type
elsif ID_INSTR(31 downto 26) = "001000" then
-- addi
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "001100" then
-- andi
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "000100" then
-- beqz
if ID_REGA_ZERO = '0' then
-- no branch
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
else
-- branch
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '1';
ID_JUMP <= "01";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
end if;
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "000101" then
-- bnez
if ID_REGA_ZERO = '1' then
-- no branch
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
else
-- branch
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '1';
ID_JUMP <= "01";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
end if;
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "001101" then
-- ori
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "011101" then
-- sgei
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "011100" then
-- slei
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "010100" then
-- slli
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "011001" then
-- snei
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "010110" then
-- srli
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "001010" then
-- subi
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "001110" then
-- xori
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "010011" then
-- jalr
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '1';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "010010" then
-- jr
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '1';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "001111" then
-- lhi
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '0';
ID_EN_RD2 <= '0';
-- Data hazard
ID_HAZARD_WB <= '0';
ID_HAZARD_MEM <= '0';
ID_HAZARD_EX <= '0';
elsif ID_INSTR(31 downto 26) = "011000" then
-- seqi
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "111101" then
-- sgeui
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "011011" then
-- sgti
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "111011" then
-- sgtui
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "011010" then
-- slti
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "111010" then
-- sltui
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "010111" then
-- srai
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "001001" then
-- addui
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "001011" then
-- subui
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if (WB_ADD_WR = ID_ADD1) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "100011" then
-- lw
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if ((WB_ADD_WR = ID_ADD1) or (WB_ADD_WR = ID_ADD2)) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) or (MEM_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) or (EX_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "101011" then
-- sw
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
-- WB data hazard
if ((WB_ADD_WR = ID_ADD1) or (WB_ADD_WR = ID_ADD2)) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) or (MEM_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) or (EX_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "100000" then
-- lb
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if ((WB_ADD_WR = ID_ADD1) or (WB_ADD_WR = ID_ADD2)) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) or (MEM_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) or (EX_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "100100" then
-- lbu
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if ((WB_ADD_WR = ID_ADD1) or (WB_ADD_WR = ID_ADD2)) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) or (MEM_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) or (EX_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "100101" then
-- lhu
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '0';
-- WB data hazard
if ((WB_ADD_WR = ID_ADD1) or (WB_ADD_WR = ID_ADD2)) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) or (MEM_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) or (EX_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
elsif ID_INSTR(31 downto 26) = "101000" then
-- sb
ID_SIGN_EXT_CONTROL <= '1';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '1';
ID_EN_RD2 <= '1';
-- WB data hazard
if ((WB_ADD_WR = ID_ADD1) or (WB_ADD_WR = ID_ADD2)) and (WB_EN_WR = '1') then
ID_HAZARD_WB <= '1';
else
ID_HAZARD_WB <= '0';
end if;
-- MEM data hazard
if MEM_INSTR(31 downto 26) = "010101" then
ID_HAZARD_MEM <= '0';
elsif MEM_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in MEM stage
if (MEM_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif (MEM_INSTR(31 downto 26) = "101011") or (MEM_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in MEM stage
if ((MEM_INSTR(15 downto 11) = ID_ADD1) or (MEM_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
elsif ((MEM_INSTR(31 downto 26) = "000010") or (MEM_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in MEM stage
ID_HAZARD_MEM <= '0';
else
-- other I-Type instruction in MEM stage
if (MEM_INSTR(20 downto 16) = ID_ADD1) or (MEM_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_MEM <= '1';
else
ID_HAZARD_MEM <= '0';
end if;
end if;
-- EX data hazard
if EX_INSTR(31 downto 26) = "010101" then
ID_HAZARD_EX <= '0';
elsif EX_INSTR(31 downto 26) = "000000" then
-- REG-REG instruction in EX stage
if (EX_INSTR(15 downto 11) = ID_ADD1) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif (EX_INSTR(31 downto 26) = "101011") or (EX_INSTR(31 downto 26) = "101000") then
-- sw, sb instruction in EX stage
if ((EX_INSTR(15 downto 11) = ID_ADD1) or (EX_INSTR(15 downto 11) = ID_ADD2)) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
elsif ((EX_INSTR(31 downto 26) = "000010") or (EX_INSTR(31 downto 26) = "000011")) then
-- j, jal instruction in EX stage
ID_HAZARD_EX <= '0';
else
-- other I-Type instruction in EX stage
if (EX_INSTR(20 downto 16) = ID_ADD1) or (EX_INSTR(20 downto 16) = ID_ADD2) then
ID_HAZARD_EX <= '1';
else
ID_HAZARD_EX <= '0';
end if;
end if;
-- J-Type
elsif ID_INSTR(31 downto 26) = "000010" then
-- j
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '1';
ID_JUMP <= "10";
ID_EN_RD1 <= '0';
ID_EN_RD2 <= '0';
-- Data hazard
ID_HAZARD_WB <= '0';
ID_HAZARD_MEM <= '0';
ID_HAZARD_EX <= '0';
elsif ID_INSTR(31 downto 26) = "000011" then
-- jal
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '1';
ID_JUMP <= "10";
ID_EN_RD1 <= '0';
ID_EN_RD2 <= '0';
-- Data hazard
ID_HAZARD_WB <= '0';
ID_HAZARD_MEM <= '0';
ID_HAZARD_EX <= '0';
-- nop
elsif ID_INSTR(31 downto 26) = "010101" then
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '0';
ID_EN_RD2 <= '0';
-- Data hazard
ID_HAZARD_WB <= '0';
ID_HAZARD_MEM <= '0';
ID_HAZARD_EX <= '0';
else
-- nop
ID_SIGN_EXT_CONTROL <= '0';
ID_PC_SRC <= '0';
ID_JUMP <= "00";
ID_EN_RD1 <= '0';
ID_EN_RD2 <= '0';
-- Data hazard
ID_HAZARD_WB <= '0';
ID_HAZARD_MEM <= '0';
ID_HAZARD_EX <= '0';
end if;
end if;
end process;
----------------------------------------------------------------
-- Execution stage
----------------------------------------------------------------
EX_ALU_A <= EX_REGA when EX_A_SEL = '0' else
EX_PC when EX_A_SEL = '1';
EX_ALU_B <= EX_REGB when EX_B_SEL = "00" else
EX_IMM16_EXT when EX_B_SEL = "01" else
conv_std_logic_vector(8, ARCH) when EX_B_SEL = "10" else
EX_REGB when EX_B_SEL = "11";
EX_OUT <= EX_ALU_OUT when EX_SEL = '0' else
EX_MULT_OUT when EX_SEL = '1';
-- Control unit
EX_control_unit_process: process(MEM_STALL, EX_INSTR, CLOCK)
begin
if MEM_STALL = '1' then
-- Next stage stalled
EX_STALL <= '1';
ID_EX_REGA_EN <= '0';
ID_EX_REGB_EN <= '0';
ID_EX_IMM16_EXT_EN <= '0';
ID_EX_PC_EN <= '0';
ID_EX_INSTR_EN <= '0';
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
else
EX_STALL <= '0';
ID_EX_REGA_EN <= '1';
ID_EX_REGB_EN <= '1';
ID_EX_IMM16_EXT_EN <= '1';
ID_EX_PC_EN <= '1';
ID_EX_INSTR_EN <= '1';
if EX_INSTR(31 downto 26) = "000000" then
-- R-Type instruction
if EX_INSTR(10 downto 0) = "00000100000" then
-- add
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000100100" then
-- and
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "1000";
EX_ALU_SEL <= "10";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000100101" then
-- or
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "1110";
EX_ALU_SEL <= "10";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000101101" then
-- sge
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "001000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000101100" then
-- sle
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "100000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000000100" then
-- sll
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "11";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000101001" then
-- sne
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000010";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000000110" then
-- srl
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "101";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "11";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000100010" then
-- sub
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000100110" then
-- xor
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0110";
EX_ALU_SEL <= "10";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000100001" then
-- addu
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000101000" then
-- seq
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000001";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000111101" then
-- sgeu
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "001000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000101011" then
-- sgt
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000100";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000111011" then
-- sgtu
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000100";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000101010" then
-- slt
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "010000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000111010" then
-- sltu
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "010000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000000111" then
-- sra
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "100";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "11";
EX_SEL <= '0';
elsif EX_INSTR(10 downto 0) = "00000100011" then
-- subu
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
else
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
end if;
elsif EX_INSTR(31 downto 26) = "000001" then
if EX_INSTR(10 downto 0) = "00000001110" then
-- mult
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '1';
else
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '1';
end if;
-- I-Type
elsif EX_INSTR(31 downto 26) = "001000" then
-- addi
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "001100" then
-- andi
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "1000";
EX_ALU_SEL <= "10";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "000100" then
-- beqz
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "000101" then
-- bnez
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "001101" then
-- ori
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "1110";
EX_ALU_SEL <= "10";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "011101" then
-- sgei
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "001000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "011100" then
-- slei
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "100000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "010100" then
-- slli
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "11";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "011001" then
-- snei
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000010";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "010110" then
-- srli
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "101";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "11";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "001010" then
-- subi
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "001110" then
-- xori
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0110";
EX_ALU_SEL <= "10";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "010011" then
-- jalr
EX_A_SEL <= '1';
EX_B_SEL <= "10";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "010010" then
-- jr
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "001111" then
-- lhi
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "011000" then
-- seqi
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000001";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "111101" then
-- sgeui
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "001000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "011011" then
-- sgti
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000100";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "111011" then
-- sgtui
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000100";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "011010" then
-- slti
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "010000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "111010" then
-- sltui
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "010000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "01";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "010111" then
-- srai
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "100";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "11";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "001001" then
-- addui
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "001011" then
-- subui
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '0';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "100011" then
-- lw
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "101011" then
-- sw
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "100000" then
-- lb
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "100100" then
-- lbu
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "100101" then
-- lhu
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "101000" then
-- sb
EX_A_SEL <= '0';
EX_B_SEL <= "01";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
-- J-Type
elsif EX_INSTR(31 downto 26) = "000010" then
-- j
EX_A_SEL <= '0';
EX_B_SEL <= "00";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
elsif EX_INSTR(31 downto 26) = "000011" then
-- jal
EX_A_SEL <= '1';
EX_B_SEL <= "10";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
-- nop
elsif EX_INSTR(31 downto 26) = "010101" then
EX_A_SEL <= '0';
EX_B_SEL <= "10";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
else
-- nop
EX_A_SEL <= '0';
EX_B_SEL <= "10";
EX_ADD_SUB <= '1';
EX_COMPARATOR_CW<= "000000";
EX_SHIFTER_CW <= "111";
EX_LOGIC_CW <= "0000";
EX_ALU_SEL <= "00";
EX_SEL <= '0';
end if;
end if;
end process;
----------------------------------------------------------------
-- Memory stage
----------------------------------------------------------------
PORT_REGB <= MEM_REGB;
PORT_ALU <= MEM_ALU;
MEM_DATA_RAM <= PORT_DATA_RAM;
PORT_SIZE <= MEM_SIZE;
PORT_R_W <= MEM_R_W;
PORT_EN <= MEM_EN;
-- Control unit
MEM_control_unit_process: process(WB_STALL, MEM_INSTR, CLOCK)
begin
if WB_STALL = '1' then
-- Next stage stalled
MEM_STALL <= '1';
EX_MEM_REGB_EN <= '0';
EX_MEM_OUT_EN <= '0';
EX_MEM_INSTR_EN <= '0';
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
else
MEM_STALL <= '0';
EX_MEM_REGB_EN <= '1';
EX_MEM_OUT_EN <= '1';
EX_MEM_INSTR_EN <= '1';
if MEM_INSTR(31 downto 26) = "000000" then
-- R-Type instruction
if MEM_INSTR(10 downto 0) = "00000100000" then
-- add
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000100100" then
-- and
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000100101" then
-- or
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000101101" then
-- sge
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000101100" then
-- sle
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000000100" then
-- sll
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000101001" then
-- sne
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000000110" then
-- srl
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000100010" then
-- sub
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000100110" then
-- xor
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000100001" then
-- addu
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000101000" then
-- seq
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000111101" then
-- sgeu
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000101011" then
-- sgt
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000111011" then
-- sgtu
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000101010" then
-- slt
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000111010" then
-- sltu
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000000111" then
-- sra
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(10 downto 0) = "00000100011" then
-- subu
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
else
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
end if;
elsif MEM_INSTR(31 downto 26) = "000001" then
if MEM_INSTR(10 downto 0) = "00000001110" then
-- mult
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
else
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
end if;
-- I-Type
elsif MEM_INSTR(31 downto 26) = "001000" then
-- addi
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "001100" then
-- andi
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "000100" then
-- beqz
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "000101" then
-- bnez
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "001101" then
-- ori
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "011101" then
-- sgei
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "011100" then
-- slei
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "010100" then
-- slli
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "011001" then
-- snei
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "010110" then
-- srli
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "001010" then
-- subi
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "001110" then
-- xori
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "010011" then
-- jalr
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "010010" then
-- jr
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "001111" then
-- lhi
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "011000" then
-- seqi
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "111101" then
-- sgeui
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "011011" then
-- sgti
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "111011" then
-- sgtui
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "011010" then
-- slti
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "111010" then
-- sltui
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "010111" then
-- srai
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "001001" then
-- addui
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "001011" then
-- subui
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "100011" then
-- lw
MEM_R_W <= '1';
MEM_EN <= '1';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "101011" then
-- sw
MEM_R_W <= '0';
MEM_EN <= '1';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "100000" then
-- lb
MEM_R_W <= '1';
MEM_EN <= '1';
MEM_SIZE<= "10";
elsif MEM_INSTR(31 downto 26) = "100100" then
-- lbu
MEM_R_W <= '1';
MEM_EN <= '1';
MEM_SIZE<= "10";
elsif MEM_INSTR(31 downto 26) = "100101" then
-- lhu
MEM_R_W <= '1';
MEM_EN <= '1';
MEM_SIZE<= "01";
elsif MEM_INSTR(31 downto 26) = "101000" then
-- sb
MEM_R_W <= '0';
MEM_EN <= '1';
MEM_SIZE<= "10";
-- J-Type
elsif MEM_INSTR(31 downto 26) = "000010" then
-- j
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
elsif MEM_INSTR(31 downto 26) = "000011" then
-- jal
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
-- nop
elsif MEM_INSTR(31 downto 26) = "010101" then
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
else
-- nop
MEM_R_W <= '0';
MEM_EN <= '0';
MEM_SIZE<= "00";
end if;
end if;
end process;
----------------------------------------------------------------
-- Write-back stage
----------------------------------------------------------------
WB_DATA <= WB_DATA_RAM when WB_DATA_SEL = '0' else
WB_ALU when WB_DATA_SEL = '1';
WB_DATA_WR <= WB_DATA when WB_EXT_SEL = "00" else
WB_DATA_EXT_8 when WB_EXT_SEL = "01" else
WB_DATA_EXT_16 when WB_EXT_SEL = "10" else
WB_DATA when WB_EXT_SEL = "11";
-- Control unit
WB_control_unit_process: process(WB_INSTR, CLOCK)
begin
if WB_INSTR(31 downto 26) = "000000" then
-- R-Type instruction
if WB_INSTR(10 downto 0) = "00000100000" then
-- add
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000100100" then
-- and
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000100101" then
-- or
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000101101" then
-- sge
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000101100" then
-- sle
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000000100" then
-- sll
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000101001" then
-- sne
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000000110" then
-- srl
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000100010" then
-- sub
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000100110" then
-- xor
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000100001" then
-- addu
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000101000" then
-- seq
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000111101" then
-- sgeu
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000101011" then
-- sgt
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000111011" then
-- sgtu
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000101010" then
-- slt
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000111010" then
-- sltu
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000000111" then
-- sra
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(10 downto 0) = "00000100011" then
-- subu
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
else
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= "00000";
WB_EN_WR <= '0';
WB_SIGN_EXT_16_CONTROL <= '1';
end if;
elsif WB_INSTR(31 downto 26) = "000001" then
if WB_INSTR(10 downto 0) = "00000001110" then
-- mult
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
else
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(15 downto 11);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
end if;
-- I-Type
elsif WB_INSTR(31 downto 26) = "001000" then
-- addi
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "001100" then
-- andi
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "000100" then
-- beqz
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '0';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "000101" then
-- bnez
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '0';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "001101" then
-- ori
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "011101" then
-- sgei
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "011100" then
-- slei
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "010100" then
-- slli
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "011001" then
-- snei
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "010110" then
-- srli
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "001010" then
-- subi
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "001110" then
-- xori
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "010011" then
-- jalr
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= "11111";
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "010010" then
-- jr
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "001111" then
-- lhi
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "10";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '0';
elsif WB_INSTR(31 downto 26) = "011000" then
-- seqi
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "111101" then
-- sgeui
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "011011" then
-- sgti
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "111011" then
-- sgtui
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "011010" then
-- slti
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "111010" then
-- sltui
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "010111" then
-- srai
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "001001" then
-- addui
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "001011" then
-- subui
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "100011" then
-- lw
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '0';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "101011" then
-- sw
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '0';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '0';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "100000" then
-- lb
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '0';
WB_EXT_SEL <= "01";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "100100" then
-- lbu
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '0';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "100101" then
-- lhu
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '0';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "101000" then
-- sb
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '0';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '0';
WB_SIGN_EXT_16_CONTROL <= '1';
-- J-Type
elsif WB_INSTR(31 downto 26) = "000010" then
-- j
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
elsif WB_INSTR(31 downto 26) = "000011" then
-- jal
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "10";
WB_ADD_WR <= "11111";
WB_EN_WR <= '1';
WB_SIGN_EXT_16_CONTROL <= '1';
-- nop
elsif WB_INSTR(31 downto 26) = "010101" then
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '0';
WB_SIGN_EXT_16_CONTROL <= '1';
else
-- nop
WB_STALL <= '0';
MEM_WB_DATA_RAM_EN <= '1';
MEM_WB_ALU_EN <= '1';
MEM_WB_INSTR_EN <= '1';
WB_DATA_SEL <= '1';
WB_EXT_SEL <= "00";
WB_ADD_WR <= WB_INSTR(20 downto 16);
WB_EN_WR <= '0';
WB_SIGN_EXT_16_CONTROL <= '1';
end if;
end process;
end architecture RTL; | lgpl-2.1 | d42a65a8566a140804acaa460df39c37 | 0.515647 | 2.582824 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_valptr.vhd | 2 | 1,454 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_dhuff_tbl_valptr;
architecture augh of p_jinfo_ac_dhuff_tbl_valptr is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(8 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | cc9614b14fea203cdc13835fb039194d | 0.675378 | 2.862205 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2532.vhd | 4 | 1,783 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2532.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n02i02532ent IS
END c07s03b05x00p06n02i02532ent;
ARCHITECTURE c07s03b05x00p06n02i02532arch OF c07s03b05x00p06n02i02532ent IS
signal R1 : REAL := 10.0;
signal I2 : INTEGER := 0;
BEGIN
TESTING: PROCESS
BEGIN
I2 <= INTEGER(R1);
wait for 5 ns;
assert NOT( I2=10 )
report "***PASSED TEST: c07s03b05x00p06n02i02532"
severity NOTE;
assert ( I2=10 )
report "***FAILED TEST: c07s03b05x00p06n02i02532 - The type conversion from real to integer type failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n02i02532arch;
| gpl-2.0 | 53d1672335e9f7a5710f3b2f4bbff0fe | 0.665171 | 3.653689 | false | true | false | false |
tgingold/ghdl | libraries/synopsys/std_logic_misc.vhdl | 2 | 6,037 | --------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library SYNOPSYS;
--use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR; --!V08
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
--START-!V08
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
--END-!V08
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--START-!V08
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--END-!V08
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
--START-!V08
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
--END-!V08
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
| gpl-2.0 | 73b8bc7905193471e29a62be4af0f1a1 | 0.533378 | 4.019308 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1231/top.vhdl | 1 | 1,395 | library ieee;
use ieee.std_logic_1164.all;
entity SINGLE_SRL is
generic (SRL_WIDTH : integer := 24);
port (
clk : in std_logic;
inp : in std_logic;
outp : out std_logic);
end SINGLE_SRL;
architecture beh of SINGLE_SRL is
signal shift_reg : std_logic_vector (SRL_WIDTH-1 downto 0);
begin
assert SRL_WIDTH <= 17
report "The size of Shift Register exceeds the size of a single SRL"
severity FAILURE;
process (clk)
begin
if rising_edge(clk) then
shift_reg <= shift_reg (SRL_WIDTH-2 downto 0) & inp;
end if;
end process;
outp <= shift_reg(SRL_WIDTH-1);
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity TOP is
port (
clk : in std_logic;
inp1, inp2 : in std_logic;
outp1, outp2 : out std_logic);
end TOP;
architecture beh of TOP is
component SINGLE_SRL is
generic (SRL_WIDTH : integer := 16);
port(
clk : in std_logic;
inp : in std_logic;
outp : out std_logic);
end component;
begin
inst1: SINGLE_SRL
generic map (SRL_WIDTH => 13)
port map(
clk => clk,
inp => inp1,
outp => outp1 );
inst2: SINGLE_SRL
generic map (SRL_WIDTH => 18)
port map(
clk => clk,
inp => inp2,
outp => outp2 );
end beh;
| gpl-2.0 | 2c5b93c12b9f434e86027f3896cffa69 | 0.551971 | 3.632813 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc857.vhd | 4 | 10,449 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc857.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00857pkg_2 is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00857pkg_2;
package body c01s03b01x00p12n01i00857pkg_2 is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00857pkg_2;
use work.c01s03b01x00p12n01i00857pkg_2.all;
package c01s03b01x00p12n01i00857pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant dumy : bit_vector(zero to three) := "1010" ;
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00857pkg;
use work.c01s03b01x00p12n01i00857pkg.all;
use work.c01s03b01x00p12n01i00857pkg_2.all;
entity c01s03b01x00p12n01i00857ent_a is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture c01s03b01x00p12n01i00857ent_a of c01s03b01x00p12n01i00857ent_a is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration c01s03b01x00p12n01i00857ent_abench of c01s03b01x00p12n01i00857ent_a is
for c01s03b01x00p12n01i00857ent_a
end for;
end;
use work.c01s03b01x00p12n01i00857pkg.all;
use work.c01s03b01x00p12n01i00857pkg_2.all;
ENTITY c01s03b01x00p12n01i00857ent IS
END c01s03b01x00p12n01i00857ent;
ARCHITECTURE c01s03b01x00p12n01i00857arch OF c01s03b01x00p12n01i00857ent IS
component c01s03b01x00p12n01i00857ent_a
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component c01s03b01x00p12n01i00857ent_a
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : c01s03b01x00p12n01i00857ent_a
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:c01s03b01x00p12n01i00857ent_a
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00857"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00857 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00857arch;
configuration c01s03b01x00p12n01i00857cfg of c01s03b01x00p12n01i00857ent is
for c01s03b01x00p12n01i00857arch
for K
for T5:c01s03b01x00p12n01i00857ent_a use configuration work.c01s03b01x00p12n01i00857ent_abench;
end for;
for G(dumy'low to 3)
for T1:c01s03b01x00p12n01i00857ent_a
use configuration work.c01s03b01x00p12n01i00857ent_abench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 | 31e1f624d225b884ed6c3ee12d07bd65 | 0.61135 | 3.225996 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1292/psl_next_event_e.vhdl | 1 | 1,777 | library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
ch <= seq(index);
data <= to_bit(ch);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity psl_next_event_e is
end entity psl_next_event_e;
architecture psl of psl_next_event_e is
signal clk : std_logic := '0';
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
signal a, b, c : std_logic;
begin
-- 012345678901234
SEQ_A : sequencer generic map ("_-______-______") port map (clk, a);
SEQ_B : sequencer generic map ("___-__-___-__-_") port map (clk, b);
SEQ_C : sequencer generic map ("______-___-____") port map (clk, c);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion holds
assert_NEXT_EVENT_a : assert always (a -> next_event_e(b)[1 to 2](c));
process
begin
for i in 1 to 2*20 loop
wait for 1 ns;
clk <= not clk;
end loop;
wait;
end process;
end architecture psl;
| gpl-2.0 | 36e593619890bca2ac8b3b7b3806654a | 0.568936 | 3.417308 | false | false | false | false |
tgingold/ghdl | testsuite/synth/output01/output06.vhdl | 1 | 360 | library ieee;
use ieee.std_logic_1164.all;
entity output06 is
port (i : std_logic;
o : out std_logic_vector (3 downto 0));
end output06;
architecture behav of output06 is
signal s : std_logic_vector(3 downto 0);
begin
process (i)
begin
s(0) <= i;
s (1) <= not i;
s (3) <= i;
end process;
s (2) <= '0';
o <= s;
end behav;
| gpl-2.0 | 2fdd20f57acde5b944acca0b73a46b79 | 0.583333 | 2.8125 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1137/utestbench.vhdl | 1 | 2,071 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity testbench is
end entity;
architecture simu of testbench is
-- Dummy control
signal clk : std_ulogic := '0';
signal simu_clock_enable : std_ulogic := '1';
-- Dummy source signal
signal data_src : std_ulogic_vector(1 downto 0) := "00";
-- Three destination signals
signal data_dst1 : std_ulogic_vector(1 downto 0) := "11";
signal data_dst2 : std_ulogic_vector(1 downto 0) := "11";
signal data_dst3 : std_ulogic_vector(1 downto 0) := "11";
signal data_dst4 : std_ulogic_vector(1 downto 0) := "11";
begin
-- Solution 1
-- THIS WORKS
process(all)
variable idx : integer;
begin
for c in 0 to 1 loop
idx := c;
data_dst1(idx) <= data_src(idx);
end loop;
end process;
-- Solution 2
-- FIXME THIS DOES NOT WORK, CREATES XXX
gen2 : for c in 0 to 1 generate
process(all)
variable idx : integer;
begin
idx := c;
data_dst2(idx) <= data_src(idx);
end process;
end generate;
-- Solution 4
-- THIS WORKS
gen4 : for c in 0 to 1 generate
process(all)
constant idx : integer := c;
begin
data_dst4(idx) <= data_src(idx);
end process;
end generate;
-- Solution 3
-- THIS WORKS
gen3 : for c in 0 to 1 generate
constant idx : integer := c;
begin
data_dst3(idx) <= data_src(idx);
end generate;
-- Dummy clock generation
clk <= (not clk) and simu_clock_enable after 5 ns;
-- Main testbench process
process
-- To print simulation messages
variable l : line;
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
write(l, string'("Result 1 : "));
write(l, to_string(data_dst1));
writeline(output, l);
write(l, string'("Result 2 : "));
write(l, to_string(data_dst2));
writeline(output, l);
write(l, string'("Result 3 : "));
write(l, to_string(data_dst3));
writeline(output, l);
write(l, string'("Result 4 : "));
write(l, to_string(data_dst4));
writeline(output, l);
simu_clock_enable <= '0';
end process;
end architecture;
| gpl-2.0 | d893d0d310762b4a4d78d10b2634ffa7 | 0.642685 | 2.904628 | false | false | false | false |
tgingold/ghdl | testsuite/synth/memmux01/memmux07.vhdl | 1 | 552 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux07 is
port (ad : std_logic;
val : std_logic_vector (1 downto 0);
dat : std_logic_vector (7 downto 0);
res : out std_logic_vector (7 downto 0));
end memmux07;
architecture behav of memmux07 is
begin
process (ad, val, dat)
variable lo : natural;
variable t : std_logic_vector(7 downto 0);
begin
lo := to_integer(unsigned'(0 => ad));
t := dat;
t (4 * lo + 1 downto 4 * lo) := val;
res <= t;
end process;
end behav;
| gpl-2.0 | 290b962df4c522466edda8b39e0d61ec | 0.61413 | 3.172414 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-b.vhd | 4 | 17,205 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlx-b.vhd,v 1.4 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.4 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
library work;
use work.dlx_instr.all;
architecture behavior of dlx is
begin
interpreter : process
is
type reg_array is array (reg_index) of dlx_bv_word;
variable reg : reg_array;
variable fp_reg : reg_array;
variable PC : dlx_bv_word;
constant PC_incr : dlx_bv_word := X"0000_0004";
variable IR : dlx_bv_word;
alias IR_opcode : dlx_opcode is IR(0 to 5);
alias IR_sp_func : dlx_sp_func is IR(26 to 31);
alias IR_fp_func : dlx_fp_func is IR(27 to 31);
alias IR_rs1 : dlx_reg_addr is IR(6 to 10);
alias IR_rs2 : dlx_reg_addr is IR(11 to 15);
alias IR_Itype_rd : dlx_reg_addr is IR(11 to 15);
alias IR_Rtype_rd : dlx_reg_addr is IR(16 to 20);
alias IR_immed16 : dlx_immed16 is IR(16 to 31);
alias IR_immed26 : dlx_immed26 is IR(6 to 31);
variable disassembled_instr : string(1 to 40);
variable disassembled_instr_len : positive;
variable rs1, rs2, Itype_rd, Rtype_rd : reg_index;
variable mem_addr_reg : dlx_bv_address;
variable mem_data_reg : dlx_bv_word;
variable overflow : boolean;
-- lookup table for result of set instructions
type set_result_table is array (boolean) of dlx_bv_word;
constant set_if : set_result_table := ( false => X"0000_0000",
true => X"0000_0001" );
variable instr_count : natural;
-- local procedures for use within the interpreter
procedure bus_read ( address : in dlx_bv_address;
data_width : in dlx_mem_width;
instr_fetch : in std_logic;
data : out dlx_bv_word ) is
begin
wait until rising_edge(phi1);
if To_bit(reset) = '1' then
return;
end if;
a <= To_X01(address) after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
ifetch <= instr_fetch after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
loop
wait until falling_edge(phi2);
if To_bit(reset) = '1' then
return;
end if;
exit when To_bit(ready) = '1';
end loop;
assert not Is_X(d) report "Bus read data contains unknown bits";
data := To_bitvector(d);
mem_enable <= '0' after Tpd_clk_out;
end procedure bus_read;
procedure bus_write ( address : in dlx_bv_address;
data_width : in dlx_mem_width;
data : in dlx_bv_word ) is
begin
wait until rising_edge(phi1);
if To_bit(reset) = '1' then
return;
end if;
a <= To_X01(address) after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
d <= To_X01Z(data) after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
loop
wait until falling_edge(phi2);
if To_bit(reset) = '1' then
return;
end if;
exit when To_bit(ready) = '1';
end loop;
d <= disabled_dlx_word after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end procedure bus_write;
procedure execute_op_special is
begin
case IR_sp_func is
when sp_func_nop =>
null;
when sp_func_add =>
bv_add(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_addu =>
bv_addu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_sub =>
bv_sub(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_subu =>
bv_subu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_sll =>
reg(Rtype_rd) := reg(rs1) sll bv_to_natural(reg(rs2)(27 to 31));
when sp_func_srl =>
reg(Rtype_rd) := reg(rs1) srl bv_to_natural(reg(rs2)(27 to 31));
when sp_func_sra =>
reg(Rtype_rd) := reg(rs1) sra bv_to_natural(reg(rs2)(27 to 31));
when sp_func_and =>
reg(Rtype_rd) := reg(rs1) and reg(rs2);
when sp_func_or =>
reg(Rtype_rd) := reg(rs1) or reg(rs2);
when sp_func_xor =>
reg(Rtype_rd) := reg(rs1) xor reg(rs2);
when sp_func_sequ =>
reg(Rtype_rd) := set_if( reg(rs1) = reg(rs2) );
when sp_func_sneu =>
reg(Rtype_rd) := set_if( reg(rs1) /= reg(rs2) );
when sp_func_sltu =>
reg(Rtype_rd) := set_if( reg(rs1) < reg(rs2) );
when sp_func_sgtu =>
reg(Rtype_rd) := set_if( reg(rs1) > reg(rs2) );
when sp_func_sleu =>
reg(Rtype_rd) := set_if( reg(rs1) <= reg(rs2) );
when sp_func_sgeu =>
reg(Rtype_rd) := set_if( reg(rs1) >= reg(rs2) );
when sp_func_seq =>
reg(Rtype_rd) := set_if( reg(rs1) = reg(rs2) );
when sp_func_sne =>
reg(Rtype_rd) := set_if( reg(rs1) /= reg(rs2) );
when sp_func_slt =>
reg(Rtype_rd) := set_if( bv_lt(reg(rs1), reg(rs2)) );
when sp_func_sgt =>
reg(Rtype_rd) := set_if( bv_gt(reg(rs1), reg(rs2)) );
when sp_func_sle =>
reg(Rtype_rd) := set_if( bv_le(reg(rs1), reg(rs2)) );
when sp_func_sge =>
reg(Rtype_rd) := set_if( bv_ge(reg(rs1), reg(rs2)) );
when sp_func_movi2s | sp_func_movs2i
| sp_func_movf | sp_func_movd
| sp_func_movfp2i | sp_func_movi2fp =>
report sp_func_names(bv_to_natural(IR_sp_func))
& " instruction not implemented" severity warning;
when others =>
report "undefined special instruction function" severity error;
end case;
end procedure execute_op_special;
procedure execute_op_fparith is
begin
case IR_fp_func is
when fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu
| fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
| fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
| fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f
| fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d
| fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf
| fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned
| fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
report fp_func_names(bv_to_natural(IR_fp_func))
& " instruction not implemented" severity warning;
when others =>
report "undefined floating point instruction function" severity error;
end case;
end procedure execute_op_fparith;
procedure execute_load ( data_width : dlx_mem_width; unsigned : boolean ) is
variable temp : dlx_bv_word;
-- type for least-significant two bits of address
subtype ls_2_addr_bits is bit_vector(1 downto 0);
begin
mem_addr_reg := reg(rs1) + bv_sext(IR_immed16, 32);
bus_read(mem_addr_reg, data_width, '0', mem_data_reg);
if To_bit(reset) = '1' then
return;
end if;
case data_width is
when dlx_mem_width_byte =>
case ls_2_addr_bits'(mem_addr_reg(1 downto 0)) is
when B"00" =>
temp(0 to 7) := mem_data_reg(0 to 7);
when B"01" =>
temp(0 to 7) := mem_data_reg(8 to 15);
when B"10" =>
temp(0 to 7) := mem_data_reg(16 to 23);
when B"11" =>
temp(0 to 7) := mem_data_reg(24 to 31);
end case;
if unsigned then
reg(Itype_rd) := bv_zext(temp(0 to 7), 32);
else
reg(Itype_rd) := bv_sext(temp(0 to 7), 32);
end if;
when dlx_mem_width_halfword =>
if mem_addr_reg(1) = '0' then
temp(0 to 15) := mem_data_reg(0 to 15);
else
temp(0 to 15) := mem_data_reg(16 to 31);
end if;
if unsigned then
reg(Itype_rd) := bv_zext(temp(0 to 15), 32);
else
reg(Itype_rd) := bv_sext(temp(0 to 15), 32);
end if;
when dlx_mem_width_word =>
reg(Itype_rd) := mem_data_reg;
when others =>
null;
end case;
end procedure execute_load;
procedure execute_store ( data_width : dlx_mem_width ) is
variable temp : dlx_bv_word;
-- type for least-significant two bits of address
subtype ls_2_addr_bits is bit_vector(1 downto 0);
begin
mem_addr_reg := reg(rs1) + bv_sext(IR_immed16, 32);
mem_data_reg := X"0000_0000";
case data_width is
when dlx_mem_width_byte =>
case ls_2_addr_bits'(mem_addr_reg(1 downto 0)) is
when B"00" =>
mem_data_reg(0 to 7) := reg(Itype_rd)(0 to 7);
when B"01" =>
mem_data_reg(8 to 15) := reg(Itype_rd)(0 to 7);
when B"10" =>
mem_data_reg(16 to 23) := reg(Itype_rd)(0 to 7);
when B"11" =>
mem_data_reg(24 to 31) := reg(Itype_rd)(0 to 7);
end case;
when dlx_mem_width_halfword =>
if mem_addr_reg(1) = '0' then
mem_data_reg(0 to 15) := reg(Itype_rd)(0 to 15);
else
mem_data_reg(16 to 31) := reg(Itype_rd)(0 to 15);
end if;
when dlx_mem_width_word =>
mem_data_reg := reg(Itype_rd);
when others =>
null;
end case;
bus_write(mem_addr_reg, data_width, mem_data_reg);
end procedure execute_store;
begin -- interpreter
-- reset the processor
d <= disabled_dlx_word;
halt <= '0';
write_enable <= '0';
mem_enable <= '0';
reg(0) := X"0000_0000";
PC := X"0000_0000";
instr_count := 0;
wait on phi2 until falling_edge(phi2) and To_bit(reset) = '0';
-- fetch-decode-execute loop
while To_bit(reset) /= '1' loop
-- fetch next instruction
instr_count := instr_count + 1;
if debug = msg_every_100_instructions and instr_count mod 100 = 0 then
report "instruction count = " & natural'image(instr_count);
end if;
if debug >= msg_each_instruction then
report "fetching instruction";
end if;
bus_read( address => PC, data_width => dlx_mem_width_word,
instr_fetch => '1', data => IR );
exit when To_bit(reset) = '1';
if debug >= trace_each_instruction then
disassemble(IR, disassembled_instr, disassembled_instr_len);
report disassembled_instr(1 to disassembled_instr_len);
end if;
wait until rising_edge(phi1);
-- increment the PC to point to the following instruction
if debug = trace_each_step then
report "incrementing PC";
end if;
PC := bv_addu(PC, PC_incr);
-- decode the instruction
if debug = trace_each_step then
report "decoding instruction";
end if;
rs1 := bv_to_natural(IR_rs1);
rs2 := bv_to_natural(IR_rs2);
Itype_rd := bv_to_natural(IR_Itype_rd);
Rtype_rd := bv_to_natural(IR_Rtype_rd);
-- execute the instruction
if debug = trace_each_step then
report "executing instruction";
end if;
overflow := false;
case IR_opcode is
when op_special =>
execute_op_special;
when op_fparith =>
execute_op_fparith;
when op_j =>
PC := PC + bv_sext(IR_immed26, 32);
when op_jal =>
reg(link_reg) := PC;
PC := PC + bv_sext(IR_immed26, 32);
when op_jr =>
PC := reg(rs1);
when op_jalr =>
reg(link_reg) := PC;
PC := reg(rs1);
when op_beqz =>
if reg(rs1) = X"0000_0000" then
PC := PC + bv_sext(IR_immed16, 32);
end if;
when op_bnez =>
if reg(rs1) /= X"0000_0000" then
PC := PC + bv_sext(IR_immed16, 32);
end if;
when op_addi =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_addui =>
bv_addu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subi =>
bv_sub(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subui =>
bv_subu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_slli =>
reg(Itype_rd) := reg(rs1) sll bv_to_natural(IR_immed16(11 to 15));
when op_srli =>
reg(Itype_rd) := reg(rs1) srl bv_to_natural(IR_immed16(11 to 15));
when op_srai =>
reg(Itype_rd) := reg(rs1) sra bv_to_natural(IR_immed16(11 to 15));
when op_andi =>
reg(Itype_rd) := reg(rs1) and bv_zext(IR_immed16, 32);
when op_ori =>
reg(Itype_rd) := reg(rs1) or bv_zext(IR_immed16, 32);
when op_xori =>
reg(Itype_rd) := reg(rs1) xor bv_zext(IR_immed16, 32);
when op_lhi =>
reg(Itype_rd) := IR_immed16 & X"0000";
when op_sequi =>
reg(Itype_rd) := set_if( reg(rs1) = bv_zext(IR_immed16, 32) );
when op_sneui =>
reg(Itype_rd) := set_if( reg(rs1) /= bv_zext(IR_immed16, 32) );
when op_sltui =>
reg(Itype_rd) := set_if( reg(rs1) < bv_zext(IR_immed16, 32) );
when op_sgtui =>
reg(Itype_rd) := set_if( reg(rs1) > bv_zext(IR_immed16, 32) );
when op_sleui =>
reg(Itype_rd) := set_if( reg(rs1) <= bv_zext(IR_immed16, 32) );
when op_sgeui =>
reg(Itype_rd) := set_if( reg(rs1) >= bv_zext(IR_immed16, 32) );
when op_seqi =>
reg(Itype_rd) := set_if( reg(rs1) = bv_sext(IR_immed16, 32) );
when op_snei =>
reg(Itype_rd) := set_if( reg(rs1) /= bv_sext(IR_immed16, 32) );
when op_slti =>
reg(Itype_rd) := set_if( bv_lt(reg(rs1), bv_sext(IR_immed16, 32)) );
when op_sgti =>
reg(Itype_rd) := set_if( bv_gt(reg(rs1), bv_sext(IR_immed16, 32)) );
when op_slei =>
reg(Itype_rd) := set_if( bv_le(reg(rs1), bv_sext(IR_immed16, 32)) );
when op_sgei =>
reg(Itype_rd) := set_if( bv_ge(reg(rs1), bv_sext(IR_immed16, 32)) );
when op_trap =>
report "TRAP instruction encountered, execution halted" severity note;
halt <= '1' after Tpd_clk_out;
wait until To_bit(reset) = '1';
exit;
when op_lb =>
execute_load(data_width => dlx_mem_width_byte, unsigned => false);
exit when To_bit(reset) = '1';
when op_lh =>
execute_load(data_width => dlx_mem_width_halfword, unsigned => false);
exit when To_bit(reset) = '1';
when op_lw =>
execute_load(data_width => dlx_mem_width_word, unsigned => false);
exit when To_bit(reset) = '1';
when op_lbu =>
execute_load(data_width => dlx_mem_width_byte, unsigned => true);
exit when To_bit(reset) = '1';
when op_lhu =>
execute_load(data_width => dlx_mem_width_halfword, unsigned => true);
exit when To_bit(reset) = '1';
when op_sb =>
execute_store ( data_width => dlx_mem_width_byte );
exit when To_bit(reset) = '1';
when op_sh =>
execute_store ( data_width => dlx_mem_width_halfword );
exit when To_bit(reset) = '1';
when op_sw =>
execute_store ( data_width => dlx_mem_width_word );
exit when To_bit(reset) = '1';
when op_rfe | op_bfpt | op_bfpf | op_lf | op_ld | op_sf | op_sd =>
report opcode_names(bv_to_natural(IR_opcode))
& " instruction not implemented" severity warning;
when others =>
report "undefined instruction" severity error;
end case;
-- fix up R0 in case it was overwritten
reg(0) := X"0000_0000";
-- overflow and divide-by-zero exception handing
-- (not implemented)
if debug = trace_each_step then
report "end of execution";
end if;
end loop;
-- loop is only exited when reset active:
-- process interpreter starts again from beginning
end process interpreter;
end architecture behavior;
| gpl-2.0 | 8f1ecd308a21b7f0f767aaf111a64437 | 0.543389 | 3.308018 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd | 4 | 2,292 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_cache is
end entity tb_cache;
architecture test of tb_cache is
signal halt : bit := '0';
begin
dut : entity work.cache(instrumented)
generic map ( cache_size => 128*1024, block_size => 16,
associativity => 2, benchmark_name => "dhrystone " )
port map ( halt => halt );
halt <= '1' after 10 ns;
end architecture test;
entity tb_cache_read_data is
end entity tb_cache_read_data;
architecture reader of tb_cache_read_data is
begin
process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file open read_mode is "cache-measurements";
variable measurement : measurement_record;
use std.textio.all;
variable L : line;
begin
while not endfile(measurements) loop
read(measurements, measurement);
write(L, measurement.cache_size);
write(L, ' ');
write(L, measurement.block_size);
write(L, ' ');
write(L, measurement.associativity);
write(L, ' ');
write(L, measurement.benchmark_name);
write(L, ' ');
write(L, measurement.miss_rate);
write(L, ' ');
write(L, measurement.ave_access_time);
writeline(output, L);
end loop;
wait;
end process;
end architecture reader;
| gpl-2.0 | 454083ded70d3df74a263c4f744a9a66 | 0.672775 | 3.979167 | false | false | false | false |
tgingold/ghdl | testsuite/synth/cnt01/cnt04.vhdl | 1 | 592 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
entity cnt04 is
port (
clk : in std_logic;
rst : in std_logic;
counter : out std_logic_vector (7 downto 0)
);
end cnt04;
architecture behav of cnt04 is
signal s_count : unsigned(7 downto 0); -- := (others => '0');
begin
process(clk, rst)
begin
if rst = '1' then
s_count <= (others => '0');
elsif rising_edge(clk) then
s_count <= s_count + 1;
end if;
end process;
-- connect internal signal to output
counter <= std_logic_vector(s_count + 1);
end behav;
| gpl-2.0 | 5e6bf01b26271c5a6ceb56eac76f4de0 | 0.60473 | 3.182796 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1101/ent.vhdl | 1 | 2,119 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
generic (
INT : integer := -25;
SL : std_logic := '1'
);
port (
a : in signed(7 downto 0);
b : in signed(7 downto 0);
const : out signed(7 downto 0);
absolute1 : out unsigned(7 downto 0);
absolute2 : out unsigned(7 downto 0);
sum : out signed(8 downto 0);
diff : out signed(8 downto 0);
inv_diff : out signed(8 downto 0);
quarter : out signed(7 downto 0);
int_sum : out signed(8 downto 0);
int_diff : out signed(8 downto 0);
inv_int_sum : out signed(8 downto 0);
inv_int_diff : out signed(8 downto 0);
sl_sum : out signed(8 downto 0);
sl_diff : out signed(8 downto 0);
inv_sl_sum : out signed(8 downto 0);
inv_sl_diff : out signed(8 downto 0);
lt : out boolean;
le : out boolean;
eq : out boolean;
neq : out boolean;
ge : out boolean;
gt : out boolean;
int_lt : out boolean;
int_le : out boolean;
int_eq : out boolean;
int_neq : out boolean;
int_ge : out boolean;
int_gt : out boolean;
inv_int_lt : out boolean;
inv_int_le : out boolean;
inv_int_eq : out boolean;
inv_int_neq : out boolean;
inv_int_ge : out boolean;
inv_int_gt : out boolean
);
end;
architecture a of ent is
signal ra, rb : signed(8 downto 0);
begin
ra <= resize(a, 9);
rb <= resize(b, 9);
const <= to_signed(INT, const'length);
absolute1 <= to_unsigned(abs(INT), absolute1'length);
absolute2 <= unsigned(abs(a));
sum <= ra + rb;
diff <= ra + (-rb);
inv_diff <= rb - ra;
quarter <= a / 4;
int_sum <= ra + INT;
int_diff <= ra - INT;
inv_int_sum <= INT + ra;
inv_int_diff <= INT - ra;
sl_sum <= ra + SL;
sl_diff <= ra - SL;
inv_sl_sum <= SL + ra;
inv_sl_diff <= SL - ra;
lt <= a < b;
le <= a <= b;
eq <= a = b;
neq <= a /= b;
ge <= a >= b;
gt <= a > b;
int_lt <= a < INT;
int_le <= a <= INT;
int_eq <= a = INT;
int_neq <= a /= INT;
int_ge <= a >= INT;
int_gt <= a > INT;
inv_int_lt <= INT < b;
inv_int_le <= INT <= b;
inv_int_eq <= INT = b;
inv_int_neq <= INT /= b;
inv_int_ge <= INT >= b;
inv_int_gt <= INT > b;
end;
| gpl-2.0 | ced2c1acdbd16c6c75d288acd6fa4f35 | 0.573384 | 2.475467 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc869.vhd | 4 | 12,336 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc869.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00869pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
subtype dumy is integer range 0 to 3;
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00869pkg;
use work.c01s03b01x00p12n01i00869pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00869pkg.all;
entity test1 is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test1 of test1 is
begin
sigout1 <= false;
sigout2 <= '0';
sigout4 <= error;
sigout5 <= 6;
sigout6 <= 6.0;
sigout7 <= 6 ns;
sigout8 <= 6;
sigout9 <= 6;
sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
end;
configuration test1bench of test1 is
for test1
end for;
end;
use work.c01s03b01x00p12n01i00869pkg.all;
ENTITY c01s03b01x00p12n01i00869ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
port(
dumy : inout bit_vector(zero to three));
END c01s03b01x00p12n01i00869ent;
ARCHITECTURE c01s03b01x00p12n01i00869arch OF c01s03b01x00p12n01i00869ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test1
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test1
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
variable dumb : bit_vector(zero to three);
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***PASSED TEST: c01s03b01x00p12n01i00869"
severity NOTE;
assert ( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***FAILED TEST: c01s03b01x00p12n01i00869 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00869arch;
configuration c01s03b01x00p12n01i00869cfg of c01s03b01x00p12n01i00869ent is
for c01s03b01x00p12n01i00869arch
for K
for all:test1 use configuration work.test1bench;
end for;
for G(0 to 3)
for T1 :test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 | f1f9d561da7ba529db6ec2e40df59769 | 0.572065 | 3.348534 | false | true | false | false |
mistryalok/FPGA | Xilinx/ISE/Basics/muxx/muxx.vhd | 1 | 1,176 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:52:30 04/03/2013
-- Design Name:
-- Module Name: muxx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity muxx is
Port ( S : in bit_VECTOR (1 downto 0);
A : in STD_LOGIC_VECTOR (3 downto 0);
D : out STD_LOGIC);
end muxx;
architecture Behavioral of muxx is
begin
process(s)
--variable d : std_logic;
begin
case s is
when "00" => d <= A(0);
when "01" => d <= A(1);
when "10" => d <= A(2);
when "11" => d <= A(3);
end case;
-- D <= d;
end process;
end Behavioral;
| gpl-3.0 | 478c994312701d89d386cf8dd13c9e9e | 0.511054 | 3.47929 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd | 4 | 1,924 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book:
entity and_or_inv is
port ( a1, a2, b1, b2 : in bit := '1';
y : out bit );
end entity and_or_inv;
-- end of code from book
----------------------------------------------------------------
architecture functional of and_or_inv is
begin
func : y <= not ((a1 and a2) or (b1 and b2));
end architecture functional;
----------------------------------------------------------------
entity inline_23 is
end entity inline_23;
----------------------------------------------------------------
library util; use util.stimulus_generators.all;
architecture test of inline_23 is
signal A, B, C, F : bit;
signal test_input : bit_vector(2 downto 0);
begin
-- code from book:
f_cell : entity work.and_or_inv
port map ( a1 => A, a2 => B, b1 => C, b2 => open, y => F );
-- end of code from book
----------------
stimulus : all_possible_values( bv => test_input,
delay_between_values => 10 ns );
(A, B, C) <= test_input;
verifier :
postponed assert F = not ((A and B) or C)
report "function model produced unexpected result";
end architecture test;
| gpl-2.0 | f4c21ae3f7c41be03285437381ce4799 | 0.602391 | 3.942623 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue1191/mux_fifo.vhd | 1 | 2,376 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mux_fifo_pkg.all;
entity mux_fifo is
generic (g_enabled_channels : std_logic_vector;
g_extend : natural range 0 to 1);
port (rst : in std_logic;
clk : in std_logic;
-- fifo if
fifo_if_in : inout t_mux_fifo_if;
-- out if
dataout : out std_logic_vector;
wr_en : out std_logic;
full : in std_logic);
end entity mux_fifo;
architecture simple of mux_fifo is
type t_state is (s_wait, s_capture, s_write);
signal index : integer := -1;
signal state : t_state;
function DetectFirstNonEmpty (EmptyIn : std_logic_vector) return integer is
begin
for I in EmptyIn'range loop
if EmptyIn(I) = '0' then
return i;
end if;
end loop;
return -1;
end function;
begin
fifo_if_in.clk <= clk;
u_mux : process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
index <= -1;
dataout <= (others => '0');
wr_en <= '0';
fifo_if_in.rd <= (others => '0');
state <= s_wait;
else
case state is
when s_wait =>
-- index <= DetectFirstNonEmpty(empty and enabled_channels);
index <= DetectFirstNonEmpty(fifo_if_in.empty);
dataout <= (others => '0');
wr_en <= '0';
fifo_if_in.rd <= (others => '0');
if index >= 0 then
fifo_if_in.rd(index) <= '1';
state <= s_capture;
end if;
when s_capture =>
dataout <= (others => '0');
wr_en <= '0';
fifo_if_in.rd <= (others => '0');
if not(full) then
state <= s_write;
end if;
when s_write =>
index <= -1;
if g_extend = 1 then
dataout <= fifo_if_in.data(index) & std_logic_vector(to_signed(index, 8));
else
dataout <= fifo_if_in.data(index);
end if;
wr_en <= '1';
fifo_if_in.rd <= (others => '0');
state <= s_wait;
end case;
end if;
end if;
end process u_mux;
end architecture simple;
| gpl-2.0 | d7fcd4ce2b7249a7bf9c5372fdc3b68a | 0.464646 | 3.633028 | false | false | false | false |
pleonex/Efponga | Pong/vga_pll.vhd | 1 | 14,508 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: vga_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.1 Build 201 11/27/2006 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY vga_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END vga_pll;
ARCHITECTURE SYN OF vga_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "-3000",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_pll.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_pll.ppf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_pll.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_pll.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_pll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_pll_inst.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_pll_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_pll_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | ecf15e4890895c9bb745fc505fe93531 | 0.683071 | 3.32295 | false | false | false | false |
tgingold/ghdl | testsuite/synth/arr01/tb_arr07.vhdl | 1 | 1,012 | entity tb_arr07 is
end tb_arr07;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_arr07 is
signal clk : std_logic;
signal val : std_logic_vector(7 downto 0);
signal res : std_logic_vector(7 downto 0);
signal par : std_logic;
begin
dut: entity work.arr07
port map (clk => clk, val => val, res => res, par => par);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
for i in 0 to 15 loop
val <= std_logic_vector (to_unsigned(i, 4) & to_unsigned (15 - i, 4));
pulse;
end loop;
assert res = x"0f" severity failure;
val <= x"e4";
pulse;
assert res = x"1e" severity failure;
val <= x"c5";
pulse;
assert res = x"2d" severity failure;
val <= x"f6";
pulse;
assert res = x"3c" severity failure;
val <= x"57";
pulse;
assert res = x"4b" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 41ebb16c07324f2f330c249a21ab7907 | 0.588933 | 3.1625 | false | false | false | false |
nickg/nvc | test/simp/constarr.vhd | 1 | 454 | entity constarr is
end entity;
architecture a of constarr is
function bit_to_char (b : bit) return character is
type table_t is array (bit) of character;
constant table : table_t := ( '0' => '0',
'1' => '1' ); -- OK
begin
return table(b);
end function;
constant c1 : character := bit_to_char('1');
constant c2 : character := bit_to_char('0');
begin
end architecture;
| gpl-3.0 | 6bd122616d37cd2656f7bf73c05eb7cc | 0.550661 | 3.721311 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1069/ram4.vhdl | 1 | 1,662 | library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH : positive := 7;
WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH - 1 downto 0);
clk_b : in std_logic;
read_b : in std_logic;
write_b : in std_logic;
addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0);
data_read_b : out std_logic_vector(WIDTH - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
begin
process(clk_a, clk_b)
type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
variable store : ram_t := (others => (others => '0'));
begin
if rising_edge(clk_a) then
if read_a = '1' then
data_read_a <= store(to_integer(unsigned(addr_a)));
end if;
if write_a = '1' then
store(to_integer(unsigned(addr_a))) := data_write_a;
end if;
end if;
if rising_edge(clk_b) then
if read_b = '1' then
data_read_b <= store(to_integer(unsigned(addr_b)));
end if;
if write_b = '1' then
store(to_integer(unsigned(addr_b))) := data_write_b;
end if;
end if;
end process;
end behavioral;
| gpl-2.0 | f41e348745e625d68539c13c0f35e912 | 0.524669 | 3.324 | false | false | false | false |
nickg/nvc | test/regress/null1.vhd | 1 | 1,168 | entity null1 is
end entity;
architecture test of null1 is
type int_array is array (integer range <>) of integer;
function get_null return int_array is
variable b : int_array(7 to -999999) := (others => 0);
begin
return b;
end function;
function get_left(x : int_array) return integer is
begin
return x'left;
end function;
function get_right(x : int_array) return integer is
begin
return x'right;
end function;
begin
process is
variable a : int_array(0 to -1) := (others => 0);
variable b : int_array(7 to -999999) := (others => 0);
variable c : int_array(0 downto 1) := (others => 0);
begin
report integer'image(a'length);
assert a'length = 0;
report integer'image(b'length);
assert b'length = 0;
report integer'image(c'length);
assert c'length = 0;
a := get_null;
assert get_left(b) = 7;
-- This is probably wrong according to the LRM but we currently
-- normalise the indexes of null arrays
assert get_right(b) = 6;
wait;
end process;
end architecture;
| gpl-3.0 | 34ec2a472aa2b15aba447736a6dadae2 | 0.587329 | 3.842105 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/IO_DECODER.vhd | 1 | 3,376 | -- IO DECODER for SCOMP
-- This eliminates the need for a lot of NAND decoders or Comparators
-- that would otherwise be spread around the TOP_SCOMP BDF
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY IO_DECODER IS
PORT
(
IO_ADDR : IN STD_LOGIC_VECTOR(7 downto 0);
IO_CYCLE : IN STD_LOGIC;
SWITCH_EN : OUT STD_LOGIC;
LED_EN : OUT STD_LOGIC;
TIMER_EN : OUT STD_LOGIC;
DIG_IN_EN : OUT STD_LOGIC;
HEX1_EN : OUT STD_LOGIC;
HEX2_EN : OUT STD_LOGIC;
LCD_EN : OUT STD_LOGIC;
LED2_EN : OUT STD_LOGIC;
BEEP_EN : OUT STD_LOGIC;
CT_EN : OUT STD_LOGIC;
L_POS_EN : OUT STD_LOGIC;
L_VEL_EN : OUT STD_LOGIC;
L_VELCTRL_EN : OUT STD_LOGIC;
R_POS_EN : OUT STD_LOGIC;
R_VEL_EN : OUT STD_LOGIC;
R_VELCTRL_EN : OUT STD_LOGIC;
SONAR_EN : OUT STD_LOGIC;
I2C_CMD_EN : OUT STD_LOGIC;
I2C_DATA_EN : OUT STD_LOGIC;
I2C_RDY_EN : OUT STD_LOGIC;
UART_D_EN : OUT STD_LOGIC;
UART_S_EN : OUT STD_LOGIC;
XPOS_EN : OUT STD_LOGIC;
YPOS_EN : OUT STD_LOGIC;
TPOS_EN : OUT STD_LOGIC;
POS_RSTN : OUT STD_LOGIC;
RIN_EN : OUT STD_LOGIC;
LIN_EN : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE a OF IO_DECODER IS
SIGNAL IO_INT : INTEGER RANGE 0 TO 511;
begin
IO_INT <= TO_INTEGER(UNSIGNED(IO_CYCLE & IO_ADDR));
-- note that this results in a three-digit hex number whose
-- upper digit is 1 if IO_CYCLE is asserted, and whose
-- lower two digits are the I/O address being presented
-- The lines below decode each valid I/O address ...
SWITCH_EN <= '1' WHEN IO_INT = 16#100# ELSE '0';
LED_EN <= '1' WHEN IO_INT = 16#101# ELSE '0';
TIMER_EN <= '1' WHEN IO_INT = 16#102# ELSE '0';
DIG_IN_EN <= '1' WHEN IO_INT = 16#103# ELSE '0';
HEX1_EN <= '1' WHEN IO_INT = 16#104# ELSE '0';
HEX2_EN <= '1' WHEN IO_INT = 16#105# ELSE '0';
LCD_EN <= '1' WHEN IO_INT = 16#106# ELSE '0';
LED2_EN <= '1' WHEN IO_INT = 16#107# ELSE '0';
BEEP_EN <= '1' WHEN IO_INT = 16#10A# ELSE '0';
CT_EN <= '1' WHEN IO_INT = 16#10C# ELSE '0';
L_POS_EN <= '1' WHEN IO_INT = 16#180# ELSE '0';
L_VEL_EN <= '1' WHEN IO_INT = 16#182# ELSE '0';
L_VELCTRL_EN <= '1' WHEN IO_INT = 16#183# ELSE '0';
R_POS_EN <= '1' WHEN IO_INT = 16#188# ELSE '0';
R_VEL_EN <= '1' WHEN IO_INT = 16#18A# ELSE '0';
R_VELCTRL_EN <= '1' WHEN IO_INT = 16#18B# ELSE '0';
I2C_CMD_EN <= '1' WHEN IO_INT = 16#190# ELSE '0';
I2C_DATA_EN <= '1' WHEN IO_INT = 16#191# ELSE '0';
I2C_RDY_EN <= '1' WHEN IO_INT = 16#192# ELSE '0';
UART_D_EN <= '1' WHEN IO_INT = 16#198# ELSE '0';
UART_S_EN <= '1' WHEN IO_INT = 16#199# ELSE '0';
SONAR_EN <= '1' WHEN ((IO_INT >= 16#1A0#) AND (IO_INT < 16#1B7#) ) ELSE '0';
XPOS_EN <= '1' WHEN IO_INT = 16#1C0# ELSE '0';
YPOS_EN <= '1' WHEN IO_INT = 16#1C1# ELSE '0';
TPOS_EN <= '1' WHEN IO_INT = 16#1C2# ELSE '0';
POS_RSTN <= '0' WHEN IO_INT = 16#1C3# ELSE '1';
RIN_EN <= '1' WHEN IO_INT = 16#1C8# ELSE '0';
LIN_EN <= '1' WHEN IO_INT = 16#1C9# ELSE '0';
END a;
| mit | 8769eefd0c886f89a94824b3ea5de81c | 0.522512 | 2.7008 | false | false | false | false |
tgingold/ghdl | testsuite/synth/output01/tb_output06.vhdl | 1 | 459 | library ieee;
use ieee.std_logic_1164.all;
entity tb_output06 is
end tb_output06;
architecture behav of tb_output06 is
signal i : std_logic;
signal o : std_logic_vector (3 downto 0);
begin
inst: entity work.output06
port map (i => i, o => o);
process
begin
i <= '0';
wait for 1 ns;
assert o = "0010" severity failure;
i <= '1';
wait for 1 ns;
assert o = "1001" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | e9bf90802117148a78595d88c4e642c8 | 0.625272 | 3.1875 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket61/bug.vhdl | 3 | 1,165 | entity ent is
end entity;
architecture a of ent is
begin
main : process is
constant c : boolean := false;
variable v : boolean;
type enum is (a, b, short, \Extended\, \Weird\\Name\);
variable e : enum;
begin
report to_string(c); -- Cause TYPES.INTERNAL_ERROR
report to_string(false); -- Cause TYPES.INTERNAL_ERROR
report to_string(integer'(1)); -- Cause TYPES.INTERNAL_ERROR
report to_string(v); -- Works
report to_string(\Extended\);
report to_string(\Weird\\Name\);
assert to_string(CR) = (1 => CR) severity failure;
assert to_string(integer'(1)) = "1" severity failure;
assert to_string(integer'(-12)) = "-12" severity failure;
assert to_string(FaLse) = "false" severity failure;
assert to_string (\Extended\) = "Extended" severity failure;
assert to_string(\Weird\\Name\) = "Weird\Name" severity failure;
assert enum'image(\Weird\\Name\) = "\Weird\\Name\" severity failure;
e := \Weird\\Name\;
assert enum'image(e) = "\Weird\\Name\" severity failure;
report to_string(e);
assert to_string(e) = "Weird\Name" severity failure;
wait;
end process;
end architecture;
| gpl-2.0 | 32248088613668ae346b41c8980468fd | 0.653219 | 3.629283 | false | false | false | false |
tgingold/ghdl | libraries/openieee/v93/numeric_std-body.vhdl | 1 | 86,312 | -- This -*- vhdl -*- file was generated from numeric_std-body.proto
-- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric std package body.
-- The implementation is based only on the specifications.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
package body NUMERIC_STD is
constant NO_WARNING : Boolean := False;
constant null_unsigned : unsigned (0 downto 1) := (others => '0');
constant null_signed : signed (0 downto 1) := (others => '0');
subtype nat1 is natural range 0 to 1;
type nat1_to_sl_type is array (nat1) of std_ulogic;
constant nat1_to_01 : nat1_to_sl_type := (0 => '0', 1 => '1');
subtype sl_01 is std_ulogic range '0' to '1';
subtype sl_x01 is std_ulogic range 'X' to '1';
type carry_array is array (sl_01, sl_01, sl_01) of sl_01;
constant compute_carry : carry_array :=
('0' => ('0' => ('0' => '0', '1' => '0'),
'1' => ('0' => '0', '1' => '1')),
'1' => ('0' => ('0' => '0', '1' => '1'),
'1' => ('0' => '1', '1' => '1')));
constant compute_sum : carry_array :=
('0' => ('0' => ('0' => '0', '1' => '1'),
'1' => ('0' => '1', '1' => '0')),
'1' => ('0' => ('0' => '1', '1' => '0'),
'1' => ('0' => '0', '1' => '1')));
type sl_to_x01_array is array (std_ulogic) of sl_x01;
constant sl_to_x01 : sl_to_x01_array :=
('0' | 'L' => '0', '1' | 'H' => '1', others => 'X');
type compare_type is (compare_unknown,
compare_lt,
compare_eq,
compare_gt);
-- Match.
-- '-' matches with everything.
-- '0'/'L' matches, '1'/'H' matches.
type match_table_type is array (std_ulogic, std_ulogic) of boolean;
constant match_table: match_table_type :=
('0' | 'L' => ('0' | 'L' | '-' => true, others => false),
'1' | 'H' => ('1' | 'H' | '-' => true, others => false),
'-' => (others => true),
others => ('-' => true, others => false));
function MAX (L, R : natural) return natural is
begin
if L > R then
return L;
else
return R;
end if;
end MAX;
function TO_INTEGER (ARG : UNSIGNED) return NATURAL
is
variable argn : UNSIGNED (ARG'Length -1 downto 0);
variable res : natural := 0;
begin
if argn'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null array detected, returning 0"
severity warning;
return 0;
end if;
argn := TO_01 (ARG, 'X');
if argn (0) = 'X' then
assert NO_WARNING
report
"NUMERIC_STD.TO_INTEGER: non logical value detected, returning 0"
severity warning;
return 0;
end if;
for i in argn'range loop
res := res + res;
if argn (i) = '1' then
res := res + 1;
end if;
end loop;
return res;
end TO_INTEGER;
function TO_INTEGER (ARG : SIGNED) return INTEGER
is
variable argn : SIGNED (ARG'Length -1 downto 0);
variable res : integer := 0;
variable b : STD_ULOGIC;
begin
if argn'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null array detected, returning 0"
severity warning;
return 0;
end if;
argn := TO_01 (ARG, 'X');
if argn (0) = 'X' then
assert NO_WARNING
report
"NUMERIC_STD.TO_INTEGER: non logical value detected, returning 0"
severity warning;
return 0;
end if;
if argn (argn'left) = '1' then
-- Negative value
b := '0';
else
b := '1';
end if;
for i in argn'range loop
res := res + res;
if argn (i) = b then
res := res + 1;
end if;
end loop;
if b = '0' then
-- Avoid overflow.
res := -res - 1;
end if;
return res;
end TO_INTEGER;
function TO_01 (S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED
is
subtype res_type is SIGNED (S'Length - 1 downto 0);
variable res : res_type;
alias snorm: res_type is S;
begin
if S'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null array detected"
severity warning;
return null_signed;
else
for i in res_type'range loop
case snorm (i) is
when '0' | 'L' => res (i) := '0';
when '1' | 'H' => res (i) := '1';
when others =>
assert NO_WARNING
report "NUMERIC_STD.TO_01: non logical value detected"
severity warning;
res := (others => XMAP);
exit;
end case;
end loop;
end if;
return res;
end TO_01;
function TO_01 (S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED
is
subtype res_type is UNSIGNED (S'Length - 1 downto 0);
variable res : res_type;
alias snorm: res_type is S;
begin
if S'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null array detected"
severity warning;
return null_unsigned;
else
for i in res_type'range loop
case snorm (i) is
when '0' | 'L' => res (i) := '0';
when '1' | 'H' => res (i) := '1';
when others =>
assert NO_WARNING
report "NUMERIC_STD.TO_01: non logical value detected"
severity warning;
res := (others => XMAP);
exit;
end case;
end loop;
end if;
return res;
end TO_01;
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED
is
variable res : UNSIGNED (SIZE - 1 downto 0);
variable a : natural := arg;
variable d : nat1;
begin
if size = 0 then
return null_unsigned;
end if;
for i in res'reverse_range loop
d := a rem 2;
res (i) := nat1_to_01 (d);
a := a / 2;
end loop;
if a /= 0 then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector is truncated"
severity warning;
end if;
return res;
end TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED
is
variable res : SIGNED (SIZE - 1 downto 0);
variable v : integer := arg;
variable b0, b1 : std_ulogic;
variable d : nat1;
begin
if size = 0 then
return null_signed;
end if;
if arg < 0 then
-- Use one complement to avoid overflow:
-- -v = (not v) + 1
-- not v = -v - 1
-- not v = -(v + 1)
v := -(arg + 1);
b0 := '1';
b1 := '0';
else
v := arg;
b0 := '0';
b1 := '1';
end if;
for i in res'reverse_range loop
d := v rem 2;
v := v / 2;
if d = 0 then
res (i) := b0;
else
res (i) := b1;
end if;
end loop;
if v /= 0 or res (res'left) /= b0 then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector is truncated"
severity warning;
end if;
return res;
end TO_SIGNED;
function std_match (l, r : std_ulogic) return boolean is
begin
return match_table (l, r);
end std_match;
function std_match (l, r : std_ulogic_vector) return boolean
is
alias la : std_ulogic_vector (l'length downto 1) is l;
alias ra : std_ulogic_vector (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function std_match (l, r : std_logic_vector) return boolean
is
alias la : std_logic_vector (l'length downto 1) is l;
alias ra : std_logic_vector (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function std_match (l, r : UNSIGNED) return boolean
is
alias la : UNSIGNED (l'length downto 1) is l;
alias ra : UNSIGNED (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function std_match (l, r : SIGNED) return boolean
is
alias la : SIGNED (l'length downto 1) is l;
alias ra : SIGNED (r'length downto 1) is r;
begin
if la'left = 0 or ra'left = 0 then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null argument, returning false"
severity warning;
return false;
elsif la'left /= ra'left then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: args length mismatch, returning false"
severity warning;
return false;
else
for i in la'range loop
if not match_table (la (i), ra (i)) then
return false;
end if;
end loop;
return true;
end if;
end std_match;
function "+" (l, r : UNSIGNED) return UNSIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is UNSIGNED (lft downto 0);
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_UNSIGNED;
end if;
carry := '0';
for i in 0 to lft loop
if i > la'left then
lb := '0';
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := '0';
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "+";
function "+" (l, r : SIGNED) return SIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is SIGNED (lft downto 0);
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_SIGNED;
end if;
carry := '0';
for i in 0 to lft loop
if i > la'left then
lb := l (l'left);
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := r (r'left);
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "+";
function "+" (l : UNSIGNED; r : NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '0';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : NATURAL; r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '0';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
ld := l1 - 2 * l2;
l1 := l2;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : SIGNED; r : INTEGER) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '0';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= -rmsb then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "+" (l : INTEGER; r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '0';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
if l1 < 0 then
ld := 2 * l2 - l1;
l1 := l2 - ld;
else
ld := l1 - 2 * l2;
l1 := l2;
end if;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""+"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= -lmsb then
assert NO_WARNING
report "NUMERIC_STD.""+"": vector is truncated"
severity warning;
end if;
return res;
end "+";
function "-" (l, r : UNSIGNED) return UNSIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is UNSIGNED (lft downto 0);
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_UNSIGNED;
end if;
carry := '1';
for i in 0 to lft loop
if i > la'left then
lb := '0';
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := '0';
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "-";
function "-" (l, r : SIGNED) return SIGNED
is
constant lft : integer := MAX (l'length, r'length) - 1;
subtype res_type is SIGNED (lft downto 0);
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if la'left < 0 or ra'left < 0 then
return null_SIGNED;
end if;
carry := '1';
for i in 0 to lft loop
if i > la'left then
lb := l (l'left);
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := r (r'left);
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
return res;
end "-";
function "-" (l : UNSIGNED; r : NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '1';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : NATURAL; r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_UNSIGNED;
end if;
carry := '1';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
ld := l1 - 2 * l2;
l1 := l2;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= 0 then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : SIGNED; r : INTEGER) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '1';
r1 := r;
for i in res'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
r1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if r1 /= -rmsb then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "-" (l : INTEGER; r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : res_type;
variable lb, rb, carry : sl_x01;
begin
if res'length < 0 then
return null_SIGNED;
end if;
carry := '1';
l1 := l;
for i in res'reverse_range loop
rb := sl_to_x01 (ra (i));
l2 := l1 / 2;
if l1 < 0 then
ld := 2 * l2 - l1;
l1 := l2 - ld;
else
ld := l1 - 2 * l2;
l1 := l2;
end if;
lb := nat1_to_01 (ld);
if rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
res := (others => 'X');
l1 := 0;
exit;
end if;
rb := not rb;
res (i) := compute_sum (carry, rb, lb);
carry := compute_carry (carry, rb, lb);
end loop;
if l1 /= -lmsb then
assert NO_WARNING
report "NUMERIC_STD.""-"": vector is truncated"
severity warning;
end if;
return res;
end "-";
function "*" (L, R : UNSIGNED) return UNSIGNED
is
alias la : UNSIGNED (L'Length - 1 downto 0) is l;
alias ra : UNSIGNED (R'Length - 1 downto 0) is r;
variable res : UNSIGNED (L'length + R'Length -1 downto 0) := (others => '0');
variable rb, lb, vb, carry : sl_x01;
begin
if la'length = 0 or ra'length = 0 then
return null_UNSIGNED;
end if;
-- Shift and add L.
for i in natural range 0 to ra'left loop
rb := sl_to_x01 (ra (i));
if rb = '1' then
-- Compute res := res + shift_left (l, i).
carry := '0';
for j in la'reverse_range loop
lb := la (j);
vb := res (i + j);
res (i + j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
-- Propagate carry.
for j in i + la'length to res'left loop
exit when carry = '0';
vb := res (j);
res (j) := carry xor vb;
carry := carry and vb;
end loop;
elsif rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""*"": non logical value detected"
severity warning;
end if;
end loop;
return res;
end "*";
function "*" (L, R : SIGNED) return SIGNED
is
alias la : SIGNED (L'Length - 1 downto 0) is l;
alias ra : SIGNED (R'Length - 1 downto 0) is r;
variable res : SIGNED (L'length + R'Length -1 downto 0) := (others => '0');
variable rb, lb, vb, carry : sl_x01;
begin
if la'length = 0 or ra'length = 0 then
return null_SIGNED;
end if;
-- Shift and add L.
for i in natural range 0 to ra'left - 1 loop
rb := sl_to_x01 (ra (i));
if rb = '1' then
-- Compute res := res + shift_left (l, i).
carry := '0';
for j in la'reverse_range loop
lb := la (j);
vb := res (i + j);
res (i + j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
-- Sign extend and propagate carry.
lb := la (la'left);
for j in i + l'length to res'left loop
vb := res (j);
res (j) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
elsif rb = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""*"": non logical value detected"
severity warning;
end if;
end loop;
if ra (ra'left) = '1' then
-- R is a negative number. It is considered as:
-- -2**n + (Rn-1 Rn-2 ... R0).
-- Compute res := res - 2**n * l.
carry := '1';
for i in la'reverse_range loop
vb := res (ra'length - 1 + i);
lb := not la (i);
res (ra'length - 1+ i) := compute_sum (carry, vb, lb);
carry := compute_carry (carry, vb, lb);
end loop;
vb := res (res'left);
lb := not la (la'left);
res (res'left) := compute_sum (carry, vb, lb);
end if;
return res;
end "*";
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant size : natural := l'length;
begin
if size = 0 then
return null_UNSIGNED;
end if;
return l * to_UNSIGNED (r, size);
end "*";
function "*" (L : SIGNED; R : INTEGER) return SIGNED
is
constant size : natural := l'length;
begin
if size = 0 then
return null_SIGNED;
end if;
return l * to_SIGNED (r, size);
end "*";
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant size : natural := r'length;
begin
if size = 0 then
return null_UNSIGNED;
end if;
return r * to_UNSIGNED (l, size);
end "*";
function "*" (L : INTEGER; R : SIGNED) return SIGNED
is
constant size : natural := r'length;
begin
if size = 0 then
return null_SIGNED;
end if;
return r * to_SIGNED (l, size);
end "*";
function has_0x (a : UNSIGNED) return sl_x01
is
variable res : sl_x01 := '0';
begin
for i in a'range loop
if a (i) = 'X' then
return 'X';
end if;
res := res or a (i);
end loop;
return res;
end has_0x;
-- All index range are normalized (N downto 0).
-- NUM and QUOT have the same range.
-- DEM and REMAIN have the same range.
-- No 'X'.
procedure divmod (num, dem : UNSIGNED; quot, remain : out UNSIGNED)
is
variable reg : unsigned (dem'left + 1 downto 0) := (others => '0');
variable sub : unsigned (dem'range) := (others => '0');
variable carry, d : sl_x01;
begin
for i in num'range loop
-- Shift
reg (reg'left downto 1) := reg (reg'left - 1 downto 0);
reg (0) := num (i);
-- Substract
carry := '1';
for j in dem'reverse_range loop
d := not dem (j);
sub (j) := compute_sum (carry, reg (j), d);
carry := compute_carry (carry, reg (j), d);
end loop;
carry := compute_carry (carry, reg (reg'left), '1');
-- Test
if carry = '0' then
-- Greater than
quot (i) := '0';
else
quot (i) := '1';
reg (reg'left) := '0';
reg (sub'range) := sub;
end if;
end loop;
remain := reg (dem'range);
end divmod;
function size_unsigned (n : natural) return natural
is
-- At least one bit (even for 0).
variable res : natural := 1;
variable n1 : natural := n;
begin
while n1 > 1 loop
res := res + 1;
n1 := n1 / 2;
end loop;
return res;
end size_unsigned;
function size_signed (n : integer) return natural
is
variable res : natural := 1;
variable n1 : natural;
begin
if n >= 0 then
n1 := n;
else
-- Use /N = -X -1 = -(X + 1) (No overflow).
n1 := -(n + 1);
end if;
while n1 /= 0 loop
res := res + 1;
n1 := n1 / 2;
end loop;
return res;
end size_signed;
function "/" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""/"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return quot;
end "/";
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return l / to_unsigned (r, r_size);
end "/";
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return resize (to_unsigned (l, l_size) / r, r'length);
end "/";
function "rem" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""rem"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return rema;
end "rem";
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return resize (l rem to_unsigned (r, r_size), l'length);
end "rem";
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return to_unsigned (l, l_size) rem r;
end "rem";
function "mod" (L, R : UNSIGNED) return UNSIGNED
is
subtype l_type is UNSIGNED (L'length - 1 downto 0);
subtype r_type is UNSIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
variable quot : l_type;
variable rema : r_type;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_unsigned;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""mod"": division by 0"
severity error;
divmod (la, ra, quot, rema);
return rema;
end "mod";
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED
is
constant r_size : natural := size_unsigned (r);
begin
if l'length = 0 then
return null_unsigned;
end if;
return resize (l mod to_unsigned (r, r_size), l'length);
end "mod";
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED
is
constant l_size : natural := size_unsigned (l);
begin
if r'length = 0 then
return null_unsigned;
end if;
return to_unsigned (l, l_size) mod r;
end "mod";
function has_0x (a : SIGNED) return sl_x01
is
variable res : sl_x01 := '0';
begin
for i in a'range loop
if a (i) = 'X' then
return 'X';
end if;
res := res or a (i);
end loop;
return res;
end has_0x;
function "-" (ARG : SIGNED) return SIGNED
is
subtype arg_type is SIGNED (ARG'length - 1 downto 0);
alias arga : arg_type is arg;
variable res : arg_type;
variable carry, a : sl_x01;
begin
if arga'length = 0 then
return null_signed;
end if;
if has_0x (arga) = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
return arg_type'(others => 'X');
end if;
carry := '1';
for i in arga'reverse_range loop
a := not arga (i);
res (i) := carry xor a;
carry := carry and a;
end loop;
return res;
end "-";
function "abs" (ARG : SIGNED) return SIGNED
is
subtype arg_type is SIGNED (ARG'length - 1 downto 0);
alias arga : arg_type is arg;
variable res : arg_type;
variable carry, a : sl_x01;
begin
if arga'length = 0 then
return null_signed;
end if;
if has_0x (arga) = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""-"": non logical value detected"
severity warning;
return arg_type'(others => 'X');
end if;
if arga (arga'left) = '0' then
return arga;
end if;
carry := '1';
for i in arga'reverse_range loop
a := not arga (i);
res (i) := carry xor a;
carry := carry and a;
end loop;
return res;
end "abs";
function "/" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""/"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""/"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
if (ra (ra'left) xor la (la'left)) = '1' then
return -signed (quot);
else
return signed (quot);
end if;
end "/";
function "/" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return l / to_signed (r, r_size);
end "/";
function "/" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return resize (to_signed (l, max (l_size, r'length)) / r, r'length);
end "/";
function "rem" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""rem"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""rem"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
-- Result of rem has the sign of the dividend.
if la (la'left) = '1' then
return -signed (rema);
else
return signed (rema);
end if;
end "rem";
function "rem" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return resize (l rem to_signed (r, r_size), l'length);
end "rem";
function "rem" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return to_signed (l, l_size) rem r;
end "rem";
function "mod" (L, R : SIGNED) return SIGNED
is
subtype l_type is SIGNED (L'length - 1 downto 0);
subtype r_type is SIGNED (R'length - 1 downto 0);
alias la : l_type is l;
alias ra : r_type is r;
subtype l_utype is UNSIGNED (l_type'range);
subtype r_utype is UNSIGNED (r_type'range);
variable lu : l_utype;
variable ru : r_utype;
variable quot : l_utype;
variable rema : r_utype;
variable r0 : sl_x01 := has_0x (r);
begin
if la'length = 0 or ra'length = 0 then
return null_signed;
end if;
if has_0x (l) = 'X' or r0 = 'X' then
assert NO_WARNING
report "NUMERIC_STD.""mod"": non logical value detected"
severity warning;
return l_type'(others => 'X');
end if;
assert r0 /= '0'
report "NUMERIC_STD.""mod"": division by 0"
severity error;
if la (la'left) = '1' then
lu := unsigned (-la);
else
lu := unsigned (la);
end if;
if ra (ra'left) = '1' then
ru := unsigned (-ra);
else
ru := unsigned (ra);
end if;
divmod (lu, ru, quot, rema);
-- Result of mod has the sign of the divisor.
if rema = r_utype'(others => '0') then
-- If the remainder is 0, then the modulus is 0.
return signed (rema);
else
if ra (ra'left) = '1' then
if la (la'left) = '1' then
return -signed (rema);
else
return ra + signed (rema);
end if;
else
if la (la'left) = '1' then
return ra - signed (rema);
else
return signed (rema);
end if;
end if;
end if;
end "mod";
function "mod" (L : SIGNED; R : INTEGER) return SIGNED
is
constant r_size : natural := size_signed (r);
begin
if l'length = 0 then
return null_signed;
end if;
return resize (l mod to_signed (r, r_size), l'length);
end "mod";
function "mod" (L : INTEGER; R : SIGNED) return SIGNED
is
constant l_size : natural := size_signed (l);
begin
if r'length = 0 then
return null_signed;
end if;
return to_signed (l, l_size) mod r;
end "mod";
function resize (ARG : UNSIGNED; NEW_SIZE: natural) return UNSIGNED
is
alias arg1 : UNSIGNED (ARG'length - 1 downto 0) is arg;
variable res : UNSIGNED (new_size - 1 downto 0) := (others => '0');
begin
if new_size = 0 then
return null_UNSIGNED;
end if;
if arg1'length = 0 then
return res;
end if;
if arg1'length > new_size then
-- Reduction.
res := arg1 (res'range);
else
-- Expansion
res (arg1'range) := arg1;
end if;
return res;
end resize;
function resize (ARG : SIGNED; NEW_SIZE: natural) return SIGNED
is
alias arg1 : SIGNED (ARG'length - 1 downto 0) is arg;
variable res : SIGNED (new_size - 1 downto 0) := (others => '0');
begin
if new_size = 0 then
return null_SIGNED;
end if;
if arg1'length = 0 then
return res;
end if;
if arg1'length > new_size then
-- Reduction.
res (res'left) := arg1 (arg1'left);
res (res'left - 1 downto 0) := arg1 (res'left - 1 downto 0);
else
-- Expansion
res (arg1'range) := arg1;
res (res'left downto arg1'length) := (others => arg1 (arg1'left));
end if;
return res;
end resize;
function "not" (l : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not la (I);
end loop;
return res;
end "not";
function "not" (l : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable res : res_type;
begin
for I in res_type'range loop
res (I) := not la (I);
end loop;
return res;
end "not";
function "and" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""and"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) and ra (I);
end loop;
end if;
return res;
end "and";
function "and" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""and"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) and ra (I);
end loop;
end if;
return res;
end "and";
function "nand" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nand"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nand ra (I);
end loop;
end if;
return res;
end "nand";
function "nand" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nand"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nand ra (I);
end loop;
end if;
return res;
end "nand";
function "or" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""or"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) or ra (I);
end loop;
end if;
return res;
end "or";
function "or" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""or"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) or ra (I);
end loop;
end if;
return res;
end "or";
function "nor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nor ra (I);
end loop;
end if;
return res;
end "nor";
function "nor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""nor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) nor ra (I);
end loop;
end if;
return res;
end "nor";
function "xor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) xor ra (I);
end loop;
end if;
return res;
end "xor";
function "xor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) xor ra (I);
end loop;
end if;
return res;
end "xor";
function "xnor" (l, r : UNSIGNED) return UNSIGNED
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xnor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) xnor ra (I);
end loop;
end if;
return res;
end "xnor";
function "xnor" (l, r : SIGNED) return SIGNED
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable res : res_type;
begin
if la'left /= ra'left then
assert false
report "NUMERIC_STD.""xnor"": arguments are not of the same length"
severity failure;
res := (others => 'X');
else
for I in res_type'range loop
res (I) := la (I) xnor ra (I);
end loop;
end if;
return res;
end "xnor";
function ucompare (l, r : UNSIGNED) return compare_type
is
constant sz : integer := MAX (l'length, r'length) - 1;
alias la : UNSIGNED (l'length - 1 downto 0) is l;
alias ra : UNSIGNED (r'length - 1 downto 0) is r;
variable lb, rb : sl_x01;
variable res : compare_type;
begin
res := compare_eq;
for i in 0 to sz loop
if i > la'left then
lb := '0';
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := '0';
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
return res;
end ucompare;
function scompare (l, r : SIGNED) return compare_type
is
constant sz : integer := MAX (l'length, r'length) - 1;
alias la : SIGNED (l'length - 1 downto 0) is l;
alias ra : SIGNED (r'length - 1 downto 0) is r;
variable lb, rb : sl_x01;
variable res : compare_type;
begin
-- Consider sign bit as S * -(2**N).
lb := sl_to_x01 (la (la'left));
rb := sl_to_x01 (ra (ra'left));
if lb = '1' and rb = '0' then
return compare_lt;
elsif lb = '0' and rb = '1' then
return compare_gt;
else
res := compare_eq;
end if;
for i in 0 to sz - 1 loop
if i > la'left then
lb := l (l'left);
else
lb := sl_to_x01 (la (i));
end if;
if i > ra'left then
rb := r (r'left);
else
rb := sl_to_x01 (ra (i));
end if;
if lb = 'X' or rb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
return res;
end scompare;
function ucompare (l : UNSIGNED; r : NATURAL) return compare_type
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable lb, rb : sl_x01;
variable res : compare_type;
begin
res := compare_eq;
r1 := r;
for i in la'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
rd := r1 - 2 * r2;
r1 := r2;
rb := nat1_to_01 (rd);
if lb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
if r1 /= 0 then
res := compare_lt;
end if;
return res;
end ucompare;
function scompare (l : SIGNED; r : INTEGER) return compare_type
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable lb, rb : sl_x01;
variable res : compare_type;
begin
res := compare_eq;
r1 := r;
for i in la'reverse_range loop
lb := sl_to_x01 (la (i));
r2 := r1 / 2;
if r1 < 0 then
rd := 2 * r2 - r1;
r1 := r2 - rd;
else
rd := r1 - 2 * r2;
r1 := r2;
end if;
rb := nat1_to_01 (rd);
if lb = 'X' then
return compare_unknown;
end if;
if lb = '1' and rb = '0' then
res := compare_gt;
elsif lb = '0' and rb = '1' then
res := compare_lt;
end if;
end loop;
if sl_to_x01 (l (l'left)) = '1' then
if r >= 0 then
res := compare_lt;
end if;
else
if r < 0 then
res := compare_gt;
end if;
end if;
return res;
end scompare;
function "=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq = res;
end "=";
function "=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return res = compare_eq;
end "=";
function "=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq = res;
end "=";
function "/=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq /= res;
end "/=";
function "/=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return res /= compare_eq;
end "/=";
function "/=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""/="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq /= res;
end "/=";
function ">" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq > res;
end ">";
function ">" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return res > compare_eq;
end ">";
function ">" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq > res;
end ">";
function ">=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq >= res;
end ">=";
function ">=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return res >= compare_eq;
end ">=";
function ">=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD."">="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq >= res;
end ">=";
function "<" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq < res;
end "<";
function "<" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return res < compare_eq;
end "<";
function "<" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<"": non logical value detected"
severity warning;
return false;
end if;
return compare_eq < res;
end "<";
function "<=" (l, r : UNSIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l, r : SIGNED) return boolean
is
variable res : compare_type;
begin
if l'length = 0 or r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l : UNSIGNED; r : NATURAL) return boolean
is
subtype res_type is UNSIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : NATURAL;
variable rd : nat1;
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l : NATURAL; r : UNSIGNED) return boolean
is
subtype res_type is UNSIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : NATURAL;
variable ld : nat1;
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := ucompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq <= res;
end "<=";
function "<=" (l : SIGNED; r : INTEGER) return boolean
is
subtype res_type is SIGNED (l'length - 1 downto 0);
alias la : res_type is l;
variable r1, r2 : INTEGER;
variable rd : nat1;
constant rmsb : nat1 := boolean'pos(r < 0);
variable res : compare_type;
begin
if l'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (l, r);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return res <= compare_eq;
end "<=";
function "<=" (l : INTEGER; r : SIGNED) return boolean
is
subtype res_type is SIGNED (r'length - 1 downto 0);
alias ra : res_type is r;
variable l1, l2 : INTEGER;
variable ld : nat1;
constant lmsb : nat1 := boolean'pos(l < 0);
variable res : compare_type;
begin
if r'length = 0 then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument, returning FALSE"
severity warning;
return false;
end if;
res := scompare (r, l);
if res = compare_unknown then
assert NO_WARNING
report "NUMERIC_STD.""<="": non logical value detected"
severity warning;
return false;
end if;
return compare_eq <= res;
end "<=";
function shift_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
end if;
return res;
end shift_left;
function shift_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
end if;
return res;
end shift_right;
function rotate_left (ARG : UNSIGNED; COUNT: natural) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count rem res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end rotate_left;
function rotate_right (ARG : UNSIGNED; COUNT: natural) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count rem res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end rotate_right;
function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count >= 0 and count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
elsif count < 0 and count >= -arg1'left then
res (res'left + count downto 0) := arg1 (arg1'left downto -count);
end if;
return res;
end "sll";
function "srl" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
if count >= 0 and count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
elsif count < 0 and count >= -arg1'left then
res (res'left downto -count) := arg1 (arg1'left + count downto 0);
end if;
return res;
end "srl";
function "rol" (ARG : UNSIGNED; COUNT: integer) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count mod res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end "rol";
function "ror" (ARG : UNSIGNED; COUNT: integer) return UNSIGNED
is
subtype res_type is UNSIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_UNSIGNED;
end if;
cnt := count mod res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end "ror";
function shift_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
end if;
return res;
end shift_left;
function shift_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => arg1 (arg1'left));
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
end if;
return res;
end shift_right;
function rotate_left (ARG : SIGNED; COUNT: natural) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count rem res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end rotate_left;
function rotate_right (ARG : SIGNED; COUNT: natural) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count rem res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end rotate_right;
function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count >= 0 and count <= arg1'left then
res (res'left downto count) := arg1 (arg1'left - count downto 0);
elsif count < 0 and count >= -arg1'left then
res (res'left + count downto 0) := arg1 (arg1'left downto -count);
end if;
return res;
end "sll";
function "srl" (ARG : SIGNED; COUNT: INTEGER) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
begin
if res'length = 0 then
return null_SIGNED;
end if;
if count >= 0 and count <= arg1'left then
res (res'left - count downto 0) := arg1 (arg1'left downto count);
elsif count < 0 and count >= -arg1'left then
res (res'left downto -count) := arg1 (arg1'left + count downto 0);
end if;
return res;
end "srl";
function "rol" (ARG : SIGNED; COUNT: integer) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count mod res'length;
res (res'left downto cnt) := arg1 (res'left - cnt downto 0);
res (cnt - 1 downto 0) := arg1 (res'left downto res'left - cnt + 1);
return res;
end "rol";
function "ror" (ARG : SIGNED; COUNT: integer) return SIGNED
is
subtype res_type is SIGNED (ARG'length - 1 downto 0);
alias arg1 : res_type is arg;
variable res : res_type := (others => '0');
variable cnt : natural;
begin
if res'length = 0 then
return null_SIGNED;
end if;
cnt := count mod res'length;
res (res'left - cnt downto 0) := arg1 (res'left downto cnt);
res (res'left downto res'left - cnt + 1) := arg1 (cnt - 1 downto 0);
return res;
end "ror";
end NUMERIC_STD;
| gpl-2.0 | dffd012a7c5c7ac4913a7e80b19372e6 | 0.547502 | 3.696762 | false | false | false | false |
tgingold/ghdl | testsuite/synth/subprg01/tb_subprg02.vhdl | 1 | 636 | entity tb_subprg02 is
end tb_subprg02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_subprg02 is
signal a, na : std_logic_vector (3 downto 0);
signal n : natural range 0 to 1;
signal clk : std_logic;
begin
dut: entity work.subprg02
port map (a, n, clk, na);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
n <= 0;
clk <= '0';
a <= x"0";
pulse;
assert na = x"f" severity failure;
a <= x"5";
pulse;
assert na = x"a" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 195afced700056dd2841e814820dccb9 | 0.580189 | 3.19598 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue241/rec.vhdl | 2 | 362 | entity rec is
end;
architecture behav of rec is
type rec_type is record
a, b : natural;
end record;
constant r1 : rec_type := (a | b => 2);
constant b : boolean := r1.a = r1.b;
begin
process
variable a : integer := 5;
begin
case a = 5 is
when b => null;
when false => null;
end case;
wait;
end process;
end behav;
| gpl-2.0 | 84c56e469a309b15c0648a587fe7a93b | 0.58011 | 3.261261 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-b.vhd | 4 | 4,355 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mac-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of mac is
constant Tpd_clk_out : time := 3 ns;
signal fp_x_real, fp_x_imag,
fp_y_real, fp_y_imag,
fp_s_real, fp_s_imag : real := 0.0;
begin
x_real_converter : entity work.to_fp(behavioral)
port map ( x_real, fp_x_real );
x_imag_converter : entity work.to_fp(behavioral)
port map ( x_imag, fp_x_imag );
y_real_converter : entity work.to_fp(behavioral)
port map ( y_real, fp_y_real );
y_imag_converter : entity work.to_fp(behavioral)
port map ( y_imag, fp_y_imag );
behavior : process (clk) is
variable input_x_real, input_x_imag, input_y_real, input_y_imag : real := 0.0;
variable real_part_product_1, real_part_product_2,
imag_part_product_1, imag_part_product_2 : real := 0.0;
variable real_product, imag_product : real := 0.0;
variable real_sum, imag_sum : real := 0.0;
variable real_accumulator_ovf, imag_accumulator_ovf : boolean := false;
type boolean_to_stdulogic_table is array (boolean) of std_ulogic;
constant boolean_to_stdulogic : boolean_to_stdulogic_table
:= (false => '0', true => '1');
begin
if rising_edge(clk) then
-- work from the end of the pipeline back to the start, so as
-- not to overwrite previous results in pipeline registers before
-- they are used
-- update accumulator and generate outputs
if To_X01(clr) = '1' then
real_sum := 0.0;
real_accumulator_ovf := false;
imag_sum := 0.0;
imag_accumulator_ovf := false;
else
real_sum := real_product + real_sum;
real_accumulator_ovf := real_accumulator_ovf
or real_sum < -16.0 or real_sum >= +16.0;
imag_sum := imag_product + imag_sum;
imag_accumulator_ovf := imag_accumulator_ovf
or imag_sum < -16.0 or imag_sum >= +16.0;
end if;
fp_s_real <= real_sum after Tpd_clk_out;
fp_s_imag <= imag_sum after Tpd_clk_out;
ovf <= boolean_to_stdulogic(
real_accumulator_ovf or imag_accumulator_ovf
or real_sum < -1.0 or real_sum >= +1.0
or imag_sum < -1.0 or imag_sum >= +1.0 )
after Tpd_clk_out;
-- update product registers using partial products
real_product := real_part_product_1 - real_part_product_2;
imag_product := imag_part_product_1 + imag_part_product_2;
-- update partial product registers using latched inputs
real_part_product_1 := input_x_real * input_y_real;
real_part_product_2 := input_x_imag * input_y_imag;
imag_part_product_1 := input_x_real * input_y_imag;
imag_part_product_2 := input_x_imag * input_y_real;
-- update input registers using MAC inputs
input_x_real := fp_x_real;
input_x_imag := fp_x_imag;
input_y_real := fp_y_real;
input_y_imag := fp_y_imag;
end if;
end process behavior;
s_real_converter : entity work.to_vector(behavioral)
port map ( fp_s_real, s_real );
s_imag_converter : entity work.to_vector(behavioral)
port map ( fp_s_imag, s_imag );
end architecture behavioral;
| gpl-2.0 | 195a81aad129e7260f8e585885a4bc58 | 0.585993 | 3.690678 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/PoC/src/common/config.vhdl | 1 | 47,835 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Global configuration settings.
--
-- Description:
-- -------------------------------------
-- This file evaluates the settings declared in the project specific package my_config.
-- See also template file my_config.vhdl.template.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany,
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
package config_private is
-- TODO:
-- ===========================================================================
subtype T_BOARD_STRING is string(1 to 16);
subtype T_BOARD_CONFIG_STRING is string(1 to 64);
subtype T_DEVICE_STRING is string(1 to 32);
-- Data structures to describe UART / RS232
type T_BOARD_UART_DESC is record
IsDTE : boolean; -- Data terminal Equipment (e.g. PC, Printer)
FlowControl : T_BOARD_CONFIG_STRING; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS)
BaudRate : T_BOARD_CONFIG_STRING; -- e.g. "115.2 kBd"
BaudRate_Max : T_BOARD_CONFIG_STRING;
end record;
-- Data structures to describe Ethernet
type T_BOARD_ETHERNET_DESC is record
IPStyle : T_BOARD_CONFIG_STRING;
RS_DataInterface : T_BOARD_CONFIG_STRING;
PHY_Device : T_BOARD_CONFIG_STRING;
PHY_DeviceAddress : std_logic_vector(7 downto 0);
PHY_DataInterface : T_BOARD_CONFIG_STRING;
PHY_ManagementInterface : T_BOARD_CONFIG_STRING;
end record;
subtype T_BOARD_ETHERNET_DESC_INDEX is natural range 0 to 7;
type T_BOARD_ETHERNET_DESC_VECTOR is array(natural range <>) of T_BOARD_ETHERNET_DESC;
-- Data structures to describe a board layout
type T_BOARD_INFO is record
BoardName : T_BOARD_CONFIG_STRING;
FPGADevice : T_BOARD_CONFIG_STRING;
UART : T_BOARD_UART_DESC;
Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX);
EthernetCount : T_BOARD_ETHERNET_DESC_INDEX;
end record;
type T_BOARD_INFO_VECTOR is array (natural range <>) of T_BOARD_INFO;
constant C_POC_NUL : character;
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING;
constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING;
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING;
constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR;
function conf(str : string) return T_BOARD_CONFIG_STRING;
end package;
package body config_private is
constant C_POC_NUL : character := '~';
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING := (others => C_POC_NUL);
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL);
function conf(str : string) return T_BOARD_CONFIG_STRING is
constant ConstNUL : string(1 to 1) := (others => C_POC_NUL);
variable Result : string(1 to T_BOARD_CONFIG_STRING'length);
begin
Result := (others => C_POC_NUL);
if (str'length > 0) then
Result(1 to bound(T_BOARD_CONFIG_STRING'length, 1, str'length)) := ite((str'length > 0), str(1 to imin(T_BOARD_CONFIG_STRING'length, str'length)), ConstNUL);
end if;
return Result;
end function;
constant C_BOARD_ETHERNET_DESC_EMPTY : T_BOARD_ETHERNET_DESC := (
IPStyle => C_BOARD_CONFIG_STRING_EMPTY,
RS_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
PHY_Device => C_BOARD_CONFIG_STRING_EMPTY,
PHY_DeviceAddress => x"00",
PHY_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
PHY_ManagementInterface => C_BOARD_CONFIG_STRING_EMPTY
);
-- predefined UART descriptions
function brd_CreateUART(IsDTE : boolean; FlowControl : string; BaudRate : string; BaudRate_Max : string := "") return T_BOARD_UART_DESC is
variable Result : T_BOARD_UART_DESC;
begin
Result.IsDTE := IsDTE;
Result.FlowControl := conf(FlowControl);
Result.BaudRate := conf(BaudRate);
Result.BaudRate_Max := ite((BaudRate_Max = ""), conf(BaudRate), conf(BaudRate_Max));
return Result;
end function;
-- IsDTE FlowControl BaudRate
constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "0 Bd");
constant C_BOARD_UART_DTE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_HWCTS : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "HW_CTS_RTS", "115.2 kBd");
constant C_BOARD_UART_DCE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd");
constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd");
function brd_CreateEthernet(IPStyle : string; RS_DataInt : string; PHY_Device : string; PHY_DevAddress : std_logic_vector(7 downto 0); PHY_DataInt : string; PHY_MgntInt : string) return T_BOARD_ETHERNET_DESC is
variable Result : T_BOARD_ETHERNET_DESC;
begin
Result.IPStyle := conf(IPStyle);
Result.RS_DataInterface := conf(RS_DataInt);
Result.PHY_Device := conf(PHY_Device);
Result.PHY_DeviceAddress := PHY_DevAddress;
Result.PHY_DataInterface := conf(PHY_DataInt);
Result.PHY_ManagementInterface := conf(PHY_MgntInt);
return Result;
end function;
constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("", "", "", x"00", "", "");
constant C_BOARD_ETH_SOFT_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_HARD_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("HARD", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_SOFT_SGMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "SGMII", "MDIO_OVER_IIC");
constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY);
-- Board Descriptions
-- ===========================================================================
constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := (
(
BoardName => conf("GENERIC"),
FPGADevice => conf("GENERIC"), -- GENERIC
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY
),
EthernetCount => 1
),
-- Altera boards
-- =========================================================================
(
BoardName => conf("DE0"),
FPGADevice => conf("EP3C16F484"), -- EP3C16F484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S2GXAV"),
FPGADevice => conf("EP2SGX90FF1508C3"), -- EP2SGX90FF1508C3
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("DE4"),
FPGADevice => conf("EP4SGX230KF40C2"), -- EP4SGX230KF40C2
UART => C_BOARD_UART_DCE_460800_NONE,
Ethernet => (
0 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"00", "RGMII", "MDIO"),
1 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"01", "RGMII", "MDIO"),
2 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"02", "RGMII", "MDIO"),
3 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"03", "RGMII", "MDIO"),
others => C_BOARD_ETH_EMPTY
),
EthernetCount => 4
),(
BoardName => conf("DE5"),
FPGADevice => conf("EP5SGXEA7N2F45C2"), -- EP5SGXEA7N2F45C2
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Lattice boards
-- =========================================================================
(
BoardName => conf("ECP5 Versa"),
FPGADevice => conf("LFE5UM-45F-6BG381C"), -- LFE5UM-45F-6BG381C
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Xilinx boards
-- =========================================================================
(
BoardName => conf("S3SK200"),
FPGADevice => conf("XC3S200-4FT256"), -- XC3S200-4FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S3SK1000"),
FPGADevice => conf("XC3S1000-4FT256"), -- XC2S1000-4FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S3ESK500"),
FPGADevice => conf("XC3S500E-4FG320"), -- XC3S500E-4FG320
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S3ESK1600"),
FPGADevice => conf("XC3S1600E-4FG320"), -- XC3S1600E-4FG320
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("ATLYS"),
FPGADevice => conf("XC6SLX45-3CSG324"), -- XC6SLX45-3CSG324
UART => C_BOARD_UART_DCE_460800_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ZC706"),
FPGADevice => conf("XC7Z045-2FFG900"), -- XC7Z045-2FFG900C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("ZedBoard"),
FPGADevice => conf("XC7Z020-1CLG484"), -- XC7Z020-1CLG484
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("AC701"),
FPGADevice => conf("XC7A200T-2FBG676C"), -- XC7A200T-2FBG676C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("KC705"),
FPGADevice => conf("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML505"),
FPGADevice => conf("XC5VLX50T-1FF1136"), -- XC5VLX50T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML506"),
FPGADevice => conf("XC5VSX50T-1FFG1136"), -- XC5VSX50T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML507"),
FPGADevice => conf("XC5VFX70T-1FFG1136"), -- XC5VFX70T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("XUPV5"),
FPGADevice => conf("XC5VLX110T-1FF1136"), -- XC5VLX110T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML605"),
FPGADevice => conf("XC6VLX240T-1FF1156"), -- XC6VLX240T-1FF1156
UART => C_BOARD_UART_EMPTY,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("VC707"),
FPGADevice => conf("XC7VX485T-2FFG1761C"), -- XC7VX485T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_SGMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("VC709"),
FPGADevice => conf("XC7VX690T-2FFG1761C"), -- XC7VX690T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Custom Board (MUST BE LAST ONE)
-- =========================================================================
(
BoardName => conf("Custom"),
FPGADevice => conf("Device is unknown for a custom board"),
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
)
);
end package body;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.my_config.all;
use PoC.my_project.all;
use PoC.config_private.all;
use PoC.utils.all;
package config is
constant PROJECT_DIR : string := MY_PROJECT_DIR;
constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM;
constant POC_VERBOSE : boolean := MY_VERBOSE;
-- List of known FPGA / Chip vendors
-- ---------------------------------------------------------------------------
type T_VENDOR is (
VENDOR_UNKNOWN,
VENDOR_GENERIC,
VENDOR_ALTERA,
VENDOR_LATTICE,
VENDOR_XILINX
);
-- List of known synthesis tool chains
-- ---------------------------------------------------------------------------
type T_SYNTHESIS_TOOL is (
SYNTHESIS_TOOL_UNKNOWN,
SYNTHESIS_TOOL_GENERIC,
SYNTHESIS_TOOL_ALTERA_QUARTUS2,
SYNTHESIS_TOOL_LATTICE_LSE,
SYNTHESIS_TOOL_SYNOPSIS,
SYNTHESIS_TOOL_XILINX_XST,
SYNTHESIS_TOOL_XILINX_VIVADO
);
-- List of known device families
-- ---------------------------------------------------------------------------
type T_DEVICE_FAMILY is (
DEVICE_FAMILY_UNKNOWN,
DEVICE_FAMILY_GENERIC,
-- Altera
DEVICE_FAMILY_ARRIA,
DEVICE_FAMILY_CYCLONE,
DEVICE_FAMILY_STRATIX,
-- Lattice
DEVICE_FAMILY_ICE,
DEVICE_FAMILY_MACHXO,
DEVICE_FAMILY_ECP,
-- Xilinx
DEVICE_FAMILY_SPARTAN,
DEVICE_FAMILY_ZYNQ,
DEVICE_FAMILY_ARTIX,
DEVICE_FAMILY_KINTEX,
DEVICE_FAMILY_VIRTEX
);
type T_DEVICE_SERIES is (
DEVICE_SERIES_UNKNOWN,
DEVICE_SERIES_GENERIC,
-- Xilinx FPGA series
DEVICE_SERIES_7_SERIES,
DEVICE_SERIES_ULTRASCALE,
DEVICE_SERIES_ULTRASCALE_PLUS
);
-- List of known devices
-- ---------------------------------------------------------------------------
type T_DEVICE is (
DEVICE_UNKNOWN,
DEVICE_GENERIC,
-- Altera
DEVICE_MAX2, DEVICE_MAX10, -- Altera.Max
DEVICE_ARRIA1, DEVICE_ARRIA2, DEVICE_ARRIA5, DEVICE_ARRIA10, -- Altera.Arria
DEVICE_CYCLONE1, DEVICE_CYCLONE2, DEVICE_CYCLONE3, DEVICE_CYCLONE4, -- Altera.Cyclone
DEVICE_CYCLONE5, --
DEVICE_STRATIX1, DEVICE_STRATIX2, DEVICE_STRATIX3, DEVICE_STRATIX4, -- Altera.Stratix
DEVICE_STRATIX5, DEVICE_STRATIX10, --
-- Lattice
DEVICE_ICE40, DEVICE_ICE65, DEVICE_ICE5, -- Lattice.iCE
DEVICE_MACHXO, DEVICE_MACHXO2, -- Lattice.MachXO
DEVICE_ECP3, DEVICE_ECP4, DEVICE_ECP5, -- Lattice.ECP
-- Xilinx
DEVICE_SPARTAN3, DEVICE_SPARTAN6, -- Xilinx.Spartan
DEVICE_ZYNQ7, DEVICE_ZYNQ_ULTRA_PLUS, -- Xilinx.Zynq
DEVICE_ARTIX7, -- Xilinx.Artix
DEVICE_KINTEX7, DEVICE_KINTEX_ULTRA, DEVICE_KINTEX_ULTRA_PLUS, -- Xilinx.Kintex
DEVICE_VIRTEX4, DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex
DEVICE_VIRTEX_ULTRA, DEVICE_VIRTEX_ULTRA_PLUS --
);
-- List of known device subtypes
-- ---------------------------------------------------------------------------
type T_DEVICE_SUBTYPE is (
DEVICE_SUBTYPE_NONE,
DEVICE_SUBTYPE_GENERIC,
-- Altera
DEVICE_SUBTYPE_E,
DEVICE_SUBTYPE_GS,
DEVICE_SUBTYPE_GX,
DEVICE_SUBTYPE_GT,
-- Lattice
DEVICE_SUBTYPE_U,
DEVICE_SUBTYPE_UM,
-- Xilinx
DEVICE_SUBTYPE_X,
DEVICE_SUBTYPE_T,
DEVICE_SUBTYPE_XT,
DEVICE_SUBTYPE_HT,
DEVICE_SUBTYPE_LX,
DEVICE_SUBTYPE_SXT,
DEVICE_SUBTYPE_LXT,
DEVICE_SUBTYPE_TXT,
DEVICE_SUBTYPE_FXT,
DEVICE_SUBTYPE_CXT,
DEVICE_SUBTYPE_HXT
);
-- List of known transceiver (sub-)types
-- ---------------------------------------------------------------------------
type T_TRANSCEIVER is (
TRANSCEIVER_NONE,
TRANSCEIVER_GENERIC,
-- TODO: add more? Altera transceivers
-- Altera transceivers
TRANSCEIVER_GXB, -- Altera GXB transceiver
--Lattice transceivers
TRANSCEIVER_MGT, -- Lattice transceiver
-- Xilinx transceivers
TRANSCEIVER_GTP_DUAL, TRANSCEIVER_GTPE1, TRANSCEIVER_GTPE2, -- Xilinx GTP transceivers
TRANSCEIVER_GTX, TRANSCEIVER_GTXE1, TRANSCEIVER_GTXE2, -- Xilinx GTX transceivers
TRANSCEIVER_GTH, TRANSCEIVER_GTHE1, TRANSCEIVER_GTHE2, -- Xilinx GTH transceivers
TRANSCEIVER_GTZ, -- Xilinx GTZ transceivers
TRANSCEIVER_GTY -- Xilinx GTY transceivers
);
-- Properties of an FPGA architecture
-- ===========================================================================
type T_DEVICE_INFO is record
Vendor : T_VENDOR;
Device : T_DEVICE;
DevFamily : T_DEVICE_FAMILY;
DevGeneration : natural;
DevNumber : natural;
DevSubType : T_DEVICE_SUBTYPE;
DevSeries : T_DEVICE_SERIES;
TransceiverType : T_TRANSCEIVER;
LUT_FanIn : positive;
end record;
-- Functions extracting board and PCB properties from "MY_BOARD"
-- which is declared in package "my_config".
-- ===========================================================================
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural;
function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO;
function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string;
function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string;
function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string;
-- Functions extracting device and architecture properties from "MY_DEVICE"
-- which is declared in package "my_config".
-- ===========================================================================
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL;
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE;
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE;
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES;
function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive;
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO;
-- Convert T_DEVICE to string representation as required by "altera_mf" library
-- ===========================================================================
function getAlteraDeviceName (device : T_DEVICE) return string;
-- force FSM to predefined encoding in debug mode
-- ===========================================================================
function getFSMEncoding_gray(debug : boolean) return string;
end package;
package body config is
-- inlined function from PoC.utils, to break dependency
-- ===========================================================================
function ite(cond : boolean; value1 : string; value2 : string) return string is begin
if cond then return value1; else return value2; end if;
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return ((character'pos('0') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('9')));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return (((character'pos('a') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('z'))) or
((character'pos('A') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('Z'))));
end function;
function str_length(str : string) return natural is
begin
for i in str'range loop
if str(i) = C_POC_NUL then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_trim(str : string) return string is
begin
for i in str'range loop
if str(i) = C_POC_NUL then
return str(str'low to i-1);
end if;
end loop;
return str;
end function;
function str_imatch(str1 : string; str2 : string) return boolean is
constant len : natural := imin(str1'length, str2'length);
variable chr1 : character;
variable chr2 : character;
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in 0 to len-1 loop
chr1 := str1(str1'low + i);
chr2 := str2(str2'low + i);
if (character'pos('A') <= CHARACTER'pos(chr1)) and (character'pos(chr1) <= CHARACTER'pos('Z')) then
chr1 := character'val(CHARACTER'pos(chr1) - character'pos('A') + CHARACTER'pos('a'));
end if;
if (character'pos('A') <= CHARACTER'pos(chr2)) and (character'pos(chr2) <= CHARACTER'pos('Z')) then
chr2 := character'val(CHARACTER'pos(chr2) - character'pos('A') + CHARACTER'pos('a'));
end if;
if chr1 /= chr2 then
return FALSE;
elsif (chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL) then
return FALSE;
elsif (chr1 = C_POC_NUL) and (chr2 = C_POC_NUL) then
return TRUE;
end if;
end loop;
-- check special cases,
if ((str1'length = len) and (str2'length = len)) then -- both strings are fully consumed and equal
return TRUE;
elsif (str1'length > len) then
return (str1(str1'low + len) = C_POC_NUL); -- str1 is longer, but str_length equals len
else
return (str2(str2'low + len) = C_POC_NUL); -- str2 is longer, but str_length equals len
end if;
end function;
function str_find(str : string; pattern : string; start : natural := 0) return boolean is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return TRUE;
end if;
end loop;
return FALSE;
end function;
-- private functions required by board description
-- ModelSim requires that this functions is defined before it is used below.
-- ===========================================================================
function getLocalDeviceString(DeviceString : string) return string is
constant ConstNUL : string(1 to 1) := (others => C_POC_NUL);
constant MY_DEVICE_STR : string := BOARD_DEVICE;
variable Result : string(1 to T_DEVICE_STRING'length);
begin
Result := (others => C_POC_NUL);
-- report DeviceString for debugging
if POC_VERBOSE then
report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE;
end if;
-- if DeviceString is populated
if (str_length(DeviceString) /= 0) and not str_imatch(DeviceString, "None") then
Result(1 to bound(T_DEVICE_STRING'length, 1, DeviceString'length)) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL);
-- if MY_DEVICE is set, prefer it
elsif (str_length(MY_DEVICE) /= 0) and not str_imatch(MY_DEVICE, "None") then
Result(1 to bound(T_DEVICE_STRING'length, 1, MY_DEVICE'length)) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL);
-- otherwise use MY_BOARD
else
Result(1 to bound(T_DEVICE_STRING'length, 1, MY_DEVICE_STR'length)) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL);
end if;
return Result;
end function;
function extractFirstNumber(str : string) return natural is
variable low : integer;
variable high : integer;
variable Result : natural;
variable Digit : integer;
begin
low := -1;
high := -1;
for i in str'low to str'high loop
if chr_isDigit(str(i)) then
low := i;
exit;
end if;
end loop;
-- abort if no digit can be found
if low = -1 then return 0; end if;
for i in (low + 1) to str'high loop
if chr_isAlpha(str(i)) then
high := i - 1;
exit;
end if;
end loop;
if high = -1 then return 0; end if;
-- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1
-- convert substring to a number
for i in low to high loop
if not chr_isDigit(str(i)) then
return 0;
end if;
Result := (Result * 10) + (character'pos(str(i)) - character'pos('0'));
end loop;
return Result;
end function;
-- Public functions
-- ===========================================================================
-- TODO: comment
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural is
constant MY_BRD : T_BOARD_CONFIG_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig), conf(MY_BOARD));
constant BOARD_NAME : string := str_trim(MY_BRD);
begin
if POC_VERBOSE then report "PoC configuration: Used board is '" & BOARD_NAME & "'" severity NOTE; end if;
for i in C_BOARD_INFO_LIST'range loop
if str_imatch(BOARD_NAME, C_BOARD_INFO_LIST(i).BoardName) then
return i;
end if;
end loop;
report "Unknown board name in MY_BOARD = " & MY_BRD & "." severity failure;
return C_BOARD_INFO_LIST'high;
end function;
function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is
constant BRD : natural := BOARD(BoardConfig);
begin
return C_BOARD_INFO_LIST(BRD);
end function;
-- TODO: comment
function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is
constant BRD : natural := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).BoardName);
end function;
-- TODO: comment
function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is
constant BRD : natural := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice);
end function;
function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is
constant BRD : natural := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate);
end function;
-- purpose: extract vendor from MY_DEVICE
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN_STR2 : string(1 to 2) := MY_DEV(1 to 2); -- TODO: test if alias declarations also work out on all platforms
constant VEN_STR3 : string(1 to 3) := MY_DEV(1 to 3); -- TODO: test if alias declarations also work out on all platforms
begin
case VEN_STR2 is
when "GE" => return VENDOR_GENERIC;
when "EP" => return VENDOR_ALTERA;
when "XC" => return VENDOR_XILINX;
when others => null;
end case;
case VEN_STR3 is
when "iCE" => return VENDOR_LATTICE; -- iCE devices
when "LCM" => return VENDOR_LATTICE; -- MachXO device
when "LFE" => return VENDOR_LATTICE; -- ECP devices
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
return VENDOR_UNKNOWN;
end case;
end function;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL is
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_GENERIC =>
return SYNTHESIS_TOOL_GENERIC;
when VENDOR_ALTERA =>
return SYNTHESIS_TOOL_ALTERA_QUARTUS2;
when VENDOR_LATTICE =>
return SYNTHESIS_TOOL_LATTICE_LSE;
--return SYNTHESIS_TOOL_SYNOPSIS;
when VENDOR_XILINX =>
if (1 fs /= 1 us) then
return SYNTHESIS_TOOL_XILINX_XST;
else
return SYNTHESIS_TOOL_XILINX_VIVADO;
end if;
when others =>
return SYNTHESIS_TOOL_UNKNOWN;
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant DEV_STR : string(3 to 4) := MY_DEV(3 to 4); -- TODO: test if alias declarations also work out on all platforms
begin
case VEN is
when VENDOR_GENERIC =>
if (MY_DEV(1 to 7) = "GENERIC") then return DEVICE_GENERIC;
else report "Unknown Generic device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when VENDOR_ALTERA =>
case DEV_STR is
when "1C" => return DEVICE_CYCLONE1;
when "2C" => return DEVICE_CYCLONE2;
when "3C" => return DEVICE_CYCLONE3;
when "1S" => return DEVICE_STRATIX1;
when "2S" => return DEVICE_STRATIX2;
when "4S" => return DEVICE_STRATIX4;
when "5S" => return DEVICE_STRATIX5;
when others => report "Unknown Altera device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_LATTICE =>
if (MY_DEV(1 to 6) = "LCMX02") then return DEVICE_MACHXO2;
elsif (MY_DEV(1 to 5) = "LCMX0") then return DEVICE_MACHXO;
elsif (MY_DEV(1 to 5) = "iCE40") then return DEVICE_ICE40;
elsif (MY_DEV(1 to 5) = "iCE65") then return DEVICE_ICE65;
elsif (MY_DEV(1 to 4) = "iCE5") then return DEVICE_ICE5;
elsif (MY_DEV(1 to 4) = "LFE3") then return DEVICE_ECP3;
elsif (MY_DEV(1 to 4) = "LFE4") then return DEVICE_ECP4;
elsif (MY_DEV(1 to 4) = "LFE5") then return DEVICE_ECP5;
else report "Unknown Lattice device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when VENDOR_XILINX =>
case DEV_STR is
when "7A" => return DEVICE_ARTIX7;
when "7K" => return DEVICE_KINTEX7;
when "KU" => return DEVICE_KINTEX_ULTRA;
when "3S" => return DEVICE_SPARTAN3;
when "6S" => return DEVICE_SPARTAN6;
when "4V" => return DEVICE_VIRTEX4;
when "5V" => return DEVICE_VIRTEX5;
when "6V" => return DEVICE_VIRTEX6;
when "7V" => return DEVICE_VIRTEX7;
when "VU" => return DEVICE_VIRTEX_ULTRA;
when "7Z" => return DEVICE_ZYNQ7;
when others => report "Unknown Xilinx device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure;
end case;
return DEVICE_UNKNOWN;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant FAM_CHAR : character := MY_DEV(4);
begin
case VEN is
when VENDOR_GENERIC =>
return DEVICE_FAMILY_GENERIC;
when VENDOR_ALTERA =>
case FAM_CHAR is
when 'C' => return DEVICE_FAMILY_CYCLONE;
when 'S' => return DEVICE_FAMILY_STRATIX;
when others => report "Unknown Altera device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_LATTICE =>
case FAM_CHAR is
--when 'M' => return DEVICE_FAMILY_MACHXO;
when 'E' => return DEVICE_FAMILY_ECP;
when others => report "Unknown Lattice device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_XILINX =>
case FAM_CHAR is
when 'A' => return DEVICE_FAMILY_ARTIX;
when 'K' => return DEVICE_FAMILY_KINTEX;
when 'S' => return DEVICE_FAMILY_SPARTAN;
when 'V' => return DEVICE_FAMILY_VIRTEX;
when 'Z' => return DEVICE_FAMILY_ZYNQ;
when others => report "Unknown Xilinx device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
return DEVICE_FAMILY_UNKNOWN;
end function;
-- some devices share some common features: e.g. XADC, BlockRAM, ...
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
begin
case DEV is
when DEVICE_GENERIC =>
return DEVICE_SERIES_GENERIC;
-- all Xilinx ****7 devices
when DEVICE_ARTIX7 | DEVICE_KINTEX7 | DEVICE_VIRTEX7 | DEVICE_ZYNQ7 =>
return DEVICE_SERIES_7_SERIES;
-- all Xilinx ****UltraScale devices
when DEVICE_KINTEX_ULTRA | DEVICE_VIRTEX_ULTRA =>
return DEVICE_SERIES_ULTRASCALE;
-- all Xilinx ****UltraScale+ devices
when DEVICE_KINTEX_ULTRA_PLUS | DEVICE_VIRTEX_ULTRA_PLUS | DEVICE_ZYNQ_ULTRA_PLUS =>
return DEVICE_SERIES_ULTRASCALE_PLUS;
when others =>
return DEVICE_SERIES_UNKNOWN;
end case;
end function;
function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString);
begin
if SERIES = DEVICE_SERIES_7_SERIES then
return 7;
else
return 0;
end if;
end function;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_GENERIC => return 0;
when VENDOR_ALTERA => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when VENDOR_LATTICE => return extractFirstNumber(MY_DEV(6 to MY_DEV'high));
when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
return 0;
end case;
end function;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(MY_DEV);
constant DEV_SUB_STR : string(1 to 2) := MY_DEV(5 to 6); -- WORKAROUND: for GHDL
begin
case DEV is
when DEVICE_GENERIC => return DEVICE_SUBTYPE_GENERIC;
-- TODO: extract Arria GX subtype
when DEVICE_ARRIA1 =>
report "TODO: parse Arria device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- TODO: extract ArriaII GX,GZ subtype
when DEVICE_ARRIA2 =>
report "TODO: parse ArriaII device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- TODO: extract ArriaV GX, GT, SX, GZ subtype
when DEVICE_ARRIA5 =>
report "TODO: parse ArriaV device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- TODO: extract Arria10 GX, GT, SX subtype
when DEVICE_ARRIA10 =>
report "TODO: parse Arria10 device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- Altera Cyclon I, II, III, IV, V devices have no subtype
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 | DEVICE_CYCLONE4 |
DEVICE_CYCLONE5 => return DEVICE_SUBTYPE_NONE;
when DEVICE_STRATIX2 =>
if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE;
elsif DEV_SUB_STR = "GX" then return DEVICE_SUBTYPE_GX;
else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_STRATIX4 =>
if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E;
elsif DEV_SUB_STR = "GX" then return DEVICE_SUBTYPE_GX;
-- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT;
else report "Unknown Stratix IV subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
-- TODO: extract StratixV subtype
when DEVICE_STRATIX5 =>
report "TODO: parse Stratix V device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
when DEVICE_ECP5 =>
if (DEV_SUB_STR(1) = 'U') then return DEVICE_SUBTYPE_U;
elsif DEV_SUB_STR = "UM" then return DEVICE_SUBTYPE_UM;
else report "Unknown Lattice ECP5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_SPARTAN3 =>
report "TODO: parse Spartan3 / Spartan3E / Spartan3AN device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
when DEVICE_SPARTAN6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX4 =>
report "Unkown Virtex 4" severity failure;
when DEVICE_VIRTEX5 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT;
elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT;
elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT;
else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_ARTIX7 =>
if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_KINTEX7 =>
if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_KINTEX_ULTRA => return DEVICE_SUBTYPE_NONE;
when DEVICE_KINTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
when DEVICE_VIRTEX7 =>
if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT;
elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT;
else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX_ULTRA => return DEVICE_SUBTYPE_NONE;
when DEVICE_VIRTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
when DEVICE_ZYNQ7 => return DEVICE_SUBTYPE_NONE;
when DEVICE_ZYNQ_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
when others => report "Device sub-type is unknown for the given device." severity failure;
end case;
return DEVICE_SUBTYPE_NONE;
end function;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString);
begin
case SERIES is
when DEVICE_SERIES_GENERIC => return 6;
when DEVICE_SERIES_7_SERIES | DEVICE_SERIES_ULTRASCALE |
DEVICE_SERIES_ULTRASCALE_PLUS => return 6;
when others => null;
end case;
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return 4;
when DEVICE_STRATIX1 | DEVICE_STRATIX2 => return 4;
when DEVICE_STRATIX4 | DEVICE_STRATIX5 => return 6;
when DEVICE_ECP5 => return 4;
when DEVICE_SPARTAN3 => return 4;
when DEVICE_SPARTAN6 => return 6;
when DEVICE_VIRTEX4 | DEVICE_VIRTEX5 | DEVICE_VIRTEX6 => return 6;
when others => report "LUT fan-in is unknown for the given device, using default (4)." severity failure;
return 4;
end case;
end function;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
constant DEV_NUM : natural := DEVICE_NUMBER(DeviceString);
constant DEV_SUB : T_DEVICE_SUBTYPE := DEVICE_SUBTYPE(DeviceString);
begin
case DEV is
when DEVICE_GENERIC => return TRANSCEIVER_GENERIC;
when DEVICE_MAX2 | DEVICE_MAX10 => return TRANSCEIVER_NONE; -- Altera MAX II, 10 devices have no transceivers
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return TRANSCEIVER_NONE; -- Altera Cyclon I, II, III devices have no transceivers
when DEVICE_STRATIX2 => return TRANSCEIVER_GXB;
when DEVICE_STRATIX4 => return TRANSCEIVER_GXB;
--when DEVICE_STRATIX5 => return TRANSCEIVER_GXB;
when DEVICE_ECP5 => return TRANSCEIVER_MGT;
when DEVICE_SPARTAN3 => return TRANSCEIVER_NONE; -- Xilinx Spartan3 devices have no transceivers
when DEVICE_SPARTAN6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTPE1;
when others => report "Unknown Spartan-6 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX4 =>
report "Unknown Virtex-4" severity failure;
when DEVICE_VIRTEX5 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_TXT => return TRANSCEIVER_GTX;
when DEVICE_SUBTYPE_FXT => return TRANSCEIVER_GTX;
when others => report "Unknown Virtex-5 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_HXT => return TRANSCEIVER_GTXE1;
when others => report "Unknown Virtex-6 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure;
end case;
when DEVICE_ARTIX7 => return TRANSCEIVER_GTPE2;
when DEVICE_KINTEX7 => return TRANSCEIVER_GTXE2;
when DEVICE_VIRTEX7 =>
case DEV_SUB is
when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2;
when DEVICE_SUBTYPE_XT =>
if DEV_NUM = 485 then return TRANSCEIVER_GTXE2;
else return TRANSCEIVER_GTHE2;
end if;
when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2;
when others => report "Unknown Virtex-7 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure;
end case;
when DEVICE_ZYNQ7 =>
case DEV_NUM is
when 10 | 20 => return TRANSCEIVER_NONE;
when 15 => return TRANSCEIVER_GTPE2;
when others => return TRANSCEIVER_GTXE2;
end case;
when others => report "Unknown device." severity failure;
end case;
return TRANSCEIVER_NONE;
end function;
-- purpose: extract architecture properties from DEVICE
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO is
variable Result : T_DEVICE_INFO;
begin
Result.Vendor := VENDOR(DeviceString);
Result.Device := DEVICE(DeviceString);
Result.DevFamily := DEVICE_FAMILY(DeviceString);
Result.DevSubType := DEVICE_SUBTYPE(DeviceString);
Result.DevSeries := DEVICE_SERIES(DeviceString);
Result.DevGeneration := DEVICE_GENERATION(DeviceString);
Result.DevNumber := DEVICE_NUMBER(DeviceString);
Result.TransceiverType := TRANSCEIVER_TYPE(DeviceString);
Result.LUT_FanIn := LUT_FANIN(DeviceString);
return Result;
end function;
-- Convert T_DEVICE to string representation as required by "altera_mf" library
function getAlteraDeviceName (device : T_DEVICE) return string is
begin
case device is
when DEVICE_ARRIA1 => return "Arria";
when DEVICE_ARRIA2 => return "Arria II";
when DEVICE_ARRIA5 => return "Arria V";
when DEVICE_ARRIA10 => return "Arria 10";
when DEVICE_CYCLONE1 => return "Cyclone";
when DEVICE_CYCLONE2 => return "Cyclone II";
when DEVICE_CYCLONE3 => return "Cyclone III";
when DEVICE_CYCLONE4 => return "Cyclone IV";
when DEVICE_CYCLONE5 => return "Cyclone V";
when DEVICE_STRATIX1 => return "Stratix";
when DEVICE_STRATIX2 => return "Stratix II";
when DEVICE_STRATIX3 => return "Stratix III";
when DEVICE_STRATIX4 => return "Stratix IV";
when DEVICE_STRATIX5 => return "Stratix V";
when DEVICE_STRATIX10 => return "Stratix 10";
when others =>
report "Unknown Altera device." severity failure;
return "";
end case;
end function;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : boolean) return string is
begin
if debug then
return "gray";
else
case VENDOR is
when VENDOR_ALTERA => return "default";
--when VENDOR_LATTICE => return "default";
when VENDOR_XILINX => return "auto";
when others => report "Unknown vendor." severity failure;
return "";
end case;
end if;
end function;
end package body;
| gpl-2.0 | 68af7a4d1e85c6ae146e453200c3eb42 | 0.628347 | 3.262738 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/sim/vhdl/AESL_autobram_histo.vhd | 1 | 19,484 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity AESL_autobram_histo is
generic (
constant TV_IN : STRING (1 to 43) := "../tv/cdatafile/c.doHist.autotvin_histo.dat";
constant TV_OUT : STRING (1 to 48) := "../tv/rtldatafile/rtl.doHist.autotvout_histo.dat";
constant DATA_WIDTH : INTEGER := 32;
constant ADDR_WIDTH : integer := 32;
constant DEPTH : integer := 256
);
port (
Clk_A : IN STD_LOGIC;
Rst_A : IN STD_LOGIC;
EN_A : IN STD_LOGIC;
WEN_A : IN STD_LOGIC_VECTOR (DATA_WIDTH/8 - 1 downto 0);
Addr_A : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
Din_A : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
Dout_A : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
Clk_B : IN STD_LOGIC;
Rst_B : IN STD_LOGIC;
EN_B : IN STD_LOGIC;
WEN_B : IN STD_LOGIC_VECTOR (DATA_WIDTH/8 - 1 downto 0);
Addr_B : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
Din_B : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
Dout_B : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobram_histo;
architecture behav of AESL_autobram_histo is
-- Inner signals
type arr2D is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem : arr2D := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
begin
---------------------------Read array-------------------
-- Read data from file to array
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable token_len : INTEGER;
variable token_int : INTEGER;
variable transaction_idx : INTEGER;
variable idx : INTEGER;
begin
wait until Rst_A = '0';
transaction_idx := 0;
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait for 0.2 ns;
while(ready /= '1') loop
wait until Clk_A'event and Clk_A = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
wait until Clk_A'event and Clk_A = '1';
end loop;
file_close(fp);
wait;
end process;
-- Read data from array to RTL
read_proc_A : process(Clk_A, Rst_A)
begin
if(Rst_A = '1') then
Dout_A <= (others => '0');
elsif (Clk_A'event and Clk_A = '1') then
if(EN_A = '1' and (CONV_INTEGER(Addr_A)*8/32 < DEPTH)) then
Dout_A <= mem(CONV_INTEGER(Addr_A)*8/32);
end if;
end if;
end process;
read_proc_B : process(Clk_B, Rst_B)
begin
if(Rst_B = '1') then
Dout_B <= (others => '0');
elsif (Clk_B'event and Clk_B = '1') then
if(EN_B = '1' and (CONV_INTEGER(Addr_B)*8/32 < DEPTH)) then
Dout_B <= mem(CONV_INTEGER(Addr_B)*8/32);
end if;
end if;
end process;
----------------------Write array------------------------
--Write data from RTL to array
write_proc_A : process(Clk_A)
begin
if(EN_A = '1') then
if(WEN_A(0) = '1') then
mem(CONV_INTEGER(Addr_A)*8/DATA_WIDTH)(0*8+7 downto 0*8) := Din_A(0*8+7 downto 0*8);
end if;
if(WEN_A(1) = '1') then
mem(CONV_INTEGER(Addr_A)*8/DATA_WIDTH)(1*8+7 downto 1*8) := Din_A(1*8+7 downto 1*8);
end if;
if(WEN_A(2) = '1') then
mem(CONV_INTEGER(Addr_A)*8/DATA_WIDTH)(2*8+7 downto 2*8) := Din_A(2*8+7 downto 2*8);
end if;
if(WEN_A(3) = '1') then
mem(CONV_INTEGER(Addr_A)*8/DATA_WIDTH)(3*8+7 downto 3*8) := Din_A(3*8+7 downto 3*8);
end if;
end if;
end process;
write_proc_B : process(Clk_B)
begin
if(EN_B = '1') then
if(WEN_B(0) = '1') then
mem(CONV_INTEGER(Addr_B)*8/DATA_WIDTH)(0*8+7 downto 0*8) := Din_B(0*8+7 downto 0*8);
end if;
if(WEN_B(1) = '1') then
mem(CONV_INTEGER(Addr_B)*8/DATA_WIDTH)(1*8+7 downto 1*8) := Din_B(1*8+7 downto 1*8);
end if;
if(WEN_B(2) = '1') then
mem(CONV_INTEGER(Addr_B)*8/DATA_WIDTH)(2*8+7 downto 2*8) := Din_B(2*8+7 downto 2*8);
end if;
if(WEN_B(3) = '1') then
mem(CONV_INTEGER(Addr_B)*8/DATA_WIDTH)(3*8+7 downto 3*8) := Din_B(3*8+7 downto 3*8);
end if;
end if;
end process;
-- Write data from array to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable transaction_idx : INTEGER;
begin
wait until (Rst_A = '0');
transaction_idx := 0;
while(true) loop
wait for 0.1 ns;
while(done /= '1') loop
wait until Clk_A'event and Clk_A = '1';
wait for 0.1 ns;
end loop;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
wait until Clk_A'event and Clk_A = '1';
end loop;
wait;
end process;
end behav;
| gpl-3.0 | 9ab6791ac12a59d2fc3af0eb8ebad018 | 0.40813 | 3.795092 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug06/repro.vhdl | 3 | 780 | library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture fum of foo is
constant A: std_logic_vector (7 downto 0) := X"04";
function slv_image(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end;
begin
SOME_LABEL:
process
begin
wait for 1 ns;
if A <= "00001011" then -- if A <= std_logic_vector'("00001011") then
report "A = " & slv_image(A) ;
end if;
wait;
end process;
end architecture;
| gpl-2.0 | 3d3f05719418ef24a90b0f9bb3cd1758 | 0.592308 | 3.545455 | false | false | false | false |
tgingold/ghdl | testsuite/synth/var01/tb_var05.vhdl | 1 | 847 | entity tb_var05 is
end tb_var05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var05 is
signal clk : std_logic;
signal sel : std_logic;
signal a, b : std_logic_vector (1 downto 0);
signal res : std_logic_vector (1 downto 0);
begin
dut: entity work.var05
port map (
sel => sel,
a => a,
b => b,
res => res);
process
begin
sel <= '1';
a <= "00";
b <= "11";
wait for 1 ns;
assert res = "11" severity failure;
sel <= '0';
a <= "00";
b <= "11";
wait for 1 ns;
assert res = "00" severity failure;
sel <= '0';
a <= "10";
b <= "01";
wait for 1 ns;
assert res = "10" severity failure;
sel <= '1';
a <= "10";
b <= "01";
wait for 1 ns;
assert res = "01" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | e787a68665d146cf80ea8e72759381a1 | 0.525384 | 3.113971 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/lpm_mult_oe0.vhd | 1 | 4,829 | -- megafunction wizard: %LPM_MULT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_mult
-- ============================================================
-- File Name: lpm_mult_oe0.vhd
-- Megafunction Name(s):
-- lpm_mult
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_mult_oe0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_mult_oe0;
ARCHITECTURE SYN OF lpm_mult_oe0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_mult
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_widtha : NATURAL;
lpm_widthb : NATURAL;
lpm_widthp : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
lpm_mult_component : lpm_mult
GENERIC MAP (
lpm_hint => "MAXIMIZE_SPEED=5",
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 27,
lpm_widthb => 5,
lpm_widthp => 32
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
-- Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedMult NUMERIC "1"
-- Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
-- Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
-- Retrieval info: PRIVATE: WidthA NUMERIC "27"
-- Retrieval info: PRIVATE: WidthB NUMERIC "5"
-- Retrieval info: PRIVATE: WidthP NUMERIC "32"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: optimize NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
-- Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "27"
-- Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
-- Retrieval info: USED_PORT: dataa 0 0 27 0 INPUT NODEFVAL dataa[26..0]
-- Retrieval info: USED_PORT: datab 0 0 5 0 INPUT NODEFVAL datab[4..0]
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: @dataa 0 0 27 0 dataa 0 0 27 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 5 0 datab 0 0 5 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| mit | edcafe1e0d04e170a80bbfd110e40bb5 | 0.639884 | 3.569106 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug019/PoC/tb/io/uart/uart_rx_tb.vhdl | 2 | 4,072 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: uart_rx_tb
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Testbench for arith_counter_bcd
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.simulation.all;
use PoC.uart.all;
entity uart_rx_tb is
end entity;
architecture tb of uart_rx_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
constant BAUDRATE : BAUD := 4.2 MBd;
signal Clock : STD_LOGIC;
signal Reset : STD_LOGIC;
signal BitClock : STD_LOGIC;
signal BitClock_x8 : STD_LOGIC;
signal UART_RX : STD_LOGIC;
signal RX_Strobe : STD_LOGIC;
signal RX_Data : T_SLV_8;
function simGenerateWaveform_UART_Word(Data : T_SLV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
constant BIT_TIME : TIME := to_time(to_freq(Baudrate));
variable Result : T_SIM_WAVEFORM_SL(0 to 9) := (others => (Delay => BIT_TIME, Value => '-'));
begin
Result(0).Value := '0';
for i in Data'range loop
Result(i + 1).Value := Data(i);
end loop;
Result(9).Value := '1';
return Result;
end function;
function simGenerateWaveform_UART_Stream(Data : T_SLVV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
variable Result : T_SIM_WAVEFORM_SL(0 to (Data'length * 10) - 1);
begin
for i in Data'range loop
Result(i * 10 to ((i + 1) * 10) - 1) := simGenerateWaveform_UART_Word(Data(i), BAUDRATE);
end loop;
return Result;
end function;
constant DATA_STREAM : T_SLVV_8 := (x"12", x"45", x"FE", x"C4", x"02");
begin
simGenerateClock(Clock, CLOCK_FREQ);
simGenerateWaveform(Reset, simGenerateWaveform_Reset(Pause => 50 ns));
p1f: if true generate
simGenerateWaveform(UART_RX, simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE), '1');
end generate;
p1t: if false generate
process
constant wf : T_SIM_WAVEFORM_SL := simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE);
begin
simGenerateWaveform(UART_RX, wf, '1');
end process;
end generate;
bclk : entity PoC.uart_bclk
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE
)
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
bclk_x8 => BitClock_x8
);
RX : entity PoC.uart_rx
generic map (
OUT_REGS => FALSE
)
port map (
clk => Clock,
rst => Reset,
bclk_x8 => BitClock_x8,
dos => RX_Strobe,
dout => RX_Data,
rxd => UART_RX
);
process
begin
for i in DATA_STREAM'range loop
wait until rising_edge(Clock) and (RX_Strobe = '1');
report TIME'image(NOW) severity NOTE;
tbAssert((RX_Data = DATA_STREAM(i)), "Data Byte " & INTEGER'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h'));
end loop;
wait for 1 us;
simStop;
tbPrintResult;
wait;
end process;
end architecture;
| gpl-2.0 | 71122ada358b983eae7b7284e7fbe1fd | 0.614194 | 3.201258 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_wrdata_cntl.vhd | 7 | 91,473 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_sg_wrdata_cntl;
architecture implementation of axi_sg_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
-- coverage off
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-- coverage on
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_s2mm_strm_wready_del : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
-- sig_s2mm_strm_wready_del;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
sig_s2mm_strm_wready_del <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
sig_s2mm_strm_wready_del <= sig_s2mm_strm_wready;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= (others => '1') when mmap_reset = '0' else (others => '0'); --sig_strt_strb_reg
-- data2skid_wstrb <= sig_strt_strb_reg
-- When (sig_first_dbeat = '1')
-- Else sig_last_strb_reg
-- When (sig_last_dbeat = '1')
-- Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
-- coverage off
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
-- coverage on
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
-- coverage off
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
-- coverage on
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
-- GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
--
-- -- local constants
-- Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
-- Constant NUM_ZEROS_WIDTH : integer := 8;
-- Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
-- Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
-- funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
--
-- Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
--
--
--
-- -- local signals
-- signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
-- signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
-- signal lsig_ld_byte_cntr : std_logic := '0';
-- signal lsig_incr_byte_cntr : std_logic := '0';
-- signal lsig_clr_byte_cntr : std_logic := '0';
-- signal lsig_end_of_cmd_reg : std_logic := '0';
-- signal lsig_eop_s_h_reg : std_logic := '0';
-- signal lsig_eop_reg : std_logic := '0';
-- signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
--
--
--
--
-- begin
--
--
-- -- Assign the outputs to the Write Status Controller
-- data2wsc_eop <= lsig_eop_reg and
-- not(sig_next_calc_error_reg);
--
-- data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
--
--
--
-- -- WRSTRB logic ------------------------------
--
--
--
-- --sig_strbgen_bytes <= (others => '1'); -- set to the max value
--
--
-- -- set the length to the max number of bytes per databeat
-- sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
--
--
--
--
--
--
-- sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
-- STRBGEN_ADDR_SLICE_WIDTH)) ;
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_STRT_STRB_GEN
-- --
-- -- Description:
-- -- Strobe generator used to generate the starting databeat
-- -- strobe value for soft shutdown case where the S2MM has to
-- -- flush out all of the transfers that have been committed
-- -- to the AXI Write address channel. Starting Strobes must
-- -- match the committed address offest for each transfer.
-- --
-- ------------------------------------------------------------
-- I_STRT_STRB_GEN : entity axi_sg_v4_1_2.axi_sg_strb_gen2
-- generic map (
--
-- C_OP_MODE => 0 , -- 0 = Offset/Length mode
-- C_STRB_WIDTH => BYTES_PER_DBEAT ,
-- C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
-- C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
--
-- )
-- port map (
--
-- start_addr_offset => sig_strbgen_addr ,
-- end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
-- num_valid_bytes => sig_strbgen_bytes ,
-- strb_out => sig_sfhalt_next_strt_strb
--
-- );
--
--
--
--
--
--
--
-- -- Generate the WSTRB to use during soft shutdown
-- sig_halt_strb <= sig_strt_strb_reg
-- When (sig_first_dbeat = '1' or
-- sig_single_dbeat = '1')
-- Else (others => '1');
--
--
--
-- -- Generate the Write Strobes for the MMap Write Data Channel
-- -- for the Indeterminate BTT case. Strobes come from the Stream
-- -- input from the Indeterminate BTT module during normal operation.
-- -- However, during soft shutdown, those strobes become unpredictable
-- -- so generated strobes have to be used.
-- data2skid_wstrb <= sig_halt_strb
-- When (sig_halt_reg = '1')
--
-- Else s2mm_strm_wstrb;
--
--
--
-- -- Generate the Stream Ready for the Stream input side
-- sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
-- (sig_mmap2data_ready and -- MMap is accepting the xfers
-- sig_addr_chan_rdy and -- xfers are commited on the address channel and
-- sig_dqual_rdy and -- there are commands in the command fifo
-- not(sig_calc_error_reg) and -- No internal error
-- not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- -- or when the soft shutdown has completed
--
--
-- -- MMap Write Data Channel Valid Handshaking
-- sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
-- sig_halt_reg ) and -- force valid if halt requested
-- sig_addr_chan_rdy and -- xfers are commited on the address channel and
-- sig_dqual_rdy and -- there are commands in the command fifo
-- not(sig_calc_error_reg) and -- No internal error
-- not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- -- or when the soft shutdown has completed
--
--
--
-- -- TLAST Error housekeeping for Indeterminate BTT Mode
-- -- There is no Underrun/overrun in Stroe and Forward mode
--
-- sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
-- sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_EOP_REG_FLOP
-- --
-- -- Process Description:
-- -- Register the End of Packet marker.
-- --
-- -------------------------------------------------------------
-- IMP_EOP_REG_FLOP : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_end_of_cmd_reg <= '0';
-- lsig_eop_reg <= '0';
--
--
-- Elsif (sig_good_strm_dbeat = '1') Then
--
--
-- lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
-- s2mm_strm_wlast;
--
-- lsig_eop_reg <= s2mm_strm_eop;
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_EOP_REG_FLOP;
--
--
--
--
--
-- ----- Byte Counter Logic -----------------------------------------------
-- -- The Byte counter reflects the actual byte count received on the
-- -- Stream input for each parent command loaded into the S2MM command
-- -- FIFO. Thus it counts input bytes until the command complete qualifier
-- -- is set and the TLAST input from the Stream input.
--
--
-- lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
-- not(sig_good_strm_dbeat); -- immediately after the previous one finished.
--
--
-- lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
-- sig_good_strm_dbeat; -- immediately after the previous one finished.
--
-- lsig_incr_byte_cntr <= sig_good_strm_dbeat;
--
--
-- lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
-- BYTE_CNTR_WIDTH);
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_BYTE_CMTR
-- --
-- -- Process Description:
-- -- Keeps a running byte count per burst packet loaded into the
-- -- xfer FIFO. It is based on the strobes set on the incoming
-- -- Stream dbeat.
-- --
-- -------------------------------------------------------------
-- IMP_BYTE_CMTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- lsig_clr_byte_cntr = '1') then
--
-- lsig_byte_cntr <= (others => '0');
--
-- elsif (lsig_ld_byte_cntr = '1') then
--
-- lsig_byte_cntr <= lsig_byte_cntr_incr_value;
--
-- elsif (lsig_incr_byte_cntr = '1') then
--
-- lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
--
-- else
-- null; -- hold current value
-- end if;
-- end if;
-- end process IMP_BYTE_CMTR;
--
--
--
--
--
-- end generate GEN_INDET_BTT;
--
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-3.0 | ed27f79b727f1f94ff1732b69ec6ee9d | 0.417544 | 4.924787 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1081.vhd | 4 | 2,007 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1081.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n02i01081ent IS
END c06s05b00x00p01n02i01081ent;
ARCHITECTURE c06s05b00x00p01n02i01081arch OF c06s05b00x00p01n02i01081ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
BEGIN
TESTING: PROCESS
VARIABLE var : bit_vector_8 := B"1110_0010";
VARIABLE v1 : bit_vector_4 := B"0011";
VARIABLE v2 : bit_vector_4 := B"1111";
BEGIN
var (0 to 3) := v1;
var (4 to 7) := v2;
assert NOT( var = B"0011_1111" )
report "***PASSED TEST: c06s05b00x00p01n02i01081"
severity NOTE;
assert ( var = B"0011_1111" )
report "***FAILED TEST: c06s05b00x00p01n02i01081 - Slices of a variable may be the target of a variable assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n02i01081arch;
| gpl-2.0 | f494a130084691d613d616ddcde5ed34 | 0.657698 | 3.496516 | false | true | false | false |
tgingold/ghdl | testsuite/synth/fsm01/fsm_6s.vhdl | 1 | 1,157 | library ieee;
use ieee.std_logic_1164.all;
entity fsm_6s is
port (clk : std_logic;
rst : std_logic;
d : std_logic;
done : out std_logic);
end fsm_6s;
architecture behav of fsm_6s is
type state_t is (S0_1, S1_0, S2_0, S3_1, S4_0, S5_1);
signal s : state_t;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
s <= S0_1;
done <= '0';
else
-- Reset by default
s <= S0_1;
done <= '0';
case s is
when S0_1 =>
if d = '1' then
s <= S1_0;
end if;
when S1_0 =>
if d = '0' then
s <= S2_0;
end if;
when S2_0 =>
if d = '0' then
s <= S3_1;
end if;
when S3_1 =>
if d = '1' then
s <= S4_0;
end if;
when S4_0 =>
if d = '0' then
s <= S5_1;
end if;
when S5_1 =>
if d = '1' then
done <= '1';
end if;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 9dddc5e4812e2aea2b434332cc4cd08c | 0.384615 | 3.187328 | false | false | false | false |
snow4life/PipelinedDLX | booth.vhd | 1 | 2,941 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity BOOTH is
generic(N: integer);
port( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
P: out std_logic_vector((2*N)-1 downto 0));
end entity BOOTH;
architecture BEHAVIORAL of BOOTH is
signal A_ext: std_logic_vector((2*N)-1 downto 0);
signal B_ext: std_logic_vector(N+1 downto 0);
type operands_array is array (0 to N/2) of std_logic_vector((2*N)-1 downto 0);
signal operand: operands_array;
signal operand_inverted: operands_array;
signal operand_doubled: operands_array;
signal operand_doubled_inverted: operands_array;
type decoded_array is array (0 to (N/2)) of std_logic_vector((2*N)-1 downto 0);
signal decoded: decoded_array;
type partial_products_array is array (2 to (N/2)+1) of std_logic_vector((2*N)-1 downto 0);
signal partial_products: partial_products_array;
begin
A_ext((2*N)-1 downto N) <= (others => '0');
A_ext(N-1 downto 0) <= A;
B_ext(N+1 downto N) <= "00";
B_ext(N-1 downto 0) <= B;
operand(0) <= A_ext;
operand_inverted(0) <= (not A_ext) + '1';
operand_doubled(0) <= to_StdLogicVector((to_bitvector(A_ext)) sll 1);
operand_doubled_inverted(0) <= to_StdLogicVector((to_bitvector(operand_inverted(0))) sll 1);
SHIFTS: for i in 1 to N/2 generate
operand(i) <= to_StdLogicVector((to_bitvector(operand(i-1))) sll 2);
operand_inverted(i) <= to_StdLogicVector((to_bitvector(operand_inverted(i-1))) sll 2);
operand_doubled(i) <= to_StdLogicVector((to_bitvector(operand_doubled(i-1))) sll 2);
operand_doubled_inverted(i) <= to_StdLogicVector((to_bitvector(operand_doubled_inverted(i-1))) sll 2);
end generate SHIFTS;
partial_products(2) <= decoded(0) + decoded(1);
PARTIAL_PRODUCT_GENERATOR: for i in 3 to (N/2)+1 generate
partial_products(i) <= partial_products(i-1) + decoded(i-1);
end generate PARTIAL_PRODUCT_GENERATOR;
decoded(0) <= conv_std_logic_vector(0, 2*N) when B_ext(1 downto 0) = "00" else
operand(0) when B_ext(1 downto 0) = "01" else
operand_doubled_inverted(0) when B_ext(1 downto 0) = "10" else
operand_inverted(0) when B_ext(1 downto 0) = "11";
ENCODER: for i in 1 to N/2 generate
decoded(i) <= conv_std_logic_vector(0, 2*N) when B_ext((i*2)+1 downto (i*2)-1) = "000" else
operand(i) when B_ext((i*2)+1 downto (i*2)-1) = "001" else
operand(i) when B_ext((i*2)+1 downto (i*2)-1) = "010" else
operand_doubled(i) when B_ext((i*2)+1 downto (i*2)-1) = "011" else
operand_doubled_inverted(i) when B_ext((i*2)+1 downto (i*2)-1) = "100" else
operand_inverted(i) when B_ext((i*2)+1 downto (i*2)-1) = "101" else
operand_inverted(i) when B_ext((i*2)+1 downto (i*2)-1) = "110" else
conv_std_logic_vector(0, 2*N) when B_ext((i*2)+1 downto (i*2)-1) = "111";
end generate ENCODER;
P <= partial_products((N/2)+1);
end architecture BEHAVIORAL;
| lgpl-2.1 | f3a04035d94d97961bbd371cb464304c | 0.6678 | 2.668784 | false | false | false | false |
nickg/nvc | test/regress/elab34.vhd | 1 | 1,575 | entity sub is
generic ( width : positive );
port (
clk : in bit;
rst : in bit;
vec : out integer_vector(1 to width) );
end entity;
architecture test of sub is
begin
g1: if width = 1 generate
p: process (clk) is
begin
if rst = '1' then
vec(1) <= 0;
elsif rising_edge(clk) then
vec(1) <= vec(1) + 1;
end if;
end process;
else g2: generate
u1: entity work.sub
generic map ( width / 2 )
port map ( clk, rst, vec(1 to width / 2) );
u2: entity work.sub
generic map ( width / 2 )
port map ( clk, rst, vec(width/2 + 1 to width) );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab34 is
end entity;
architecture test of elab34 is
signal clk, rst : bit := '1';
signal vec : integer_vector(1 to 8);
begin
top: entity work.sub
generic map ( 8 )
port map ( clk, rst, vec );
check: process is
begin
wait for 1 ns;
rst <= '0';
clk <= '0';
assert vec = (1 to 8 => 0);
wait for 1 ns;
clk <= '1';
assert vec = (1 to 8 => 0);
wait for 0 ns;
assert vec = (1 to 8 => 0);
wait for 0 ns;
assert vec = (1 to 8 => 1);
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert vec = (1 to 8 => 2);
wait;
end process;
end architecture;
| gpl-3.0 | a232de0377bf8ac4a7f416759054be3a | 0.448254 | 3.850856 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1193/counters_7.vhdl | 1 | 492 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity counters_7 is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counters_7;
architecture archi of counters_7 is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
| gpl-2.0 | 5679818e8fec388df08d72edf05563ee | 0.575203 | 3.236842 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/v_split6.vhd | 2 | 1,357 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split6 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v_split6;
architecture augh of v_split6 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 5022dee11a873b27be1702e58954b4be | 0.668386 | 2.856842 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/PoC/tb/sort/sortnet/sortnet_tb.pkg.vhdl | 2 | 3,817 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library OSVVM;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
package sortnet_tb is
generic (
META_BITS : positive;
DATA_BITS : positive;
INPUTS : positive
);
subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
function to_dv(slm : T_SLM) return T_DATA_VECTOR;
function to_slm(dv : T_DATA_VECTOR) return T_SLM;
type T_SCOREBOARD_DATA is record
IsKey : std_logic;
Meta : std_logic_vector(META_BITS - 1 downto 0);
Data : T_DATA_VECTOR(INPUTS - 1 downto 0);
end record;
function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean;
function to_string(dataset : T_SCOREBOARD_DATA) return string;
package P_SCOREBOARD is new OSVVM.ScoreboardGenericPkg
generic map (
ExpectedType => T_SCOREBOARD_DATA,
ActualType => T_SCOREBOARD_DATA,
Match => match,
expected_to_string => to_string, --[T_SCOREBOARD_DATA return string],
actual_to_string => to_string
);
alias PT_SCOREBOARD is P_SCOREBOARD.ScoreBoardPType;
end package;
package body sortnet_tb is
function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean is
variable good : boolean;
begin
good := (expected.IsKey = actual.IsKey);
good := good and (expected.Meta = actual.Meta);
if (expected.IsKey = '1') then
for i in expected.Data'range loop
good := good and (expected.Data(i) = actual.Data(i));
exit when (good = FALSE);
end loop;
end if;
return good;
end function;
function to_string(dataset : T_SCOREBOARD_DATA) return string is
variable KeyMarker : string(1 to 2);
begin
KeyMarker := ite((dataset.IsKey = '1'), "* ", " ");
-- for i in 0 to 0 loop --dataset.Key'range loop
return "Data: " & to_string(dataset.Data(0), 'h') & KeyMarker &
" Meta: " & to_string(dataset.Meta, 'h');
-- end loop;
end function;
function to_dv(slm : T_SLM) return T_DATA_VECTOR is
variable Result : T_DATA_VECTOR(slm'range(1));
begin
for i in slm'high(1) downto slm'low(1) loop
for j in T_DATA'range loop
Result(i)(j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_slm(dv : T_DATA_VECTOR) return T_SLM is
variable Result : T_SLM(dv'range, T_DATA'range);
begin
for i in dv'range loop
for j in T_DATA'range loop
Result(i, j) := dv(i)(j);
end loop;
end loop;
return Result;
end function;
end package body;
| gpl-2.0 | a822940987e0d59883373a46cce42e13 | 0.627194 | 3.35708 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/ODOMETRY.vhd | 1 | 6,859 | -- This file contains most of the vhdl necessary for an
-- SCOMP peripheral that performs dead reckoning odometry.
--
-- Specifically, it already contains:
-- Necessary input and output ports
-- Hardware and logic to interface with SCOMP's IO bus
-- Two look-up tables with values for SINE and COSINE
-- Two 16x16-bit multiplers
-- A synchronous process in which to update the odometry
-- Some registers to do math with
-- Some math
--
-- It needs:
-- Some additional registers (probably)
-- Additional math
LIBRARY IEEE;
LIBRARY ALTERA_MF;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE ALTERA_MF.ALTERA_MF_COMPONENTS.ALL;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY ODOMETRY IS
PORT(
CLOCK : IN STD_LOGIC; -- determines the update frequency of the odometry
RESETN : IN STD_LOGIC; -- resets all internal registers
IO_WRITE : IN STD_LOGIC; -- signal from SCOMP
CSX, CSY, CST : IN STD_LOGIC; -- chip-select for X, Y, and theta position
ENC_LPOS : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- incoming wheel encoder position (absolute since reset)
ENC_RPOS : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- incoming wheel encoder position (absolute since reset)
IO_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) -- SCOMP's IO bus lines
);
END ODOMETRY;
ARCHITECTURE A OF ODOMETRY IS
SIGNAL READ_REQ : STD_LOGIC; -- read request from SCOMP
SIGNAL RPOS, LPOS : STD_LOGIC_VECTOR(15 DOWNTO 0); -- internal buffers for the encoder counts
SIGNAL dU, lastSUM : STD_LOGIC_VECTOR(15 DOWNTO 0); -- register for math
SIGNAL XPOS, YPOS : STD_LOGIC_VECTOR(31 DOWNTO 0); -- the X & Y positions kept internally
SIGNAL THETA, SIN_THETA, COS_THETA : STD_LOGIC_VECTOR(15 DOWNTO 0); -- angle, and LUT outputs
SIGNAL THETA360 : STD_LOGIC_VECTOR(19 DOWNTO 0); -- scaled theta value
SIGNAL dUxSIN, dUxCOS : STD_LOGIC_VECTOR(31 DOWNTO 0); -- outputs of the mutipliers
SIGNAL OUTSELECT : STD_LOGIC_VECTOR(2 DOWNTO 0); -- used to select the appropriate output data
SIGNAL OUTDATA : STD_LOGIC_VECTOR(15 DOWNTO 0); -- register that SCOMP reads
CONSTANT THETASCALE : STD_LOGIC_VECTOR(9 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(516,10));
BEGIN
-- ALTSYNCRAM for look-up table (LUT).
-- This RAM is set up as ROM; there is no way to write
-- to it, but it can be loaded with any data from a .MIF file.
-- A MIF has been created with a table of fixed-point
-- SINE values. See the file itself or supporting
-- documentation for more details. Note that the input
-- does NOT have to be in degrees or radians; the division
-- of the circle is user-defined.
-- This memory is synchronous, but here we clock it on the
-- falling edge of the clock so that the data changes between
-- updates to the odometry (which is on the rising edges).
SIN_LUT : altsyncram
GENERIC MAP (
lpm_type => "altsyncram",
width_a => 16,
numwords_a => 2048,
widthad_a => 11,
init_file => "SIN_table.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE"
)
PORT MAP (
clock0 => NOT(CLOCK),
address_a => THETA(10 DOWNTO 0), -- input is angle
q_a => SIN_THETA -- output is sin(angle)
);
-- another LUT, for COSINE values
COS_LUT : altsyncram
GENERIC MAP (
lpm_type => "altsyncram",
width_a => 16,
numwords_a => 2048,
widthad_a => 11,
init_file => "COS_table.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE"
)
PORT MAP (
clock0 => NOT(CLOCK),
address_a => THETA(10 DOWNTO 0), -- input is angle
q_a => COS_THETA -- output is cos(angle)
);
-- LPM_MULT for multiplier.
-- This is an asynchronous device: it multiplies the
-- inputs together and provides an output after the
-- propagation delay of the internal gates.
MULTIPLIERX: LPM_MULT
GENERIC MAP(
lpm_widthA => 16,
lpm_widthB => 16,
lpm_widthP => 32,
lpm_representation => "SIGNED"
)
PORT MAP(
dataA => dU,
dataB => SIN_THETA,
result => dUxSIN
);
-- Another multiplier.
MULTIPLIERY: LPM_MULT
GENERIC MAP(
lpm_widthA => 16,
lpm_widthB => 16,
lpm_widthP => 32,
lpm_representation => "SIGNED"
)
PORT MAP(
dataA => dU,
dataB => COS_THETA,
result => dUxCOS
);
-- Multiplier to scale THETA
MULTIPLIERT: LPM_MULT
GENERIC MAP(
lpm_hint => "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 10,
lpm_widthb => 10,
lpm_widthp => 20
)
PORT MAP(
dataA => THETA(10 DOWNTO 1),
dataB => THETASCALE,
result => THETA360
);
-- LPM tri-state function to drive I/O bus
IO_BUS: LPM_BUSTRI
GENERIC MAP (
lpm_width => 16
)
PORT MAP (
data => OUTDATA, -- send this register
enabledt => READ_REQ, -- when SCOMP requests data
tridata => IO_DATA
);
-- READ_REQ is asserted when SCOMP is requesting ANY data from us
READ_REQ <= NOT(IO_WRITE) AND (CSX OR CSY OR CST);
-- OUTSELECT is used to choose the output.
OUTSELECT <= CSX & CSY & CST;
-- Here we use OUTSELECT to output the appropriate data.
-- Note that XPOS and YPOS are 32 bits, but the bus is 16 bits,
-- so a subset must be taken. It makes sense to ignore the
-- fractional part of the number, which in this case is 10 bits.
-- We should then drop another bit because we don't divide dU by two when
-- it is calculated; however, leaving that extra bit results in units
-- of 1.05mm, which is the same as the other robot posn/vel units.
WITH OUTSELECT SELECT OUTDATA <=
XPOS(26 DOWNTO 11) WHEN "100",
YPOS(26 DOWNTO 11) WHEN "010",
("000000"&THETA360(19 DOWNTO 10)) WHEN "001",
x"0000" WHEN OTHERS;
PROCESS (RESETN, CLOCK)
BEGIN
IF RESETN = '0' THEN -- reset all registers
XPOS <= x"00000000";
YPOS <= x"00000000";
THETA <= x"0000";
RPOS <= x"0000";
LPOS <= x"0000";
dU <= x"0000";
lastSUM <= x"0000";
ELSIF RISING_EDGE(CLOCK) THEN
RPOS <= ENC_RPOS;
LPOS <= ENC_LPOS;
THETA <= STD_LOGIC_VECTOR(SIGNED(RPOS - LPOS) MOD 1428); -- will always be [0,1427]
-- Add dU*COS(theta) to the previous XPOS, and similar with YPOS
XPOS <= XPOS + dUxCOS;
YPOS <= YPOS + dUxSIN;
-- dU is the difference between last sum and current sum. We don't bother
-- dividing by two here. We instead do it when returning the values to SCOMP.
dU <= (LPOS + RPOS) - lastSUM;
lastSUM <= (LPOS + RPOS);
END IF;
END PROCESS;
END A;
| mit | 077fc2a53336f4832ade776e65cd1847 | 0.655052 | 3.250711 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue875/test.vhdl | 1 | 2,722 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all;
use ieee.std_logic_textio.all;
entity example_file_io_tb is
end example_file_io_tb;
architecture behave of example_file_io_tb is
------------------------------------------------------------------------------
-- Declare the Component under Test
------------------------------------------------------------------------------
component module_ripple_carrier_adder is
generic (
g_WIDTH: natural);
port (
i_add_term1 : in std_logic_vector(g_WIDTH-1 downto 0);
i_add_term2 : in std_logic_vector(g_WIDTH-1 downto 0);
o_result : out std_logic_vector(g_WIDTH downto 0);
);
end component module_ripple_carrier_adder;
------------------------------------------------------------------------------
-- Testbench Internal Signals
------------------------------------------------------------------------------
file file_VECTOR : text;
file file_RESULT: text;
constant c_WIDTH : natural := 4;
signal r_ADD_TERM1 : std_logic_vector(c_WIDTH-1 downto 0) := (others => '0');
signal r_ADD_TERM2 : std_logic_vector(c_WIDTH-1 downto 0) := (others => '0');
signal w_SUM : std_logic_vector(c_WIDTH downto 0);
begin
------------------------------------------------------------------------------
-- Instantiate and Map UUT
------------------------------------------------------------------------------
MODULE_RIPPLE_CARRY_ADDER_INST : module_ripple_carry_adder
generic map (
g_WIDTH => c_WIDTH)
port map (
i_addr_term1 => r_ADD_TERM1,
i_addr_term2 => r_ADD_TERM2,
o_result => w_SUM
);
------------------------------------------------------------------------------
-- This procedure reads the file input_vectors.txt which is located in the
-- simulation project area.
-- It will read the data in and send it to the ripple carry adder component
-- to perform the operations. The result is written to the
-- output_results.txt file, located in the same directory.
------------------------------------------------------------------------------
begin
file_open(file_VECTORS, "input_vectors.txt", read_mode);
file_open(file_RESULTS, "output_results.txt", write_mode);
while not endfile(file_VECTORS) loop
readline(file_VECTORS, v_ILINE);
read(v_ILINE, v_ADD_TERM1);
read(v_ILINE, v_SPACE);
read(v_ILINE, V_ADD_TERM2);
-- Pass the variable to a signal to allow the ripple-carry to use it
r_ADD_TERM1 <= v_ADD_TERM1;
r_ADD_TERM2 <= v_ADD_TERM2;
wait for 60 ns;
write(v_OLINE, w_SUM, right, c_WIDTH);
writeline(file_RESULTS, v_OLINE);
end loop;
file_close(file_VECTORS);
file_close(file_RESULTS);
wait;
end process;
end behave;
| gpl-2.0 | 7ae44c55616a2a48708cecc7a1df8775 | 0.524247 | 3.648794 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/sim/vhdl/AESL_axi_s_inStream.vhd | 1 | 87,061 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity AESL_axi_s_inStream is
generic (
constant TV_IN_inStream_TDATA : STRING (1 to 55) := "../tv/cdatafile/c.doHist.autotvin_inStream_V_data_V.dat";
constant INGRESS_STATUS_inStream_TDATA : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_data_V.dat";
constant TV_IN_inStream_TKEEP : STRING (1 to 55) := "../tv/cdatafile/c.doHist.autotvin_inStream_V_keep_V.dat";
constant INGRESS_STATUS_inStream_TKEEP : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_keep_V.dat";
constant TV_IN_inStream_TSTRB : STRING (1 to 55) := "../tv/cdatafile/c.doHist.autotvin_inStream_V_strb_V.dat";
constant INGRESS_STATUS_inStream_TSTRB : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_strb_V.dat";
constant TV_IN_inStream_TUSER : STRING (1 to 55) := "../tv/cdatafile/c.doHist.autotvin_inStream_V_user_V.dat";
constant INGRESS_STATUS_inStream_TUSER : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_user_V.dat";
constant TV_IN_inStream_TLAST : STRING (1 to 55) := "../tv/cdatafile/c.doHist.autotvin_inStream_V_last_V.dat";
constant INGRESS_STATUS_inStream_TLAST : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_last_V.dat";
constant TV_IN_inStream_TID : STRING (1 to 53) := "../tv/cdatafile/c.doHist.autotvin_inStream_V_id_V.dat";
constant INGRESS_STATUS_inStream_TID : STRING (1 to 59) := "../tv/stream_size/stream_ingress_status_inStream_V_id_V.dat";
constant TV_IN_inStream_TDEST : STRING (1 to 55) := "../tv/cdatafile/c.doHist.autotvin_inStream_V_dest_V.dat";
constant INGRESS_STATUS_inStream_TDEST : STRING (1 to 61) := "../tv/stream_size/stream_ingress_status_inStream_V_dest_V.dat";
constant INTERFACE_TYPE : STRING (1 to 5) := "axi_s";
constant AUTOTB_TRANSACTION_NUM : INTEGER := 1
);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_inStream_TDATA : OUT STD_LOGIC_VECTOR (8 - 1 downto 0);
inStream_TDATA_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TKEEP : OUT STD_LOGIC_VECTOR (1 - 1 downto 0);
inStream_TKEEP_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TSTRB : OUT STD_LOGIC_VECTOR (1 - 1 downto 0);
inStream_TSTRB_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TUSER : OUT STD_LOGIC_VECTOR (2 - 1 downto 0);
inStream_TUSER_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TLAST : OUT STD_LOGIC_VECTOR (1 - 1 downto 0);
inStream_TLAST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TID : OUT STD_LOGIC_VECTOR (5 - 1 downto 0);
inStream_TID_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TDEST : OUT STD_LOGIC_VECTOR (6 - 1 downto 0);
inStream_TDEST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TVALID : OUT STD_LOGIC;
TRAN_inStream_TREADY : IN STD_LOGIC;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_axi_s_inStream;
architecture behav of AESL_axi_s_inStream is
------------------------Local signal-------------------
signal reg_inStream_TVALID : STD_LOGIC;
signal inStream_TDATA_mInPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TDATA_mOutPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TDATA_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TDATA_empty_n : STD_LOGIC;
signal inStream_TDATA_full_n : STD_LOGIC;
type inStream_TDATA_arr2D is array(0 to 76800) of STD_LOGIC_VECTOR(8 - 1 downto 0);
signal inStream_TDATA_mem : inStream_TDATA_arr2D := (others => (others => '0'));
signal inStream_TDATA_ingress_status : INTEGER;
signal inStream_TDATA_ingress_status_bit : STD_LOGIC;
signal inStream_TDATA_in_i : INTEGER;
signal inStream_TDATA_in_end : STD_LOGIC;
signal inStream_TDATA_in_end_reg : STD_LOGIC;
signal inStream_TDATA_in_size : INTEGER;
signal inStream_TDATA_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TDATA_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TKEEP_mInPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TKEEP_mOutPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TKEEP_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TKEEP_empty_n : STD_LOGIC;
signal inStream_TKEEP_full_n : STD_LOGIC;
type inStream_TKEEP_arr2D is array(0 to 76800) of STD_LOGIC_VECTOR(1 - 1 downto 0);
signal inStream_TKEEP_mem : inStream_TKEEP_arr2D := (others => (others => '0'));
signal inStream_TKEEP_ingress_status : INTEGER;
signal inStream_TKEEP_ingress_status_bit : STD_LOGIC;
signal inStream_TKEEP_in_i : INTEGER;
signal inStream_TKEEP_in_end : STD_LOGIC;
signal inStream_TKEEP_in_end_reg : STD_LOGIC;
signal inStream_TKEEP_in_size : INTEGER;
signal inStream_TKEEP_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TKEEP_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TSTRB_mInPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TSTRB_mOutPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TSTRB_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TSTRB_empty_n : STD_LOGIC;
signal inStream_TSTRB_full_n : STD_LOGIC;
type inStream_TSTRB_arr2D is array(0 to 76800) of STD_LOGIC_VECTOR(1 - 1 downto 0);
signal inStream_TSTRB_mem : inStream_TSTRB_arr2D := (others => (others => '0'));
signal inStream_TSTRB_ingress_status : INTEGER;
signal inStream_TSTRB_ingress_status_bit : STD_LOGIC;
signal inStream_TSTRB_in_i : INTEGER;
signal inStream_TSTRB_in_end : STD_LOGIC;
signal inStream_TSTRB_in_end_reg : STD_LOGIC;
signal inStream_TSTRB_in_size : INTEGER;
signal inStream_TSTRB_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TSTRB_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TUSER_mInPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TUSER_mOutPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TUSER_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TUSER_empty_n : STD_LOGIC;
signal inStream_TUSER_full_n : STD_LOGIC;
type inStream_TUSER_arr2D is array(0 to 76800) of STD_LOGIC_VECTOR(2 - 1 downto 0);
signal inStream_TUSER_mem : inStream_TUSER_arr2D := (others => (others => '0'));
signal inStream_TUSER_ingress_status : INTEGER;
signal inStream_TUSER_ingress_status_bit : STD_LOGIC;
signal inStream_TUSER_in_i : INTEGER;
signal inStream_TUSER_in_end : STD_LOGIC;
signal inStream_TUSER_in_end_reg : STD_LOGIC;
signal inStream_TUSER_in_size : INTEGER;
signal inStream_TUSER_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TUSER_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TLAST_mInPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TLAST_mOutPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TLAST_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TLAST_empty_n : STD_LOGIC;
signal inStream_TLAST_full_n : STD_LOGIC;
type inStream_TLAST_arr2D is array(0 to 76800) of STD_LOGIC_VECTOR(1 - 1 downto 0);
signal inStream_TLAST_mem : inStream_TLAST_arr2D := (others => (others => '0'));
signal inStream_TLAST_ingress_status : INTEGER;
signal inStream_TLAST_ingress_status_bit : STD_LOGIC;
signal inStream_TLAST_in_i : INTEGER;
signal inStream_TLAST_in_end : STD_LOGIC;
signal inStream_TLAST_in_end_reg : STD_LOGIC;
signal inStream_TLAST_in_size : INTEGER;
signal inStream_TLAST_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TLAST_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TID_mInPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TID_mOutPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TID_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TID_empty_n : STD_LOGIC;
signal inStream_TID_full_n : STD_LOGIC;
type inStream_TID_arr2D is array(0 to 76800) of STD_LOGIC_VECTOR(5 - 1 downto 0);
signal inStream_TID_mem : inStream_TID_arr2D := (others => (others => '0'));
signal inStream_TID_ingress_status : INTEGER;
signal inStream_TID_ingress_status_bit : STD_LOGIC;
signal inStream_TID_in_i : INTEGER;
signal inStream_TID_in_end : STD_LOGIC;
signal inStream_TID_in_end_reg : STD_LOGIC;
signal inStream_TID_in_size : INTEGER;
signal inStream_TID_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TID_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TDEST_mInPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TDEST_mOutPtr : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
signal inStream_TDEST_mFlag_hint : STD_LOGIC := '0'; -- 0:empty hint, 1: full hint
signal inStream_TDEST_empty_n : STD_LOGIC;
signal inStream_TDEST_full_n : STD_LOGIC;
type inStream_TDEST_arr2D is array(0 to 76800) of STD_LOGIC_VECTOR(6 - 1 downto 0);
signal inStream_TDEST_mem : inStream_TDEST_arr2D := (others => (others => '0'));
signal inStream_TDEST_ingress_status : INTEGER;
signal inStream_TDEST_ingress_status_bit : STD_LOGIC;
signal inStream_TDEST_in_i : INTEGER;
signal inStream_TDEST_in_end : STD_LOGIC;
signal inStream_TDEST_in_end_reg : STD_LOGIC;
signal inStream_TDEST_in_size : INTEGER;
signal inStream_TDEST_trans_num_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal inStream_TDEST_trans_num_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal reset_reg : STD_LOGIC;
function esl_icmp_eq(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if v1 = v2 then
res := "1";
else
res := "0";
end if;
return res;
end function;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_icmp_ult(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if unsigned(v1) < unsigned(v2) then
res := "1";
else
res := "0";
end if;
return res;
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if (RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if (i = 1) then
if ((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif ((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif ((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif ((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end esl_str_dec2int;
begin
TRAN_inStream_TVALID_proc : process( inStream_TDATA_empty_n, inStream_TKEEP_empty_n, inStream_TSTRB_empty_n, inStream_TUSER_empty_n, inStream_TLAST_empty_n, inStream_TID_empty_n, inStream_TDEST_empty_n, reset, inStream_TDATA_ingress_status_bit , inStream_TKEEP_ingress_status_bit , inStream_TSTRB_ingress_status_bit , inStream_TUSER_ingress_status_bit , inStream_TLAST_ingress_status_bit , inStream_TID_ingress_status_bit , inStream_TDEST_ingress_status_bit)
begin
if reset = '0' then
TRAN_inStream_TVALID <= '0';
reg_inStream_TVALID <= '0';
else
TRAN_inStream_TVALID <= (inStream_TDATA_ingress_status_bit and inStream_TKEEP_ingress_status_bit and inStream_TSTRB_ingress_status_bit and inStream_TUSER_ingress_status_bit and inStream_TLAST_ingress_status_bit and inStream_TID_ingress_status_bit and inStream_TDEST_ingress_status_bit) or ('1' and inStream_TDATA_empty_n and inStream_TKEEP_empty_n and inStream_TSTRB_empty_n and inStream_TUSER_empty_n and inStream_TLAST_empty_n and inStream_TID_empty_n and inStream_TDEST_empty_n and '1');
reg_inStream_TVALID <= (inStream_TDATA_ingress_status_bit and inStream_TKEEP_ingress_status_bit and inStream_TSTRB_ingress_status_bit and inStream_TUSER_ingress_status_bit and inStream_TLAST_ingress_status_bit and inStream_TID_ingress_status_bit and inStream_TDEST_ingress_status_bit) or ('1' and inStream_TDATA_empty_n and inStream_TKEEP_empty_n and inStream_TSTRB_empty_n and inStream_TUSER_empty_n and inStream_TLAST_empty_n and inStream_TID_empty_n and inStream_TDEST_empty_n and '1');
end if;
end process;
------------------------Read-only axi_s-------------------
-- Write operation for read_only axi_s port
inStream_TDATA_ingress_status_bit <= '1' when inStream_TDATA_ingress_status > 0 else '0';
inStream_TKEEP_ingress_status_bit <= '1' when inStream_TKEEP_ingress_status > 0 else '0';
inStream_TSTRB_ingress_status_bit <= '1' when inStream_TSTRB_ingress_status > 0 else '0';
inStream_TUSER_ingress_status_bit <= '1' when inStream_TUSER_ingress_status > 0 else '0';
inStream_TLAST_ingress_status_bit <= '1' when inStream_TLAST_ingress_status > 0 else '0';
inStream_TID_ingress_status_bit <= '1' when inStream_TID_ingress_status > 0 else '0';
inStream_TDEST_ingress_status_bit <= '1' when inStream_TDEST_ingress_status > 0 else '0';
proc_gen_reset_reg: process(clk)
begin
if(clk'event and clk = '1') then
reset_reg <= reset;
end if;
end process;
------------------------------- inStream_TDATA --------------------------------
inStream_TDATA_empty_n_proc : process(inStream_TDATA_mInPtr, inStream_TDATA_mOutPtr, inStream_TDATA_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TDATA_mInPtr, inStream_TDATA_mOutPtr) = "1" and (inStream_TDATA_mFlag_hint = '0')) then
inStream_TDATA_empty_n <= '0';
else
inStream_TDATA_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TDATA_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_data_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_data_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TDATA_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TDATA_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TDATA_in_end <= '1' when ((inStream_TDATA_in_size = 0) and (reset_reg = '1')) or ((inStream_TDATA_in_i = (inStream_TDATA_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TDATA_trans_num_sig <= inStream_TDATA_trans_num_reg + 1 when ((inStream_TDATA_in_end = '1') and (inStream_TDATA_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TDATA_trans_num_reg;
inStream_TDATA_trans_num <= inStream_TDATA_trans_num_sig;
proc_gen_inStream_TDATA_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TDATA_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TDATA_in_i < inStream_TDATA_in_size - 1) then
inStream_TDATA_in_i <= inStream_TDATA_in_i + 1;
elsif(inStream_TDATA_in_end = '1') then
inStream_TDATA_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TDATA_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TDATA_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TDATA_trans_num_reg <= inStream_TDATA_trans_num_sig;
end if;
end process;
proc_gen_inStream_TDATA_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TDATA_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TDATA_in_end_reg <= inStream_TDATA_in_end;
end if;
end process;
inStream_TDATA_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TDATA_mInPtr_var : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
variable inStream_TDATA_mem_var : inStream_TDATA_arr2D := (others => (others => '0'));
begin
inStream_TDATA_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TDATA, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TDATA & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TDATA, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TDATA & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TDATA_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TDATA_mInPtr_var) > 76800 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TDATA_mem_var(CONV_INTEGER(inStream_TDATA_mInPtr_var)) := esl_str2lv_hex(token, 8);
inStream_TDATA_mInPtr_var := esl_add(inStream_TDATA_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TDATA_mInPtr <= inStream_TDATA_mInPtr_var;
inStream_TDATA_mem <= inStream_TDATA_mem_var;
inStream_TDATA_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TDATA_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TDATA_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TDATA_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TDATA_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TDATA <= inStream_TDATA_mem(CONV_INTEGER(inStream_TDATA_mOutPtr));
inStream_TDATA_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TDATA_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TDATA_mOutPtr,inStream_TDATA_mInPtr) = "1") then
inStream_TDATA_mOutPtr <= esl_add(inStream_TDATA_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TKEEP --------------------------------
inStream_TKEEP_empty_n_proc : process(inStream_TKEEP_mInPtr, inStream_TKEEP_mOutPtr, inStream_TKEEP_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TKEEP_mInPtr, inStream_TKEEP_mOutPtr) = "1" and (inStream_TKEEP_mFlag_hint = '0')) then
inStream_TKEEP_empty_n <= '0';
else
inStream_TKEEP_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TKEEP_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_keep_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_keep_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TKEEP_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TKEEP_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TKEEP_in_end <= '1' when ((inStream_TKEEP_in_size = 0) and (reset_reg = '1')) or ((inStream_TKEEP_in_i = (inStream_TKEEP_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TKEEP_trans_num_sig <= inStream_TKEEP_trans_num_reg + 1 when ((inStream_TKEEP_in_end = '1') and (inStream_TKEEP_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TKEEP_trans_num_reg;
inStream_TKEEP_trans_num <= inStream_TKEEP_trans_num_sig;
proc_gen_inStream_TKEEP_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TKEEP_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TKEEP_in_i < inStream_TKEEP_in_size - 1) then
inStream_TKEEP_in_i <= inStream_TKEEP_in_i + 1;
elsif(inStream_TKEEP_in_end = '1') then
inStream_TKEEP_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TKEEP_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TKEEP_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TKEEP_trans_num_reg <= inStream_TKEEP_trans_num_sig;
end if;
end process;
proc_gen_inStream_TKEEP_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TKEEP_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TKEEP_in_end_reg <= inStream_TKEEP_in_end;
end if;
end process;
inStream_TKEEP_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TKEEP_mInPtr_var : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
variable inStream_TKEEP_mem_var : inStream_TKEEP_arr2D := (others => (others => '0'));
begin
inStream_TKEEP_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TKEEP, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TKEEP & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TKEEP, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TKEEP & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TKEEP_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TKEEP_mInPtr_var) > 76800 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TKEEP_mem_var(CONV_INTEGER(inStream_TKEEP_mInPtr_var)) := esl_str2lv_hex(token, 1);
inStream_TKEEP_mInPtr_var := esl_add(inStream_TKEEP_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TKEEP_mInPtr <= inStream_TKEEP_mInPtr_var;
inStream_TKEEP_mem <= inStream_TKEEP_mem_var;
inStream_TKEEP_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TKEEP_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TKEEP_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TKEEP_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TKEEP_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TKEEP <= inStream_TKEEP_mem(CONV_INTEGER(inStream_TKEEP_mOutPtr));
inStream_TKEEP_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TKEEP_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TKEEP_mOutPtr,inStream_TKEEP_mInPtr) = "1") then
inStream_TKEEP_mOutPtr <= esl_add(inStream_TKEEP_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TSTRB --------------------------------
inStream_TSTRB_empty_n_proc : process(inStream_TSTRB_mInPtr, inStream_TSTRB_mOutPtr, inStream_TSTRB_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TSTRB_mInPtr, inStream_TSTRB_mOutPtr) = "1" and (inStream_TSTRB_mFlag_hint = '0')) then
inStream_TSTRB_empty_n <= '0';
else
inStream_TSTRB_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TSTRB_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_strb_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_strb_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TSTRB_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TSTRB_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TSTRB_in_end <= '1' when ((inStream_TSTRB_in_size = 0) and (reset_reg = '1')) or ((inStream_TSTRB_in_i = (inStream_TSTRB_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TSTRB_trans_num_sig <= inStream_TSTRB_trans_num_reg + 1 when ((inStream_TSTRB_in_end = '1') and (inStream_TSTRB_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TSTRB_trans_num_reg;
inStream_TSTRB_trans_num <= inStream_TSTRB_trans_num_sig;
proc_gen_inStream_TSTRB_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TSTRB_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TSTRB_in_i < inStream_TSTRB_in_size - 1) then
inStream_TSTRB_in_i <= inStream_TSTRB_in_i + 1;
elsif(inStream_TSTRB_in_end = '1') then
inStream_TSTRB_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TSTRB_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TSTRB_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TSTRB_trans_num_reg <= inStream_TSTRB_trans_num_sig;
end if;
end process;
proc_gen_inStream_TSTRB_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TSTRB_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TSTRB_in_end_reg <= inStream_TSTRB_in_end;
end if;
end process;
inStream_TSTRB_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TSTRB_mInPtr_var : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
variable inStream_TSTRB_mem_var : inStream_TSTRB_arr2D := (others => (others => '0'));
begin
inStream_TSTRB_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TSTRB, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TSTRB & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TSTRB, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TSTRB & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TSTRB_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TSTRB_mInPtr_var) > 76800 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TSTRB_mem_var(CONV_INTEGER(inStream_TSTRB_mInPtr_var)) := esl_str2lv_hex(token, 1);
inStream_TSTRB_mInPtr_var := esl_add(inStream_TSTRB_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TSTRB_mInPtr <= inStream_TSTRB_mInPtr_var;
inStream_TSTRB_mem <= inStream_TSTRB_mem_var;
inStream_TSTRB_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TSTRB_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TSTRB_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TSTRB_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TSTRB_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TSTRB <= inStream_TSTRB_mem(CONV_INTEGER(inStream_TSTRB_mOutPtr));
inStream_TSTRB_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TSTRB_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TSTRB_mOutPtr,inStream_TSTRB_mInPtr) = "1") then
inStream_TSTRB_mOutPtr <= esl_add(inStream_TSTRB_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TUSER --------------------------------
inStream_TUSER_empty_n_proc : process(inStream_TUSER_mInPtr, inStream_TUSER_mOutPtr, inStream_TUSER_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TUSER_mInPtr, inStream_TUSER_mOutPtr) = "1" and (inStream_TUSER_mFlag_hint = '0')) then
inStream_TUSER_empty_n <= '0';
else
inStream_TUSER_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TUSER_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_user_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_user_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TUSER_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TUSER_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TUSER_in_end <= '1' when ((inStream_TUSER_in_size = 0) and (reset_reg = '1')) or ((inStream_TUSER_in_i = (inStream_TUSER_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TUSER_trans_num_sig <= inStream_TUSER_trans_num_reg + 1 when ((inStream_TUSER_in_end = '1') and (inStream_TUSER_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TUSER_trans_num_reg;
inStream_TUSER_trans_num <= inStream_TUSER_trans_num_sig;
proc_gen_inStream_TUSER_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TUSER_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TUSER_in_i < inStream_TUSER_in_size - 1) then
inStream_TUSER_in_i <= inStream_TUSER_in_i + 1;
elsif(inStream_TUSER_in_end = '1') then
inStream_TUSER_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TUSER_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TUSER_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TUSER_trans_num_reg <= inStream_TUSER_trans_num_sig;
end if;
end process;
proc_gen_inStream_TUSER_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TUSER_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TUSER_in_end_reg <= inStream_TUSER_in_end;
end if;
end process;
inStream_TUSER_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TUSER_mInPtr_var : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
variable inStream_TUSER_mem_var : inStream_TUSER_arr2D := (others => (others => '0'));
begin
inStream_TUSER_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TUSER, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TUSER & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TUSER, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TUSER & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TUSER_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TUSER_mInPtr_var) > 76800 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TUSER_mem_var(CONV_INTEGER(inStream_TUSER_mInPtr_var)) := esl_str2lv_hex(token, 2);
inStream_TUSER_mInPtr_var := esl_add(inStream_TUSER_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TUSER_mInPtr <= inStream_TUSER_mInPtr_var;
inStream_TUSER_mem <= inStream_TUSER_mem_var;
inStream_TUSER_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TUSER_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TUSER_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TUSER_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TUSER_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TUSER <= inStream_TUSER_mem(CONV_INTEGER(inStream_TUSER_mOutPtr));
inStream_TUSER_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TUSER_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TUSER_mOutPtr,inStream_TUSER_mInPtr) = "1") then
inStream_TUSER_mOutPtr <= esl_add(inStream_TUSER_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TLAST --------------------------------
inStream_TLAST_empty_n_proc : process(inStream_TLAST_mInPtr, inStream_TLAST_mOutPtr, inStream_TLAST_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TLAST_mInPtr, inStream_TLAST_mOutPtr) = "1" and (inStream_TLAST_mFlag_hint = '0')) then
inStream_TLAST_empty_n <= '0';
else
inStream_TLAST_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TLAST_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_last_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_last_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TLAST_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TLAST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TLAST_in_end <= '1' when ((inStream_TLAST_in_size = 0) and (reset_reg = '1')) or ((inStream_TLAST_in_i = (inStream_TLAST_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TLAST_trans_num_sig <= inStream_TLAST_trans_num_reg + 1 when ((inStream_TLAST_in_end = '1') and (inStream_TLAST_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TLAST_trans_num_reg;
inStream_TLAST_trans_num <= inStream_TLAST_trans_num_sig;
proc_gen_inStream_TLAST_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TLAST_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TLAST_in_i < inStream_TLAST_in_size - 1) then
inStream_TLAST_in_i <= inStream_TLAST_in_i + 1;
elsif(inStream_TLAST_in_end = '1') then
inStream_TLAST_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TLAST_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TLAST_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TLAST_trans_num_reg <= inStream_TLAST_trans_num_sig;
end if;
end process;
proc_gen_inStream_TLAST_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TLAST_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TLAST_in_end_reg <= inStream_TLAST_in_end;
end if;
end process;
inStream_TLAST_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TLAST_mInPtr_var : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
variable inStream_TLAST_mem_var : inStream_TLAST_arr2D := (others => (others => '0'));
begin
inStream_TLAST_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TLAST, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TLAST & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TLAST, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TLAST & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TLAST_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TLAST_mInPtr_var) > 76800 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TLAST_mem_var(CONV_INTEGER(inStream_TLAST_mInPtr_var)) := esl_str2lv_hex(token, 1);
inStream_TLAST_mInPtr_var := esl_add(inStream_TLAST_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TLAST_mInPtr <= inStream_TLAST_mInPtr_var;
inStream_TLAST_mem <= inStream_TLAST_mem_var;
inStream_TLAST_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TLAST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TLAST_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TLAST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TLAST_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TLAST <= inStream_TLAST_mem(CONV_INTEGER(inStream_TLAST_mOutPtr));
inStream_TLAST_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TLAST_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TLAST_mOutPtr,inStream_TLAST_mInPtr) = "1") then
inStream_TLAST_mOutPtr <= esl_add(inStream_TLAST_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TID --------------------------------
inStream_TID_empty_n_proc : process(inStream_TID_mInPtr, inStream_TID_mOutPtr, inStream_TID_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TID_mInPtr, inStream_TID_mOutPtr) = "1" and (inStream_TID_mFlag_hint = '0')) then
inStream_TID_empty_n <= '0';
else
inStream_TID_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TID_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_id_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_id_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TID_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TID_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TID_in_end <= '1' when ((inStream_TID_in_size = 0) and (reset_reg = '1')) or ((inStream_TID_in_i = (inStream_TID_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TID_trans_num_sig <= inStream_TID_trans_num_reg + 1 when ((inStream_TID_in_end = '1') and (inStream_TID_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TID_trans_num_reg;
inStream_TID_trans_num <= inStream_TID_trans_num_sig;
proc_gen_inStream_TID_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TID_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TID_in_i < inStream_TID_in_size - 1) then
inStream_TID_in_i <= inStream_TID_in_i + 1;
elsif(inStream_TID_in_end = '1') then
inStream_TID_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TID_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TID_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TID_trans_num_reg <= inStream_TID_trans_num_sig;
end if;
end process;
proc_gen_inStream_TID_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TID_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TID_in_end_reg <= inStream_TID_in_end;
end if;
end process;
inStream_TID_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TID_mInPtr_var : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
variable inStream_TID_mem_var : inStream_TID_arr2D := (others => (others => '0'));
begin
inStream_TID_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TID, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TID & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TID, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TID & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TID_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TID_mInPtr_var) > 76800 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TID_mem_var(CONV_INTEGER(inStream_TID_mInPtr_var)) := esl_str2lv_hex(token, 5);
inStream_TID_mInPtr_var := esl_add(inStream_TID_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TID_mInPtr <= inStream_TID_mInPtr_var;
inStream_TID_mem <= inStream_TID_mem_var;
inStream_TID_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TID_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TID_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TID_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TID_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TID <= inStream_TID_mem(CONV_INTEGER(inStream_TID_mOutPtr));
inStream_TID_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TID_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TID_mOutPtr,inStream_TID_mInPtr) = "1") then
inStream_TID_mOutPtr <= esl_add(inStream_TID_mOutPtr, "1");
end if;
end if;
end if;
end process;
------------------------------- inStream_TDEST --------------------------------
inStream_TDEST_empty_n_proc : process(inStream_TDEST_mInPtr, inStream_TDEST_mOutPtr, inStream_TDEST_mFlag_hint)
begin
if (esl_icmp_eq(inStream_TDEST_mInPtr, inStream_TDEST_mOutPtr) = "1" and (inStream_TDEST_mFlag_hint = '0')) then
inStream_TDEST_empty_n <= '0';
else
inStream_TDEST_empty_n <= '1';
end if;
end process;
proc_gen_inStream_TDEST_in_size: process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable i : INTEGER;
variable token_line : LINE;
variable token : STRING(1 to 200);
begin
file_open(fstatus, fp,"../tv/stream_size/stream_size_in_inStream_V_dest_V.dat" , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & "../tv/stream_size/stream_size_in_inStream_V_dest_V.dat" & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
wait until reset = '1';
wait until clk'event and clk = '1';
while(token(1 to 14) /= "[[[/runtime]]]") loop
i := 0;
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
inStream_TDEST_in_size <= esl_str_dec2int(token);
wait until clk'event and clk = '0';
while (inStream_TDEST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token); --[[/transaction]]
esl_read_token(fp, token_line, token);
end loop;
if(token(1 to 14) /= "[[[/runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
wait until clk'event and clk = '1';
file_close (fp);
wait;
end process;
inStream_TDEST_in_end <= '1' when ((inStream_TDEST_in_size = 0) and (reset_reg = '1')) or ((inStream_TDEST_in_i = (inStream_TDEST_in_size - 1)) and (TRAN_inStream_TREADY = '1')) else '0';
inStream_TDEST_trans_num_sig <= inStream_TDEST_trans_num_reg + 1 when ((inStream_TDEST_in_end = '1') and (inStream_TDEST_trans_num_reg /= AUTOTB_TRANSACTION_NUM + 1)) else inStream_TDEST_trans_num_reg;
inStream_TDEST_trans_num <= inStream_TDEST_trans_num_sig;
proc_gen_inStream_TDEST_in_i : process(reset, clk)
begin
if(reset = '0') then
inStream_TDEST_in_i <= 0;
elsif(clk'event and clk = '1') then
if(TRAN_inStream_TREADY = '1' and inStream_TDEST_in_i < inStream_TDEST_in_size - 1) then
inStream_TDEST_in_i <= inStream_TDEST_in_i + 1;
elsif(inStream_TDEST_in_end = '1') then
inStream_TDEST_in_i <= 0;
end if;
end if;
end process;
proc_gen_inStream_TDEST_trans_num_reg : process(reset, clk)
begin
if(reset = '0') then
inStream_TDEST_trans_num_reg <= X"00000001";
elsif(clk'event and clk = '1') then
inStream_TDEST_trans_num_reg <= inStream_TDEST_trans_num_sig;
end if;
end process;
proc_gen_inStream_TDEST_in_end_reg: process(reset, clk)
begin
if(reset = '0') then
inStream_TDEST_in_end_reg <= '0';
elsif(clk'event and clk = '1') then
inStream_TDEST_in_end_reg <= inStream_TDEST_in_end;
end if;
end process;
inStream_TDEST_read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_len : INTEGER;
variable token_int : INTEGER;
file fp_ingress_status : TEXT;
variable fstatus_ingress_status : FILE_OPEN_STATUS;
variable token_line_ingress_status : LINE;
variable token_ingress_status : STRING(1 to 128);
variable ingress_status_var : INTEGER;
variable transaction_idx : INTEGER;
variable inStream_TDEST_mInPtr_var : STD_LOGIC_VECTOR (18 downto 0) := (others => '0');
variable inStream_TDEST_mem_var : inStream_TDEST_arr2D := (others => (others => '0'));
begin
inStream_TDEST_mFlag_hint <= '0';
transaction_idx := 0;
wait until reset = '1';
wait until clk'event and clk = '1';
file_open(fstatus, fp, TV_IN_inStream_TDEST, READ_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_inStream_TDEST & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if (token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
file_open(fstatus_ingress_status, fp_ingress_status, INGRESS_STATUS_inStream_TDEST, READ_MODE);
if (fstatus_ingress_status /= OPEN_OK) then
assert false report "Open file " & INGRESS_STATUS_inStream_TDEST & " failed!!!" severity failure;
end if;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
while (token(1 to 14) /= "[[[/runtime]]]") loop
if (token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
esl_read_token(fp, token_line, token);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status); -- Skip transaction number
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
inStream_TDEST_mInPtr_var := (others => '0');
while (token(1 to 16) /= "[[/transaction]]") loop
if (CONV_INTEGER(inStream_TDEST_mInPtr_var) > 76800 - 1) then
assert false report "Fifo overflow!" severity failure;
end if;
inStream_TDEST_mem_var(CONV_INTEGER(inStream_TDEST_mInPtr_var)) := esl_str2lv_hex(token, 6);
inStream_TDEST_mInPtr_var := esl_add(inStream_TDEST_mInPtr_var, "1");
esl_read_token(fp, token_line, token);
ingress_status_var := esl_str_dec2int(token_ingress_status);
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
end loop;
inStream_TDEST_mInPtr <= inStream_TDEST_mInPtr_var;
inStream_TDEST_mem <= inStream_TDEST_mem_var;
inStream_TDEST_mFlag_hint <= '0';
wait until clk'event and clk = '0';
while (inStream_TDEST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
esl_read_token(fp, token_line, token);
inStream_TDEST_ingress_status <= ingress_status_var;
esl_read_token(fp_ingress_status, token_line_ingress_status, token_ingress_status);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
wait until clk'event and clk = '0';
while (inStream_TDEST_in_end_reg /= '1') loop
wait until clk'event and clk = '0';
end loop;
inStream_TDEST_mFlag_hint <= '1';
wait;
end process;
TRAN_inStream_TDEST <= inStream_TDEST_mem(CONV_INTEGER(inStream_TDEST_mOutPtr));
inStream_TDEST_mOutPtr_proc : process(clk)
begin
if (clk'event and clk = '0') then
if (ready = '1') then
inStream_TDEST_mOutPtr <= (others => '0');
end if;
elsif (clk'event and clk = '1') then
if (reg_inStream_TVALID = '1' and TRAN_inStream_TREADY = '1') then
if (esl_icmp_ult(inStream_TDEST_mOutPtr,inStream_TDEST_mInPtr) = "1") then
inStream_TDEST_mOutPtr <= esl_add(inStream_TDEST_mOutPtr, "1");
end if;
end if;
end if;
end process;
end behav;
| gpl-3.0 | d2a71078b9b4be9a73793ee5c5cfabb5 | 0.574046 | 3.585413 | false | false | false | false |
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4784)
`protect data_block
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`protect end_protected
| gpl-3.0 | 5fee51820b30c6e0aa1073f6258cac0a | 0.918844 | 1.949489 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl | 1 | 314 | architecture rtl_comp_inst of leds_wrapper is
begin
leds_comp_inst : entity work.leds(spin1)
port map(
clk => clk,
led1 => led1,
led2 => led2,
led3 => led3,
led4 => led4,
led5 => led5,
led6 => led6,
led7 => led7,
led8 => led8
);
end architecture;
| gpl-2.0 | 524001d5b85c3a8fbba4b35b7241b4d3 | 0.528662 | 3.108911 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug15993/testbench.vhdl | 3 | 2,500 | -- Test Bench
-- inspired from http://ghdl.free.fr/ghdl/A-full-adder.html#A-full-adder
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
ENTITY add_tb IS
END add_tb;
-------------------------------------------------------------------------------
ARCHITECTURE behave OF add_tb IS
COMPONENT add4
GENERIC ( n : INTEGER := 4 );
PORT ( a, b : IN STD_LOGIC_VECTOR ( n-1 DOWNTO 0 );
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR ( n DOWNTO 0 ) );
END COMPONENT;
FOR ALL: add4 USE ENTITY work.addern;
SIGNAL i0, i1 : STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
SIGNAL s : STD_LOGIC_VECTOR ( 4 DOWNTO 0 );
SIGNAL ci : STD_LOGIC;
BEGIN
adder0: add4
PORT MAP ( a => i0, b => i1, cin => ci, sum => s );
-- This process does the real job.
PROCESS
TYPE pattern_type IS RECORD
-- The inputs of the adder.
i0, i1 : STD_LOGIC_VECTOR( 3 DOWNTO 0 );
ci : STD_LOGIC;
-- The expected outputs of the adder.
s : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
END RECORD;
-- The patterns to apply.
TYPE pattern_array IS ARRAY (natural RANGE <>) OF pattern_type;
CONSTANT patterns : pattern_array :=
(("0000", "0000", '0', "00000"),
("0000", "0001", '0', "00001"),
("0001", "0000", '0', "00001"),
("0001", "0001", '0', "00010"),
("0001", "0001", '1', "00011"),
("0001", "0010", '0', "00011"),
("0001", "0010", '1', "00100"),
("0010", "0010", '0', "00100"));
BEGIN
-- Check each pattern.
FOR i IN patterns'RANGE LOOP
-- Set the inputs.
i0 <= patterns(i).i0;
i1 <= patterns(i).i1;
ci <= patterns(i).ci;
-- Wait for the results.
WAIT FOR 1 ns;
-- Check the outputs.
ASSERT s = patterns(i).s
REPORT "bad sum value" SEVERITY note;
-- assert co = patterns(i).co
-- report "bad carray out value" severity error;
END LOOP;
ASSERT false REPORT "end of test" SEVERITY note;
-- Wait forever; this will finish the simulation.
WAIT;
END PROCESS;
END behave;
| gpl-2.0 | 07348bd8742368538768f55b3e89e3eb | 0.448 | 4.118616 | false | false | false | false |
nickg/nvc | test/eopt/arrayref1.vhd | 1 | 746 | entity arrayref is
end entity;
architecture test of arrayref is
function resolved (x : bit_vector) return bit;
subtype r_bit is resolved bit;
type r_bit_vector is array (natural range <>) of r_bit;
type bv2d is array (integer range <>) of r_bit_vector(1 downto 0);
signal x : r_bit_vector(2 downto 0); -- 0..2
signal y : r_bit_vector(1 downto 0); -- 3..4
signal i : integer; -- 5..5
signal p : bv2d(0 to 1); -- 6..9
signal q : bv2d(0 to 2); -- 10..15
signal r : bv2d(0 to 2); -- 16..21
begin
x(0) <= '1';
x(1) <= '0';
y(i) <= '1';
p(0)(i) <= '1';
p(1) <= "00";
q(i) <= "10";
r(2)(i) <= '1';
end architecture;
| gpl-3.0 | 18e2cc9a4a0ed27fc470511de8643961 | 0.493298 | 2.972112 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug061/datastructure.vhdl | 2 | 2,138 | library ieee;
use ieee.std_logic_1164.all;
package DataStructures is
-- Simple hashing functions
function Modulo_Int (d : integer; size : positive) return natural;
function Modulo (d : string; size : positive) return natural;
-- Dictionaries
package Integer_Integer_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => integer,
VALUE_TYPE => integer,
to_hash => Modulo_Int);
package Integer_StdLogicVector_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => integer,
VALUE_TYPE => std_logic_vector,
to_hash => Modulo_Int);
package String_String_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => string,
VALUE_TYPE => string,
to_hash => Modulo);
package String_StdLogicVector_Dict_Pkg is new work.corelib_Dict
generic map (KEY_TYPE => string,
VALUE_TYPE => std_logic_vector,
to_hash => Modulo);
-- Aliases for convenience reasons
alias Integer_Integer_Dict is Integer_Integer_Dict_Pkg.PT_DICT;
alias Integer_Slv_Dict is Integer_StdLogicVector_Dict_Pkg.PT_DICT;
alias String_String_Dict is String_String_Dict_Pkg.PT_DICT;
alias String_Slv_Dict is String_StdLogicVector_Dict_Pkg.PT_DICT;
end package;
package body DataStructures is
-- Simple modulo function for integers
function Modulo_int (d : integer; size : positive) return natural is
begin
return d mod size;
end function Modulo_Int;
-- Simple modulo function for ISO 8859 Latin-1 8-bit strings
-- of arbitrary length (>= VHDL 93)
function Modulo (d : string; size : positive) return natural is
variable hash : natural := 0;
begin
assert size <= ((natural'high - 255) / 256 + 1)
report Modulo[string, natural return natural]'instance_name & ": size parameter too large, possible overflow"
severity failure;
for i in d'range loop
hash := (hash * 256 + Character'Pos (d(i))) mod size;
end loop;
return hash;
end function Modulo;
end package body DataStructures;
| gpl-2.0 | bdc563592f9e894b4de55fe127463800 | 0.651076 | 3.981378 | false | false | false | false |
tgingold/ghdl | testsuite/synth/arr01/arr07.vhdl | 1 | 923 | library ieee;
use ieee.std_logic_1164.all;
entity arr07 is
port (clk : in std_logic;
val : std_logic_vector(7 downto 0);
res : out std_logic_vector(7 downto 0);
par : out std_logic);
end arr07;
architecture behav of arr07 is
type pipe_el is record
val : std_logic_vector(7 downto 0);
odd : std_logic;
end record;
type pipe_type is array (0 to 15) of pipe_el;
signal mem : pipe_type;
signal n_mem : pipe_type;
signal tick : std_logic := '0';
begin
process(clk)
begin
if rising_edge (clk) then
mem <= n_mem;
tick <= not tick;
end if;
end process;
process(mem, val, tick)
variable v : pipe_type;
begin
for i in 1 to pipe_type'high loop
v (i) := mem (i - 1);
end loop;
v (0).val := val;
v (0).odd := tick;
n_mem <= v;
end process;
res <= mem (pipe_type'high).val;
par <= mem (pipe_type'high).odd;
end behav;
| gpl-2.0 | 2a85057288b1eded57a6ee31a7b8b8b9 | 0.590466 | 3.056291 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd | 4 | 1,593 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
signal y : bit := '0';
signal or_a_b : bit := '0';
signal clk : bit := '0';
begin
process_3_a : process is
begin
-- code from book:
y <= not or_a_b after 5 ns;
-- end of code from book
wait on or_a_b;
end process process_3_a;
stimulus_3_a : process is
begin
or_a_b <= '1' after 20 ns,
'0' after 40 ns;
wait;
end process stimulus_3_a;
process_3_b : process is
constant T_pw : delay_length := 10 ns;
begin
-- code from book:
clk <= '1' after T_pw, '0' after 2*T_pw;
-- end of code from book
wait for 2*T_pw;
end process process_3_b;
end architecture test;
| gpl-2.0 | 5658bb09b3b25547441a47812b39120d | 0.635907 | 3.721963 | false | false | false | false |
nickg/nvc | test/regress/genpack4.vhd | 1 | 1,936 | package poly is
generic (a, b : integer);
function apply (x : integer) return integer;
end package;
package body poly is
function add (x, y : integer) return integer is
begin
return x + y;
end function;
function mul (x, y : integer) return integer is
begin
return x * y;
end function;
function apply (x : integer) return integer is
begin
return add(mul(x, a), b);
end function;
end package body;
-------------------------------------------------------------------------------
package wrapper is
generic ( package p is new work.poly generic map ( <> ) );
function wrapped_apply (n : integer) return integer;
procedure check_params (xa, xb : integer);
end package;
package body wrapper is
use p.all;
function wrapped_apply (n : integer) return integer is
begin
return apply(n);
end function;
procedure check_params (xa, xb : integer) is
begin
report "a=" & to_string(a) & " b=" & to_string(b);
assert a = xa;
assert b = xb;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity genpack4 is
end entity;
architecture test of genpack4 is
package my_poly1 is new work.poly generic map (a => 2, b => 3);
package my_wrap1 is new work.wrapper generic map (p => my_poly1);
package my_poly2 is new work.poly generic map (a => 5, b => 1);
package my_wrap2 is new work.wrapper generic map (p => my_poly2);
begin
main: process is
variable v : integer := 5;
begin
assert my_wrap1.wrapped_apply(2) = 7;
wait for 1 ns;
assert my_wrap1.wrapped_apply(v) = 13;
my_wrap1.check_params(2, 3);
assert my_wrap2.wrapped_apply(2) = 11;
assert my_wrap2.wrapped_apply(v) = 26;
my_wrap2.check_params(v, 1);
wait;
end process;
end architecture;
| gpl-3.0 | 5f50420b37e47c9420a009bd6497c3e1 | 0.56405 | 3.856574 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/fixed_generic_pkg.vhdl | 2 | 66,781 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Fixed-point package (Generic package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.fixed_float_types.all;
package fixed_generic_pkg is
generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
no_warning : BOOLEAN := false
);
-- Author David Bishop ([email protected])
constant CopyRightNotice : STRING :=
"Copyright IEEE P1076 WG. Licensed Apache 2.0";
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
alias U_ufixed is UNRESOLVED_ufixed;
alias U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is (resolved) UNRESOLVED_ufixed;
subtype sfixed is (resolved) UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNRESOLVED_UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNRESOLVED_UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : UNRESOLVED_SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : UNRESOLVED_SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & TO_STRING(x) severity error;
function TO_STRING (value : UNRESOLVED_ufixed) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function TO_OSTRING (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function TO_HSTRING (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function TO_STRING (value : UNRESOLVED_sfixed) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function TO_OSTRING (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function TO_HSTRING (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
end package fixed_generic_pkg;
| gpl-2.0 | 8f75eec4a46a400ec63e87b7012bab30 | 0.618529 | 4.138634 | false | false | false | false |
tgingold/ghdl | testsuite/synth/oper01/snum02.vhdl | 1 | 547 | entity snum02 is
port (ok : out boolean);
end snum02;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of snum02 is
-- add sgn int
constant a1 : signed (7 downto 0) := x"1d";
constant b1 : integer := 3;
constant r1 : signed (7 downto 0) := a1 + b1;
constant a2 : signed (7 downto 0) := x"24";
constant b2 : integer := -4;
constant r2 : signed (7 downto 0) := a2 + b2;
signal er1 : signed (7 downto 0) := x"20";
begin
-- ok <= r1 = x"20";
ok <= r1 = er1 and r2 = er1;
end behav;
| gpl-2.0 | 592885bf7e11ed38926e584937354090 | 0.612431 | 2.790816 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/v_split2.vhd | 2 | 1,357 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split2 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v_split2;
architecture augh of v_split2 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | be9b71655a57a605c2cec4a56fbfd010 | 0.668386 | 2.856842 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_router_async_s1d2_x4_b/tb_sip_router_async_s1d2.vhd | 1 | 12,527 | -------------------------------------------------------------------------------------
-- FILE NAME : tb_sip_router_async_s1d2.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - tb_sip_router_async_s1d2
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_sip_router_async_s1d2 is
end tb_sip_router_async_s1d2;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_sip_router_async_s1d2 is
-------------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------------
component generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end component generic_host_emu;
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_10_MHZ : time := 100 ns;
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_368_MHZ : time := 2.7126 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
constant DATA_WIDTH : natural := 8;
constant ADDR_WIDTH : natural := 8;
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
type bus016 is array(natural range <>) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal clk200 : std_logic := '1';
signal clk100 : std_logic := '1';
signal rst_delay : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal rst_rstin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_clkin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_cmd : std_logic;
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal out_cmd_val : std_logic;
signal out_cmd : std_logic_vector(63 downto 0);
signal adc0_out : std_logic_vector(63 downto 0);
signal adc0_val : std_logic;
signal adc0_stop : std_logic;
signal dac0_out : std_logic_vector(63 downto 0);
signal dac0_val : std_logic;
signal dac0_stop : std_logic;
signal flop : std_logic := '1';
--stimulus
signal samples16bit : bus016(3 downto 0) := (others=>(others=>'0'));
signal base_cnt : std_logic_vector(15 downto 0);
signal send_data : std_logic_vector(63 downto 0);
signal send_valid : std_logic;
signal valid_in_cnt : std_logic_vector(31 downto 0);
signal valid_out_cnt : std_logic_vector(31 downto 0);
signal valid_out : std_logic;
signal diff_001 : std_logic_vector(31 downto 0);
signal in_stop : std_logic;
signal data_recv : std_logic_vector(63 downto 0);
signal verify_error : std_logic := '0';
signal verify_cnt : std_logic_vector(63 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_125_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
clk200 <= not clk200 after CLK_167_MHZ / 2;
clk100 <= not clk100 after CLK_125_MHZ / 2;
rst <= '0' after CLK_125_MHZ * 10;
rst_delay <= '0' after CLK_125_MHZ * 20;
rstn <= '1' after CLK_125_MHZ * 10;
rst_rstin <= (0=>rst, 1 => rst, 2=> rst, others =>'0');
clk_clkin <= (13 => clk200, 14 => clk100, others=>clk);
-----------------------------------------------------------
-- Host Interface
-----------------------------------------------------------
inst0_generic_host: generic_host_emu
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"00000FF",
private_start_addr_gen => x"0000000",
private_stop_addr_gen => x"00000FF"
)
port map (
cmdclk_out_cmdclk => clk_cmd, -- out std_logic;
cmd_in_cmdin => out_cmd , -- in std_logic_vector(63 downto 0);
cmd_in_cmdin_val => out_cmd_val, -- in std_logic;
cmd_out_cmdout => in_cmd, -- out std_logic_vector(63 downto 0);
cmd_out_cmdout_val => in_cmd_val, -- out std_logic;
ifpga_rst_out_ifpga_rst => open, -- out std_logic;
clk_clkin => (others=>'0'),-- in std_logic_vector(31 downto 0);
rst_rstin => (others=>'0'),-- in std_logic_vector(31 downto 0);
sys_clk => clk, -- in std_logic;
sys_reset_n => rstn, -- in std_logic;
in_data_in_stop => adc0_stop, -- out std_logic;
in_data_in_dval => adc0_val, -- in std_logic;
in_data_in_data => adc0_out, -- in std_logic_vector(63 downto 0);
out_data_out_stop => dac0_stop, -- in std_logic;
out_data_out_dval => dac0_val, -- out std_logic;
out_data_out_data => dac0_out -- out std_logic_vector(63 downto 0)
);
-----------------------------------------------------------------------------------
-- Unit under test
-----------------------------------------------------------------------------------
sip_router_async_s1d2_x4_b_0 : entity xil_defaultlib.sip_router_async_s1d2_x4_b
generic map
(
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"0001FFF",
private_start_addr_gen => x"0000200",
private_stop_addr_gen => x"00002FF"
)
port map
(
cmdclk_in_cmdclk => clk_cmd,
cmd_in_cmdin => in_cmd,
cmd_in_cmdin_val => in_cmd_val,
cmd_out_cmdout => out_cmd,
cmd_out_cmdout_val => out_cmd_val,
clk_clkin => clk_clkin,
rst_rstin => rst_rstin,
in0_in_stop => in_stop,
in0_in_dval => send_valid,
in0_in_data => send_data,
in1_in_stop => open,
in1_in_dval => send_valid,
in1_in_data => send_data,
in2_in_stop => open,
in2_in_dval => send_valid,
in2_in_data => send_data,
in3_in_stop => open,
in3_in_dval => send_valid,
in3_in_data => send_data,
out0_0_out_stop => '0',
out0_0_out_dval => open,
out0_0_out_data => open,
out1_0_out_stop => '0',
out1_0_out_dval => open,
out1_0_out_data => open,
out2_0_out_stop => '0',
out2_0_out_dval => open,
out2_0_out_data => open,
out3_0_out_stop => '0',
out3_0_out_dval => open,
out3_0_out_data => open,
out0_1_out_stop => '0',
out0_1_out_dval => valid_out,
out0_1_out_data => data_recv,
out1_1_out_stop => '0',
out1_1_out_dval => open,
out1_1_out_data => open,
out2_1_out_stop => '0',
out2_1_out_dval => open,
out2_1_out_data => open,
out3_1_out_stop => '0',
out3_1_out_dval => open,
out3_1_out_data => open
);
process(clk100, rst_delay)
begin
if rst_delay = '1' then
valid_out_cnt <= (others=>'0');
verify_error <= '0';
verify_cnt <= x"00000000_00000001";
elsif rising_edge(clk100) then
if valid_out = '1' then
valid_out_cnt <= valid_out_cnt + 1;
verify_cnt <= verify_cnt + 1;
end if;
if valid_out = '1' and verify_cnt /= data_recv then
verify_error <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Data generation
-----------------------------------------------------------------------------------
process(clk200, rst_delay)
begin
if rising_edge(clk200) then
if rst_delay = '1' then
base_cnt <= (others =>'0');
send_valid <= '0';
send_data <= (others=>'0');
valid_in_cnt <= (others=>'0');
diff_001 <= (others=>'0');
else
if in_stop = '0' then
base_cnt <= base_cnt + 4;
-- send_data <= samples16bit(3) & samples16bit(2) & samples16bit(1) & samples16bit(0);
send_data <= send_data + 1; -- samples16bit(3) & samples16bit(2) & samples16bit(1) & samples16bit(0);
send_valid <= '1';
else
send_valid <= '0';
end if;
if send_valid = '1' then
valid_in_cnt <= valid_in_cnt + 1;
end if;
diff_001 <= valid_in_cnt - valid_out_cnt;
end if;
end if;
end process;
samples16bit(0) <= base_cnt + 0;
samples16bit(1) <= base_cnt + 1;
samples16bit(2) <= base_cnt + 2;
samples16bit(3) <= base_cnt + 3;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | 0265d3ca69f172407ec520f7ef35eafa | 0.43075 | 3.737172 | false | false | false | false |
nickg/nvc | test/lower/attr1.vhd | 1 | 507 | entity attr1 is
end entity;
architecture test of attr1 is
type my_int is range 10 downto 0;
begin
p1: process is
variable x : integer := 0;
variable y : my_int;
variable z : integer := 1;
begin
assert integer'succ(x) = 1;
assert integer'pred(x) = -1;
assert integer'leftof(z) = 0;
assert integer'rightof(z) = 2;
assert my_int'leftof(y) = 2;
assert my_int'rightof(y) = 0;
wait;
end process;
end architecture;
| gpl-3.0 | 2d3f69b644b028086d39c2646f62a816 | 0.571992 | 3.496552 | false | false | false | false |
tgingold/ghdl | testsuite/synth/mem2d01/tb_dpram1r.vhdl | 1 | 1,344 | entity tb_dpram1r is
end tb_dpram1r;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dpram1r is
signal raddr : natural range 0 to 3;
signal rbit : natural range 0 to 7;
signal rdat : std_logic;
signal waddr : natural range 0 to 3;
signal wdat : std_logic_vector(7 downto 0);
signal clk : std_logic;
begin
dut: entity work.dpram1r
port map (raddr => raddr, rbit => rbit, rdat => rdat,
waddr => waddr, wdat => wdat,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
raddr <= 0;
rbit <= 0;
waddr <= 1;
wdat <= x"e1";
pulse;
raddr <= 1;
rbit <= 0;
waddr <= 0;
wdat <= x"f0";
pulse;
assert rdat = '1' severity failure;
raddr <= 1;
rbit <= 1;
waddr <= 2;
wdat <= x"d2";
pulse;
assert rdat = '0' severity failure;
raddr <= 1;
rbit <= 7;
waddr <= 3;
wdat <= x"c3";
pulse;
assert rdat = '1' severity failure;
raddr <= 3;
rbit <= 7;
waddr <= 0;
wdat <= x"f0";
pulse;
assert rdat = '1' severity failure;
raddr <= 3;
rbit <= 5;
waddr <= 0;
wdat <= x"f0";
pulse;
assert rdat = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 25bec6637fba7776a7ca9aeee1c1aa36 | 0.532738 | 3.36 | false | false | false | false |
nickg/nvc | test/bounds/case2.vhd | 1 | 1,145 | entity incorrect_choice_length is
end entity;
architecture arch of incorrect_choice_length is
type some_datastructure_t is record
name : string;
value : natural range 0 to 3;
end record;
type some_datastructure_array is array (natural range <>) of some_datastructure_t;
constant some_datastructure : some_datastructure_array(0 to 3) := (
0 => (name => "zarro", value => 0),
1 => (name => "one", value => 1),
2 => (name => "two", value => 2),
3 => (name => "three", value => 3)
);
begin
process is
variable int : integer;
procedure printValue(constant x: some_datastructure_t) is
begin
case x.name is
when "zarro" =>
report "We got value : " & natural'image(x.value);
when "one" =>
report "We got value : " & natural'image(x.value);
when "two" =>
report "We got value : " & natural'image(x.value);
when "three" =>
report "We got value : " & natural'image(x.value);
end case;
end procedure;
begin
printValue(some_datastructure(0));
printValue(some_datastructure(1));
printValue(some_datastructure(2));
printValue(some_datastructure(3));
end process;
end architecture;
| gpl-3.0 | 7c4d9258e997483d046aca7e9e22e219 | 0.655022 | 3.15427 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue216/repro1.vhdl | 2 | 346 | entity repro1 is
generic (c : natural := 4);
end repro1;
architecture behav of repro1 is
constant cmap : string (1 to 5) :=
(1 => 'a', 2 => 'b', 3 => 'c', 4 => 'd', 5 => 'e');
begin
process
variable v : character;
begin
v := cmap (c);
assert v = 'd' report "bad value" severity error;
wait;
end process;
end behav;
| gpl-2.0 | bbc1080eac0c5d317c6303d5dbbe1355 | 0.566474 | 3.089286 | false | false | false | false |
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