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nickg/nvc | test/regress/issue516.vhd | 1 | 3,264 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue516 is
end entity;
architecture beh of issue516 is
type t_event_ctrl_unresolved is record
val : std_logic;
ack : std_logic;
end record;
type t_event_ctrl_drivers is array (natural range <> ) of t_event_ctrl_unresolved;
function resolved_event_ctrl(input_vector : t_event_ctrl_drivers) return t_event_ctrl_unresolved;
subtype t_event_ctrl is resolved_event_ctrl t_event_ctrl_unresolved;
type t_events_unresolved is record
flag1 : t_event_ctrl;
flag2 : t_event_ctrl;
end record;
type t_events_drivers is array (natural range <> ) of t_events_unresolved;
function resolved_events(input_vector : t_events_drivers) return t_events_unresolved;
subtype t_events is resolved_events t_events_unresolved;
function resolved_event_ctrl(
input_vector : t_event_ctrl_drivers
) return t_event_ctrl_unresolved
is
variable ret : t_event_ctrl_unresolved := (others => '0');
begin
if input_vector'length = 0 THEN
return ret;
else
for i in input_vector'range loop
if input_vector(i).val = '1' then
ret.val := '1';
end if;
if input_vector(i).ack = '1' then
ret.ack := '1';
end if;
end loop;
return ret;
end if;
end function resolved_event_ctrl;
function resolved_events(
input_vector : t_events_drivers
) return t_events_unresolved
is
variable ret : t_events_unresolved := (others => (others => '0'));
begin
if input_vector'length = 0 THEN
return ret;
else
for i in input_vector'range loop
ret.flag1 := resolved_event_ctrl(t_event_ctrl_drivers'(ret.flag1, input_vector(i).flag2));
ret.flag2 := resolved_event_ctrl(t_event_ctrl_drivers'(ret.flag2, input_vector(i).flag2));
end loop;
return ret;
end if;
end function resolved_events;
signal events : t_events;
signal passed : boolean;
begin
p_events : process
begin
events <= (others => (others => '0'));
loop
wait on events.flag2.val;
report "Got val" severity note;
if rising_edge(events.flag2.val) then
report "Sending ack" severity note;
events.flag2.ack <= '1' after 1 us, '0' after 1.1 us;
end if;
if falling_edge(events.flag2.val) then
report "Resetting ack" severity note;
events.flag2.ack <= '1', '0' after 1 ns;
end if;
end loop;
end process p_events;
process
procedure com2(signal flag : inout t_event_ctrl) is
begin
events.flag2.val <= '1';
report "Send val 1" severity note;
wait until events.flag2.ack = '1';
report "Got ack" severity note;
report "Send val 0" severity note;
events.flag2.val <= '1';
wait until events.flag2.ack = '0';
report "Got ack 0" severity note;
end procedure;
procedure com(signal flag_event : inout t_events) is
begin
com2(flag_event.flag2);
end procedure;
begin
wait for 1 us;
report "Running" severity note;
com(events);
passed <= true;
wait;
end process;
check: process is
begin
wait for 5 us;
assert passed;
wait;
end process;
end architecture beh;
| gpl-3.0 | d2a8145954ca46c0d7032e6bd7613b32 | 0.635723 | 3.524838 | false | false | false | false |
tgingold/ghdl | testsuite/synth/rec01/rec01.vhdl | 1 | 593 | library ieee;
use ieee.std_logic_1164.all;
use work.rec01_pkg.all;
entity rec01 is
port (inp : myrec;
rst : std_logic;
clk : std_logic;
o : out std_logic);
end rec01;
architecture behav of rec01 is
signal s : myrec;
begin
process (clk) is
begin
if rising_edge (clk) then
if rst = '1' then
s <= (a => "0000", b => '0');
else
if inp.b = '1' then
s <= (a => inp.a, b => '1');
else
s <= inp;
end if;
end if;
end if;
end process;
o <= '1' when s.a (1) = s.b else '0';
end behav;
| gpl-2.0 | f14a63aacf0e9122f5ffb632c3141d3b | 0.49747 | 3.010152 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/top.vhd | 2 | 261,165 | library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(7 downto 0);
stdin_data : in std_logic_vector(7 downto 0);
stdin_rdy : out std_logic
);
end top;
architecture augh of top is
-- Declaration of components
component cmp_869 is
port (
eq : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in0 : in std_logic_vector(7 downto 0)
);
end component;
component cmp_978 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_979 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_847 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_855 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_852 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component mul_213 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_216 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_214 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component cmp_846 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_848 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_849 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component p_jinfo_comps_info_id is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_h_samp_factor is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_quant_tbl_no is
port (
wa0_data : in std_logic_vector(1 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(1 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_comps_info_dc_tbl_no is
port (
wa0_data : in std_logic;
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic;
wa0_en : in std_logic
);
end component;
component p_jinfo_quant_tbl_quantval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_dc_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component p_jinfo_ac_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_vpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_hpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component outdata_comp_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(14 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(14 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component izigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end component;
component jpegfilebuf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(12 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(12 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component huffbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component idctbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(8 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(8 downto 0);
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component quantbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(5 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component extend_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(20 downto 0)
);
end component;
component bit_set_mask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0)
);
end component;
component lmask is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0)
);
end component;
component huff_make_dhuff_tb_ac_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_ac_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_dc_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component huff_make_dhuff_tb_dc_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end component;
component rgb_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end component;
component zigzag_index is
port (
clk : in std_logic;
ra0_addr : in std_logic_vector(5 downto 0);
ra0_data : out std_logic_vector(5 downto 0)
);
end component;
component shr_212 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end component;
component mul_209 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component mul_210 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component shl_211 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end component;
component sub_206 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_207 is
port (
ge : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_208 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_205 is
port (
gt : out std_logic;
ge : out std_logic;
lt : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component add_202 is
port (
output : out std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component add_203 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component add_204 is
port (
output : out std_logic_vector(24 downto 0);
in_b : in std_logic_vector(24 downto 0);
in_a : in std_logic_vector(24 downto 0)
);
end component;
component add_201 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component add_200 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end component;
component cmp_775 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_779 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_780 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_787 is
port (
eq : out std_logic;
in1 : in std_logic;
in0 : in std_logic
);
end component;
component cmp_788 is
port (
eq : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_790 is
port (
ne : out std_logic;
in1 : in std_logic_vector(3 downto 0);
in0 : in std_logic_vector(3 downto 0)
);
end component;
component cmp_792 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_793 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_794 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_791 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_804 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_800 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_799 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_865 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_882 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_885 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_887 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component mul_215 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component cmp_850 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_851 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_861 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_871 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_873 is
port (
eq : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in0 : in std_logic_vector(7 downto 0)
);
end component;
component cmp_879 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_880 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component sub_217 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component cmp_863 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end component;
component cmp_868 is
port (
eq : out std_logic;
in1 : in std_logic_vector(23 downto 0);
in0 : in std_logic_vector(23 downto 0)
);
end component;
component cmp_877 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_878 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component sub_218 is
port (
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_220 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component sub_221 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component mul_222 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end component;
component sub_219 is
port (
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end component;
component cmp_962 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_975 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component fsm_224 is
port (
clock : in std_logic;
reset : in std_logic;
out40 : out std_logic;
in2 : in std_logic;
in11 : in std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out152 : out std_logic;
in12 : in std_logic;
out153 : out std_logic;
out154 : out std_logic;
in13 : in std_logic;
out156 : out std_logic;
out157 : out std_logic;
out160 : out std_logic;
out162 : out std_logic;
out165 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out175 : out std_logic;
out177 : out std_logic;
out180 : out std_logic;
out184 : out std_logic;
in14 : in std_logic;
out186 : out std_logic;
out189 : out std_logic;
out191 : out std_logic;
out192 : out std_logic;
out193 : out std_logic;
out197 : out std_logic;
out199 : out std_logic;
out201 : out std_logic;
out202 : out std_logic;
out205 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
in15 : in std_logic;
out221 : out std_logic;
out222 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out231 : out std_logic;
out99 : out std_logic;
in6 : in std_logic;
out92 : out std_logic;
out232 : out std_logic;
in16 : in std_logic;
out234 : out std_logic;
out236 : out std_logic;
out239 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out245 : out std_logic;
out246 : out std_logic;
out247 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
in17 : in std_logic;
out263 : out std_logic;
out264 : out std_logic;
out266 : out std_logic;
in18 : in std_logic;
out267 : out std_logic;
out268 : out std_logic;
out270 : out std_logic;
out273 : out std_logic;
out275 : out std_logic;
out276 : out std_logic;
in19 : in std_logic;
out279 : out std_logic;
in20 : in std_logic;
out281 : out std_logic;
out282 : out std_logic;
in21 : in std_logic;
out283 : out std_logic;
out286 : out std_logic;
out289 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out299 : out std_logic;
out300 : out std_logic;
out304 : out std_logic;
out305 : out std_logic;
in22 : in std_logic;
out306 : out std_logic;
out310 : out std_logic;
out311 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
in23 : in std_logic;
out316 : out std_logic;
out317 : out std_logic;
out320 : out std_logic;
out322 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out328 : out std_logic;
out332 : out std_logic;
out333 : out std_logic;
out334 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out339 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out93 : out std_logic;
out98 : out std_logic;
out85 : out std_logic;
out87 : out std_logic;
out88 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out83 : out std_logic;
out84 : out std_logic;
in5 : in std_logic;
out77 : out std_logic;
out78 : out std_logic;
out71 : out std_logic;
out72 : out std_logic;
in4 : in std_logic;
out65 : out std_logic;
out67 : out std_logic;
out60 : out std_logic;
out64 : out std_logic;
in3 : in std_logic;
out59 : out std_logic;
out53 : out std_logic;
out55 : out std_logic;
out49 : out std_logic;
out44 : out std_logic;
out104 : out std_logic;
out107 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
in7 : in std_logic;
out117 : out std_logic;
out119 : out std_logic;
out122 : out std_logic;
in8 : in std_logic;
out128 : out std_logic;
in9 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
in10 : in std_logic;
out139 : out std_logic;
out143 : out std_logic;
out144 : out std_logic;
out32 : out std_logic;
out35 : out std_logic;
out27 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
in1 : in std_logic;
out15 : out std_logic;
out16 : out std_logic;
out11 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out7 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
out3 : out std_logic;
out4 : out std_logic;
in0 : in std_logic;
in24 : in std_logic;
out346 : out std_logic;
out347 : out std_logic;
out348 : out std_logic;
out349 : out std_logic;
in25 : in std_logic;
out350 : out std_logic;
out351 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out365 : out std_logic;
out366 : out std_logic;
out370 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out375 : out std_logic;
in26 : in std_logic;
out376 : out std_logic;
out378 : out std_logic;
out379 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
in27 : in std_logic;
out384 : out std_logic;
in28 : in std_logic;
out391 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out405 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
in29 : in std_logic;
out412 : out std_logic;
out414 : out std_logic;
out415 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out422 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
in30 : in std_logic;
out428 : out std_logic;
out429 : out std_logic;
out432 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out437 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
in31 : in std_logic;
out443 : out std_logic;
in32 : in std_logic;
out445 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
in33 : in std_logic;
out453 : out std_logic;
out455 : out std_logic;
out458 : out std_logic;
in34 : in std_logic;
out462 : out std_logic;
out464 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out472 : out std_logic;
in35 : in std_logic;
out478 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
in36 : in std_logic;
out491 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out500 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
in37 : in std_logic;
out506 : out std_logic;
out508 : out std_logic;
in38 : in std_logic;
out510 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out515 : out std_logic;
out517 : out std_logic;
out519 : out std_logic;
in39 : in std_logic;
out523 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out530 : out std_logic;
out531 : out std_logic;
out533 : out std_logic;
out534 : out std_logic;
out537 : out std_logic;
out538 : out std_logic;
out549 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out561 : out std_logic;
in40 : in std_logic;
out566 : out std_logic;
out567 : out std_logic;
out568 : out std_logic;
out569 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out574 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
in41 : in std_logic;
out578 : out std_logic;
out581 : out std_logic;
out589 : out std_logic;
out590 : out std_logic;
out595 : out std_logic;
out597 : out std_logic;
out599 : out std_logic;
out601 : out std_logic;
out602 : out std_logic;
out607 : out std_logic;
out610 : out std_logic;
out612 : out std_logic;
in42 : in std_logic;
out614 : out std_logic;
out621 : out std_logic;
out628 : out std_logic;
out635 : out std_logic;
out636 : out std_logic;
out638 : out std_logic;
out640 : out std_logic;
out643 : out std_logic;
out646 : out std_logic;
out649 : out std_logic;
out651 : out std_logic;
out656 : out std_logic;
in43 : in std_logic;
out658 : out std_logic;
out659 : out std_logic;
out661 : out std_logic;
out663 : out std_logic;
out664 : out std_logic;
in44 : in std_logic;
out667 : out std_logic;
out668 : out std_logic;
out670 : out std_logic;
out672 : out std_logic;
out674 : out std_logic;
in45 : in std_logic;
out679 : out std_logic;
out681 : out std_logic;
out683 : out std_logic;
out686 : out std_logic;
out688 : out std_logic;
out690 : out std_logic;
out692 : out std_logic;
out694 : out std_logic;
out696 : out std_logic;
out697 : out std_logic;
out698 : out std_logic;
out699 : out std_logic;
out700 : out std_logic;
out703 : out std_logic;
out704 : out std_logic;
out706 : out std_logic;
out708 : out std_logic;
out710 : out std_logic;
out712 : out std_logic;
out715 : out std_logic;
out718 : out std_logic;
in46 : in std_logic;
out722 : out std_logic;
out724 : out std_logic;
out726 : out std_logic;
out728 : out std_logic;
out731 : out std_logic;
out733 : out std_logic;
out734 : out std_logic;
out737 : out std_logic;
out739 : out std_logic;
out740 : out std_logic;
out743 : out std_logic;
out745 : out std_logic;
out746 : out std_logic;
in47 : in std_logic;
out749 : out std_logic;
out753 : out std_logic;
out755 : out std_logic;
out759 : out std_logic;
in48 : in std_logic;
out762 : out std_logic;
out764 : out std_logic;
out765 : out std_logic;
out767 : out std_logic;
out768 : out std_logic;
in49 : in std_logic;
out772 : out std_logic;
in50 : in std_logic;
out775 : out std_logic;
out776 : out std_logic;
out778 : out std_logic;
out783 : out std_logic;
out784 : out std_logic;
out787 : out std_logic;
out791 : out std_logic;
in51 : in std_logic;
out794 : out std_logic;
out795 : out std_logic;
in52 : in std_logic;
out799 : out std_logic;
out802 : out std_logic;
out806 : out std_logic;
out809 : out std_logic;
out812 : out std_logic;
out815 : out std_logic;
out826 : out std_logic;
out828 : out std_logic;
in53 : in std_logic;
in54 : in std_logic;
out843 : out std_logic;
out848 : out std_logic;
out852 : out std_logic;
in55 : in std_logic;
out855 : out std_logic;
out858 : out std_logic;
in56 : in std_logic;
out860 : out std_logic;
out861 : out std_logic;
out863 : out std_logic;
out866 : out std_logic;
out872 : out std_logic;
in57 : in std_logic;
out874 : out std_logic;
out876 : out std_logic;
out879 : out std_logic;
out882 : out std_logic;
out886 : out std_logic;
out887 : out std_logic;
in58 : in std_logic;
out888 : out std_logic;
out892 : out std_logic;
out894 : out std_logic;
out895 : out std_logic;
out896 : out std_logic;
out901 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out905 : out std_logic;
out907 : out std_logic;
out918 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out923 : out std_logic;
out925 : out std_logic;
out928 : out std_logic;
out929 : out std_logic;
out931 : out std_logic;
out933 : out std_logic;
out936 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out939 : out std_logic;
out942 : out std_logic;
out943 : out std_logic;
out944 : out std_logic;
out947 : out std_logic;
out948 : out std_logic;
out949 : out std_logic;
out951 : out std_logic;
in59 : in std_logic;
out952 : out std_logic;
out953 : out std_logic;
out955 : out std_logic;
out956 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
in60 : in std_logic;
in61 : in std_logic;
out962 : out std_logic;
out963 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
in62 : in std_logic;
out978 : out std_logic;
out979 : out std_logic;
out981 : out std_logic;
out982 : out std_logic;
out985 : out std_logic;
out986 : out std_logic;
out989 : out std_logic;
in63 : in std_logic;
in64 : in std_logic;
in65 : in std_logic;
in66 : in std_logic;
in67 : in std_logic;
in68 : in std_logic;
in69 : in std_logic;
in70 : in std_logic;
in71 : in std_logic;
in72 : in std_logic;
in73 : in std_logic;
in74 : in std_logic;
in75 : in std_logic;
in76 : in std_logic;
in77 : in std_logic;
in78 : in std_logic;
out990 : out std_logic;
out991 : out std_logic;
out993 : out std_logic;
out994 : out std_logic;
out996 : out std_logic;
out997 : out std_logic;
out998 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1005 : out std_logic;
out1006 : out std_logic;
out1007 : out std_logic;
out1009 : out std_logic;
out1011 : out std_logic;
out1012 : out std_logic;
out1013 : out std_logic;
out1014 : out std_logic;
out1015 : out std_logic;
out1016 : out std_logic;
out1018 : out std_logic;
out1019 : out std_logic;
out1021 : out std_logic;
out1022 : out std_logic;
out1024 : out std_logic;
out1026 : out std_logic;
out1027 : out std_logic;
out1029 : out std_logic;
out1030 : out std_logic;
out1032 : out std_logic;
out1033 : out std_logic;
out1035 : out std_logic;
out1036 : out std_logic;
out1037 : out std_logic;
out1057 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1070 : out std_logic;
out1072 : out std_logic;
out1073 : out std_logic;
out1075 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1082 : out std_logic;
out1083 : out std_logic;
out1084 : out std_logic;
out1085 : out std_logic;
out1088 : out std_logic;
out1089 : out std_logic;
out1091 : out std_logic;
out1092 : out std_logic;
out1094 : out std_logic;
out1096 : out std_logic;
out1098 : out std_logic;
out1101 : out std_logic;
out1104 : out std_logic;
out1107 : out std_logic;
out1109 : out std_logic;
out1111 : out std_logic;
out1114 : out std_logic;
out1119 : out std_logic;
out1121 : out std_logic;
out1125 : out std_logic;
out1126 : out std_logic;
out1128 : out std_logic;
out1131 : out std_logic;
out1134 : out std_logic;
out1137 : out std_logic;
out1139 : out std_logic;
out1141 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1155 : out std_logic;
out1158 : out std_logic;
out1160 : out std_logic;
out1164 : out std_logic;
out1166 : out std_logic;
out1169 : out std_logic;
out1171 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1190 : out std_logic;
out1213 : out std_logic;
out1215 : out std_logic;
out1217 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out1223 : out std_logic;
out1228 : out std_logic;
out1229 : out std_logic;
out1231 : out std_logic;
out1235 : out std_logic;
out1236 : out std_logic;
out1240 : out std_logic;
out1243 : out std_logic;
out1250 : out std_logic;
out1252 : out std_logic;
out1253 : out std_logic;
out1258 : out std_logic;
out1262 : out std_logic;
out1266 : out std_logic;
out1269 : out std_logic;
out1275 : out std_logic;
out1278 : out std_logic;
out1279 : out std_logic;
out1284 : out std_logic;
out1286 : out std_logic;
out1287 : out std_logic;
out1289 : out std_logic;
out1290 : out std_logic;
out1292 : out std_logic;
out1293 : out std_logic;
out1295 : out std_logic;
out1298 : out std_logic;
out1301 : out std_logic;
out1302 : out std_logic;
out1303 : out std_logic;
out1308 : out std_logic;
out1309 : out std_logic;
out1311 : out std_logic;
out1318 : out std_logic;
out1319 : out std_logic;
out1320 : out std_logic;
out1323 : out std_logic;
out1324 : out std_logic;
out1326 : out std_logic;
out1327 : out std_logic;
out1329 : out std_logic;
out1337 : out std_logic;
out1339 : out std_logic;
out1340 : out std_logic;
out1341 : out std_logic;
out1344 : out std_logic;
out1346 : out std_logic;
out1349 : out std_logic;
out1353 : out std_logic;
out1356 : out std_logic;
out1362 : out std_logic;
out1363 : out std_logic;
out1364 : out std_logic;
out1365 : out std_logic;
out1366 : out std_logic;
out1368 : out std_logic;
out1370 : out std_logic;
out1375 : out std_logic;
out1378 : out std_logic;
out1381 : out std_logic;
out1383 : out std_logic;
out1387 : out std_logic
);
end component;
component muxb_784 is
port (
in_sel : in std_logic;
out_data : out std_logic_vector(31 downto 0);
in_data0 : in std_logic_vector(31 downto 0);
in_data1 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_964 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_972 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_973 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_974 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_985 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_971 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
component cmp_977 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end component;
-- Declaration of signals
signal sig_clock : std_logic;
signal sig_reset : std_logic;
signal augh_test_159 : std_logic;
signal augh_test_6 : std_logic;
signal augh_test_9 : std_logic;
signal augh_test_10 : std_logic;
signal augh_test_26 : std_logic;
signal augh_test_49 : std_logic;
signal augh_test_52 : std_logic;
signal augh_test_53 : std_logic;
signal augh_test_62 : std_logic;
signal augh_test_67 : std_logic;
signal augh_test_72 : std_logic;
signal augh_test_77 : std_logic;
signal augh_test_83 : std_logic;
signal augh_test_89 : std_logic;
signal augh_test_90 : std_logic;
signal augh_test_94 : std_logic;
signal augh_test_99 : std_logic;
signal augh_test_100 : std_logic;
signal augh_test_101 : std_logic;
signal augh_test_102 : std_logic;
signal augh_test_103 : std_logic;
signal augh_test_104 : std_logic;
signal augh_test_105 : std_logic;
signal augh_test_106 : std_logic;
signal augh_test_107 : std_logic;
signal augh_test_108 : std_logic;
signal augh_test_109 : std_logic;
signal augh_test_111 : std_logic;
signal augh_test_113 : std_logic;
signal augh_test_114 : std_logic;
signal augh_test_115 : std_logic;
signal augh_test_118 : std_logic;
signal augh_test_119 : std_logic;
signal augh_test_120 : std_logic;
signal augh_test_122 : std_logic;
signal augh_test_123 : std_logic;
signal augh_test_124 : std_logic;
signal augh_test_125 : std_logic;
signal augh_test_126 : std_logic;
signal augh_test_127 : std_logic;
signal augh_test_128 : std_logic;
signal augh_test_130 : std_logic;
signal augh_test_131 : std_logic;
signal augh_test_132 : std_logic;
signal augh_test_133 : std_logic;
signal augh_test_134 : std_logic;
signal augh_test_136 : std_logic;
signal augh_test_138 : std_logic;
signal augh_test_142 : std_logic;
signal augh_test_144 : std_logic;
signal augh_test_148 : std_logic;
signal augh_test_150 : std_logic;
signal augh_test_151 : std_logic;
signal augh_test_152 : std_logic;
signal augh_test_154 : std_logic;
signal augh_test_155 : std_logic;
signal augh_test_157 : std_logic;
signal augh_test_158 : std_logic;
signal augh_test_165 : std_logic;
signal augh_test_166 : std_logic;
signal augh_test_167 : std_logic;
signal augh_test_168 : std_logic;
signal sig_start : std_logic;
signal augh_test_171 : std_logic;
signal augh_test_178 : std_logic;
signal augh_test_179 : std_logic;
signal augh_test_180 : std_logic;
signal augh_test_182 : std_logic;
signal augh_test_183 : std_logic;
signal augh_test_184 : std_logic;
signal augh_test_186 : std_logic;
signal augh_test_187 : std_logic;
signal augh_test_188 : std_logic;
signal augh_test_189 : std_logic;
signal augh_test_194 : std_logic;
signal augh_test_196 : std_logic;
signal augh_test_197 : std_logic;
signal sig_990 : std_logic;
signal sig_991 : std_logic;
signal sig_992 : std_logic_vector(31 downto 0);
signal sig_993 : std_logic;
signal sig_994 : std_logic;
signal sig_995 : std_logic;
signal sig_996 : std_logic;
signal sig_997 : std_logic;
signal sig_998 : std_logic;
signal sig_999 : std_logic;
signal sig_1000 : std_logic;
signal sig_1001 : std_logic;
signal sig_1002 : std_logic;
signal sig_1003 : std_logic;
signal sig_1004 : std_logic;
signal sig_1005 : std_logic;
signal sig_1006 : std_logic;
signal sig_1007 : std_logic;
signal sig_1008 : std_logic;
signal sig_1009 : std_logic;
signal sig_1010 : std_logic;
signal sig_1011 : std_logic;
signal sig_1012 : std_logic;
signal sig_1013 : std_logic;
signal sig_1014 : std_logic;
signal sig_1015 : std_logic;
signal sig_1016 : std_logic;
signal sig_1017 : std_logic;
signal sig_1018 : std_logic;
signal sig_1019 : std_logic;
signal sig_1020 : std_logic;
signal sig_1021 : std_logic;
signal sig_1022 : std_logic;
signal sig_1023 : std_logic;
signal sig_1024 : std_logic;
signal sig_1025 : std_logic;
signal sig_1026 : std_logic;
signal sig_1027 : std_logic;
signal sig_1028 : std_logic;
signal sig_1029 : std_logic;
signal sig_1030 : std_logic;
signal sig_1031 : std_logic;
signal sig_1032 : std_logic;
signal sig_1033 : std_logic;
signal sig_1034 : std_logic;
signal sig_1035 : std_logic;
signal sig_1036 : std_logic;
signal sig_1037 : std_logic;
signal sig_1038 : std_logic;
signal sig_1039 : std_logic;
signal sig_1040 : std_logic;
signal sig_1041 : std_logic;
signal sig_1042 : std_logic;
signal sig_1043 : std_logic;
signal sig_1044 : std_logic;
signal sig_1045 : std_logic;
signal sig_1046 : std_logic;
signal sig_1047 : std_logic;
signal sig_1048 : std_logic;
signal sig_1049 : std_logic;
signal sig_1050 : std_logic;
signal sig_1051 : std_logic;
signal sig_1052 : std_logic;
signal sig_1053 : std_logic;
signal sig_1054 : std_logic;
signal sig_1055 : std_logic;
signal sig_1056 : std_logic;
signal sig_1057 : std_logic;
signal sig_1058 : std_logic;
signal sig_1059 : std_logic;
signal sig_1060 : std_logic;
signal sig_1061 : std_logic;
signal sig_1062 : std_logic;
signal sig_1063 : std_logic;
signal sig_1064 : std_logic;
signal sig_1065 : std_logic;
signal sig_1066 : std_logic;
signal sig_1067 : std_logic;
signal sig_1068 : std_logic;
signal sig_1069 : std_logic;
signal sig_1070 : std_logic;
signal sig_1071 : std_logic;
signal sig_1072 : std_logic;
signal sig_1073 : std_logic;
signal sig_1074 : std_logic;
signal sig_1075 : std_logic;
signal sig_1076 : std_logic;
signal sig_1077 : std_logic;
signal sig_1078 : std_logic;
signal sig_1079 : std_logic;
signal sig_1080 : std_logic;
signal sig_1081 : std_logic;
signal sig_1082 : std_logic;
signal sig_1083 : std_logic;
signal sig_1084 : std_logic;
signal sig_1085 : std_logic;
signal sig_1086 : std_logic;
signal sig_1087 : std_logic;
signal sig_1088 : std_logic;
signal sig_1089 : std_logic;
signal sig_1090 : std_logic;
signal sig_1091 : std_logic;
signal sig_1092 : std_logic;
signal sig_1093 : std_logic;
signal sig_1094 : std_logic;
signal sig_1095 : std_logic;
signal sig_1096 : std_logic;
signal sig_1097 : std_logic;
signal sig_1098 : std_logic;
signal sig_1099 : std_logic;
signal sig_1100 : std_logic;
signal sig_1101 : std_logic;
signal sig_1102 : std_logic;
signal sig_1103 : std_logic;
signal sig_1104 : std_logic;
signal sig_1105 : std_logic;
signal sig_1106 : std_logic;
signal sig_1107 : std_logic;
signal sig_1108 : std_logic;
signal sig_1109 : std_logic;
signal sig_1110 : std_logic;
signal sig_1111 : std_logic;
signal sig_1112 : std_logic;
signal sig_1113 : std_logic;
signal sig_1114 : std_logic;
signal sig_1115 : std_logic;
signal sig_1116 : std_logic;
signal sig_1117 : std_logic;
signal sig_1118 : std_logic;
signal sig_1119 : std_logic;
signal sig_1120 : std_logic;
signal sig_1121 : std_logic;
signal sig_1122 : std_logic;
signal sig_1123 : std_logic;
signal sig_1124 : std_logic;
signal sig_1125 : std_logic;
signal sig_1126 : std_logic;
signal sig_1127 : std_logic;
signal sig_1128 : std_logic;
signal sig_1129 : std_logic;
signal sig_1130 : std_logic;
signal sig_1131 : std_logic;
signal sig_1132 : std_logic;
signal sig_1133 : std_logic;
signal sig_1134 : std_logic;
signal sig_1135 : std_logic;
signal sig_1136 : std_logic;
signal sig_1137 : std_logic;
signal sig_1138 : std_logic;
signal sig_1139 : std_logic;
signal sig_1140 : std_logic;
signal sig_1141 : std_logic;
signal sig_1142 : std_logic;
signal sig_1143 : std_logic;
signal sig_1144 : std_logic;
signal sig_1145 : std_logic;
signal sig_1146 : std_logic;
signal sig_1147 : std_logic;
signal sig_1148 : std_logic;
signal sig_1149 : std_logic;
signal sig_1150 : std_logic;
signal sig_1151 : std_logic;
signal sig_1152 : std_logic;
signal sig_1153 : std_logic;
signal sig_1154 : std_logic;
signal sig_1155 : std_logic;
signal sig_1156 : std_logic;
signal sig_1157 : std_logic;
signal sig_1158 : std_logic;
signal sig_1159 : std_logic;
signal sig_1160 : std_logic;
signal sig_1161 : std_logic;
signal sig_1162 : std_logic;
signal sig_1163 : std_logic;
signal sig_1164 : std_logic;
signal sig_1165 : std_logic;
signal sig_1166 : std_logic;
signal sig_1167 : std_logic;
signal sig_1168 : std_logic;
signal sig_1169 : std_logic;
signal sig_1170 : std_logic;
signal sig_1171 : std_logic;
signal sig_1172 : std_logic;
signal sig_1173 : std_logic;
signal sig_1174 : std_logic;
signal sig_1175 : std_logic;
signal sig_1176 : std_logic;
signal sig_1177 : std_logic;
signal sig_1178 : std_logic;
signal sig_1179 : std_logic;
signal sig_1180 : std_logic;
signal sig_1181 : std_logic;
signal sig_1182 : std_logic;
signal sig_1183 : std_logic;
signal sig_1184 : std_logic;
signal sig_1185 : std_logic;
signal sig_1186 : std_logic;
signal sig_1187 : std_logic;
signal sig_1188 : std_logic;
signal sig_1189 : std_logic;
signal sig_1190 : std_logic;
signal sig_1191 : std_logic;
signal sig_1192 : std_logic;
signal sig_1193 : std_logic;
signal sig_1194 : std_logic;
signal sig_1195 : std_logic;
signal sig_1196 : std_logic;
signal sig_1197 : std_logic;
signal sig_1198 : std_logic;
signal sig_1199 : std_logic;
signal sig_1200 : std_logic;
signal sig_1201 : std_logic;
signal sig_1202 : std_logic;
signal sig_1203 : std_logic;
signal sig_1204 : std_logic;
signal sig_1205 : std_logic;
signal sig_1206 : std_logic;
signal sig_1207 : std_logic;
signal sig_1208 : std_logic;
signal sig_1209 : std_logic;
signal sig_1210 : std_logic;
signal sig_1211 : std_logic;
signal sig_1212 : std_logic;
signal sig_1213 : std_logic;
signal sig_1214 : std_logic;
signal sig_1215 : std_logic;
signal sig_1216 : std_logic;
signal sig_1217 : std_logic;
signal sig_1218 : std_logic;
signal sig_1219 : std_logic;
signal sig_1220 : std_logic;
signal sig_1221 : std_logic;
signal sig_1222 : std_logic;
signal sig_1223 : std_logic;
signal sig_1224 : std_logic;
signal sig_1225 : std_logic;
signal sig_1226 : std_logic;
signal sig_1227 : std_logic;
signal sig_1228 : std_logic;
signal sig_1229 : std_logic;
signal sig_1230 : std_logic;
signal sig_1231 : std_logic;
signal sig_1232 : std_logic;
signal sig_1233 : std_logic;
signal sig_1234 : std_logic;
signal sig_1235 : std_logic;
signal sig_1236 : std_logic;
signal sig_1237 : std_logic;
signal sig_1238 : std_logic;
signal sig_1239 : std_logic;
signal sig_1240 : std_logic;
signal sig_1241 : std_logic;
signal sig_1242 : std_logic;
signal sig_1243 : std_logic;
signal sig_1244 : std_logic;
signal sig_1245 : std_logic;
signal sig_1246 : std_logic;
signal sig_1247 : std_logic;
signal sig_1248 : std_logic;
signal sig_1249 : std_logic;
signal sig_1250 : std_logic;
signal sig_1251 : std_logic;
signal sig_1252 : std_logic;
signal sig_1253 : std_logic;
signal sig_1254 : std_logic;
signal sig_1255 : std_logic;
signal sig_1256 : std_logic;
signal sig_1257 : std_logic;
signal sig_1258 : std_logic;
signal sig_1259 : std_logic;
signal sig_1260 : std_logic;
signal sig_1261 : std_logic;
signal sig_1262 : std_logic;
signal sig_1263 : std_logic;
signal sig_1264 : std_logic;
signal sig_1265 : std_logic;
signal sig_1266 : std_logic;
signal sig_1267 : std_logic;
signal sig_1268 : std_logic;
signal sig_1269 : std_logic;
signal sig_1270 : std_logic;
signal sig_1271 : std_logic;
signal sig_1272 : std_logic;
signal sig_1273 : std_logic;
signal sig_1274 : std_logic;
signal sig_1275 : std_logic;
signal sig_1276 : std_logic;
signal sig_1277 : std_logic;
signal sig_1278 : std_logic;
signal sig_1279 : std_logic;
signal sig_1280 : std_logic;
signal sig_1281 : std_logic;
signal sig_1282 : std_logic;
signal sig_1283 : std_logic;
signal sig_1284 : std_logic;
signal sig_1285 : std_logic;
signal sig_1286 : std_logic;
signal sig_1287 : std_logic;
signal sig_1288 : std_logic;
signal sig_1289 : std_logic;
signal sig_1290 : std_logic;
signal sig_1291 : std_logic;
signal sig_1292 : std_logic;
signal sig_1293 : std_logic;
signal sig_1294 : std_logic;
signal sig_1295 : std_logic;
signal sig_1296 : std_logic;
signal sig_1297 : std_logic;
signal sig_1298 : std_logic;
signal sig_1299 : std_logic;
signal sig_1300 : std_logic;
signal sig_1301 : std_logic;
signal sig_1302 : std_logic;
signal sig_1303 : std_logic;
signal sig_1304 : std_logic;
signal sig_1305 : std_logic;
signal sig_1306 : std_logic;
signal sig_1307 : std_logic;
signal sig_1308 : std_logic;
signal sig_1309 : std_logic;
signal sig_1310 : std_logic;
signal sig_1311 : std_logic;
signal sig_1312 : std_logic;
signal sig_1313 : std_logic;
signal sig_1314 : std_logic;
signal sig_1315 : std_logic;
signal sig_1316 : std_logic;
signal sig_1317 : std_logic;
signal sig_1318 : std_logic;
signal sig_1319 : std_logic;
signal sig_1320 : std_logic;
signal sig_1321 : std_logic;
signal sig_1322 : std_logic;
signal sig_1323 : std_logic;
signal sig_1324 : std_logic;
signal sig_1325 : std_logic;
signal sig_1326 : std_logic;
signal sig_1327 : std_logic;
signal sig_1328 : std_logic;
signal sig_1329 : std_logic;
signal sig_1330 : std_logic;
signal sig_1331 : std_logic;
signal sig_1332 : std_logic;
signal sig_1333 : std_logic;
signal sig_1334 : std_logic;
signal sig_1335 : std_logic;
signal sig_1336 : std_logic;
signal sig_1337 : std_logic;
signal sig_1338 : std_logic;
signal sig_1339 : std_logic;
signal sig_1340 : std_logic;
signal sig_1341 : std_logic;
signal sig_1342 : std_logic;
signal sig_1343 : std_logic;
signal sig_1344 : std_logic;
signal sig_1345 : std_logic;
signal sig_1346 : std_logic;
signal sig_1347 : std_logic;
signal sig_1348 : std_logic;
signal sig_1349 : std_logic;
signal sig_1350 : std_logic;
signal sig_1351 : std_logic;
signal sig_1352 : std_logic;
signal sig_1353 : std_logic;
signal sig_1354 : std_logic;
signal sig_1355 : std_logic;
signal sig_1356 : std_logic;
signal sig_1357 : std_logic;
signal sig_1358 : std_logic;
signal sig_1359 : std_logic;
signal sig_1360 : std_logic;
signal sig_1361 : std_logic;
signal sig_1362 : std_logic;
signal sig_1363 : std_logic;
signal sig_1364 : std_logic;
signal sig_1365 : std_logic;
signal sig_1366 : std_logic;
signal sig_1367 : std_logic;
signal sig_1368 : std_logic;
signal sig_1369 : std_logic;
signal sig_1370 : std_logic;
signal sig_1371 : std_logic;
signal sig_1372 : std_logic;
signal sig_1373 : std_logic;
signal sig_1374 : std_logic;
signal sig_1375 : std_logic;
signal sig_1376 : std_logic;
signal sig_1377 : std_logic;
signal sig_1378 : std_logic;
signal sig_1379 : std_logic;
signal sig_1380 : std_logic;
signal sig_1381 : std_logic;
signal sig_1382 : std_logic;
signal sig_1383 : std_logic;
signal sig_1384 : std_logic;
signal sig_1385 : std_logic;
signal sig_1386 : std_logic;
signal sig_1387 : std_logic;
signal sig_1388 : std_logic;
signal sig_1389 : std_logic;
signal sig_1390 : std_logic;
signal sig_1391 : std_logic;
signal sig_1392 : std_logic;
signal sig_1393 : std_logic;
signal sig_1394 : std_logic;
signal sig_1395 : std_logic;
signal sig_1396 : std_logic;
signal sig_1397 : std_logic;
signal sig_1398 : std_logic;
signal sig_1399 : std_logic;
signal sig_1400 : std_logic;
signal sig_1401 : std_logic;
signal sig_1402 : std_logic;
signal sig_1403 : std_logic;
signal sig_1404 : std_logic;
signal sig_1405 : std_logic;
signal sig_1406 : std_logic;
signal sig_1407 : std_logic;
signal sig_1408 : std_logic;
signal sig_1409 : std_logic;
signal sig_1410 : std_logic;
signal sig_1411 : std_logic;
signal sig_1412 : std_logic;
signal sig_1413 : std_logic;
signal sig_1414 : std_logic;
signal sig_1415 : std_logic;
signal sig_1416 : std_logic;
signal sig_1417 : std_logic;
signal sig_1418 : std_logic;
signal sig_1419 : std_logic;
signal sig_1420 : std_logic;
signal sig_1421 : std_logic;
signal sig_1422 : std_logic;
signal sig_1423 : std_logic;
signal sig_1424 : std_logic;
signal sig_1425 : std_logic;
signal sig_1426 : std_logic;
signal sig_1427 : std_logic;
signal sig_1428 : std_logic;
signal sig_1429 : std_logic;
signal sig_1430 : std_logic;
signal sig_1431 : std_logic;
signal sig_1432 : std_logic;
signal sig_1433 : std_logic;
signal sig_1434 : std_logic;
signal sig_1435 : std_logic;
signal sig_1436 : std_logic;
signal sig_1437 : std_logic;
signal sig_1438 : std_logic;
signal sig_1439 : std_logic;
signal sig_1440 : std_logic;
signal sig_1441 : std_logic;
signal sig_1442 : std_logic;
signal sig_1443 : std_logic;
signal sig_1444 : std_logic;
signal sig_1445 : std_logic;
signal sig_1446 : std_logic;
signal sig_1447 : std_logic;
signal sig_1448 : std_logic;
signal sig_1449 : std_logic;
signal sig_1450 : std_logic;
signal sig_1451 : std_logic;
signal sig_1452 : std_logic;
signal sig_1453 : std_logic;
signal sig_1454 : std_logic;
signal sig_1455 : std_logic;
signal sig_1456 : std_logic;
signal sig_1457 : std_logic;
signal sig_1458 : std_logic;
signal sig_1459 : std_logic;
signal sig_1460 : std_logic;
signal sig_1461 : std_logic;
signal sig_1462 : std_logic;
signal sig_1463 : std_logic;
signal sig_1464 : std_logic;
signal sig_1465 : std_logic;
signal sig_1466 : std_logic;
signal sig_1467 : std_logic;
signal sig_1468 : std_logic;
signal sig_1469 : std_logic;
signal sig_1470 : std_logic;
signal sig_1471 : std_logic;
signal sig_1472 : std_logic;
signal sig_1473 : std_logic;
signal sig_1474 : std_logic;
signal sig_1475 : std_logic;
signal sig_1476 : std_logic;
signal sig_1477 : std_logic;
signal sig_1478 : std_logic;
signal sig_1479 : std_logic;
signal sig_1480 : std_logic;
signal sig_1481 : std_logic;
signal sig_1482 : std_logic;
signal sig_1483 : std_logic;
signal sig_1484 : std_logic;
signal sig_1485 : std_logic;
signal sig_1486 : std_logic;
signal sig_1487 : std_logic;
signal sig_1488 : std_logic;
signal sig_1489 : std_logic;
signal sig_1490 : std_logic;
signal sig_1491 : std_logic;
signal sig_1492 : std_logic;
signal sig_1493 : std_logic;
signal sig_1494 : std_logic;
signal sig_1495 : std_logic;
signal sig_1496 : std_logic;
signal sig_1497 : std_logic;
signal sig_1498 : std_logic;
signal sig_1499 : std_logic;
signal sig_1500 : std_logic;
signal sig_1501 : std_logic;
signal sig_1502 : std_logic;
signal sig_1503 : std_logic;
signal sig_1504 : std_logic;
signal sig_1505 : std_logic;
signal sig_1506 : std_logic;
signal sig_1507 : std_logic;
signal sig_1508 : std_logic;
signal sig_1509 : std_logic;
signal sig_1510 : std_logic;
signal sig_1511 : std_logic;
signal sig_1512 : std_logic;
signal sig_1513 : std_logic;
signal sig_1514 : std_logic;
signal sig_1515 : std_logic;
signal sig_1516 : std_logic;
signal sig_1517 : std_logic;
signal sig_1518 : std_logic;
signal sig_1519 : std_logic;
signal sig_1520 : std_logic;
signal sig_1521 : std_logic;
signal sig_1522 : std_logic;
signal sig_1523 : std_logic;
signal sig_1524 : std_logic;
signal sig_1525 : std_logic;
signal sig_1526 : std_logic;
signal sig_1527 : std_logic;
signal sig_1528 : std_logic;
signal sig_1529 : std_logic;
signal sig_1530 : std_logic;
signal sig_1531 : std_logic;
signal sig_1532 : std_logic;
signal sig_1533 : std_logic;
signal sig_1534 : std_logic;
signal sig_1535 : std_logic;
signal sig_1536 : std_logic;
signal sig_1537 : std_logic;
signal sig_1538 : std_logic;
signal sig_1539 : std_logic;
signal sig_1540 : std_logic;
signal sig_1541 : std_logic;
signal sig_1542 : std_logic;
signal sig_1543 : std_logic;
signal sig_1544 : std_logic;
signal sig_1545 : std_logic;
signal sig_1546 : std_logic;
signal sig_1547 : std_logic;
signal sig_1548 : std_logic;
signal sig_1549 : std_logic;
signal sig_1550 : std_logic;
signal sig_1551 : std_logic;
signal sig_1552 : std_logic;
signal sig_1553 : std_logic;
signal sig_1554 : std_logic;
signal sig_1555 : std_logic;
signal sig_1556 : std_logic;
signal sig_1557 : std_logic;
signal sig_1558 : std_logic;
signal sig_1559 : std_logic;
signal sig_1560 : std_logic;
signal sig_1561 : std_logic;
signal sig_1562 : std_logic;
signal sig_1563 : std_logic;
signal sig_1564 : std_logic;
signal sig_1565 : std_logic;
signal sig_1566 : std_logic;
signal sig_1567 : std_logic;
signal sig_1568 : std_logic;
signal sig_1569 : std_logic;
signal sig_1570 : std_logic;
signal sig_1571 : std_logic;
signal sig_1572 : std_logic;
signal sig_1573 : std_logic;
signal sig_1574 : std_logic;
signal sig_1575 : std_logic;
signal sig_1576 : std_logic;
signal sig_1577 : std_logic;
signal sig_1578 : std_logic;
signal sig_1579 : std_logic;
signal sig_1580 : std_logic;
signal sig_1581 : std_logic;
signal sig_1582 : std_logic;
signal sig_1583 : std_logic;
signal sig_1584 : std_logic;
signal sig_1585 : std_logic_vector(40 downto 0);
signal sig_1586 : std_logic;
signal sig_1587 : std_logic_vector(40 downto 0);
signal sig_1588 : std_logic_vector(40 downto 0);
signal sig_1589 : std_logic;
signal sig_1590 : std_logic_vector(40 downto 0);
signal sig_1591 : std_logic;
signal sig_1592 : std_logic_vector(40 downto 0);
signal sig_1593 : std_logic;
signal sig_1594 : std_logic;
signal sig_1595 : std_logic;
signal sig_1596 : std_logic_vector(40 downto 0);
signal sig_1597 : std_logic;
signal sig_1598 : std_logic;
signal sig_1599 : std_logic;
signal sig_1600 : std_logic_vector(40 downto 0);
signal sig_1601 : std_logic;
signal sig_1602 : std_logic;
signal sig_1603 : std_logic;
signal sig_1604 : std_logic;
signal sig_1605 : std_logic;
signal sig_1606 : std_logic;
signal sig_1607 : std_logic;
signal sig_1608 : std_logic;
signal sig_1609 : std_logic_vector(38 downto 0);
signal sig_1610 : std_logic_vector(38 downto 0);
signal sig_1611 : std_logic_vector(24 downto 0);
signal sig_1612 : std_logic_vector(38 downto 0);
signal sig_1613 : std_logic_vector(31 downto 0);
signal sig_1614 : std_logic_vector(40 downto 0);
signal sig_1615 : std_logic;
signal sig_1616 : std_logic;
signal sig_1617 : std_logic;
signal sig_1618 : std_logic;
signal sig_1619 : std_logic_vector(40 downto 0);
signal sig_1620 : std_logic;
signal sig_1621 : std_logic_vector(40 downto 0);
signal sig_1622 : std_logic;
signal sig_1623 : std_logic;
signal sig_1624 : std_logic_vector(40 downto 0);
signal sig_1625 : std_logic;
signal sig_1626 : std_logic_vector(31 downto 0);
signal sig_1627 : std_logic_vector(40 downto 0);
signal sig_1628 : std_logic_vector(40 downto 0);
signal sig_1629 : std_logic_vector(31 downto 0);
signal sig_1630 : std_logic_vector(5 downto 0);
signal sig_1631 : std_logic_vector(7 downto 0);
signal sig_1632 : std_logic_vector(31 downto 0);
signal sig_1633 : std_logic_vector(31 downto 0);
signal sig_1634 : std_logic_vector(31 downto 0);
signal sig_1635 : std_logic_vector(31 downto 0);
signal sig_1636 : std_logic_vector(31 downto 0);
signal sig_1637 : std_logic_vector(31 downto 0);
signal sig_1638 : std_logic_vector(20 downto 0);
signal sig_1639 : std_logic_vector(31 downto 0);
signal sig_1640 : std_logic_vector(31 downto 0);
signal sig_1641 : std_logic_vector(31 downto 0);
signal sig_1642 : std_logic_vector(31 downto 0);
signal sig_1643 : std_logic_vector(31 downto 0);
signal sig_1644 : std_logic_vector(7 downto 0);
signal sig_1645 : std_logic_vector(5 downto 0);
signal sig_1646 : std_logic_vector(7 downto 0);
signal sig_1647 : std_logic_vector(31 downto 0);
signal sig_1648 : std_logic_vector(31 downto 0);
signal sig_1649 : std_logic_vector(8 downto 0);
signal sig_1650 : std_logic_vector(8 downto 0);
signal sig_1651 : std_logic_vector(31 downto 0);
signal sig_1652 : std_logic_vector(31 downto 0);
signal sig_1653 : std_logic_vector(8 downto 0);
signal sig_1654 : std_logic_vector(8 downto 0);
signal sig_1655 : std_logic_vector(31 downto 0);
signal sig_1656 : std_logic_vector(31 downto 0);
signal sig_1657 : std_logic_vector(31 downto 0);
signal sig_1658 : std_logic_vector(31 downto 0);
signal sig_1659 : std_logic_vector(31 downto 0);
signal sig_1660 : std_logic_vector(31 downto 0);
signal sig_1661 : std_logic_vector(31 downto 0);
signal sig_1662 : std_logic;
signal sig_1663 : std_logic_vector(1 downto 0);
signal sig_1664 : std_logic_vector(7 downto 0);
signal sig_1665 : std_logic_vector(7 downto 0);
signal sig_1666 : std_logic_vector(40 downto 0);
signal sig_1667 : std_logic_vector(40 downto 0);
signal sig_1668 : std_logic_vector(40 downto 0);
signal sig_1669 : std_logic;
signal sig_1670 : std_logic;
signal sig_1671 : std_logic_vector(31 downto 0);
signal sig_1672 : std_logic_vector(31 downto 0);
signal sig_1673 : std_logic_vector(40 downto 0);
signal sig_1674 : std_logic_vector(40 downto 0);
signal sig_1675 : std_logic_vector(40 downto 0);
signal sig_1676 : std_logic_vector(40 downto 0);
signal sig_1677 : std_logic_vector(31 downto 0);
signal sig_1678 : std_logic_vector(31 downto 0);
signal sig_1679 : std_logic_vector(40 downto 0);
signal sig_1680 : std_logic_vector(31 downto 0);
signal sig_1681 : std_logic_vector(31 downto 0);
signal sig_1682 : std_logic_vector(31 downto 0);
signal sig_1683 : std_logic_vector(31 downto 0);
signal sig_1684 : std_logic_vector(31 downto 0);
signal sig_1685 : std_logic_vector(31 downto 0);
signal sig_1686 : std_logic_vector(31 downto 0);
signal sig_1687 : std_logic_vector(31 downto 0);
signal sig_1688 : std_logic_vector(24 downto 0);
signal sig_1689 : std_logic_vector(40 downto 0);
signal sig_1690 : std_logic_vector(31 downto 0);
signal sig_1691 : std_logic_vector(9 downto 0);
signal sig_1692 : std_logic_vector(8 downto 0);
signal sig_1693 : std_logic_vector(14 downto 0);
signal sig_1694 : std_logic_vector(14 downto 0);
signal sig_1695 : std_logic_vector(6 downto 0);
signal sig_1696 : std_logic_vector(6 downto 0);
signal sig_1697 : std_logic_vector(6 downto 0);
signal sig_1698 : std_logic_vector(6 downto 0);
signal sig_1699 : std_logic_vector(6 downto 0);
signal sig_1700 : std_logic_vector(6 downto 0);
signal sig_1701 : std_logic_vector(6 downto 0);
signal sig_1702 : std_logic_vector(6 downto 0);
signal sig_1703 : std_logic_vector(9 downto 0);
signal sig_1704 : std_logic_vector(6 downto 0);
signal sig_1705 : std_logic_vector(9 downto 0);
signal sig_1706 : std_logic_vector(6 downto 0);
signal sig_1707 : std_logic_vector(7 downto 0);
signal sig_1708 : std_logic_vector(31 downto 0);
signal sig_1709 : std_logic_vector(31 downto 0);
signal sig_1710 : std_logic_vector(31 downto 0);
signal sig_1711 : std_logic_vector(31 downto 0);
signal sig_1712 : std_logic_vector(31 downto 0);
signal sig_1713 : std_logic_vector(31 downto 0);
signal sig_1714 : std_logic_vector(31 downto 0);
signal sig_1715 : std_logic_vector(31 downto 0);
signal sig_1716 : std_logic_vector(31 downto 0);
-- Other inlined components
signal mux_967 : std_logic_vector(31 downto 0);
signal and_976 : std_logic;
signal and_982 : std_logic_vector(31 downto 0);
signal and_983 : std_logic_vector(27 downto 0);
signal and_984 : std_logic_vector(31 downto 0);
signal mux_689 : std_logic_vector(31 downto 0);
signal mux_690 : std_logic_vector(6 downto 0);
signal mux_691 : std_logic_vector(6 downto 0);
signal and_853 : std_logic_vector(31 downto 0);
signal izigzagmatrix_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_233 : std_logic_vector(31 downto 0);
signal izigzagmatrix_out_idx : std_logic_vector(31 downto 0) := (others => '0');
signal iquantize_qidx : std_logic_vector(1 downto 0) := (others => '0');
signal write8_u8 : std_logic_vector(7 downto 0) := (others => '0');
signal p_jinfo_image_height : std_logic_vector(15 downto 0) := (others => '0');
signal p_jinfo_image_width : std_logic_vector(15 downto 0) := (others => '0');
signal mux_671 : std_logic_vector(31 downto 0);
signal p_jinfo_num_components : std_logic_vector(7 downto 0) := (others => '0');
signal p_jinfo_smp_fact : std_logic_vector(1 downto 0) := (others => '0');
signal mux_665 : std_logic_vector(1 downto 0);
signal mux_663 : std_logic_vector(31 downto 0);
signal mux_664 : std_logic_vector(1 downto 0);
signal mux_659 : std_logic_vector(31 downto 0);
signal mux_660 : std_logic_vector(1 downto 0);
signal mux_661 : std_logic_vector(1 downto 0);
signal mux_652 : std_logic_vector(12 downto 0);
signal mux_648 : std_logic_vector(31 downto 0);
signal mux_633 : std_logic_vector(31 downto 0);
signal mux_622 : std_logic_vector(31 downto 0);
signal mux_614 : std_logic_vector(31 downto 0);
signal mux_616 : std_logic_vector(31 downto 0);
signal p_jinfo_mcuwidth : std_logic_vector(31 downto 0) := (others => '0');
signal mux_602 : std_logic_vector(31 downto 0);
signal p_jinfo_mcuheight : std_logic_vector(31 downto 0) := (others => '0');
signal mux_600 : std_logic_vector(31 downto 0);
signal p_jinfo_nummcu : std_logic_vector(31 downto 0) := (others => '0');
signal i_jinfo_jpeg_data : std_logic_vector(31 downto 0) := (others => '0');
signal mux_593 : std_logic_vector(31 downto 0);
signal curhuffreadbuf_idx : std_logic_vector(31 downto 0) := (others => '0');
signal mux_587 : std_logic_vector(31 downto 0);
signal outdata_image_width : std_logic_vector(7 downto 0) := (others => '0');
signal mux_585 : std_logic_vector(15 downto 0);
signal outdata_image_height : std_logic_vector(7 downto 0) := (others => '0');
signal mux_580 : std_logic_vector(7 downto 0);
signal mux_569 : std_logic_vector(7 downto 0);
signal mux_567 : std_logic_vector(31 downto 0);
signal mux_568 : std_logic_vector(7 downto 0);
signal mux_563 : std_logic_vector(8 downto 0);
signal mux_565 : std_logic_vector(8 downto 0);
signal mux_561 : std_logic_vector(31 downto 0);
signal mux_562 : std_logic_vector(8 downto 0);
signal mux_557 : std_logic_vector(31 downto 0);
signal mux_558 : std_logic_vector(5 downto 0);
signal mux_559 : std_logic_vector(5 downto 0);
signal mux_555 : std_logic_vector(31 downto 0);
signal mux_551 : std_logic_vector(31 downto 0);
signal mux_553 : std_logic_vector(31 downto 0);
signal mux_549 : std_logic_vector(31 downto 0);
signal mux_545 : std_logic_vector(31 downto 0);
signal mux_547 : std_logic_vector(31 downto 0);
signal mux_543 : std_logic_vector(31 downto 0);
signal mux_731 : std_logic_vector(7 downto 0);
signal mux_727 : std_logic_vector(6 downto 0);
signal mux_723 : std_logic_vector(9 downto 0);
signal mux_719 : std_logic_vector(6 downto 0);
signal mux_539 : std_logic_vector(31 downto 0);
signal mux_541 : std_logic_vector(31 downto 0);
signal mux_537 : std_logic_vector(31 downto 0);
signal mux_533 : std_logic_vector(31 downto 0);
signal mux_535 : std_logic_vector(31 downto 0);
signal mux_715 : std_logic_vector(9 downto 0);
signal mux_711 : std_logic;
signal mux_705 : std_logic_vector(31 downto 0);
signal mux_706 : std_logic_vector(6 downto 0);
signal mux_707 : std_logic_vector(6 downto 0);
signal mux_531 : std_logic_vector(31 downto 0);
signal mux_529 : std_logic_vector(31 downto 0);
signal mux_695 : std_logic;
signal mux_524 : std_logic_vector(4 downto 0);
signal mux_521 : std_logic_vector(31 downto 0);
signal readbuf_idx : std_logic_vector(31 downto 0) := (others => '0');
signal read_byte : std_logic_vector(7 downto 0) := (others => '0');
signal read_word : std_logic_vector(15 downto 0) := (others => '0');
signal read_word_c : std_logic_vector(7 downto 0) := (others => '0');
signal mux_519 : std_logic_vector(31 downto 0);
signal mux_517 : std_logic_vector(7 downto 0);
signal next_marker : std_logic_vector(7 downto 0) := (others => '0');
signal next_marker_c : std_logic_vector(7 downto 0) := (others => '0');
signal get_sof_ci : std_logic_vector(31 downto 0) := (others => '0');
signal mux_507 : std_logic_vector(31 downto 0);
signal mux_505 : std_logic_vector(31 downto 0);
signal get_sof_i_comp_info_id : std_logic_vector(1 downto 0) := (others => '0');
signal mux_501 : std_logic_vector(31 downto 0);
signal get_sof_i_comp_info_h_samp_factor : std_logic_vector(1 downto 0) := (others => '0');
signal get_sof_i_comp_info_quant_tbl_no : std_logic_vector(1 downto 0) := (others => '0');
signal mux_492 : std_logic_vector(31 downto 0);
signal mux_488 : std_logic_vector(31 downto 0);
signal mux_490 : std_logic_vector(31 downto 0);
signal get_sos_num_comp : std_logic_vector(7 downto 0) := (others => '0');
signal mux_486 : std_logic_vector(31 downto 0);
signal get_sos_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_482 : std_logic_vector(31 downto 0);
signal mux_484 : std_logic_vector(31 downto 0);
signal get_sos_c : std_logic := '0';
signal mux_480 : std_logic_vector(31 downto 0);
signal get_sos_cc : std_logic_vector(7 downto 0) := (others => '0');
signal mux_476 : std_logic_vector(31 downto 0);
signal mux_478 : std_logic_vector(8 downto 0);
signal get_sos_ci : std_logic_vector(31 downto 0) := (others => '0');
signal get_sos_j : std_logic_vector(31 downto 0) := (others => '0');
signal get_sos_i_comp_info_dc_tbl_no : std_logic_vector(1 downto 0) := (others => '0');
signal get_dht_length : std_logic_vector(31 downto 0) := (others => '0');
signal get_dht_index : std_logic := '0';
signal mux_459 : std_logic_vector(31 downto 0);
signal get_dht_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_455 : std_logic_vector(31 downto 0);
signal mux_457 : std_logic_vector(31 downto 0);
signal get_dht_count : std_logic_vector(31 downto 0) := (others => '0');
signal mux_453 : std_logic_vector(31 downto 0);
signal mux_449 : std_logic_vector(31 downto 0);
signal mux_451 : std_logic_vector(31 downto 0);
signal get_dht_is_ac : std_logic := '0';
signal get_dqt_length : std_logic_vector(31 downto 0) := (others => '0');
signal mux_447 : std_logic_vector(31 downto 0);
signal get_dqt_prec : std_logic_vector(3 downto 0) := (others => '0');
signal mux_443 : std_logic_vector(31 downto 0);
signal mux_445 : std_logic_vector(8 downto 0);
signal get_dqt_num : std_logic_vector(1 downto 0) := (others => '0');
signal get_dqt_i : std_logic_vector(31 downto 0) := (others => '0');
signal get_dqt_tmp : std_logic_vector(15 downto 0) := (others => '0');
signal read_markers_unread_marker : std_logic_vector(7 downto 0) := (others => '0');
signal read_markers_sow_soi : std_logic := '0';
signal mux_430 : std_logic_vector(31 downto 0);
signal mux_422 : std_logic_vector(31 downto 0);
signal mux_424 : std_logic_vector(31 downto 0);
signal chenidct_i : std_logic_vector(31 downto 0) := (others => '0');
signal mux_416 : std_logic_vector(31 downto 0);
signal chenidct_aidx : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_a0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_410 : std_logic_vector(31 downto 0);
signal chenidct_a1 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_408 : std_logic_vector(31 downto 0);
signal chenidct_a2 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_a3 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_b0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_398 : std_logic_vector(31 downto 0);
signal mux_400 : std_logic_vector(31 downto 0);
signal chenidct_b1 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_b2 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_392 : std_logic_vector(31 downto 0);
signal mux_394 : std_logic_vector(31 downto 0);
signal chenidct_b3 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c1 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c2 : std_logic_vector(31 downto 0) := (others => '0');
signal chenidct_c3 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_378 : std_logic_vector(7 downto 0);
signal mux_379 : std_logic_vector(9 downto 0);
signal mux_375 : std_logic_vector(1 downto 0);
signal mux_373 : std_logic_vector(1 downto 0);
signal current_read_byte : std_logic_vector(31 downto 0) := (others => '0');
signal mux_365 : std_logic_vector(31 downto 0);
signal mux_367 : std_logic_vector(31 downto 0);
signal read_position : std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
signal pgetc : std_logic_vector(7 downto 0) := (others => '0');
signal pgetc_temp : std_logic_vector(7 downto 0) := (others => '0');
signal buf_getb : std_logic := '0';
signal buf_getv : std_logic_vector(31 downto 0) := (others => '0');
signal buf_getv_n : std_logic_vector(31 downto 0) := (others => '0');
signal mux_363 : std_logic_vector(31 downto 0);
signal buf_getv_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_359 : std_logic_vector(31 downto 0);
signal mux_361 : std_logic_vector(31 downto 0);
signal buf_getv_rv : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_tbl_no : std_logic := '0';
signal huff_make_dhuff_tb_ac_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_i_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_ac_j : std_logic_vector(31 downto 0) := (others => '0');
signal mux_347 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_ac_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_345 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_ac_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_341 : std_logic_vector(2 downto 0);
signal mux_343 : std_logic_vector(1 downto 0);
signal huff_make_dhuff_tb_ac_size : std_logic_vector(31 downto 0) := (others => '0');
signal mux_339 : std_logic_vector(2 downto 0);
signal huff_make_dhuff_tb_ac_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_335 : std_logic_vector(31 downto 0);
signal mux_337 : std_logic_vector(2 downto 0);
signal mux_333 : std_logic_vector(31 downto 0);
signal mux_331 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc : std_logic_vector(31 downto 0) := (others => '0');
signal huff_make_dhuff_tb_dc_tbl_no : std_logic := '0';
signal huff_make_dhuff_tb_dc_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0');
signal mux_323 : std_logic_vector(5 downto 0);
signal huff_make_dhuff_tb_dc_i_c0 : std_logic_vector(31 downto 0) := (others => '0');
signal mux_320 : std_logic_vector(31 downto 0);
signal mux_322 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc_j : std_logic_vector(31 downto 0) := (others => '0');
signal mux_317 : std_logic_vector(1 downto 0);
signal huff_make_dhuff_tb_dc_p : std_logic_vector(31 downto 0) := (others => '0');
signal mux_314 : std_logic_vector(31 downto 0);
signal mux_315 : std_logic_vector(31 downto 0);
signal mux_316 : std_logic_vector(31 downto 0);
signal huff_make_dhuff_tb_dc_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_313 : std_logic_vector(8 downto 0);
signal huff_make_dhuff_tb_dc_size : std_logic_vector(31 downto 0) := (others => '0');
signal mux_308 : std_logic_vector(2 downto 0);
signal huff_make_dhuff_tb_dc_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_306 : std_logic_vector(40 downto 0);
signal mux_307 : std_logic_vector(40 downto 0);
signal mux_302 : std_logic_vector(40 downto 0);
signal mux_303 : std_logic_vector(40 downto 0);
signal decodehuffman_ac : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_ac_tbl_no : std_logic := '0';
signal mux_294 : std_logic_vector(1 downto 0);
signal decodehuffman_ac_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0');
signal mux_290 : std_logic_vector(40 downto 0);
signal mux_291 : std_logic_vector(40 downto 0);
signal mux_292 : std_logic_vector(31 downto 0);
signal decodehuffman_ac_code : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_ac_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_286 : std_logic_vector(31 downto 0);
signal decodehuffman_ac_p : std_logic_vector(8 downto 0) := (others => '0');
signal decodehuffman_dc : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffman_dc_tbl_no : std_logic := '0';
signal decodehuffman_dc_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0');
signal mux_275 : std_logic_vector(31 downto 0);
signal decodehuffman_dc_code : std_logic_vector(31 downto 0) := (others => '0');
signal mux_272 : std_logic_vector(38 downto 0);
signal mux_274 : std_logic_vector(31 downto 0);
signal decodehuffman_dc_l : std_logic_vector(31 downto 0) := (others => '0');
signal mux_271 : std_logic_vector(38 downto 0);
signal decodehuffman_dc_p : std_logic_vector(8 downto 0) := (others => '0');
signal decodehuffmcu_bufdim1 : std_logic_vector(1 downto 0) := (others => '0');
signal mux_266 : std_logic_vector(38 downto 0);
signal mux_265 : std_logic_vector(38 downto 0);
signal decodehuffmcu_s : std_logic_vector(31 downto 0) := (others => '0');
signal mux_260 : std_logic_vector(38 downto 0);
signal mux_261 : std_logic_vector(38 downto 0);
signal mux_262 : std_logic_vector(31 downto 0);
signal decodehuffmcu_diff : std_logic_vector(31 downto 0) := (others => '0');
signal mux_257 : std_logic_vector(31 downto 0);
signal decodehuffmcu_tbl_no : std_logic := '0';
signal decodehuffmcu_i : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffmcu_k : std_logic_vector(31 downto 0) := (others => '0');
signal decodehuffmcu_n : std_logic_vector(27 downto 0) := (others => '0');
signal writeoneblock_outidx : std_logic_vector(1 downto 0) := (others => '0');
signal writeoneblock_indim1 : std_logic_vector(1 downto 0) := (others => '0');
signal writeoneblock_width : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_height : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_voffs : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_hoffs : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_i : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_e : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_inidx : std_logic_vector(31 downto 0) := (others => '0');
signal writeoneblock_diff : std_logic_vector(12 downto 0) := (others => '0');
signal writeblock_i : std_logic_vector(1 downto 0) := (others => '0');
signal write4blocks_i : std_logic_vector(1 downto 0) := (others => '0');
signal write4blocks_voffs : std_logic_vector(31 downto 0) := (others => '0');
signal write4blocks_hoffs : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_p : std_logic_vector(1 downto 0) := (others => '0');
signal yuvtorgb_yidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_uidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_vidx : std_logic_vector(2 downto 0) := (others => '0');
signal yuvtorgb_r : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_g : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_b : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_y : std_logic_vector(23 downto 0) := (others => '0');
signal yuvtorgb_u : std_logic_vector(30 downto 0) := (others => '0');
signal yuvtorgb_v : std_logic_vector(31 downto 0) := (others => '0');
signal yuvtorgb_i : std_logic_vector(31 downto 0) := (others => '0');
signal decode_block_comp_no : std_logic_vector(1 downto 0) := (others => '0');
signal decode_block_out_buf_idx : std_logic_vector(2 downto 0) := (others => '0');
signal decode_block_in_buf_idx : std_logic_vector(1 downto 0) := (others => '0');
signal decode_start_i : std_logic_vector(31 downto 0) := (others => '0');
signal decode_start_currentmcu : std_logic_vector(31 downto 0) := (others => '0');
signal nand_786 : std_logic;
signal or_845 : std_logic_vector(31 downto 0);
signal or_854 : std_logic_vector(31 downto 0);
signal or_866 : std_logic_vector(31 downto 0);
signal jpeg2bmp_main_i : std_logic_vector(31 downto 0) := (others => '0');
signal jpeg2bmp_main_j : std_logic_vector(31 downto 0) := (others => '0');
signal read8_ret0_195 : std_logic_vector(7 downto 0) := (others => '0');
signal and_785 : std_logic;
signal and_801 : std_logic_vector(31 downto 0);
signal mux_761 : std_logic_vector(8 downto 0);
signal mux_782 : std_logic_vector(31 downto 0);
signal or_802 : std_logic_vector(23 downto 0);
signal and_803 : std_logic_vector(31 downto 0);
signal mux_822 : std_logic_vector(31 downto 0);
signal mux_823 : std_logic_vector(31 downto 0);
signal mux_776 : std_logic_vector(31 downto 0);
signal mux_820 : std_logic_vector(31 downto 0);
signal mux_824 : std_logic_vector(31 downto 0);
signal mux_825 : std_logic_vector(31 downto 0);
signal mux_760 : std_logic_vector(31 downto 0);
signal and_789 : std_logic;
signal mux_759 : std_logic_vector(5 downto 0);
signal mux_768 : std_logic_vector(31 downto 0);
signal mux_757 : std_logic_vector(7 downto 0);
signal mux_773 : std_logic_vector(7 downto 0);
signal mux_762 : std_logic_vector(31 downto 0);
signal mux_766 : std_logic_vector(31 downto 0);
signal mux_781 : std_logic_vector(31 downto 0);
signal mux_797 : std_logic_vector(31 downto 0);
signal mux_821 : std_logic_vector(31 downto 0);
signal mux_826 : std_logic_vector(31 downto 0);
signal mux_778 : std_logic_vector(31 downto 0);
signal mux_827 : std_logic_vector(31 downto 0);
signal mux_815 : std_logic_vector(31 downto 0);
signal mux_798 : std_logic_vector(31 downto 0);
signal mux_816 : std_logic_vector(31 downto 0);
signal mux_817 : std_logic_vector(31 downto 0);
signal mux_777 : std_logic_vector(31 downto 0);
signal mux_819 : std_logic_vector(31 downto 0);
signal mux_783 : std_logic_vector(31 downto 0);
signal mux_795 : std_logic_vector(31 downto 0);
signal mux_796 : std_logic_vector(31 downto 0);
signal mux_805 : std_logic_vector(31 downto 0);
signal mux_806 : std_logic_vector(31 downto 0);
signal mux_807 : std_logic_vector(31 downto 0);
signal mux_808 : std_logic_vector(31 downto 0);
signal mux_809 : std_logic_vector(31 downto 0);
signal mux_810 : std_logic_vector(31 downto 0);
signal mux_811 : std_logic_vector(31 downto 0);
signal mux_812 : std_logic_vector(31 downto 0);
signal mux_813 : std_logic_vector(31 downto 0);
signal mux_814 : std_logic_vector(31 downto 0);
signal mux_818 : std_logic_vector(31 downto 0);
signal mux_828 : std_logic_vector(31 downto 0);
signal mux_829 : std_logic_vector(31 downto 0);
signal mux_830 : std_logic_vector(31 downto 0);
signal mux_831 : std_logic_vector(31 downto 0);
signal mux_832 : std_logic_vector(31 downto 0);
signal mux_836 : std_logic_vector(31 downto 0);
signal mux_837 : std_logic_vector(31 downto 0);
signal mux_839 : std_logic_vector(31 downto 0);
signal mux_840 : std_logic_vector(31 downto 0);
signal mux_841 : std_logic_vector(31 downto 0);
signal mux_842 : std_logic_vector(31 downto 0);
signal mux_843 : std_logic_vector(31 downto 0);
signal mux_856 : std_logic_vector(31 downto 0);
signal and_864 : std_logic;
signal mux_870 : std_logic_vector(31 downto 0);
signal mux_872 : std_logic_vector(1 downto 0);
signal mux_875 : std_logic_vector(31 downto 0);
signal mux_891 : std_logic_vector(31 downto 0);
signal mux_892 : std_logic_vector(31 downto 0);
signal mux_893 : std_logic_vector(31 downto 0);
signal mux_894 : std_logic_vector(31 downto 0);
signal mux_895 : std_logic_vector(31 downto 0);
signal mux_896 : std_logic_vector(31 downto 0);
signal mux_897 : std_logic_vector(31 downto 0);
signal mux_898 : std_logic_vector(31 downto 0);
signal mux_899 : std_logic_vector(31 downto 0);
signal mux_900 : std_logic_vector(31 downto 0);
signal mux_901 : std_logic_vector(31 downto 0);
signal mux_902 : std_logic_vector(31 downto 0);
signal mux_903 : std_logic_vector(31 downto 0);
signal mux_904 : std_logic_vector(31 downto 0);
signal mux_905 : std_logic_vector(31 downto 0);
signal mux_906 : std_logic_vector(31 downto 0);
signal mux_907 : std_logic_vector(31 downto 0);
signal mux_908 : std_logic_vector(31 downto 0);
signal mux_917 : std_logic_vector(31 downto 0);
signal mux_918 : std_logic_vector(31 downto 0);
signal mux_924 : std_logic_vector(31 downto 0);
signal mux_925 : std_logic_vector(31 downto 0);
signal mux_928 : std_logic_vector(31 downto 0);
signal mux_929 : std_logic_vector(31 downto 0);
signal mux_931 : std_logic_vector(31 downto 0);
signal mux_932 : std_logic_vector(31 downto 0);
signal mux_934 : std_logic_vector(31 downto 0);
signal mux_935 : std_logic_vector(31 downto 0);
signal mux_936 : std_logic_vector(31 downto 0);
signal mux_937 : std_logic_vector(31 downto 0);
signal mux_938 : std_logic_vector(31 downto 0);
signal mux_939 : std_logic_vector(31 downto 0);
signal mux_941 : std_logic_vector(31 downto 0);
signal mux_944 : std_logic_vector(31 downto 0);
signal mux_945 : std_logic_vector(31 downto 0);
signal mux_946 : std_logic_vector(31 downto 0);
signal mux_833 : std_logic_vector(31 downto 0);
signal mux_834 : std_logic_vector(31 downto 0);
signal mux_835 : std_logic_vector(31 downto 0);
signal mux_838 : std_logic_vector(31 downto 0);
signal mux_844 : std_logic_vector(31 downto 0);
signal mux_857 : std_logic_vector(31 downto 0);
signal mux_858 : std_logic_vector(31 downto 0);
signal mux_859 : std_logic_vector(31 downto 0);
signal mux_874 : std_logic_vector(31 downto 0);
signal mux_888 : std_logic_vector(31 downto 0);
signal mux_889 : std_logic_vector(31 downto 0);
signal mux_913 : std_logic_vector(31 downto 0);
signal mux_914 : std_logic_vector(31 downto 0);
signal mux_915 : std_logic_vector(31 downto 0);
signal mux_916 : std_logic_vector(31 downto 0);
signal mux_933 : std_logic_vector(31 downto 0);
signal mux_940 : std_logic_vector(31 downto 0);
signal mux_942 : std_logic_vector(31 downto 0);
signal and_867 : std_logic;
signal mux_909 : std_logic_vector(31 downto 0);
signal mux_910 : std_logic_vector(31 downto 0);
signal mux_911 : std_logic_vector(31 downto 0);
signal mux_920 : std_logic_vector(31 downto 0);
signal mux_921 : std_logic_vector(31 downto 0);
signal mux_926 : std_logic_vector(31 downto 0);
signal mux_927 : std_logic_vector(31 downto 0);
signal mux_943 : std_logic_vector(31 downto 0);
signal mux_886 : std_logic;
signal mux_922 : std_logic_vector(31 downto 0);
signal mux_923 : std_logic_vector(31 downto 0);
signal mux_930 : std_logic_vector(31 downto 0);
signal mux_987 : std_logic_vector(31 downto 0);
signal and_860 : std_logic_vector(31 downto 0);
signal and_881 : std_logic_vector(31 downto 0);
signal and_884 : std_logic_vector(31 downto 0);
signal mux_890 : std_logic_vector(31 downto 0);
signal mux_912 : std_logic_vector(31 downto 0);
signal mux_919 : std_logic_vector(31 downto 0);
signal mux_948 : std_logic_vector(31 downto 0);
signal mux_949 : std_logic_vector(31 downto 0);
signal mux_950 : std_logic_vector(31 downto 0);
signal and_862 : std_logic;
signal mux_953 : std_logic_vector(31 downto 0);
signal mux_954 : std_logic_vector(31 downto 0);
signal mux_955 : std_logic_vector(31 downto 0);
signal mux_951 : std_logic_vector(31 downto 0);
signal mux_952 : std_logic_vector(31 downto 0);
signal mux_959 : std_logic_vector(31 downto 0);
signal mux_960 : std_logic_vector(31 downto 0);
signal mux_961 : std_logic_vector(31 downto 0);
signal mux_965 : std_logic_vector(31 downto 0);
signal mux_966 : std_logic_vector(31 downto 0);
signal and_876 : std_logic_vector(7 downto 0);
signal mux_956 : std_logic_vector(31 downto 0);
signal mux_957 : std_logic_vector(31 downto 0);
signal mux_947 : std_logic_vector(31 downto 0);
signal mux_968 : std_logic_vector(31 downto 0);
signal mux_969 : std_logic_vector(31 downto 0);
signal mux_970 : std_logic_vector(31 downto 0);
signal mux_980 : std_logic_vector(31 downto 0);
signal mux_981 : std_logic_vector(31 downto 0);
signal mux_958 : std_logic_vector(31 downto 0);
signal and_963 : std_logic;
signal mux_986 : std_logic_vector(31 downto 0);
signal mux_988 : std_logic_vector(31 downto 0);
signal mux_989 : std_logic_vector(31 downto 0);
-- This utility function is used for inlining MUX behaviour
-- Little utility function to ease concatenation of an std_logic
-- and explicitely return an std_logic_vector
function repeat(N: natural; B: std_logic) return std_logic_vector is
variable result: std_logic_vector(N-1 downto 0);
begin
result := (others => B);
return result;
end;
begin
-- Instantiation of components
cmp_869_i : cmp_869 port map (
eq => sig_1670,
in1 => sig_1665,
in0 => get_sos_cc
);
cmp_978_i : cmp_978 port map (
ne => augh_test_132,
in1 => sig_1633,
in0 => huff_make_dhuff_tb_dc_size
);
cmp_979_i : cmp_979 port map (
ne => augh_test_124,
in1 => sig_1635,
in0 => huff_make_dhuff_tb_ac_size
);
cmp_847_i : cmp_847 port map (
eq => augh_test_100,
in1 => sig_1716,
in0 => "00000000000000000000000011000000"
);
cmp_855_i : cmp_855 port map (
ne => sig_1669,
in1 => sig_1715,
in0 => "00000000000000000000000000000000"
);
cmp_852_i : cmp_852 port map (
eq => augh_test_94,
in1 => sig_1714,
in0 => "00000000000000000000000000000000"
);
mul_213_i : mul_213 port map (
output => sig_1668,
in_b => "00000000000000000000000000110001",
in_a => chenidct_b3
);
mul_216_i : mul_216 port map (
output => sig_1667,
in_b => sig_1713,
in_a => mux_762
);
mul_214_i : mul_214 port map (
output => sig_1666,
in_b => sig_1712,
in_a => mux_760
);
cmp_846_i : cmp_846 port map (
eq => augh_test_99,
in1 => sig_1711,
in0 => "00000000000000000000000011011000"
);
cmp_848_i : cmp_848 port map (
eq => augh_test_101,
in1 => sig_1710,
in0 => "00000000000000000000000011011010"
);
cmp_849_i : cmp_849 port map (
eq => augh_test_102,
in1 => sig_1709,
in0 => "00000000000000000000000011000100"
);
p_jinfo_comps_info_id_i : p_jinfo_comps_info_id port map (
wa0_data => read_byte,
wa0_addr => get_sof_i_comp_info_id,
clk => sig_clock,
ra0_addr => get_sos_ci(1 downto 0),
ra0_data => sig_1665,
wa0_en => sig_1213
);
p_jinfo_comps_info_h_samp_factor_i : p_jinfo_comps_info_h_samp_factor port map (
wa0_data => and_876,
wa0_addr => get_sof_i_comp_info_h_samp_factor,
clk => sig_clock,
ra0_addr => "00",
ra0_data => sig_1664,
wa0_en => sig_1214
);
p_jinfo_comps_info_quant_tbl_no_i : p_jinfo_comps_info_quant_tbl_no port map (
wa0_data => read_byte(1 downto 0),
wa0_addr => get_sof_i_comp_info_quant_tbl_no,
clk => sig_clock,
ra0_addr => decode_block_comp_no,
ra0_data => sig_1663,
wa0_en => sig_1212
);
p_jinfo_comps_info_dc_tbl_no_i : p_jinfo_comps_info_dc_tbl_no port map (
wa0_data => get_sos_c,
wa0_addr => get_sos_i_comp_info_dc_tbl_no,
clk => sig_clock,
ra0_addr => decode_block_comp_no,
ra0_data => sig_1662,
wa0_en => sig_1252
);
p_jinfo_quant_tbl_quantval_i : p_jinfo_quant_tbl_quantval port map (
wa0_data => sig_1708,
wa0_addr => sig_1707,
clk => sig_clock,
ra0_addr => mux_731,
ra0_data => sig_1661,
wa0_en => sig_1334
);
p_jinfo_dc_xhuff_tbl_bits_i : p_jinfo_dc_xhuff_tbl_bits port map (
wa0_data => mux_782,
wa0_addr => sig_1706,
clk => sig_clock,
ra0_addr => mux_727,
ra0_data => sig_1660,
wa0_en => sig_1457
);
p_jinfo_dc_xhuff_tbl_huffval_i : p_jinfo_dc_xhuff_tbl_huffval port map (
wa0_data => mux_778,
wa0_addr => sig_1705,
clk => sig_clock,
ra0_addr => mux_723,
ra0_data => sig_1659,
wa0_en => sig_1540
);
p_jinfo_ac_xhuff_tbl_bits_i : p_jinfo_ac_xhuff_tbl_bits port map (
wa0_data => mux_783,
wa0_addr => sig_1704,
clk => sig_clock,
ra0_addr => mux_719,
ra0_data => sig_1658,
wa0_en => sig_1457
);
p_jinfo_ac_xhuff_tbl_huffval_i : p_jinfo_ac_xhuff_tbl_huffval port map (
wa0_data => mux_781,
wa0_addr => sig_1703,
clk => sig_clock,
ra0_addr => mux_715,
ra0_data => sig_1657,
wa0_en => sig_1540
);
p_jinfo_dc_dhuff_tbl_ml_i : p_jinfo_dc_dhuff_tbl_ml port map (
wa0_data => huff_make_dhuff_tb_dc,
wa0_addr => sig_1188,
clk => sig_clock,
ra0_addr => mux_711,
ra0_data => sig_1656,
wa0_en => sig_1190
);
p_jinfo_dc_dhuff_tbl_maxcode_i : p_jinfo_dc_dhuff_tbl_maxcode port map (
wa0_data => mux_705,
wa0_addr => mux_706,
clk => sig_clock,
ra0_addr => mux_707,
ra0_data => sig_1655,
wa0_en => sig_1560
);
p_jinfo_dc_dhuff_tbl_mincode_i : p_jinfo_dc_dhuff_tbl_mincode port map (
wa0_data => sig_1632(8 downto 0),
wa0_addr => sig_1702,
clk => sig_clock,
ra0_addr => sig_1701,
ra0_data => sig_1654,
wa0_en => sig_1039
);
p_jinfo_dc_dhuff_tbl_valptr_i : p_jinfo_dc_dhuff_tbl_valptr port map (
wa0_data => huff_make_dhuff_tb_dc_p(8 downto 0),
wa0_addr => sig_1700,
clk => sig_clock,
ra0_addr => sig_1699,
ra0_data => sig_1653,
wa0_en => sig_1039
);
p_jinfo_ac_dhuff_tbl_ml_i : p_jinfo_ac_dhuff_tbl_ml port map (
wa0_data => huff_make_dhuff_tb_ac,
wa0_addr => sig_1183,
clk => sig_clock,
ra0_addr => mux_695,
ra0_data => sig_1652,
wa0_en => sig_1185
);
p_jinfo_ac_dhuff_tbl_maxcode_i : p_jinfo_ac_dhuff_tbl_maxcode port map (
wa0_data => mux_689,
wa0_addr => mux_690,
clk => sig_clock,
ra0_addr => mux_691,
ra0_data => sig_1651,
wa0_en => sig_1522
);
p_jinfo_ac_dhuff_tbl_mincode_i : p_jinfo_ac_dhuff_tbl_mincode port map (
wa0_data => sig_1634(8 downto 0),
wa0_addr => sig_1698,
clk => sig_clock,
ra0_addr => sig_1697,
ra0_data => sig_1650,
wa0_en => sig_1549
);
p_jinfo_ac_dhuff_tbl_valptr_i : p_jinfo_ac_dhuff_tbl_valptr port map (
wa0_data => huff_make_dhuff_tb_ac_p(8 downto 0),
wa0_addr => sig_1696,
clk => sig_clock,
ra0_addr => sig_1695,
ra0_data => sig_1649,
wa0_en => sig_1549
);
outdata_comp_vpos_i : outdata_comp_vpos port map (
wa0_data => mux_663,
wa0_addr => mux_664,
clk => sig_clock,
ra0_addr => mux_665,
ra0_data => sig_1648,
wa0_en => sig_1295
);
outdata_comp_hpos_i : outdata_comp_hpos port map (
wa0_data => mux_659,
wa0_addr => mux_660,
clk => sig_clock,
ra0_addr => mux_661,
ra0_data => sig_1647,
wa0_en => sig_1295
);
outdata_comp_buf_i : outdata_comp_buf port map (
wa0_data => sig_1631,
wa0_addr => sig_1694,
clk => sig_clock,
ra0_addr => sig_1693,
ra0_data => sig_1646,
wa0_en => sig_1013
);
izigzag_index_i : izigzag_index port map (
clk => sig_clock,
ra0_addr => get_dqt_i(5 downto 0),
ra0_data => sig_1645
);
jpegfilebuf_i : jpegfilebuf port map (
wa0_data => read8_ret0_195,
wa0_addr => jpeg2bmp_main_i(12 downto 0),
clk => sig_clock,
ra0_addr => mux_652,
ra0_data => sig_1644,
wa0_en => sig_1041
);
huffbuff_i : huffbuff port map (
wa0_data => mux_567,
wa0_addr => mux_568,
clk => sig_clock,
ra0_addr => mux_569,
ra0_data => sig_1643,
wa0_en => sig_1428
);
idctbuff_i : idctbuff port map (
wa0_data => mux_561,
wa0_addr => mux_562,
clk => sig_clock,
ra2_data => sig_1642,
ra2_addr => mux_563,
ra1_data => sig_1641,
ra1_addr => sig_1692,
ra0_addr => mux_565,
ra0_data => sig_1640,
wa0_en => sig_1474
);
quantbuff_i : quantbuff port map (
wa0_data => mux_557,
wa0_addr => mux_558,
clk => sig_clock,
ra0_addr => mux_559,
ra0_data => sig_1639,
wa0_en => sig_1431
);
extend_mask_i : extend_mask port map (
clk => sig_clock,
ra0_addr => decodehuffmcu_s(4 downto 0),
ra0_data => sig_1638
);
bit_set_mask_i : bit_set_mask port map (
clk => sig_clock,
ra0_addr => mux_524,
ra0_data => sig_1637
);
lmask_i : lmask port map (
clk => sig_clock,
ra0_addr => buf_getv_n(4 downto 0),
ra0_data => sig_1636
);
huff_make_dhuff_tb_ac_huffsize_i : huff_make_dhuff_tb_ac_huffsize port map (
wa0_data => mux_476,
wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
clk => sig_clock,
ra0_addr => mux_478,
ra0_data => sig_1635,
wa0_en => sig_1501
);
huff_make_dhuff_tb_ac_huffcode_i : huff_make_dhuff_tb_ac_huffcode port map (
wa0_data => huff_make_dhuff_tb_ac_code,
wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
clk => sig_clock,
ra0_addr => huff_make_dhuff_tb_ac_p(8 downto 0),
ra0_data => sig_1634,
wa0_en => sig_1024
);
huff_make_dhuff_tb_dc_huffsize_i : huff_make_dhuff_tb_dc_huffsize port map (
wa0_data => mux_443,
wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
clk => sig_clock,
ra0_addr => mux_445,
ra0_data => sig_1633,
wa0_en => sig_1530
);
huff_make_dhuff_tb_dc_huffcode_i : huff_make_dhuff_tb_dc_huffcode port map (
wa0_data => huff_make_dhuff_tb_dc_code,
wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
clk => sig_clock,
ra0_addr => huff_make_dhuff_tb_dc_p(8 downto 0),
ra0_data => sig_1632,
wa0_en => sig_1036
);
rgb_buf_i : rgb_buf port map (
wa0_data => mux_378,
wa0_addr => mux_379,
clk => sig_clock,
ra0_addr => sig_1691,
ra0_data => sig_1631,
wa0_en => sig_1236
);
zigzag_index_i : zigzag_index port map (
clk => sig_clock,
ra0_addr => izigzagmatrix_i(5 downto 0),
ra0_data => sig_1630
);
shr_212_i : shr_212 port map (
output => sig_1629,
input => mux_322,
shift => mux_323,
padding => '0'
);
mul_209_i : mul_209 port map (
output => sig_1628,
in_b => mux_315,
in_a => mux_316
);
mul_210_i : mul_210 port map (
output => sig_1627,
in_b => sig_1690,
in_a => mux_314
);
shl_211_i : shl_211 port map (
output => sig_1626,
input => current_read_byte,
shift => buf_getv_p(5 downto 0),
padding => '0'
);
sub_206_i : sub_206 port map (
gt => sig_1625,
output => sig_1624,
sign => '1',
in_b => mux_306,
in_a => mux_307
);
sub_207_i : sub_207 port map (
ge => sig_1623,
le => sig_1622,
output => sig_1621,
sign => '1',
in_b => mux_302,
in_a => mux_303
);
sub_208_i : sub_208 port map (
ge => sig_1620,
output => sig_1619,
sign => '1',
in_b => "00000000000000000000000000000000000000000",
in_a => sig_1689
);
sub_205_i : sub_205 port map (
gt => sig_1618,
ge => sig_1617,
lt => sig_1616,
le => sig_1615,
output => sig_1614,
sign => '1',
in_b => mux_290,
in_a => mux_291
);
add_202_i : add_202 port map (
output => sig_1613,
in_b => mux_274,
in_a => mux_275
);
add_203_i : add_203 port map (
output => sig_1612,
in_b => mux_271,
in_a => mux_272
);
add_204_i : add_204 port map (
output => sig_1611,
in_b => "0000000000000000000000001",
in_a => sig_1688
);
add_201_i : add_201 port map (
output => sig_1610,
in_b => mux_265,
in_a => mux_266
);
add_200_i : add_200 port map (
output => sig_1609,
in_b => mux_260,
in_a => mux_261
);
cmp_775_i : cmp_775 port map (
eq => augh_test_158,
in1 => sig_1687,
in0 => "00000000000000000000000000001111"
);
cmp_779_i : cmp_779 port map (
eq => sig_1608,
in1 => sig_1686,
in0 => "00000000000000000000000000000000"
);
cmp_780_i : cmp_780 port map (
ne => sig_1607,
in1 => sig_1685,
in0 => "00000000000000000000000000000000"
);
cmp_787_i : cmp_787 port map (
eq => sig_1606,
in1 => '0',
in0 => sig_1610(0)
);
cmp_788_i : cmp_788 port map (
eq => sig_1605,
in1 => "000",
in0 => sig_1642(2 downto 0)
);
cmp_790_i : cmp_790 port map (
ne => sig_1604,
in1 => sig_1624(3 downto 0),
in0 => "0000"
);
cmp_792_i : cmp_792 port map (
eq => augh_test_134,
in1 => sig_1660,
in0 => "00000000000000000000000000000000"
);
cmp_793_i : cmp_793 port map (
eq => augh_test_131,
in1 => sig_1633,
in0 => "00000000000000000000000000000000"
);
cmp_794_i : cmp_794 port map (
eq => augh_test_126,
in1 => sig_1658,
in0 => "00000000000000000000000000000000"
);
cmp_791_i : cmp_791 port map (
ne => augh_test_148,
in1 => decodehuffman_dc,
in0 => "00000000000000000000000000000000"
);
cmp_804_i : cmp_804 port map (
ne => augh_test_113,
in1 => and_803,
in0 => "00000000000000000000000000000000"
);
cmp_800_i : cmp_800 port map (
eq => augh_test_118,
in1 => buf_getv_p,
in0 => "00000000000000000000000000000000"
);
cmp_799_i : cmp_799 port map (
eq => augh_test_123,
in1 => sig_1635,
in0 => "00000000000000000000000000000000"
);
cmp_865_i : cmp_865 port map (
ne => sig_1603,
in1 => sig_1624(2 downto 0),
in0 => "000"
);
cmp_882_i : cmp_882 port map (
eq => augh_test_157,
in1 => and_881,
in0 => "00000000000000000000000000000000"
);
cmp_885_i : cmp_885 port map (
ne => sig_1602,
in1 => and_884,
in0 => "00000000000000000000000000000000"
);
cmp_887_i : cmp_887 port map (
eq => sig_1601,
in1 => and_884,
in0 => "00000000000000000000000000000000"
);
mul_215_i : mul_215 port map (
output => sig_1600,
in_b => "00000000000000000000000111011001",
in_a => chenidct_b2
);
cmp_850_i : cmp_850 port map (
eq => augh_test_103,
in1 => sig_1684,
in0 => "00000000000000000000000011011011"
);
cmp_851_i : cmp_851 port map (
eq => augh_test_104,
in1 => sig_1683,
in0 => "00000000000000000000000011011001"
);
cmp_861_i : cmp_861 port map (
eq => augh_test_150,
in1 => and_860,
in0 => "00000000000000000000000000000000"
);
cmp_871_i : cmp_871 port map (
eq => sig_1599,
in1 => sig_1682,
in0 => "00000000000000000000000000000000"
);
cmp_873_i : cmp_873 port map (
eq => sig_1598,
in1 => sig_1664,
in0 => "00000010"
);
cmp_879_i : cmp_879 port map (
ne => augh_test_6,
in1 => sig_1681,
in0 => "00000000000000000000000011111111"
);
cmp_880_i : cmp_880 port map (
eq => augh_test_9,
in1 => sig_1680,
in0 => "00000000000000000000000011111111"
);
sub_217_i : sub_217 port map (
ge => sig_1597,
output => sig_1596,
sign => '1',
in_b => "00000000000000000000000000000000000000000",
in_a => sig_1679
);
cmp_863_i : cmp_863 port map (
ne => sig_1595,
in1 => sig_1614(2 downto 0),
in0 => "000"
);
cmp_868_i : cmp_868 port map (
eq => sig_1594,
in1 => "000000000000000000000000",
in0 => "000000000000000000000000"
);
cmp_877_i : cmp_877 port map (
ne => augh_test_109,
in1 => sig_1678,
in0 => "00000000000000000000000000000000"
);
cmp_878_i : cmp_878 port map (
ne => augh_test_10,
in1 => sig_1677,
in0 => "00000000000000000000000000000000"
);
sub_218_i : sub_218 port map (
le => sig_1593,
output => sig_1592,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1676
);
sub_220_i : sub_220 port map (
gt => sig_1591,
output => sig_1590,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1675
);
sub_221_i : sub_221 port map (
gt => sig_1589,
output => sig_1588,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1674
);
mul_222_i : mul_222 port map (
output => sig_1587,
in_b => "00000000000000000000000010110101",
in_a => mux_233
);
sub_219_i : sub_219 port map (
le => sig_1586,
output => sig_1585,
sign => '1',
in_b => "00000000000000000000000000000000011111111",
in_a => sig_1673
);
cmp_962_i : cmp_962 port map (
ne => augh_test_62,
in1 => get_sos_j,
in0 => "11111111111111111111111111111111"
);
cmp_975_i : cmp_975 port map (
ne => augh_test_154,
in1 => decodehuffmcu_s,
in0 => "00000000000000000000000000000000"
);
fsm_224_i : fsm_224 port map (
clock => sig_clock,
reset => sig_reset,
out40 => sig_1584,
in2 => augh_test_152,
in11 => augh_test_131,
out146 => sig_1583,
out148 => sig_1582,
out150 => sig_1581,
out152 => sig_1580,
in12 => augh_test_128,
out153 => sig_1579,
out154 => sig_1578,
in13 => augh_test_127,
out156 => sig_1577,
out157 => sig_1576,
out160 => sig_1575,
out162 => sig_1574,
out165 => sig_1573,
out170 => sig_1572,
out171 => sig_1571,
out173 => sig_1570,
out175 => sig_1569,
out177 => sig_1568,
out180 => sig_1567,
out184 => sig_1566,
in14 => augh_test_126,
out186 => sig_1565,
out189 => sig_1564,
out191 => sig_1563,
out192 => sig_1562,
out193 => sig_1561,
out197 => sig_1560,
out199 => sig_1559,
out201 => sig_1558,
out202 => sig_1557,
out205 => sig_1556,
out207 => sig_1555,
out208 => sig_1554,
out209 => sig_1553,
out210 => sig_1552,
out212 => sig_1551,
out213 => sig_1550,
in15 => augh_test_125,
out221 => sig_1549,
out222 => sig_1548,
out224 => sig_1547,
out225 => sig_1546,
out228 => sig_1545,
out229 => sig_1544,
out230 => sig_1543,
out231 => sig_1542,
out99 => sig_1541,
in6 => augh_test_142,
out92 => sig_1540,
out232 => sig_1539,
in16 => augh_test_123,
out234 => sig_1538,
out236 => sig_1537,
out239 => sig_1536,
out240 => sig_1535,
out241 => sig_1534,
out245 => sig_1533,
out246 => sig_1532,
out247 => sig_1531,
out251 => sig_1530,
out252 => sig_1529,
out253 => sig_1528,
out255 => sig_1527,
out256 => sig_1526,
out258 => sig_1525,
out259 => sig_1524,
in17 => augh_test_120,
out263 => sig_1523,
out264 => sig_1522,
out266 => sig_1521,
in18 => augh_test_119,
out267 => sig_1520,
out268 => sig_1519,
out270 => sig_1518,
out273 => sig_1517,
out275 => sig_1516,
out276 => sig_1515,
in19 => augh_test_118,
out279 => sig_1514,
in20 => augh_test_115,
out281 => sig_1513,
out282 => sig_1512,
in21 => augh_test_114,
out283 => sig_1511,
out286 => sig_1510,
out289 => sig_1509,
out296 => sig_1508,
out297 => sig_1507,
out299 => sig_1506,
out300 => sig_1505,
out304 => sig_1504,
out305 => sig_1503,
in22 => augh_test_113,
out306 => sig_1502,
out310 => sig_1501,
out311 => sig_1500,
out313 => sig_1499,
out314 => sig_1498,
in23 => augh_test_111,
out316 => sig_1497,
out317 => sig_1496,
out320 => sig_1495,
out322 => sig_1494,
out324 => sig_1493,
out325 => sig_1492,
out326 => sig_1491,
out328 => sig_1490,
out332 => sig_1489,
out333 => sig_1488,
out334 => sig_1487,
out335 => sig_1486,
out338 => sig_1485,
out339 => sig_1484,
out341 => sig_1483,
out342 => sig_1482,
out344 => sig_1481,
out93 => sig_1480,
out98 => sig_1479,
out85 => sig_1478,
out87 => sig_1477,
out88 => sig_1476,
out80 => sig_1475,
out82 => sig_1474,
out83 => sig_1473,
out84 => sig_1472,
in5 => augh_test_144,
out77 => sig_1471,
out78 => sig_1470,
out71 => sig_1469,
out72 => sig_1468,
in4 => augh_test_148,
out65 => sig_1467,
out67 => sig_1466,
out60 => sig_1465,
out64 => sig_1464,
in3 => augh_test_151,
out59 => sig_1463,
out53 => sig_1462,
out55 => sig_1461,
out49 => sig_1460,
out44 => sig_1459,
out104 => sig_1458,
out107 => sig_1457,
out111 => sig_1456,
out112 => sig_1455,
out114 => sig_1454,
in7 => augh_test_138,
out117 => sig_1453,
out119 => sig_1452,
out122 => sig_1451,
in8 => augh_test_136,
out128 => sig_1450,
in9 => augh_test_134,
out129 => sig_1449,
out130 => sig_1448,
out133 => sig_1447,
out134 => sig_1446,
out136 => sig_1445,
out137 => sig_1444,
in10 => augh_test_133,
out139 => sig_1443,
out143 => sig_1442,
out144 => sig_1441,
out32 => sig_1440,
out35 => sig_1439,
out27 => sig_1438,
out25 => sig_1437,
out26 => sig_1436,
in1 => augh_test_158,
out15 => sig_1435,
out16 => sig_1434,
out11 => sig_1433,
out13 => sig_1432,
out14 => sig_1431,
out7 => sig_1430,
out1 => sig_1429,
out2 => sig_1428,
out3 => sig_1427,
out4 => sig_1426,
in0 => augh_test_159,
in24 => augh_test_107,
out346 => sig_1425,
out347 => sig_1424,
out348 => sig_1423,
out349 => sig_1422,
in25 => augh_test_106,
out350 => sig_1421,
out351 => sig_1420,
out355 => sig_1419,
out356 => sig_1418,
out357 => sig_1417,
out358 => sig_1416,
out360 => sig_1415,
out362 => sig_1414,
out363 => sig_1413,
out364 => sig_1412,
out365 => sig_1411,
out366 => sig_1410,
out370 => sig_1409,
out371 => sig_1408,
out372 => sig_1407,
out373 => sig_1406,
out375 => sig_1405,
in26 => augh_test_105,
out376 => sig_1404,
out378 => sig_1403,
out379 => sig_1402,
out381 => sig_1401,
out382 => sig_1400,
in27 => augh_test_99,
out384 => sig_1399,
in28 => augh_test_100,
out391 => sig_1398,
out395 => sig_1397,
out396 => sig_1396,
out401 => sig_1395,
out402 => sig_1394,
out403 => sig_1393,
out404 => sig_1392,
out405 => sig_1391,
out407 => sig_1390,
out408 => sig_1389,
out409 => sig_1388,
out410 => sig_1387,
in29 => augh_test_101,
out412 => sig_1386,
out414 => sig_1385,
out415 => sig_1384,
out417 => sig_1383,
out418 => sig_1382,
out419 => sig_1381,
out420 => sig_1380,
out422 => sig_1379,
out424 => sig_1378,
out425 => sig_1377,
out426 => sig_1376,
in30 => augh_test_102,
out428 => sig_1375,
out429 => sig_1374,
out432 => sig_1373,
out433 => sig_1372,
out434 => sig_1371,
out437 => sig_1370,
out440 => sig_1369,
out441 => sig_1368,
in31 => augh_test_103,
out443 => sig_1367,
in32 => augh_test_104,
out445 => sig_1366,
out447 => sig_1365,
out448 => sig_1364,
out450 => sig_1363,
in33 => augh_test_94,
out453 => sig_1362,
out455 => sig_1361,
out458 => sig_1360,
in34 => augh_test_90,
out462 => sig_1359,
out464 => sig_1358,
out467 => sig_1357,
out468 => sig_1356,
out472 => sig_1355,
in35 => augh_test_89,
out478 => sig_1354,
out479 => sig_1353,
out480 => sig_1352,
out487 => sig_1351,
out488 => sig_1350,
in36 => augh_test_83,
out491 => sig_1349,
out496 => sig_1348,
out497 => sig_1347,
out498 => sig_1346,
out500 => sig_1345,
out504 => sig_1344,
out505 => sig_1343,
in37 => augh_test_150,
out506 => sig_1342,
out508 => sig_1341,
in38 => augh_test_77,
out510 => sig_1340,
out513 => sig_1339,
out514 => sig_1338,
out515 => sig_1337,
out517 => sig_1336,
out519 => sig_1335,
in39 => augh_test_72,
out523 => sig_1334,
out526 => sig_1333,
out527 => sig_1332,
out528 => sig_1331,
out530 => sig_1330,
out531 => sig_1329,
out533 => sig_1328,
out534 => sig_1327,
out537 => sig_1326,
out538 => sig_1325,
out549 => sig_1324,
out558 => sig_1323,
out559 => sig_1322,
out561 => sig_1321,
in40 => augh_test_67,
out566 => sig_1320,
out567 => sig_1319,
out568 => sig_1318,
out569 => sig_1317,
out570 => sig_1316,
out572 => sig_1315,
out574 => sig_1314,
out575 => sig_1313,
out577 => sig_1312,
in41 => augh_test_52,
out578 => sig_1311,
out581 => sig_1310,
out589 => sig_1309,
out590 => sig_1308,
out595 => sig_1307,
out597 => sig_1306,
out599 => sig_1305,
out601 => sig_1304,
out602 => sig_1303,
out607 => sig_1302,
out610 => sig_1301,
out612 => sig_1300,
in42 => augh_test_53,
out614 => sig_1299,
out621 => sig_1298,
out628 => sig_1297,
out635 => sig_1296,
out636 => sig_1295,
out638 => sig_1294,
out640 => sig_1293,
out643 => sig_1292,
out646 => sig_1291,
out649 => sig_1290,
out651 => sig_1289,
out656 => sig_1288,
in43 => augh_test_49,
out658 => sig_1287,
out659 => sig_1286,
out661 => sig_1285,
out663 => sig_1284,
out664 => sig_1283,
in44 => augh_test_109,
out667 => sig_1282,
out668 => sig_1281,
out670 => sig_1280,
out672 => sig_1279,
out674 => sig_1278,
in45 => augh_test_26,
out679 => sig_1277,
out681 => sig_1276,
out683 => sig_1275,
out686 => sig_1274,
out688 => sig_1273,
out690 => sig_1272,
out692 => sig_1271,
out694 => sig_1270,
out696 => sig_1269,
out697 => sig_1268,
out698 => sig_1267,
out699 => sig_1266,
out700 => sig_1265,
out703 => sig_1264,
out704 => sig_1263,
out706 => sig_1262,
out708 => sig_1261,
out710 => sig_1260,
out712 => sig_1259,
out715 => sig_1258,
out718 => sig_1257,
in46 => augh_test_10,
out722 => sig_1256,
out724 => sig_1255,
out726 => sig_1254,
out728 => sig_1253,
out731 => sig_1252,
out733 => sig_1251,
out734 => sig_1250,
out737 => sig_1249,
out739 => sig_1248,
out740 => sig_1247,
out743 => sig_1246,
out745 => sig_1245,
out746 => sig_1244,
in47 => augh_test_6,
out749 => sig_1243,
out753 => sig_1242,
out755 => sig_1241,
out759 => sig_1240,
in48 => augh_test_9,
out762 => sig_1239,
out764 => sig_1238,
out765 => sig_1237,
out767 => sig_1236,
out768 => sig_1235,
in49 => augh_test_157,
out772 => sig_1234,
in50 => stdout_ack,
out775 => sig_1233,
out776 => sig_1232,
out778 => sig_1231,
out783 => sig_1230,
out784 => sig_1229,
out787 => sig_1228,
out791 => sig_1227,
in51 => stdin_ack,
out794 => sig_1226,
out795 => sig_1225,
in52 => augh_test_62,
out799 => sig_1224,
out802 => sig_1223,
out806 => sig_1222,
out809 => sig_1221,
out812 => sig_1220,
out815 => sig_1219,
out826 => sig_1218,
out828 => sig_1217,
in53 => augh_test_122,
in54 => augh_test_197,
out843 => sig_1216,
out848 => sig_1215,
out852 => sig_1214,
in55 => augh_test_196,
out855 => sig_1213,
out858 => sig_1212,
in56 => augh_test_189,
out860 => sig_1211,
out861 => sig_1210,
out863 => sig_1209,
out866 => sig_1208,
out872 => sig_1207,
in57 => augh_test_188,
out874 => sig_1206,
out876 => sig_1205,
out879 => sig_1204,
out882 => sig_1203,
out886 => sig_1202,
out887 => sig_1201,
in58 => augh_test_187,
out888 => sig_1200,
out892 => sig_1199,
out894 => sig_1198,
out895 => sig_1197,
out896 => sig_1196,
out901 => sig_1195,
out902 => sig_1194,
out903 => sig_1193,
out905 => sig_1192,
out907 => sig_1191,
out918 => sig_1190,
out920 => sig_1189,
out921 => sig_1188,
out923 => sig_1187,
out925 => sig_1186,
out928 => sig_1185,
out929 => sig_1184,
out931 => sig_1183,
out933 => sig_1182,
out936 => stdout_rdy,
out937 => sig_1181,
out938 => sig_1180,
out939 => sig_1179,
out942 => sig_1178,
out943 => sig_1177,
out944 => sig_1176,
out947 => sig_1175,
out948 => sig_1174,
out949 => sig_1173,
out951 => sig_1172,
in59 => augh_test_186,
out952 => sig_1171,
out953 => sig_1170,
out955 => sig_1169,
out956 => sig_1168,
out957 => sig_1167,
out958 => sig_1166,
in60 => augh_test_184,
in61 => augh_test_183,
out962 => sig_1165,
out963 => sig_1164,
out972 => sig_1163,
out973 => sig_1162,
out974 => sig_1161,
in62 => augh_test_182,
out978 => sig_1160,
out979 => sig_1159,
out981 => sig_1158,
out982 => sig_1157,
out985 => sig_1156,
out986 => sig_1155,
out989 => sig_1154,
in63 => augh_test_180,
in64 => augh_test_179,
in65 => augh_test_178,
in66 => augh_test_194,
in67 => augh_test_154,
in68 => augh_test_130,
in69 => augh_test_132,
in70 => augh_test_124,
in71 => augh_test_171,
in72 => augh_test_168,
in73 => augh_test_167,
in74 => augh_test_166,
in75 => augh_test_165,
in76 => augh_test_108,
in77 => sig_start,
in78 => augh_test_155,
out990 => sig_1153,
out991 => sig_1152,
out993 => sig_1151,
out994 => sig_1150,
out996 => sig_1149,
out997 => sig_1148,
out998 => sig_1147,
out999 => sig_1146,
out1000 => sig_1145,
out1002 => sig_1144,
out1003 => sig_1143,
out1005 => sig_1142,
out1006 => sig_1141,
out1007 => sig_1140,
out1009 => sig_1139,
out1011 => sig_1138,
out1012 => sig_1137,
out1013 => sig_1136,
out1014 => sig_1135,
out1015 => sig_1134,
out1016 => sig_1133,
out1018 => sig_1132,
out1019 => sig_1131,
out1021 => sig_1130,
out1022 => sig_1129,
out1024 => sig_1128,
out1026 => sig_1127,
out1027 => sig_1126,
out1029 => sig_1125,
out1030 => sig_1124,
out1032 => sig_1123,
out1033 => sig_1122,
out1035 => sig_1121,
out1036 => sig_1120,
out1037 => sig_1119,
out1057 => sig_1118,
out1068 => sig_1117,
out1069 => sig_1116,
out1070 => sig_1115,
out1072 => sig_1114,
out1073 => sig_1113,
out1075 => sig_1112,
out1078 => sig_1111,
out1080 => sig_1110,
out1082 => sig_1109,
out1083 => sig_1108,
out1084 => sig_1107,
out1085 => sig_1106,
out1088 => sig_1105,
out1089 => sig_1104,
out1091 => sig_1103,
out1092 => sig_1102,
out1094 => sig_1101,
out1096 => sig_1100,
out1098 => sig_1099,
out1101 => sig_1098,
out1104 => sig_1097,
out1107 => sig_1096,
out1109 => sig_1095,
out1111 => sig_1094,
out1114 => sig_1093,
out1119 => sig_1092,
out1121 => sig_1091,
out1125 => sig_1090,
out1126 => sig_1089,
out1128 => sig_1088,
out1131 => sig_1087,
out1134 => sig_1086,
out1137 => sig_1085,
out1139 => sig_1084,
out1141 => sig_1083,
out1145 => sig_1082,
out1146 => sig_1081,
out1147 => sig_1080,
out1150 => sig_1079,
out1151 => sig_1078,
out1152 => sig_1077,
out1155 => sig_1076,
out1158 => sig_1075,
out1160 => sig_1074,
out1164 => sig_1073,
out1166 => sig_1072,
out1169 => sig_1071,
out1171 => sig_1070,
out1174 => sig_1069,
out1175 => sig_1068,
out1176 => sig_1067,
out1180 => sig_1066,
out1181 => sig_1065,
out1182 => sig_1064,
out1185 => sig_1063,
out1186 => sig_1062,
out1187 => sig_1061,
out1190 => sig_1060,
out1213 => sig_1059,
out1215 => sig_1058,
out1217 => sig_1057,
out1220 => sig_1056,
out1221 => sig_1055,
out1223 => sig_1054,
out1228 => sig_1053,
out1229 => sig_1052,
out1231 => sig_1051,
out1235 => sig_1050,
out1236 => sig_1049,
out1240 => sig_1048,
out1243 => sig_1047,
out1250 => sig_1046,
out1252 => sig_1045,
out1253 => sig_1044,
out1258 => sig_1043,
out1262 => sig_1042,
out1266 => sig_1041,
out1269 => sig_1040,
out1275 => sig_1039,
out1278 => sig_1038,
out1279 => sig_1037,
out1284 => sig_1036,
out1286 => sig_1035,
out1287 => sig_1034,
out1289 => sig_1033,
out1290 => sig_1032,
out1292 => sig_1031,
out1293 => sig_1030,
out1295 => sig_1029,
out1298 => sig_1028,
out1301 => sig_1027,
out1302 => sig_1026,
out1303 => sig_1025,
out1308 => sig_1024,
out1309 => sig_1023,
out1311 => sig_1022,
out1318 => sig_1021,
out1319 => sig_1020,
out1320 => sig_1019,
out1323 => sig_1018,
out1324 => sig_1017,
out1326 => sig_1016,
out1327 => sig_1015,
out1329 => sig_1014,
out1337 => sig_1013,
out1339 => sig_1012,
out1340 => sig_1011,
out1341 => sig_1010,
out1344 => sig_1009,
out1346 => sig_1008,
out1349 => sig_1007,
out1353 => sig_1006,
out1356 => sig_1005,
out1362 => sig_1004,
out1363 => sig_1003,
out1364 => sig_1002,
out1365 => sig_1001,
out1366 => sig_1000,
out1368 => sig_999,
out1370 => sig_998,
out1375 => sig_997,
out1378 => sig_996,
out1381 => sig_995,
out1383 => sig_994,
out1387 => sig_993
);
muxb_784_i : muxb_784 port map (
in_sel => sig_1616,
out_data => sig_992,
in_data0 => sig_1609(31 downto 0),
in_data1 => sig_1613
);
cmp_964_i : cmp_964 port map (
eq => sig_991,
in1 => sig_1635,
in0 => huff_make_dhuff_tb_ac_size
);
cmp_972_i : cmp_972 port map (
ne => augh_test_196,
in1 => jpeg2bmp_main_i,
in0 => "00000000000000000000000000000010"
);
cmp_973_i : cmp_973 port map (
eq => augh_test_180,
in1 => sig_1672,
in0 => "00000000000000000000000000000000"
);
cmp_974_i : cmp_974 port map (
ne => augh_test_194,
in1 => jpeg2bmp_main_i,
in0 => "00000000000000000001010001010110"
);
cmp_985_i : cmp_985 port map (
eq => augh_test_108,
in1 => sig_1671,
in0 => "00000000000000000000000011111111"
);
cmp_971_i : cmp_971 port map (
ne => augh_test_197,
in1 => jpeg2bmp_main_j,
in0 => "00000000000000000001010010111101"
);
cmp_977_i : cmp_977 port map (
eq => sig_990,
in1 => sig_1633,
in0 => huff_make_dhuff_tb_dc_size
);
-- Behaviour of component 'mux_967' model 'mux'
mux_967 <=
(repeat(32, sig_1620) and mux_968);
-- Behaviour of component 'and_976' model 'and'
and_976 <=
sig_1615 and
sig_990;
-- Behaviour of component 'and_982' model 'and'
and_982 <=
"00000000000000000000000000001111" and
decodehuffman_ac;
-- Behaviour of component 'and_983' model 'and'
and_983 <=
"0000000000000000000000001111" and
decodehuffman_ac(31 downto 4);
-- Behaviour of component 'and_984' model 'and'
and_984 <=
sig_1636 and
buf_getv_rv;
-- Behaviour of component 'mux_689' model 'mux'
mux_689 <=
(repeat(32, sig_1034) and sig_1634) or
(repeat(32, sig_1520) and "11111111111111111111111111111111") or
(repeat(32, sig_1523) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_690' model 'mux'
mux_690 <=
(repeat(7, sig_1519) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or
(repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0));
-- Behaviour of component 'mux_691' model 'mux'
mux_691 <=
(repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0)) or
(repeat(7, sig_1568) and decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0)) or
(repeat(7, sig_1570) and decodehuffman_ac_tbl_no & decodehuffman_ac_dhuff_ml);
-- Behaviour of component 'and_853' model 'and'
and_853 <=
sig_1636 and
sig_1629;
-- Behaviour of component 'mux_233' model 'mux'
mux_233 <=
(repeat(32, sig_1118) and sig_1609(31 downto 0)) or
(repeat(32, sig_1324) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_671' model 'mux'
mux_671 <=
(repeat(32, sig_1183) and i_jinfo_jpeg_data) or
(repeat(32, sig_1441) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_665' model 'mux'
mux_665 <=
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_663' model 'mux'
mux_663 <=
(repeat(32, sig_1163) and sig_1609(30 downto 0) & sig_1648(0)) or
(repeat(32, sig_1161) and mux_896) or
(repeat(32, sig_1215) and mux_874) or
(repeat(32, sig_1297) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_664' model 'mux'
mux_664 <=
(repeat(2, sig_1043) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_659' model 'mux'
mux_659 <=
(repeat(32, sig_1163) and sig_1610(30 downto 0) & sig_1647(0)) or
(repeat(32, sig_1161) and mux_897) or
(repeat(32, sig_1215) and mux_875) or
(repeat(32, sig_1297) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_660' model 'mux'
mux_660 <=
(repeat(2, sig_1043) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_661' model 'mux'
mux_661 <=
(repeat(2, sig_1162) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0)) or
(repeat(2, sig_1296) and writeblock_i);
-- Behaviour of component 'mux_652' model 'mux'
mux_652 <=
(repeat(13, sig_1247) and readbuf_idx(12 downto 0)) or
(repeat(13, sig_1441) and curhuffreadbuf_idx(12 downto 0));
-- Behaviour of component 'mux_648' model 'mux'
mux_648 <=
(repeat(32, sig_1247) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_633' model 'mux'
mux_633 <=
(repeat(32, sig_1211) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_622' model 'mux'
mux_622 <=
(repeat(32, sig_1251) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_614' model 'mux'
mux_614 <=
(repeat(32, sig_1269) and "00000000000000000000000000000011") or
(repeat(32, sig_1287) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_616' model 'mux'
mux_616 <=
(repeat(32, sig_1254) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_602' model 'mux'
mux_602 <=
(repeat(32, sig_1198) and "00000000000000000000000000000001") or
(repeat(32, sig_1479) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_600' model 'mux'
mux_600 <=
(repeat(32, sig_1458) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_593' model 'mux'
mux_593 <=
(repeat(32, sig_1240) and mux_870) or
(repeat(32, sig_1317) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_587' model 'mux'
mux_587 <=
(repeat(32, sig_1335) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_585' model 'mux'
mux_585 <=
(repeat(16, sig_1337) and read_word) or
(repeat(16, sig_1339) and "00000000" & read_byte);
-- Behaviour of component 'mux_580' model 'mux'
mux_580 <=
(repeat(8, sig_1346) and read_byte) or
(repeat(8, sig_1348) and next_marker);
-- Behaviour of component 'mux_569' model 'mux'
mux_569 <=
(repeat(8, sig_1027) and decodehuffmcu_bufdim1 & "000000") or
(repeat(8, sig_1268) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or
(repeat(8, sig_1436) and decode_block_in_buf_idx & sig_1630);
-- Behaviour of component 'mux_567' model 'mux'
mux_567 <=
(repeat(32, sig_1257) and sig_1610(31 downto 0)) or
(repeat(32, sig_1000) and decodehuffmcu_diff) or
(repeat(32, sig_1202) and buf_getv) or
(repeat(32, sig_1267) and or_866);
-- Behaviour of component 'mux_568' model 'mux'
mux_568 <=
(repeat(8, sig_1266) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or
(repeat(8, sig_1000) and decodehuffmcu_bufdim1 & "000000") or
(repeat(8, sig_1443) and decodehuffmcu_bufdim1 & decodehuffmcu_i(5 downto 0)) or
(repeat(8, sig_1429) and decode_start_i(1 downto 0) & "000000");
-- Behaviour of component 'mux_563' model 'mux'
mux_563 <=
(repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or
(repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or
(repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or
(repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or
(repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or
(repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or
(repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or
(repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or
(repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or
(repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or
(repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or
(repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or
(repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or
(repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or
(repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or
(repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or
(repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or
(repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or
(repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or
(repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or
(repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or
(repeat(9, sig_1414) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or
(repeat(9, sig_1451) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or
(repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or
(repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or
(repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or
(repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or
(repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or
(repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or
(repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or
(repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or
(repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or
(repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or
(repeat(9, sig_1299) and yuvtorgb_yidx & yuvtorgb_i(5 downto 0)) or
(repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or
(repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or
(repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or
(repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or
(repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or
(repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or
(repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or
(repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or
(repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or
(repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or
(repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or
(repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or
(repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or
(repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or
(repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or
(repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or
(repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or
(repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or
(repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or
(repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or
(repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or
(repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or
(repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or
(repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or
(repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or
(repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or
(repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or
(repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or
(repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or
(repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or
(repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or
(repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or
(repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or
(repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000");
-- Behaviour of component 'mux_565' model 'mux'
mux_565 <=
(repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001") or
(repeat(9, sig_1299) and yuvtorgb_vidx & yuvtorgb_i(5 downto 0));
-- Behaviour of component 'mux_561' model 'mux'
mux_561 <=
(repeat(32, sig_1556) and sig_1610(24 downto 0) & sig_1642(6 downto 0)) or
(repeat(32, sig_1400) and mux_817) or
(repeat(32, sig_1399) and mux_819) or
(repeat(32, sig_1395) and sig_1609(31 downto 0)) or
(repeat(32, sig_1392) and sig_1614(31 downto 0)) or
(repeat(32, sig_1390) and mux_821) or
(repeat(32, sig_1416) and mux_807) or
(repeat(32, sig_1387) and mux_823) or
(repeat(32, sig_1386) and mux_825) or
(repeat(32, sig_1385) and mux_827) or
(repeat(32, sig_1383) and mux_829) or
(repeat(32, sig_1380) and mux_831) or
(repeat(32, sig_1379) and mux_833) or
(repeat(32, sig_1378) and mux_835) or
(repeat(32, sig_1374) and mux_837) or
(repeat(32, sig_1419) and mux_805) or
(repeat(32, sig_1513) and mux_797) or
(repeat(32, sig_1516) and mux_795) or
(repeat(32, sig_1409) and mux_809) or
(repeat(32, sig_1406) and mux_811) or
(repeat(32, sig_1404) and mux_813) or
(repeat(32, sig_1402) and mux_815) or
(repeat(32, sig_1451) and sig_992) or
(repeat(32, sig_1475) and mux_776) or
(repeat(32, sig_1373) and mux_839) or
(repeat(32, sig_1369) and mux_841) or
(repeat(32, sig_1364) and mux_843) or
(repeat(32, sig_1329) and mux_856) or
(repeat(32, sig_1327) and mux_858) or
(repeat(32, sig_1263) and sig_1610(31 downto 0)) or
(repeat(32, sig_1176) and mux_888) or
(repeat(32, sig_1175) and mux_890) or
(repeat(32, sig_1173) and mux_892) or
(repeat(32, sig_1172) and mux_894) or
(repeat(32, sig_1160) and mux_898) or
(repeat(32, sig_1158) and mux_900) or
(repeat(32, sig_1154) and mux_902) or
(repeat(32, sig_1152) and mux_904) or
(repeat(32, sig_1150) and mux_906) or
(repeat(32, sig_1149) and mux_908) or
(repeat(32, sig_1148) and mux_910) or
(repeat(32, sig_1147) and mux_912) or
(repeat(32, sig_1145) and mux_914) or
(repeat(32, sig_1143) and mux_916) or
(repeat(32, sig_1142) and mux_918) or
(repeat(32, sig_1140) and mux_920) or
(repeat(32, sig_1139) and mux_922) or
(repeat(32, sig_1138) and mux_924) or
(repeat(32, sig_1136) and mux_926) or
(repeat(32, sig_1135) and mux_928) or
(repeat(32, sig_1133) and mux_930) or
(repeat(32, sig_1131) and mux_932) or
(repeat(32, sig_1129) and mux_934) or
(repeat(32, sig_1128) and mux_936) or
(repeat(32, sig_1127) and mux_938) or
(repeat(32, sig_1125) and mux_940) or
(repeat(32, sig_1123) and mux_942) or
(repeat(32, sig_1121) and mux_944) or
(repeat(32, sig_1119) and mux_946) or
(repeat(32, sig_1117) and mux_948) or
(repeat(32, sig_1115) and mux_950) or
(repeat(32, sig_1113) and mux_952) or
(repeat(32, sig_1109) and mux_954) or
(repeat(32, sig_1106) and mux_956) or
(repeat(32, sig_1105) and mux_958) or
(repeat(32, sig_1103) and mux_960) or
(repeat(32, sig_1031) and mux_980) or
(repeat(32, sig_1003) and mux_986) or
(repeat(32, sig_1002) and mux_988);
-- Behaviour of component 'mux_562' model 'mux'
mux_562 <=
(repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or
(repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or
(repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or
(repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or
(repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or
(repeat(9, sig_1391) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or
(repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or
(repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or
(repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or
(repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or
(repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or
(repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or
(repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or
(repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or
(repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or
(repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or
(repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or
(repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or
(repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or
(repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or
(repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or
(repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or
(repeat(9, sig_1450) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or
(repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or
(repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or
(repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or
(repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or
(repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or
(repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or
(repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or
(repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or
(repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or
(repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or
(repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or
(repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or
(repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or
(repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or
(repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or
(repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or
(repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or
(repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or
(repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or
(repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or
(repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or
(repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or
(repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or
(repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or
(repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or
(repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or
(repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or
(repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or
(repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or
(repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or
(repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or
(repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or
(repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or
(repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or
(repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or
(repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or
(repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or
(repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or
(repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or
(repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or
(repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or
(repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or
(repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or
(repeat(9, sig_1087) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000") or
(repeat(9, sig_1083) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001");
-- Behaviour of component 'mux_557' model 'mux'
mux_557 <=
(repeat(32, sig_1436) and sig_1643) or
(repeat(32, sig_1433) and sig_1628(31 downto 0));
-- Behaviour of component 'mux_558' model 'mux'
mux_558 <=
(repeat(6, sig_1564) and "000101") or
(repeat(6, sig_1321) and "110001") or
(repeat(6, sig_1320) and "000110") or
(repeat(6, sig_1315) and "010101") or
(repeat(6, sig_1311) and "011111") or
(repeat(6, sig_1301) and "100101") or
(repeat(6, sig_1367) and "111010") or
(repeat(6, sig_1293) and "100111") or
(repeat(6, sig_1277) and "000010") or
(repeat(6, sig_1276) and "111001") or
(repeat(6, sig_1275) and "010001") or
(repeat(6, sig_1270) and "110000") or
(repeat(6, sig_1260) and "101001") or
(repeat(6, sig_1259) and "111100") or
(repeat(6, sig_1258) and "011000") or
(repeat(6, sig_1371) and "110111") or
(repeat(6, sig_1410) and "011001") or
(repeat(6, sig_1508) and "001101") or
(repeat(6, sig_1361) and "101100") or
(repeat(6, sig_1359) and "001000") or
(repeat(6, sig_1358) and "101011") or
(repeat(6, sig_1436) and izigzagmatrix_out_idx(5 downto 0)) or
(repeat(6, sig_1432) and "010010") or
(repeat(6, sig_1256) and "010110") or
(repeat(6, sig_1255) and "000011") or
(repeat(6, sig_1246) and "100011") or
(repeat(6, sig_1239) and "100001") or
(repeat(6, sig_1235) and "100100") or
(repeat(6, sig_1231) and "100110") or
(repeat(6, sig_1230) and "100000") or
(repeat(6, sig_1228) and "110101") or
(repeat(6, sig_1227) and "101101") or
(repeat(6, sig_1226) and "011110") or
(repeat(6, sig_1225) and "000100") or
(repeat(6, sig_1223) and "000111") or
(repeat(6, sig_1222) and "110110") or
(repeat(6, sig_1221) and "011101") or
(repeat(6, sig_1220) and "101110") or
(repeat(6, sig_1166) and "001110") or
(repeat(6, sig_1164) and "110100") or
(repeat(6, sig_1156) and "010100") or
(repeat(6, sig_1155) and "101010") or
(repeat(6, sig_1099) and "011010") or
(repeat(6, sig_1098) and "101111") or
(repeat(6, sig_1097) and "010011") or
(repeat(6, sig_1094) and "010111") or
(repeat(6, sig_1093) and "111000") or
(repeat(6, sig_1092) and "011100") or
(repeat(6, sig_1091) and "000001") or
(repeat(6, sig_1090) and "001001") or
(repeat(6, sig_1086) and "001011") or
(repeat(6, sig_1085) and "110010") or
(repeat(6, sig_1084) and "010000") or
(repeat(6, sig_1079) and "001111") or
(repeat(6, sig_1076) and "001010") or
(repeat(6, sig_1075) and "110011") or
(repeat(6, sig_1074) and "111111") or
(repeat(6, sig_1071) and "011011") or
(repeat(6, sig_1063) and "001100") or
(repeat(6, sig_1054) and "101000") or
(repeat(6, sig_1050) and "100010") or
(repeat(6, sig_1028) and "111101") or
(repeat(6, sig_1022) and "111110") or
(repeat(6, sig_1007) and "111011");
-- Behaviour of component 'mux_559' model 'mux'
mux_559 <=
(repeat(6, sig_1581) and chenidct_i(5 downto 0)) or
(repeat(6, sig_1358) and "101011") or
(repeat(6, sig_1321) and "110001") or
(repeat(6, sig_1320) and "000110") or
(repeat(6, sig_1315) and "010101") or
(repeat(6, sig_1311) and "011111") or
(repeat(6, sig_1371) and "110111") or
(repeat(6, sig_1301) and "100101") or
(repeat(6, sig_1293) and "100111") or
(repeat(6, sig_1277) and "000010") or
(repeat(6, sig_1276) and "111001") or
(repeat(6, sig_1275) and "010001") or
(repeat(6, sig_1270) and "110000") or
(repeat(6, sig_1260) and "101001") or
(repeat(6, sig_1259) and "111100") or
(repeat(6, sig_1410) and "011001") or
(repeat(6, sig_1508) and "001101") or
(repeat(6, sig_1564) and "000101") or
(repeat(6, sig_1367) and "111010") or
(repeat(6, sig_1361) and "101100") or
(repeat(6, sig_1359) and "001000") or
(repeat(6, sig_1473) and chenidct_aidx(5 downto 0)) or
(repeat(6, sig_1432) and "010010") or
(repeat(6, sig_1258) and "011000") or
(repeat(6, sig_1256) and "010110") or
(repeat(6, sig_1255) and "000011") or
(repeat(6, sig_1246) and "100011") or
(repeat(6, sig_1239) and "100001") or
(repeat(6, sig_1235) and "100100") or
(repeat(6, sig_1231) and "100110") or
(repeat(6, sig_1230) and "100000") or
(repeat(6, sig_1228) and "110101") or
(repeat(6, sig_1227) and "101101") or
(repeat(6, sig_1226) and "011110") or
(repeat(6, sig_1225) and "000100") or
(repeat(6, sig_1223) and "000111") or
(repeat(6, sig_1222) and "110110") or
(repeat(6, sig_1221) and "011101") or
(repeat(6, sig_1220) and "101110") or
(repeat(6, sig_1166) and "001110") or
(repeat(6, sig_1164) and "110100") or
(repeat(6, sig_1156) and "010100") or
(repeat(6, sig_1155) and "101010") or
(repeat(6, sig_1099) and "011010") or
(repeat(6, sig_1098) and "101111") or
(repeat(6, sig_1097) and "010011") or
(repeat(6, sig_1094) and "010111") or
(repeat(6, sig_1093) and "111000") or
(repeat(6, sig_1092) and "011100") or
(repeat(6, sig_1091) and "000001") or
(repeat(6, sig_1090) and "001001") or
(repeat(6, sig_1086) and "001011") or
(repeat(6, sig_1085) and "110010") or
(repeat(6, sig_1084) and "010000") or
(repeat(6, sig_1079) and "001111") or
(repeat(6, sig_1076) and "001010") or
(repeat(6, sig_1075) and "110011") or
(repeat(6, sig_1074) and "111111") or
(repeat(6, sig_1071) and "011011") or
(repeat(6, sig_1063) and "001100") or
(repeat(6, sig_1054) and "101000") or
(repeat(6, sig_1050) and "100010") or
(repeat(6, sig_1028) and "111101") or
(repeat(6, sig_1022) and "111110") or
(repeat(6, sig_1007) and "111011");
-- Behaviour of component 'mux_555' model 'mux'
mux_555 <=
(repeat(32, sig_1396) and sig_1613) or
(repeat(32, sig_1449) and sig_1612(31 downto 0));
-- Behaviour of component 'mux_551' model 'mux'
mux_551 <=
(repeat(32, sig_1118) and sig_1587(39 downto 8)) or
(repeat(32, sig_1088) and sig_1640) or
(repeat(32, sig_1332) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_553' model 'mux'
mux_553 <=
(repeat(32, sig_1411) and sig_1610(31 downto 0)) or
(repeat(32, sig_1111) and sig_1609(28 downto 0) & chenidct_aidx(2 downto 0)) or
(repeat(32, sig_1262) and sig_1609(31 downto 0)) or
(repeat(32, sig_1582) and sig_1610(28 downto 0) & chenidct_i(2 downto 0)) or
(repeat(32, sig_1477) and sig_1610(28 downto 0) & chenidct_aidx(2 downto 0));
-- Behaviour of component 'mux_549' model 'mux'
mux_549 <=
(repeat(32, sig_1323) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1274) and sig_1642) or
(repeat(32, sig_1324) and sig_1587(39 downto 8)) or
(repeat(32, sig_1463) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_545' model 'mux'
mux_545 <=
(repeat(32, sig_1118) and sig_1612(38 downto 7)) or
(repeat(32, sig_1040) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1351) and sig_1642) or
(repeat(32, sig_1463) and sig_1613);
-- Behaviour of component 'mux_547' model 'mux'
mux_547 <=
(repeat(32, sig_1349) and sig_1614(40 downto 9)) or
(repeat(32, sig_1001) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1413) and sig_1642) or
(repeat(32, sig_1463) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_543' model 'mux'
mux_543 <=
(repeat(32, sig_1088) and sig_1642) or
(repeat(32, sig_1581) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_731' model 'mux'
mux_731 <=
(repeat(8, sig_1508) and iquantize_qidx & "001101") or
(repeat(8, sig_1320) and iquantize_qidx & "000110") or
(repeat(8, sig_1315) and iquantize_qidx & "010101") or
(repeat(8, sig_1311) and iquantize_qidx & "011111") or
(repeat(8, sig_1301) and iquantize_qidx & "100101") or
(repeat(8, sig_1293) and iquantize_qidx & "100111") or
(repeat(8, sig_1361) and iquantize_qidx & "101100") or
(repeat(8, sig_1277) and iquantize_qidx & "000010") or
(repeat(8, sig_1276) and iquantize_qidx & "111001") or
(repeat(8, sig_1275) and iquantize_qidx & "010001") or
(repeat(8, sig_1270) and iquantize_qidx & "110000") or
(repeat(8, sig_1260) and iquantize_qidx & "101001") or
(repeat(8, sig_1259) and iquantize_qidx & "111100") or
(repeat(8, sig_1258) and iquantize_qidx & "011000") or
(repeat(8, sig_1256) and iquantize_qidx & "010110") or
(repeat(8, sig_1367) and iquantize_qidx & "111010") or
(repeat(8, sig_1371) and iquantize_qidx & "110111") or
(repeat(8, sig_1410) and iquantize_qidx & "011001") or
(repeat(8, sig_1360) and iquantize_qidx & "000000") or
(repeat(8, sig_1359) and iquantize_qidx & "001000") or
(repeat(8, sig_1358) and iquantize_qidx & "101011") or
(repeat(8, sig_1321) and iquantize_qidx & "110001") or
(repeat(8, sig_1564) and iquantize_qidx & "000101") or
(repeat(8, sig_1432) and iquantize_qidx & "010010") or
(repeat(8, sig_1255) and iquantize_qidx & "000011") or
(repeat(8, sig_1246) and iquantize_qidx & "100011") or
(repeat(8, sig_1239) and iquantize_qidx & "100001") or
(repeat(8, sig_1235) and iquantize_qidx & "100100") or
(repeat(8, sig_1231) and iquantize_qidx & "100110") or
(repeat(8, sig_1230) and iquantize_qidx & "100000") or
(repeat(8, sig_1228) and iquantize_qidx & "110101") or
(repeat(8, sig_1227) and iquantize_qidx & "101101") or
(repeat(8, sig_1226) and iquantize_qidx & "011110") or
(repeat(8, sig_1225) and iquantize_qidx & "000100") or
(repeat(8, sig_1223) and iquantize_qidx & "000111") or
(repeat(8, sig_1222) and iquantize_qidx & "110110") or
(repeat(8, sig_1221) and iquantize_qidx & "011101") or
(repeat(8, sig_1220) and iquantize_qidx & "101110") or
(repeat(8, sig_1166) and iquantize_qidx & "001110") or
(repeat(8, sig_1164) and iquantize_qidx & "110100") or
(repeat(8, sig_1156) and iquantize_qidx & "010100") or
(repeat(8, sig_1155) and iquantize_qidx & "101010") or
(repeat(8, sig_1099) and iquantize_qidx & "011010") or
(repeat(8, sig_1098) and iquantize_qidx & "101111") or
(repeat(8, sig_1097) and iquantize_qidx & "010011") or
(repeat(8, sig_1094) and iquantize_qidx & "010111") or
(repeat(8, sig_1093) and iquantize_qidx & "111000") or
(repeat(8, sig_1092) and iquantize_qidx & "011100") or
(repeat(8, sig_1091) and iquantize_qidx & "000001") or
(repeat(8, sig_1090) and iquantize_qidx & "001001") or
(repeat(8, sig_1086) and iquantize_qidx & "001011") or
(repeat(8, sig_1085) and iquantize_qidx & "110010") or
(repeat(8, sig_1084) and iquantize_qidx & "010000") or
(repeat(8, sig_1079) and iquantize_qidx & "001111") or
(repeat(8, sig_1076) and iquantize_qidx & "001010") or
(repeat(8, sig_1075) and iquantize_qidx & "110011") or
(repeat(8, sig_1074) and iquantize_qidx & "111111") or
(repeat(8, sig_1071) and iquantize_qidx & "011011") or
(repeat(8, sig_1063) and iquantize_qidx & "001100") or
(repeat(8, sig_1054) and iquantize_qidx & "101000") or
(repeat(8, sig_1050) and iquantize_qidx & "100010") or
(repeat(8, sig_1028) and iquantize_qidx & "111101") or
(repeat(8, sig_1022) and iquantize_qidx & "111110") or
(repeat(8, sig_1007) and iquantize_qidx & "111011");
-- Behaviour of component 'mux_727' model 'mux'
mux_727 <=
(repeat(7, sig_1534) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_i_c0(5 downto 0)) or
(repeat(7, sig_1552) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or
(repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0));
-- Behaviour of component 'mux_723' model 'mux'
mux_723 <=
(repeat(10, sig_1304) and decodehuffman_dc_tbl_no & decodehuffman_dc_p) or
(repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0));
-- Behaviour of component 'mux_719' model 'mux'
mux_719 <=
(repeat(7, sig_1505) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_i_c0(5 downto 0)) or
(repeat(7, sig_1547) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or
(repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0));
-- Behaviour of component 'mux_539' model 'mux'
mux_539 <=
(repeat(32, sig_1118) and sig_1624(31 downto 0)) or
(repeat(32, sig_1354) and sig_1642) or
(repeat(32, sig_1472) and sig_1639(29 downto 0) & "00");
-- Behaviour of component 'mux_541' model 'mux'
mux_541 <=
(repeat(32, sig_999) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1118) and sig_1613) or
(repeat(32, sig_1357) and sig_1642);
-- Behaviour of component 'mux_537' model 'mux'
mux_537 <=
(repeat(32, sig_1285) and sig_1642) or
(repeat(32, sig_1325) and sig_1639(29 downto 0) & "00") or
(repeat(32, sig_1463) and sig_1621(31 downto 0));
-- Behaviour of component 'mux_533' model 'mux'
mux_533 <=
(repeat(32, sig_1324) and sig_1614(40 downto 9)) or
(repeat(32, sig_1395) and sig_1627(39 downto 8));
-- Behaviour of component 'mux_535' model 'mux'
mux_535 <=
(repeat(32, sig_1118) and sig_1614(40 downto 9)) or
(repeat(32, sig_1463) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_715' model 'mux'
mux_715 <=
(repeat(10, sig_1284) and decodehuffman_ac_tbl_no & decodehuffman_ac_p) or
(repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0));
-- Behaviour of component 'mux_711' model 'mux'
mux_711 <=
(sig_1170 and decodehuffmcu_tbl_no) or
(sig_1189 and '1');
-- Behaviour of component 'mux_705' model 'mux'
mux_705 <=
(repeat(32, sig_1271) and sig_1632) or
(repeat(32, sig_1554) and "11111111111111111111111111111111") or
(repeat(32, sig_1561) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_706' model 'mux'
mux_706 <=
(repeat(7, sig_1553) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or
(repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0));
-- Behaviour of component 'mux_707' model 'mux'
mux_707 <=
(repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0)) or
(repeat(7, sig_1575) and decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0)) or
(repeat(7, sig_1577) and decodehuffman_dc_tbl_no & decodehuffman_dc_dhuff_ml);
-- Behaviour of component 'mux_531' model 'mux'
mux_531 <=
(repeat(32, sig_1324) and sig_1609(38 downto 7)) or
(repeat(32, sig_1395) and sig_1628(39 downto 8));
-- Behaviour of component 'mux_529' model 'mux'
mux_529 <=
(repeat(32, sig_1118) and sig_1610(38 downto 7)) or
(repeat(32, sig_1463) and sig_1613);
-- Behaviour of component 'mux_695' model 'mux'
mux_695 <=
(sig_1184 and '1') or
(sig_1453 and decodehuffmcu_tbl_no);
-- Behaviour of component 'mux_524' model 'mux'
mux_524 <=
(repeat(5, sig_1310) and decodehuffmcu_s(4 downto 0)) or
(repeat(5, sig_1482) and read_position(4 downto 0));
-- Behaviour of component 'mux_521' model 'mux'
mux_521 <=
(repeat(32, sig_1422) and "000000000000000000000000" & pgetc) or
(repeat(32, sig_1493) and or_802 & pgetc);
-- Behaviour of component 'mux_519' model 'mux'
mux_519 <=
(repeat(32, sig_1484) and sig_1614(31 downto 0)) or
(repeat(32, sig_1355) and sig_1624(31 downto 0)) or
(repeat(32, sig_1421) and "00000000000000000000000000000111") or
(repeat(32, sig_1493) and sig_1610(28 downto 0) & read_position(2 downto 0)) or
(repeat(32, sig_1497) and "11111111111111111111111111111111");
-- Behaviour of component 'mux_517' model 'mux'
mux_517 <=
(repeat(8, sig_1423) and "11111111") or
(repeat(8, sig_1425) and pgetc_temp);
-- Behaviour of component 'mux_507' model 'mux'
mux_507 <=
(repeat(32, sig_1008) and and_984) or
(repeat(32, sig_1345) and and_853) or
(repeat(32, sig_1497) and and_801);
-- Behaviour of component 'mux_505' model 'mux'
mux_505 <=
(repeat(32, sig_1167) and sig_1614(31 downto 0)) or
(repeat(32, sig_1197) and decodehuffmcu_s) or
(repeat(32, sig_1201) and decodehuffman_dc);
-- Behaviour of component 'mux_501' model 'mux'
mux_501 <=
(repeat(32, sig_1355) and or_845) or
(repeat(32, sig_1489) and sig_1626);
-- Behaviour of component 'mux_492' model 'mux'
mux_492 <=
(repeat(32, sig_1186) and sig_1652) or
(repeat(32, sig_1514) and "00000000000000000000000000000001") or
(repeat(32, sig_1544) and huff_make_dhuff_tb_ac_l);
-- Behaviour of component 'mux_488' model 'mux'
mux_488 <=
(repeat(32, sig_1499) and sig_1609(31 downto 0)) or
(repeat(32, sig_1504) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_490' model 'mux'
mux_490 <=
(repeat(32, sig_1498) and "00000000000000000000000000000001") or
(repeat(32, sig_1507) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_486' model 'mux'
mux_486 <=
(repeat(32, sig_1500) and sig_1610(31 downto 0)) or
(repeat(32, sig_1544) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_482' model 'mux'
mux_482 <=
(repeat(32, sig_1283) and sig_1610(31 downto 0)) or
(repeat(32, sig_1558) and sig_1635);
-- Behaviour of component 'mux_484' model 'mux'
mux_484 <=
(repeat(32, sig_1023) and sig_1609(31 downto 0)) or
(repeat(32, sig_1283) and huff_make_dhuff_tb_ac_code(30 downto 0) & '0');
-- Behaviour of component 'mux_480' model 'mux'
mux_480 <=
(repeat(32, sig_1514) and "00000000000000000000000000000001") or
(repeat(32, sig_1525) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_476' model 'mux'
mux_476 <=
(repeat(32, sig_1499) and huff_make_dhuff_tb_ac_i_c0);
-- Behaviour of component 'mux_478' model 'mux'
mux_478 <=
(repeat(9, sig_1511) and huff_make_dhuff_tb_ac_p(8 downto 0));
-- Behaviour of component 'mux_459' model 'mux'
mux_459 <=
(repeat(32, sig_1038) and huff_make_dhuff_tb_dc_l) or
(repeat(32, sig_1305) and sig_1656) or
(repeat(32, sig_1542) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_455' model 'mux'
mux_455 <=
(repeat(32, sig_1527) and sig_1609(31 downto 0)) or
(repeat(32, sig_1533) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_457' model 'mux'
mux_457 <=
(repeat(32, sig_1526) and "00000000000000000000000000000001") or
(repeat(32, sig_1536) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_453' model 'mux'
mux_453 <=
(repeat(32, sig_1038) and sig_1609(31 downto 0)) or
(repeat(32, sig_1528) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_449' model 'mux'
mux_449 <=
(repeat(32, sig_1033) and sig_1633) or
(repeat(32, sig_1068) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_451' model 'mux'
mux_451 <=
(repeat(32, sig_1035) and sig_1609(31 downto 0)) or
(repeat(32, sig_1068) and huff_make_dhuff_tb_dc_code(30 downto 0) & '0');
-- Behaviour of component 'mux_447' model 'mux'
mux_447 <=
(repeat(32, sig_1542) and "00000000000000000000000000000001") or
(repeat(32, sig_1563) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_443' model 'mux'
mux_443 <=
(repeat(32, sig_1527) and huff_make_dhuff_tb_dc_i_c0);
-- Behaviour of component 'mux_445' model 'mux'
mux_445 <=
(repeat(9, sig_1537) and huff_make_dhuff_tb_dc_p(8 downto 0));
-- Behaviour of component 'mux_430' model 'mux'
mux_430 <=
(repeat(32, sig_1284) and sig_1657);
-- Behaviour of component 'mux_422' model 'mux'
mux_422 <=
(repeat(32, sig_1565) and "00000000000000000000000000000001") or
(repeat(32, sig_1567) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_424' model 'mux'
mux_424 <=
(repeat(32, sig_1565) and "0000000000000000000000000000000" & buf_getb) or
(repeat(32, sig_1567) and sig_1610(30 downto 0) & buf_getb);
-- Behaviour of component 'mux_416' model 'mux'
mux_416 <=
(repeat(32, sig_1304) and sig_1659);
-- Behaviour of component 'mux_410' model 'mux'
mux_410 <=
(repeat(32, sig_1571) and "0000000000000000000000000000000" & buf_getb) or
(repeat(32, sig_1574) and sig_1610(30 downto 0) & buf_getb);
-- Behaviour of component 'mux_408' model 'mux'
mux_408 <=
(repeat(32, sig_1571) and "00000000000000000000000000000001") or
(repeat(32, sig_1574) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_398' model 'mux'
mux_398 <=
(repeat(32, sig_1026) and sig_1610(31 downto 0)) or
(repeat(32, sig_1341) and buf_getv) or
(repeat(32, sig_1344) and or_854);
-- Behaviour of component 'mux_400' model 'mux'
mux_400 <=
(repeat(32, sig_1030) and and_982) or
(repeat(32, sig_1342) and sig_1614(31 downto 0)) or
(repeat(32, sig_1579) and decodehuffman_dc);
-- Behaviour of component 'mux_392' model 'mux'
mux_392 <=
(repeat(32, sig_1454) and "00000000000000000000000000000001") or
(repeat(32, sig_1466) and sig_1610(31 downto 0)) or
(repeat(32, sig_1464) and sig_1610(27 downto 0) & decodehuffmcu_k(3 downto 0));
-- Behaviour of component 'mux_394' model 'mux'
mux_394 <=
(repeat(32, sig_1443) and sig_1610(31 downto 0)) or
(repeat(32, sig_1445) and "00000000000000000000000000000001");
-- Behaviour of component 'mux_378' model 'mux'
mux_378 <=
(repeat(8, sig_1070) and yuvtorgb_r(7 downto 0)) or
(repeat(8, sig_1234) and yuvtorgb_b(7 downto 0)) or
(repeat(8, sig_1237) and yuvtorgb_g(7 downto 0));
-- Behaviour of component 'mux_379' model 'mux'
mux_379 <=
(repeat(10, sig_1070) and yuvtorgb_p & "00" & yuvtorgb_i(5 downto 0)) or
(repeat(10, sig_1234) and yuvtorgb_p & "10" & yuvtorgb_i(5 downto 0)) or
(repeat(10, sig_1237) and yuvtorgb_p & "01" & yuvtorgb_i(5 downto 0));
-- Behaviour of component 'mux_375' model 'mux'
mux_375 <=
(repeat(2, sig_1020) and write4blocks_i) or
(repeat(2, sig_1196) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_373' model 'mux'
mux_373 <=
(repeat(2, sig_1005) and "10") or
(repeat(2, sig_1004) and "11") or
(repeat(2, sig_1019) and "01");
-- Behaviour of component 'mux_365' model 'mux'
mux_365 <=
(repeat(32, sig_1005) and sig_1614(31 downto 0)) or
(repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or
(repeat(32, sig_1196) and sig_1647(28 downto 0) & "000");
-- Behaviour of component 'mux_367' model 'mux'
mux_367 <=
(repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or
(repeat(32, sig_1021) and write4blocks_voffs) or
(repeat(32, sig_1196) and sig_1648(28 downto 0) & "000");
-- Behaviour of component 'mux_363' model 'mux'
mux_363 <=
(repeat(32, sig_1018) and sig_1610(31 downto 0)) or
(repeat(32, sig_1065) and writeoneblock_voffs);
-- Behaviour of component 'mux_359' model 'mux'
mux_359 <=
(repeat(32, sig_1012) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_361' model 'mux'
mux_361 <=
(repeat(32, sig_1017) and sig_1610(31 downto 0)) or
(repeat(32, sig_1081) and writeoneblock_hoffs);
-- Behaviour of component 'mux_347' model 'mux'
mux_347 <=
(repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or
(repeat(32, sig_1194) and sig_1648(28 downto 0) & "000");
-- Behaviour of component 'mux_345' model 'mux'
mux_345 <=
(repeat(32, sig_1005) and sig_1614(31 downto 0)) or
(repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or
(repeat(32, sig_1194) and sig_1647(28 downto 0) & "000");
-- Behaviour of component 'mux_341' model 'mux'
mux_341 <=
(repeat(3, sig_993) and decode_start_i(2 downto 0));
-- Behaviour of component 'mux_343' model 'mux'
mux_343 <=
(repeat(2, sig_993) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_339' model 'mux'
mux_339 <=
(repeat(3, sig_993) and "100") or
(repeat(3, sig_997) and "001");
-- Behaviour of component 'mux_335' model 'mux'
mux_335 <=
(repeat(32, sig_1060) and mux_965) or
(repeat(32, sig_1217) and sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24 downto 1));
-- Behaviour of component 'mux_337' model 'mux'
mux_337 <=
(repeat(3, sig_993) and "101") or
(repeat(3, sig_997) and "010");
-- Behaviour of component 'mux_333' model 'mux'
mux_333 <=
(repeat(32, sig_1060) and mux_969) or
(repeat(32, sig_1217) and sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24 downto 1));
-- Behaviour of component 'mux_331' model 'mux'
mux_331 <=
(repeat(32, sig_1060) and mux_967) or
(repeat(32, sig_1217) and sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24 downto 1));
-- Behaviour of component 'mux_323' model 'mux'
mux_323 <=
(repeat(6, sig_1345) and buf_getv_p(5 downto 0)) or
(repeat(6, sig_1355) and sig_1614(5 downto 0));
-- Behaviour of component 'mux_320' model 'mux'
mux_320 <=
(repeat(32, sig_1234) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_322' model 'mux'
mux_322 <=
(repeat(32, sig_1345) and current_read_byte) or
(repeat(32, sig_1355) and "000000000000000000000000" & pgetc);
-- Behaviour of component 'mux_317' model 'mux'
mux_317 <=
(repeat(2, sig_995) and "01") or
(repeat(2, sig_994) and "10") or
(repeat(2, sig_1045) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_314' model 'mux'
mux_314 <=
(repeat(32, sig_1324) and chenidct_a2) or
(repeat(32, sig_1118) and chenidct_a3) or
(repeat(32, sig_1217) and yuvtorgb_v(30) & yuvtorgb_v(30 downto 0)) or
(repeat(32, sig_1349) and chenidct_b3) or
(repeat(32, sig_1395) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_315' model 'mux'
mux_315 <=
(repeat(32, sig_1349) and "00000000000000000000000000110001") or
(repeat(32, sig_1101) and p_jinfo_mcuwidth) or
(repeat(32, sig_1118) and "00000000000000000000000000011001") or
(repeat(32, sig_1217) and "00000000000000000000000000001011") or
(repeat(32, sig_1324) and "00000000000000000000000011010101") or
(repeat(32, sig_1081) and writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12 downto 0)) or
(repeat(32, sig_1395) and "00000000000000000000000010110101") or
(repeat(32, sig_1433) and sig_1661);
-- Behaviour of component 'mux_316' model 'mux'
mux_316 <=
(repeat(32, sig_1349) and chenidct_b2) or
(repeat(32, sig_1101) and p_jinfo_mcuheight) or
(repeat(32, sig_1118) and chenidct_a0) or
(repeat(32, sig_1217) and yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28 downto 0)) or
(repeat(32, sig_1324) and chenidct_a1) or
(repeat(32, sig_1081) and writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12 downto 0)) or
(repeat(32, sig_1395) and sig_1610(31 downto 0)) or
(repeat(32, sig_1433) and sig_1639);
-- Behaviour of component 'mux_313' model 'mux'
mux_313 <=
(repeat(9, sig_1324) and "001000111") or
(repeat(9, sig_1118) and "011111011") or
(repeat(9, sig_1217) and "001011011") or
(repeat(9, sig_1349) and "111011001") or
(repeat(9, sig_1395) and "010110101");
-- Behaviour of component 'mux_308' model 'mux'
mux_308 <=
(repeat(3, sig_994) and "101") or
(repeat(3, sig_995) and "100") or
(repeat(3, sig_1046) and decode_start_i(2 downto 0));
-- Behaviour of component 'mux_306' model 'mux'
mux_306 <=
(repeat(41, sig_1451) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or
(repeat(41, sig_1308) and "00000000000000000000000000000000000000001") or
(repeat(41, sig_1324) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(41, sig_1355) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1217) and sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30 downto 0) & '0') or
(repeat(41, sig_1161) and "00000000000000000000000000000000000000010") or
(repeat(41, sig_1118) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or
(repeat(41, sig_1463) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2);
-- Behaviour of component 'mux_307' model 'mux'
mux_307 <=
(repeat(41, sig_1355) and "00000000000000000000000000000000000000111") or
(repeat(41, sig_1217) and sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31 downto 0)) or
(repeat(41, sig_1299) and sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30 downto 0)) or
(repeat(41, sig_1309) and p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width) or
(repeat(41, sig_1324) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(41, sig_1216) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or
(repeat(41, sig_1118) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1463) and chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3);
-- Behaviour of component 'mux_302' model 'mux'
mux_302 <=
(repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or
(repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or
(repeat(41, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3);
-- Behaviour of component 'mux_303' model 'mux'
mux_303 <=
(repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1471) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0);
-- Behaviour of component 'mux_294' model 'mux'
mux_294 <=
(repeat(2, sig_995) and "01") or
(repeat(2, sig_994) and "10") or
(repeat(2, sig_1045) and decode_start_i(1 downto 0));
-- Behaviour of component 'mux_290' model 'mux'
mux_290 <=
(repeat(41, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(41, sig_1376) and "00000000000000000000000000000000000000111") or
(repeat(41, sig_1363) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or
(repeat(41, sig_1355) and buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5 downto 0)) or
(repeat(41, sig_1349) and sig_1627) or
(repeat(41, sig_1534) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or
(repeat(41, sig_1324) and sig_1667(38 downto 0) & "00") or
(repeat(41, sig_1318) and "00000000000000000000000000000000000000010") or
(repeat(41, sig_1313) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or
(repeat(41, sig_1300) and "00000000000000000000000000000000000010001") or
(repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or
(repeat(41, sig_1292) and sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654) or
(repeat(41, sig_1289) and sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650) or
(repeat(41, sig_1280) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(41, sig_1550) and "00000000000000000000000000000000000010000") or
(repeat(41, sig_1569) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or
(repeat(41, sig_1576) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or
(repeat(41, sig_1505) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or
(repeat(41, sig_1491) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1486) and "00000000000000000000000000000000000010111") or
(repeat(41, sig_1485) and "00000000000000000000000000000000000000001") or
(repeat(41, sig_1440) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(41, sig_1434) and "00000000000000000000000000000000000111111") or
(repeat(41, sig_1244) and "000000000000000000000000000000000" & p_jinfo_num_components) or
(repeat(41, sig_1241) and "000000000000000000000000000000000" & get_sos_num_comp) or
(repeat(41, sig_1240) and "00000000000000000000000000000000001000000") or
(repeat(41, sig_1229) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(41, sig_1217) and sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28 downto 0) & "000") or
(repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or
(repeat(41, sig_1165) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1118) and sig_1627(39 downto 0) & '0') or
(repeat(41, sig_1089) and "00000000000000000000000000000000001000001") or
(repeat(41, sig_1077) and "00000000000000000000000000000000100000000") or
(repeat(41, sig_1049) and "00000000000000000000000000000000000000011") or
(repeat(41, sig_1048) and p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu) or
(repeat(41, sig_1032) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or
(repeat(41, sig_1015) and writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width) or
(repeat(41, sig_1014) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_hoffs(2 downto 0)) or
(repeat(41, sig_1010) and writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height) or
(repeat(41, sig_1009) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_voffs(2 downto 0));
-- Behaviour of component 'mux_291' model 'mux'
mux_291 <=
(repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or
(repeat(41, sig_1505) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or
(repeat(41, sig_1502) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or
(repeat(41, sig_1492) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or
(repeat(41, sig_1487) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or
(repeat(41, sig_1420) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i) or
(repeat(41, sig_1569) and decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code) or
(repeat(41, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(41, sig_1393) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or
(repeat(41, sig_1363) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(41, sig_1355) and "00000000000000000000000000000000000001000") or
(repeat(41, sig_1349) and sig_1628(38 downto 0) & "00") or
(repeat(41, sig_1342) and decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s) or
(repeat(41, sig_1336) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or
(repeat(41, sig_1324) and sig_1666(39 downto 0) & '0') or
(repeat(41, sig_1576) and decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code) or
(repeat(41, sig_1446) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or
(repeat(41, sig_1455) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or
(repeat(41, sig_1551) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or
(repeat(41, sig_1534) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or
(repeat(41, sig_1531) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or
(repeat(41, sig_1518) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or
(repeat(41, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or
(repeat(41, sig_1435) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or
(repeat(41, sig_1322) and get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length) or
(repeat(41, sig_1319) and read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word) or
(repeat(41, sig_1314) and get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length) or
(repeat(41, sig_1309) and p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height) or
(repeat(41, sig_1303) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or
(repeat(41, sig_1299) and sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640) or
(repeat(41, sig_1291) and sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8 downto 0)) or
(repeat(41, sig_1287) and get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j) or
(repeat(41, sig_1280) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or
(repeat(41, sig_1245) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or
(repeat(41, sig_1241) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or
(repeat(41, sig_1229) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(41, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y & "00000000") or
(repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(41, sig_1209) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or
(repeat(41, sig_1168) and buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n) or
(repeat(41, sig_1118) and sig_1628(37) & sig_1628(37 downto 0) & "00") or
(repeat(41, sig_1078) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or
(repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or
(repeat(41, sig_1051) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or
(repeat(41, sig_1048) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or
(repeat(41, sig_1037) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or
(repeat(41, sig_1025) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or
(repeat(41, sig_1016) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or
(repeat(41, sig_1011) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or
(repeat(41, sig_1005) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs);
-- Behaviour of component 'mux_292' model 'mux'
mux_292 <=
(repeat(32, sig_1294) and sig_1613) or
(repeat(32, sig_1427) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_286' model 'mux'
mux_286 <=
(repeat(32, sig_1047) and sig_1610(31 downto 0)) or
(repeat(32, sig_1052) and sig_1610(29 downto 0) & decode_start_currentmcu(1 downto 0));
-- Behaviour of component 'mux_275' model 'mux'
mux_275 <=
(repeat(32, sig_1396) and chenidct_i) or
(repeat(32, sig_1118) and chenidct_a1) or
(repeat(32, sig_1217) and sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23 downto 0) & sig_1666(6)) or
(repeat(32, sig_1294) and decode_start_i) or
(repeat(32, sig_1309) and sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16 downto 3)) or
(repeat(32, sig_1451) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 4)) or
(repeat(32, sig_1463) and chenidct_c3);
-- Behaviour of component 'mux_272' model 'mux'
mux_272 <=
(repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or
(repeat(39, sig_1118) and sig_1600(40 downto 2)) or
(repeat(39, sig_1309) and sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16 downto 0)) or
(repeat(39, sig_1449) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i);
-- Behaviour of component 'mux_274' model 'mux'
mux_274 <=
(repeat(32, sig_1397) and "00000000000000000000000000000001") or
(repeat(32, sig_1118) and chenidct_a2) or
(repeat(32, sig_1309) and "0000000000000000000000000000000" & and_864) or
(repeat(32, sig_1451) and "0000000000000000000000000000000" & and_789) or
(repeat(32, sig_1463) and chenidct_c2);
-- Behaviour of component 'mux_271' model 'mux'
mux_271 <=
(repeat(39, sig_1118) and sig_1668(38 downto 0)) or
(repeat(39, sig_1217) and sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31 downto 8)) or
(repeat(39, sig_1448) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_266' model 'mux'
mux_266 <=
(repeat(39, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(39, sig_1574) and decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30 downto 0)) or
(repeat(39, sig_1567) and decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30 downto 0)) or
(repeat(39, sig_1563) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or
(repeat(39, sig_1561) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or
(repeat(39, sig_1556) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 7)) or
(repeat(39, sig_1479) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or
(repeat(39, sig_1548) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or
(repeat(39, sig_1536) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or
(repeat(39, sig_1529) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or
(repeat(39, sig_1525) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or
(repeat(39, sig_1523) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or
(repeat(39, sig_1507) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or
(repeat(39, sig_1493) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31 downto 3)) or
(repeat(39, sig_1412) and "0000000" & chenidct_aidx) or
(repeat(39, sig_1477) and "0000000000" & chenidct_aidx(31 downto 3)) or
(repeat(39, sig_1466) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or
(repeat(39, sig_1464) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31 downto 4)) or
(repeat(39, sig_1451) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 3)) or
(repeat(39, sig_1443) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or
(repeat(39, sig_1441) and "0000000" & curhuffreadbuf_idx) or
(repeat(39, sig_1582) and "0000000000" & chenidct_i(31 downto 3)) or
(repeat(39, sig_1436) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or
(repeat(39, sig_1427) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or
(repeat(39, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or
(repeat(39, sig_1350) and "0000000" & chenidct_i(28 downto 0) & "001") or
(repeat(39, sig_1335) and get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num) or
(repeat(39, sig_1309) and sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16 downto 3)) or
(repeat(39, sig_1297) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or
(repeat(39, sig_1292) and sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653) or
(repeat(39, sig_1289) and sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649) or
(repeat(39, sig_1283) and huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size) or
(repeat(39, sig_1264) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or
(repeat(39, sig_1257) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or
(repeat(39, sig_1254) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or
(repeat(39, sig_1251) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or
(repeat(39, sig_1247) and "0000000" & readbuf_idx) or
(repeat(39, sig_1234) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or
(repeat(39, sig_1217) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 7)) or
(repeat(39, sig_1211) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or
(repeat(39, sig_1163) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31 downto 1)) or
(repeat(39, sig_1118) and sig_1666(39 downto 1)) or
(repeat(39, sig_1112) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(39, sig_1110) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or
(repeat(39, sig_1073) and "0000000000000000000000000000000000000" & sig_1663) or
(repeat(39, sig_1068) and huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size) or
(repeat(39, sig_1059) and "0000000" & jpeg2bmp_main_j) or
(repeat(39, sig_1056) and "0000000" & jpeg2bmp_main_i) or
(repeat(39, sig_1052) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31 downto 2)) or
(repeat(39, sig_1047) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or
(repeat(39, sig_1026) and decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff) or
(repeat(39, sig_1021) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31 downto 3)) or
(repeat(39, sig_1018) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or
(repeat(39, sig_1017) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or
(repeat(39, sig_1014) and writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31 downto 3)) or
(repeat(39, sig_1012) and writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff) or
(repeat(39, sig_1009) and writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31 downto 3)) or
(repeat(39, sig_1005) and write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31 downto 3));
-- Behaviour of component 'mux_265' model 'mux'
mux_265 <=
(repeat(39, sig_1112) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or
(repeat(39, sig_1110) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or
(repeat(39, sig_1027) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or
(repeat(39, sig_1012) and writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12 downto 0)) or
(repeat(39, sig_1006) and "00000000000" & decodehuffmcu_n) or
(repeat(39, sig_1309) and "00000000000000000000000000000000000000" & and_862) or
(repeat(39, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or
(repeat(39, sig_1546) and "111111111111111111111111111111111111111") or
(repeat(39, sig_1556) and "000000000000000000000000000000000000001") or
(repeat(39, sig_1292) and decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8 downto 0)) or
(repeat(39, sig_1289) and decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8 downto 0)) or
(repeat(39, sig_1264) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(39, sig_1118) and sig_1667(37) & sig_1667(37 downto 0)) or
(repeat(39, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(39, sig_1426) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_260' model 'mux'
mux_260 <=
(repeat(39, sig_1458) and "0000000000000000000000000000000" & read_byte) or
(repeat(39, sig_1324) and sig_1627(38 downto 0)) or
(repeat(39, sig_1395) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or
(repeat(39, sig_1544) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or
(repeat(39, sig_1451) and "00000000000000000000000000000000000000" & and_785) or
(repeat(39, sig_1217) and sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30 downto 7)) or
(repeat(39, sig_1118) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or
(repeat(39, sig_1038) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or
(repeat(39, sig_1463) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or
(repeat(39, sig_1438) and "000000000000000000000000000000000000001");
-- Behaviour of component 'mux_261' model 'mux'
mux_261 <=
(repeat(39, sig_1458) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or
(repeat(39, sig_1324) and sig_1628(39 downto 1)) or
(repeat(39, sig_1309) and sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16 downto 0)) or
(repeat(39, sig_1297) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or
(repeat(39, sig_1262) and "0000000" & chenidct_aidx) or
(repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or
(repeat(39, sig_1546) and sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31 downto 0)) or
(repeat(39, sig_1163) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31 downto 1)) or
(repeat(39, sig_1111) and "0000000000" & chenidct_aidx(31 downto 3)) or
(repeat(39, sig_1035) and huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code) or
(repeat(39, sig_1023) and huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code) or
(repeat(39, sig_1012) and "0000000" & writeoneblock_inidx) or
(repeat(39, sig_1567) and decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l) or
(repeat(39, sig_1574) and decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l) or
(repeat(39, sig_1451) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 1)) or
(repeat(39, sig_1527) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or
(repeat(39, sig_1499) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or
(repeat(39, sig_1398) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or
(repeat(39, sig_1335) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or
(repeat(39, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or
(repeat(39, sig_1436) and izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx);
-- Behaviour of component 'mux_262' model 'mux'
mux_262 <=
(repeat(32, sig_1056) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_257' model 'mux'
mux_257 <=
(repeat(32, sig_1059) and sig_1610(31 downto 0));
-- Behaviour of component 'nand_786' model 'nand'
nand_786 <= not (
sig_1605 and
sig_1606
);
-- Behaviour of component 'or_845' model 'or'
or_845 <=
sig_1629 or
buf_getv_rv;
-- Behaviour of component 'or_854' model 'or'
or_854 <=
sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or
buf_getv;
-- Behaviour of component 'or_866' model 'or'
or_866 <=
sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or
sig_1643;
-- Behaviour of component 'and_785' model 'and'
and_785 <=
nand_786 and
sig_1610(28);
-- Behaviour of component 'and_801' model 'and'
and_801 <=
sig_1636 and
current_read_byte;
-- Behaviour of component 'mux_761' model 'mux'
mux_761 <=
(repeat(9, sig_1118) and "000011001") or
(repeat(9, sig_1217) and "101100111") or
(repeat(9, sig_1324) and "001000111");
-- Behaviour of component 'mux_782' model 'mux'
mux_782 <=
(repeat(32, sig_1607) and sig_1660) or
(repeat(32, sig_1608) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'or_802' model 'or'
or_802 <=
current_read_byte(23 downto 0) or
"000000000000000000000000";
-- Behaviour of component 'and_803' model 'and'
and_803 <=
sig_1637 and
current_read_byte;
-- Behaviour of component 'mux_822' model 'mux'
mux_822 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_823' model 'mux'
mux_823 <=
(repeat(32, sig_1617) and mux_824);
-- Behaviour of component 'mux_776' model 'mux'
mux_776 <=
(repeat(32, sig_1617) and mux_777);
-- Behaviour of component 'mux_820' model 'mux'
mux_820 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_824' model 'mux'
mux_824 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_825' model 'mux'
mux_825 <=
(repeat(32, sig_1617) and mux_826);
-- Behaviour of component 'mux_760' model 'mux'
mux_760 <=
(repeat(32, sig_1118) and chenidct_a0) or
(repeat(32, sig_1217) and yuvtorgb_u(30) & yuvtorgb_u) or
(repeat(32, sig_1324) and chenidct_a2);
-- Behaviour of component 'and_789' model 'and'
and_789 <=
sig_1604 and
sig_1624(31);
-- Behaviour of component 'mux_759' model 'mux'
mux_759 <=
(repeat(6, sig_1118) and "111011") or
(repeat(6, sig_1217) and "100011") or
(repeat(6, sig_1324) and "010101");
-- Behaviour of component 'mux_768' model 'mux'
mux_768 <=
(repeat(32, sig_1436) and sig_1610(31 downto 0));
-- Behaviour of component 'mux_757' model 'mux'
mux_757 <=
(repeat(8, sig_1057) and sig_1646) or
(repeat(8, sig_1062) and outdata_image_height);
-- Behaviour of component 'mux_773' model 'mux'
mux_773 <=
(repeat(8, sig_1179) and outdata_image_height) or
(repeat(8, sig_1180) and outdata_image_width) or
(repeat(8, sig_1181) and write8_u8);
-- Behaviour of component 'mux_762' model 'mux'
mux_762 <=
(repeat(32, sig_1118) and chenidct_a3) or
(repeat(32, sig_1217) and yuvtorgb_v) or
(repeat(32, sig_1324) and chenidct_a1);
-- Behaviour of component 'mux_766' model 'mux'
mux_766 <=
(repeat(32, sig_1436) and sig_1609(31 downto 0));
-- Behaviour of component 'mux_781' model 'mux'
mux_781 <=
(repeat(32, sig_1608) and sig_1657) or
(repeat(32, sig_1607) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_797' model 'mux'
mux_797 <=
(repeat(32, sig_1617) and mux_798);
-- Behaviour of component 'mux_821' model 'mux'
mux_821 <=
(repeat(32, sig_1617) and mux_822);
-- Behaviour of component 'mux_826' model 'mux'
mux_826 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_778' model 'mux'
mux_778 <=
(repeat(32, sig_1607) and sig_1659) or
(repeat(32, sig_1608) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_827' model 'mux'
mux_827 <=
(repeat(32, sig_1617) and mux_828);
-- Behaviour of component 'mux_815' model 'mux'
mux_815 <=
(repeat(32, sig_1617) and mux_816);
-- Behaviour of component 'mux_798' model 'mux'
mux_798 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_816' model 'mux'
mux_816 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_817' model 'mux'
mux_817 <=
(repeat(32, sig_1617) and mux_818);
-- Behaviour of component 'mux_777' model 'mux'
mux_777 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_819' model 'mux'
mux_819 <=
(repeat(32, sig_1617) and mux_820);
-- Behaviour of component 'mux_783' model 'mux'
mux_783 <=
(repeat(32, sig_1608) and sig_1658) or
(repeat(32, sig_1607) and "000000000000000000000000" & read_byte);
-- Behaviour of component 'mux_795' model 'mux'
mux_795 <=
(repeat(32, sig_1617) and mux_796);
-- Behaviour of component 'mux_796' model 'mux'
mux_796 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_805' model 'mux'
mux_805 <=
(repeat(32, sig_1617) and mux_806);
-- Behaviour of component 'mux_806' model 'mux'
mux_806 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_807' model 'mux'
mux_807 <=
(repeat(32, sig_1617) and mux_808);
-- Behaviour of component 'mux_808' model 'mux'
mux_808 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_809' model 'mux'
mux_809 <=
(repeat(32, sig_1617) and mux_810);
-- Behaviour of component 'mux_810' model 'mux'
mux_810 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_811' model 'mux'
mux_811 <=
(repeat(32, sig_1617) and mux_812);
-- Behaviour of component 'mux_812' model 'mux'
mux_812 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_813' model 'mux'
mux_813 <=
(repeat(32, sig_1617) and mux_814);
-- Behaviour of component 'mux_814' model 'mux'
mux_814 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_818' model 'mux'
mux_818 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_828' model 'mux'
mux_828 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_829' model 'mux'
mux_829 <=
(repeat(32, sig_1617) and mux_830);
-- Behaviour of component 'mux_830' model 'mux'
mux_830 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_831' model 'mux'
mux_831 <=
(repeat(32, sig_1617) and mux_832);
-- Behaviour of component 'mux_832' model 'mux'
mux_832 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_836' model 'mux'
mux_836 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_837' model 'mux'
mux_837 <=
(repeat(32, sig_1617) and mux_838);
-- Behaviour of component 'mux_839' model 'mux'
mux_839 <=
(repeat(32, sig_1617) and mux_840);
-- Behaviour of component 'mux_840' model 'mux'
mux_840 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_841' model 'mux'
mux_841 <=
(repeat(32, sig_1617) and mux_842);
-- Behaviour of component 'mux_842' model 'mux'
mux_842 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_843' model 'mux'
mux_843 <=
(repeat(32, sig_1617) and mux_844);
-- Behaviour of component 'mux_856' model 'mux'
mux_856 <=
(repeat(32, sig_1617) and mux_857);
-- Behaviour of component 'and_864' model 'and'
and_864 <=
sig_1603 and
sig_1624(16);
-- Behaviour of component 'mux_870' model 'mux'
mux_870 <=
(repeat(32, sig_1599) and get_dqt_length) or
(repeat(32, sig_1669) and sig_1614(31 downto 0));
-- Behaviour of component 'mux_872' model 'mux'
mux_872 <=
(repeat(2, sig_1598) and "10");
-- Behaviour of component 'mux_875' model 'mux'
mux_875 <=
(repeat(32, sig_1616) and sig_1647);
-- Behaviour of component 'mux_891' model 'mux'
mux_891 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_892' model 'mux'
mux_892 <=
(repeat(32, sig_1617) and mux_893);
-- Behaviour of component 'mux_893' model 'mux'
mux_893 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_894' model 'mux'
mux_894 <=
(repeat(32, sig_1617) and mux_895);
-- Behaviour of component 'mux_895' model 'mux'
mux_895 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_896' model 'mux'
mux_896 <=
(repeat(32, sig_1623) and sig_1648) or
(repeat(32, sig_1616) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_897' model 'mux'
mux_897 <=
(repeat(32, sig_1616) and sig_1647);
-- Behaviour of component 'mux_898' model 'mux'
mux_898 <=
(repeat(32, sig_1617) and mux_899);
-- Behaviour of component 'mux_899' model 'mux'
mux_899 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_900' model 'mux'
mux_900 <=
(repeat(32, sig_1617) and mux_901);
-- Behaviour of component 'mux_901' model 'mux'
mux_901 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_902' model 'mux'
mux_902 <=
(repeat(32, sig_1617) and mux_903);
-- Behaviour of component 'mux_903' model 'mux'
mux_903 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_904' model 'mux'
mux_904 <=
(repeat(32, sig_1617) and mux_905);
-- Behaviour of component 'mux_905' model 'mux'
mux_905 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_906' model 'mux'
mux_906 <=
(repeat(32, sig_1617) and mux_907);
-- Behaviour of component 'mux_907' model 'mux'
mux_907 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_908' model 'mux'
mux_908 <=
(repeat(32, sig_1617) and mux_909);
-- Behaviour of component 'mux_917' model 'mux'
mux_917 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_918' model 'mux'
mux_918 <=
(repeat(32, sig_1617) and mux_919);
-- Behaviour of component 'mux_924' model 'mux'
mux_924 <=
(repeat(32, sig_1617) and mux_925);
-- Behaviour of component 'mux_925' model 'mux'
mux_925 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_928' model 'mux'
mux_928 <=
(repeat(32, sig_1617) and mux_929);
-- Behaviour of component 'mux_929' model 'mux'
mux_929 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_931' model 'mux'
mux_931 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_932' model 'mux'
mux_932 <=
(repeat(32, sig_1617) and mux_933);
-- Behaviour of component 'mux_934' model 'mux'
mux_934 <=
(repeat(32, sig_1617) and mux_935);
-- Behaviour of component 'mux_935' model 'mux'
mux_935 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_936' model 'mux'
mux_936 <=
(repeat(32, sig_1617) and mux_937);
-- Behaviour of component 'mux_937' model 'mux'
mux_937 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_938' model 'mux'
mux_938 <=
(repeat(32, sig_1617) and mux_939);
-- Behaviour of component 'mux_939' model 'mux'
mux_939 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_941' model 'mux'
mux_941 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_944' model 'mux'
mux_944 <=
(repeat(32, sig_1617) and mux_945);
-- Behaviour of component 'mux_945' model 'mux'
mux_945 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_946' model 'mux'
mux_946 <=
(repeat(32, sig_1617) and mux_947);
-- Behaviour of component 'mux_833' model 'mux'
mux_833 <=
(repeat(32, sig_1617) and mux_834);
-- Behaviour of component 'mux_834' model 'mux'
mux_834 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_835' model 'mux'
mux_835 <=
(repeat(32, sig_1617) and mux_836);
-- Behaviour of component 'mux_838' model 'mux'
mux_838 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_844' model 'mux'
mux_844 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_857' model 'mux'
mux_857 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_858' model 'mux'
mux_858 <=
(repeat(32, sig_1617) and mux_859);
-- Behaviour of component 'mux_859' model 'mux'
mux_859 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_874' model 'mux'
mux_874 <=
(repeat(32, sig_1623) and sig_1648) or
(repeat(32, sig_1616) and sig_1624(31 downto 0));
-- Behaviour of component 'mux_888' model 'mux'
mux_888 <=
(repeat(32, sig_1617) and mux_889);
-- Behaviour of component 'mux_889' model 'mux'
mux_889 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_913' model 'mux'
mux_913 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_914' model 'mux'
mux_914 <=
(repeat(32, sig_1617) and mux_915);
-- Behaviour of component 'mux_915' model 'mux'
mux_915 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_916' model 'mux'
mux_916 <=
(repeat(32, sig_1617) and mux_917);
-- Behaviour of component 'mux_933' model 'mux'
mux_933 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_940' model 'mux'
mux_940 <=
(repeat(32, sig_1617) and mux_941);
-- Behaviour of component 'mux_942' model 'mux'
mux_942 <=
(repeat(32, sig_1617) and mux_943);
-- Behaviour of component 'and_867' model 'and'
and_867 <=
sig_1670 and
sig_1594;
-- Behaviour of component 'mux_909' model 'mux'
mux_909 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_910' model 'mux'
mux_910 <=
(repeat(32, sig_1617) and mux_911);
-- Behaviour of component 'mux_911' model 'mux'
mux_911 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_920' model 'mux'
mux_920 <=
(repeat(32, sig_1617) and mux_921);
-- Behaviour of component 'mux_921' model 'mux'
mux_921 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_926' model 'mux'
mux_926 <=
(repeat(32, sig_1617) and mux_927);
-- Behaviour of component 'mux_927' model 'mux'
mux_927 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_943' model 'mux'
mux_943 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_886' model 'mux'
mux_886 <=
(sig_1601 and read_byte(0)) or
(sig_1602 and read_byte(0));
-- Behaviour of component 'mux_922' model 'mux'
mux_922 <=
(repeat(32, sig_1617) and mux_923);
-- Behaviour of component 'mux_923' model 'mux'
mux_923 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_930' model 'mux'
mux_930 <=
(repeat(32, sig_1617) and mux_931);
-- Behaviour of component 'mux_987' model 'mux'
mux_987 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'and_860' model 'and'
and_860 <=
sig_1637 and
buf_getv;
-- Behaviour of component 'and_881' model 'and'
and_881 <=
sig_1637 and
sig_1643;
-- Behaviour of component 'and_884' model 'and'
and_884 <=
"00000000000000000000000000010000" and
"000000000000000000000000" & read_byte;
-- Behaviour of component 'mux_890' model 'mux'
mux_890 <=
(repeat(32, sig_1617) and mux_891);
-- Behaviour of component 'mux_912' model 'mux'
mux_912 <=
(repeat(32, sig_1617) and mux_913);
-- Behaviour of component 'mux_919' model 'mux'
mux_919 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_948' model 'mux'
mux_948 <=
(repeat(32, sig_1617) and mux_949);
-- Behaviour of component 'mux_949' model 'mux'
mux_949 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_950' model 'mux'
mux_950 <=
(repeat(32, sig_1617) and mux_951);
-- Behaviour of component 'and_862' model 'and'
and_862 <=
sig_1595 and
sig_1614(16);
-- Behaviour of component 'mux_953' model 'mux'
mux_953 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_954' model 'mux'
mux_954 <=
(repeat(32, sig_1617) and mux_955);
-- Behaviour of component 'mux_955' model 'mux'
mux_955 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_951' model 'mux'
mux_951 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_952' model 'mux'
mux_952 <=
(repeat(32, sig_1617) and mux_953);
-- Behaviour of component 'mux_959' model 'mux'
mux_959 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_960' model 'mux'
mux_960 <=
(repeat(32, sig_1617) and mux_961);
-- Behaviour of component 'mux_961' model 'mux'
mux_961 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_965' model 'mux'
mux_965 <=
(repeat(32, sig_1617) and mux_966);
-- Behaviour of component 'mux_966' model 'mux'
mux_966 <=
(repeat(32, sig_1622) and yuvtorgb_r) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'and_876' model 'and'
and_876 <=
"00001111" and
"0000" & read_byte(7 downto 4);
-- Behaviour of component 'mux_956' model 'mux'
mux_956 <=
(repeat(32, sig_1617) and mux_957);
-- Behaviour of component 'mux_957' model 'mux'
mux_957 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_947' model 'mux'
mux_947 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_968' model 'mux'
mux_968 <=
(repeat(32, sig_1593) and yuvtorgb_b) or
(repeat(32, sig_1591) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_969' model 'mux'
mux_969 <=
(repeat(32, sig_1597) and mux_970);
-- Behaviour of component 'mux_970' model 'mux'
mux_970 <=
(repeat(32, sig_1586) and yuvtorgb_g) or
(repeat(32, sig_1589) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_980' model 'mux'
mux_980 <=
(repeat(32, sig_1617) and mux_981);
-- Behaviour of component 'mux_981' model 'mux'
mux_981 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of component 'mux_958' model 'mux'
mux_958 <=
(repeat(32, sig_1617) and mux_959);
-- Behaviour of component 'and_963' model 'and'
and_963 <=
sig_1615 and
sig_991;
-- Behaviour of component 'mux_986' model 'mux'
mux_986 <=
(repeat(32, sig_1617) and mux_987);
-- Behaviour of component 'mux_988' model 'mux'
mux_988 <=
(repeat(32, sig_1617) and mux_989);
-- Behaviour of component 'mux_989' model 'mux'
mux_989 <=
(repeat(32, sig_1622) and sig_1642) or
(repeat(32, sig_1625) and "00000000000000000000000011111111");
-- Behaviour of all components of model 'reg'
-- Registers with clock = sig_clock and no reset
process(sig_clock)
begin
if rising_edge(sig_clock) then
if sig_1437 = '1' then
izigzagmatrix_i <= mux_768;
end if;
if sig_1437 = '1' then
izigzagmatrix_out_idx <= mux_766;
end if;
if sig_1072 = '1' then
iquantize_qidx <= sig_1610(1 downto 0);
end if;
if sig_1061 = '1' then
write8_u8 <= mux_757;
end if;
if sig_1206 = '1' then
p_jinfo_image_height <= read_word;
end if;
if sig_1207 = '1' then
p_jinfo_image_width <= read_word;
end if;
if sig_1204 = '1' then
p_jinfo_num_components <= read_byte;
end if;
if sig_1219 = '1' then
p_jinfo_smp_fact <= mux_872;
end if;
if sig_1307 = '1' then
p_jinfo_mcuwidth <= sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17 downto 0);
end if;
if sig_1307 = '1' then
p_jinfo_mcuheight <= sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17 downto 0);
end if;
if sig_1100 = '1' then
p_jinfo_nummcu <= sig_1628(31 downto 0);
end if;
if sig_1273 = '1' then
i_jinfo_jpeg_data <= readbuf_idx;
end if;
if sig_1583 = '1' then
curhuffreadbuf_idx <= mux_671;
end if;
if sig_1042 = '1' then
outdata_image_width <= p_jinfo_image_width(7 downto 0);
end if;
if sig_1042 = '1' then
outdata_image_height <= p_jinfo_image_height(7 downto 0);
end if;
if sig_1340 = '1' then
readbuf_idx <= mux_648;
end if;
if sig_1053 = '1' then
read_byte <= sig_1644;
end if;
if sig_1249 = '1' then
read_word <= read_word_c & sig_1644;
end if;
if sig_1248 = '1' then
read_word_c <= sig_1644;
end if;
if sig_1205 = '1' then
next_marker <= next_marker_c;
end if;
if sig_1203 = '1' then
next_marker_c <= read_byte;
end if;
if sig_1210 = '1' then
get_sof_ci <= mux_633;
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_id <= get_sof_ci(1 downto 0);
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_h_samp_factor <= get_sof_ci(1 downto 0);
end if;
if sig_1208 = '1' then
get_sof_i_comp_info_quant_tbl_no <= get_sof_ci(1 downto 0);
end if;
if sig_1224 = '1' then
get_sos_num_comp <= read_byte;
end if;
if sig_1250 = '1' then
get_sos_i <= mux_622;
end if;
if sig_1272 = '1' then
get_sos_c <= read_byte(4);
end if;
if sig_1242 = '1' then
get_sos_cc <= read_byte;
end if;
if sig_1253 = '1' then
get_sos_ci <= mux_616;
end if;
if sig_1286 = '1' then
get_sos_j <= mux_614;
end if;
if sig_1243 = '1' then
get_sos_i_comp_info_dc_tbl_no <= get_sos_ci(1 downto 0);
end if;
if sig_1312 = '1' then
get_dht_length <= sig_1614(31 downto 0);
end if;
if sig_1199 = '1' then
get_dht_index <= mux_886;
end if;
if sig_1541 = '1' then
get_dht_i <= mux_602;
end if;
if sig_1456 = '1' then
get_dht_count <= mux_600;
end if;
if sig_1199 = '1' then
get_dht_is_ac <= sig_1602;
end if;
if sig_1316 = '1' then
get_dqt_length <= mux_593;
end if;
if sig_1302 = '1' then
get_dqt_prec <= read_byte(7 downto 4);
end if;
if sig_1302 = '1' then
get_dqt_num <= read_byte(1 downto 0);
end if;
if sig_1333 = '1' then
get_dqt_i <= mux_587;
end if;
if sig_1338 = '1' then
get_dqt_tmp <= mux_585;
end if;
if sig_1347 = '1' then
read_markers_unread_marker <= mux_580;
end if;
if sig_1352 = '1' then
read_markers_sow_soi <= sig_1353;
end if;
if sig_1447 = '1' then
chenidct_i <= mux_555;
end if;
if sig_1476 = '1' then
chenidct_aidx <= mux_553;
end if;
if sig_1462 = '1' then
chenidct_a0 <= mux_551;
end if;
if sig_1439 = '1' then
chenidct_a1 <= mux_549;
end if;
if sig_1584 = '1' then
chenidct_a2 <= mux_547;
end if;
if sig_1465 = '1' then
chenidct_a3 <= mux_545;
end if;
if sig_1459 = '1' then
chenidct_b0 <= mux_543;
end if;
if sig_1356 = '1' then
chenidct_b1 <= mux_541;
end if;
if sig_1478 = '1' then
chenidct_b2 <= mux_539;
end if;
if sig_1460 = '1' then
chenidct_b3 <= mux_537;
end if;
if sig_1461 = '1' then
chenidct_c0 <= mux_535;
end if;
if sig_1394 = '1' then
chenidct_c1 <= mux_533;
end if;
if sig_1394 = '1' then
chenidct_c2 <= mux_531;
end if;
if sig_1461 = '1' then
chenidct_c3 <= mux_529;
end if;
if sig_1494 = '1' then
current_read_byte <= mux_521;
end if;
if sig_1424 = '1' then
pgetc <= mux_517;
end if;
if sig_1442 = '1' then
pgetc_temp <= sig_1644;
end if;
if sig_1483 = '1' then
buf_getb <= sig_1481;
end if;
if sig_1495 = '1' then
buf_getv <= mux_507;
end if;
if sig_1200 = '1' then
buf_getv_n <= mux_505;
end if;
if sig_1490 = '1' then
buf_getv_p <= sig_1614(31 downto 0);
end if;
if sig_1488 = '1' then
buf_getv_rv <= mux_501;
end if;
if sig_1521 = '1' then
huff_make_dhuff_tb_ac <= huff_make_dhuff_tb_ac_p_dhtbl_ml;
end if;
if sig_1187 = '1' then
huff_make_dhuff_tb_ac_tbl_no <= sig_1184;
end if;
if sig_1543 = '1' then
huff_make_dhuff_tb_ac_p_dhtbl_ml <= mux_492;
end if;
if sig_1506 = '1' then
huff_make_dhuff_tb_ac_i_c0 <= mux_490;
end if;
if sig_1503 = '1' then
huff_make_dhuff_tb_ac_j <= mux_488;
end if;
if sig_1545 = '1' then
huff_make_dhuff_tb_ac_p <= mux_486;
end if;
if sig_1282 = '1' then
huff_make_dhuff_tb_ac_code <= mux_484;
end if;
if sig_1557 = '1' then
huff_make_dhuff_tb_ac_size <= mux_482;
end if;
if sig_1524 = '1' then
huff_make_dhuff_tb_ac_l <= mux_480;
end if;
if sig_1559 = '1' then
huff_make_dhuff_tb_dc <= huff_make_dhuff_tb_dc_p_dhtbl_ml;
end if;
if sig_1306 = '1' then
huff_make_dhuff_tb_dc_tbl_no <= sig_1189;
end if;
if sig_1539 = '1' then
huff_make_dhuff_tb_dc_p_dhtbl_ml <= mux_459;
end if;
if sig_1535 = '1' then
huff_make_dhuff_tb_dc_i_c0 <= mux_457;
end if;
if sig_1532 = '1' then
huff_make_dhuff_tb_dc_j <= mux_455;
end if;
if sig_1538 = '1' then
huff_make_dhuff_tb_dc_p <= mux_453;
end if;
if sig_1067 = '1' then
huff_make_dhuff_tb_dc_code <= mux_451;
end if;
if sig_1069 = '1' then
huff_make_dhuff_tb_dc_size <= mux_449;
end if;
if sig_1562 = '1' then
huff_make_dhuff_tb_dc_l <= mux_447;
end if;
if sig_1572 = '1' then
decodehuffman_ac <= mux_430;
end if;
if sig_1452 = '1' then
decodehuffman_ac_tbl_no <= decodehuffmcu_tbl_no;
end if;
if sig_1452 = '1' then
decodehuffman_ac_dhuff_ml <= sig_1652(5 downto 0);
end if;
if sig_1566 = '1' then
decodehuffman_ac_code <= mux_424;
end if;
if sig_1566 = '1' then
decodehuffman_ac_l <= mux_422;
end if;
if sig_1288 = '1' then
decodehuffman_ac_p <= sig_1614(8 downto 0);
end if;
if sig_1580 = '1' then
decodehuffman_dc <= mux_416;
end if;
if sig_1509 = '1' then
decodehuffman_dc_tbl_no <= sig_1662;
end if;
if sig_1169 = '1' then
decodehuffman_dc_dhuff_ml <= sig_1656(5 downto 0);
end if;
if sig_1573 = '1' then
decodehuffman_dc_code <= mux_410;
end if;
if sig_1573 = '1' then
decodehuffman_dc_l <= mux_408;
end if;
if sig_1290 = '1' then
decodehuffman_dc_p <= sig_1614(8 downto 0);
end if;
if sig_1509 = '1' then
decodehuffmcu_bufdim1 <= decode_block_in_buf_idx;
end if;
if sig_1578 = '1' then
decodehuffmcu_s <= mux_400;
end if;
if sig_1343 = '1' then
decodehuffmcu_diff <= mux_398;
end if;
if sig_1509 = '1' then
decodehuffmcu_tbl_no <= sig_1662;
end if;
if sig_1444 = '1' then
decodehuffmcu_i <= mux_394;
end if;
if sig_1467 = '1' then
decodehuffmcu_k <= mux_392;
end if;
if sig_1029 = '1' then
decodehuffmcu_n <= and_983;
end if;
if sig_1195 = '1' then
writeoneblock_outidx <= mux_375;
end if;
if sig_1195 = '1' then
writeoneblock_indim1 <= mux_373;
end if;
if sig_1195 = '1' then
writeoneblock_width <= p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width;
end if;
if sig_1195 = '1' then
writeoneblock_height <= p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height;
end if;
if sig_1195 = '1' then
writeoneblock_voffs <= mux_367;
end if;
if sig_1195 = '1' then
writeoneblock_hoffs <= mux_365;
end if;
if sig_1064 = '1' then
writeoneblock_i <= mux_363;
end if;
if sig_1080 = '1' then
writeoneblock_e <= mux_361;
end if;
if sig_1066 = '1' then
writeoneblock_inidx <= mux_359;
end if;
if sig_1082 = '1' then
writeoneblock_diff <= sig_1628(12 downto 0);
end if;
if sig_996 = '1' then
writeblock_i <= decode_start_i(1 downto 0);
end if;
if sig_1191 = '1' then
write4blocks_i <= decode_start_i(1 downto 0);
end if;
if sig_1193 = '1' then
write4blocks_voffs <= mux_347;
end if;
if sig_1192 = '1' then
write4blocks_hoffs <= mux_345;
end if;
if sig_998 = '1' then
yuvtorgb_p <= mux_343;
end if;
if sig_998 = '1' then
yuvtorgb_yidx <= mux_341;
end if;
if sig_998 = '1' then
yuvtorgb_uidx <= mux_339;
end if;
if sig_998 = '1' then
yuvtorgb_vidx <= mux_337;
end if;
if sig_1218 = '1' then
yuvtorgb_r <= mux_335;
end if;
if sig_1218 = '1' then
yuvtorgb_g <= mux_333;
end if;
if sig_1218 = '1' then
yuvtorgb_b <= mux_331;
end if;
if sig_1298 = '1' then
yuvtorgb_y <= sig_1642(23 downto 0);
end if;
if sig_1298 = '1' then
yuvtorgb_u <= sig_1624(30 downto 0);
end if;
if sig_1298 = '1' then
yuvtorgb_v <= sig_1614(31 downto 0);
end if;
if sig_1233 = '1' then
yuvtorgb_i <= mux_320;
end if;
if sig_1044 = '1' then
decode_block_comp_no <= mux_317;
end if;
if sig_1044 = '1' then
decode_block_out_buf_idx <= mux_308;
end if;
if sig_1044 = '1' then
decode_block_in_buf_idx <= mux_294;
end if;
if sig_1430 = '1' then
decode_start_i <= mux_292;
end if;
if sig_1182 = '1' then
decode_start_currentmcu <= mux_286;
end if;
if sig_1055 = '1' then
jpeg2bmp_main_i <= mux_262;
end if;
if sig_1058 = '1' then
jpeg2bmp_main_j <= mux_257;
end if;
if sig_1178 = '1' then
read8_ret0_195 <= stdin_data;
end if;
end if;
end process;
-- Registers with clock = sig_clock and reset = sig_reset active '1'
process(sig_clock, sig_reset)
begin
if sig_reset = '1' then
read_position <= "11111111111111111111111111111111";
else
if rising_edge(sig_clock) then
if sig_1496 = '1' then
read_position <= mux_519;
end if;
end if;
end if;
end process;
-- Remaining signal assignments
-- Those who are not assigned by component instantiation
sig_clock <= clock;
sig_reset <= reset;
augh_test_159 <= sig_1615;
augh_test_26 <= sig_1616;
augh_test_49 <= sig_1616;
augh_test_52 <= sig_1616;
augh_test_53 <= and_867;
augh_test_67 <= sig_1618;
augh_test_72 <= sig_1615;
augh_test_77 <= sig_1616;
augh_test_83 <= sig_1618;
augh_test_89 <= sig_1615;
augh_test_90 <= sig_1669;
augh_test_105 <= sig_1615;
augh_test_106 <= sig_1615;
augh_test_107 <= sig_1615;
augh_test_111 <= sig_1616;
augh_test_114 <= sig_1618;
augh_test_115 <= sig_1618;
augh_test_119 <= sig_1615;
augh_test_120 <= sig_1615;
augh_test_122 <= and_963;
augh_test_125 <= sig_1615;
augh_test_127 <= sig_1615;
augh_test_128 <= sig_1615;
augh_test_130 <= and_976;
augh_test_133 <= sig_1615;
augh_test_136 <= sig_1618;
augh_test_138 <= sig_1616;
augh_test_142 <= sig_1618;
augh_test_144 <= sig_1616;
augh_test_151 <= sig_1615;
augh_test_152 <= sig_1615;
augh_test_155 <= sig_1618;
augh_test_165 <= sig_1616;
augh_test_166 <= sig_1616;
augh_test_167 <= sig_1616;
augh_test_168 <= sig_1616;
sig_start <= start;
augh_test_171 <= sig_1615;
augh_test_178 <= sig_1615;
augh_test_179 <= sig_1615;
augh_test_182 <= sig_1616;
augh_test_183 <= sig_1615;
augh_test_184 <= sig_1615;
augh_test_186 <= sig_1616;
augh_test_187 <= sig_1615;
augh_test_188 <= sig_1615;
augh_test_189 <= sig_1615;
sig_1671 <= "000000000000000000000000" & pgetc_temp;
sig_1672 <= "000000000000000000000000000000" & p_jinfo_smp_fact;
sig_1673 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1674 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1675 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1676 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1677 <= "000000000000000000000000" & next_marker_c;
sig_1678 <= "000000000000000000000000" & pgetc_temp;
sig_1679 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g;
sig_1680 <= "000000000000000000000000" & read_byte;
sig_1681 <= "000000000000000000000000" & next_marker_c;
sig_1682 <= "0000000000000000000000000000" & get_dqt_prec;
sig_1683 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1684 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1685 <= "0000000000000000000000000000000" & get_dht_is_ac;
sig_1686 <= "0000000000000000000000000000000" & get_dht_is_ac;
sig_1687 <= "0000" & decodehuffmcu_n;
sig_1688 <= sig_1612(23 downto 0) & sig_1667(7);
sig_1689 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b;
sig_1690 <= "00000000000000000000000" & mux_313;
sig_1691 <= writeoneblock_indim1 & writeoneblock_outidx & writeoneblock_inidx(5 downto 0);
sig_1692 <= yuvtorgb_uidx & yuvtorgb_i(5 downto 0);
sig_1693 <= jpeg2bmp_main_i(1 downto 0) & jpeg2bmp_main_j(12 downto 0);
sig_1694 <= writeoneblock_outidx & sig_1610(12 downto 0);
sig_1695 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0);
sig_1696 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0);
sig_1697 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0);
sig_1698 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0);
sig_1699 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0);
sig_1700 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0);
sig_1701 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0);
sig_1702 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0);
sig_1703 <= get_dht_index & get_dht_i(8 downto 0);
sig_1704 <= get_dht_index & get_dht_i(5 downto 0);
sig_1705 <= get_dht_index & get_dht_i(8 downto 0);
sig_1706 <= get_dht_index & get_dht_i(5 downto 0);
sig_1707 <= sig_1610(1 downto 0) & sig_1645;
sig_1708 <= "0000000000000000" & get_dqt_tmp;
sig_1709 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1710 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1711 <= "000000000000000000000000" & read_markers_unread_marker;
sig_1712 <= "00000000000000000000000011" & mux_759;
sig_1713 <= "00000000000000000000000" & mux_761;
sig_1714 <= "0000000000000000000000000000000" & read_markers_sow_soi;
sig_1715 <= "0000000000000000000000000000" & get_dqt_prec;
sig_1716 <= "000000000000000000000000" & read_markers_unread_marker;
-- Remaining top-level ports assignments
-- Those who are not assigned by component instantiation
stdout_data <= mux_773;
stdin_rdy <= sig_1178;
end architecture;
| gpl-2.0 | 5865923ef6f6963fdd19fcdfc321d5b7 | 0.656191 | 2.622033 | false | false | false | false |
nickg/nvc | test/regress/func19.vhd | 1 | 549 | entity func19 is
end entity;
architecture test of func19 is
function maybe_not_return (x : integer) return integer is
begin
if x > 0 then
return x * 2;
end if;
end function;
signal x, y : integer := 0;
begin
p1: y <= maybe_not_return(x);
p2: process is
begin
x <= 55;
wait for 1 ns;
assert y = 110;
x <= -1;
wait for 1 ns;
assert false report "should not reach here: " & integer'image(y);
wait;
end process;
end architecture;
| gpl-3.0 | 3b591094d624aab0dc9fa9c388a3b75f | 0.542805 | 3.709459 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_22.vhd | 4 | 2,483 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity mux4 is
port ( i0, i1, i2, i3, sel0, sel1 : in bit;
z : out bit );
end entity mux4;
-- end of code from book
----------------------------------------------------------------
architecture functional of mux4 is
begin
out_select : process (sel0, sel1, i0, i1, i2, i3) is
subtype bits_2 is bit_vector(1 downto 0);
begin
case bits_2'(sel1, sel0) is
when "00" => z <= i0;
when "01" => z <= i1;
when "10" => z <= i2;
when "11" => z <= i3;
end case;
end process out_select;
end architecture functional;
----------------------------------------------------------------
entity ch_05_22 is
end entity ch_05_22;
----------------------------------------------------------------
architecture test of ch_05_22 is
signal select_line, line0, line1, result_line : bit;
begin
-- code from book:
a_mux : entity work.mux4
port map ( sel0 => select_line, i0 => line0, i1 => line1,
z => result_line,
sel1 => '0', i2 => '1', i3 => '1' );
-- end of code from book
----------------
stimulus : process is
begin
wait for 5 ns;
line0 <= '1'; wait for 5 ns;
line1 <= '1'; wait for 5 ns;
select_line <= '1'; wait for 5 ns;
line1 <= '0'; wait for 5 ns;
line0 <= '0'; wait for 5 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 93b2da4cda5a5ad2c93db1f4f6ab82ea | 0.522352 | 3.773556 | false | false | false | false |
nickg/nvc | test/regress/record22.vhd | 1 | 1,356 | package pack is
type r1 is record
x : integer;
y : character;
end record;
type r1_vec is array (natural range <>) of r1;
type r2 is record
p : r1;
q : r1_vec(1 to 2);
end record;
type r2_vec is array (natural range <>) of r2;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in r2;
y : out r2_vec(1 to 3) );
end entity;
architecture test of sub is
begin
p1: process is
begin
wait for 1 ns;
assert x = ( ( 1, '2' ), ( ( 3, '4' ), ( 5, '6' ) ) );
y(3) <= ( ( 7, 'a' ), ( ( 8, 'b' ), ( 9, 'c' ) ) );
wait on x;
assert x = ( ( 1, '2' ), ( ( 42, '4' ), ( 5, '6' ) ) );
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record22 is
end entity;
use work.pack.all;
architecture test of record22 is
signal s : r2;
signal t : r2_vec(1 to 3);
begin
uut: entity work.sub port map ( s, t );
main: process is
begin
s <= ( ( 1, '2' ), ( ( 3, '4' ), ( 5, '6' ) ) );
wait for 2 ns;
assert t(3) = ( ( 7, 'a' ), ( ( 8, 'b' ), ( 9, 'c' ) ) );
s.q(1).x <= 42;
wait;
end process;
end architecture;
| gpl-3.0 | 0c745bfe597dce14fce224babeb89a04 | 0.406342 | 3.190588 | false | false | false | false |
lfmunoz/vhdl | templates/sip_cmd/stellar_generic_cmd.vhd | 3 | 10,351 | --------------------------------------------------------------------------------
-- file name : fmc144_stellar_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity -fmc144_stellar_cmd
-- arch_itecture - arch_fmc144_stellar_cmd
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-01-2009 new version
-- 31-08-2009 added the mailbox input port
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity stellar_generic_cmd is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end entity stellar_generic_cmd;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture arch_stellar_cmd of stellar_generic_cmd is
-----------------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------------
constant CMD_WR : std_logic_vector(3 downto 0) := x"1";
constant CMD_RD : std_logic_vector(3 downto 0) := x"2";
constant CMD_RD_ACK : std_logic_vector(3 downto 0) := x"4";
-----------------------------------------------------------------------------------
-- Dignal declarations
-----------------------------------------------------------------------------------
signal register_wr : std_logic;
signal register_rd : std_logic;
signal out_cmd_val_sig : std_logic;
signal in_reg_addr_sig : std_logic_vector(27 downto 0);
signal mbx_in_val_sig : std_logic;
signal mbx_received : std_logic;
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component;
-----------------------------------------------------------------------------------
-- Begin
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr,
inbusy => open,
pulseout => out_reg_val
);
p2p1: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_rd,
inbusy => open,
pulseout => in_reg_req
);
p2p2: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd,
rst => reset,
pulsein => in_reg_val,
inbusy => open,
pulseout => out_cmd_val_sig
);
p2p3: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => mbx_in_val,
inbusy => open,
pulseout => mbx_in_val_sig
);
-----------------------------------------------------------------------------------
-- Synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process (reset, clk_cmd)
begin
if (reset = '1') then
in_reg_addr_sig <= (others => '0');
register_rd <= '0';
mbx_received <= '0';
out_cmd <= (others => '0');
out_cmd_val <= '0';
elsif (clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig = '1' and mbx_in_val_sig = '1') then
mbx_received <= '1';
elsif( mbx_received = '1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig = '1') then
out_cmd(31 downto 0) <= in_reg;
out_cmd(59 downto 32) <= in_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_RD_ACK;
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= start_addr;
out_cmd(63 downto 60) <= (others=>'0');
else
out_cmd(63 downto 0) <= (others=>'0');
end if;
if (out_cmd_val_sig = '1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(reset, clk_cmd)
begin
if (reset = '1') then
out_reg_addr <= (others => '0');
out_reg <= (others => '0');
register_wr <= '0';
elsif(clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
out_reg_addr <= in_cmd(59 downto 32) - start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
-----------------------------------------------------------------------------------
-- End
-----------------------------------------------------------------------------------
end architecture arch_stellar_cmd;
| mit | 418ac6e8588d2bbf142a2516c9f3f67f | 0.465172 | 4.268454 | false | false | false | false |
LaurentCabaret/pyVhdl2Sch | datas/test_files/C9.vhd | 1 | 703 | library ieee;
use ieee.std_logic_1164.all;
package a_pkg is
function x_res (to_resolve: std_logic_vector) return std_ulogic;
end a_pkg;
package body a_pkg is
function x_res (to_resolve: std_logic_vector) return std_ulogic is
variable r: std_ulogic;
begin
r := 'Z';
for i in to_resolve'range loop
r := r or to_resolve(i);
end loop;
return r;
end function x_res;
end a_pkg;
library ieee;
use ieee.std_logic_1164.all;
use work.a_pkg.all;
entity foo is
port (
signal a_signal: in std_logic;
signal b: in std_logic;
signal c: in std_logic;
signal p: out x_res std_logic
);
end foo;
architecture fum of foo is
begin
p <= a;
p <= b;
p <= c;
end architecture; | bsd-2-clause | 706af41ee9444163c7e9cd8b1f5f7b2c | 0.662873 | 2.584559 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug24326/tb_thingy7.vhdl | 2 | 353 | entity tb_thingy is
end tb_thingy;
architecture tb of tb_thingy is
component thingy is
generic (
a_a : integer
);
port (
x_x : in bit;
y_y : out bit
);
end component;
signal stimuli : bit;
signal response : bit;
begin
dut : thingy
generic map (
a_a => 42
)
port map (
x%x => stimuli, -- <==
y_y => response
);
end tb;
| gpl-2.0 | cf1395eae4bda50fe20e4c05c762c2c9 | 0.592068 | 2.557971 | false | false | false | false |
nickg/nvc | test/bounds/case3.vhd | 1 | 454 | entity case3 is
end entity;
architecture test of case3 is
signal s : bit_vector(1 to 3);
signal t : bit;
begin
p1: process (s) is
begin
case s is
when "100" =>
t <= '1';
when "101" =>
t <= '0';
when "100" => -- Error
t <= '1';
when others =>
null;
end case;
end process;
end architecture;
| gpl-3.0 | b8522136ca556275f99dd29a36aee9b6 | 0.405286 | 4.09009 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/hdl/design_1.vhd | 1 | 252,032 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016
--Date : Thu Jun 23 02:18:07 2016
--Host : darkin-UX303LN running 64-bit elementary OS Freya
--Command : generate_target design_1.bd
--Design : design_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1R706YB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1R706YB;
architecture STRUCTURE of m00_couplers_imp_1R706YB is
component design_1_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= auto_pc_to_m00_couplers_ARID(0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= auto_pc_to_m00_couplers_AWID(0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(63 downto 0) <= auto_pc_to_m00_couplers_WDATA(63 downto 0);
M_AXI_wid(0) <= auto_pc_to_m00_couplers_WID(0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_pc_to_m00_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(0) <= m00_couplers_to_auto_pc_BID(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(63 downto 0) <= m00_couplers_to_auto_pc_RDATA(63 downto 0);
S_AXI_rid(0) <= m00_couplers_to_auto_pc_RID(0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(63 downto 0) <= S_AXI_wdata(63 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(7 downto 0) <= S_AXI_wstrb(7 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_1_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => auto_pc_to_m00_couplers_ARID(0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => auto_pc_to_m00_couplers_AWID(0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(0) => auto_pc_to_m00_couplers_BID(0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => auto_pc_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(0) => auto_pc_to_m00_couplers_RID(0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => auto_pc_to_m00_couplers_WDATA(63 downto 0),
m_axi_wid(0) => auto_pc_to_m00_couplers_WID(0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_pc_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(0) => m00_couplers_to_auto_pc_ARID(0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(0) => m00_couplers_to_auto_pc_AWID(0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(0) => m00_couplers_to_auto_pc_BID(0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(63 downto 0) => m00_couplers_to_auto_pc_RDATA(63 downto 0),
s_axi_rid(0) => m00_couplers_to_auto_pc_RID(0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(63 downto 0) => m00_couplers_to_auto_pc_WDATA(63 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(7 downto 0) => m00_couplers_to_auto_pc_WSTRB(7 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_OBU1DD is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_OBU1DD;
architecture STRUCTURE of m00_couplers_imp_OBU1DD is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1FBREZ4 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_1FBREZ4;
architecture STRUCTURE of m01_couplers_imp_1FBREZ4 is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_MVV5YQ is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_MVV5YQ;
architecture STRUCTURE of m02_couplers_imp_MVV5YQ is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1GHG26R is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1GHG26R;
architecture STRUCTURE of m03_couplers_imp_1GHG26R is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1CFO1MB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1CFO1MB;
architecture STRUCTURE of s00_couplers_imp_1CFO1MB is
component design_1_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_1_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_7HNO1D is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s00_couplers_imp_7HNO1D;
architecture STRUCTURE of s00_couplers_imp_7HNO1D is
component design_1_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_1_auto_us_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_RVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID;
M_AXI_rready <= auto_us_to_s00_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_us_ARREADY;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID;
auto_us_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_us_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_us_RREADY <= S_AXI_rready;
auto_us: component design_1_auto_us_0
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s00_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_us_to_s00_couplers_RLAST,
m_axi_rready => auto_us_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s00_couplers_RVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1(0),
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s00_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_us_ARVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s00_couplers_to_auto_us_RLAST,
s_axi_rready => s00_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_us_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1W60HW0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1W60HW0;
architecture STRUCTURE of s01_couplers_imp_1W60HW0 is
component design_1_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC
);
end component design_1_auto_us_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s01_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s01_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_WVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s01_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_awaddr(31 downto 0) <= auto_us_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s01_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s01_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s01_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s01_couplers_BREADY;
M_AXI_wdata(63 downto 0) <= auto_us_to_s01_couplers_WDATA(63 downto 0);
M_AXI_wlast <= auto_us_to_s01_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_us_to_s01_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_us_to_s01_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_awready <= s01_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_auto_us_BVALID;
S_AXI_wready <= s01_couplers_to_auto_us_WREADY;
auto_us_to_s01_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s01_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s01_couplers_to_auto_us_BREADY <= S_AXI_bready;
s01_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s01_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
auto_us: component design_1_auto_us_1
port map (
m_axi_awaddr(31 downto 0) => auto_us_to_s01_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s01_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s01_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s01_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s01_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s01_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s01_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s01_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s01_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s01_couplers_AWVALID,
m_axi_bready => auto_us_to_s01_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s01_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s01_couplers_BVALID,
m_axi_wdata(63 downto 0) => auto_us_to_s01_couplers_WDATA(63 downto 0),
m_axi_wlast => auto_us_to_s01_couplers_WLAST,
m_axi_wready => auto_us_to_s01_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_us_to_s01_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_us_to_s01_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_aresetn => S_ARESETN_1(0),
s_axi_awaddr(31 downto 0) => s01_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s01_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s01_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s01_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s01_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => s01_couplers_to_auto_us_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s01_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s01_couplers_to_auto_us_AWVALID,
s_axi_bready => s01_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s01_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s01_couplers_to_auto_us_BVALID,
s_axi_wdata(31 downto 0) => s01_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s01_couplers_to_auto_us_WLAST,
s_axi_wready => s01_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s01_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s01_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC
);
end design_1_axi_mem_intercon_0;
architecture STRUCTURE of design_1_axi_mem_intercon_0 is
component design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC;
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 64 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(63 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0);
M00_AXI_wid(0) <= m00_couplers_to_axi_mem_intercon_WID(0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(7 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_awready <= axi_mem_intercon_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= axi_mem_intercon_to_s01_couplers_BVALID;
S01_AXI_wready <= axi_mem_intercon_to_s01_couplers_WREADY;
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
axi_mem_intercon_to_s01_couplers_BREADY <= S01_AXI_bready;
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST <= S01_AXI_wlast;
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID <= S01_AXI_wvalid;
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0);
m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1R706YB
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0),
M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0),
M_AXI_wid(0) => m00_couplers_to_axi_mem_intercon_WID(0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(7 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(0) => xbar_to_m00_couplers_BID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
S_AXI_rid(0) => xbar_to_m00_couplers_RID(0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_7HNO1D
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID
);
s01_couplers: entity work.s01_couplers_imp_1W60HW0
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s01_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s01_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_wdata(63 downto 0) => s01_couplers_to_xbar_WDATA(63 downto 0),
M_AXI_wlast => s01_couplers_to_xbar_WLAST,
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(7 downto 0) => s01_couplers_to_xbar_WSTRB(7 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s01_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s01_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s01_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s01_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s01_couplers_WVALID
);
xbar: component design_1_xbar_0
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => xbar_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => xbar_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(0) => xbar_to_m00_couplers_BID(0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(0) => xbar_to_m00_couplers_RID(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(3 downto 2) => B"00",
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(7 downto 4) => B"0000",
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(1 downto 0) => B"00",
s_axi_arlen(15 downto 8) => B"00000000",
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(1) => '0',
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(5 downto 3) => B"000",
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(7 downto 4) => B"0000",
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(5 downto 3) => B"000",
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(1) => '0',
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(1 downto 0) => B"00",
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1) => s01_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(0) => '0',
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(7 downto 4) => s01_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0),
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => '0',
s_axi_bid(1 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(1 downto 0),
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => '0',
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0),
s_axi_rdata(127 downto 64) => NLW_xbar_s_axi_rdata_UNCONNECTED(127 downto 64),
s_axi_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
s_axi_rid(1 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(1 downto 0),
s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(1) => '0',
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(127 downto 64) => s01_couplers_to_xbar_WDATA(63 downto 0),
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST,
s_axi_wlast(0) => '1',
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0),
s_axi_wstrb(15 downto 8) => s01_couplers_to_xbar_WSTRB(7 downto 0),
s_axi_wstrb(7 downto 0) => B"11111111",
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_1_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_1_processing_system7_0_axi_periph_0 is
component design_1_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_1_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_xbar_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1(0) <= M03_ARESETN(0);
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_processing_system7_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_processing_system7_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready;
m03_couplers_to_processing_system7_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_processing_system7_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_processing_system7_0_axi_periph_WREADY <= M03_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_OBU1DD
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1FBREZ4
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_MVV5YQ
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1GHG26R
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN(0) => M03_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
s00_couplers: entity work.s00_couplers_imp_1CFO1MB
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component design_1_xbar_1
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(11 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(11 downto 0),
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(11 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(11 downto 0),
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => NLW_xbar_m_axi_wstrb_UNCONNECTED(3 downto 0),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1 is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=22,numReposBlks=12,numNonXlnxBlks=1,numHierBlks=10,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=1,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=3,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
end design_1;
architecture STRUCTURE of design_1 is
component design_1_axi_dma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
mm2s_introut : out STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component design_1_axi_dma_0_0;
component design_1_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end component design_1_axi_timer_0_0;
component design_1_ila_0_0 is
port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 5 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component design_1_ila_0_0;
component design_1_processing_system7_0_0 is
port (
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_1_processing_system7_0_0;
component design_1_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_rst_processing_system7_0_100M_0;
component design_1_doImgProc_0_2 is
port (
s_axi_CRTL_BUS_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_CRTL_BUS_AWVALID : in STD_LOGIC;
s_axi_CRTL_BUS_AWREADY : out STD_LOGIC;
s_axi_CRTL_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_CRTL_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_CRTL_BUS_WVALID : in STD_LOGIC;
s_axi_CRTL_BUS_WREADY : out STD_LOGIC;
s_axi_CRTL_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_CRTL_BUS_BVALID : out STD_LOGIC;
s_axi_CRTL_BUS_BREADY : in STD_LOGIC;
s_axi_CRTL_BUS_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_CRTL_BUS_ARVALID : in STD_LOGIC;
s_axi_CRTL_BUS_ARREADY : out STD_LOGIC;
s_axi_CRTL_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_CRTL_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_CRTL_BUS_RVALID : out STD_LOGIC;
s_axi_CRTL_BUS_RREADY : in STD_LOGIC;
s_axi_KERNEL_BUS_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_KERNEL_BUS_AWVALID : in STD_LOGIC;
s_axi_KERNEL_BUS_AWREADY : out STD_LOGIC;
s_axi_KERNEL_BUS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_KERNEL_BUS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_KERNEL_BUS_WVALID : in STD_LOGIC;
s_axi_KERNEL_BUS_WREADY : out STD_LOGIC;
s_axi_KERNEL_BUS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_KERNEL_BUS_BVALID : out STD_LOGIC;
s_axi_KERNEL_BUS_BREADY : in STD_LOGIC;
s_axi_KERNEL_BUS_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_KERNEL_BUS_ARVALID : in STD_LOGIC;
s_axi_KERNEL_BUS_ARREADY : out STD_LOGIC;
s_axi_KERNEL_BUS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_KERNEL_BUS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_KERNEL_BUS_RVALID : out STD_LOGIC;
s_axi_KERNEL_BUS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC;
inStream_TVALID : in STD_LOGIC;
inStream_TREADY : out STD_LOGIC;
inStream_TDATA : in STD_LOGIC_VECTOR ( 7 downto 0 );
inStream_TDEST : in STD_LOGIC_VECTOR ( 5 downto 0 );
inStream_TKEEP : in STD_LOGIC_VECTOR ( 0 to 0 );
inStream_TSTRB : in STD_LOGIC_VECTOR ( 0 to 0 );
inStream_TUSER : in STD_LOGIC_VECTOR ( 1 downto 0 );
inStream_TLAST : in STD_LOGIC_VECTOR ( 0 to 0 );
inStream_TID : in STD_LOGIC_VECTOR ( 4 downto 0 );
outStream_TVALID : out STD_LOGIC;
outStream_TREADY : in STD_LOGIC;
outStream_TDATA : out STD_LOGIC_VECTOR ( 7 downto 0 );
outStream_TDEST : out STD_LOGIC_VECTOR ( 5 downto 0 );
outStream_TKEEP : out STD_LOGIC_VECTOR ( 0 to 0 );
outStream_TSTRB : out STD_LOGIC_VECTOR ( 0 to 0 );
outStream_TUSER : out STD_LOGIC_VECTOR ( 1 downto 0 );
outStream_TLAST : out STD_LOGIC_VECTOR ( 0 to 0 );
outStream_TID : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component design_1_doImgProc_0_2;
signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal doImgProc_0_outStream_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
signal doImgProc_0_outStream_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 );
signal doImgProc_0_outStream_TLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal doImgProc_0_outStream_TREADY : STD_LOGIC;
signal doImgProc_0_outStream_TVALID : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_dma_0_mm2s_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_s2mm_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
signal NLW_doImgProc_0_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_doImgProc_0_outStream_TDEST_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_doImgProc_0_outStream_TID_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_doImgProc_0_outStream_TSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_doImgProc_0_outStream_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_dma_0: component design_1_axi_dma_0_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_0_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_0_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_0_M_AXI_S2MM_WVALID,
m_axis_mm2s_tdata(7 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(7 downto 0),
m_axis_mm2s_tkeep(0) => axi_dma_0_M_AXIS_MM2S_TKEEP(0),
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
mm2s_introut => NLW_axi_dma_0_mm2s_introut_UNCONNECTED,
mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED,
s2mm_introut => NLW_axi_dma_0_s2mm_introut_UNCONNECTED,
s2mm_prmry_reset_out_n => NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_lite_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
s_axis_s2mm_tdata(7 downto 0) => doImgProc_0_outStream_TDATA(7 downto 0),
s_axis_s2mm_tkeep(0) => doImgProc_0_outStream_TKEEP(0),
s_axis_s2mm_tlast => doImgProc_0_outStream_TLAST(0),
s_axis_s2mm_tready => doImgProc_0_outStream_TREADY,
s_axis_s2mm_tvalid => doImgProc_0_outStream_TVALID
);
axi_mem_intercon: entity work.design_1_axi_mem_intercon_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
M00_AXI_wid(0) => axi_mem_intercon_M00_AXI_WID(0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
S00_AXI_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
S00_AXI_rready => axi_dma_0_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S01_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
S01_AXI_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
S01_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
S01_AXI_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
S01_AXI_bready => axi_dma_0_M_AXI_S2MM_BREADY,
S01_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
S01_AXI_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
S01_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
S01_AXI_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
S01_AXI_wready => axi_dma_0_M_AXI_S2MM_WREADY,
S01_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
S01_AXI_wvalid => axi_dma_0_M_AXI_S2MM_WVALID
);
axi_timer_0: component design_1_axi_timer_0_0
port map (
capturetrig0 => '0',
capturetrig1 => '0',
freeze => '0',
generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
interrupt => NLW_axi_timer_0_interrupt_UNCONNECTED,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(4 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(4 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_bready => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID(0)
);
doImgProc_0: component design_1_doImgProc_0_2
port map (
ap_clk => processing_system7_0_FCLK_CLK0,
ap_rst_n => rst_processing_system7_0_100M_peripheral_aresetn(0),
inStream_TDATA(7 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(7 downto 0),
inStream_TDEST(5 downto 0) => B"000000",
inStream_TID(4 downto 0) => B"00000",
inStream_TKEEP(0) => axi_dma_0_M_AXIS_MM2S_TKEEP(0),
inStream_TLAST(0) => axi_dma_0_M_AXIS_MM2S_TLAST,
inStream_TREADY => axi_dma_0_M_AXIS_MM2S_TREADY,
inStream_TSTRB(0) => '1',
inStream_TUSER(1 downto 0) => B"00",
inStream_TVALID => axi_dma_0_M_AXIS_MM2S_TVALID,
interrupt => NLW_doImgProc_0_interrupt_UNCONNECTED,
outStream_TDATA(7 downto 0) => doImgProc_0_outStream_TDATA(7 downto 0),
outStream_TDEST(5 downto 0) => NLW_doImgProc_0_outStream_TDEST_UNCONNECTED(5 downto 0),
outStream_TID(4 downto 0) => NLW_doImgProc_0_outStream_TID_UNCONNECTED(4 downto 0),
outStream_TKEEP(0) => doImgProc_0_outStream_TKEEP(0),
outStream_TLAST(0) => doImgProc_0_outStream_TLAST(0),
outStream_TREADY => doImgProc_0_outStream_TREADY,
outStream_TSTRB(0) => NLW_doImgProc_0_outStream_TSTRB_UNCONNECTED(0),
outStream_TUSER(1 downto 0) => NLW_doImgProc_0_outStream_TUSER_UNCONNECTED(1 downto 0),
outStream_TVALID => doImgProc_0_outStream_TVALID,
s_axi_CRTL_BUS_ARADDR(4 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(4 downto 0),
s_axi_CRTL_BUS_ARREADY => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s_axi_CRTL_BUS_ARVALID => processing_system7_0_axi_periph_M02_AXI_ARVALID,
s_axi_CRTL_BUS_AWADDR(4 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(4 downto 0),
s_axi_CRTL_BUS_AWREADY => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s_axi_CRTL_BUS_AWVALID => processing_system7_0_axi_periph_M02_AXI_AWVALID,
s_axi_CRTL_BUS_BREADY => processing_system7_0_axi_periph_M02_AXI_BREADY,
s_axi_CRTL_BUS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_CRTL_BUS_BVALID => processing_system7_0_axi_periph_M02_AXI_BVALID,
s_axi_CRTL_BUS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_CRTL_BUS_RREADY => processing_system7_0_axi_periph_M02_AXI_RREADY,
s_axi_CRTL_BUS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_CRTL_BUS_RVALID => processing_system7_0_axi_periph_M02_AXI_RVALID,
s_axi_CRTL_BUS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_CRTL_BUS_WREADY => processing_system7_0_axi_periph_M02_AXI_WREADY,
s_axi_CRTL_BUS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_CRTL_BUS_WVALID => processing_system7_0_axi_periph_M02_AXI_WVALID,
s_axi_KERNEL_BUS_ARADDR(4 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(4 downto 0),
s_axi_KERNEL_BUS_ARREADY => processing_system7_0_axi_periph_M03_AXI_ARREADY,
s_axi_KERNEL_BUS_ARVALID => processing_system7_0_axi_periph_M03_AXI_ARVALID,
s_axi_KERNEL_BUS_AWADDR(4 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(4 downto 0),
s_axi_KERNEL_BUS_AWREADY => processing_system7_0_axi_periph_M03_AXI_AWREADY,
s_axi_KERNEL_BUS_AWVALID => processing_system7_0_axi_periph_M03_AXI_AWVALID,
s_axi_KERNEL_BUS_BREADY => processing_system7_0_axi_periph_M03_AXI_BREADY,
s_axi_KERNEL_BUS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s_axi_KERNEL_BUS_BVALID => processing_system7_0_axi_periph_M03_AXI_BVALID,
s_axi_KERNEL_BUS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s_axi_KERNEL_BUS_RREADY => processing_system7_0_axi_periph_M03_AXI_RREADY,
s_axi_KERNEL_BUS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s_axi_KERNEL_BUS_RVALID => processing_system7_0_axi_periph_M03_AXI_RVALID,
s_axi_KERNEL_BUS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s_axi_KERNEL_BUS_WREADY => processing_system7_0_axi_periph_M03_AXI_WREADY,
s_axi_KERNEL_BUS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s_axi_KERNEL_BUS_WVALID => processing_system7_0_axi_periph_M03_AXI_WVALID
);
ila_0: component design_1_ila_0_0
port map (
clk => processing_system7_0_FCLK_CLK0,
probe0(0) => doImgProc_0_outStream_TREADY,
probe1(7 downto 0) => doImgProc_0_outStream_TDATA(7 downto 0),
probe2(0) => '0',
probe3(0) => doImgProc_0_outStream_TVALID,
probe4(0) => doImgProc_0_outStream_TLAST(0),
probe5(1 downto 0) => B"00",
probe6(0) => doImgProc_0_outStream_TKEEP(0),
probe7(5 downto 0) => B"000000",
probe8(4 downto 0) => B"00000"
);
processing_system7_0: component design_1_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
ENET0_PTP_DELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 1) => B"00000",
S_AXI_HP0_ARID(0) => axi_mem_intercon_M00_AXI_ARID(0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 1) => B"00000",
S_AXI_HP0_AWID(0) => axi_mem_intercon_M00_AXI_AWID(0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
S_AXI_HP0_WID(5 downto 1) => B"00000",
S_AXI_HP0_WID(0) => axi_mem_intercon_M00_AXI_WID(0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_1_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
M03_ACLK => processing_system7_0_FCLK_CLK0,
M03_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component design_1_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
| gpl-3.0 | 6f3601e09d40a83865e25458fe516547 | 0.677077 | 2.799018 | false | false | false | false |
tgingold/ghdl | testsuite/synth/arr01/tb_arr05.vhdl | 1 | 1,000 | entity tb_arr05 is
end tb_arr05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr05 is
signal clk : std_logic;
signal val : std_logic_vector(7 downto 0);
signal res : std_logic_vector(7 downto 0);
signal par : std_logic;
begin
dut: entity work.arr05
port map (clk => clk, val => val, res => res, par => par);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
val <= x"a0";
pulse;
val <= x"71";
pulse;
val <= x"82";
pulse;
val <= x"23";
pulse;
val <= x"fe";
pulse;
assert res = x"a0" severity failure;
val <= x"e4";
pulse;
assert res = x"71" severity failure;
val <= x"c5";
pulse;
assert res = x"82" severity failure;
val <= x"f6";
pulse;
assert res = x"23" severity failure;
val <= x"57";
pulse;
assert res = x"fe" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 342995220ec53abe378c66f06a08c605 | 0.561 | 3.184713 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd | 4 | 1,743 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity freq_detect is
port ( terminal input : electrical;
terminal freq_out : electrical );
end entity freq_detect;
----------------------------------------------------------------
architecture threshold_crossing of freq_detect is
quantity v_in across input to electrical_ref;
quantity v_out across i_out through freq_out to electrical_ref;
signal freq : real := 0.0;
constant threshold : real := 0.0;
constant scale_factor : real := 1.0e-6;
begin
detect: process ( v_in'above(threshold) ) is
variable t_previous : real := real'low;
begin
if v_in > threshold then
freq <= scale_factor / ( now - t_previous );
t_previous := now;
end if;
end process detect;
v_out == freq'ramp(1.0e-9, 1.0e-9);
end threshold_crossing;
| gpl-2.0 | 12ae9ab974f5bc70cb6cca8e40890ab7 | 0.658635 | 4.081967 | false | false | false | false |
nickg/nvc | test/parse/based.vhd | 1 | 697 | PACKAGE pp IS
CONSTANT a : INTEGER := 2#1101#;
CONSTANT b : INTEGER := 3#20#;
CONSTANT c : INTEGER := 8#7#;
CONSTANT d : INTEGER := 10#1234#;
CONSTANT e : INTEGER := 16#beef01#;
CONSTANT f : INTEGER := 2#1_0#;
CONSTANT g : INTEGER := 2:1_0:;
CONSTANT h : INTEGER := 16#abababab#;
CONSTANT i : INTEGER := 16#1A#;
CONSTANT j : INTEGER := 2#1111_1111#;
CONSTANT k : INTEGER := 16#FF#;
CONSTANT l : INTEGER := 016#0FF#;
CONSTANT m : INTEGER := 16#E#E1;
CONSTANT n : INTEGER := 2#1110_0000#;
CONSTANT o : REAL := 16#F.FF#E+2;
CONSTANT p : REAL := 2#1.1111_1111_111#E11;
CONSTANT x : INTEGER := 2:1110_0000:;
CONSTANT y : REAL := 16:F.FF:E+2;
END PACKAGE;
| gpl-3.0 | d2cae528d26c69ba26439fc45c8970ec | 0.596844 | 3.017316 | false | false | false | false |
mistryalok/FPGA | Xilinx/ISE/Basics/SR_flipflop/SR_flipflop.vhd | 1 | 1,148 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:31:19 05/02/2013
-- Design Name:
-- Module Name: SR_flipflop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SR_flipflop is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : out std_logic;
Qn : out std_logic);
end SR_flipflop;
architecture Behavioral of SR_flipflop is
begin
process(S,R)
begin
Q <= '0';
Qn <= '0';
if(s= '1')then
Q<= '1';
Qn <='0';
elsif (R= '1') then
Q<= '0';
Qn <= '1';
end if;
end process;
end Behavioral;
| gpl-3.0 | 8cdde45b669cf618af17742f67c0d439 | 0.510453 | 3.5 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1211/tb_delay_ul.vhdl | 1 | 1,341 | entity tb_delay_ul is
end tb_delay_ul;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_delay_ul is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal dout : std_logic;
signal en : std_logic;
begin
dut: entity work.delay_ul
port map (
sig_out => dout,
sig_in => din,
clock => clk,
reset => rst,
Enable => En);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
en <= '1';
wait for 1 ns;
assert dout = '0' severity failure;
rst <= '0';
din <= '1';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '0' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
din <= '1';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
din <= '1';
rst <= '1';
pulse;
assert dout = '0' severity failure;
rst <= '0';
din <= '1';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 91175f99ed97c9e71663893dc4df88bc | 0.530947 | 3.403553 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket32/arith_prefix_and.vhdl | 3 | 2,968 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix AND computation: y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0'
-- This implementation uses carry chains for wider implementations.
--
-- Authors: Thomas B. Preusser
-- =============================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
entity arith_prefix_and is
generic (
N : positive
);
port (
x : in std_logic_vector(N-1 downto 0);
y : out std_logic_vector(N-1 downto 0)
);
end arith_prefix_and;
architecture rtl of arith_prefix_and is
type T_VENDOR is (VENDOR_XILINX, VENDOR_ALTERA);
constant VENDOR : T_VENDOR := VENDOR_XILINX;
begin
y(0) <= x(0);
gen1: if N > 1 generate
signal p : unsigned(N-1 downto 1);
begin
p(1) <= x(0) and x(1);
gen2: if N > 2 generate
p(N-1 downto 2) <= unsigned(x(N-1 downto 2));
-- Generic Carry Chain through Addition
genGeneric: if VENDOR /= VENDOR_XILINX generate
signal s : std_logic_vector(N downto 1);
begin
s <= std_logic_vector(('0' & p) + 1);
y(N-1 downto 2) <= s(N downto 3) xor ('0' & x(N-1 downto 3));
end generate genGeneric;
-- Direct Carry Chain by MUXCY Instantiation
genXilinx: if VENDOR = VENDOR_XILINX generate
-- component MUXCY
-- port (
-- S : in std_logic;
-- DI : in std_logic;
-- CI : in std_logic;
-- O : out std_logic
-- );
-- end component;
signal c : std_logic_vector(N-1 downto 0);
begin
c(0) <= '1';
genChain: for i in 1 to N-1 generate
mux : entity unisim.MUXCY
port map (
S => p(i),
DI => '0',
CI => c(i-1),
O => c(i)
);
end generate genChain;
y(N-1 downto 2) <= c(N-1 downto 2);
end generate genXilinx;
end generate gen2;
y(1) <= p(1);
end generate gen1;
end rtl;
| gpl-2.0 | 3e070210f75612414771735c5533dc06 | 0.565891 | 3.307692 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1362.vhd | 4 | 6,566 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1362.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01362ent IS
END c08s05b00x00p03n01i01362ent;
ARCHITECTURE c08s05b00x00p03n01i01362arch OF c08s05b00x00p03n01i01362ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
--
BEGIN
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***PASSED TEST: c08s05b00x00p03n01i01362"
severity NOTE;
assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***FAILED TEST: c08s05b00x00p03n01i01362 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01362arch;
| gpl-2.0 | 46410877fa994d7e6dc4ba756d58fa76 | 0.58346 | 2.93387 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket29/iomapper.vhdl | 3 | 24,390 | use WORK.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.debugtools.all;
entity iomapper is
port (Clk : in std_logic;
cpuclock : in std_logic;
pixelclk : in std_logic;
uartclock : in std_logic;
clock50mhz : in std_logic;
phi0 : in std_logic;
reset : in std_logic;
reset_out : out std_logic;
irq : out std_logic;
nmi : out std_logic;
restore_nmi : out std_logic;
cpu_hypervisor_mode : in std_logic;
address : in std_logic_vector(19 downto 0);
r : in std_logic;
w : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
sd_data_o : out std_logic_vector(7 downto 0);
sector_buffer_mapped : out std_logic;
key_scancode : in unsigned(15 downto 0);
key_scancode_toggle : in std_logic;
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
ps2data : in std_logic;
ps2clock : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
ampPWM : out std_logic;
ampSD : out std_logic;
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0);
seg_led : out unsigned(31 downto 0);
viciii_iomode : in std_logic_vector(1 downto 0);
colourram_at_dc00 : in std_logic;
---------------------------------------------------------------------------
-- IO port to far call stack
---------------------------------------------------------------------------
farcallstack_we : in std_logic;
farcallstack_addr : in std_logic_vector(8 downto 0);
farcallstack_din : in std_logic_vector(63 downto 0);
farcallstack_dout : out std_logic_vector(63 downto 0)
);
end iomapper;
architecture behavioral of iomapper is
component kickstart is
port (
Clk : in std_logic;
address : in std_logic_vector(13 downto 0);
we : in std_logic;
cs : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0));
end component;
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in unsigned(4 downto 0); -- address lines
di : in unsigned(7 downto 0); -- data in (to chip)
do : out unsigned(7 downto 0); -- data out (from chip)
pot_x : in unsigned(7 downto 0); -- paddle input-X
pot_y : in unsigned(7 downto 0); -- paddle input-Y
audio_data : out unsigned(17 downto 0)
);
end component;
component ethernet is
port (
clock : in std_logic;
clock50mhz : in std_logic;
reset : in std_logic;
irq : out std_logic := 'Z';
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
-- Signals from the VIC-IV frame packer to supply the compressed video feed
buffer_moby_toggle : in std_logic := '0';
buffer_address : out unsigned(11 downto 0);
buffer_rdata : in unsigned(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : out std_logic;
eth_keycode : out unsigned(15 downto 0);
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component sdcardio is
port (
clock : in std_logic;
pixelclk : in std_logic;
reset : in std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_read : in std_logic;
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
-- If colour RAM is mapped at $DC00-$DFFF, then don't map sector buffer
colourram_at_dc00 : in std_logic;
viciii_iomode : in std_logic_vector(1 downto 0);
sectorbuffermapped : out std_logic;
sectorbuffermapped2 : out std_logic;
sectorbuffercs : in std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
-- Accelerometer
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
-- Microphone
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
-- Audio in from digital SIDs
leftsid_audio : in unsigned(17 downto 0);
rightsid_audio : in unsigned(17 downto 0);
-- Audio output
ampPWM : out std_logic;
ampSD : out std_logic;
-- Temperature sensor
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
last_scan_code : in std_logic_vector(12 downto 0);
-------------------------------------------------------------------------
-- And general switch inputs on the FPGA board (good as place as any here)
-------------------------------------------------------------------------
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0)
);
end component;
component cia6526 is
port (
cpuclock : in std_logic;
phi0 : in std_logic;
todclock : in std_logic;
reset : in std_logic;
irq : out std_logic := '1';
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
cs : in std_logic;
fastio_address : in unsigned(7 downto 0);
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
portaout : out std_logic_vector(7 downto 0);
portain : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
flagin : in std_logic;
pcout : out std_logic;
spout : out std_logic;
spin : in std_logic;
countout : out std_logic;
countin : in std_logic);
end component;
component keymapper is
port (
pixelclk : in std_logic;
last_scan_code : out std_logic_vector(12 downto 0);
nmi : out std_logic := 'Z';
reset : out std_logic := 'Z';
-- PS2 keyboard interface
ps2clock : in std_logic;
ps2data : in std_logic;
-- CIA ports
porta_in : in std_logic_vector(7 downto 0);
portb_in : in std_logic_vector(7 downto 0);
porta_out : out std_logic_vector(7 downto 0);
portb_out : out std_logic_vector(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : in std_logic;
eth_keycode : in unsigned(15 downto 0)
);
end component;
component framepacker is
port (
pixelclock : in std_logic;
ioclock : in std_logic;
hypervisor_mode : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
-- Signals for ethernet controller
buffer_moby_toggle : out std_logic := '0';
buffer_address : in unsigned(11 downto 0);
buffer_rdata : out unsigned(7 downto 0);
---------------------------------------------------------------------------
-- fast IO port (clocked at CPU clock).
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component farcallstack IS
PORT (
-- CPU fastio port
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- CPU parallel push/pop port
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
end component;
signal kickstartcs : std_logic;
signal reset_high : std_logic;
signal clock50hz : std_logic := '1';
constant divisor50hz : integer := 640000; -- 64MHz/50Hz/2;
signal counter50hz : integer := 0;
signal cia1cs : std_logic;
signal cia2cs : std_logic;
signal sectorbuffercs : std_logic;
signal sector_buffer_mapped_read : std_logic;
signal farcallstackcs : std_logic;
signal farcallstack_w : std_logic;
signal farcallstack_wdata : std_logic_vector(63 downto 0);
signal farcallstack_rdata : std_logic_vector(63 downto 0);
signal last_scan_code : std_logic_vector(12 downto 0);
signal cia1porta_out : std_logic_vector(7 downto 0);
signal cia1porta_in : std_logic_vector(7 downto 0);
signal cia1portb_out : std_logic_vector(7 downto 0);
signal cia1portb_in : std_logic_vector(7 downto 0);
signal leftsid_cs : std_logic;
signal leftsid_audio : unsigned(17 downto 0);
signal rightsid_cs : std_logic;
signal rightsid_audio : unsigned(17 downto 0);
signal spare_bits : unsigned(4 downto 0);
signal buffer_moby_toggle : std_logic;
signal buffer_address : unsigned(11 downto 0);
signal buffer_rdata : unsigned(7 downto 0);
signal eth_keycode_toggle : std_logic;
signal eth_keycode : unsigned(15 downto 0);
begin
kickstartrom : kickstart port map (
clk => clk,
address => address(13 downto 0),
we => w,
cs => kickstartcs,
data_i => data_i,
data_o => data_o);
framepacker0: framepacker port map (
ioclock => clk,
pixelclock => pixelclk,
hypervisor_mode => cpu_hypervisor_mode,
pixel_stream_in => pixel_stream_in,
pixel_y => pixel_y,
pixel_valid => pixel_valid,
pixel_newframe => pixel_newframe,
pixel_newraster => pixel_newraster,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
fastio_addr => unsigned(address(19 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_read => r,
fastio_wdata => unsigned(data_i)
);
cia1: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => irq,
reg_isr_out => reg_isr_out,
imask_ta_out => imask_ta_out,
cs => cia1cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
portaout => cia1porta_out,
portbout => cia1portb_out,
portain => cia1porta_in,
portbin => cia1portb_in,
flagin => '1',
spin => '1',
countin => '1'
);
cia2two: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => nmi,
cs => cia2cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
-- CIA ports not connected by default
portbin => x"ff",
portain => x"ff",
flagin => '1',
spin => '1',
countin => '1'
);
keymapper0 : keymapper port map (
pixelclk => clk,
nmi => restore_nmi,
reset => reset_out,
ps2clock => ps2clock,
ps2data => ps2data,
last_scan_code => last_scan_code,
-- key_status => seg_led(1 downto 0),
porta_in => cia1porta_out,
portb_in => cia1portb_out,
porta_out => cia1porta_in,
portb_out => cia1portb_in,
-- remote keyboard input via ethernet
-- eth_keycode_toggle => eth_keycode_toggle,
-- eth_keycode => eth_keycode
-- remote
eth_keycode_toggle => key_scancode_toggle,
eth_keycode => key_scancode
);
leftsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => leftsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"01",
pot_y => x"02",
audio_data => leftsid_audio);
rightsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => rightsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"03",
pot_y => x"04",
audio_data => rightsid_audio);
ethernet0 : ethernet port map (
clock50mhz => clock50mhz,
clock => clk,
reset => reset,
irq => irq,
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio => eth_mdio,
eth_mdc => eth_mdc,
eth_reset => eth_reset,
eth_rxd => eth_rxd,
eth_txd => eth_txd,
eth_txen => eth_txen,
eth_rxdv => eth_rxdv,
eth_rxer => eth_rxer,
eth_interrupt => eth_interrupt,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
eth_keycode_toggle => eth_keycode_toggle,
eth_keycode => eth_keycode,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o
);
sdcard0 : sdcardio port map (
pixelclk => pixelclk,
clock => clk,
reset => reset,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o,
colourram_at_dc00 => colourram_at_dc00,
viciii_iomode => viciii_iomode,
sectorbuffermapped => sector_buffer_mapped,
sectorbuffermapped2 => sector_buffer_mapped_read,
sectorbuffercs => sectorbuffercs,
led => led,
motor => motor,
sw => sw,
btn => btn,
cs_bo => cs_bo,
sclk_o => sclk_o,
mosi_o => mosi_o,
miso_i => miso_i,
aclMISO => aclMISO,
aclMOSI => aclMOSI,
aclSS => aclSS,
aclSCK => aclSCK,
aclInt1 => aclInt1,
aclInt2 => aclInt2,
micData => micData,
micClk => micClk,
micLRSel => micLRSel,
leftsid_audio => leftsid_audio,
rightsid_audio => rightsid_audio,
ampSD => ampSD,
ampPWM => ampPWM,
tmpSDA => tmpSDA,
tmpSCL => tmpSCL,
tmpInt => tmpInt,
tmpCT => tmpCT,
QspiSCK => QspiSCK,
QspiDB => QspiDB,
QspiCSn => QspiCSn,
last_scan_code => last_scan_code
);
farcallstack0: farcallstack port map (
clka => clk,
ena => farcallstackcs,
wea(0) => w,
addra => address(11 downto 0),
dina => data_i,
douta => data_o,
clkb => cpuclock,
web(0) => farcallstack_w,
addrb => farcallstack_addr,
dinb => farcallstack_wdata,
doutb => farcallstack_rdata
);
process(reset)
begin
reset_high <= not reset;
end process;
process(clk)
begin
if rising_edge(clk) then
-- Generate 50Hz signal for TOD clock
-- (Note that we are a bit conflicted here, as our video mode is PALx4,
-- but at 60Hz. We will make our CIAs take 50Hz like in most PAL countries
-- so that we don't confuse things too much. We will probably add a 50Hz
-- raster interrupt filter to help music and games play at the right rate.)
if counter50hz<divisor50hz then
counter50hz <= counter50hz + 1;
else
clock50hz <= not clock50hz;
counter50hz <= 0;
end if;
seg_led(12) <= eth_keycode_toggle;
seg_led(11) <= last_scan_code(12);
seg_led(10 downto 0) <= unsigned(last_scan_code(10 downto 0));
end if;
end process;
process (r,w,address,cia1portb_in,cia1porta_out,colourram_at_dc00,
sector_buffer_mapped_read)
begin -- process
if (r or w) = '1' then
-- @IO:GS $FFF8000-$FFFBFFF 16KB Kickstart/hypervisor ROM
-- @IO:GS $FFF8000 Hypervisor entry point when $D67F is written
if address(19 downto 14)&"00" = x"F8" then
kickstartcs <= cpu_hypervisor_mode;
else
kickstartcs <='0';
end if;
-- @IO:GS $FFF0000-$FFF0FFF - CPU far call stack (512x8 byte entries)
if address(19 downto 12) = x"F0" then
farcallstackcs <= '1';
else
farcallstackcs <= '0';
end if;
-- sdcard sector buffer: only mapped if no colour ram @ $DC00, and if
-- the sectorbuffer mapping flag is set
sectorbuffercs <= '0';
report "fastio address = $" & to_hstring(address) severity note;
if address(19 downto 16) = x"D"
and address(15 downto 14) = "00"
and address(11 downto 9)&'0' = x"E"
and sector_buffer_mapped_read = '1' and colourram_at_dc00 = '0' then
sectorbuffercs <= '1';
report "selecting SD card sector buffer" severity note;
end if;
-- Also map SD card sector buffer at $FFD6000 - $FFD61FF regardless of
-- VIC-IV IO mode and mapping of colour RAM
if address(19 downto 8) = x"D60" or address(19 downto 8) = x"D61" then
sectorbuffercs <= '1';
end if;
-- Now map the SIDs
-- @IO:C64 $D440-$D47F = left SID
-- @IO:C64 $D400-$D43F = right SID
-- @IO:C64 $D480-$D4FF = repeated images of SIDs
-- Presumably repeated through to $D5FF. But we will repeat to $D4FF only
-- so that we can use $D500-$D5FF for other stuff.
case address(19 downto 8) is
when x"D04" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D14" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D24" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D34" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when others => leftsid_cs <= '0'; rightsid_cs <= '0';
end case;
-- $D500 - $D5FF is not currently used. Probably use some for FPU.
-- $D600 - $D60F is reserved for 6551 serial UART emulation for C65
-- compatibility (6551 actually only has 4 registers).
-- 6551 is not currently implemented, so this is just unmapped for now,
-- except for any read values required to allow the C65 ROM to function.
-- Hypervisor control (only visible from hypervisor mode) $D640 - $D67F
-- The hypervisor is a CPU provided function.
-- SD controller and miscellaneous hardware (microphone, accelerometer etc)
-- uses $D680 - $D6FF
-- CPU uses $FFD{0,1,2,3}700 for DMAgic and other CPU-hosted IO registers.
-- Now map the CIAs.
-- These are a bit fun, because they only get mapped if colour RAM isn't
-- being mapped in $DC00-$DFFF using the C65 2K colour ram register
cia1cs <='0';
cia2cs <='0';
if colourram_at_dc00='0' and sector_buffer_mapped_read='0' then
case address(19 downto 8) is
when x"D0C" => cia1cs <='1';
when x"D1C" => cia1cs <='1';
when x"D2C" => cia1cs <='1';
when x"D3C" => cia1cs <='1';
when x"D0D" => cia2cs <='1';
when x"D1D" => cia2cs <='1';
when x"D2D" => cia2cs <='1';
when x"D3D" => cia2cs <='1';
when others => null;
end case;
end if;
else
cia1cs <= '0';
cia2cs <= '0';
kickstartcs <= '0';
sectorbuffercs <= '0';
leftsid_cs <= '0';
rightsid_cs <= '0';
farcallstackcs <= '0';
end if;
end process;
end behavioral;
| gpl-2.0 | f1fe00d2c5021ccd7b827cdaabe6222d | 0.528782 | 3.872043 | false | false | false | false |
tgingold/ghdl | testsuite/synth/psl01/assert1.vhdl | 1 | 528 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity assert1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end assert1;
architecture behav of assert1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
--psl default clock is rising_edge(clk);
--psl assert always val /= 5 abort rst;
end behav;
| gpl-2.0 | c5df21ef0597cf4b0e09f19f6ba3e486 | 0.628788 | 3.219512 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_router_async_s1d2_x4_b/src/sip_router_async_s1d2_x4_b_stellar_cmd.vhd | 1 | 11,535 | --------------------------------------------------------------------------------
-- file name : sip_router_async_s1d2_x4_b_stellar_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity -sip_router_async_s1d2_x4_b_stellar_cmd
-- arch_itecture - arch_sip_router_async_s1d2_x4_b_stellar_cmd
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-01-2009 new version
-- 31-08-2009 added the mailbox input port
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- specify libraries.
--------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_1164.all ;
--------------------------------------------------------------------------------
-- entity declaration
--------------------------------------------------------------------------------
entity sip_router_async_s1d2_x4_b_stellar_cmd is
generic
(
start_addr :std_logic_vector(27 downto 0):=x"0000000";
stop_addr :std_logic_vector(27 downto 0):=x"0000010"
);
port
(
reset :in std_logic;
--command if
clk_cmd :in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd :out std_logic_vector(63 downto 0);
out_cmd_val :out std_logic;
in_cmd :in std_logic_vector(63 downto 0);
in_cmd_val :in std_logic;
--register interface
clk_reg :in std_logic; --register interface is synchronous to this clock
out_reg :out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val :out std_logic; --the out_reg has valid data (pulse)
out_reg_addr :out std_logic_vector(27 downto 0);--out register address
in_reg :in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val :in std_logic; --pulse to indicate requested register is valid
in_reg_req :out std_logic; --pulse to request data
in_reg_addr :out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_out_reg :out std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_out_val :out std_logic;
mbx_in_reg :in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val :in std_logic --pulse to indicate mailbox is valid
);
end entity sip_router_async_s1d2_x4_b_stellar_cmd ;
--------------------------------------------------------------------------------
-- arch_itecture declaration
--------------------------------------------------------------------------------
architecture arch_sip_router_async_s1d2_x4_b_stellar_cmd of sip_router_async_s1d2_x4_b_stellar_cmd is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
constant cmd_mbx :std_logic_vector(3 downto 0) :=x"0";
constant cmd_rd :std_logic_vector(3 downto 0) :=x"2";
constant cmd_wr :std_logic_vector(3 downto 0) :=x"1";
constant cmd_rd_ack :std_logic_vector(3 downto 0) :=x"4";
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
signal register_wr :std_logic;
signal register_rd :std_logic;
signal out_cmd_val_sig :std_logic;
signal in_reg_addr_sig :std_logic_vector(27 downto 0);
signal mbx_in_val_sig :std_logic;
signal mbx_received :std_logic;
signal mbx_out_val_sig :std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk :in std_logic;
out_clk :in std_logic;
rst :in std_logic;
pulsein :in std_logic;
inbusy :out std_logic;
pulseout :out std_logic
);
end component;
begin
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg,
rst =>reset,
pulsein =>register_wr,
inbusy =>open,
pulseout =>out_reg_val
);
p2p1: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg,
rst =>reset,
pulsein =>register_rd,
inbusy =>open,
pulseout =>in_reg_req
);
p2p2: pulse2pulse
port map
(
in_clk =>clk_reg,
out_clk =>clk_cmd ,
rst =>reset,
pulsein =>in_reg_val,
inbusy =>open,
pulseout =>out_cmd_val_sig
);
p2p3: pulse2pulse
port map
(
in_clk =>clk_reg,
out_clk =>clk_cmd ,
rst =>reset,
pulsein =>mbx_in_val,
inbusy =>open,
pulseout =>mbx_in_val_sig
);
p2p4: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg ,
rst =>reset,
pulsein =>mbx_out_val_sig,
inbusy =>open,
pulseout =>mbx_out_val
);
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process(clk_cmd )
begin
if(clk_cmd'event and clk_cmd='1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig='1' and mbx_in_val_sig='1') then
mbx_received <= '1';
elsif( mbx_received ='1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig='1') then
out_cmd(31 downto 0) <=in_reg;
out_cmd(59 downto 32)<=in_reg_addr_sig+start_addr;
out_cmd(63 downto 60)<=cmd_rd_ack;
elsif (mbx_in_val_sig='1' or mbx_received='1' ) then
out_cmd(31 downto 0) <=mbx_in_reg;
out_cmd(59 downto 32)<=start_addr;
out_cmd(63 downto 60)<=cmd_mbx;
else
out_cmd(63 downto 0)<=(others=>'0');
end if;
if (out_cmd_val_sig='1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig='1' or mbx_received='1' ) then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(clk_cmd )
begin
if(clk_cmd'event and clk_cmd='1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
out_reg_addr <= in_cmd(59 downto 32)-start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx) then
mbx_out_reg <= in_cmd(31 downto 0);
end if;
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx ) then
mbx_out_val_sig <= '1';
else
mbx_out_val_sig <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
end architecture arch_sip_router_async_s1d2_x4_b_stellar_cmd ; -- of sip_router_async_s1d2_x4_b_stellar_cmd
| mit | b6f52cbc9b48f36ea18d3d884fc1ed4f | 0.452362 | 4.115234 | false | false | false | false |
tgingold/ghdl | testsuite/synth/comp01/tb_and6.vhdl | 1 | 914 | library ieee;
use ieee.std_logic_1164.all;
entity tb_and6 is
end tb_and6;
architecture behav of tb_and6 is
signal i0, i1, i2, i3, i4, i5 : std_logic;
signal o : std_logic;
begin
dut : entity work.and6
port map (i0 => i0, i1 => i1, i2 => i2, i3 => i4, i4 => i4,
i5 => i5, o => o);
process
constant v0 : std_logic_vector := b"1011";
constant v1 : std_logic_vector := b"1111";
constant v2 : std_logic_vector := b"1111";
constant v3 : std_logic_vector := b"1111";
constant v4 : std_logic_vector := b"1111";
constant v5 : std_logic_vector := b"1101";
constant ov : std_logic_vector := b"1001";
begin
for i in ov'range loop
i0 <= v0 (i);
i1 <= v1 (i);
i2 <= v2 (i);
i3 <= v3 (i);
i4 <= v4 (i);
i5 <= v5 (i);
wait for 1 ns;
assert o = ov(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | 923fe13ae83baf01397a2326b876383a | 0.552516 | 2.761329 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_timer_v2_0/hdl/src/vhdl/tc_core.vhd | 3 | 18,217 | -------------------------------------------------------------------------------
-- TC_Core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_core.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Dual Timer/Counter for PLB bus
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_AWIDTH -- PLB address bus width
-- C_DWIDTH -- PLB data bus width
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- PLB Clock
-- Rst -- PLB Reset
-- Bus2ip_addr -- bus to ip address bus
-- Bus2ip_be -- byte enables
-- Bus2ip_data -- bus to ip data bus
--
-- TC_DBus -- ip to bus data bus
-- bus2ip_rdce -- read select
-- bus2ip_wrce -- write select
-- ip2bus_rdack -- read acknowledge
-- ip2bus_wrack -- write acknowledge
-- TC_errAck -- error acknowledge
-------------------------------------------------------------------------------
-- Timer/Counter signals
-------------------------------------------------------------------------------
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- PWM0 -- Pulse Width Modulation Ouput 0
-- Interrupt -- Interrupt
-- Freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0_10;
use axi_timer_v2_0_10.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0_10.TC_Types.PWMA0_POS;
use axi_timer_v2_0_10.TC_Types.PWMB0_POS;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
library unisim;
use unisim.vcomponents.FDRS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity tc_core is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 5;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Rst : in std_logic;
-- PLB signals
Bus2ip_addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2ip_be : in std_logic_vector(0 to 3);
Bus2ip_data : in std_logic_vector(0 to 31);
TC_DBus : out std_logic_vector(0 to 31);
bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
TC_errAck : out std_logic;
-- PTC signals
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic
);
end entity tc_core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of tc_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Attribute declaration
attribute syn_keep : boolean;
--Signal declaration
signal load_Counter_Reg : std_logic_vector(0 to 1);
signal load_Load_Reg : std_logic_vector(0 to 1);
signal write_Load_Reg : std_logic_vector(0 to 1);
signal captGen_Mux_Sel : std_logic_vector(0 to 1);
signal loadReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal counterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal tCSR0_Reg : QUADLET_TYPE;
signal tCSR1_Reg : QUADLET_TYPE;
signal counter_TC : std_logic_vector(0 to 1);
signal counter_En : std_logic_vector(0 to 1);
signal count_Down : std_logic_vector(0 to 1);
attribute syn_keep of count_Down : signal is true;
signal iPWM0 : std_logic;
signal iGenerateOut0 : std_logic;
signal iGenerateOut1 : std_logic;
signal pwm_Reset : std_logic;
signal Read_Reg_In : QUADLET_TYPE;
signal read_Mux_In : std_logic_vector(0 to 6*32-1);
signal read_Mux_S : std_logic_vector(0 to 5);
begin -- architecture imp
-----------------------------------------------------------------------------
-- Generating the acknowledgement/error signals
-----------------------------------------------------------------------------
ip2bus_rdack <= (Bus2ip_rdce(0) or Bus2ip_rdce(1) or Bus2ip_rdce(2) or
Bus2ip_rdce(4) or Bus2ip_rdce(5) or
Bus2ip_rdce(6) or Bus2ip_rdce(7));
ip2bus_wrack <= (Bus2ip_wrce(0) or Bus2ip_wrce(1) or Bus2ip_wrce(2) or
Bus2ip_wrce(4) or Bus2ip_wrce(5) or
Bus2ip_wrce(6) or Bus2ip_wrce(7));
--TCR0 AND TCR1 is read only register, hence writing to these register
--will not generate error ack.
--Modify TC_errAck <= (Bus2ip_wrce(2)or Bus2ip_wrce(6)) on 11/11/08 to;
TC_errAck <= '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--Process :READ_MUX_INPUT
-----------------------------------------------------------------------------
READ_MUX_INPUT: process (TCSR0_Reg,TCSR1_Reg,LoadReg_DBus,CounterReg_DBus) is
begin
read_Mux_In(0 to 19) <= (others => '0');
read_Mux_In(20 to 31) <= TCSR0_Reg(20 to 31);
read_Mux_In(32 to 52) <= (others => '0');
read_Mux_In(53 to 63) <= TCSR1_Reg(21 to 31);
if C_COUNT_WIDTH < C_DWIDTH then
for i in 1 to C_DWIDTH-C_COUNT_WIDTH loop
read_Mux_In(63 +i) <= '0';
read_Mux_In(95 +i) <= '0';
read_Mux_In(127+i) <= '0';
read_Mux_In(159+i) <= '0';
end loop;
end if;
read_Mux_In(64 +C_DWIDTH-C_COUNT_WIDTH to 95) <=
LoadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(96 +C_DWIDTH-C_COUNT_WIDTH to 127) <=
LoadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
read_Mux_In(128+C_DWIDTH-C_COUNT_WIDTH to 159) <=
CounterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(160+C_DWIDTH-C_COUNT_WIDTH to 191) <=
CounterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
end process READ_MUX_INPUT;
---------------------------------------------------------
-- Create read mux select input
-- Bus2ip_rdce(0) -->TCSR0 REG READ ENABLE
-- Bus2ip_rdce(4) -->TCSR1 REG READ ENABLE
-- Bus2ip_rdce(1) -->TLR0 REG READ ENABLE
-- Bus2ip_rdce(5) -->TLR1 REG READ ENABLE
-- Bus2ip_rdce(2) -->TCR0 REG READ ENABLE
-- Bus2ip_rdce(6) -->TCR1 REG READ ENABLE
---------------------------------------------------------
read_Mux_S <= Bus2ip_rdce(0) & Bus2ip_rdce(4)& Bus2ip_rdce(1)
& Bus2ip_rdce(5) & Bus2ip_rdce(2) & Bus2ip_rdce(6);
-- mux_onehot_f
READ_MUX_I: entity axi_timer_v2_0_10.mux_onehot_f
generic map(
C_DW => 32,
C_NB => 6,
C_FAMILY => C_FAMILY)
port map(
D => read_Mux_In, --[in]
S => read_Mux_S, --[in]
Y => Read_Reg_In --[out]
);
--slave to bus data bus assignment
TC_DBus <= Read_Reg_In ;
------------------------------------------------------------------
------------------------------------------------------------------
-- COUNTER MODULE
------------------------------------------------------------------
COUNTER_0_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(0), --[in]
Load_Load_Reg => load_Load_Reg(0), --[in]
Write_Load_Reg => write_Load_Reg(0), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(0), --[in]
Counter_En => counter_En(0), --[in]
Count_Down => count_Down(0), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
Counter_TC => counter_TC(0) --[out]
);
----------------------------------------------------------------------
--GEN_SECOND_TIMER:SECOND COUNTER MODULE IS ADDED TO DESIGN
--WHEN C_ONE_TIMER_ONLY /= 1
----------------------------------------------------------------------
GEN_SECOND_TIMER: if C_ONE_TIMER_ONLY /= 1 generate
COUNTER_1_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(1), --[in]
Load_Load_Reg => load_Load_Reg(1), --[in]
Write_Load_Reg => write_Load_Reg(1), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(1), --[in]
Counter_En => counter_En(1), --[in]
Count_Down => count_Down(1), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
Counter_TC => counter_TC(1) --[out]
);
end generate GEN_SECOND_TIMER;
----------------------------------------------------------------------
--GEN_NO_SECOND_TIMER: GENERATE WHEN C_ONE_TIMER_ONLY = 1
----------------------------------------------------------------------
GEN_NO_SECOND_TIMER: if C_ONE_TIMER_ONLY = 1 generate
loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counter_TC(1) <= '0';
end generate GEN_NO_SECOND_TIMER;
----------------------------------------------------------------------
--TIMER_CONTROL_I: TIMER_CONTROL MODULE
----------------------------------------------------------------------
TIMER_CONTROL_I: entity axi_timer_v2_0_10.timer_control
generic map (
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
Clk => Clk, -- [in]
Reset => Rst, -- [in]
CaptureTrig0 => CaptureTrig0, -- [in]
CaptureTrig1 => CaptureTrig1, -- [in]
GenerateOut0 => iGenerateOut0, -- [out]
GenerateOut1 => iGenerateOut1, -- [out]
Interrupt => Interrupt, -- [out]
Counter_TC => counter_TC, -- [in]
Bus2ip_data => Bus2ip_data, -- [in]
BE => Bus2ip_be, -- [in]
Load_Counter_Reg => load_Counter_Reg, -- [out]
Load_Load_Reg => load_Load_Reg, -- [out]
Write_Load_Reg => write_Load_Reg, -- [out]
CaptGen_Mux_Sel => captGen_Mux_Sel, -- [out]
Counter_En => counter_En, -- [out]
Count_Down => count_Down, -- [out]
Bus2ip_rdce => Bus2ip_rdce, -- [in]
Bus2ip_wrce => Bus2ip_wrce, -- [in]
Freeze => Freeze, -- [in]
TCSR0_Reg => tCSR0_Reg(20 to 31), -- [out]
TCSR1_Reg => tCSR1_Reg(21 to 31) -- [out]
);
tCSR0_Reg (0 to 19) <= (others => '0');
tCSR1_Reg (0 to 20) <= (others => '0');
pwm_Reset <= iGenerateOut1 or
(not tCSR0_Reg(PWMA0_POS) and not tCSR1_Reg(PWMB0_POS));
PWM_FF_I: component FDRS
port map (
Q => iPWM0, -- [out]
C => Clk, -- [in]
D => iPWM0, -- [in]
R => pwm_Reset, -- [in]
S => iGenerateOut0 -- [in]
);
PWM0 <= iPWM0;
GenerateOut0 <= iGenerateOut0;
GenerateOut1 <= iGenerateOut1;
end architecture IMP;
| gpl-3.0 | aba9fe71d3b3c59fbb434da1bfba4e07 | 0.465444 | 3.944781 | false | false | false | false |
tgingold/ghdl | testsuite/synth/var01/tb_var01.vhdl | 1 | 1,046 | entity tb_var01 is
end tb_var01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var01 is
signal clk : std_logic;
signal mask : std_logic_vector (3 downto 0);
signal val : std_logic_vector (31 downto 0);
signal res : std_logic_vector (31 downto 0);
begin
dut: entity work.var01
port map (
clk => clk,
mask => mask,
val => val,
res => res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
mask <= x"f";
val <= x"12_34_56_78";
pulse;
assert res = x"12_34_56_78" report "res=" & to_hstring (res) severity failure;
mask <= x"8";
val <= x"9a_00_00_00";
pulse;
assert res = x"9a_34_56_78" severity failure;
mask <= x"0";
val <= x"00_00_00_00";
pulse;
assert res = x"9a_34_56_78" severity failure;
mask <= x"5";
val <= x"00_bc_00_de";
pulse;
assert res = x"9a_bc_56_de" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 1eabf71556d79632b5423fc744baf3b8 | 0.56501 | 2.997135 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue467/axi_master.vhd | 1 | 4,180 | -------------------------------------------------------------------------------
-- Title : AXI-Lite Master BFM
-- Project : P500
-------------------------------------------------------------------------------
-- File : axi_master.vhd
-- Author : Rob Gaddi <[email protected]>
-- Company : Highland Technology, Inc.
-- Created : 21-Nov-2017
-- Last update: 21-Nov-2017
-- Platform : Simulation
-- Standard : VHDL-2008
-------------------------------------------------------------------------------
-- Description: Simulation model of an AXI4-Lite bus master.
-------------------------------------------------------------------------------
-- Revision History:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.TbUtilPkg.all;
use osvvm.AlertLogPkg.all;
use work.AbstractMmPkg.all;
entity axi_master is
generic (
LOG_NAME : string := "axi_master";
DATAWIDTH : positive := 32;
ADDRWIDTH : positive := 12
);
port (
-- AXI interface
AWADDR : out std_logic_vector(ADDRWIDTH-1 downto 0);
AWPROT : out std_logic_vector(2 downto 0);
AWVALID : out std_logic;
AWREADY : in std_logic;
WDATA : out std_logic_vector(DATAWIDTH-1 downto 0);
WSTRB : out std_logic_vector((DATAWIDTH/8)-1 downto 0);
WVALID : out std_logic;
WREADY : in std_logic;
BRESP : in std_logic_vector(1 downto 0);
BVALID : in std_logic;
BREADY : out std_logic;
ARADDR : out std_logic_vector(ADDRWIDTH-1 downto 0);
ARPROT : out std_logic_vector(2 downto 0);
ARVALID : out std_logic;
ARREADY : in std_logic;
RDATA : in std_logic_vector(DATAWIDTH-1 downto 0);
RRESP : in std_logic_vector(1 downto 0);
RVALID : in std_logic;
RREADY : out std_logic;
ACLK : in std_logic;
ARESETn : in std_logic;
-- AMR interface
amr : inout AbstractMmRecType
);
end entity axi_master;
architecture Behavioral of axi_master is
constant ALRT : AlertLogIDType := GetAlertLogID(LOG_NAME);
signal prot: std_logic_vector(2 downto 0);
constant BADREADDATA : std_logic_vector(RDATA'range) := (others => 'X');
begin
INITIALIZE: process
begin
prot <= (others => '0');
wait;
end process INITIALIZE;
AXI: process
procedure SingleRead is
variable request_ack : boolean := false;
begin
ARADDR <= STD_LOGIC_VECTOR(GetByteAddress(amr));
ARPROT <= prot;
ARVALID <= '1';
while not request_ack loop
wait until rising_edge(ACLK);
if RVALID = '1' then
RREADY <= '0';
request_ack := true;
end if;
end loop;
RREADY <= '1';
wait until rising_edge(ACLK) and RVALID='1';
if RRESP = "00" then
amr.readdata <= RDATA;
else
amr.readdata <= BADREADDATA;
end if;
RREADY <= '0';
end procedure SingleRead;
procedure SingleWrite is
variable addr_ack : boolean := false;
variable data_ack : boolean := false;
variable resp_ack : boolean := false;
begin
AWADDR <= STD_LOGIC_VECTOR(GetByteAddress(amr));
AWPROT <= prot;
AWVALID <= '1';
WDATA <= amr.writedata;
WSTRB <= amr.byteen;
WVALID <= '1';
while not (addr_ack and data_ack) loop
wait until rising_edge(ACLK);
if AWREADY = '1' then
AWVALID <= '0';
addr_ack := true;
end if;
if WREADY = '1' then
WVALID <= '0';
data_ack := true;
end if;
end loop;
BREADY <= '1';
wait until rising_edge(ACLK) and BVALID='1';
BREADY <= '0';
end procedure SingleWrite;
begin
InitializeAmr(amr);
amr.alert <= ALRT;
loop
AWVALID <= '0';
WVALID <= '0';
BREADY <= '0';
ARVALID <= '0';
RREADY <= '0';
WaitForTransaction(ACLK, amr.rdy, amr.ack);
if ARESETn = '0' then
wait until ARESETn = '1';
end if;
case amr.trans is
when SINGLE =>
if amr.write = AMR_READ then
SingleRead;
else
SingleWrite;
end if;
when others =>
Alert(ALRT, "Transaction type " & TransactionType'image(amr.trans) &
" not supported by model.", FAILURE);
end case;
end loop;
end process AXI;
end architecture Behavioral;
| gpl-2.0 | 27e4d4be9986dd4997302e3591a2db31 | 0.569139 | 3.420622 | false | false | false | false |
nickg/nvc | lib/std.08/textio.vhd | 1 | 6,827 | -------------------------------------------------------------------------------
-- Copyright (C) 2012-2021 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TEXTIO package as defined by IEEE 1076-2008
-------------------------------------------------------------------------------
package textio is
type line is access string;
type text is file of string;
type side is (RIGHT, LEFT);
subtype width is natural;
function justify (value : string;
justified : side := right;
field : width := 0) return string;
file input : text open READ_MODE is "STD_INPUT";
file output : text open WRITE_MODE is "STD_OUTPUT";
procedure readline (file f: text; l: inout line);
procedure read (l : inout line;
value : out bit;
good : out boolean );
procedure read (l : inout line;
value : out bit );
procedure read (l : inout line;
value : out bit_vector;
good : out boolean );
procedure read (l : inout line;
value : out bit_vector );
procedure read (l : inout line;
value : out boolean;
good : out boolean );
procedure read (l : inout line;
value : out boolean );
procedure read (l : inout line;
value : out character;
good : out boolean );
procedure read (l : inout line;
value : out character );
procedure read (l : inout line;
value : out integer;
good : out boolean );
procedure read (l : inout line;
value : out integer );
procedure read (l : inout line;
value : out real;
good : out boolean );
procedure read (l : inout line;
value : out real );
procedure read (l : inout line;
value : out string;
good : out boolean );
procedure read (l : inout line;
value : out string );
procedure read (l : inout line;
value : out time;
good : out boolean );
procedure read (l : inout line;
value : out time );
procedure sread (l : inout line;
value : out string;
strlen : out natural);
alias string_read is sread [line, string, natural];
alias bread is read [line, bit_vector, boolean];
alias bread is read [line, bit_vector];
alias binary_read is read [line, bit_vector, boolean];
alias binary_read is read [line, bit_vector];
procedure oread (l : inout line;
value : out bit_vector;
good : out boolean);
procedure oread (l : inout line;
value : out bit_vector);
alias octal_read is oread [line, bit_vector, boolean];
alias octal_read is oread [line, bit_vector];
procedure hread (l : inout line;
value : out bit_vector;
good : out boolean);
procedure hread (l : inout line;
value : out bit_vector);
alias hex_read is hread [line, bit_vector, boolean];
alias hex_read is hread [line, bit_vector];
procedure writeline (file f : text; l : inout line);
procedure tee (file f : text; l : inout line);
procedure write (l : inout line;
value : in bit;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in boolean;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in character;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in integer;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in real;
justified : in side:= right;
field : in width := 0;
digits : in natural:= 0 );
procedure write (l : inout line;
value : in real;
format : in string );
procedure write (l : inout line;
value : in string;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in time;
justified : in side := right;
field : in width := 0;
unit : in time := ns );
alias swrite is write [line, string, side, width];
alias string_write is write [line, string, side, width];
alias bwrite is write [line, bit_vector, side, width];
alias binary_write is write [line, bit_vector, side, width];
procedure owrite (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0);
alias octal_write is owrite [line, bit_vector, side, width];
procedure hwrite (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0);
alias hex_write is hwrite [line, bit_vector, side, width];
end package;
| gpl-3.0 | 3c92d2bd385c548b604efddc213cb700 | 0.46111 | 4.979577 | false | false | false | false |
nickg/nvc | test/sem/concat.vhd | 1 | 1,297 | entity concat is
end entity;
architecture arch of concat is
type int_array is array (integer range <>) of integer;
begin
process
variable w : int_array(1 to 4);
variable x, y : int_array(1 to 3);
variable z : int_array(1 to 6);
variable s : string(1 to 5);
variable t : int_array(1 to 2);
variable b : bit_vector(1 to 3);
variable c : bit_vector(1 to 4);
begin
x := ( 1, 2, 3 );
y := ( 4, 5, 6 );
z := x & y; -- OK
w := 1 & x; -- OK
w := y & 5; -- OK
s := 'h' & string'("ello"); -- OK
s := 1 & string'("ello"); -- Error
t := 6 & 7; -- OK
t := 7 & character'( 'x' ); -- Error
c := bit_vector(b & '1'); -- OK
assert "10" = ("1" & b(1)); -- OK
assert ("1" & b(1)) = "10"; -- OK
assert "10" = (b(1) & "0"); -- OK
wait;
end process;
process
type mem_type is array (1 to 128) of bit_vector(7 downto 0);
variable mem : mem_type;
variable byte : bit_vector(7 downto 0);
begin
mem := mem(1 to 127) & byte; -- OK
wait;
end process;
end architecture;
| gpl-3.0 | 2a74866021fbadaa761023873a69dd78 | 0.420971 | 3.543716 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2068.vhd | 4 | 2,534 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2068.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02068ent IS
END c07s02b04x00p01n02i02068ent;
ARCHITECTURE c07s02b04x00p01n02i02068arch OF c07s02b04x00p01n02i02068ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable DISTV : DISTANCE := 1 A;
BEGIN
POSV := POSV + DISTV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02068 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02068arch;
| gpl-2.0 | 4dc900f76040db8bbe0c15627fb280db | 0.578532 | 4.060897 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1273/assert5.vhdl | 1 | 460 | library ieee;
use ieee.std_logic_1164.all;
entity assert5 is
port (v : std_logic_Vector (7 downto 0);
en : std_logic;
clk : std_logic;
rst : std_logic;
res : out std_logic);
end;
architecture behav of assert5 is
begin
process (clk, rst)
begin
if rst = '1' then
res <= '0';
elsif rising_edge(clk) and en = '1' then
assert v /= x"05";
res <= v(0) xor v(1);
end if;
end process;
end behav;
| gpl-2.0 | efab46755269f8c63880bb8a5f6e33d4 | 0.565217 | 3.087248 | false | false | false | false |
tgingold/ghdl | testsuite/gna/ticket19/psl_test_cover2.vhd | 2 | 1,252 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_cover2 is
end entity psl_test_cover2;
architecture test of psl_test_cover2 is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 20 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_COVER test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- cover directive seems not supported (ignored by GHDL)
-- psl cover {s_write ; not(s_read)};
end architecture test;
| gpl-2.0 | 216de39292012ca65e15dafc7039fb9d | 0.582268 | 3.091358 | false | true | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/syn/vhdl/doHist.vhd | 4 | 18,248 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity doHist is
generic (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TKEEP : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TUSER : IN STD_LOGIC_VECTOR (1 downto 0);
inStream_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TID : IN STD_LOGIC_VECTOR (4 downto 0);
inStream_TDEST : IN STD_LOGIC_VECTOR (5 downto 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
histo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
histo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_DATA_WIDTH-1 downto 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_DATA_WIDTH/8-1 downto 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_DATA_WIDTH-1 downto 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of doHist is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"doHist,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.860000,HLS_SYN_LAT=524546,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=95,HLS_SYN_LUT=210}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv19_0 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv9_100 : STD_LOGIC_VECTOR (8 downto 0) := "100000000";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv19_40000 : STD_LOGIC_VECTOR (18 downto 0) := "1000000000000000000";
constant ap_const_lv19_1 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000001";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_21 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal inStream_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_53 : BOOLEAN;
signal exitcond_fu_148_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal idxHist_1_fu_137_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_102 : BOOLEAN;
signal idxPixel_1_fu_154_p2 : STD_LOGIC_VECTOR (18 downto 0);
signal idxPixel_1_reg_187 : STD_LOGIC_VECTOR (18 downto 0);
signal ap_sig_108 : BOOLEAN;
signal histo_addr_1_reg_192 : STD_LOGIC_VECTOR (7 downto 0);
signal idxHist_reg_109 : STD_LOGIC_VECTOR (8 downto 0);
signal exitcond2_fu_131_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal idxPixel_reg_120 : STD_LOGIC_VECTOR (18 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_130 : BOOLEAN;
signal tmp_fu_143_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_fu_164_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal histo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_169_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
component doHist_CTRL_BUS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
doHist_CTRL_BUS_s_axi_U : component doHist_CTRL_BUS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_BUS_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_BUS_DATA_WIDTH)
port map (
AWVALID => s_axi_CTRL_BUS_AWVALID,
AWREADY => s_axi_CTRL_BUS_AWREADY,
AWADDR => s_axi_CTRL_BUS_AWADDR,
WVALID => s_axi_CTRL_BUS_WVALID,
WREADY => s_axi_CTRL_BUS_WREADY,
WDATA => s_axi_CTRL_BUS_WDATA,
WSTRB => s_axi_CTRL_BUS_WSTRB,
ARVALID => s_axi_CTRL_BUS_ARVALID,
ARREADY => s_axi_CTRL_BUS_ARREADY,
ARADDR => s_axi_CTRL_BUS_ARADDR,
RVALID => s_axi_CTRL_BUS_RVALID,
RREADY => s_axi_CTRL_BUS_RREADY,
RDATA => s_axi_CTRL_BUS_RDATA,
RRESP => s_axi_CTRL_BUS_RRESP,
BVALID => s_axi_CTRL_BUS_BVALID,
BREADY => s_axi_CTRL_BUS_BREADY,
BRESP => s_axi_CTRL_BUS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
idxHist_reg_109_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond2_fu_131_p2))) then
idxHist_reg_109 <= idxHist_1_fu_137_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
idxHist_reg_109 <= ap_const_lv9_0;
end if;
end if;
end process;
idxPixel_reg_120_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond2_fu_131_p2)))) then
idxPixel_reg_120 <= ap_const_lv19_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
idxPixel_reg_120 <= idxPixel_1_reg_187;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (exitcond_fu_148_p2 = ap_const_lv1_0) and not(ap_sig_108))) then
histo_addr_1_reg_192 <= tmp_3_fu_164_p1(8 - 1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not(ap_sig_108))) then
idxPixel_1_reg_187 <= idxPixel_1_fu_154_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond_fu_148_p2, ap_sig_108, exitcond2_fu_131_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((ap_const_lv1_0 = exitcond2_fu_131_p2)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
if ((not(ap_sig_108) and not((exitcond_fu_148_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((exitcond_fu_148_p2 = ap_const_lv1_0) and not(ap_sig_108))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
ap_done_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, exitcond_fu_148_p2, ap_sig_108)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not(ap_sig_108) and not((exitcond_fu_148_p2 = ap_const_lv1_0)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, exitcond_fu_148_p2, ap_sig_108)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not(ap_sig_108) and not((exitcond_fu_148_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_102_assign_proc : process(ap_CS_fsm)
begin
ap_sig_102 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
ap_sig_108_assign_proc : process(inStream_TVALID, exitcond_fu_148_p2)
begin
ap_sig_108 <= ((exitcond_fu_148_p2 = ap_const_lv1_0) and (inStream_TVALID = ap_const_logic_0));
end process;
ap_sig_130_assign_proc : process(ap_CS_fsm)
begin
ap_sig_130 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
ap_sig_21_assign_proc : process(ap_CS_fsm)
begin
ap_sig_21 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
ap_sig_53_assign_proc : process(ap_CS_fsm)
begin
ap_sig_53 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_21)
begin
if (ap_sig_21) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_102)
begin
if (ap_sig_102) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_53)
begin
if (ap_sig_53) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_130)
begin
if (ap_sig_130) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
exitcond2_fu_131_p2 <= "1" when (idxHist_reg_109 = ap_const_lv9_100) else "0";
exitcond_fu_148_p2 <= "1" when (idxPixel_reg_120 = ap_const_lv19_40000) else "0";
histo_Addr_A <= std_logic_vector(shift_left(unsigned(histo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
histo_Addr_A_orig_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st2_fsm_1, histo_addr_1_reg_192, ap_sig_cseq_ST_st4_fsm_3, tmp_fu_143_p1, tmp_3_fu_164_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
histo_Addr_A_orig <= std_logic_vector(resize(unsigned(histo_addr_1_reg_192),32));
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
histo_Addr_A_orig <= tmp_fu_143_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
histo_Addr_A_orig <= tmp_3_fu_164_p1(32 - 1 downto 0);
else
histo_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
histo_Clk_A <= ap_clk;
histo_Din_A_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, tmp_4_fu_169_p2)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
histo_Din_A <= tmp_4_fu_169_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
histo_Din_A <= ap_const_lv32_0;
else
histo_Din_A <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
histo_EN_A_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_108, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not(ap_sig_108)) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3))) then
histo_EN_A <= ap_const_logic_1;
else
histo_EN_A <= ap_const_logic_0;
end if;
end process;
histo_Rst_A_assign_proc : process(ap_rst_n)
begin
histo_Rst_A <= not(ap_rst_n);
end process;
histo_WEN_A_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond2_fu_131_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond2_fu_131_p2)) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3))) then
histo_WEN_A <= ap_const_lv4_F;
else
histo_WEN_A <= ap_const_lv4_0;
end if;
end process;
idxHist_1_fu_137_p2 <= std_logic_vector(unsigned(idxHist_reg_109) + unsigned(ap_const_lv9_1));
idxPixel_1_fu_154_p2 <= std_logic_vector(unsigned(idxPixel_reg_120) + unsigned(ap_const_lv19_1));
inStream_TDATA_blk_n_assign_proc : process(inStream_TVALID, ap_sig_cseq_ST_st3_fsm_2, exitcond_fu_148_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (exitcond_fu_148_p2 = ap_const_lv1_0))) then
inStream_TDATA_blk_n <= inStream_TVALID;
else
inStream_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
inStream_TREADY_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, exitcond_fu_148_p2, ap_sig_108)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (exitcond_fu_148_p2 = ap_const_lv1_0) and not(ap_sig_108)))) then
inStream_TREADY <= ap_const_logic_1;
else
inStream_TREADY <= ap_const_logic_0;
end if;
end process;
tmp_3_fu_164_p1 <= std_logic_vector(resize(unsigned(inStream_TDATA),64));
tmp_4_fu_169_p2 <= std_logic_vector(unsigned(histo_Dout_A) + unsigned(ap_const_lv32_1));
tmp_fu_143_p1 <= std_logic_vector(resize(unsigned(idxHist_reg_109),64));
end behav;
| gpl-3.0 | 65ec9bfa9ce9933f2d1a787cf660be1d | 0.584941 | 2.906195 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1051/psi_tb_txt_util.vhd | 1 | 19,510 | ------------------------------------------------------------------------------
---- ----
---- Text Utils ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Utils to handle text. Used for the testbenches. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Authors: ----
---- - Oyvind Harboe, oyvind.harboe zylin.com ----
---- - Oliver Bründler, Paul Scherrer Instititute ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Oyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) Paul Scherrer Institute (www.psi.ch) ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: txt_util (Package) ----
---- File name: txt_util.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- std.textio ----
---- Target FPGA: N/A ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
-- library zpu;
package psi_tb_txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
function hstr(slv: unsigned) return string;
-- convert integer to string, VHDL2008 built-in equivalent
function to_string(int : integer) return string;
-- convert real to string, VHDL2008 built-in equivalent
function to_string(num : real) return string;
-- convert signed to string, VHDL2008 built-in equivalent
function to_string(num : signed) return string;
-- convert unsigned to string, VHDL2008 built-in equivalent
function to_string(num : unsigned) return string;
-- convert std_logic_vector to string, VHDL2008 built-in equivalent
function to_string(num : std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
procedure str_write(file out_file: TEXT;
new_string: in string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end package psi_tb_txt_util;
package body psi_tb_txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
--synopsys translate off
write(msg_line, text);
writeline(output, msg_line);
--synopsys translate on
end procedure print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end procedure print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end function chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1):=chr(sl);
return s;
end function str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r:=1;
for i in slv'range loop
result(r) := chr(slv(i));
r:=r+1;
end loop;
return result;
end function str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end function str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end function chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp : string(1 to 10);
variable num : integer;
variable abs_int : integer;
variable len : integer:=1;
variable power : integer:=1;
begin
-- bug fix for negative numbers
abs_int:=abs(int);
num :=abs_int;
while num>=base loop -- Determine how many
len:=len+1; -- characters required
num:=num/base; -- to represent the
end loop; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i):=chr(abs_int/power mod base); -- a string starting
power:=power*base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int<0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end function str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end function str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0):=(others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen:=(slv'left+1)/4;
if (slv'left+1) mod 4/=0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen-1) downto 0 loop
fourbit:=longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen-I):='0';
when "0001" => hex(hexlen-I):='1';
when "0010" => hex(hexlen-I):='2';
when "0011" => hex(hexlen-I):='3';
when "0100" => hex(hexlen-I):='4';
when "0101" => hex(hexlen-I):='5';
when "0110" => hex(hexlen-I):='6';
when "0111" => hex(hexlen-I):='7';
when "1000" => hex(hexlen-I):='8';
when "1001" => hex(hexlen-I):='9';
when "1010" => hex(hexlen-I):='A';
when "1011" => hex(hexlen-I):='B';
when "1100" => hex(hexlen-I):='C';
when "1101" => hex(hexlen-I):='D';
when "1110" => hex(hexlen-I):='E';
when "1111" => hex(hexlen-I):='F';
when "ZZZZ" => hex(hexlen-I):='z';
when "UUUU" => hex(hexlen-I):='u';
when "XXXX" => hex(hexlen-I):='x';
when others => hex(hexlen-I):='?';
end case;
end loop;
return hex(1 to hexlen);
end function hstr;
function hstr(slv: unsigned) return string is
begin
return hstr(std_logic_vector(slv));
end function hstr;
-- VHDL2008 to_string built-in equivalents
function to_string(int : integer) return string is
begin
return str(int);
end function;
function to_string(num : real) return string is
begin
return real'image(num);
end function;
function to_string(num : signed) return string is
begin
return integer'image(to_integer(num));
end function;
function to_string(num : unsigned) return string is
begin
return integer'image(to_integer(num));
end function;
function to_string(num : std_logic_vector) return string is
begin
return str(num);
end function;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u:='A';
when 'b' => u:='B';
when 'c' => u:='C';
when 'd' => u:='D';
when 'e' => u:='E';
when 'f' => u:='F';
when 'g' => u:='G';
when 'h' => u:='H';
when 'i' => u:='I';
when 'j' => u:='J';
when 'k' => u:='K';
when 'l' => u:='L';
when 'm' => u:='M';
when 'n' => u:='N';
when 'o' => u:='O';
when 'p' => u:='P';
when 'q' => u:='Q';
when 'r' => u:='R';
when 's' => u:='S';
when 't' => u:='T';
when 'u' => u:='U';
when 'v' => u:='V';
when 'w' => u:='W';
when 'x' => u:='X';
when 'y' => u:='Y';
when 'z' => u:='Z';
when others => u:=c;
end case;
return u;
end function to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l:='a';
when 'B' => l:='b';
when 'C' => l:='c';
when 'D' => l:='d';
when 'E' => l:='e';
when 'F' => l:='f';
when 'G' => l:='g';
when 'H' => l:='h';
when 'I' => l:='i';
when 'J' => l:='j';
when 'K' => l:='k';
when 'L' => l:='l';
when 'M' => l:='m';
when 'N' => l:='n';
when 'O' => l:='o';
when 'P' => l:='p';
when 'Q' => l:='q';
when 'R' => l:='r';
when 'S' => l:='s';
when 'T' => l:='t';
when 'U' => l:='u';
when 'V' => l:='v';
when 'W' => l:='w';
when 'X' => l:='x';
when 'Y' => l:='y';
when 'Z' => l:='z';
when others => l:=c;
end case;
return l;
end function to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):=to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):=to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl : std_logic;
begin
case c is
when 'U' =>
sl:='U';
when 'X' =>
sl:='X';
when '0' =>
sl:='0';
when '1' =>
sl:='1';
when 'Z' =>
sl:='Z';
when 'W' =>
sl:='W';
when 'L' =>
sl:='L';
when 'H' =>
sl:='H';
when '-' =>
sl:='-';
when others =>
sl:='X';
end case;
return sl;
end function to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv : std_logic_vector(s'high-s'low downto 0);
variable k : integer;
begin
k:=s'high-s'low;
for i in s'range loop
slv(k):=to_std_logic(s(i));
k :=k-1;
end loop;
return slv;
end function to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l : line;
variable c : character;
variable is_string : boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i):=' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l,c,is_string);
res_string(i):=c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end procedure str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l,new_string);
writeline(out_file,l);
end procedure print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l,char);
writeline(out_file,l);
end procedure print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file,new_string(i));
if new_string(i)=LF then -- end of string
exit;
end if;
end loop;
end str_write;
end package body psi_tb_txt_util;
| gpl-2.0 | 026e4d82418bc97413647753fb9982f1 | 0.44482 | 4.349833 | false | false | false | false |
tgingold/ghdl | testsuite/synth/simple01/tb_simple01.vhdl | 1 | 681 | entity tb_simple01 is
end tb_simple01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_simple01 is
signal a : std_logic;
signal b : std_logic;
signal c : std_logic;
signal z : std_logic;
begin
dut: entity work.simple01
port map (a, b, c, z);
process
constant av : std_logic_vector := b"1101";
constant bv : std_logic_vector := b"0111";
constant cv : std_logic_vector := b"0011";
constant zv : std_logic_vector := b"0111";
begin
for i in av'range loop
a <= av (i);
b <= bv (i);
c <= cv (i);
wait for 1 ns;
assert z = zv(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | 5688ffa0cb0bed0956bcd4d971c50c35 | 0.606461 | 3.152778 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth14/top_pkg.vhdl | 1 | 786 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package top_pack is
type top_reg_t is record
prescale : integer range 0 to (2**24)-1;
count : integer range 0 to 3;
blip : std_logic;
y : std_logic_vector(1 to 5);
end record;
constant TOP_REG_RESET : top_reg_t := ( 0, 0, '0', (others => '0') );
function to_slv(C:integer; B:std_logic; E:std_logic) return std_logic_vector;
component top port (
clk : in std_logic;
D : out std_logic_vector(1 to 5));
end component;
end package;
package body top_pack is
function to_slv(C:integer; B:std_logic; E:std_logic) return std_logic_vector is
variable ret : std_logic_vector(1 to 5) := (others => '0');
begin
ret(C+1) := E;
ret(5) := B;
return ret;
end to_slv;
end top_pack;
| gpl-2.0 | 7fd4d8bb738d7f528422ab68e784b4ee | 0.641221 | 2.710345 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/hdl/vhdl/rd_chnl.vhd | 2 | 207,535 | -------------------------------------------------------------------------------
-- rd_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: rd_chnl.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller read channel interfaces. Controls all
-- handshaking and data flow on the AXI read address (AR)
-- and read data (R) channels.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/3/2011 v1.03a
-- ~~~~~~
-- Edits for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/14/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter.
-- Similar edits as wr_chnl on Hsiao ECC code.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update for usage of ecc_gen.vhd module directly from MIG.
-- Clean-up XST warnings.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Found issue with ECC decoding on read path. Remove MSB '0' usage
-- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits.
-- Modify read data signal used in single bit error correction.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Move all MIG functions to package body.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Clean-up unused signal, narrow_addr_inc.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 4/21/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- Add defaults to araddr_pipe_sel & axi_arready_int when in single port mode.
-- Remove use of IF_IS_AXI4 constant.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 5/26/2011 v1.03a
-- ~~~~~~
-- With CR # 609695, update else clause for narrow_burst_cnt_ld to
-- remove simulation warnings when axi_byte_div_curr_arsize = zero.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.wrap_brst;
use work.ua_narrow;
use work.checkbit_handler;
use work.checkbit_handler_64;
use work.correct_one_bit;
use work.correct_one_bit_64;
use work.ecc_gen;
use work.parity;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity rd_chnl is
generic (
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_AXI_ID_WIDTH : integer := 4;
-- AXI ID vector width
C_S_AXI_SUPPORTS_NARROW : integer := 1;
-- Support for narrow burst operations
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to "AXI4LITE" to optimize out burst transaction support
C_SINGLE_PORT_BRAM : integer := 0;
-- Enable single port usage of BRAM
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0 -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
);
port (
-- AXI Global Signals
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI Read Address Channel Signals (AR)
AXI_ARID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_ARADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Specifies the number of data transfers in the burst
-- "0000 0000" 1 data transfer
-- "0000 0001" 2 data transfers
-- ...
-- "1111 1111" 256 data transfers
AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Specifies the max number of data bytes to transfer in each data beat
-- "000" 1 byte to transfer
-- "001" 2 bytes to transfer
-- "010" 3 bytes to transfer
-- ...
AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Specifies burst type
-- "00" FIXED = Fixed burst address (handled as INCR)
-- "01" INCR = Increment burst address
-- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary
-- "11" Reserved (not checked)
AXI_ARLOCK : in std_logic;
AXI_ARCACHE : in std_logic_vector(3 downto 0);
AXI_ARPROT : in std_logic_vector(2 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
AXI_RID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_RDATA : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- ECC Register Interface Signals
Enable_ECC : in std_logic;
BRAM_Addr_En : out std_logic;
CE_Failing_We : out std_logic := '0';
Sl_CE : out std_logic := '0';
Sl_UE : out std_logic := '0';
-- Single Port Arbitration Signals
Arb2AR_Active : in std_logic;
AR2Arb_Active_Clr : out std_logic := '0';
Sng_BRAM_Addr_Ld_En : out std_logic := '0';
Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
Sng_BRAM_Addr_Inc : out std_logic := '0';
Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- BRAM Read Port Interface Signals
BRAM_En : out std_logic;
BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0);
BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
end entity rd_chnl;
-------------------------------------------------------------------------------
architecture implementation of rd_chnl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Set constants for ARLEN equal to a count of one or two beats.
constant AXI_ARLEN_ONE : std_logic_vector(7 downto 0) := (others => '0');
constant AXI_ARLEN_TWO : std_logic_vector(7 downto 0) := "00000001";
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
-- Move to full_axi module
-- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8);
-- Not used
-- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
-- Determine maximum size for narrow burst length counter
-- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits
-- resulting in a count 3 downto 0 => so minimum counter width = 2 bits.
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits
-- resulting in a count 31 downto 0 => so minimum counter width = 5 bits.
constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8);
constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- Max length burst count AXI4 specification
constant C_MAX_BRST_CNT : integer := 256;
constant C_BRST_CNT_SIZE : integer := log2 (C_MAX_BRST_CNT);
-- When the burst count = 0
constant C_BRST_CNT_ZERO : std_logic_vector(C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- Burst count = 1
constant C_BRST_CNT_ONE : std_logic_vector(7 downto 0) := "00000001";
-- Burst count = 2
constant C_BRST_CNT_TWO : std_logic_vector(7 downto 0) := "00000010";
-- Read data mux select constants (for signal rddata_mux_sel)
-- '0' selects BRAM
-- '1' selects read skid buffer
constant C_RDDATA_MUX_BRAM : std_logic := '0';
constant C_RDDATA_MUX_SKID_BUF : std_logic := '1';
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
-- AXI Burst Types
-- AXI Spec 4.4
constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10";
constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01";
constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00";
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Internal ECC data width size.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH);
-- For use with ECC functions (to use LUT6 components or let synthesis infer the optimal implementation).
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_ADDR_SM_TYPE is ( IDLE,
LD_ARADDR
);
signal rd_addr_sm_cs, rd_addr_sm_ns : RD_ADDR_SM_TYPE;
signal ar_active_set : std_logic := '0';
signal ar_active_set_i : std_logic := '0';
signal ar_active_clr : std_logic := '0';
signal ar_active : std_logic := '0';
signal ar_active_d1 : std_logic := '0';
signal ar_active_re : std_logic := '0';
signal axi_araddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal curr_araddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
signal araddr_pipe_ld : std_logic := '0';
signal araddr_pipe_ld_i : std_logic := '0';
signal araddr_pipe_sel : std_logic := '0';
-- '0' indicates mux select from AXI
-- '1' indicates mux select from AR Addr Register
signal axi_araddr_full : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal axi_early_arready_int : std_logic := '0';
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_d2 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
signal axi_aresetn_re_reg : std_logic := '0';
signal no_ar_ack_cmb : std_logic := '0';
signal no_ar_ack : std_logic := '0';
signal pend_rd_op_cmb : std_logic := '0';
signal pend_rd_op : std_logic := '0';
signal axi_arid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_arsize_pipe : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arsize_pipe_4byte : std_logic := '0';
signal axi_arsize_pipe_8byte : std_logic := '0';
signal axi_arsize_pipe_16byte : std_logic := '0';
signal axi_arsize_pipe_32byte : std_logic := '0';
-- v1.03a
signal axi_arsize_pipe_max : std_logic := '0';
signal curr_arsize : std_logic_vector (2 downto 0) := (others => '0');
signal curr_arsize_reg : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arlen_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arlen_pipe_1_or_2 : std_logic := '0';
signal curr_arlen : std_logic_vector(7 downto 0) := (others => '0');
signal curr_arlen_reg : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arburst_pipe : std_logic_vector(1 downto 0) := (others => '0');
signal axi_arburst_pipe_fixed : std_logic := '0';
signal curr_arburst : std_logic_vector(1 downto 0) := (others => '0');
signal curr_wrap_burst : std_logic := '0';
signal curr_wrap_burst_reg : std_logic := '0';
signal max_wrap_burst : std_logic := '0';
signal curr_incr_burst : std_logic := '0';
signal curr_fixed_burst : std_logic := '0';
signal curr_fixed_burst_reg : std_logic := '0';
-- BRAM Address Counter
signal bram_addr_ld_en : std_logic := '0';
signal bram_addr_ld_en_i : std_logic := '0';
signal bram_addr_ld_en_mod : std_logic := '0';
signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_inc : std_logic := '0';
signal bram_addr_inc_mod : std_logic := '0';
signal bram_addr_inc_wrap_mod : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_DATA_SM_TYPE is ( IDLE,
SNG_ADDR,
SEC_ADDR,
FULL_PIPE,
FULL_THROTTLE,
LAST_ADDR,
LAST_THROTTLE,
LAST_DATA,
LAST_DATA_AR_PEND
);
signal rd_data_sm_cs, rd_data_sm_ns : RD_DATA_SM_TYPE;
signal rd_adv_buf : std_logic := '0';
signal axi_rd_burst : std_logic := '0';
signal axi_rd_burst_two : std_logic := '0';
signal act_rd_burst : std_logic := '0';
signal act_rd_burst_set : std_logic := '0';
signal act_rd_burst_clr : std_logic := '0';
signal act_rd_burst_two : std_logic := '0';
-- Rd Data Buffer/Register
signal rd_skid_buf_ld_cmb : std_logic := '0';
signal rd_skid_buf_ld_reg : std_logic := '0';
signal rd_skid_buf_ld : std_logic := '0';
signal rd_skid_buf_ld_imm : std_logic := '0';
signal rd_skid_buf : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal rddata_mux_sel_cmb : std_logic := '0';
signal rddata_mux_sel : std_logic := '0';
signal axi_rdata_en : std_logic := '0';
signal axi_rdata_mux : std_logic_vector (C_AXI_DATA_WIDTH+8*C_ECC-1 downto 0) := (others => '0');
-- Read Burst Counter
signal brst_cnt_max : std_logic := '0';
signal brst_cnt_max_d1 : std_logic := '0';
signal brst_cnt_max_re : std_logic := '0';
signal end_brst_rd_clr_cmb : std_logic := '0';
signal end_brst_rd_clr : std_logic := '0';
signal end_brst_rd : std_logic := '0';
signal brst_zero : std_logic := '0';
signal brst_one : std_logic := '0';
signal brst_cnt_ld : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
signal brst_cnt_rst : std_logic := '0';
signal brst_cnt_ld_en : std_logic := '0';
signal brst_cnt_ld_en_i : std_logic := '0';
signal brst_cnt_dec : std_logic := '0';
signal brst_cnt : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- AXI Read Response Signals
signal axi_rid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp_full : std_logic := '0';
signal axi_rid_temp_full_d1 : std_logic := '0';
signal axi_rid_temp_full_fe : std_logic := '0';
signal axi_rid_temp2 : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp2_full : std_logic := '0';
signal axi_b2b_rid_adv : std_logic := '0';
signal axi_rid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_clr_ok : std_logic := '0';
signal axi_rvalid_set_cmb : std_logic := '0';
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
-- Internal BRAM Signals
signal bram_en_cmb : std_logic := '0';
signal bram_en_int : std_logic := '0';
signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
-- Narrow Burst Signals
signal curr_narrow_burst_cmb : std_logic := '0';
signal curr_narrow_burst : std_logic := '0';
signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_addr_rst : std_logic := '0';
signal narrow_addr_ld_en : std_logic := '0';
signal narrow_addr_dec : std_logic := '0';
signal narrow_bram_addr_inc : std_logic := '0';
signal narrow_bram_addr_inc_d1 : std_logic := '0';
signal narrow_bram_addr_inc_re : std_logic := '0';
signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal curr_ua_narrow_wrap : std_logic := '0';
signal curr_ua_narrow_incr : std_logic := '0';
signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- State machine type declarations
type RLAST_SM_TYPE is ( IDLE,
W8_THROTTLE,
W8_2ND_LAST_DATA,
W8_LAST_DATA,
-- W8_LAST_DATA_B2,
W8_THROTTLE_B2
);
signal rlast_sm_cs, rlast_sm_ns : RLAST_SM_TYPE;
signal last_bram_addr : std_logic := '0';
signal set_last_bram_addr : std_logic := '0';
signal alast_bram_addr : std_logic := '0';
signal rd_b2b_elgible : std_logic := '0';
signal rd_b2b_elgible_no_thr_check : std_logic := '0';
signal throttle_last_data : std_logic := '0';
signal disable_b2b_brst_cmb : std_logic := '0';
signal disable_b2b_brst : std_logic := '0';
signal axi_b2b_brst_cmb : std_logic := '0';
signal axi_b2b_brst : std_logic := '0';
signal do_cmplt_burst_cmb : std_logic := '0';
signal do_cmplt_burst : std_logic := '0';
signal do_cmplt_burst_clr : std_logic := '0';
-------------------------------------------------------------------------------
-- ECC Signals
-------------------------------------------------------------------------------
signal UnCorrectedRdData : std_logic_vector (0 to C_AXI_DATA_WIDTH-1) := (others => '0');
-- Move vector from core ECC module to use in AXI RDATA register output
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to ECC @ 32-bit data width
signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to ECC @ 64-bit data width
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Sl_UE_i : std_logic := '0';
signal UE_Q : std_logic := '0';
-- v1.03a
-- Hsiao ECC
signal syndrome_r : std_logic_vector (C_INT_ECC_WIDTH - 1 downto 0) := (others => '0');
constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- AXI Read Address Channel Output Signals
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_DUAL
-- Purpose: Generate AXI_ARREADY when in dual port mode.
---------------------------------------------------------------------------
GEN_ARREADY_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-- Ensure ARREADY only gets asserted early when acknowledge recognized
-- on AXI read data channel.
AXI_ARREADY <= axi_arready_int or (axi_early_arready_int and rd_adv_buf);
end generate GEN_ARREADY_DUAL;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_SNG
-- Purpose: Generate AXI_ARREADY when in single port mode.
---------------------------------------------------------------------------
GEN_ARREADY_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- ARREADY generated by sng_port_arb module
AXI_ARREADY <= '0';
axi_arready_int <= '0';
end generate GEN_ARREADY_SNG;
---------------------------------------------------------------------------
-- AXI Read Data Channel Output Signals
---------------------------------------------------------------------------
-- UE flag is detected is same clock cycle that read data is presented on
-- the AXI bus. Must drive SLVERR combinatorially to align with corrupted
-- detected data word.
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
AXI_RVALID <= axi_rvalid_int;
AXI_RID <= axi_rid_int;
AXI_RLAST <= axi_rlast_int;
---------------------------------------------------------------------------
--
-- *** AXI Read Address Channel Interface ***
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_SNG
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- Unused AW pipeline (set default values)
araddr_pipe_ld <= '0';
axi_araddr_pipe <= AXI_ARADDR;
axi_arid_pipe <= AXI_ARID;
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
axi_arlen_pipe_1_or_2 <= '0';
axi_arburst_pipe_fixed <= '0';
axi_araddr_full <= '0';
end generate GEN_AR_PIPE_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_DUAL
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-----------------------------------------------------------------------
-- AXI Read Address Buffer/Register
-- (mimic behavior of address pipeline for AXI_ARID)
-----------------------------------------------------------------------
GEN_ARADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate
begin
REG_ARADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
axi_araddr_pipe (i) <= AXI_ARADDR (i);
else
axi_araddr_pipe (i) <= axi_araddr_pipe (i);
end if;
end if;
end process REG_ARADDR;
end generate GEN_ARADDR;
-------------------------------------------------------------------
-- Register ARID
-- No reset condition to save resources/timing
-------------------------------------------------------------------
REG_ARID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arid_pipe <= AXI_ARID;
else
axi_arid_pipe <= axi_arid_pipe;
end if;
end if;
end process REG_ARID;
---------------------------------------------------------------------------
-- In parallel to ARADDR pipeline and ARID
-- Use same control signals to capture AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST.
-- Register AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST
-- No reset condition to save resources/timing
REG_ARCTRL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
else
axi_arsize_pipe <= axi_arsize_pipe;
axi_arlen_pipe <= axi_arlen_pipe;
axi_arburst_pipe <= axi_arburst_pipe;
end if;
end if;
end process REG_ARCTRL;
---------------------------------------------------------------------------
-- Create signals that indicate value of AXI_ARLEN in pipeline stage
-- Used to decode length of burst when BRAM address can be loaded early
-- when pipeline is full.
--
-- Add early decode of ARBURST in pipeline.
-- Copy logic from WR_CHNL module (similar logic).
-- Add early decode of ARSIZE = 4 bytes in pipeline.
REG_ARLEN_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
-- Create merge to decode ARLEN of ONE or TWO
if (AXI_ARLEN = AXI_ARLEN_ONE) or (AXI_ARLEN = AXI_ARLEN_TWO) then
axi_arlen_pipe_1_or_2 <= '1';
else
axi_arlen_pipe_1_or_2 <= '0';
end if;
-- Early decode on value in pipeline of ARBURST
if (AXI_ARBURST = C_AXI_BURST_FIXED) then
axi_arburst_pipe_fixed <= '1';
else
axi_arburst_pipe_fixed <= '0';
end if;
else
axi_arlen_pipe_1_or_2 <= axi_arlen_pipe_1_or_2;
axi_arburst_pipe_fixed <= axi_arburst_pipe_fixed;
end if;
end if;
end process REG_ARLEN_PIPE;
---------------------------------------------------------------------------
-- Create full flag for ARADDR pipeline
-- Set when read address register is loaded.
-- Cleared when read address stored in register is loaded into BRAM
-- address counter.
REG_RDADDR_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- (bram_addr_ld_en = '1' and araddr_pipe_sel = '1') then
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and araddr_pipe_ld = '0') then
axi_araddr_full <= '0';
elsif (araddr_pipe_ld = '1') then
axi_araddr_full <= '1';
else
axi_araddr_full <= axi_araddr_full;
end if;
end if;
end process REG_RDADDR_FULL;
---------------------------------------------------------------------------
end generate GEN_AR_PIPE_DUAL;
---------------------------------------------------------------------------
-- v1.03a
-- Add early decode of ARSIZE = max size in pipeline based on AXI data
-- bus width (use constant, C_AXI_SIZE_MAX)
REG_ARSIZE_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arsize_pipe_max <= '0';
elsif (araddr_pipe_ld = '1') then
-- Early decode of ARSIZE in pipeline equal to max # of bytes
-- based on AXI data bus width
if (AXI_ARSIZE = C_AXI_SIZE_MAX) then
axi_arsize_pipe_max <= '1';
else
axi_arsize_pipe_max <= '0';
end if;
else
axi_arsize_pipe_max <= axi_arsize_pipe_max;
end if;
end if;
end process REG_ARSIZE_PIPE;
---------------------------------------------------------------------------
-- Generate: GE_ARREADY
-- Purpose: ARREADY is only created here when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_ARREADY: if (C_SINGLE_PORT_BRAM = 0) generate
begin
----------------------------------------------------------------------------
-- AXI_ARREADY Output Register
-- Description: Keep AXI_ARREADY output asserted until ARADDR pipeline
-- is full. When a full condition is reached, negate
-- ARREADY as another AR address can not be accepted.
-- Add condition to keep ARReady asserted if loading current
--- ARADDR pipeline value into the BRAM address counter.
-- Indicated by assertion of bram_addr_ld_en & araddr_pipe_sel.
--
----------------------------------------------------------------------------
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arready_int <= '0';
-- Detect end of S_AXI_AResetn to assert AWREADY and accept
-- new AWADDR values
elsif (axi_aresetn_re_reg = '1') or
-- Add condition for early ARREADY to keep pipeline full
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and axi_early_arready_int = '0') then
axi_arready_int <= '1';
-- Add conditional check if ARREADY is asserted (with ARVALID) (one clock cycle later)
-- when the address pipeline is full.
elsif (araddr_pipe_ld = '1') or
(AXI_ARVALID = '1' and axi_arready_int = '1' and axi_araddr_full = '1') then
axi_arready_int <= '0';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
----------------------------------------------------------------------------
REG_EARLY_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_early_arready_int <= '0';
-- Pending ARADDR and ARREADY is not yet asserted to accept
-- operation (due to ARADDR being full)
elsif (AXI_ARVALID = '1' and axi_arready_int = '0' and
axi_araddr_full = '1') and
(alast_bram_addr = '1') and
-- Add check for elgible back-to-back BRAM load
(rd_b2b_elgible = '1') then
axi_early_arready_int <= '1';
else
axi_early_arready_int <= '0';
end if;
end if;
end process REG_EARLY_ARREADY;
---------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert ARREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
axi_aresetn_d2 <= axi_aresetn_d1;
axi_aresetn_re_reg <= axi_aresetn_re;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL_ADDR_CNT
-- Purpose: Instantiate BRAM address counter unique for wr_chnl logic
-- only when controller configured in dual port mode.
---------------------------------------------------------------------------
GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- Replace I_ADDR_CNT module usage of pf_counter in proc_common library.
-- Only need to use lower 12-bits of address due to max AXI burst size
-- Since AXI guarantees bursts do not cross 4KB boundary, the counting part
-- of I_ADDR_CNT can be reduced to max 4KB.
--
-- No reset on bram_addr_int.
-- Increment ONLY.
REG_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (bram_addr_ld_en_mod = '1') then
bram_addr_int <= bram_addr_ld;
elsif (bram_addr_inc_mod = '1') then
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process REG_ADDR_CNT;
---------------------------------------------------------------------------
-- Set defaults to shared address counter
-- Only used in single port configurations
Sng_BRAM_Addr_Ld_En <= '0';
Sng_BRAM_Addr_Ld <= (others => '0');
Sng_BRAM_Addr_Inc <= '0';
end generate GEN_DUAL_ADDR_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_SNG_ADDR_CNT
-- Purpose: When configured in single port BRAM mode, address counter
-- is shared with rd_chnl module. Assign output signals here
-- to counter instantiation at full_axi module level.
---------------------------------------------------------------------------
GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod;
Sng_BRAM_Addr_Ld <= bram_addr_ld;
Sng_BRAM_Addr_Inc <= bram_addr_inc_mod;
bram_addr_int <= Sng_BRAM_Addr;
end generate GEN_SNG_ADDR_CNT;
---------------------------------------------------------------------------
-- BRAM address load mux.
-- Either load BRAM counter directly from AXI bus or from stored registered value
-- Use registered signal to indicate current operation is a WRAP burst
--
-- Match bram_addr_ld to what asserts bram_addr_ld_en_mod
-- Include bram_addr_inc_mod when asserted to use bram_addr_ld_wrap value
-- (otherwise use pipelined or AXI bus value to load BRAM address counter)
bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1') else
axi_araddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
---------------------------------------------------------------------------
-- On wrap burst max loads (simultaneous BRAM address increment is asserted).
-- Ensure that load has higher priority over increment.
-- Use registered signal to indicate current operation is a WRAP burst
bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
(max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1'))
else '0';
-- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal
-- logic. No need for the check if the current operation is NOT a fixed AND a wrap
-- burst. The transfer will be one or the other.
-- Found issue when narrow FIXED length burst is incorrectly
-- incrementing BRAM address counter
bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0')
else narrow_bram_addr_inc_re;
----------------------------------------------------------------------------
-- Narrow bursting
--
-- Handle read burst addressing on narrow burst operations
-- Intercept BRAM address increment flag, bram_addr_inc and only
-- increment address when the number of BRAM reads match the width of the
-- AXI data bus.
-- For a 32-bit BRAM, byte burst will increment the BRAM address
-- after four reads from BRAM.
-- For a 256-bit BRAM, a byte burst will increment the BRAM address
-- after 32 reads from BRAM.
-- Based on current operation being a narrow burst, hold off BRAM
-- address increment until narrow burst fits BRAM data width.
-- For non narrow burst operations, use bram_addr_inc from data SM.
--
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
-- bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
-- narrow_bram_addr_inc_re;
--
--
-- Replace w/ below generate statements based on supporting narrow transfers or not.
-- Create generate statement around the signal assignment for bram_addr_inc_mod.
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_INC_MOD_W_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are supported in design instantiation.
---------------------------------------------------------------------------
GEN_BRAM_INC_MOD_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
(narrow_bram_addr_inc_re and not (curr_fixed_burst_reg));
end generate GEN_BRAM_INC_MOD_W_NARROW;
---------------------------------------------------------------------------
-- Generate: GEN_WO_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are not supported in the design instantiation.
-- Drive default values for narrow counter and logic when
-- narrow operation support is disabled.
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg);
narrow_addr_rst <= '0';
narrow_burst_cnt_ld_mod <= (others => '0');
narrow_addr_dec <= '0';
narrow_addr_ld_en <= '0';
narrow_bram_addr_inc <= '0';
narrow_bram_addr_inc_d1 <= '0';
narrow_bram_addr_inc_re <= '0';
narrow_addr_int <= (others => '0');
curr_narrow_burst <= '0';
end generate GEN_WO_NARROW;
---------------------------------------------------------------------------
--
-- Only instantiate NARROW_CNT and supporting logic when narrow transfers
-- are supported and utilized by masters in the AXI system.
-- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this.
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT
-- Purpose: Instantiate narrow counter and logic when narrow
-- operation support is enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- Generate seperate smaller counter for narrow burst operations
-- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library.
--
-- Counter size is adjusted based on size of data burst.
--
-- For example, 32-bit data width BRAM, minimum narrow width
-- burst is 8 bits resulting in a count 3 downto 0. So the
-- minimum counter width = 2 bits.
--
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst
-- is 8 bits resulting in a count 31 downto 0. So the
-- minimum counter width = 5 bits.
--
-- Size of counter = C_NARROW_BURST_CNT_LEN
--
---------------------------------------------------------------------------
REG_NARROW_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (narrow_addr_rst = '1') then
narrow_addr_int <= (others => '0');
-- Load enable
elsif (narrow_addr_ld_en = '1') then
narrow_addr_int <= narrow_burst_cnt_ld_mod;
-- Decrement ONLY (no increment functionality)
elsif (narrow_addr_dec = '1') then
narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <=
std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1);
end if;
end if;
end process REG_NARROW_CNT;
---------------------------------------------------------------------------
narrow_addr_rst <= not (S_AXI_AResetn);
-- Modify narrow burst count load value based on
-- unalignment of AXI address value
narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else
narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else
narrow_burst_cnt_ld_reg;
narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0';
narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re;
narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and
(curr_narrow_burst = '1')
-- Ensure that narrow address counter doesn't
-- flag max or get loaded to
-- reset narrow counter until AXI read data
-- bus has acknowledged current
-- data on the AXI bus. Use rd_adv_buf signal
-- to indicate the non throttle
-- condition on the AXI bus.
and (bram_addr_inc = '1')
else '0';
----------------------------------------------------------------------------
-- Detect rising edge of narrow_bram_addr_inc
REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_bram_addr_inc_d1 <= '0';
else
narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc;
end if;
end if;
end process REG_NARROW_BRAM_ADDR_INC;
narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and
(narrow_bram_addr_inc_d1 = '0')
else '0';
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT;
----------------------------------------------------------------------------
-- Specify current ARSIZE signal
-- Address pipeline MUX
curr_arsize <= axi_arsize_pipe when (araddr_pipe_sel = '1') else AXI_ARSIZE;
REG_ARSIZE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_arsize_reg <= (others => '0');
-- Register curr_arsize when bram_addr_ld_en = '1'
elsif (bram_addr_ld_en = '1') then
curr_arsize_reg <= curr_arsize;
else
curr_arsize_reg <= curr_arsize_reg;
end if;
end if;
end process REG_ARSIZE;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_EN
-- Purpose: Only instantiate logic to determine if current burst
-- is a narrow burst when narrow bursting logic is supported.
---------------------------------------------------------------------------
GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-----------------------------------------------------------------------
-- Determine "narrow" burst transfers
-- Compare the ARSIZE to the BRAM data width
-----------------------------------------------------------------------
-- v1.03a
-- Detect if current burst operation is of size /= to the full
-- AXI data bus width. If not, then the current operation is a
-- "narrow" burst.
curr_narrow_burst_cmb <= '1' when (curr_arsize /= C_AXI_SIZE_MAX) else '0';
---------------------------------------------------------------------------
-- Register flag indicating the current operation
-- is a narrow read burst
NARROW_BURST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Need to reset this flag at end of narrow burst operation
-- Ensure if curr_narrow_burst got set during previous transaction, axi_rlast_set
-- doesn't clear the flag (add check for pend_rd_op negated).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_set = '1' and pend_rd_op = '0' and bram_addr_ld_en = '0') then
curr_narrow_burst <= '0';
-- Add check for burst operation using ARLEN value
-- Ensure that narrow burst flag does not get set during FIXED burst types
elsif (bram_addr_ld_en = '1') and (curr_arlen /= AXI_ARLEN_ONE) and
(curr_fixed_burst = '0') then
curr_narrow_burst <= curr_narrow_burst_cmb;
end if;
end if;
end process NARROW_BURST_REG;
end generate GEN_NARROW_EN;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT_LD
-- Purpose: Only instantiate logic to determine narrow burst counter
-- load value when narrow bursts are enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
signal curr_arsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal axi_byte_div_curr_arsize : integer := 1;
begin
-- v1.03a
-- Create narrow burst counter load value based on current operation
-- "narrow" data width (indicated by value of AWSIZE).
curr_arsize_unsigned <= unsigned (curr_arsize);
-- XST does not support divisors that are not constants and powers of 2.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- narrow_burst_cnt_ld <= std_logic_vector (
-- to_unsigned (
-- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_arsize_unsigned))) ) - 1,
-- C_NARROW_BURST_CNT_LEN));
-- -- With this new process and subsequent signal assignment:
-- DIV_AWSIZE: process (curr_arsize_unsigned)
-- begin
--
-- case (to_integer (curr_arsize_unsigned)) is
-- when 0 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
-- when 1 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
-- when 2 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
-- when 3 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
-- when 4 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
-- when 5 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
-- when 6 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
-- when 7 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
-- --coverage off
-- when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
-- --coverage on
-- end case;
--
-- end process DIV_AWSIZE;
-- w/ CR # 609695
-- With this new process and subsequent signal assignment:
DIV_AWSIZE: process (curr_arsize_unsigned)
begin
case (curr_arsize_unsigned) is
when "000" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
--coverage off
when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
--coverage on
end case;
end process DIV_AWSIZE;
-- v1.03a
-- Replace with new signal assignment.
-- For synthesis to support only divisors that are constant and powers of two.
-- Updated else clause for simulation warnings w/ CR # 609695
narrow_burst_cnt_ld <= std_logic_vector (
to_unsigned (
(axi_byte_div_curr_arsize) - 1, C_NARROW_BURST_CNT_LEN))
when (axi_byte_div_curr_arsize > 0)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
-- Register narrow burst count load indicator
REG_NAR_BRST_CNT_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_burst_cnt_ld_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld;
else
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg;
end if;
end if;
end process REG_NAR_BRST_CNT_LD;
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT_LD;
----------------------------------------------------------------------------
-- Handling for WRAP burst types
--
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Boundary is reached based on ARSIZE and ARLEN.
--
-- Goal is to minimize muxing on initial load of counter value.
-- On WRAP burst types, detect when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value set to '0'.
----------------------------------------------------------------------------
-- Detect valid WRAP burst types
curr_wrap_burst <= '1' when (curr_arburst = C_AXI_BURST_WRAP) else '0';
curr_incr_burst <= '1' when (curr_arburst = C_AXI_BURST_INCR) else '0';
curr_fixed_burst <= '1' when (curr_arburst = C_AXI_BURST_FIXED) else '0';
----------------------------------------------------------------------------
-- Register curr_wrap_burst & curr_fixed_burst signals when BRAM
-- address counter is initially loaded
REG_CURR_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_wrap_burst_reg <= '0';
curr_fixed_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_wrap_burst_reg <= curr_wrap_burst;
curr_fixed_burst_reg <= curr_fixed_burst;
else
curr_wrap_burst_reg <= curr_wrap_burst_reg;
curr_fixed_burst_reg <= curr_fixed_burst_reg;
end if;
end if;
end process REG_CURR_BRST;
---------------------------------------------------------------------------
-- Instance: I_WRAP_BRST
--
-- Description:
--
-- Instantiate WRAP_BRST module
-- Logic to generate the wrap around value to load into the BRAM address
-- counter on WRAP burst transactions.
-- WRAP value is based on current ARLEN, ARSIZE (for narrows) and
-- data width of BRAM module.
--
---------------------------------------------------------------------------
I_WRAP_BRST : entity work.wrap_brst
generic map (
C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
curr_axlen => curr_arlen ,
curr_axsize => curr_arsize ,
curr_narrow_burst => curr_narrow_burst ,
narrow_bram_addr_inc_re => narrow_bram_addr_inc_re ,
bram_addr_ld_en => bram_addr_ld_en ,
bram_addr_ld => bram_addr_ld ,
bram_addr_int => bram_addr_int ,
bram_addr_ld_wrap => bram_addr_ld_wrap ,
max_wrap_burst_mod => max_wrap_burst
);
----------------------------------------------------------------------------
-- Specify current ARBURST signal
-- Input address pipeline MUX
curr_arburst <= axi_arburst_pipe when (araddr_pipe_sel = '1') else AXI_ARBURST;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_arlen <= axi_arlen_pipe when (araddr_pipe_sel = '1') else AXI_ARLEN;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_UA_NARROW
-- Purpose: Only instantiate logic for burst narrow WRAP operations when
-- AXI bus protocol is not set for AXI-LITE and narrow
-- burst operations are supported.
--
---------------------------------------------------------------------------
GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- New logic to detect unaligned address on a narrow WRAP burst transaction.
-- If this condition is met, then the narrow burst counter will be
-- initially loaded with an offset value corresponding to the unalignment
-- in the ARADDR value.
--
--
-- Create a sub module for all logic to determine the narrow burst counter
-- offset value on unaligned WRAP burst operations.
--
-- Module generates the following signals:
--
-- => curr_ua_narrow_wrap, to indicate the current
-- operation is an unaligned narrow WRAP burst.
--
-- => curr_ua_narrow_incr, to load narrow burst counter
-- for unaligned INCR burst operations.
--
-- => ua_narrow_load, narrow counter load value.
-- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0)
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Instance: I_UA_NARROW
--
-- Description:
--
-- Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- Logic is customized for each C_AXI_DATA_WIDTH.
--
---------------------------------------------------------------------------
I_UA_NARROW : entity work.ua_narrow
generic map (
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN
)
port map (
curr_wrap_burst => curr_wrap_burst , -- in
curr_incr_burst => curr_incr_burst , -- in
bram_addr_ld_en => bram_addr_ld_en , -- in
curr_axlen => curr_arlen , -- in
curr_axsize => curr_arsize , -- in
curr_axaddr_lsb => curr_araddr_lsb , -- in
curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out
curr_ua_narrow_incr => curr_ua_narrow_incr , -- out
ua_narrow_load => ua_narrow_load -- out
);
-- Use in all C_AXI_DATA_WIDTH generate statements
-- Only probe least significant BRAM address bits
-- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0.
curr_araddr_lsb <= axi_araddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0);
end generate GEN_UA_NARROW;
----------------------------------------------------------------------------
--
-- New logic to detect if pending operation in ARADDR pipeline is
-- elgible for back-to-back no "bubble" performance. And BRAM address
-- counter can be loaded upon last BRAM address presented for the current
-- operation.
-- This condition exists when the ARADDR pipeline is full and the pending
-- operation is a burst >= length of two data beats.
-- And not a FIXED burst type (must be INCR or WRAP type).
-- The DATA SM handles detecting a throttle condition and will void
-- the capability to be a back-to-back in performance transaction.
--
-- Add check if new operation is a narrow burst (to be loaded into BRAM
-- counter)
-- Add check for throttling condition on after last BRAM address is
-- presented
--
----------------------------------------------------------------------------
-- v1.03a
rd_b2b_elgible_no_thr_check <= '1' when (axi_araddr_full = '1') and
(axi_arlen_pipe_1_or_2 /= '1') and
(axi_arburst_pipe_fixed /= '1') and
(disable_b2b_brst = '0') and
(axi_arsize_pipe_max = '1')
else '0';
rd_b2b_elgible <= '1' when (rd_b2b_elgible_no_thr_check = '1') and
(throttle_last_data = '0')
else '0';
-- Check if SM is in LAST_THROTTLE state which also indicates we are throttling at
-- the last data beat in the read burst. Ensures that the bursts are not implemented
-- as back-to-back bursts and RVALID will negate upon recognition of RLAST and RID
-- pipeline will be advanced properly.
-- Fix timing path on araddr_pipe_sel generated in RDADDR SM
-- SM uses rd_b2b_elgible signal which checks throttle condition on
-- last data beat to hold off loading new BRAM address counter for next
-- back-to-back operation.
-- Attempt to modify logic in generation of throttle_last_data signal.
throttle_last_data <= '1' when ((brst_zero = '1') and (rd_adv_buf = '0')) or
(rd_data_sm_cs = LAST_THROTTLE)
else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_AR_SNG
-- Purpose: If single port BRAM configuration, set all AR flags from
-- logic generated in sng_port_arb module.
--
---------------------------------------------------------------------------
GEN_AR_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
araddr_pipe_sel <= '0'; -- Unused in single port configuration
ar_active <= Arb2AR_Active;
bram_addr_ld_en <= ar_active_re;
brst_cnt_ld_en <= ar_active_re;
AR2Arb_Active_Clr <= axi_rlast_int and AXI_RREADY;
-- Rising edge detect of Arb2AR_Active
RE_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Clear ar_active_d1 early w/ ar_active
-- So back to back ar_active assertions see the new transaction
-- and initiate the read transfer.
if (S_AXI_AResetn = C_RESET_ACTIVE) or ((axi_rlast_int and AXI_RREADY) = '1') then
ar_active_d1 <= '0';
else
ar_active_d1 <= ar_active;
end if;
end if;
end process RE_AR_ACT;
ar_active_re <= '1' when (ar_active = '1' and ar_active_d1 = '0') else '0';
end generate GEN_AR_SNG;
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_DUAL
-- Purpose: Generate AW control state machine logic only when AXI4
-- controller is configured for dual port mode. In dual port
-- mode, wr_chnl has full access over AW & port A of BRAM.
--
---------------------------------------------------------------------------
GEN_AR_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
AR2Arb_Active_Clr <= '0'; -- Only used in single port case
---------------------------------------------------------------------------
-- RD ADDR State Machine
--
-- Description: Central processing unit for AXI write address
-- channel interface handling and handshaking.
--
-- Outputs: araddr_pipe_ld Not Registered
-- araddr_pipe_sel Not Registered
-- bram_addr_ld_en Not Registered
-- brst_cnt_ld_en Not Registered
-- ar_active_set Not Registered
--
-- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_ADDR_SM_CMB_PROCESS: process ( AXI_ARVALID,
axi_araddr_full,
ar_active,
no_ar_ack,
pend_rd_op,
last_bram_addr,
rd_b2b_elgible,
rd_addr_sm_cs )
begin
-- assign default values for state machine outputs
rd_addr_sm_ns <= rd_addr_sm_cs;
araddr_pipe_ld_i <= '0';
bram_addr_ld_en_i <= '0';
brst_cnt_ld_en_i <= '0';
ar_active_set_i <= '0';
case rd_addr_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
else
rd_addr_sm_ns <= IDLE;
end if;
elsif (AXI_ARVALID = '1') then
-- If address pipeline is full
-- ARReady output is negated
-- Remain in this state
--
-- Add check for already pending read operation
-- in data SM, but waiting on throttle (even though ar_active is
-- already set to '0').
if (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- Address counter is currently busy
else
-- Check if ARADDR pipeline is not full and can be loaded
if (axi_araddr_full = '0') then
rd_addr_sm_ns <= LD_ARADDR;
araddr_pipe_ld_i <= '1';
end if;
end if; -- ar_active
-- Pending operation in pipeline that is waiting
-- until current operation is complete (ar_active = '0')
elsif (axi_araddr_full = '1') and
(ar_active = '0') and
(no_ar_ack = '0') and
(pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
end if; -- ARVALID
---------------------------- LD_ARADDR State ---------------------------
when LD_ARADDR =>
-- Check here for subsequent BRAM address load when ARADDR pipe is loaded
-- in previous clock cycle.
--
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
-- Stay in this state another clock cycle
else
rd_addr_sm_ns <= IDLE;
end if;
else
rd_addr_sm_ns <= IDLE;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_addr_sm_ns <= IDLE;
--coverage on
end case;
end process RD_ADDR_SM_CMB_PROCESS;
---------------------------------------------------------------------------
-- CR # 582705
-- Ensure combinatorial SM output signals do not get set before
-- the end of the reset (and ARREAADY can be set).
bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2;
brst_cnt_ld_en <= brst_cnt_ld_en_i and axi_aresetn_d2;
ar_active_set <= ar_active_set_i and axi_aresetn_d2;
araddr_pipe_ld <= araddr_pipe_ld_i and axi_aresetn_d2;
RD_ADDR_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
-- Ensure that ar_active does not get asserted (from SM) before
-- the end of reset and the ARREADY flag is set.
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
rd_addr_sm_cs <= IDLE;
else
rd_addr_sm_cs <= rd_addr_sm_ns;
end if;
end if;
end process RD_ADDR_SM_REG_PROCESS;
---------------------------------------------------------------------------
-- Assert araddr_pipe_sel outside of SM logic
-- The BRAM address counter will get loaded with value in ARADDR pipeline
-- when data is stored in the ARADDR pipeline.
araddr_pipe_sel <= '1' when (axi_araddr_full = '1') else '0';
---------------------------------------------------------------------------
-- Register for ar_active
REG_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
ar_active <= '0';
elsif (ar_active_set = '1') then
ar_active <= '1';
-- For code coverage closure, ensure priority encoding in if/else clause
-- to prevent checking ar_active_set in reset clause.
elsif (ar_active_clr = '1') then
ar_active <= '0';
else
ar_active <= ar_active;
end if;
end if;
end process REG_AR_ACT;
end generate GEN_AR_DUAL;
---------------------------------------------------------------------------
--
-- REG_BRST_CNT.
-- Read Burst Counter.
-- No need to decrement burst counter.
-- Able to load with fixed burst length value.
-- Replace usage of proc_common_v4_0_2 library with direct HDL.
--
-- Size of counter = C_BRST_CNT_SIZE
-- Max size of burst transfer = 256 data beats
--
---------------------------------------------------------------------------
REG_BRST_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (brst_cnt_rst = '1') then
brst_cnt <= (others => '0');
-- Load burst counter
elsif (brst_cnt_ld_en = '1') then
brst_cnt <= brst_cnt_ld;
-- Decrement ONLY (no increment functionality)
elsif (brst_cnt_dec = '1') then
brst_cnt (C_BRST_CNT_SIZE-1 downto 0) <=
std_logic_vector (unsigned (brst_cnt (C_BRST_CNT_SIZE-1 downto 0)) - 1);
end if;
end if;
end process REG_BRST_CNT;
---------------------------------------------------------------------------
brst_cnt_rst <= not (S_AXI_AResetn);
-- Determine burst count load value
-- Either load BRAM counter directly from AXI bus or from stored registered value.
-- Use mux signal for ARLEN
BRST_CNT_LD_PROCESS : process (curr_arlen)
variable brst_cnt_ld_int : integer := 0;
begin
brst_cnt_ld_int := to_integer (unsigned (curr_arlen (7 downto 0)));
brst_cnt_ld <= std_logic_vector (to_unsigned (brst_cnt_ld_int, 8));
end process BRST_CNT_LD_PROCESS;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_W_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation supports narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1')
-- Added with single port (13.1 release)
or (end_brst_rd_clr = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- Hold off assertion of brst_cnt_max on narrow burst transfers
-- Must wait until narrow burst count = 0.
if (curr_narrow_burst = '1') then
if (narrow_bram_addr_inc = '1') then
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_W_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_WO_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation does not support narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- When narrow operations are not supported in the core
-- configuration, no check for curr_narrow_burst on assertion.
brst_cnt_max <= '1';
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_WO_NARROW;
---------------------------------------------------------------------------
REG_BRST_MAX_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
brst_cnt_max_d1 <= '0';
else
brst_cnt_max_d1 <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX_D1;
brst_cnt_max_re <= '1' when (brst_cnt_max = '1') and (brst_cnt_max_d1 = '0') else '0';
-- Set flag that end of burst is reached
-- Need to capture this condition as the burst
-- counter may get reloaded for a subsequent read burst
REG_END_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- SM may assert clear flag early (in case of narrow bursts)
-- Wait until the end_brst_rd flag is asserted to clear the flag.
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(end_brst_rd_clr = '1' and end_brst_rd = '1') then
end_brst_rd <= '0';
elsif (brst_cnt_max_re = '1') then
end_brst_rd <= '1';
end if;
end if;
end process REG_END_BURST;
---------------------------------------------------------------------------
-- Create flag that indicates burst counter is reaching ZEROs (max of burst
-- length)
REG_BURST_ZERO: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ZERO)) then
brst_zero <= '0';
elsif (brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE) then
brst_zero <= '1';
else
brst_zero <= brst_zero;
end if;
end if;
end process REG_BURST_ZERO;
---------------------------------------------------------------------------
-- Create additional flag that indicates burst counter is reaching ONEs
-- (near end of burst length). Used to disable back-to-back condition in SM.
REG_BURST_ONE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ONE)) or
((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE)) then
brst_one <= '0';
elsif ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_TWO)) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld = C_BRST_CNT_ONE)) then
brst_one <= '1';
else
brst_one <= brst_one;
end if;
end if;
end process REG_BURST_ONE;
---------------------------------------------------------------------------
-- Register flags for read burst operation
REG_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear axi_rd_burst flags when burst count gets to zeros (unless the burst
-- counter is getting subsequently loaded for the new burst operation)
--
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_zero = '1' and brst_cnt_ld_en = '0') then
axi_rd_burst <= '0';
axi_rd_burst_two <= '0';
elsif (brst_cnt_ld_en = '1') then
if (curr_arlen /= AXI_ARLEN_ONE and curr_arlen /= AXI_ARLEN_TWO) then
axi_rd_burst <= '1';
else
axi_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
axi_rd_burst_two <= '1';
else
axi_rd_burst_two <= '0';
end if;
else
axi_rd_burst <= axi_rd_burst;
axi_rd_burst_two <= axi_rd_burst_two;
end if;
end if;
end process REG_RD_BURST;
---------------------------------------------------------------------------
-- Seeing issue with axi_rd_burst getting cleared too soon
-- on subsquent brst_cnt_ld_en early assertion and pend_rd_op is asserted.
-- Create flag for currently active read burst operation
-- Gets asserted when burst counter is loaded, but does not
-- get cleared until the RD_DATA_SM has completed the read
-- burst operation
REG_ACT_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (act_rd_burst_clr = '1') then
act_rd_burst <= '0';
act_rd_burst_two <= '0';
elsif (act_rd_burst_set = '1') then
-- If not loading the burst counter for a B2B operation
-- Then act_rd_burst follows axi_rd_burst and
-- act_rd_burst_two follows axi_rd_burst_two.
-- Get registered value of axi_* signal.
if (brst_cnt_ld_en = '0') then
act_rd_burst <= axi_rd_burst;
act_rd_burst_two <= axi_rd_burst_two;
else
-- Otherwise, duplicate logic for axi_* signals if burst counter
-- is getting loaded.
-- For improved code coverage here
-- The act_rd_burst_set signal will never get asserted if the burst
-- size is less than two data beats. So, the conditional check
-- for (curr_arlen /= AXI_ARLEN_ONE) is never evaluated. Removed
-- from this if clause.
if (curr_arlen /= AXI_ARLEN_TWO) then
act_rd_burst <= '1';
else
act_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
act_rd_burst_two <= '1';
else
act_rd_burst_two <= '0';
end if;
-- Note: re-code this if/else clause.
end if;
else
act_rd_burst <= act_rd_burst;
act_rd_burst_two <= act_rd_burst_two;
end if;
end if;
end process REG_ACT_RD_BURST;
---------------------------------------------------------------------------
rd_adv_buf <= axi_rvalid_int and AXI_RREADY;
---------------------------------------------------------------------------
-- RD DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
--
-- bram_en_int Registered
-- bram_addr_inc Not Registered
-- brst_cnt_dec Not Registered
-- rddata_mux_sel Registered
-- axi_rdata_en Not Registered
-- axi_rvalid_set Registered
--
--
-- RD_DATA_SM_CMB_PROCESS: Combinational process to determine next state.
-- RD_DATA_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_DATA_SM_CMB_PROCESS: process ( bram_addr_ld_en,
rd_adv_buf,
ar_active,
axi_araddr_full,
rd_b2b_elgible_no_thr_check,
disable_b2b_brst,
curr_arlen,
axi_rd_burst,
axi_rd_burst_two,
act_rd_burst,
act_rd_burst_two,
end_brst_rd,
brst_zero,
brst_one,
axi_b2b_brst,
bram_en_int,
rddata_mux_sel,
end_brst_rd_clr,
no_ar_ack,
pend_rd_op,
axi_rlast_int,
rd_data_sm_cs )
begin
-- assign default values for state machine outputs
rd_data_sm_ns <= rd_data_sm_cs;
bram_en_cmb <= bram_en_int;
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_skid_buf_ld_cmb <= '0';
rd_skid_buf_ld_imm <= '0';
rddata_mux_sel_cmb <= rddata_mux_sel;
-- Change axi_rdata_en generated from SM to be a combinatorial signal
-- Can't afford the latency when throttling on the AXI bus.
axi_rdata_en <= '0';
axi_rvalid_set_cmb <= '0';
end_brst_rd_clr_cmb <= end_brst_rd_clr;
no_ar_ack_cmb <= no_ar_ack;
pend_rd_op_cmb <= pend_rd_op;
act_rd_burst_set <= '0';
act_rd_burst_clr <= '0';
set_last_bram_addr <= '0';
alast_bram_addr <= '0';
axi_b2b_brst_cmb <= axi_b2b_brst;
disable_b2b_brst_cmb <= disable_b2b_brst;
ar_active_clr <= '0';
case rd_data_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Initiate BRAM read when address is available in controller
-- Indicated by load of BRAM address counter
-- Remove use of pend_rd_op signal.
-- Never asserted as we transition back to IDLE
-- Detected in code coverage
if (bram_addr_ld_en = '1') then
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- If currently loading BRAM address counter
-- Must check curr_arlen (mux output from pipe or AXI bus)
-- to determine length of next operation.
-- If ARLEN = 1 data beat, then set last_bram_addr signal
-- Otherwise, increment BRAM address counter.
if (curr_arlen /= AXI_ARLEN_ONE) then
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
else
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
-- Go to single active read address state
rd_data_sm_ns <= SNG_ADDR;
end if;
------------------------- SNG_ADDR State --------------------------
when SNG_ADDR =>
-- Clear flag once pending read is recognized
-- Duplicate logic here in case combinatorial flag was getting
-- set as the SM transitioned into this state.
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Reach this state on first BRAM address & enable assertion
-- For burst operation, create next BRAM address and keep enable
-- asserted
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Reset data mux select between skid buffer and BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Assert RVALID on AXI when 1st data beat available
-- from BRAM
axi_rvalid_set_cmb <= '1';
-- Reach this state when BRAM address counter is loaded
-- Use axi_rd_burst and axi_rd_burst_two to indicate if
-- operation is a single data beat burst.
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Proceed directly to get BRAM read data
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Read burst
else
-- Increment BRAM address counter (2nd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (2nd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= SEC_ADDR;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
-- If new burst is 2 data beats
-- Then disable capability on back-to-back bursts
if (axi_rd_burst_two = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
else
-- Support back-to-back for all other burst lengths
disable_b2b_brst_cmb <= '0';
end if;
end if;
------------------------- SEC_ADDR State --------------------------
when SEC_ADDR =>
-- Reach this state when the 2nd incremented address of the burst
-- is presented to the BRAM.
-- Only reach this state when axi_rd_burst = '1',
-- an active read burst.
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- If we see the next address get loaded into the BRAM counter
-- then set flag for pending operation
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
end if;
-- Check here for burst length of two data transfers
-- If so, then the SM will NOT hit the condition of a full
-- pipeline:
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAm address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
--
-- Full pipeline condition is hit for any read burst
-- length greater than 2 data beats.
if (axi_rd_burst_two = '1') then
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle.
-- This signal will negate in the next state
-- if the data is not accepted on the AXI bus.
-- So that no new data from BRAM is registered into the
-- read channel controller.
rd_skid_buf_ld_cmb <= '1';
else
-- Burst length will hit full pipeline condition
-- Increment BRAM address counter (3rd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (3rd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
end if; -- ARLEN = "0000 0001"
------------------------- FULL_PIPE State -------------------------
when FULL_PIPE =>
-- Reach this state when all three data beats in the burst
-- are active
--
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAM address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- With new pipelining capability BRAM address counter may be
-- loaded in this state. This only occurs on back-to-back
-- bursts (when enabled).
-- No flag set for pending operation.
-- Modify the if clause here to check for back-to-back burst operations
-- If we load the BRAM address in this state for a subsequent burst, then
-- this condition indicates a back-to-back burst and no need to assert
-- the pending read operation flag.
-- Seeing corner case when pend_rd_op needs to be asserted and cleared
-- in this state. If the BRAM address counter is loaded early, but
-- axi_rlast_set is delayed in getting asserted (all while in this state).
-- The signal, curr_narrow_burst can not get cleared.
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
end if;
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat of burst.
-- If not, then go to FULL_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Load read data skid buffer for BRAM capture in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1' and axi_b2b_brst = '0') then
-- Check for elgible pending read operation to support back-to-back performance.
-- If so, load BRAM address counter.
--
-- Replace rd_b2b_elgible signal check to remove path from
-- arlen_pipe through rd_b2b_elgible
-- (with data throttle check)
if (rd_b2b_elgible_no_thr_check = '1') then
rd_data_sm_ns <= FULL_PIPE;
-- Set flag to indicate back-to-back read burst
-- RVALID will not clear in this case and remain asserted
axi_b2b_brst_cmb <= '1';
-- Set flag to update active read burst or
-- read burst of two flag
act_rd_burst_set <= '1';
-- Otherwise, complete current transaction
else
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
end if;
else
-- Remain in this state until burst count reaches zero
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
-- Skid buffer load will remain asserted
-- AXI read data register is asserted
end if;
else
-- Throttling condition detected
rd_data_sm_ns <= FULL_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Negate load of read data skid buffer for BRAM capture
-- in next clock cycle due to detection of Throttle condition
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- If transitioning to throttle state
-- Then next register enable assertion of the AXI read data
-- output register needs to come from the skid buffer
-- Set read data mux select here for SKID_BUFFER data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Detect if at end of burst read as we transition to FULL_THROTTLE
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back to back "non bubble" support when AXI master
-- is throttling on current burst.
-- Seperate signal throttle_last_data will be asserted outside SM.
-- End of burst read, negate BRAM enable
bram_en_cmb <= '0';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Disable B2B capability if throttling detected when
-- burst count is equal to one.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
elsif (brst_one = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Throttle, but not end of burst
else
bram_en_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------- FULL_THROTTLE State ---------------------
when FULL_THROTTLE =>
-- Reach this state when the AXI bus throttles on the AXI data
-- beat read from BRAM (when the read pipeline is fully active)
-- Flag disable_b2b_brst_cmb should be asserted as we transition
-- to this state. Flag is asserted near the end of a read burst
-- to prevent the back-to-back performance pipelining in the BRAM
-- address counter.
-- Detect if at end of burst read
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
bram_en_cmb <= '0';
end if;
-- Set new flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Ensure read data mux is set for skid buffer data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Ensure that AXI read data output register is enabled
axi_rdata_en <= '1';
-- Must reload skid buffer here from BRAM data
-- so if needed can be presented to AXI bus on the following clock cycle
rd_skid_buf_ld_imm <= '1';
-- When detecting end of throttle condition
-- Check first if burst count is complete
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back-to-back performance when AXI master throttles
-- If we reach the end of the burst, proceed to LAST_ADDR state.
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
-- Not end of current burst w/ throttle condition
else
-- Go back to FULL_PIPE
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
end if; -- Burst Max
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_ADDR State -------------------------
when LAST_ADDR =>
-- Reach this state in the clock cycle following the last address
-- presented to the BRAM. Capture the last BRAM data beat in the
-- next clock cycle.
--
-- Data is presented to AXI bus (if no throttling detected) and
-- loaded into the skid buffer.
-- If we reach this state after back to back burst transfers
-- then clear the flag to ensure that RVALID will clear when RLAST
-- is recognized
if (axi_b2b_brst = '1') then
axi_b2b_brst_cmb <= '0';
end if;
-- Clear flag that indicates end of read burst
-- Once we reach this state, we have recognized the burst complete.
--
-- It is getting asserted too early
-- and recognition of the end of the burst is missed when throttling
-- on the last two data beats in the read.
end_brst_rd_clr_cmb <= '1';
-- Set new flag for pending operation if ar_active is asserted (BRAM
-- address has already been loaded) and we are waiting for the current
-- read burst to complete. If those two conditions apply, set this flag.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-backs for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- if (ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Load read data skid buffer for BRAM is asserted on transition
-- into this state. Only gets negated if done with operation
-- as detected in below if clause.
-- Check flag for no subsequent operations
-- Clear that now, with current operation completing
if (no_ar_ack = '1') then
no_ar_ack_cmb <= '0';
end if;
-- Check for single AXI read operations
-- If so, wait for RREADY to be asserted
-- Check for burst and bursts of two as seperate signals.
if (act_rd_burst = '0') and (act_rd_burst_two = '0') then
-- Create rvalid_set to only be asserted for a single clock
-- cycle.
-- Will get set as transitioning to LAST_ADDR on single read operations
-- Only assert RVALID here on single operations
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Data will not yet be acknowledged on AXI
-- in this state.
-- Go to wait for last data beat
rd_data_sm_ns <= LAST_DATA;
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
else
-- Only check throttling on AXI during read data burst operations
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat.
-- If not, then go to LAST_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
-- in next clock cycle
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Burst counter already at zero. Reached this state due to NO
-- pending ARADDR in the read address pipeline. However, check
-- here for any new read addresses.
-- New ARADDR detected and loaded into BRAM address counter
-- Add check here for previously loaded BRAM address
-- ar_active will be asserted (and qualify that with the
-- condition that the read burst is complete, for narrow reads).
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Instead of transitioning to SNG_ADDR
-- go to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
else
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
end if; -- bram_addr_ld_en (New read burst)
else
-- Throttling condition detected
rd_data_sm_ns <= LAST_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
end if; -- rd_adv_buf (RREADY throttle)
end if; -- AXI read burst
------------------------- LAST_THROTTLE State ---------------------
when LAST_THROTTLE =>
-- Reach this state when the AXI bus throttles on the last data
-- beat read from BRAM
-- Data to be sourced from read skid buffer
-- Add check in LAST_THROTTLE as well as LAST_ADDR
-- as we may miss the setting of this flag for a subsequent operation.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-back for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
pend_rd_op_cmb <= '1';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
-- Load read data skid buffer for BRAM capture in next clock cycle
-- of last data read
-- Read Skid buffer already loaded with last data beat from BRAM
-- Does not need to be asserted again in this state
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- Keep RVALID asserted on AXI
-- No need to assert RVALID again
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_DATA State -------------------------
when LAST_DATA =>
-- Reach this state when last BRAM data beat is
-- presented on AXI bus.
-- For a read burst, RLAST is not asserted until SM reaches
-- this state.
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Stay in this state until RREADY is asserted on AXI bus
-- Indicated by assertion of rd_adv_buf
if (rd_adv_buf = '1') then
-- Last data beat acknowledged on AXI bus
-- Check for new read burst or proceed back to IDLE
-- New ARADDR detected and loaded into BRAM address counter
-- Note: this condition may occur when C_SINGLE_PORT_BRAM = 0 or 1
if (bram_addr_ld_en = '1') or (pend_rd_op = '1') then
-- Clear flag once pending read is recognized
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- If we are loading the BRAM, then we have to view the curr_arlen
-- signal to determine if the next operation is a single transfer.
-- Or if the BRAM address counter is already loaded (and we reach
-- this if clause due to pend_rd_op then the axi_* signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (bram_addr_ld_en = '1') then
if (curr_arlen = AXI_ARLEN_ONE) then
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
elsif (pend_rd_op = '1') then
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
end if;
else
-- No pending read address to initiate next read burst.
-- Go to IDLE
rd_data_sm_ns <= IDLE;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
end if;
else
-- Throttling condition detected
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- If new ARADDR detected and loaded into BRAM address counter
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Instead of transitioning to SNG_ADDR
-- to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
-- For singles, block any subsequent loads into BRAM address
-- counter from AR SM
no_ar_ack_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------ LAST_DATA_AR_PEND --------------------
when LAST_DATA_AR_PEND =>
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Reach this state when new BRAM address is loaded into
-- BRAM address counter
-- But waiting for last RREADY/RVALID/RLAST to be asserted
-- Once this occurs, continue with pending AR operation
if (rd_adv_buf = '1') then
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- In this state, the BRAM address counter is already loaded,
-- the axi_rd_burst and axi_rd_burst_two signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
-- Code coverage tests are reporting that reaching this state
-- always when axi_rd_burst = '0' and axi_rd_burst_two = '0',
-- so no bursting operations.
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_data_sm_ns <= IDLE;
--coverage on
end case;
end process RD_DATA_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RD_DATA_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_data_sm_cs <= IDLE;
bram_en_int <= '0';
rd_skid_buf_ld_reg <= '0';
rddata_mux_sel <= C_RDDATA_MUX_BRAM;
axi_rvalid_set <= '0';
end_brst_rd_clr <= '0';
no_ar_ack <= '0';
pend_rd_op <= '0';
axi_b2b_brst <= '0';
disable_b2b_brst <= '0';
else
rd_data_sm_cs <= rd_data_sm_ns;
bram_en_int <= bram_en_cmb;
rd_skid_buf_ld_reg <= rd_skid_buf_ld_cmb;
rddata_mux_sel <= rddata_mux_sel_cmb;
axi_rvalid_set <= axi_rvalid_set_cmb;
end_brst_rd_clr <= end_brst_rd_clr_cmb;
no_ar_ack <= no_ar_ack_cmb;
pend_rd_op <= pend_rd_op_cmb;
axi_b2b_brst <= axi_b2b_brst_cmb;
disable_b2b_brst <= disable_b2b_brst_cmb;
end if;
end if;
end process RD_DATA_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Create seperate registered process for last_bram_addr signal.
-- Only asserted for a single clock cycle
-- Gets set when the burst counter is loaded with 0's (for a single data beat operation)
-- (indicated by set_last_bram_addr from DATA SM)
-- or when the burst counter is decrement and the current value = 1
REG_LAST_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
last_bram_addr <= '0';
-- The signal, set_last_bram_addr, is asserted when the DATA SM transitions to SNG_ADDR
-- on a single data beat burst. Can not use condition of loading burst counter
-- with the value of 0's (as the burst counter may be loaded during prior single operation
-- when waiting on last throttle/data beat, ie. rd_adv_buf not yet asserted).
elsif (set_last_bram_addr = '1') or
-- On burst operations at the last BRAM address presented to BRAM
(brst_cnt_dec = '1' and brst_cnt = C_BRST_CNT_ONE) then
last_bram_addr <= '1';
else
last_bram_addr <= '0';
end if;
end if;
end process REG_LAST_BRAM_ADDR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- *** AXI Read Data Channel Interface ***
--
---------------------------------------------------------------------------
rd_skid_buf_ld <= rd_skid_buf_ld_reg or rd_skid_buf_ld_imm;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_NO_ECC
-- Purpose: Generation of AXI_RDATA output register without ECC
-- logic (C_ECC = 0 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_NO_ECC: if C_ECC = 0 generate
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
---------------------------------------------------------------------------
-- AXI RdData Skid Buffer/Register
-- Sized according to size of AXI/BRAM data width
---------------------------------------------------------------------------
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0);
else
rd_skid_buf <= rd_skid_buf;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
rd_skid_buf;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA
-- Purpose: Generate each bit of AXI_RDATA.
---------------------------------------------------------------------------
GEN_RDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear output after last data beat accepted by requesting AXI master
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Don't clear RDDATA when a back to back burst is occuring on RLAST & RVALID assertion
-- For improved code coverage, can remove the signal, axi_rvalid_int from this if clause.
-- It will always be asserted in this case.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int (i) <= '0';
elsif (axi_rdata_en = '1') then
axi_rdata_int (i) <= axi_rdata_mux (i);
else
axi_rdata_int (i) <= axi_rdata_int (i);
end if;
end if;
end process REG_RDATA;
end generate GEN_RDATA;
-- If C_ECC = 0, direct output assignment to AXI_RDATA
AXI_RDATA <= axi_rdata_int;
end generate GEN_RDATA_NO_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_ECC
-- Purpose: Generation of AXI_RDATA output register when ECC
-- logic is enabled (C_ECC = 1 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_ECC: if C_ECC = 1 generate
subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1);
-- 0:6 for 32-bit ECC
-- 0:7 for 64-bit ECC
type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits;
signal rd_skid_buf_i : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- Remove GEN_RD_BUF that was doing bit reversal.
-- Replace with direct register assignments. Sized according to AXI data width.
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf_i <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf_i (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
rd_skid_buf_i <= rd_skid_buf_i;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
-- axi_rdata_mux holds data + ECC bits.
-- Previous mux on input to checkbit_handler logic.
-- Removed now (mux inserted after checkbit_handler logic before register stage)
--
-- axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
-- rd_skid_buf_i;
-- Remove GEN_RDATA that was doing bit reversal.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int <= (others => '0');
elsif (axi_rdata_en = '1') then
-- Track uncorrected data vector with AXI RDATA output pipeline
-- Mimic mux logic here (from previous post checkbit XOR logic register)
if (rddata_mux_sel = C_RDDATA_MUX_BRAM) then
axi_rdata_int (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
axi_rdata_int <= rd_skid_buf_i;
end if;
else
axi_rdata_int <= axi_rdata_int;
end if;
end if;
end process REG_RDATA;
-- When C_ECC = 1, correct any single bit errors on output read data.
-- Post register stage to improve timing on ECC logic data path.
-- Use registers in AXI Interconnect IP core.
-- Perform bit swapping on output of correct_one_bit
-- module (axi_rdata_int_corr signal).
-- AXI_RDATA (i) <= axi_rdata_int (i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Found in HW debug
-- axi_rdata_int is reversed to be returned on AXI bus.
-- AXI_RDATA (i) <= axi_rdata_int (C_AXI_DATA_WIDTH-1-i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Remove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HAMMING_ECC_CORR: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: CHK_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
constant correct_data_table_32 : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
syndrome_reg <= (others => '0');
syndrome_4_reg <= (others => '0');
syndrome_6_reg <= (others => '0');
-- Align register stage of syndrome with AXI read data pipeline
elsif (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
else
syndrome_reg <= syndrome_reg;
syndrome_4_reg <= syndrome_4_reg;
syndrome_6_reg <= syndrome_6_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on specific syndrome bits after pipeline stage before
-- correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-- Input signal is declared (N:0).
-- Output signal is (N:0).
-- In order to reuse correct_one_bit module,
-- the single data bit correction is done LSB to MSB
-- in generate statement loop.
-----------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_32 (i))
port map (
DIn => axi_rdata_int (31-i), -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (31-i)); -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
end generate GEN_CORR_32;
end generate CHK_ECC_32;
------------------------------------------------------------------------
-- Generate: CHK_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
constant correct_data_table_64 : correct_data_table_type := (
0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001",
4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001",
8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001",
12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001",
16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001",
20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001",
24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101",
28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101",
32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101",
36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101",
40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101",
44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101",
48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101",
52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101",
56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011",
60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011"
);
signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); -- Specific for 64-bit ECC
signal syndrome_7_a : std_logic;
signal syndrome_7_b : std_logic;
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Align register stage of syndrome with AXI read data pipeline
if (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_7_reg <= Syndrome_7;
else
syndrome_reg <= syndrome_reg;
syndrome_7_reg <= syndrome_7_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits after pipeline stage
-- before correct_one_bit_64 module.
PARITY_CHK7_A: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_a ); -- [out std_logic]
PARITY_CHK7_B: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_b ); -- [out std_logic]
-- Do last XOR on Syndrome MSB after pipeline stage before correct_one_bit module
-- PASSES: syndrome_reg_i (7) <= syndrome_reg (7) xor syndrome_7_b_reg;
syndrome_reg_i (7) <= syndrome_7_a xor syndrome_7_b;
syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6);
---------------------------------------------------------------------------
-- Generate: GEN_CORR_64
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_64
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-----------------------------------------------------------------------
CORR_ONE_BIT_64: entity work.correct_one_bit_64
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_64 (i))
port map (
DIn => axi_rdata_int (i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (i));
end generate GEN_CORR_64;
end generate CHK_ECC_64;
end generate GEN_HAMMING_ECC_CORR;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HSIAO_ECC_CORR: if C_ECC_TYPE = 1 generate
type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
begin
-- Reconstruct H-matrix
H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
-- Based on syndrome value, determine bits to flip in BRAM read data.
GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
ecc_rddata_r <= axi_rdata_int;
axi_rdata_int_corr (C_AXI_DATA_WIDTH-1 downto 0) <= -- UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) xor
ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_HSIAO_ECC_CORR;
end generate GEN_RDATA_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RID_SNG
-- Purpose: Generate RID output pipeline when the core is configured
-- in a single port mode.
---------------------------------------------------------------------------
GEN_RID_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_temp <= AXI_ARID;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rid_int <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_int <= AXI_ARID;
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_RID
-- Purpose: Generate RID in dual port mode (with read address pipeline).
---------------------------------------------------------------------------
GEN_RID: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- RID Output Register
--
-- Output RID value either comes from pipelined value or directly wrapped
-- ARID value. Determined by address pipeline usage.
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '0') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp <= axi_arid_pipe;
end if;
-- Add condition to check for temp utilized (temp_full now = '0'), but a
-- pending RID is stored in temp2. Must advance the pipeline.
elsif ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp <= axi_rid_temp2;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
-- Create flag that indicates if axi_rid_temp is full
REG_RID_TEMP_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp_full = '1' and
(axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and
axi_rid_temp2_full = '0') then
axi_rid_temp_full <= '0';
elsif (bram_addr_ld_en = '1') or
((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp_full <= '1';
else
axi_rid_temp_full <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL;
-- Create flag to detect falling edge of axi_rid_temp_full flag
REG_RID_TEMP_FULL_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp_full_d1 <= '0';
else
axi_rid_temp_full_d1 <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL_D1;
axi_rid_temp_full_fe <= '1' when (axi_rid_temp_full = '0' and
axi_rid_temp_full_d1 = '1') else '0';
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP2: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp2 <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp2 <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp2 <= axi_arid_pipe;
end if;
else
axi_rid_temp2 <= axi_rid_temp2;
end if;
end if;
end process REG_RID_TEMP2;
-- Create flag that indicates if axi_rid_temp2 is full
REG_RID_TEMP2_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp2_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp2_full <= '0';
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
axi_rid_temp2_full <= '1';
else
axi_rid_temp2_full <= axi_rid_temp2_full;
end if;
end if;
end process REG_RID_TEMP2_FULL;
---------------------------------------------------------------------------
-- Output RID register is enabeld when RVALID is asserted on the AXI bus
-- Clear RID when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, can remove the signal, axi_rvalid_int from statement.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rid_int <= (others => '0');
-- Add back to back case to advance RID
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP: if C_ECC = 0 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
axi_rresp_int <= RESP_OKAY;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP_ECC
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP_ECC: if C_ECC = 1 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
-- For ECC implementation
-- Check that an uncorrectable error has not occured.
-- If so, then respond with RESP_SLVERR on AXI.
-- Ok to use combinatorial signal here. The Sl_UE_i
-- flag is generated based on the registered syndrome value.
-- if (Sl_UE_i = '1') then
-- axi_rresp_int <= RESP_SLVERR;
-- else
axi_rresp_int <= RESP_OKAY;
-- end if;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP_ECC;
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Clear AXI_RVALID at the end of tranfer when able to clear
-- (axi_rlast_int = '1' and axi_rvalid_int = '1' and AXI_RREADY = '1' and
-- For improved code coverage, remove signal axi_rvalid_int.
(axi_rlast_int = '1' and AXI_RREADY = '1' and
-- Added axi_rvalid_clr_ok to check if during a back-to-back burst
-- and the back-to-back is elgible for streaming performance
axi_rvalid_clr_ok = '1') then
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
-- Create flag that gets set when we load BRAM address early in a B2B scenario
-- This will prevent the RVALID from getting cleared at the end of the current burst
-- Otherwise, the RVALID gets cleared after RLAST/RREADY dual assertion
REG_RVALID_CLR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rvalid_clr_ok <= '0';
-- When the new address loaded into the BRAM counter is for a back-to-back operation
-- Do not clear the RVALID
elsif (rd_b2b_elgible = '1' and bram_addr_ld_en = '1') then
axi_rvalid_clr_ok <= '0';
-- Else when we start a new transaction (that is not back-to-back)
-- Then enable the RVALID to get cleared upon RLAST/RREADY
elsif (bram_addr_ld_en = '1') or
(axi_rvalid_clr_ok = '0' and
(disable_b2b_brst = '1' or disable_b2b_brst_cmb = '1') and
last_bram_addr = '1') or
-- Add check for current SM state
-- If LAST_ADDR state reached, no longer performing back-to-back
-- transfers and keeping data streaming on AXI bus.
(rd_data_sm_cs = LAST_ADDR) then
axi_rvalid_clr_ok <= '1';
else
axi_rvalid_clr_ok <= axi_rvalid_clr_ok;
end if;
end if;
end process REG_RVALID_CLR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- To improve code coverage, remove
-- use of axi_rvalid_int (it will always be asserted with RLAST).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_rlast_set = '0') then
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
---------------------------------------------------------------------------
-- Generate complete flag
do_cmplt_burst_cmb <= '1' when (last_bram_addr = '1' and
axi_rd_burst = '1' and
axi_rd_burst_two = '0') else '0';
-- Register complete flags
REG_CMPLT_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (do_cmplt_burst_clr = '1') then
do_cmplt_burst <= '0';
elsif (do_cmplt_burst_cmb = '1') then
do_cmplt_burst <= '1';
else
do_cmplt_burst <= do_cmplt_burst;
end if;
end if;
end process REG_CMPLT_BURST;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- RLAST State Machine
--
-- Description: SM to generate axi_rlast_set signal.
-- Created based on IR # 555346 to track when RLAST needs
-- to be asserted for back to back transfers
-- Uses the indication when last BRAM address is presented
-- and then counts the handshaking cycles on the AXI bus
-- (RVALID and RREADY both asserted).
-- Uses rd_adv_buf to perform this operation.
--
-- Output: Name Type
-- axi_rlast_set Not Registered
-- do_cmplt_burst_clr Not Registered
--
--
-- RLAST_SM_CMB_PROCESS: Combinational process to determine next state.
-- RLAST_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RLAST_SM_CMB_PROCESS: process (
do_cmplt_burst,
last_bram_addr,
rd_adv_buf,
act_rd_burst,
axi_rd_burst,
act_rd_burst_two,
axi_rd_burst_two,
axi_rlast_int,
rlast_sm_cs )
begin
-- assign default values for state machine outputs
rlast_sm_ns <= rlast_sm_cs;
axi_rlast_set <= '0';
do_cmplt_burst_clr <= '0';
case rlast_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- If last read address is presented to BRAM
if (last_bram_addr = '1') then
-- If the operation is a single read operation
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Go to wait for last data beat
rlast_sm_ns <= W8_LAST_DATA;
-- Else the transaction is a burst
else
-- Throttle condition on 3rd to last data beat
if (rd_adv_buf = '0') then
-- If AXI read burst = 2 (only two data beats to capture)
if (axi_rd_burst_two = '1' or act_rd_burst_two = '1') then
rlast_sm_ns <= W8_THROTTLE_B2;
else
rlast_sm_ns <= W8_THROTTLE;
end if;
-- No throttle on 3rd to last data beat
else
-- Only back-to-back support when burst size is greater
-- than two data beats. We will never toggle on a burst > 2
-- when last_bram_addr is asserted (as this is no toggle
-- condition)
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
do_cmplt_burst_clr <= '1';
end if;
end if;
end if;
------------------------- W8_THROTTLE State -----------------------
when W8_THROTTLE =>
if (rd_adv_buf = '1') then
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
-- If do_cmplt_burst flag is set, then clear it
if (do_cmplt_burst = '1') then
do_cmplt_burst_clr <= '1';
end if;
end if;
---------------------- W8_2ND_LAST_DATA State ---------------------
when W8_2ND_LAST_DATA =>
if (rd_adv_buf = '1') then
-- Assert RLAST on AXI
axi_rlast_set <= '1';
rlast_sm_ns <= W8_LAST_DATA;
end if;
------------------------- W8_LAST_DATA State ----------------------
when W8_LAST_DATA =>
-- If pending single to complete, keep RLAST asserted
-- Added to only assert axi_rlast_set for a single clock cycle
-- when we enter this state and are here waiting for the
-- throttle on the AXI bus.
if (axi_rlast_int = '1') then
axi_rlast_set <= '0';
else
axi_rlast_set <= '1';
end if;
-- Wait for last data beat to transition back to IDLE
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
end if;
-------------------------- W8_THROTTLE_B2 ------------------------
when W8_THROTTLE_B2 =>
-- Wait for last data beat to transition back to IDLE
-- and set RLAST
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
axi_rlast_set <= '1';
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rlast_sm_ns <= IDLE;
--coverage on
end case;
end process RLAST_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RLAST_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rlast_sm_cs <= IDLE;
else
rlast_sm_cs <= rlast_sm_ns;
end if;
end if;
end process RLAST_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal CE_Q : std_logic := '0';
signal Sl_CE_i : std_logic := '0';
signal bram_en_int_d1 : std_logic := '0';
signal bram_en_int_d2 : std_logic := '0';
begin
-- Generate signal to advance BRAM read address pipeline to
-- capture address for ECC error conditions (in lite_ecc_reg module).
-- BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or
-- ((bram_en_int or bram_en_int_reg) and not (axi_rd_burst) and not (axi_rd_burst_two));
BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or rd_adv_buf or
((bram_en_int or bram_en_int_d1 or bram_en_int_d2) and not (axi_rd_burst) and not (axi_rd_burst_two));
-- Enable 2nd & 3rd pipeline stage for BRAM address storage with single read transfers.
BRAM_EN_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
bram_en_int_d1 <= bram_en_int;
bram_en_int_d2 <= bram_en_int_d1;
end if;
end process BRAM_EN_REG;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
-- Add extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 32-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
signal bram_din_a_rev : std_logic_vector(31 downto 0) := (others => '0'); -- Specific to BRAM data width
signal bram_din_ecc_a_rev : std_logic_vector(6 downto 0) := (others => '0'); -- Specific to BRAM data width
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
-- process (bram_din_a_i) begin
-- for k in 0 to 31 loop
-- bram_din_a_rev(k) <= bram_din_a_i(39-k);
-- end loop;
-- for k in 0 to 6 loop
-- bram_din_ecc_a_rev(0) <= bram_din_a_i(6-k);
-- end loop;
-- end process;
CHK_HANDLER_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- In 32-bit BRAM use case: DataIn (8:39)
-- CheckIn (1:7)
DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)]
--DataIn => bram_din_a_rev, -- [in std_logic_vector(0 to 31)]
--CheckIn => bram_din_ecc_a_rev, -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [out std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_32;
------------------------------------------------------------------------
-- Generate: GEN_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
-- No extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 64-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_64
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => false, -- [boolean]
C_REG => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
-- In 64-bit BRAM use case: DataIn (8:71)
-- CheckIn (0:7)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)]
CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 7)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => Syndrome_7,
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_64 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_64;
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal syndrome_ns : std_logic_vector (ECC_WIDTH - 1 downto 0) := (others => '0');
begin
-- Generate ECC check bits and syndrome values based on
-- BRAM read data.
-- Generate appropriate single or double bit error flags.
-- Instantiate ecc_gen_hsiao module, generated from MIG
I_ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( -- bram_din_a_i (0 to CODE_WIDTH-1)
BRAM_RdData (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome.
-- Same as Hamming ECC code. Syndrome value is registered.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
end if;
end process REG_SYNDROME;
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not(REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1') then -- Capture error flags
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- The signal, axi_rdata_en loads the syndrome_reg.
-- Use the AXI RVALID/READY signals to capture state of UE and CE.
-- Since flag generation uses the registered syndrome value.
-- ECC register block gets registered UE or CE conditions to update
-- ECC registers/interrupt/flag outputs.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
-- CE_Failing_We <= Sl_CE_i and Enable_ECC and axi_rvalid_set;
CE_Failing_We <= CE_Q;
---------------------------------------------------------------------------
-- Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData (Port A) (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
--
-- Port A or Port B sourcing done at full_axi module level
---------------------------------------------------------------------------
-- Original design with mux (BRAM vs. Skid Buffer) on input side of checkbit_handler logic.
-- Move mux to enable on AXI RDATA register.
bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_AXI_DATA_WIDTH-1);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Drive default output signals when ECC is diabled.
---------------------------------------------------------------------------
GEN_NO_ECC: if C_ECC = 0 generate
begin
BRAM_Addr_En <= '0';
CE_Failing_We <= '0';
Sl_CE <= '0';
Sl_UE <= '0';
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
--
-- *** BRAM Interface Signals ***
--
---------------------------------------------------------------------------
BRAM_En <= bram_en_int;
---------------------------------------------------------------------------
-- BRAM Address Generate
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
--
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
--
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
---------------------------------------------------------------------------
end architecture implementation;
| gpl-3.0 | ba146511d94fdf66c0f056afdda59f6f | 0.432192 | 4.760414 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1207/alphablender.vhdl | 1 | 2,514 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity AlphaBlender is
generic (
PixelWidth : natural := 8;
AlphaWidth : natural := 8
);
port(
clk : in std_logic;
alpha : in std_logic_vector(AlphaWidth-1 downto 0);
pixel1 : in std_logic_vector(PixelWidth-1 downto 0);
pixel2 : in std_logic_vector(PixelWidth-1 downto 0);
pixelout : out std_logic_vector(PixelWidth-1 downto 0)
);
end AlphaBlender;
architecture behavioral of AlphaBlender is
constant DspDataWidth : natural := 18;
constant DspCascadeWidth : natural := 48;
constant AlphaPadding : std_logic_vector(AlphaWidth-1 downto 0) := (others => '0');
signal ain : std_logic_vector(DspDataWidth-1 downto 0);
signal ain_r1 : std_logic_vector(DspDataWidth-1 downto 0) := (others => '0');
signal ain_r2 : std_logic_vector(DspDataWidth-1 downto 0) := (others => '0');
signal bin : std_logic_vector(DspDataWidth-1 downto 0);
signal cin : std_logic_vector(DspCascadeWidth-1 downto 0);
signal din : std_logic_vector(DspDataWidth-1 downto 0);
signal bin_r : std_logic_vector(DspDataWidth-1 downto 0) := (others => '0');
signal din_r : std_logic_vector(DspDataWidth-1 downto 0) := (others => '0');
signal cin_r1 : std_logic_vector(DspCascadeWidth-1 downto 0) := (others => '0');
signal cin_r2 : std_logic_vector(DspCascadeWidth-1 downto 0) := (others => '0');
signal cin_r3 : std_logic_vector(DspCascadeWidth-1 downto 0) := (others => '0');
signal preadd_r : std_logic_vector(DspDataWidth-1 downto 0) := (others => '0');
signal mult_r : std_logic_vector(2*DspDataWidth-1 downto 0) := (others => '0');
signal sum_r : std_logic_vector(DspCascadeWidth-1 downto 0) := (others => '0');
begin
bin <= ext(pixel1 & AlphaPadding, DspDataWidth);
cin <= ext(pixel1 & AlphaPadding & AlphaPadding, DspCascadeWidth);
din <= ext(pixel2 & AlphaPadding, DspDataWidth);
ain <= ext(alpha, DspDataWidth);
addmultadd : process (clk)
begin
if rising_edge(clk) then
ain_r1 <= ain;
ain_r2 <= ain_r1;
bin_r <= bin;
din_r <= din;
cin_r1 <= cin;
cin_r2 <= cin_r1;
cin_r3 <= cin_r2;
preadd_r <= din_r - bin_r;
mult_r <= preadd_r * ain_r2;
sum_r <= mult_r + cin_r3;
end if;
end process addmultadd;
pixelout <= sum_r(2*AlphaWidth+PixelWidth-1 downto 2*AlphaWidth);
end behavioral;
| gpl-2.0 | d78c72cac155c8f1c92432a7a07939b8 | 0.633254 | 3.13076 | false | false | false | false |
nickg/nvc | test/regress/conv6.vhd | 1 | 1,926 | package pack is
type int_vector is array (natural range <>) of natural;
function spread_ints (x : integer) return int_vector;
end package;
package body pack is
function spread_ints (x : integer) return int_vector is
variable r : int_vector(1 to 5);
begin
for i in 1 to 5 loop
r(i) := x;
end loop;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( o1 : out int_vector(1 to 5);
i1 : in integer;
i2 : in int_vector(1 to 5) );
end entity;
architecture test of sub is
begin
p1a: process is
begin
assert i1 = 0;
assert i2 = (1 to 5 => 0);
o1(1 to 3) <= (1, 2, 3);
wait for 1 ns;
assert i1 = 150;
assert i2 = (1 to 5 => 42);
o1(1) <= 10;
wait;
end process;
p1b: process is
begin
o1(4 to 5) <= (4, 5);
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity conv6 is
end entity;
use work.pack.all;
architecture test of conv6 is
signal x : integer;
signal y : int_vector(1 to 5);
signal q : natural;
function sum_ints(v : in int_vector) return integer is
variable result : integer := 0;
begin
for i in v'range loop
result := result + v(i);
end loop;
return result;
end function;
begin
uut: entity work.sub
port map ( sum_ints(o1) => x,
i1 => sum_ints(y),
i2 => spread_ints(q) );
p2: process is
begin
assert x = 0;
y <= (10, 20, 30, 40, 50);
q <= 42;
wait for 1 ns;
assert x = 15;
wait for 1 ns;
assert x = 24;
wait;
end process;
end architecture;
| gpl-3.0 | ae6677b3e952ae490b0389d5eac208a5 | 0.477674 | 3.739806 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_doHist_0_1/sim/design_1_doHist_0_1.vhd | 2 | 12,155 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls:doHist:1.0
-- IP Revision: 1606202043
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doHist_0_1 IS
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_doHist_0_1;
ARCHITECTURE design_1_doHist_0_1_arch OF design_1_doHist_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHist_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT doHist IS
GENERIC (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT doHist;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF histo_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF histo_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF histo_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF histo_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF histo_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF histo_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF histo_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA DOUT";
BEGIN
U0 : doHist
GENERIC MAP (
C_S_AXI_CTRL_BUS_ADDR_WIDTH => 4,
C_S_AXI_CTRL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CTRL_BUS_AWADDR => s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WDATA => s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_WVALID => s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_BRESP => s_axi_CTRL_BUS_BRESP,
s_axi_CTRL_BUS_BVALID => s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_ARADDR => s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RDATA => s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_RVALID => s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => s_axi_CTRL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
histo_Clk_A => histo_Clk_A,
histo_Rst_A => histo_Rst_A,
histo_EN_A => histo_EN_A,
histo_WEN_A => histo_WEN_A,
histo_Addr_A => histo_Addr_A,
histo_Din_A => histo_Din_A,
histo_Dout_A => histo_Dout_A
);
END design_1_doHist_0_1_arch;
| gpl-3.0 | 75c7afd2b033c0b01c1ba0a3b85d12c6 | 0.704072 | 3.232713 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1349.vhd | 4 | 6,500 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1349.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p10n01i01349ent IS
END c08s04b01x00p10n01i01349ent;
ARCHITECTURE c08s04b01x00p10n01i01349arch OF c08s04b01x00p10n01i01349ent IS
-- Local signals.
signal S : BIT := '0';
BEGIN
TESTING: PROCESS
-- local variables.
variable S_INITIAL : BIT;
variable ShouldBeTime : TIME;
variable k : integer := 0;
BEGIN
-- 0. Keep around the initial value of S.
S_INITIAL := S;
-- 1. When no preemption necessary, verify the results. INERTIAL SAME AS TRANSPORT.
S <= (not S) after 10 ns, (S) after 20 ns;
-- a. Wait for first transaction.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Wait for second transaction.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- 2. Preempt a transaction which is to occur at the same time as second one.
-- INERTIAL SAME AS TRANSPORT.
S_INITIAL := S;
S <= (S) after 10 ns;
S <= (not S) after 10 ns; -- Should preempt first transaction.
-- a. Verify that the second transaction comes as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Verify that the first transaction has been preempted.
ShouldBeTime := NOW + 10 ns;
wait on S for 10 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 3. Preempt a transaction which is to occur at a later time than second one.
-- INERTIAL SAME AS TRANSPORT.
S_INITIAL := S;
S <= (S) after 15 ns;
S <= (not S) after 10 ns; -- Should preempt first transaction.
-- a. Verify that the second transaction comes as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Verify that the first transaction has been preempted.
ShouldBeTime := NOW + 10 ns;
wait on S for 10 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 4. Preempt multiple transactions. INERTIAL SAME AS TRANSPORT.
S_INITIAL := S;
S <= (S) after 15 ns, (not S) after 30 ns;
S <= (not S) after 10 ns, (S) after 20 ns;
-- a. Verify that the second transactions come as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- b. Verify that the first transactions have been preempted.
ShouldBeTime := NOW + 40 ns;
wait on S for 40 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 5. Preempt transactions which occur before the second inertial assignment.
S_INITIAL := S;
S <= (S) after 5 ns;
S <= (not S) after 10 ns, (S) after 20 ns;
-- a. Verify that the second transactions come as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now and S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- b. Verify that the first transactions have been preempted.
ShouldBeTime := NOW + 40 ns;
wait on S for 40 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 6. Don't preempt transactions which occur before the second inertial assignment.
S_INITIAL := S;
S <= (not S) after 5 ns;
S <= (not S) after 10 ns, (S) after 20 ns;
-- a. Verify that the first transaction was NOT preempted.
ShouldBeTime := NOW + 5 ns;
wait on S;
if (ShouldBeTime /= now and S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
ShouldBeTime := NOW + 15 ns;
wait on S;
if (ShouldBeTime /= now and S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- b. Verify that there are no more transactions.
ShouldBeTime := NOW + 40 ns;
wait on S for 40 ns;
if (ShouldBeTime /= now ) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert NOT( k=0 )
report "***PASSED TEST: c08s04b01x00p10n01i01349"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s04b01x00p10n01i01349 - Interial signal assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p10n01i01349arch;
| gpl-2.0 | 306731e2f5408f04b708af82d4432081 | 0.604308 | 3.774681 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue265/ex1_top.vhdl | 1 | 627 | library IEEE;
use IEEE.std_logic_1164.all;
entity ex1_top is
end entity;
architecture a of ex1_top is
signal A : boolean;
function conv_inst_top(p : std_logic) return boolean is
begin
return (p = '0'); -- inverter
end function;
function conv_top_inst(p : boolean) return std_logic is
begin
if (p = FALSE) then
return '0'; -- identity
elsif (p = TRUE) then
return '1'; -- identity
else
return 'X'; -- error
end if;
end function;
begin
A <= TRUE;
inst : entity work.ex1_entity
port map (
conv_inst_top(X) => conv_top_inst(A)
);
end architecture;
| gpl-2.0 | 71e489555162cc378ad244454d1ff954 | 0.610845 | 3.31746 | false | false | false | false |
nickg/nvc | test/bounds/case.vhd | 1 | 3,474 | entity bounds_case is
end entity;
architecture test of bounds_case is
begin
process is
type letter is (A, B, C);
subtype ab is letter range B to letter'right;
variable l : letter;
variable m : ab;
begin
case l is -- Choice C not covered
when a =>
null;
when b =>
null;
end case;
case m is -- Choice B not covered
when c =>
null;
end case;
wait;
end process;
process is
variable x : integer;
variable y : natural;
begin
case x is -- Missing range
when 0 to 9 =>
null;
when 20 =>
null;
end case;
case x is -- Missing range
when 1 | 2 | 3 =>
null;
end case;
case x is -- OK
when others =>
null;
end case;
case x is -- Missing integer'right
when integer'left to integer'right - 1 =>
null;
end case;
case x is
when 1 to 100 =>
null;
when 50 => -- Duplicate
null;
when 60 to 64 => -- Duplicate
null;
when others =>
null;
end case;
case y is
when -1 => -- Out of range
null;
end case;
end process;
process is
variable x : bit_vector(1 to 3);
variable y : bit_vector(0 to 0);
subtype small is character range 'a' to 'k';
type char_vector is array (integer range <>) of character;
type small_vector is array (integer range <>) of small;
variable p : char_vector(1 to 2);
variable q : small_vector(1 to 2);
begin
case y is
when "0" =>
null;
when "1" =>
null;
end case; -- OK
case x is
when "000" | "001" =>
null;
end case; -- Missing 6 values
case x is
when ('0', '1') => -- Too few values
null;
when ('1', '0', '1', '1') => -- Too many values
null;
when "10" => -- Too few values
null;
when "1111" => -- Too many values
null;
when others =>
null;
end case;
case p is
when ('0', '1') =>
null;
when ('1', '1') =>
null;
end case; -- Missing lots of values
case q is
when ('0', '1') =>
null;
when ('1', '1') =>
null;
end case; -- Missing 98 values
end process;
process is
type my_int is range 10 downto 1;
variable x : my_int;
begin
case x is
when 10 downto 4 => null;
end case; -- Error
case x is
when 11 downto 3 => null; -- Error
when 2 downto 1 => null;
end case;
end process;
end architecture;
| gpl-3.0 | 862c05bbcc22d87c777cc652c59fffd6 | 0.376799 | 5.012987 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1042/ent.vhdl | 1 | 452 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
generic (
VAL : real := 1.5
);
port (
lt : out std_logic;
lte : out std_logic;
eq : out std_logic;
gte : out std_logic;
gt : out std_logic
);
end;
architecture a of ent is
begin
lt <= '1' when VAL < 1.5 else '0';
lte <= '1' when VAL <= 1.5 else '0';
eq <= '1' when VAL = 1.5 else '0';
gte <= '1' when VAL >= 1.5 else '0';
gt <= '1' when VAL > 1.5 else '0';
end;
| gpl-2.0 | ec07da6ba00cdb349a224378160960b4 | 0.550885 | 2.294416 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3119.vhd | 4 | 2,902 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3119.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p05n01i03119ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p05n01i03119ent_a;
ARCHITECTURE c05s02b01x01p05n01i03119arch_a OF c05s02b01x01p05n01i03119ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p05n01i03119arch_a;
configuration c05s02b01x01p05n01i03119cfg_a of c05s02b01x01p05n01i03119ent_a is
for c05s02b01x01p05n01i03119arch_a
end for;
end c05s02b01x01p05n01i03119cfg_a;
--
ENTITY c05s02b01x01p05n01i03119ent IS
END c05s02b01x01p05n01i03119ent;
ARCHITECTURE c05s02b01x01p05n01i03119arch OF c05s02b01x01p05n01i03119ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p05n01i03119"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p05n01i03119 - Use a configuration that is fully bound test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p05n01i03119arch;
configuration c05s02b01x01p05n01i03119cfg of c05s02b01x01p05n01i03119ent is
for c05s02b01x01p05n01i03119arch
for all : virtual use configuration work.c05s02b01x01p05n01i03119cfg_a;
end for;
end for;
end c05s02b01x01p05n01i03119cfg;
| gpl-2.0 | c1866d196355ea89edf88ba3e43e51f7 | 0.66368 | 3.100427 | false | true | false | false |
tgingold/ghdl | testsuite/gna/ticket65/bug.vhdl | 3 | 529 | entity ent is
end entity;
architecture a of ent is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value2); -- CONSTRAINT_ERROR
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Works
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
| gpl-2.0 | f272e4f411a7193c6c8f59c52397197d | 0.655955 | 3.30625 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue963/ent.vhdl | 1 | 501 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : in std_logic;
set : in std_logic;
reset : in std_logic;
q : out std_logic
);
end;
architecture a of ent is
signal s : std_logic;
begin
process(clk, set, reset)
begin
if set = '1' then
s <= '1';
elsif reset = '1' then
s <= '0';
elsif rising_edge(clk) then
s <= not s;
end if;
end process;
q <= s;
end;
| gpl-2.0 | bae598dcc3a9528f15736d5b05a0075d | 0.48503 | 3.408163 | false | false | false | false |
nickg/nvc | test/regress/file7.vhd | 1 | 1,029 | --
-- Reduced from VESTs cases tc640 and tc641
--
entity file7 is
end entity;
architecture test of file7 is
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array (0 to size) of word;
type primary_memory_file is file of primary_memory;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
begin
writer: process
file filein : primary_memory_file open write_mode is "iofile.42";
begin
for i in 1 to 10 loop
write(filein, C44);
end loop;
file_close(filein);
wait;
end process;
reader: process
file filein : primary_memory_file;
variable v : primary_memory;
begin
wait for 1 ns;
file_open(filein, "iofile.42");
for i in 1 to 10 loop
assert not endfile(filein);
read(filein,v);
assert v = C44;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 | 9ec8dc5299acf0be6c508862b4236268 | 0.576288 | 3.927481 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/PoC/src/common/utils.vhdl | 1 | 36,789 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
-- Paul Genssler
--
-- Package: Common functions and types
--
-- Description:
-- -------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
package utils is
-- Environment
-- ==========================================================================
-- Distinguishes simulation from synthesis
constant SIMULATION : boolean; -- deferred constant declaration
-- Type declarations
-- ==========================================================================
--+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++
type T_BOOLVEC is array(natural range <>) of boolean;
type T_INTVEC is array(natural range <>) of integer;
type T_NATVEC is array(natural range <>) of natural;
type T_POSVEC is array(natural range <>) of positive;
type T_REALVEC is array(natural range <>) of REAL;
--+ Integer subranges sometimes useful for speeding up simulation ++++++++++
subtype T_INT_8 is integer range -128 to 127;
subtype T_INT_16 is integer range -32768 to 32767;
subtype T_UINT_8 is integer range 0 to 255;
subtype T_UINT_16 is integer range 0 to 65535;
--+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Intellectual Property (IP) type
type T_IPSTYLE is (IPSTYLE_UNKNOWN, IPSTYLE_HARD, IPSTYLE_SOFT);
-- Bit Order
type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST);
-- Byte Order (Endian)
type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN);
-- rounding style
type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN);
-- define a new unrelated type T_BCD for arithmetic
-- QUESTION: extract to an own BCD package?
-- => overloaded operators for +/-/=/... and conversion functions
type T_BCD is array(3 downto 0) of std_logic;
type T_BCD_VECTOR is array(natural range <>) of T_BCD;
constant C_BCD_MINUS : T_BCD := "1010";
constant C_BCD_OFF : T_BCD := "1011";
-- Function declarations
-- ==========================================================================
--+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(a / b)
function div_ceil(a : natural; b : positive) return natural;
--+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- is input a power of 2?
function is_pow2(int : natural) return boolean;
-- round to next power of 2
function ceil_pow2(int : natural) return positive;
-- round to previous power of 2
function floor_pow2(int : natural) return natural;
--+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(ld(arg))
function log2ceil(arg : positive) return natural;
-- Calculates: max(1, ceil(ld(arg)))
function log2ceilnz(arg : positive) return positive;
-- Calculates: ceil(lg(arg))
function log10ceil(arg : positive) return natural;
-- Calculates: max(1, ceil(lg(arg)))
function log10ceilnz(arg : positive) return positive;
--+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++
function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean;
function ite(cond : boolean; value1 : integer; value2 : integer) return integer;
function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL;
function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic;
function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector;
function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector;
function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned;
function ite(cond : boolean; value1 : character; value2 : character) return character;
function ite(cond : boolean; value1 : string; value2 : string) return string;
-- conditional increment / decrement
function inc_if(cond : boolean; value : integer; increment : integer := 1) return integer;
function dec_if(cond : boolean; value : integer; decrement : integer := 1) return integer;
--+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers
alias rmin is IEEE.math_real.realmin[real, real return real];
-- function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals
function imin(vec : T_INTVEC) return integer; -- Calculates: min(vec) for a integer vector
function imin(vec : T_NATVEC) return natural; -- Calculates: min(vec) for a natural vector
function imin(vec : T_POSVEC) return positive; -- Calculates: min(vec) for a positive vector
function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector
function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers
alias rmax is IEEE.math_real.realmax[real, real return real];
-- function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals
function imax(vec : T_INTVEC) return integer; -- Calculates: max(vec) for a integer vector
function imax(vec : T_NATVEC) return natural; -- Calculates: max(vec) for a natural vector
function imax(vec : T_POSVEC) return positive; -- Calculates: max(vec) for a positive vector
function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector
function isum(vec : T_NATVEC) return natural; -- Calculates: sum(vec) for a natural vector
function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector
function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector
function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector
--+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- to integer: to_int
function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer;
function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer;
-- to std_logic: to_sl
function to_sl(Value : boolean) return std_logic;
function to_sl(Value : character) return std_logic;
-- to std_logic_vector: to_slv
function to_slv(Value : natural; Size : positive) return std_logic_vector; -- short for std_logic_vector(to_unsigned(Value, Size))
function to_BCD(Digit : integer) return T_BCD;
function to_BCD(Digit : character) return T_BCD;
function to_BCD(Digit : unsigned) return T_BCD;
function to_BCD(Digit : std_logic_vector) return T_BCD;
function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR;
function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR;
-- TODO: comment
function bound(index : integer; lowerBound : integer; upperBound : integer) return integer;
function to_index(slv : unsigned; max : natural := 0) return integer;
function to_index(slv : std_logic_vector; max : natural := 0) return integer;
-- is_*
function is_sl(c : character) return boolean;
--+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++
-- Aggregate functions
function slv_or (vec : std_logic_vector) return std_logic;
function slv_nor (vec : std_logic_vector) return std_logic;
function slv_and (vec : std_logic_vector) return std_logic;
function slv_nand(vec : std_logic_vector) return std_logic;
function slv_xor (vec : std_logic_vector) return std_logic;
-- NO slv_xnor! This operation would not be well-defined as
-- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd.
-- Reverses the elements of the passed Vector.
--
-- @synthesis supported
--
function reverse(vec : std_logic_vector) return std_logic_vector;
function reverse(vec : bit_vector) return bit_vector;
function reverse(vec : unsigned) return unsigned;
-- scale a value into a range [Minimum, Maximum]
function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer;
function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer;
function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL;
-- Resizes the vector to the specified length. The adjustment is make on
-- on the 'high end of the vector. The 'low index remains as in the argument.
-- If the result vector is larger, the extension uses the provided fill value
-- (default: '0').
-- Use the resize functions of the numeric_std package for value-preserving
-- resizes of the signed and unsigned data types.
--
-- @synthesis supported
--
function resize(vec : bit_vector; length : natural; fill : bit := '0')
return bit_vector;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0')
return std_logic_vector;
-- Shift the index range of a vector by the specified offset.
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector;
-- Shift the index range of a vector making vec'low = 0.
function movez(vec : std_logic_vector) return std_logic_vector;
function ascend(vec : std_logic_vector) return std_logic_vector;
function descend(vec : std_logic_vector) return std_logic_vector;
-- Least-Significant Set Bit (lssb):
-- Computes a vector of the same length as the argument with
-- at most one bit set at the rightmost '1' found in arg.
--
-- @synthesis supported
--
function lssb(arg : std_logic_vector) return std_logic_vector;
function lssb(arg : bit_vector) return bit_vector;
-- Returns the index of the least-significant set bit.
--
-- @synthesis supported
--
function lssb_idx(arg : std_logic_vector) return integer;
function lssb_idx(arg : bit_vector) return integer;
-- Most-Significant Set Bit (mssb): computes a vector of the same length
-- with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector;
function mssb(arg : bit_vector) return bit_vector;
function mssb_idx(arg : std_logic_vector) return integer;
function mssb_idx(arg : bit_vector) return integer;
-- Swap sub vectors in vector (endian reversal)
function swap(slv : std_logic_vector; Size : positive) return std_logic_vector;
-- Swap the bits in a chunk
function bit_swap(slv : std_logic_vector; Chunksize : positive) return std_logic_vector;
-- generate bit masks
function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector;
function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector;
function genmask_alternate(len : positive; lsb : std_logic := '0') return std_logic_vector;
--+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- One-Hot-Code to Binary-Code.
-- If a non-negative value empty_val is specified, its unsigned
-- representation will be returned upon an all-zero input. As a consequence
-- of specifying this value, no simulation warnings will be issued upon empty
-- inputs. Alleged 1-hot-encoded inputs with more than one bit asserted
-- will always raise a simulation warning.
function onehot2bin(onehot : std_logic_vector; empty_val : integer := -1) return unsigned;
-- Converts Gray-Code into Binary-Code.
--
-- @synthesis supported
--
function gray2bin (gray_val : std_logic_vector) return std_logic_vector;
-- Binary-Code to One-Hot-Code
function bin2onehot(value : std_logic_vector) return std_logic_vector;
-- Binary-Code to Gray-Code
function bin2gray(value : std_logic_vector) return std_logic_vector;
end package;
package body utils is
-- Environment
-- ==========================================================================
function is_simulation return boolean is
variable ret : boolean;
begin
ret := false;
-- WORKAROUND: for Xilinx ISE
-- Version: all versions with enabled 'use_new_parser' option
-- Issue: Is_X('X') does not evaluate to FALSE in synthesis
-- Solution: Use '--synthesis translate_on/off' pragmas
--synthesis translate_off
if Is_X('X') then ret := true; end if;
--synthesis translate_on
return ret;
end function;
-- deferred constant assignment
constant SIMULATION : boolean := is_simulation;
-- Divisions: div_*
-- ===========================================================================
-- integer division; always round-up
function div_ceil(a : natural; b : positive) return natural is -- calculates: ceil(a / b)
begin
return (a + (b - 1)) / b;
end function;
-- Power functions: *_pow2
-- ==========================================================================
-- return TRUE, if input is a power of 2
function is_pow2(int : natural) return boolean is
begin
return ceil_pow2(int) = int;
end function;
-- round to next power of 2
function ceil_pow2(int : natural) return positive is
begin
return 2 ** log2ceil(int);
end function;
-- round to previous power of 2
function floor_pow2(int : natural) return natural is
variable temp : unsigned(30 downto 0);
begin
temp := to_unsigned(int, 31);
for i in temp'range loop
if (temp(i) = '1') then
return 2 ** i;
end if;
end loop;
return 0;
end function;
-- Logarithms: log*ceil*
-- ==========================================================================
-- return log2; always rounded up
function log2ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
-- return log2; always rounded up; the return value is >= 1
function log2ceilnz(arg : positive) return positive is
begin
return imax(1, log2ceil(arg));
end function;
-- return log10; always rounded up
function log10ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 10;
log := log + 1;
end loop;
return log;
end function;
-- return log2; always rounded up; the return value is >= 1
function log10ceilnz(arg : positive) return positive is
begin
return imax(1, log10ceil(arg));
end function;
-- if-then-else (ite)
-- ==========================================================================
function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : integer; value2 : integer) return integer is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : character; value2 : character) return character is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : string; value2 : string) return string is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- conditional increment / decrement
-- ===========================================================================
-- return the by increment incremented Value if cond is true else passthrough Value
function inc_if(cond : boolean; Value : integer; increment : integer := 1) return integer is
begin
if cond then
return Value + increment;
else
return Value;
end if;
end function;
-- return the by decrement decremented Value if cond is true else passthrough Value
function dec_if(cond : boolean; Value : integer; decrement : integer := 1) return integer is
begin
if cond then
return Value - decrement;
else
return Value;
end if;
end function;
-- *min / *max / *sum
-- ===========================================================================
function imin(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 < arg2 then return arg1; end if;
return arg2;
end function;
-- function rmin(arg1 : real; arg2 : real) return real is
-- begin
-- if arg1 < arg2 then return arg1; end if;
-- return arg2;
-- end function;
function imin(vec : T_INTVEC) return integer is
variable Result : integer;
begin
Result := integer'high;
for i in vec'range loop
if vec(i) < Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imin(vec : T_NATVEC) return natural is
variable Result : natural;
begin
Result := natural'high;
for i in vec'range loop
if vec(i) < Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imin(vec : T_POSVEC) return positive is
variable Result : positive;
begin
Result := positive'high;
for i in vec'range loop
if vec(i) < Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function rmin(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'high;
for i in vec'range loop
if vec(i) < Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imax(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 > arg2 then return arg1; end if;
return arg2;
end function;
-- function rmax(arg1 : real; arg2 : real) return real is
-- begin
-- if arg1 > arg2 then return arg1; end if;
-- return arg2;
-- end function;
function imax(vec : T_INTVEC) return integer is
variable Result : integer;
begin
Result := integer'low;
for i in vec'range loop
if vec(i) > Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imax(vec : T_NATVEC) return natural is
variable Result : natural;
begin
Result := natural'low;
for i in vec'range loop
if vec(i) > Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imax(vec : T_POSVEC) return positive is
variable Result : positive;
begin
Result := positive'low;
for i in vec'range loop
if vec(i) > Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function rmax(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'low;
for i in vec'range loop
if vec(i) > Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function isum(vec : T_INTVEC) return integer is
variable Result : integer;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
function isum(vec : T_NATVEC) return natural is
variable Result : natural;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
function isum(vec : T_POSVEC) return natural is
variable Result : natural;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
function rsum(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := 0.0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
-- Vector aggregate functions: slv_*
-- ==========================================================================
function slv_or(vec : std_logic_vector) return std_logic is
variable Result : std_logic;
begin
Result := '0';
for i in vec'range loop
Result := Result or vec(i);
end loop;
return Result;
end function;
function slv_nor(vec : std_logic_vector) return std_logic is
begin
return not slv_or(vec);
end function;
function slv_and(vec : std_logic_vector) return std_logic is
variable Result : std_logic;
begin
Result := '1';
for i in vec'range loop
Result := Result and vec(i);
end loop;
return Result;
end function;
function slv_nand(vec : std_logic_vector) return std_logic is
begin
return not slv_and(vec);
end function;
function slv_xor(vec : std_logic_vector) return std_logic is
variable res : std_logic;
begin
res := '0';
for i in vec'range loop
res := res xor vec(i);
end loop;
return res;
end function;
-- ===========================================================================
-- Type conversion
-- ===========================================================================
-- Convert to integer: to_int
function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer is
begin
return ite(bool, one, zero);
end function;
function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer is
begin
if (sl = '1') then
return one;
end if;
return zero;
end function;
-- Convert to bit: to_sl
-- ===========================================================================
function to_sl(Value : boolean) return std_logic is
begin
return ite(Value, '1', '0');
end function;
function to_sl(Value : character) return std_logic is
begin
case Value is
when 'U' => return 'U';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- Convert to vector: to_slv
-- ===========================================================================
-- short for std_logic_vector(to_unsigned(Value, Size))
-- the return value is guaranteed to have the range (Size-1 downto 0)
function to_slv(Value : natural; Size : positive) return std_logic_vector is
constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size));
begin
return res;
end function;
-- Convert to T_BCD or T_BCD_VECTOR: to_BCD*
-- ===========================================================================
function to_BCD(Digit : integer) return T_BCD is
begin
return T_BCD(to_unsigned(Digit, T_BCD'length));
end function;
function to_BCD(Digit : character) return T_BCD is
begin
return T_BCD(to_unsigned((character'pos(Digit) - CHARACTER'pos('0')), T_BCD'length));
end function;
function to_BCD(Digit : unsigned) return T_BCD is
begin
return T_BCD(Digit);
end function;
function to_BCD(Digit : std_logic_vector) return T_BCD is
begin
return T_BCD(Digit);
end function;
function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is
begin
return to_BCD_Vector(integer'image(Value), Size, Fill);
end function;
function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is
variable Result : T_BCD_VECTOR(Size - 1 downto 0);
begin
Result := (others => Fill);
for i in Value'range loop
Result(Value'length - (i - Value'low) - 1) := to_BCD(Value(i));
end loop;
return Result;
end function;
-- bound array indices for simulation, to prevent out of range errors
function bound(index : integer; lowerBound : integer; upperBound : integer) return integer is
begin
if index < lowerBound then
return lowerBound;
elsif upperBound < index then
return upperBound;
else
return index;
end if;
end function;
function to_index(slv : unsigned; max : natural := 0) return integer is
variable res : integer;
begin
if (slv'length = 0) then return 0; end if;
res := to_integer(slv);
if SIMULATION and max > 0 then
res := imin(res, max);
end if;
return res;
end function;
-- bound array indices for simulation, to prevent out of range errors
function to_index(slv : std_logic_vector; max : natural := 0) return integer is
begin
return to_index(unsigned(slv), max);
end function;
-- is_*
-- ===========================================================================
function is_sl(c : character) return boolean is
begin
case c is
when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true;
when others => return false;
end case;
end function;
-- Reverse vector elements
function reverse(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'range);
begin
for i in vec'low to vec'high loop
res(vec'low + (vec'high-i)) := vec(i);
end loop;
return res;
end function;
function reverse(vec : bit_vector) return bit_vector is
variable res : bit_vector(vec'range);
begin
res := to_bitvector(reverse(to_stdlogicvector(vec)));
return res;
end function;
function reverse(vec : unsigned) return unsigned is
begin
return unsigned(reverse(std_logic_vector(vec)));
end function;
-- Swap sub vectors in vector
-- ==========================================================================
function swap(slv : std_logic_vector; Size : positive) return std_logic_vector is
constant SegmentCount : natural := slv'length / Size;
variable FromH : natural;
variable FromL : natural;
variable ToH : natural;
variable ToL : natural;
variable Result : std_logic_vector(slv'length - 1 downto 0);
begin
for i in 0 to SegmentCount - 1 loop
FromH := ((i + 1) * Size) - 1;
FromL := i * Size;
ToH := ((SegmentCount - i) * Size) - 1;
ToL := (SegmentCount - i - 1) * Size;
Result(ToH downto ToL) := slv(FromH downto FromL);
end loop;
return Result;
end function;
-- Swap the bits in a chunk
-- ==========================================================================
function bit_swap(slv : std_logic_vector; Chunksize : positive) return std_logic_vector is
constant SegmentCount : natural := slv'length / Chunksize;
variable FromH : natural;
variable FromL : natural;
variable Result : std_logic_vector(slv'length - 1 downto 0);
begin
for i in 0 to SegmentCount - 1 loop
FromH := ((i + 1) * Chunksize) - 1;
FromL := i * Chunksize;
Result(FromH downto FromL) := reverse(slv(FromH downto FromL));
end loop;
return Result;
end function;
-- generate bit masks
-- ==========================================================================
function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector is
begin
if Bits = 0 then
return (MaskLength - 1 downto 0 => '0');
else
return (MaskLength - 1 downto MaskLength - Bits + 1 => '1') & (MaskLength - Bits downto 0 => '0');
end if;
end function;
function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector is
begin
if Bits = 0 then
return (MaskLength - 1 downto 0 => '0');
else
return (MaskLength - 1 downto Bits => '0') & (Bits - 1 downto 0 => '1');
end if;
end function;
function genmask_alternate(len : positive; lsb : std_logic := '0') return std_logic_vector is
variable curr : std_logic;
variable res : std_logic_vector(len-1 downto 0);
begin
curr := lsb;
for i in res'reverse_range loop
res(i) := curr;
curr := not curr;
end loop;
return res;
end function;
-- binary encoding conversion functions
-- ==========================================================================
-- One-Hot-Code to Binary-Code
function onehot2bin(onehot : std_logic_vector; empty_val : integer := -1) return unsigned is
variable res : unsigned(log2ceilnz(imax(onehot'high, empty_val)+1)-1 downto 0);
variable chk : natural;
begin
-- Note: empty_val = 0 takes the regular path to reduce on synthesized hardware
if empty_val > 0 and onehot = (onehot'range => '0') then
res := to_unsigned(empty_val, res'length);
else
res := (others => '0');
chk := 0;
for i in onehot'range loop
if onehot(i) = '1' then
res := res or to_unsigned(i, res'length);
chk := chk + 1;
end if;
end loop;
if SIMULATION and chk /= 1 and (chk > 1 or empty_val < 0) then
report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set."
severity warning;
res := (others => 'X'); -- computed result is implementation-dependant
end if;
end if;
return res;
end function;
-- Gray-Code to Binary-Code
function gray2bin(gray_val : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(gray_val'length downto 0);
variable res : std_logic_vector(gray_val'range);
begin
tmp := '0' & gray_val;
for i in tmp'left-1 downto 0 loop
tmp(i) := tmp(i+1) xor tmp(i);
end loop;
res := tmp(tmp'left-1 downto 0);
return res;
end function;
-- Binary-Code to One-Hot-Code
function bin2onehot(Value : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(2**Value'length - 1 downto 0);
begin
result := (others => '0');
result(to_index(Value, 0)) := '1';
return result;
end function;
-- Binary-Code to Gray-Code
function bin2gray(Value : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(Value'length downto 0);
variable res : std_logic_vector(Value'range);
begin
tmp := ('0' & Value) xor (Value & '0');
res := tmp(Value'length downto 1);
return res;
end function;
-- bit searching / bit indices
-- ==========================================================================
-- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg.
function lssb(arg : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(arg'range);
begin
res := arg and std_logic_vector(unsigned(not arg)+1);
return res;
end function;
function lssb(arg : bit_vector) return bit_vector is
variable res : bit_vector(arg'range);
begin
res := to_bitvector(lssb(to_stdlogicvector(arg)));
return res;
end function;
-- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector is
begin
return reverse(lssb(reverse(arg)));
end function;
function mssb(arg : bit_vector) return bit_vector is
begin
return reverse(lssb(reverse(arg)));
end function;
-- Index of lssb
function lssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(lssb(arg)));
end function;
function lssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return lssb_idx(slv);
end function;
-- Index of mssb
function mssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(mssb(arg)));
end function;
function mssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return mssb_idx(slv);
end function;
-- scale a value into a given range
function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is
begin
return scale(real(Value), Minimum, Maximum, RoundingStyle);
end function;
function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is
variable Result : REAL;
begin
if Maximum < Minimum then
return integer'low;
else
Result := real(Value) * ((real(Maximum) + 0.5) - (real(Minimum) - 0.5)) + (real(Minimum) - 0.5);
case RoundingStyle is
when ROUND_TO_NEAREST => return integer(round(Result));
when ROUND_TO_ZERO => report "scale: unsupported RoundingStyle." severity FAILURE;
when ROUND_TO_INF => report "scale: unsupported RoundingStyle." severity FAILURE;
when ROUND_UP => return integer(ceil(Result));
when ROUND_DOWN => return integer(floor(Result));
when others => report "scale: unsupported RoundingStyle." severity FAILURE;
end case;
return integer(Result);
end if;
end function;
function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL is
begin
if Maximum < Minimum then
return REAL'low;
else
return Value * (Maximum - Minimum) + Minimum;
end if;
end function;
function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : bit_vector(vec'low to high2b);
variable res_dn : bit_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end function;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : std_logic_vector(vec'low to high2b);
variable res_dn : std_logic_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end function;
-- Move vector boundaries
-- ==========================================================================
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is
variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs);
variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs);
begin
if vec'ascending then
res_up := vec;
return res_up;
else
res_dn := vec;
return res_dn;
end if;
end function;
function movez(vec : std_logic_vector) return std_logic_vector is
begin
return move(vec, -vec'low);
end function;
function ascend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'low to vec'high);
begin
res := vec;
return res;
end function;
function descend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'high downto vec'low);
begin
res := vec;
return res;
end function;
end package body;
| gpl-2.0 | 98e8699f5c407be2273d9711a74215df | 0.630216 | 3.473938 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3043.vhd | 4 | 2,277 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3043.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p02n03i03043ent IS
END c12s02b02x00p02n03i03043ent;
ARCHITECTURE c12s02b02x00p02n03i03043arch OF c12s02b02x00p02n03i03043ent IS
BEGIN
bl1: block
generic (i1:integer; i2:integer; i3:integer; i4:integer);
generic map(i2=>-5, i1=>3, i4=>-4, i3=>6);
begin
assert (i1=3)
report "Generic association for first element I1 incorrect"
severity failure;
assert (i2=-5)
report "Generic association for second element I2 incorrect"
severity failure;
assert (i3=6)
report "Generic association for third element I3 incorrect"
severity failure;
assert (i4=-4)
report "Generic association for fourth element I4 incorrect"
severity failure;
assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***PASSED TEST: c12s02b02x00p02n03i03043"
severity NOTE;
assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***FAILED TEST: c12s02b02x00p02n03i03043 - Named association of generics creates constnats without the correct values."
severity ERROR;
end block;
END c12s02b02x00p02n03i03043arch;
| gpl-2.0 | 288b605100e649e3352d8d5d6e619b85 | 0.673254 | 3.591483 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc522.vhd | 4 | 7,095 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc522.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n01i00522ent IS
END c03s03b00x00p03n01i00522ent;
ARCHITECTURE c03s03b00x00p03n01i00522arch OF c03s03b00x00p03n01i00522ent IS
BEGIN
TESTING: PROCESS
-- Declare access types and access objects everywhere.
-- Enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
type AC1 is access SWITCH_LEVEL;
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
type AC2 is access LOGIC_SWITCH;
-- Access types.
type AC3 is access AC2;
-- array types. Constrained.
type WORD is array(0 to 31) of BIT;
type AC4 is access WORD;
-- record types.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
type AC5 is access DATE;
-- INTEGER types.
type AC6 is access INTEGER;
type POSITIVE is range 0 to INTEGER'HIGH;
type AC7 is access POSITIVE;
-- Physical types.
type AC8 is access TIME;
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
type AC10 is access DISTANCE;
-- floating point types.
type AC11 is access REAL;
type POSITIVE_R is range 0.0 to REAL'HIGH;
type AC12 is access POSITIVE_R;
-- Predefined enumerated types.
type AC13 is access BIT;
type AC14 is access SEVERITY_LEVEL;
type AC15 is access BOOLEAN;
type AC16 is access CHARACTER;
-- Other predefined types.
type AC17 is access NATURAL;
type AC18 is access STRING;
type AC19 is access BIT_VECTOR;
type MEMORY is array(0 to 64) of WORD;
type AC20 is access MEMORY;
-- Declare all the variables.
variable VAR1 : AC1;
variable VAR2 : AC2;
variable VAR3 : AC3;
variable VAR4 : AC4;
variable VAR5 : AC5;
variable VAR6 : AC6;
variable VAR7 : AC7;
variable VAR8 : AC8;
variable VAR10: AC10;
variable VAR11: AC11;
variable VAR12: AC12;
variable VAR13: AC13;
variable VAR14: AC14;
variable VAR15: AC15;
variable VAR16: AC16;
variable VAR17: AC17;
variable VAR18: AC18;
variable VAR19: AC19;
variable VAR20: AC20;
BEGIN
-- Assert that all variables are initially NULL.
assert (VAR1 = null)
report "VAR1 has not been set to NULL.";
assert (VAR2 = null)
report "VAR2 has not been set to NULL.";
assert (VAR3 = null)
report "VAR3 has not been set to NULL.";
assert (VAR4 = null)
report "VAR4 has not been set to NULL.";
assert (VAR5 = null)
report "VAR5 has not been set to NULL.";
assert (VAR6 = null)
report "VAR6 has not been set to NULL.";
assert (VAR7 = null)
report "VAR7 has not been set to NULL.";
assert (VAR8 = null)
report "VAR8 has not been set to NULL.";
assert (VAR10 = null)
report "VAR10 has not been set to NULL.";
assert (VAR11 = null)
report "VAR11 has not been set to NULL.";
assert (VAR12 = null)
report "VAR12 has not been set to NULL.";
assert (VAR13 = null)
report "VAR13 has not been set to NULL.";
assert (VAR14 = null)
report "VAR14 has not been set to NULL.";
assert (VAR15 = null)
report "VAR15 has not been set to NULL.";
assert (VAR16 = null)
report "VAR16 has not been set to NULL.";
assert (VAR17 = null)
report "VAR17 has not been set to NULL.";
assert (VAR18 = null)
report "VAR18 has not been set to NULL.";
assert (VAR19 = null)
report "VAR19 has not been set to NULL.";
assert (VAR20 = null)
report "VAR20 has not been set to NULL.";
assert NOT( (VAR1 = null)
and (VAR2 = null)
and (VAR3 = null)
and (VAR4 = null)
and (VAR5 = null)
and (VAR6 = null)
and (VAR7 = null)
and (VAR8 = null)
and (VAR10 = null)
and (VAR11 = null)
and (VAR12 = null)
and (VAR13 = null)
and (VAR14 = null)
and (VAR15 = null)
and (VAR16 = null)
and (VAR17 = null)
and (VAR18 = null)
and (VAR19 = null)
and (VAR20 = null))
report "***PASSED TEST: c03s03b00x00p03n01i00522"
severity NOTE;
assert ( (VAR1 = null)
and (VAR2 = null)
and (VAR3 = null)
and (VAR4 = null)
and (VAR5 = null)
and (VAR6 = null)
and (VAR7 = null)
and (VAR8 = null)
and (VAR10 = null)
and (VAR11 = null)
and (VAR12 = null)
and (VAR13 = null)
and (VAR14 = null)
and (VAR15 = null)
and (VAR16 = null)
and (VAR17 = null)
and (VAR18 = null)
and (VAR19 = null)
and (VAR20 = null))
report "***FAILED TEST: c03s03b00x00p03n01i00522 - The null value of an access type is the default initial value of the type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n01i00522arch;
| gpl-2.0 | 27952afd7828511b7a3858c99f1022b4 | 0.543481 | 4.01528 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_10.vhd | 4 | 1,805 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_10.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_10 is
end entity fg_a_10;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_10 is
signal clk25M, resetl : std_ulogic;
signal data, odat : std_ulogic_vector(7 downto 0);
begin
-- code from book
right_way : process ( clk25M, resetl )
begin
if resetl = '0' then
odat <= B"0000_0000";
elsif rising_edge(clk25M) then
if data = B"0000_0000" then
odat <= B"0000_0001";
else
odat <= data;
end if;
end if;
end process right_way;
-- end code from book
data <= odat(6 downto 0) & '0';
clk_gen : process is
begin
clk25M <= '0', '1' after 10 ns;
wait for 20 ns;
end process clk_gen;
resetl <= '1', '0' after 20 ns, '1' after 60 ns;
end architecture test;
| gpl-2.0 | f1e17a7619e7a7e44bf9374ae8bfb623 | 0.611634 | 3.639113 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1549.vhd | 4 | 5,209 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1549.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01549ent IS
END c08s09b00x00p10n01i01549ent;
ARCHITECTURE c08s09b00x00p10n01i01549arch OF c08s09b00x00p10n01i01549ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type COLORS is (RED, GREEN, BLUE);
-- local variables
variable EXECUTED_ONCE : BOOLEAN;
variable COUNT : INTEGER;
variable k : integer := 0;
BEGIN
-- 1. These for-loops should only execute one time.
EXECUTED_ONCE := FALSE;
for I in INTEGER'HIGH to INTEGER'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in first loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'LOW to INTEGER'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in second loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'HIGH downto INTEGER'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in third loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'LOW downto INTEGER'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in fourth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'HIGH to COLORS'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in fifth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'LOW to COLORS'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in sixth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'HIGH downto COLORS'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in seventh loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'LOW downto COLORS'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in eighth loop.";
EXECUTED_ONCE := TRUE;
end loop;
-- 2. These for-loops should be executed COUNT number of times.
COUNT := 0;
for I in 3 to 13 loop
COUNT := COUNT + 1;
end loop;
if (count /= 11) then
k := 1;
end if;
assert (COUNT = 11)
report "Failing in 9th loop.";
COUNT := 0;
for I in 13 downto 3 loop
COUNT := COUNT + 1;
end loop;
if (count /= 11) then
k := 1;
end if;
assert (COUNT = 11)
report "Failing in 10th loop.";
COUNT := 0;
for I in COLORS'LOW to COLORS'HIGH loop
COUNT := COUNT + 1;
end loop;
if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
k := 1;
end if;
assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
report "Failing in 11th loop.";
COUNT := 0;
for I in COLORS'HIGH downto COLORS'LOW loop
COUNT := COUNT + 1;
end loop;
if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
k := 1;
end if;
assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
report "Failing in 12th loop.";
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n01i01549"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n01i01549 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01549arch;
| gpl-2.0 | 403a7d41904e2aa0037d54fcfcbb8d8b | 0.597811 | 3.791121 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc395.vhd | 4 | 1,989 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc395.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p06n02i00395ent IS
END c03s02b01x01p06n02i00395ent;
ARCHITECTURE c03s02b01x01p06n02i00395arch OF c03s02b01x01p06n02i00395ent IS
type A1 is array (positive range 1 to 2) of BOOLEAN;
type R1 is record
RE1: A1; -- no_failure_here
end record;
BEGIN
TESTING: PROCESS
variable k : R1;
BEGIN
k.RE1(1) := TRUE;
k.RE1(2) := FALSE;
assert NOT( k.RE1(1) = TRUE and
k.RE1(2) = FALSE )
report "***PASSED TEST: c03s02b01x01p06n02i00395"
severity NOTE;
assert ( k.RE1(1) = TRUE and
k.RE1(2) = FALSE )
report "***FAILED TEST: c03s02b01x01p06n02i00395 - Record element cannot be an unconstrained array."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p06n02i00395arch;
| gpl-2.0 | 6f1f11d9f15b4a536cf3caa5625e61de | 0.641528 | 3.55814 | false | true | false | false |
tgingold/ghdl | testsuite/synth/synth47/test2.vhdl | 1 | 636 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port (val : out std_logic_vector (63 downto 0));
end entity test2;
architecture beh of test2 is
type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
signal s_register : t_register;
begin
-- the problem is the next line
s_register <= (0 => "1111X00Z", 1 => x"e1", 2 => x"d2", 3 => x"c3",
4 => x"b4", 5 => x"a5", 6 => x"96", 7 => x"87");
val <= s_register(7) & s_register(6) & s_register(5) & s_register(4)
& s_register(3) & s_register(2) & s_register(1) & s_register(0);
end architecture beh;
| gpl-2.0 | 3ef1277e3ce48d3ddba54085e1c03617 | 0.603774 | 2.717949 | false | true | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/lpm_bustri_oe0.vhd | 1 | 3,529 | -- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri_oe0.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri_oe0 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END lpm_bustri_oe0;
ARCHITECTURE SYN OF lpm_bustri_oe0 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 16
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
-- Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_oe0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_oe0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_oe0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_oe0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_oe0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| mit | 9d785e4c541b186585ad06884919c75f | 0.621422 | 3.734392 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc376.vhd | 4 | 1,933 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc376.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00376ent IS
END c03s02b01x01p03n03i00376ent;
ARCHITECTURE c03s02b01x01p03n03i00376arch OF c03s02b01x01p03n03i00376ent IS
type my_word is array (0 to 3) of bit;
type it is array (integer range my_word'range) of bit;
BEGIN
TESTING: PROCESS
variable itt : it;
BEGIN
assert NOT(itt(0)='0' and itt(1)='0' and itt(2)='0' and itt(3)='0')
report "***PASSED TEST: c03s02b01x01p03n03i00376"
severity NOTE;
assert (itt(0)='0' and itt(1)='0' and itt(2)='0' and itt(3)='0')
report "***FAILED TEST: c03s02b01x01p03n03i00376 - The index constraint must provide a discrete range for each index of the array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00376arch;
| gpl-2.0 | e8ac8ee7f4c7503808112a2b9566e8d2 | 0.666322 | 3.48917 | false | true | false | false |
tgingold/ghdl | testsuite/gna/ticket89/x_ieee_proposed/src/std_logic_1164_additions.vhdl | 3 | 68,369 | ------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2010/09/22 18:32:33 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.13 2010/09/22 18:32:33 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
-- pragma synthesis_off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-- end Bugzilla issue #148
-------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- Table for the ?< function (Section 9.2.3)
constant qlt : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'X'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | H |
('X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not (qlt (l, r) or match_logic_table (l,r));
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not qlt (l, r);
end function \?>=\;
-- %%% END FUNCTION "?>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r);
end function \?<\;
-- %%% END FUNCTION "?<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r) or match_logic_table (l,r);
end function \?<=\;
-- %%% END FUNCTION "?<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-- pragma synthesis_off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
| gpl-2.0 | 82a07e492513d92afef526758edf6b05 | 0.500358 | 3.939214 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_07.vhd | 4 | 1,816 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration counter_down_to_gate_level of counter is
for registered
for all : digit_register
use configuration work.reg4_gate_level;
end for;
-- . . . -- bindings for other component instances
end for; -- end of architecture registered
end configuration counter_down_to_gate_level;
-- not in book
entity fg_13_07 is
end entity fg_13_07;
use work.counter_types.all;
architecture test of fg_13_07 is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : configuration work.counter_down_to_gate_level
port map ( clk => clk, clr => clr,
q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns,
'0' after 135 ns;
end architecture test;
-- end not in book
| gpl-2.0 | f784ead376947cb6d69f767e63d46a64 | 0.628304 | 3.759834 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug037/strings.vhdl | 2 | 32,637 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- digit subtypes incl. error value (-1)
subtype T_DIGIT_BIN is INTEGER range -1 to 1;
subtype T_DIGIT_OCT is INTEGER range -1 to 7;
subtype T_DIGIT_DEC is INTEGER range -1 to 9;
subtype T_DIGIT_HEX is INTEGER range -1 to 15;
-- to_digit*
function to_digit_bin(chr : character) return T_DIGIT_BIN;
function to_digit_oct(chr : character) return T_DIGIT_OCT;
function to_digit_dec(chr : character) return T_DIGIT_DEC;
function to_digit_hex(chr : character) return T_DIGIT_HEX;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_calign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING;
function str_lalign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING;
function str_ralign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant overflow : boolean := frac >= 10**precision;
constant int2 : INTEGER := ite(overflow, int+1, int);
constant frac2 : INTEGER := ite(overflow, frac-10**precision, frac);
constant frac_str : STRING := INTEGER'image(frac2);
constant res : STRING := INTEGER'image(int2) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return T_DIGIT_BIN is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return T_DIGIT_OCT is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return T_DIGIT_DEC is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return T_DIGIT_HEX is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then -- workaround for Quartus II
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_calign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING is
constant Start : POSITIVE := (length - str'length) / 2;
variable Result : STRING(1 to length);
begin
Result := (others => FillChar);
Result(Start to (Start + str'length)) := str;
return Result;
end function;
function str_lalign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING is
variable Result : STRING(1 to length);
begin
Result := (others => FillChar);
Result(1 to str'length) := str;
return Result;
end function;
function str_ralign(str : STRING; length : NATURAL; FillChar : CHARACTER := ' ') return STRING is
variable Result : STRING(1 to length);
begin
Result := (others => FillChar);
Result((length - str'length + 1) to length) := str;
return Result;
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
| gpl-2.0 | c123917fb11c4514604ed459853441d4 | 0.61562 | 3.291679 | false | false | false | false |
tgingold/ghdl | testsuite/vpi/vpi001/mydesign.vhdl | 1 | 822 | library ieee ;
use ieee.std_logic_1164.all;
entity myentity is
generic (
genint: integer := 42;
genstring: string := "fish";
genbool: boolean := True;
gensl: std_logic := '0'
);
port (
iportbool: in boolean;
iportint: in integer;
iportsl: in std_logic;
oportbool: out boolean;
oportint: out integer;
oportsl: out std_logic
);
end myentity;
architecture arch of myentity is
constant constsl: std_logic := '0';
signal sigsl: std_logic;
constant constint: integer := 42;
signal sigint: integer;
constant constbool: boolean := True;
signal sigbool: boolean;
constant conststring: string := "fish";
begin
sigsl <= iportsl;
sigbool <= iportbool;
sigint <= iportint;
oportbool <= constbool;
oportint <= constint;
oportsl <= constsl;
end arch;
| gpl-2.0 | 51b9dbd0ec296d3e2224d5e8063a8bc5 | 0.654501 | 3.468354 | false | false | false | false |
nickg/nvc | test/sem/alias.vhd | 1 | 3,615 | entity e is
end entity;
architecture test of e is
alias my_int is integer; -- OK
signal x : my_int; -- OK
subtype s is my_int range 1 to 5; -- OK
alias my_bad : integer is integer; -- Error
alias ax is x; -- OK
signal y : ax; -- Error
alias as is s; -- OK
signal z : as; -- OK
function foo (x : bit) return integer;
function foo (x : character) return integer;
alias foo_bit is foo [bit return integer]; -- OK
alias foo_char is foo [character return integer]; -- OK
alias foo_int is foo [integer return integer]; -- Error
alias foo_p is foo [bit]; -- Error
alias foo_a is foo(1) [bit return integer]; -- Error
alias foo_b is foo [blah return integer]; -- Error
procedure bar (x : bit);
procedure bar (x : character);
alias bar_bit is bar [bit]; -- OK
alias bar_char is bar [character]; -- OK
alias bar_int is bar [integer]; -- Error
procedure test is
begin
assert foo_bit('1') = 1; -- OK
assert foo_char('1') = 1; -- OK
bar_bit('1'); -- OK
bar_char('1'); -- OK
assert foo('1') = 1; -- Error
assert foo_int(1) = 1; -- Error
bar_bit(character'( '1' )); -- Error
bar_bit(character'(1)); -- Error
end procedure;
type bv_ptr is access bit_vector;
procedure test2(variable x : bv_ptr) is
variable v : bit_vector(1 to 10);
alias va is v(x'left); -- Error
begin
end procedure;
procedure maybe_use_last_value(signal x : my_int);
procedure proc is
begin
maybe_use_last_value(ax);
end procedure;
type int_array is array (integer range <>) of integer;
alias int_vector is int_array;
type int_array_2 is array (integer range <>) of integer;
constant c1 : int_array_2(1 to 3) := (1, 2, 3);
constant c2 : int_vector(1 to 3) := int_vector(c1); -- OK
subtype bad is blah blah blah; -- Error
function foo_bad (x : bit) return bad; -- OK
function foo_bad (x : bit) return bad; -- Error (suppressed)
alias foo_o is foo_bad [bit return bad]; -- OK
alias foo_o is foo_bad [character return bad]; -- Error (suppressed)
alias my_now is std.standard.now [return delay_length]; -- OK
alias my_eq is std.standard."=" [bit, bit return boolean]; -- OK
type int_mat2d is array (integer range <>, integer range <>) of integer;
constant c3 : int_mat2d(1 to 2, 1 to 2) := ((1, 2), (3, 4));
alias c2_alias is c3; -- Error (in '93)
constant c4 : integer := int_vector; -- Error
type line is access string;
procedure access_alias ( variable p : inout line ) is
variable l : line;
alias a : string(1 to 3) is l.all; -- Error
alias b : string(1 to p'length) is p.all; -- Error
begin
end procedure;
constant LEN : natural := 20 ;
function doit return bit_vector is
alias length : natural is LEN ;
-- Following is OK, from UVVM
constant rv : bit_vector(length-1 downto 0) := (length-1 => '1', others =>'0') ;
begin
return rv ;
end function ;
procedure double_alias is
type r is record
x, y : integer;
end record;
alias a1 is r;
alias a2 is a1; -- OK
variable v : a2; -- OK
begin
end procedure;
begin
end architecture;
| gpl-3.0 | 31c01a47cb3a1180ebcb43f2c3f5d1d0 | 0.539419 | 3.73065 | false | false | false | false |
nickg/nvc | test/regress/issue570.vhd | 1 | 686 | package pack is
function "=" (L: bit; R: bit) return bit;
end package;
package body pack is
function "=" (L: bit; R: bit) return bit is
begin
if L = R then
return '1';
else
return '0';
end if;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity issue570 is
end entity;
architecture test of issue570 is
signal x : bit := '1';
begin
p1: process is
begin
assert (bit'( '1' ) = bit'( '1' )) = '1';
if x = '0' then
assert false;
end if;
wait;
end process;
end architecture;
| gpl-3.0 | 4af03614413aaed8a164cf4f0e69de31 | 0.466472 | 3.942529 | false | false | false | false |
tgingold/ghdl | testsuite/synth/conv01/pos01.vhdl | 1 | 1,061 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pos01 is
generic (g_en : boolean := True);
port (clk : std_logic;
rst : std_logic;
en : std_logic;
st : out std_logic_vector(1 downto 0));
end pos01;
architecture behav of pos01 is
type t_state is (IDLE, WAIT1, WAIT2, DONE);
signal s : t_state;
constant c1 : integer := t_state'pos(WAIT2);
constant c2 : integer := boolean'pos(g_en);
begin
process (clk) is
begin
if rising_edge(clk) then
if rst = '1' then
s <= IDLE;
else
case s is
when IDLE =>
if en = '1' then
s <= WAIT1;
end if;
when WAIT1 =>
if en = '1' then
s <= WAIT2;
end if;
when WAIT2 =>
if en = '1' then
s <= DONE;
end if;
when DONE =>
null;
end case;
end if;
end if;
end process;
st <= std_logic_vector(to_unsigned(t_state'pos(s), 2));
end behav;
| gpl-2.0 | c476b66d9a314a0e676dd770bbcff3e4 | 0.493874 | 3.478689 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xbip_dsp48_multadd_v3_0_2/xbip_dsp48_multadd_v3_0_vh_rfs.vhd | 9 | 73,491 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | a3cc85bdeb3599726fc1e43a76f4e456 | 0.951572 | 1.838378 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-r.vhd | 4 | 6,274 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mac-r.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture rtl of mac is
signal pipelined_x_real,
pipelined_x_imag,
pipelined_y_real,
pipelined_y_imag : std_ulogic_vector(15 downto 0);
signal real_part_product_1,
real_part_product_2,
imag_part_product_1,
imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal pipelined_real_part_product_1,
pipelined_real_part_product_2,
pipelined_imag_part_product_1,
pipelined_imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal real_product,
imag_product : std_ulogic_vector(32 downto 0);
signal pipelined_real_product,
pipelined_imag_product : std_ulogic_vector(19 downto 0);
signal real_sum,
imag_sum : std_ulogic_vector(21 downto 0);
signal real_accumulator_ovf,
imag_accumulator_ovf : std_ulogic;
signal pipelined_real_sum,
pipelined_imag_sum : std_ulogic_vector(21 downto 0);
signal pipelined_real_accumulator_ovf,
pipelined_imag_accumulator_ovf : std_ulogic;
begin
x_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_real, q => pipelined_x_real );
x_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_imag, q => pipelined_x_imag );
y_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_real, q => pipelined_y_real );
y_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_imag, q => pipelined_y_imag );
real_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_real,
p => real_part_product_1 );
real_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_imag,
p => real_part_product_2 );
imag_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_imag,
p => imag_part_product_1 );
imag_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_real,
p => imag_part_product_2 );
real_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_1,
q => pipelined_real_part_product_1 );
real_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_2,
q => pipelined_real_part_product_2 );
imag_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_1,
q => pipelined_imag_part_product_1 );
imag_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_2,
q => pipelined_imag_part_product_2 );
real_product_subtracter : entity work.product_adder_subtracter(behavioral)
port map ( mode => '1',
a => pipelined_real_part_product_1,
b => pipelined_real_part_product_2,
s => real_product );
imag_product_adder : entity work.product_adder_subtracter(behavioral)
port map ( mode => '0',
a => pipelined_imag_part_product_1,
b => pipelined_imag_part_product_2,
s => imag_product );
real_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => real_product(32 downto 13),
q => pipelined_real_product );
imag_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => imag_product(32 downto 13),
q => pipelined_imag_product );
real_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_real_product(19 downto 0),
a(20) => pipelined_real_product(19),
a(21) => pipelined_real_product(19),
b => pipelined_real_sum,
s => real_sum,
ovf => real_accumulator_ovf );
imag_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_imag_product(19 downto 0),
a(20) => pipelined_imag_product(19),
a(21) => pipelined_imag_product(19),
b => pipelined_imag_sum,
s => imag_sum,
ovf => imag_accumulator_ovf );
real_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => real_sum, q => pipelined_real_sum );
imag_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => imag_sum, q => pipelined_imag_sum );
real_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => real_accumulator_ovf, clr => clr,
q => pipelined_real_accumulator_ovf );
imag_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => imag_accumulator_ovf, clr => clr,
q => pipelined_imag_accumulator_ovf );
s_real <= pipelined_real_sum(21) & pipelined_real_sum(16 downto 2);
s_imag <= pipelined_imag_sum(21) & pipelined_imag_sum(16 downto 2);
result_overflow_logic : entity work.overflow_logic(behavioral)
port map ( real_accumulator_ovf => pipelined_real_accumulator_ovf,
imag_accumulator_ovf => pipelined_imag_accumulator_ovf,
real_sum => pipelined_real_sum(21 downto 17),
imag_sum => pipelined_imag_sum(21 downto 17),
ovf => ovf );
end architecture rtl;
| gpl-2.0 | 4508039e084d2038ae22c66b5f09c7b7 | 0.633408 | 3.564773 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_full_wrap.vhd | 3 | 70,871 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_reset;
use axi_datamover_v5_1_10.axi_datamover_cmd_status;
use axi_datamover_v5_1_10.axi_datamover_pcc;
use axi_datamover_v5_1_10.axi_datamover_addr_cntl;
use axi_datamover_v5_1_10.axi_datamover_rddata_cntl;
use axi_datamover_v5_1_10.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1_10.axi_datamover_mm2s_dre;
Use axi_datamover_v5_1_10.axi_datamover_rd_sf;
use axi_datamover_v5_1_10.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_full_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 1;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the incllusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit Store and Forward
-- 1 = Include Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ---------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- MM2S Halt request input control --------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Error discrete output ------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ---------
-- Used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
-------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
---------------------------------------------------------------
-- Address Posting contols ------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
---------------------------------------------------------------
-- MM2S AXI Address Channel I/O ---------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals ------------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
------------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O -----------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
---------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
----------------------------------------------------------------------------------------
-- Testing Support I/O -------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------
);
end entity axi_datamover_mm2s_full_wrap;
architecture implementation of axi_datamover_mm2s_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else -- no DRE
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others => -- 128 ratio
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for MM2S
-- modules upstream from the downsizing Store and Forward. If
-- Store and Forward is present, then the effective native width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Native Data width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled = 1) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-- Constant Declarations ----------------------------------------
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH,
C_MM2S_SDATA_WIDTH,
C_INCLUDE_MM2S_GP_SF);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S;
Constant IS_MM2S : integer range 0 to 1 := 1;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH;
Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE;
Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED;
Constant NO_INDET_BTT : integer range 0 to 1 := 0;
Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE,
C_MM2S_SDATA_WIDTH);
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE,
C_MM2S_SDATA_WIDTH);
-- Calculates the minimum needed depth of the Store and Forward FIFO
-- based on the MM2S pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * MM2S_BURST_SIZE;
-- Assigns the depth of the optional Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH,
MM2S_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2rdc_wready : std_logic := '0';
signal sig_rdc2sf_wvalid : std_logic := '0';
signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2sf_wlast : std_logic := '0';
signal sig_skid2dre_wready : std_logic := '0';
signal sig_dre2skid_wvalid : std_logic := '0';
signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2skid_wlast : std_logic := '0';
signal sig_dre2sf_wready : std_logic := '0';
signal sig_sf2dre_wvalid : std_logic := '0';
signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2dre_wlast : std_logic := '0';
signal sig_rdc2dre_new_align : std_logic := '0';
signal sig_rdc2dre_use_autodest : std_logic := '0';
signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_flush : std_logic := '0';
signal sig_sf2dre_new_align : std_logic := '0';
signal sig_sf2dre_use_autodest : std_logic := '0';
signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_flush : std_logic := '0';
signal sig_dre_new_align : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_sf_allow_addr_req : std_logic := '0';
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_sf2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2sf_cmd_valid : std_logic := '0';
signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2sf_drr : std_logic := '0';
signal sig_mstr2sf_eof : std_logic := '0';
signal sig_mstr2sf_calc_error : std_logic := '0';
signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_data2sf_cmd_cmplt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
signal mm2s_aruser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug vector output
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc
mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc
-- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
sig_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32)); -- This is the xUser and xCache values
end generate GEN_CACHE2;
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_10.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_10.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1_10.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1_10.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_MM2S ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_BTT_USED => MM2S_BTT_USED ,
C_SUPPORT_INDET_BTT => NO_INDET_BTT ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_btt => sig_mstr2sf_btt ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_10.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => mm2s_arcache_int ,
addr2axi_auser => mm2s_aruser_int ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_mm2s_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1_10.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => sig_rdc2dre_new_align ,
mm2s_dre_use_autodest => sig_rdc2dre_use_autodest ,
mm2s_dre_src_align => sig_rdc2dre_src_align ,
mm2s_dre_dest_align => sig_rdc2dre_dest_align ,
mm2s_dre_flush => sig_rdc2dre_flush ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2sf_wvalid ,
mm2s_strm_wready => sig_sf2rdc_wready ,
mm2s_strm_wdata => sig_rdc2sf_wdata ,
mm2s_strm_wstrb => sig_rdc2sf_wstrb ,
mm2s_strm_wlast => sig_rdc2sf_wlast ,
-- MM2S Store and Forward Supplimental Control ----------
mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_SF
--
-- If Generate Description:
-- Include the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate
begin
-- Merge external address posting control with the
-- Store and Forward address posting control
sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and
mm2s_allow_addr_req;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
sig_dre_new_align <= sig_sf2dre_new_align ;
sig_dre_use_autodest <= sig_sf2dre_use_autodest ;
sig_dre_src_align <= sig_sf2dre_src_align ;
sig_dre_dest_align <= sig_sf2dre_dest_align ;
sig_dre_flush <= sig_sf2dre_flush ;
------------------------------------------------------------
-- Instance: I_RD_SF
--
-- Description:
-- Instance for the MM2S Store and Forward module with
-- downsizer support.
--
------------------------------------------------------------
I_RD_SF : entity axi_datamover_v5_1_10.axi_datamover_rd_sf
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_DRE_IS_USED => INCLUDE_DRE ,
C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -------------------------------
aclk => mm2s_aclk ,
reset => sig_mmap_rst ,
-- DataMover Read Side Address Pipelining Control Interface
ok_to_post_rd_addr => sig_sf_allow_addr_req ,
rd_addr_posted => sig_addr_req_posted ,
rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S Read Data Controller -----
sf2sin_tready => sig_sf2rdc_wready ,
sin2sf_tvalid => sig_rdc2sf_wvalid ,
sin2sf_tdata => sig_rdc2sf_wdata ,
sin2sf_tkeep => sig_rdc2sf_wstrb ,
sin2sf_tlast => sig_rdc2sf_wlast ,
-- RDC Store and Forward Supplimental Controls ----------
data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
data2sf_dre_flush => sig_rdc2dre_flush ,
-- DRE Control Interface from the Command Calculator -----------------------------
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset ,
-- MM2S DRE Control -------------------------------------------------------------
sf2dre_new_align => sig_sf2dre_new_align ,
sf2dre_use_autodest => sig_sf2dre_use_autodest ,
sf2dre_src_align => sig_sf2dre_src_align ,
sf2dre_dest_align => sig_sf2dre_dest_align ,
sf2dre_flush => sig_sf2dre_flush ,
-- Stream Out ----------------------------------
sout2sf_tready => sig_dre2sf_wready ,
sf2sout_tvalid => sig_sf2dre_wvalid ,
sf2sout_tdata => sig_sf2dre_wdata ,
sf2sout_tkeep => sig_sf2dre_wstrb ,
sf2sout_tlast => sig_sf2dre_wlast
);
-- ------------------------------------------------------------
-- -- Instance: I_RD_SF
-- --
-- -- Description:
-- -- Instance for the MM2S Store and Forward module.
-- --
-- ------------------------------------------------------------
-- I_RD_SF : entity axi_datamover_v5_1_10.axi_datamover_rd_sf
-- generic map (
--
-- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
-- C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
-- C_DRE_IS_USED => INCLUDE_DRE ,
-- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
--
-- -- Clock and Reset inputs -------------------------------
-- aclk => mm2s_aclk ,
-- reset => sig_mmap_rst ,
--
--
-- -- DataMover Read Side Address Pipelining Control Interface
-- ok_to_post_rd_addr => sig_sf_allow_addr_req ,
-- rd_addr_posted => sig_addr_req_posted ,
-- rd_xfer_cmplt => sig_rd_xfer_cmplt ,
--
--
--
-- -- Read Side Stream In from DataMover MM2S -----
-- sf2sin_tready => sig_sf2dre_wready ,
-- sin2sf_tvalid => sig_dre2sf_wvalid ,
-- sin2sf_tdata => sig_dre2sf_wdata ,
-- sin2sf_tkeep => sig_dre2sf_wstrb ,
-- sin2sf_tlast => sig_dre2sf_wlast ,
--
--
--
-- -- Stream Out ----------------------------------
-- sout2sf_tready => sig_skid2sf_wready ,
-- sf2sout_tvalid => sig_sf2skid_wvalid ,
-- sf2sout_tdata => sig_sf2skid_wdata ,
-- sf2sout_tkeep => sig_sf2skid_wstrb ,
-- sf2sout_tlast => sig_sf2skid_wlast
--
-- );
end generate GEN_INCLUDE_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_SF
--
-- If Generate Description:
-- Omit the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate
begin
-- Allow external address posting control
-- Ignore Store and Forward Control
sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ;
sig_sf_allow_addr_req <= '0' ;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
-- DRE Control Bus (Connect to the Read data Controller)
sig_dre_new_align <= sig_rdc2dre_new_align ;
sig_dre_use_autodest <= sig_rdc2dre_use_autodest ;
sig_dre_src_align <= sig_rdc2dre_src_align ;
sig_dre_dest_align <= sig_rdc2dre_dest_align ;
sig_dre_flush <= sig_rdc2dre_flush ;
-- Just pass stream signals through
sig_sf2rdc_wready <= sig_dre2sf_wready ;
sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ;
sig_sf2dre_wdata <= sig_rdc2sf_wdata ;
sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ;
sig_sf2dre_wlast <= sig_rdc2sf_wlast ;
-- Always enable the DRE Cmd bus for loading to keep from
-- stalling the PCC module
sig_sf2mstr_cmd_ready <= LOGIC_HIGH;
end generate GEN_NO_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_DRE
--
-- If Generate Description:
-- Include the MM2S DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate
begin
------------------------------------------------------------
-- Instance: I_DRE64
--
-- Description:
-- Instance for the MM2S DRE whach can support widths of
-- 16 bits to 64 bits.
--
------------------------------------------------------------
I_DRE_16_to_64 : entity axi_datamover_v5_1_10.axi_datamover_mm2s_dre
generic map (
C_DWIDTH => MM2S_SDATA_WIDTH ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH
)
port map (
-- Control inputs
dre_clk => mm2s_aclk ,
dre_rst => sig_stream_rst ,
dre_new_align => sig_dre_new_align ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
dre_flush => sig_dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_sf2dre_wstrb ,
dre_in_tdata => sig_sf2dre_wdata ,
dre_in_tlast => sig_sf2dre_wlast ,
dre_in_tvalid => sig_sf2dre_wvalid ,
dre_in_tready => sig_dre2sf_wready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2skid_wstrb ,
dre_out_tdata => sig_dre2skid_wdata ,
dre_out_tlast => sig_dre2skid_wlast ,
dre_out_tvalid => sig_dre2skid_wvalid ,
dre_out_tready => sig_skid2dre_wready
);
end generate GEN_INCLUDE_MM2S_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_DRE
--
-- If Generate Description:
-- Omit the MM2S DRE and housekeep the signals that it
-- needs to output.
--
------------------------------------------------------------
GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate
begin
-- Just pass stream signals through from the Store
-- and Forward module
sig_dre2sf_wready <= sig_skid2dre_wready ;
sig_dre2skid_wvalid <= sig_sf2dre_wvalid ;
sig_dre2skid_wdata <= sig_sf2dre_wdata ;
sig_dre2skid_wstrb <= sig_sf2dre_wstrb ;
sig_dre2skid_wlast <= sig_sf2dre_wlast ;
end generate GEN_NO_MM2S_DRE;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_dre2skid_wvalid ,
s_ready => sig_skid2dre_wready ,
s_data => sig_dre2skid_wdata ,
s_strb => sig_dre2skid_wstrb ,
s_last => sig_dre2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_dre2skid_wvalid;
sig_skid2dre_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_dre2skid_wdata;
mm2s_strm_wstrb <= sig_dre2skid_wstrb;
mm2s_strm_wlast <= sig_dre2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
| gpl-3.0 | a4b9d5c68827cc10020a1d56aa1f69d4 | 0.439178 | 4.202004 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/asgn04.vhdl | 1 | 401 | library ieee;
use ieee.std_logic_1164.all;
entity asgn04 is
port (s0 : std_logic;
s1 : std_logic;
r : out std_logic_vector (2 downto 0));
end asgn04;
architecture behav of asgn04 is
begin
process (s0, s1) is
begin
r <= "000";
if s0 = '1' then
r (1) <= '1';
if s1 = '1' then
r(1 downto 0) <= "01";
end if;
end if;
end process;
end behav;
| gpl-2.0 | 94964b7a4d399f1b66f1796aae971f12 | 0.548628 | 2.843972 | false | false | false | false |
nickg/nvc | test/sem/issue58.vhd | 5 | 348 | entity issue58 is
begin
end entity issue58;
architecture a of issue58 is
type t is record
g : bit;
end record t;
constant c : t := (
g => '0'
);
component comp is
generic (g : bit_vector := "0");
end component comp;
begin
u : comp
generic map (g => (1 downto 0 => c.g));
end architecture a;
| gpl-3.0 | 2497194d8517f13e501de377bd342b25 | 0.560345 | 3.55102 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue458/e.vhdl | 1 | 1,142 | entity E is
end entity;
architecture A of E is
signal S1 : bit := '0';
signal S2_inertial : bit;
signal S2_transport : bit;
signal S2_delayed : bit;
constant LEVEL : severity_level := FAILURE;
begin
S1 <= '1' after 10 ns, '0' after 20 ns;
S2_inertial <= inertial S1 after 100 ns;
S2_transport <= transport S1 after 100 ns;
S2_delayed <= S1'delayed(100 ns);
CheckInertial: process
begin
wait until S2_inertial = '1' for 200 ns;
assert (S2_inertial = '0') report "Pulse was not rejected!" severity LEVEL;
wait;
end process;
CheckTransport: process
begin
wait until S2_transport = '1' for 115 ns;
assert (S2_transport = '1') report "Pulse was not transport delayed!" severity LEVEL;
assert (now = 110 ns) report "Transport delayed pulse was not received at 110 ns!" severity LEVEL;
wait;
end process;
CheckDelayed: process
begin
wait until S2_delayed = '1' for 115 ns;
assert (S2_delayed = '1') report "Pulse was not delayed!" severity LEVEL;
assert (now = 110 ns) report "Delayed pulse was not received at 110 ns!" severity LEVEL;
wait;
end process;
end architecture;
| gpl-2.0 | 8b1e6a0120533831b58bc950b7cc79cd | 0.682137 | 3.181058 | false | false | false | false |
nickg/nvc | test/regress/vests3.vhd | 1 | 9,130 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc745.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00745pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c: character;
d: severity_level;
e: integer;
f: real;
g: time;
h: natural;
i: positive;
j: string(1 to 7);
k: bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
function F1(inp : boolean_vector) return boolean ;
function F2(inp : bit_vector) return bit ;
function F3(inp : string) return character ;
function F4(inp : severity_level_vector) return severity_level ;
function F5(inp : integer_vector) return integer ;
function F6(inp : real_vector) return real ;
function F7(inp : time_vector) return time ;
function F8(inp : natural_vector) return natural ;
function F9(inp : positive_vector) return positive ;
function F10(inp : array_rec_std) return record_std_package ;
end c01s01b01x01p05n02i00745pkg;
package body c01s01b01x01p05n02i00745pkg is
function F1(inp : boolean_vector) return boolean is
begin
for i in 0 to 15 loop
assert(inp(i) = true) report"wrong initialization of S1" severity error;
end loop;
return false;
end F1;
function F2(inp : bit_vector) return bit is
begin
for i in 0 to 3 loop
assert(inp(i) = '0') report"wrong initialization of S2" severity error;
end loop;
return '0';
end F2;
function F3(inp : string) return character is
begin
for i in 1 to 7 loop
assert(inp(i) = 's') report"wrong initialization of S3" severity error;
end loop;
return 'h';
end F3;
function F4(inp : severity_level_vector) return severity_level is
begin
for i in 0 to 15 loop
assert(inp(i) = note) report"wrong initialization of S4" severity error;
end loop;
return error;
end F4;
function F5(inp : integer_vector) return integer is
begin
for i in 0 to 15 loop
assert(inp(i) = 3) report"wrong initialization of S5" severity error;
end loop;
return 6;
end F5;
function F6(inp : real_vector) return real is
begin
for i in 0 to 15 loop
assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
end loop;
return 6.0;
end F6;
function F7(inp : time_vector) return time is
begin
for i in 0 to 15 loop
assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
end loop;
return 6 ns;
end F7;
function F8(inp : natural_vector) return natural is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S8" severity error;
end loop;
return 6;
end F8;
function F9(inp : positive_vector) return positive is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S9" severity error;
end loop;
return 6;
end F9;
function F10(inp : array_rec_std) return record_std_package is
begin
for i in 0 to 7 loop
assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
end loop;
return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
end F10;
end c01s01b01x01p05n02i00745pkg;
use work.c01s01b01x01p05n02i00745pkg.all;
ENTITY vests3 IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "sssssss";
C11 : bit_vector := B"0000";
C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
);
port(
S1 : boolean_vector(zero to fifteen) := (others => C1);
S2 : severity_level_vector(zero to fifteen) := (others => C4);
S3 : integer_vector(zero to fifteen) := (others => C5);
S4 : real_vector(zero to fifteen) := (others => C6);
S5 : time_vector (zero to fifteen) := (others => C7);
S6 : natural_vector(zero to fifteen) := (others => C8);
S7 : positive_vector(zero to fifteen) := (others => C9);
S8 : string(one to seven) := C10;
S9 : bit_vector(zero to three) := C11;
S48: array_rec_std(zero to seven) := (others => C48)
);
END vests3;
ARCHITECTURE c01s01b01x01p05n02i00745arch OF vests3 IS
BEGIN
TESTING: PROCESS
variable var1 : boolean;
variable var4 : severity_level;
variable var5 : integer;
variable var6 : real;
variable var7 : time;
variable var8 : natural;
variable var9 : positive;
variable var2 : bit;
variable var3 : character;
variable var48: record_std_package;
BEGIN
var1 := F1(S1);
var2 := F2(S9);
var3 := F3(S8);
var4 := F4(S2);
var5 := F5(S3);
var6 := F6(S4);
var7 := F7(S5);
var8 := F8(S6);
var9 := F9(S7);
var48 := F10(S48);
wait for 1 ns;
assert(var1 = false) report "wrong assignment in the function F1" severity error;
assert(var2 = '0') report "wrong assignment in the function F2" severity error;
assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
assert(var4 = error) report "wrong assignment in the function F4" severity error;
assert(var5 = 6) report "wrong assignment in the function F5" severity error;
assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
assert(var8 = 6) report "wrong assignment in the function F8" severity error;
assert(var9 = 6) report "wrong assignment in the function F9" severity error;
assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
assert NOT( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***PASSED TEST: c01s01b01x01p05n02i00745"
severity NOTE;
assert ( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***FAILED TEST: c01s01b01x01p05n02i00745 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00745arch;
| gpl-3.0 | 8c5a644bf4de4d699426fbcd322dd206 | 0.584556 | 3.471483 | false | false | false | false |
tgingold/ghdl | testsuite/synth/oper02/tb_min01.vhdl | 1 | 398 | entity tb_min01 is
end tb_min01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_min01 is
signal l, r : natural;
signal res : natural;
begin
min01_1: entity work.min01
port map (
a => l,
b => r,
o => res);
process
begin
l <= 12;
r <= 15;
wait for 1 ns;
assert res = 12 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 3515328899fa67f057e6d93fe6cf0884 | 0.58794 | 3.085271 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_check_data/sip_capture_x4.vhd | 1 | 18,421 |
-------------------------------------------------------------------------------------
-- FILE NAME : sip_capture_4x.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_mem_if_i
-- architecture - arch_sip_mem_if_i
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Data comes in on in0 and it is multiplexed sequentially between out0 and out1
-- Data comes in on in1 and it is multiplexed sequentially between out2 and out3
-- Data comes in on in2 and if we are in mode = 0, it goes to out4 but converted from 64-bit to 128-bit
-- Data comes in on in3 and if we are in mode = 0 it is dropped stop will be held = 0. If we are in mode = 1
-- data must also come in on in2 because they are combined and go into out4.
-- sip_mem_if_i
-- Notes: sip_mem_if_i
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity sip_capture_x4 is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_in' of type 'cmdclk_in':
cmdclk_in_cmdclk : in std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'out0' of type 'wh_out':
out0_out_stop : in std_logic;
out0_out_dval : out std_logic;
out0_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out1' of type 'wh_out':
out1_out_stop : in std_logic;
out1_out_dval : out std_logic;
out1_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out2' of type 'wh_out':
out2_out_stop : in std_logic;
out2_out_dval : out std_logic;
out2_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out3' of type 'wh_out':
out3_out_stop : in std_logic;
out3_out_dval : out std_logic;
out3_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'in0' of type 'wh_in':
in0_in_stop : out std_logic;
in0_in_dval : in std_logic;
in0_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'in1' of type 'wh_in':
in1_in_stop : out std_logic;
in1_in_dval : in std_logic;
in1_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'in2' of type 'wh_in':
in2_in_stop : out std_logic;
in2_in_dval : in std_logic;
in2_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'in3' of type 'wh_in':
in3_in_stop : out std_logic;
in3_in_dval : in std_logic;
in3_in_data : in std_logic_vector(63 downto 0)
);
end entity sip_capture_x4;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture bev of sip_capture_x4 is
-------------------------------------------------------------------------------------
--Constants declaration
-------------------------------------------------------------------------------------
type bus64 is array(natural range <>) of std_logic_vector(63 downto 0);
type bus12 is array(natural range <>) of std_logic_vector(11 downto 0);
type bus08 is array(natural range <>) of std_logic_vector(7 downto 0);
attribute keep : string;
-------------------------------------------------------------------------------------
--Signal declaration
-------------------------------------------------------------------------------------
signal clk_in : std_logic;
signal clk_out : std_logic;
signal rst : std_logic;
signal local_reset : std_logic;
signal fifo_in : bus64(3 downto 0);
signal fifo_out : bus64(3 downto 0);
signal fifo_wr_en : std_logic_vector(3 downto 0);
signal fifo_valid : std_logic_vector(3 downto 0);
signal fifo_rd_en : std_logic_vector(3 downto 0);
signal fifo_empty : std_logic_vector(3 downto 0);
signal fifo_full : std_logic_vector(3 downto 0);
signal fifo_count : bus12(3 downto 0);
signal register0 : std_logic_vector(31 downto 0);
signal register1 : std_logic_vector(31 downto 0);
signal register0_r : std_logic_vector(31 downto 0);
signal register1_r : std_logic_vector(31 downto 0);
signal register2 : std_logic_vector(31 downto 0);
signal register3 : std_logic_vector(31 downto 0);
signal register4 : std_logic_vector(31 downto 0);
signal register5 : std_logic_vector(31 downto 0);
signal register6 : std_logic_vector(31 downto 0);
signal register7 : std_logic_vector(31 downto 0);
signal register8 : std_logic_vector(31 downto 0);
signal align_fifo_in : bus64(3 downto 0);
signal align_fifo_out : bus64(3 downto 0);
signal align_fifo_wr_en : std_logic_vector(3 downto 0);
signal align_fifo_valid : std_logic_vector(3 downto 0);
signal align_fifo_empty : std_logic_vector(3 downto 0);
signal align_fifo_rd_en : std_logic;
signal byte_align_out : bus64(3 downto 0);
signal byte_align_valid : std_logic_vector(3 downto 0);
signal status : bus08(3 downto 0);
signal check_reset : std_logic;
signal check_enable : std_logic;
signal perfomance_reset : std_logic;
signal performance_en : std_logic;
signal force_error : std_logic_vector(3 downto 0);
signal input_count : std_logic_vector(63 downto 0);
signal cycle_count : std_logic_vector(63 downto 0);
signal output_count : std_logic_vector(63 downto 0);
----------------------------------------------------------------------------------------
-- Debugging
---------------------------------------------------------------------------------------
COMPONENT ila_0
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0)
);
END COMPONENT;
ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF ila_0 : COMPONENT IS TRUE;
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF ila_0 : COMPONENT IS "clk,probe0[255:0]";
signal probe0 : std_logic_vector(255 downto 0);
signal dbg_data0 : std_logic_vector(63 downto 0);
signal dbg_data1 : std_logic_vector(63 downto 0);
signal dbg_data2 : std_logic_vector(63 downto 0);
signal dbg_valid0 : std_logic;
signal dbg_valid1 : std_logic;
signal dbg_valid2 : std_logic;
attribute keep of dbg_data1 : signal is "true";
attribute keep of dbg_data2 : signal is "true";
attribute keep of dbg_data0 : signal is "true";
attribute keep of dbg_valid0 : signal is "true";
attribute keep of dbg_valid1 : signal is "true";
attribute keep of dbg_valid2 : signal is "true";
--***********************************************************************************
begin
--***********************************************************************************
clk_in <= clk_clkin(13);
clk_out <= clk_clkin(14);
rst <= rst_rstin(2);
-------------------------------------------------------------------------------------
-- Local reset
-------------------------------------------------------------------------------------
process(clk_in)
begin
if rst = '1' then
local_reset <= '1';
elsif rising_edge(clk_in) then
local_reset <= '0';
end if;
end process;
-------------------------------------------------------------------------------------
-- Align Input
-------------------------------------------------------------------------------------
process(clk_in)
begin
if rising_edge(clk_in) then
if force_error(0) = '1' then
align_fifo_in(0) <= (others=>'0');
else
align_fifo_in(0) <= in0_in_data;
end if;
if force_error(1) = '1' then
align_fifo_in(1) <= (others=>'0');
else
align_fifo_in(1) <= in1_in_data;
end if;
if force_error(2) = '1' then
align_fifo_in(2) <= (others=>'0');
else
align_fifo_in(2) <= in2_in_data;
end if;
if force_error(3) = '1' then
align_fifo_in(3) <= (others=>'0');
else
align_fifo_in(3) <= in3_in_data;
end if;
align_fifo_wr_en(0) <= in0_in_dval;
align_fifo_wr_en(1) <= in1_in_dval;
align_fifo_wr_en(2) <= in2_in_dval;
align_fifo_wr_en(3) <= in3_in_dval;
end if;
end process;
in0_in_stop <= '0';
in1_in_stop <= '0';
in2_in_stop <= '0';
in3_in_stop <= '0';
alignment_generate:
for I in 0 to 3 generate
async_fifo_align_64in_out_inst0:
entity work.async_fifo_align_64in_out
port map (
clk => clk_in,
rst => local_reset,
din => align_fifo_in(I),
wr_en => align_fifo_wr_en(I),
rd_en => align_fifo_rd_en,
dout => align_fifo_out(I),
full => open,
empty => align_fifo_empty(I),
valid => align_fifo_valid(I)
);
byte_align0:
entity work.data_align
port map (
clk_in => clk_in,
rst_in => local_reset,
data_in => align_fifo_out(I),
val_in => align_fifo_valid(I),
data_out => byte_align_out(I),
val_out => byte_align_valid(I)
);
-- Data Check
data_check_0:
entity work.data_check
port map (
clk_in => clk_in,
rst_in => check_reset,
data_in => byte_align_out(I),
valid_in => byte_align_valid(I),
check_en_in => check_enable,
status_out => status(I)
);
end generate;
align_fifo_rd_en <= not or_reduce(align_fifo_empty);
-------------------------------------------------------------------------------------------
-- Performance Measure
-------------------------------------------------------------------------------------------
performance_inst0:
entity work.performance
port map(
clk_in => clk_in,
rst_in => perfomance_reset,
start_in => performance_en,
in_val => '0',
out_val => align_fifo_valid(0), --fifo_wr,
in_cnt => input_count, -- out
cycle_cnt => cycle_count, -- out
out_cnt => output_count -- out
);
-------------------------------------------------------------------------------------
-- Capture incomming data
-------------------------------------------------------------------------------------
fifo_generate:
for I in 0 to 3 generate
fifo_64in_out_inst0 : entity work.fifo_64in_out
PORT MAP (
wr_clk => clk_in,
rd_clk => clk_out,
rst => local_reset,
din => align_fifo_in(I),
wr_en => align_fifo_wr_en(I),
rd_en => fifo_rd_en(I),
dout => fifo_out(I),
full => fifo_full(I),
empty => fifo_empty(I),
valid => fifo_valid(I),
rd_data_count => fifo_count(I)
);
end generate;
fifo_rd_en(0) <= (not fifo_empty(0) and not out0_out_stop);
fifo_rd_en(1) <= (not fifo_empty(1) and not out1_out_stop);
fifo_rd_en(2) <= (not fifo_empty(2) and not out2_out_stop);
fifo_rd_en(3) <= (not fifo_empty(3) and not out3_out_stop);
-------------------------------------------------------------------------------------
-- register outputs
-------------------------------------------------------------------------------------
process(clk_out)
begin
if rising_edge(clk_out) then
out0_out_dval <= fifo_valid(0);
out0_out_data <= fifo_out(0);
out1_out_dval <= fifo_valid(1);
out1_out_data <= fifo_out(1);
out2_out_dval <= fifo_valid(2);
out2_out_data <= fifo_out(2);
out3_out_dval <= fifo_valid(3);
out3_out_data <= fifo_out(3);
end if;
end process;
-------------------------------------------------------------------------------------
-- Command Interface
-------------------------------------------------------------------------------------
ip_block_ctrl_inst0: entity work.ip_block_ctrl
generic map (
START_ADDR => private_start_addr_gen,
STOP_ADDR => private_stop_addr_gen
)
port map(
rst => rst,
clk_cmd => clk_out,
in_cmd_val => cmd_in_cmdin_val,
in_cmd => cmd_in_cmdin,
out_cmd_val => cmd_out_cmdout_val,
out_cmd => cmd_out_cmdout,
cmd_busy => open,
reg0 => register0, -- out
reg1 => register1, -- out
reg2 => register2, -- in
reg3 => register3, -- in
reg4 => register4, -- in
reg5 => register5, -- in
reg6 => register6, -- in
reg7 => register7, -- in
reg8 => register8, -- in
mbx_in_reg => (others=>'0'), -- in
mbx_in_val => '0' -- in
);
-- register mapping synth clock domain
process(clk_in)
begin
if rising_edge(clk_in) then
register0_r <= register0;
register1_r <= register1;
check_reset <= register0_r(0);
perfomance_reset <= register0_r(4);
check_enable <= register1_r(0);
performance_en <= register1_r(4);
force_error <= register1_r(11 downto 8);
end if;
end process;
-- register mapping command clock domain
process(clk_out)
begin
if rising_edge(clk_out) then
register2 <= status(3) & status(2) & status(1) & status(0);
register3 <= cycle_count(31 downto 0); -- cycle count LSB
register4 <= output_count(31 downto 0); -- output count LSB
register5 <= cycle_count(63 downto 32); -- cycle count MSB
register6 <= output_count(63 downto 32); -- output count MSB
register7 <= "0001" & fifo_count(1) & "0000" & fifo_count(0);
register8 <= "0011" & fifo_count(3) & "0010" & fifo_count(2);
end if;
end process;
-------------------------------------------------------------------------------------
-- Debug Section
-------------------------------------------------------------------------------------
--ila_inst0 : ila_0
-- PORT MAP (
-- clk => clk_in,
-- probe0 => probe0
-- );
--
--process(clk_in)
--begin
-- if rising_edge(clk_in) then
-- dbg_data0 <= byte_align_out(0);
-- dbg_data1 <= byte_align_out(1);
-- dbg_data2 <= byte_align_out(2);
-- dbg_valid0 <= align_fifo_valid(0);
-- dbg_valid1 <= align_fifo_valid(1);
-- dbg_valid2 <= align_fifo_valid(2);
-- end if;
--end process;
--
--probe0(63 downto 0) <= dbg_data0;
--probe0(127 downto 64) <= dbg_data1;
--probe0(191 downto 128) <= dbg_data2;
--probe0(192) <= dbg_valid0;
--probe0(193) <= dbg_valid1;
--probe0(194) <= dbg_valid2;
--probe0(255 downto 195) <= (others=>'0');
--***********************************************************************************
end architecture bev;
--***********************************************************************************
| mit | 67e277a5b6823d406d680d326500fef2 | 0.469301 | 3.892035 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff01/tb_dff09.vhdl | 1 | 887 | entity tb_dff09 is
end tb_dff09;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff09 is
signal clk : std_logic;
signal rstn : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff09
port map (
q => dout,
d => din,
clk => clk,
rstn => rstn);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rstn <= '0';
wait for 1 ns;
assert dout = '0' severity failure;
rstn <= '1';
din <= '1';
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
rstn <= '0';
wait for 1 ns;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 6d1c361d05cd90e1ce8789ede3c499d3 | 0.554679 | 3.372624 | false | false | false | false |
lfmunoz/vhdl | templates/host_interface/clkrst_vp780_emu.vhd | 1 | 10,234 |
-------------------------------------------------------------------------------------
-- FILE NAME : sip_clkrst_vp780.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_clkrst_vp780
-- architecture - arch_sip_clkrst_vp780
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- sip_clkrst_vp780
-- Notes: sip_clkrst_vp780
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity sip_clkrst_vp780 is
port (
--Wormhole 'cmdclk_in':
cmdclk_in_cmdclk : in std_logic;
--Wormhole 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'clkout':
clkout_clkout : out std_logic_vector(31 downto 0);
--Wormhole 'ext_vp780_clkin' of type 'ext_vp780_clkin':
clk200_n : in std_logic;
clk200_p : in std_logic;
clk300_n : in std_logic;
clk300_p : in std_logic;
aux_clk : in std_logic;
clk_synth_0 : in std_logic;
clk_synth_1 : in std_logic;
--Wormhole 'rst_out':
rst_out_rstout : out std_logic_vector(31 downto 0);
--Wormhole 'ifpga_rst_in':
ifpga_rst_in_ifpga_rst : in std_logic
);
end entity sip_clkrst_vp780;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture arch_sip_clkrst_vp780 of sip_clkrst_vp780 is
-------------------------------------------------------------------------------------
--Constants declaration
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--Signal declaration
-------------------------------------------------------------------------------------
signal clk200M_o :std_logic;
signal clk300M_o :std_logic;
-------------------------------------------------------------------------------------
--components declarations
-------------------------------------------------------------------------------------
component clkrst_vp780 is
generic ( reset_base :integer:=1024);
port
(
clk200_n : in std_logic;
clk200_p : in std_logic;
clk300_n : in std_logic;
clk300_p : in std_logic;
aux_clk : in std_logic;
clk_synth_0 : in std_logic;
clk_synth_1 : in std_logic;
reset_i :in std_logic; --reset complete FPGA
--command if
out_cmd :out std_logic_vector(63 downto 0);
out_cmd_val :out std_logic;
in_cmd :in std_logic_vector(63 downto 0);
in_cmd_val :in std_logic;
cmdclk_in :in std_logic;
--clk outputs
clk200M_o :out std_logic;
clk300M_o :out std_logic;
dly_ready_o :out std_logic;
clk_synth_0o :out std_logic;
clk_synth_90o :out std_logic;
clk_synth_180o :out std_logic;
clk_synth_270o :out std_logic;
clk_synth_D4o :out std_logic;
clk_ddr_0_div2o :out std_logic;
clk_ddr_0o :out std_logic;
clk_ddr_90o :out std_logic;
clk_ddr_180o :out std_logic;
clk_ddr_270o :out std_logic;
clk_ddr_capt_div2 :out std_logic; --the MIG design requires the div2 clock for the resynchronisation path to be gated to allow releasing the iserdes reset while the slow and fast clocks are off
clk_ddr_capt :out std_logic; --the MIG design requires the div2 clock for the resynchronisation path to be gated to allow releasing the iserdes reset while the slow and fast clocks are off
clk_ddr_reset_capt :out std_logic; --the MIG design requires the div2 clock for the resynchronisation path to be gated to allow releasing the iserdes reset while the slow and fast clocks are off
clk_synth_1o :out std_logic;
--reset outputs
reset1_o :out std_logic;
reset2_o :out std_logic;
reset3_o :out std_logic
);
end component;
begin
-------------------------------------------------------------------------------------
--components instantiations
-------------------------------------------------------------------------------------
i_clkrst_vp780:clkrst_vp780
generic map (
reset_base => 2
)
port map
(
clk200_n =>clk200_n,
clk200_p =>clk200_p,
clk300_n =>clk300_n,
clk300_p =>clk300_p,
aux_clk =>aux_clk,
clk_synth_0 =>clk_synth_0,
clk_synth_1 =>clk_synth_1,
reset_i =>ifpga_rst_in_ifpga_rst,
--command if
out_cmd =>cmd_out_cmdout,
out_cmd_val =>cmd_out_cmdout_val,
in_cmd =>cmd_in_cmdin,
in_cmd_val =>cmd_in_cmdin_val,
cmdclk_in =>cmdclk_in_cmdclk,
--clk outputs
clk200M_o =>clk200M_o,
clk300M_o =>clk300M_o,
dly_ready_o =>open,
clk_synth_0o =>clkout_clkout(0),
clk_synth_90o =>clkout_clkout(1),
clk_synth_180o =>clkout_clkout(2),
clk_synth_270o =>clkout_clkout(3),
clk_synth_D4o =>clkout_clkout(4),
clk_ddr_0_div2o =>clkout_clkout(9),
clk_ddr_0o =>clkout_clkout(5),
clk_ddr_90o =>clkout_clkout(6),
clk_ddr_180o =>clkout_clkout(7),
clk_ddr_270o =>clkout_clkout(8),
clk_ddr_capt_div2 =>clkout_clkout(16),
clk_ddr_capt =>clkout_clkout(17),
clk_ddr_reset_capt =>rst_out_rstout(16),
clk_synth_1o =>clkout_clkout(12),
--reset outputs
reset1_o =>rst_out_rstout(0),
reset2_o =>rst_out_rstout(1),
reset3_o =>rst_out_rstout(2)
);
clkout_clkout(10) <=clk200M_o;
clkout_clkout(11) <=clk200M_o; --clock is used for the command clock
clkout_clkout(18) <=clk300M_o;
-------------------------------------------------------------------------------------
--synchronous processes
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--asynchronous processes
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--asynchronous mapping
-------------------------------------------------------------------------------------
rst_out_rstout(31 downto 3) <= (others=>'0');
end architecture arch_sip_clkrst_vp780 ; -- of sip_clkrst_vp780
| mit | 044f4fc410179443928f28138186a737 | 0.410201 | 4.597484 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_ac_xhuff_tbl_bits.vhd | 2 | 1,451 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_xhuff_tbl_bits;
architecture augh of p_jinfo_ac_xhuff_tbl_bits is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 997cd4d41be44cf7d1d20ab336073965 | 0.674707 | 2.856299 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug084/mod5x.vhdl | 1 | 4,418 | library ieee;
use ieee.std_logic_1164.all;
entity mod5x is
generic (
NBITS: natural := 13
);
port (
clk: in std_logic;
dividend: in std_logic_vector (NBITS - 1 downto 0);
load: in std_logic;
remzero: out std_logic
);
end entity;
architecture foo of mod5x is
-- type remains is (r0, r1, r2, r3, r4); -- remainder values
-- type remain_array is array (NBITS downto 0) of remains;
-- signal remaindr: remain_array := (others => r0);
-- type branch is array (remains, bit) of remains;
-- -- Dave Tweeds state transition table:
-- constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
-- r1 => ('0' => r2, '1' => r3),
-- r2 => ('0' => r4, '1' => r0),
-- r3 => ('0' => r1, '1' => r2),
-- r4 => ('0' => r3, '1' => r4)
-- );
signal is_zero: std_logic;
begin
do_ig:
process (dividend)
type remains is (r0, r1, r2, r3, r4); -- remainder values
type remain_array is array (NBITS downto 0) of remains;
variable tbit: bit_vector(NBITS - 1 downto 0);
variable remaind: remain_array := (others => r0);
type branch is array (remains, bit) of remains;
-- Dave Tweeds state transition table:
constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
r1 => ('0' => r2, '1' => r3),
r2 => ('0' => r4, '1' => r0),
r3 => ('0' => r1, '1' => r2),
r4 => ('0' => r3, '1' => r4)
);
begin
do_mod:
for i in NBITS - 1 downto 0 loop
tbit := to_bitvector(dividend);
remaind(i) := br_table(remaind(i + 1),tbit(i));
end loop;
-- remaindr <= remaind; -- all values for waveform display
if remaind(0) = r0 then
is_zero <= '1';
else
is_zero <= '0';
end if;
end process;
remainders:
process (clk)
begin
if rising_edge(clk) then
remzero <= is_zero
;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mod5x_tb is
end entity;
architecture foo of mod5x_tb is
constant NBITS: integer range 0 to 13 := 8;
signal clk: std_logic := '0';
signal dividend: std_logic_vector (NBITS - 1 downto 0);
signal load: std_logic := '0';
signal remzero: std_logic;
signal psample: std_ulogic;
signal sample: std_ulogic;
signal done: boolean;
begin
DUT:
entity work.mod5x
generic map (NBITS)
port map (
clk => clk,
dividend => dividend,
load => load,
remzero => remzero
);
CLOCK:
process
begin
wait for 5 ns;
clk <= not clk;
if done'delayed(30 ns) then
wait;
end if;
end process;
STIMULI:
process
begin
for i in 0 to 2 ** NBITS - 1 loop
wait for 10 ns;
dividend <= std_logic_vector(to_unsigned(i,NBITS));
wait for 10 ns;
load <= '1';
wait for 10 ns;
load <= '0';
end loop;
wait for 15 ns;
done <= true;
wait;
end process;
SAMPLER:
process (clk)
begin
if rising_edge(clk) then
psample <= load;
sample <= psample;
end if;
end process;
MONITOR:
process (sample)
variable i: integer;
variable rem5: integer;
begin
if rising_edge (sample) then
i := to_integer(unsigned(dividend));
rem5 := i mod 5;
if rem5 = 0 and remzero /= '1' then
assert rem5 = 0 and remzero = '1'
report LF & HT &
"i = " & integer'image(i) &
" rem 5 expected " & integer'image(rem5) &
" remzero = " & std_ulogic'image(remzero)
SEVERITY ERROR;
end if;
end if;
end process;
end architecture; | gpl-2.0 | a5fa959b37a44b4d00eb7a53c9ff77ff | 0.453599 | 3.811907 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_15.vhd | 4 | 1,556 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_15.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration computer_structure of computer_system is
for structure
for interface_decoder : decoder_2_to_4
use entity work.decoder_3_to_8(basic)
generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
port map ( s0 => in0, s1 => in1, s2 => '0',
enable => '1',
y0 => out0, y1 => out1, y2 => out2, y3 => out3,
y4 => open, y5 => open, y6 => open, y7 => open );
end for;
-- . . .
end for;
end configuration computer_structure;
| gpl-2.0 | aa544e5c9af8dfe51abc2c28874865e7 | 0.588689 | 3.929293 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue524/spi2apb.vhdl | 1 | 1,885 | library IEEE;
use IEEE.std_logic_1164.all;
entity spi2apb is
port (
-- SPI
signal MISO : in std_logic;
signal MOSI : out std_logic;
signal SCLK : out std_logic;
signal SS_n : out std_logic;
-- APB
signal apb_select : in std_logic;
signal clk : in std_logic;
signal data_in : in std_logic_vector (15 downto 0);
signal data_out : out std_logic_vector (15 downto 0);
signal addr : in std_logic_vector (2 downto 0);
signal read_n : in std_logic;
signal reset_n : in std_logic;
signal write_n : in std_logic
);
end entity spi2apb;
architecture rtl of spi2apb is
type reg_type is record
enabled: std_logic;
sclk: std_logic;
running: std_logic;
continuous: std_logic;
pending: std_logic;
txValid, rxValid: std_logic;
txBuffer, rxBuffer, shift: std_logic_vector(7 downto 0);
end record;
constant reg_reset: reg_type := (
enabled => '0',
sclk => '0',
running => '0',
continuous => '0',
pending => '0',
txValid => '0',
rxValid => '0',
txBuffer => (others => '0'),
shift => (others => '0'),
rxBuffer => (others => '0')
);
signal reg_in, reg_out: reg_type;
begin
MOSI <= reg_out.shift(7);
SCLK <= reg_out.sclk;
SS_n <= not reg_out.enabled;
data_out <= "000000" & (reg_out.running or reg_out.pending) & reg_out.rxValid & reg_out.rxBuffer;
sync: process(clk, reset_n)
begin
if (rising_edge(clk)) then
reg_in <= reg_reset when (reset_n => '0') else reg_out;
end if;
end process;
clocking: process(reg_in)
begin
if (reg_in.running) then
reg_out.sclk <= "0" when reg_in else "1";
end if;
end process;
end;
-- vim: set sw=3 ts=3 sts=3 et sta sr ai si cin cino=>1s(0u0W1s:
| gpl-2.0 | e30aed4603edd11ac5f115b326cf3748 | 0.560743 | 3.157454 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/impl/ip/tmp.srcs/sources_1/ip/doHistStretch_ap_fdiv_14_no_dsp_32/sim/doHistStretch_ap_fdiv_14_no_dsp_32.vhd | 1 | 10,804 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fdiv_14_no_dsp_32;
ARCHITECTURE doHistStretch_ap_fdiv_14_no_dsp_32_arch OF doHistStretch_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fdiv_14_no_dsp_32_arch;
| gpl-3.0 | 46ef136eb68865c658e73ccd0b67a763 | 0.632821 | 3.219309 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth36/tb_bram.vhdl | 1 | 1,056 | entity tb_bram is
end tb_bram;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_bram is
signal clk, we : std_logic;
signal addr : std_logic_vector (8 downto 0);
signal dout : std_logic_vector (7 downto 0);
signal din : std_logic_vector (7 downto 0);
begin
dut: entity work.bram
port map (clk => clk, we => we, addr => addr,
data_in => din, data_out => dout);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
we <= '1';
addr <= "000000001";
din <= x"f1";
pulse;
we <= '0';
pulse;
assert dout = x"f1" severity failure;
we <= '1';
addr <= "000000011";
din <= x"f3";
pulse;
we <= '1';
addr <= "111111111";
din <= x"ff";
pulse;
we <= '0';
addr <= "000000011";
pulse;
assert dout = x"f3" severity failure;
we <= '0';
addr <= "111111111";
pulse;
assert dout = x"ff" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 6ac0caccd112e48b704afaee68603b91 | 0.539773 | 3.310345 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1138/crc_pkg.vhdl | 1 | 1,582 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package crc_pkg is
type crcParam_t is record
selLen : integer;
poly : std_ulogic_vector;
iniVect : std_ulogic_vector;
refIn : boolean;
refOut : boolean;
xorOut : std_ulogic_vector;
end record;
pure function getCrc32Param( stdCrc : string
; datLen : integer
) return crcParam_t;
end crc_pkg;
package body crc_pkg is
pure function getCrc32Param( stdCrc : string
; datLen : integer
) return crcParam_t is
variable crcParam_v : crcParam_t( poly ( 31 downto 0)
, iniVect ( 31 downto 0)
, xorOut ( 31 downto 0) );
begin
if ( "CRC-32/CCITT-FALSE" = stdCrc ) then
crcParam_v.selLen := datLen / 8 ;
crcParam_v.poly := X"04C11DB7" ;
crcParam_v.iniVect := X"FFFFFFFF" ;
crcParam_v.refIn := true ;
crcParam_v.refOut := true ;
crcParam_v.xorOut := X"FFFFFFFF" ;
else
crcParam_v.selLen := datLen / 8 ;
crcParam_v.poly := X"000000AF" ;
crcParam_v.iniVect := X"00000000" ;
crcParam_v.refIn := false ;
crcParam_v.refOut := false ;
crcParam_v.xorOut := X"00000000" ;
assert false report
" Standard crc not implemented Yet."
severity failure;
end if;
return crcParam_v;
end function;
end package body crc_pkg;
| gpl-2.0 | 0c9b674f0603c5ced80703f3c83a85fd | 0.540455 | 3.611872 | false | false | false | false |
nickg/nvc | test/parse/vhdl2008.vhd | 1 | 6,830 | --
-- Grab bag of miscellaneous VHDL-2008 syntax
--
entity vhdl2008 is
end entity;
package genpack is
generic ( x : integer := 5; y : boolean ); -- OK
generic map ( x => 5, y => false ); -- OK
constant c : bit_vector(1 to x) := (1 to x => '1');
end package;
package genpack2 is
generic ( x : integer := 5; y : boolean ); -- OK
function add_x_if_y ( arg : integer ) return integer;
end package;
package body genpack2 is
function add_x_if_y ( arg : integer ) return integer is
begin
if y then
return arg + x;
else
return arg;
end if;
end function;
end package body;
package primary_genpack2 is new work.genpack2 generic map (4, false); -- OK
architecture test of vhdl2008 is
type my_utype is (a, b, c);
type my_utype_vector is array (natural range <>) of my_utype;
function resolved (s : my_utype_vector) return my_utype;
subtype my_type is resolved my_utype;
subtype my_type_vector is (resolved) my_utype_vector; -- OK
type my_logical_vec is array (natural range <>) of bit;
type my_bool is (true, false);
package my_genpack2 is new work.genpack2 generic map (1, true); -- OK
begin
process is
variable b : bit;
variable v : my_logical_vec(1 to 3);
begin
b := or v; -- OK
if or v = '1' then end if; -- OK
b := and v; -- OK
b := xor v; -- OK
b := xnor v; -- OK
b := nand v; -- OK
b := nor v; -- OK
end process;
process is
variable b : bit;
variable v : my_logical_vec(1 to 3);
begin
b := b ?= '1'; -- OK
b := b ?/= '1'; -- OK
b := b ?< '0'; -- OK
b := b ?> '0'; -- OK
b := b ?<= '1'; -- OK
b := b ?>= '1'; -- OK
b := v ?= "101"; -- OK
b := v ?/= "111"; -- OK
end process;
process is
variable b : bit;
variable i : integer;
function "??"(x : integer) return boolean;
begin
if b then end if; -- OK
if b xor '1' then end if; -- OK
while b and '1' loop end loop; -- OK
if i + 1 then end if; -- OK
if now + 1 ns then end if; -- Error
while true loop
exit when b or '1'; -- OK
next when b or '1'; -- OK
end loop;
wait until b xor '0'; -- OK
assert b nor '1'; -- OK
assert ?? 1; -- OK
end process;
/* This is a comment */
/* Comments /* do not nest */
process is
variable x, y : integer;
begin
x := 1 when y > 2 else 5; -- OK
end process;
process is
variable x : string(7 downto 0);
begin
x := 8x"0"; -- OK
x := 6x"a"; -- OK
x := 4x"4"; -- OK
x := 2x"4"; -- Error
x := 0x"5"; -- Error
x := 18x"383fe"; -- OK
x := 0b"0000"; -- OK
x := d"5"; -- OK
x := 5d"25"; -- OK
x := 120d"83298148949012041209428481024019511"; -- Error
x := uo"5"; -- OK
x := 5sb"11"; -- OK
x := 2sb"1111110"; -- OK
x := 2sb"10110101"; -- Error
x := 4x"0f"; -- OK
x := Uo"2C"; -- OK
x := d"C4"; -- Error
x := 8x"-"; -- OK
x := 12d"13"; -- OK
end process;
b2: block is
signal s : integer;
begin
process is
begin
s <= 1 when s < 0 else 5; -- OK
end process;
end block;
process is
type int_vec2 is array (natural range <>) of integer_vector; -- OK
constant a : int_vec2(1 to 3)(1 to 2) := ( -- OK
(1, 2), (3, 4), (5, 6) );
begin
assert a(1)(1) = 1; -- OK
end process;
b3: block is
signal s : integer;
begin
process is
begin
s <= force 1; -- OK
s <= force out 1; -- OK
s <= force in 2; -- OK
s <= release; -- OK
s <= release out; -- OK
end process;
end block;
process is
variable x : bit_vector(1 to 3);
begin
case? x is -- OK
when "010" => null;
when others => null;
end case?;
case? x is
when others => null;
end case; -- Error
case x is
when others => null;
end case ?; -- Error
end process;
b4: block is
procedure foo (x : integer_vector; y : integer) is
variable a : x'subtype; -- OK
variable b : integer'subtype; -- OK
variable c : b4'subtype; -- Error
variable d : x'element; -- OK
variable e : y'element; -- Error
variable f : b4'element; -- Error
begin
end procedure;
begin
end block;
b5: block is
function gen1 generic (n : integer) (x : integer) return integer is
begin -- OK
return 1;
end function;
function gen2 generic (n : integer) -- OK
parameter (x : integer) return integer;
function gen3 generic (type t; p : t) (x : t) return integer; -- Ok
function my_gen1 is new gen1 generic map (5); -- OK
begin
end block;
b6: block is
constant c1 : string := to_string(100); -- OK
begin
end block;
b7: block is
signal s : integer;
signal b : bit;
begin
s <= 1 when b else 2; -- OK
s <= 2 when '1' else 6; -- OK
process is
variable v : integer;
begin
v := 1 when b else 5; -- OK
s <= 5 when b else 7; -- OK
end process;
end block;
g1: if g1a: true generate -- OK
elsif g2: false generate
begin
end g2;
else generate
end generate;
g1: if true generate
end g1; -- Error
else foo: generate
end bar; -- Error
end generate;
end architecture;
| gpl-3.0 | b1f45e8a58b9d7e8572b341868115706 | 0.411859 | 4.072749 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc988.vhd | 4 | 46,773 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc988.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p06n01i00988pkg is
------------------------------------USING ONLY WHITE MATTER---------------------------------
--------------------------------------------------------------------------------------------
---ACCESS TYPE FROM STANDARD PACKAGE
type boolean_ptr is access boolean ; --simple boolean type
type bit_ptr is access bit ; --simple bit type
type char_ptr is access character; --simple character type
type severity_level_ptr is access severity_level; --simple severity type
type integer_ptr is access integer; --simple integer type
type real_ptr is access real; --simple real type
type time_ptr is access time; --simple time type
type natural_ptr is access natural; --simple natural type
type positive_ptr is access positive; --simple positive type
type string_ptr is access string; --simple string type
type bit_vector_ptr is access bit_vector; --simple bit_vector type
--------------------------------------------------------------------------------------------
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
---------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
---------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
---------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
---------------------------------------------------------------------------------------------
--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type s2boolean_vector is array (natural range <>,natural range <>) of boolean;
type s2bit_vector is array (natural range<>,natural range <>) of bit;
type s2char_vector is array (natural range<>,natural range <>) of character;
type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
type s2integer_vector is array (natural range <>,natural range <>) of integer;
type s2real_vector is array (natural range <>,natural range <>) of real;
type s2time_vector is array (natural range <>,natural range <>) of time;
type s2natural_vector is array (natural range <>,natural range <>) of natural;
type s2positive_vector is array (natural range <>,natural range <>) of positive;
----------------------------------------------------------------------------------------------
--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type column is range 1 to 64;
type row is range 1 to 1024;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS FROM STANDARD PACKAGE
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS UNCONSTRAINT ARRAYS
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
-----------------------------------------------------------------------------------------------
type record_of_ptr is record
a:boolean_ptr ; --simple boolean type
b:bit_ptr; --simple bit type
c:char_ptr; --simple character type
e:severity_level_ptr; --simple severity type
f:integer_ptr; --simple integer type
g: real_ptr ; --simple real type
h:time_ptr; --simple time type
i: natural_ptr; --simple natural type
j:positive_ptr; --simple positive type
k: string_ptr; --simple string type
l: bit_vector_ptr; --simple bit_vector type
end record;
-----------------------------------------------------------------------------------------------
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
h: record_of_ptr;
i: record_array_st;
end record;
-----------------------------------------------------------------------------------------------
--ACCESS TYPES FOR ABOVE
-----------------------------------------------------------------------------------------------
type boolean_vector_ptr is access boolean_vector;
type severity_level_vector_ptr is access severity_level_vector;
type integer_vector_ptr is access integer_vector;
type real_vector_ptr is access real_vector;
type time_vector_ptr is access time_vector;
type natural_vector_ptr is access natural_vector;
type positive_vector_ptr is access positive_vector;
-----------------------------------------------------------------------------------------------
type boolean_vector_st_ptr is access boolean_vector_st;--(0 to 15);
type severity_level_vector_st_ptr is access severity_level_vector_st;--(0 to 15);
type integer_vector_st_ptr is access integer_vector_st;--(0 to 15);
type real_vector_st_ptr is access real_vector_st;--(0 to 15);
type time_vector_st_ptr is access time_vector_st;--(0 to 15);
type natural_vector_st_ptr is access natural_vector_st;--(0 to 15);
type positive_vector_st_ptr is access positive_vector_st;--(0 to 15);
-----------------------------------------------------------------------------------------------
type boolean_cons_vector_ptr is access boolean_cons_vector;
type severity_level_cons_vector_ptr is access severity_level_cons_vector;
type integer_cons_vector_ptr is access integer_cons_vector;
type real_cons_vector_ptr is access real_cons_vector;
type time_cons_vector_ptr is access time_cons_vector;
type natural_cons_vector_ptr is access natural_cons_vector;
type positive_cons_vector_ptr is access positive_cons_vector;
-----------------------------------------------------------------------------------------------
type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
type sev_lvl_cons_vecofvec_ptr is access severity_level_cons_vectorofvector;
type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
type real_cons_vectorofvector_ptr is access real_cons_vectorofvector;
type time_cons_vectorofvector_ptr is access time_cons_vectorofvector;
type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
type posi_cons_vecofvec_ptr is access positive_cons_vectorofvector;
-----------------------------------------------------------------------------------------------
type s2boolean_vector_ptr is access s2boolean_vector;
type s2bit_vector_ptr is access s2bit_vector;
type s2char_vector_ptr is access s2char_vector;
type s2severity_level_vector_ptr is access s2severity_level_vector;
type s2integer_vector_ptr is access s2integer_vector;
type s2real_vector_ptr is access s2real_vector;
type s2time_vector_ptr is access s2time_vector;
type s2positive_vector_ptr is access s2positive_vector;
-----------------------------------------------------------------------------------------------
type s2boolean_cons_vector_ptr is access s2boolean_cons_vector;
type s2bit_cons_vector_ptr is access s2bit_cons_vector;
type s2char_cons_vector_ptr is access s2char_cons_vector;
type s2sev_lvl_cons_vec_ptr is access s2severity_level_cons_vector;
type s2integer_cons_vector_ptr is access s2integer_cons_vector;
type s2real_cons_vector_ptr is access s2real_cons_vector;
type s2time_cons_vector_ptr is access s2time_cons_vector;
type s2natural_cons_vector_ptr is access s2natural_cons_vector;
type s2positive_cons_vector_ptr is access s2positive_cons_vector;
----------------------------------------------------------------------------------------------
type record_std_package_ptr is access record_std_package;
type record_cons_array_ptr is access record_cons_array;
type record_2cons_array_ptr is access record_2cons_array;
type record_cons_arrayofarray_ptr is access record_cons_arrayofarray;
type record_of_ptr_ptr is access record_of_ptr;
type record_of_records_ptr is access record_of_records;
type record_array_st_ptr is access record_array_st;
-----------------------------------------------------------------------------------------------
-------------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-----------------------------
type four_value is ('Z','0','1','X'); --enumerated type
type four_value_map is array(four_value) of boolean;
subtype binary is four_value range '0' to '1';
type four_value_vector is array (natural range <>) of four_value; --unconstraint array of
type byte is array(0 to 7) of bit;
subtype word is bit_vector(0 to 15); --constrained array
function resolution(i:in four_value_vector) return four_value; --bus resolution
subtype four_value_state is resolution four_value; --function type
type state_vector is array (natural range <>) of four_value_state; --unconstraint array of
constant size :integer := 63;
type primary_memory is array(0 to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:binary;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
subtype delay is integer range 1 to 10;
type four_value_ptr is access four_value;
type four_value_map_ptr is access four_value_map;
type binary_ptr is access binary;
type four_value_vector_ptr is access four_value_vector; --ennumerated type
type byte_ptr is access byte;
type word_ptr is access word;
type four_value_state_ptr is access four_value_state;
type state_vector_ptr is access state_vector; --type returned by resolu.
type primary_memory_ptr is access primary_memory;
type primary_memory_module_ptr is access primary_memory_module;
type whole_memory_ptr is access whole_memory;
type current_ptr is access current;
type resistance_ptr is access resistance;
type delay_ptr is access delay;
-------------------------------------------------------------------------------------------
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
--constant C33 : s2boolean_vector := ((true,true),(false,false));
--constant C34 : s2bit_vector := ((B"0011"),(B"1100"));
--constant C35 : s2char_vector := (('s','h'),('i','s'));
--constant C36 : s2severity_level_vector := ((note,error),(error,note));
--constant C37 : s2integer_vector := ((1,2,3,4),(4,3,2,1));
--constant C38 : s2real_vector := ((1.0,2.0,3.0,4.0),(4.0,3.0,2.0,1.0));
--constant C39 : s2time_vector := ((1 ns, 2 ns, 3 ns, 4 ns),(1 ns, 2 ns, 3 ns, 4 ns));
--constant C40 : s2positive_vector := ((1,2,3,4),(4,3,2,1));
constant C41 : s2boolean_cons_vector := (others =>(others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others =>(others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others =>(others => C6));
constant C47 : s2time_cons_vector := (others =>(others => C7));
constant C48 : s2natural_cons_vector := (others =>(others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
--constant C54 : record_of_ptr := (NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
--constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
--constant C55 : record_of_records := (C50,C51,C52,C53,C54,C54a);
constant C56 : four_value := 'Z';
constant C57 : four_value_map := (true,true,true,true);
constant C58 : binary := '0';
constant C59 : four_value_vector := ('1','0','1','0');
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C62 : four_value_state := 'Z';
constant C63 : state_vector := ('Z','Z','Z','Z');
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
end c06s03b00x00p06n01i00988pkg;
package body c06s03b00x00p06n01i00988pkg is
function resolution(i:in four_value_vector) return four_value is
variable temp :four_value := 'Z';
begin
return temp;
end;
end c06s03b00x00p06n01i00988pkg;
use work.c06s03b00x00p06n01i00988pkg.all;
ENTITY c06s03b00x00p06n01i00988ent IS
END c06s03b00x00p06n01i00988ent;
ARCHITECTURE c06s03b00x00p06n01i00988arch OF c06s03b00x00p06n01i00988ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean_ptr := new boolean;
variable var2 : bit_ptr := new bit;
variable var3 : char_ptr := new character;
variable var4 : severity_level_ptr := new severity_level;
variable var5 : integer_ptr := new integer;
variable var6 : real_ptr := new real;
variable var7 : time_ptr := new time;
variable var8 : natural_ptr := new natural;
variable var9 : positive_ptr := new positive;
variable var10 : string_ptr := new string(1 to 7);
variable var11 : bit_vector_ptr := new bit_vector(0 to 3);
variable var12 : boolean_vector_ptr := new boolean_vector(0 to 1);
variable var13 : severity_level_vector_ptr := new severity_level_vector(0 to 1);
variable var14 : integer_vector_ptr := new integer_vector(0 to 3);
variable var15 : real_vector_ptr := new real_vector(0 to 3);
variable var16 : time_vector_ptr := new time_vector(0 to 3);
variable var17 : natural_vector_ptr := new natural_vector(0 to 3);
variable var18 : positive_vector_ptr := new positive_vector( 0 to 3);
variable var19 : boolean_cons_vector_ptr := new boolean_cons_vector;
variable var20 : severity_level_cons_vector_ptr := new severity_level_cons_vector;
variable var21 : integer_cons_vector_ptr := new integer_cons_vector;
variable var22 : real_cons_vector_ptr := new real_cons_vector;
variable var23 : time_cons_vector_ptr := new time_cons_vector;
variable var24 : natural_cons_vector_ptr := new natural_cons_vector;
variable var25 : positive_cons_vector_ptr := new positive_cons_vector;
variable var26 : boolean_cons_vectorofvector_ptr := new boolean_cons_vectorofvector;
variable var27 : sev_lvl_cons_vecofvec_ptr := new severity_level_cons_vectorofvector;
variable var28 : integer_cons_vectorofvector_ptr := new integer_cons_vectorofvector;
variable var29 : real_cons_vectorofvector_ptr := new real_cons_vectorofvector;
variable var30 : time_cons_vectorofvector_ptr := new time_cons_vectorofvector;
variable var31 : natural_cons_vectorofvector_ptr := new natural_cons_vectorofvector;
variable var32 : posi_cons_vecofvec_ptr := new positive_cons_vectorofvector;
--variable var33 : s2boolean_vector_ptr := new s2boolean_vector;
--variable var34 : s2bit_vector_ptr := new s2bit_vector;
--variable var35 : s2char_vector_ptr := new s2char_vector;
--variable var36 : s2severity_level_vector_ptr := new s2severity_level_vector;
--variable var37 : s2integer_vector_ptr := new s2integer_vector;
--variable var38 : s2real_vector_ptr := new s2real_vector;
--variable var39 : s2time_vector_ptr := new s2time_vector;
--variable var40 : s2positive_vector_ptr := new s2positive_vector;
variable var41 : s2boolean_cons_vector_ptr := new s2boolean_cons_vector;
variable var42 : s2bit_cons_vector_ptr := new s2bit_cons_vector;
variable var43 : s2char_cons_vector_ptr := new s2char_cons_vector;
variable var44 : s2sev_lvl_cons_vec_ptr := new s2severity_level_cons_vector;
variable var45 : s2integer_cons_vector_ptr := new s2integer_cons_vector;
variable var46 : s2real_cons_vector_ptr := new s2real_cons_vector;
variable var47 : s2time_cons_vector_ptr := new s2time_cons_vector;
variable var48 : s2natural_cons_vector_ptr := new s2natural_cons_vector;
variable var49 : s2positive_cons_vector_ptr := new s2positive_cons_vector;
variable var50 : record_std_package_ptr := new record_std_package;
variable var51 : record_cons_array_ptr := new record_cons_array;
variable var52 : record_2cons_array_ptr := new record_2cons_array;
variable var53 : record_cons_arrayofarray_ptr := new record_cons_arrayofarray;
variable var54 : record_of_ptr_ptr := new record_of_ptr;
variable var55 : record_of_records_ptr := new record_of_records;
variable var56 : four_value_ptr := new four_value;
variable var57 : four_value_map_ptr := new four_value_map;
variable var58 : binary_ptr := new binary;
variable var59 : four_value_vector_ptr := new four_value_vector(0 to 3);
variable var60 : byte_ptr := new byte;
variable var61 : word_ptr := new word;
variable var62 : four_value_state_ptr := new four_value_state;
variable var63 : state_vector_ptr := new state_vector(0 to 3);
variable var64 : primary_memory_ptr := new primary_memory;
variable var65 : primary_memory_module_ptr := new primary_memory_module;
variable var66 : whole_memory_ptr := new whole_memory;
variable var67 : current_ptr := new current;
variable var68 : resistance_ptr := new resistance;
variable var69 : delay_ptr := new delay;
variable var70 : boolean_vector_st_ptr := new boolean_vector_st;
variable var71 : severity_level_vector_st_ptr := new severity_level_vector_st;
variable var72 : integer_vector_st_ptr := new integer_vector_st;
variable var73 : real_vector_st_ptr := new real_vector_st;
variable var74 : time_vector_st_ptr := new time_vector_st;
variable var75 : natural_vector_st_ptr := new natural_vector_st;
variable var76 : positive_vector_st_ptr := new positive_vector_st;
variable var54a : record_array_st_ptr := new record_array_st;
variable vari1 : boolean := C1;
variable vari2 : bit := C2;
variable vari3 : character := C3;
variable vari4 : severity_level := C4;
variable vari5 : integer := C5;
variable vari6 : real := C6;
variable vari7 : time := C7;
variable vari8 : natural := C8;
variable vari9 : positive := C9;
variable vari10 : string(1 to 7) := C10;
variable vari11 : bit_vector(0 to 3):= C11;
variable vari12 : boolean_vector(0 to 1):= C12;
variable vari13 : severity_level_vector(0 to 1) := C13;
variable vari14 : integer_vector(0 to 3) := C14;
variable vari15 : real_vector(0 to 3):= C15;
variable vari16 : time_vector(0 to 3):= C16;
variable vari17 : natural_vector(0 to 3):= C17;
variable vari18 : positive_vector(0 to 3):= C18;
variable vari19 : boolean_cons_vector := C19;
variable vari20 : severity_level_cons_vector := C20;
variable vari21 : integer_cons_vector := C21;
variable vari22 : real_cons_vector := C22;
variable vari23 : time_cons_vector := C23;
variable vari24 : natural_cons_vector := C24;
variable vari25 : positive_cons_vector := C25;
variable vari26 : boolean_cons_vectorofvector := C26;
variable vari27 : severity_level_cons_vectorofvector := C27;
variable vari28 : integer_cons_vectorofvector := C28;
variable vari29 : real_cons_vectorofvector := C29;
variable vari30 : time_cons_vectorofvector := C30;
variable vari31 : natural_cons_vectorofvector := C31;
variable vari32 : positive_cons_vectorofvector := C32;
--variable vari33 : s2boolean_vector := C33;
--variable vari34 : s2bit_vector := C34;
--variable vari35 : s2char_vector := C35;
--variable vari36 : s2severity_level_vector := C36;
--variable vari37 : s2integer_vector := C37;
--variable vari38 : s2real_vector := C38;
--variable vari39 : s2time_vector := C39;
--variable vari40 : s2positive_vector := C40;
variable vari41 : s2boolean_cons_vector := C41;
variable vari42 : s2bit_cons_vector := C42;
variable vari43 : s2char_cons_vector := C43;
variable vari44 : s2severity_level_cons_vector := C44;
variable vari45 : s2integer_cons_vector := C45;
variable vari46 : s2real_cons_vector := C46;
variable vari47 : s2time_cons_vector := C47;
variable vari48 : s2natural_cons_vector := C48;
variable vari49 : s2positive_cons_vector := C49;
variable vari50 : record_std_package := C50;
variable vari51 : record_cons_array := C51;
variable vari52 : record_2cons_array := C52;
variable vari53 : record_cons_arrayofarray := C53;
--variable vari54 : record_of_ptr := C54;
--variable vari55 : record_of_records := C55;
variable vari56 : four_value := C56;
variable vari57 : four_value_map := C57;
variable vari58 : binary := C58;
variable vari59 : four_value_vector(0 to 3):= C59;
variable vari60 : byte := C60;
variable vari61 : word := C61;
variable vari62 : four_value_state := C62;
variable vari63 : state_vector(0 to 3):= C63;
variable vari64 : primary_memory := C64;
variable vari65 : primary_memory_module := C65;
variable vari66 : whole_memory := C66;
variable vari67 : current := C67;
variable vari68 : resistance := C68;
variable vari69 : delay := C69;
variable vari70 : boolean_vector_st := C70;
variable vari71 : severity_level_vector_st := C71;
variable vari72 : integer_vector_st := C72;
variable vari73 : real_vector_st := C73;
variable vari74 : time_vector_st := C74;
variable vari75 : natural_vector_st := C75;
variable vari76 : positive_vector_st := C76;
--variable vari54a : record_array_st := C54a;
BEGIN
var1.all := vari1;
var2.all := vari2;
var3.all := vari3;
var4.all := vari4;
var5.all := vari5;
var6.all := vari6;
var7.all := vari7;
var8.all := vari8;
var9.all := vari9;
var10.all := vari10;
var11.all := vari11;
var12.all := vari12;
var13.all := vari13;
var14.all := vari14;
var15.all := vari15;
var16.all := vari16;
var17.all := vari17;
var18.all := vari18;
var19.all := vari19;
var20.all := vari20;
var21.all := vari21;
var22.all := vari22;
var23.all := vari23;
var24.all := vari24;
var25.all := vari25;
var26.all := vari26;
var27.all := vari27;
var28.all := vari28;
var29.all := vari29;
var30.all := vari30;
var31.all := vari31;
var32.all := vari32;
--var33.all := vari33;
--var34.all := vari34;
--var35.all := vari35;
--var36.all := vari36;
--var37.all := vari37;
--var38.all := vari38;
--var39.all := vari39;
--var40.all := vari40;
var41.all := vari41;
var42.all := vari42;
var43.all := vari43;
var44.all := vari44;
var45.all := vari45;
var46.all := vari46;
var47.all := vari47;
var48.all := vari48;
var49.all := vari49;
var50.all := vari50;
var51.all := vari51;
var52.all := vari52;
var53.all := vari53;
--var54.all := vari54;
--var55.all := vari55;
var56.all := vari56;
var57.all := vari57;
var58.all := vari58;
var59.all := vari59;
var60.all := vari60;
var61.all := vari61;
var62.all := vari62;
var63.all := vari63;
var64.all := vari64;
var65.all := vari65;
var66.all := vari66;
var67.all := vari67;
var68.all := vari68;
var69.all := vari69;
var70.all := vari70;
var71.all := vari71;
var72.all := vari72;
var73.all := vari73;
var74.all := vari74;
var75.all := vari75;
var76.all := vari76;
--var54a.all := vari54a;
ASSERT var1.all = C1 REPORT "Improper Assignment of var1" SEVERITY FAILURE;
ASSERT var2.all = C2 REPORT "Improper Assignment of var2" SEVERITY FAILURE;
ASSERT var3.all = C3 REPORT "Improper Assignment of var3" SEVERITY FAILURE;
ASSERT var4.all = C4 REPORT "Improper Assignment of var4" SEVERITY FAILURE;
ASSERT var5.all = C5 REPORT "Improper Assignment of var5" SEVERITY FAILURE;
ASSERT var6.all = C6 REPORT "Improper Assignment of var6" SEVERITY FAILURE;
ASSERT var7.all = C7 REPORT "Improper Assignment of var7" SEVERITY FAILURE;
ASSERT var8.all = C8 REPORT "Improper Assignment of var8" SEVERITY FAILURE;
ASSERT var9.all = C9 REPORT "Improper Assignment of var9" SEVERITY FAILURE;
ASSERT var10.all = C10 REPORT "Improper Assignment of var10" SEVERITY FAILURE;
ASSERT var11.all = C11 REPORT "Improper Assignment of var11" SEVERITY FAILURE;
ASSERT var12.all = C12 REPORT "Improper Assignment of var12" SEVERITY FAILURE;
ASSERT var13.all = C13 REPORT "Improper Assignment of var13" SEVERITY FAILURE;
ASSERT var14.all = C14 REPORT "Improper Assignment of var14" SEVERITY FAILURE;
ASSERT var15.all = C15 REPORT "Improper Assignment of var15" SEVERITY FAILURE;
ASSERT var16.all = C16 REPORT "Improper Assignment of var16" SEVERITY FAILURE;
ASSERT var17.all = C17 REPORT "Improper Assignment of var17" SEVERITY FAILURE;
ASSERT var18.all = C18 REPORT "Improper Assignment of var18" SEVERITY FAILURE;
ASSERT var19.all = C19 REPORT "Improper Assignment of var19" SEVERITY FAILURE;
ASSERT var20.all = C20 REPORT "Improper Assignment of var20" SEVERITY FAILURE;
ASSERT var21.all = C21 REPORT "Improper Assignment of var21" SEVERITY FAILURE;
ASSERT var22.all = C22 REPORT "Improper Assignment of var22" SEVERITY FAILURE;
ASSERT var23.all = C23 REPORT "Improper Assignment of var23" SEVERITY FAILURE;
ASSERT var24.all = C24 REPORT "Improper Assignment of var24" SEVERITY FAILURE;
ASSERT var25.all = C25 REPORT "Improper Assignment of var25" SEVERITY FAILURE;
ASSERT var26.all = C26 REPORT "Improper Assignment of var26" SEVERITY FAILURE;
ASSERT var27.all = C27 REPORT "Improper Assignment of var27" SEVERITY FAILURE;
ASSERT var28.all = C28 REPORT "Improper Assignment of var28" SEVERITY FAILURE;
ASSERT var29.all = C29 REPORT "Improper Assignment of var29" SEVERITY FAILURE;
ASSERT var30.all = C30 REPORT "Improper Assignment of var30" SEVERITY FAILURE;
ASSERT var31.all = C31 REPORT "Improper Assignment of var31" SEVERITY FAILURE;
ASSERT var32.all = C32 REPORT "Improper Assignment of var32" SEVERITY FAILURE;
--ASSERT var33.all = C33 REPORT "Improper Assignment of var33" SEVERITY FAILURE;
--ASSERT var34.all = C34 REPORT "Improper Assignment of var34" SEVERITY FAILURE;
--ASSERT var35.all = C35 REPORT "Improper Assignment of var35" SEVERITY FAILURE;
--ASSERT var36.all = C36 REPORT "Improper Assignment of var36" SEVERITY FAILURE;
--ASSERT var37.all = C37 REPORT "Improper Assignment of var37" SEVERITY FAILURE;
--ASSERT var38.all = C38 REPORT "Improper Assignment of var38" SEVERITY FAILURE;
--ASSERT var39.all = C39 REPORT "Improper Assignment of var39" SEVERITY FAILURE;
--ASSERT var40.all = C40 REPORT "Improper Assignment of var40" SEVERITY FAILURE;
ASSERT var41.all = C41 REPORT "Improper Assignment of var41" SEVERITY FAILURE;
ASSERT var42.all = C42 REPORT "Improper Assignment of var42" SEVERITY FAILURE;
ASSERT var43.all = C43 REPORT "Improper Assignment of var43" SEVERITY FAILURE;
ASSERT var44.all = C44 REPORT "Improper Assignment of var44" SEVERITY FAILURE;
ASSERT var45.all = C45 REPORT "Improper Assignment of var45" SEVERITY FAILURE;
ASSERT var46.all = C46 REPORT "Improper Assignment of var46" SEVERITY FAILURE;
ASSERT var47.all = C47 REPORT "Improper Assignment of var47" SEVERITY FAILURE;
ASSERT var48.all = C48 REPORT "Improper Assignment of var48" SEVERITY FAILURE;
ASSERT var49.all = C49 REPORT "Improper Assignment of var49" SEVERITY FAILURE;
ASSERT var50.all = C50 REPORT "Improper Assignment of var50" SEVERITY FAILURE;
ASSERT var51.all = C51 REPORT "Improper Assignment of var51" SEVERITY FAILURE;
ASSERT var52.all = C52 REPORT "Improper Assignment of var52" SEVERITY FAILURE;
ASSERT var53.all = C53 REPORT "Improper Assignment of var53" SEVERITY FAILURE;
--ASSERT var54.all = C54 REPORT "Improper Assignment of var54" SEVERITY FAILURE;
--ASSERT var54a.all = C54a REPORT "Improper Assignment of var54a" SEVERITY FAILURE;
--ASSERT var55.all = C55 REPORT "Improper Assignment of var55" SEVERITY FAILURE;
ASSERT var56.all = C56 REPORT "Improper Assignment of var56" SEVERITY FAILURE;
ASSERT var57.all = C57 REPORT "Improper Assignment of var57" SEVERITY FAILURE;
ASSERT var58.all = C58 REPORT "Improper Assignment of var58" SEVERITY FAILURE;
ASSERT var59.all = C59 REPORT "Improper Assignment of var59" SEVERITY FAILURE;
ASSERT var60.all = C60 REPORT "Improper Assignment of var60" SEVERITY FAILURE;
ASSERT var61.all = C61 REPORT "Improper Assignment of var61" SEVERITY FAILURE;
ASSERT var62.all = C62 REPORT "Improper Assignment of var62" SEVERITY FAILURE;
ASSERT var63.all = C63 REPORT "Improper Assignment of var63" SEVERITY FAILURE;
ASSERT var64.all = C64 REPORT "Improper Assignment of var64" SEVERITY FAILURE;
ASSERT var65.all = C65 REPORT "Improper Assignment of var65" SEVERITY FAILURE;
ASSERT var66.all = C66 REPORT "Improper Assignment of var66" SEVERITY FAILURE;
ASSERT var67.all = C67 REPORT "Improper Assignment of var67" SEVERITY FAILURE;
ASSERT var68.all = C68 REPORT "Improper Assignment of var68" SEVERITY FAILURE;
ASSERT var69.all = C69 REPORT "Improper Assignment of var69" SEVERITY FAILURE;
ASSERT var70.all = C70 REPORT "Improper Assignment of var70" SEVERITY FAILURE;
ASSERT var71.all = C71 REPORT "Improper Assignment of var71" SEVERITY FAILURE;
ASSERT var72.all = C72 REPORT "Improper Assignment of var72" SEVERITY FAILURE;
ASSERT var73.all = C73 REPORT "Improper Assignment of var73" SEVERITY FAILURE;
ASSERT var74.all = C74 REPORT "Improper Assignment of var74" SEVERITY FAILURE;
ASSERT var75.all = C75 REPORT "Improper Assignment of var75" SEVERITY FAILURE;
ASSERT var76.all = C76 REPORT "Improper Assignment of var76" SEVERITY FAILURE;
assert NOT( var1.all = C1 and
var2.all = C2 and
var3.all = C3 and
var4.all = C4 and
var5.all = C5 and
var6.all = C6 and
var7.all = C7 and
var8.all = C8 and
var9.all = C9 and
var10.all = C10 and
var11.all = C11 and
var12.all = C12 and
var13.all = C13 and
var14.all = C14 and
var15.all = C15 and
var16.all = C16 and
var17.all = C17 and
var18.all = C18 and
var19.all = C19 and
var20.all = C20 and
var21.all = C21 and
var22.all = C22 and
var23.all = C23 and
var24.all = C24 and
var25.all = C25 and
var26.all = C26 and
var27.all = C27 and
var28.all = C28 and
var29.all = C29 and
var30.all = C30 and
var31.all = C31 and
var32.all = C32 and
-- var33.all = C33 and
-- var34.all = C34 and
-- var35.all = C35 and
-- var36.all = C36 and
-- var37.all = C37 and
-- var38.all = C38 and
-- var39.all = C39 and
-- var40.all = C40 and
var41.all = C41 and
var42.all = C42 and
var43.all = C43 and
var44.all = C44 and
var45.all = C45 and
var46.all = C46 and
var47.all = C47 and
var48.all = C48 and
var49.all = C49 and
var50.all = C50 and
var51.all = C51 and
var52.all = C52 and
var53.all = C53 and
-- var54.all = C54 and
-- var54a.all = C54a and
-- var55.all = C55 and
var56.all = C56 and
var57.all = C57 and
var58.all = C58 and
var59.all = C59 and
var60.all = C60 and
var61.all = C61 and
var62.all = C62 and
var63.all = C63 and
var64.all = C64 and
var65.all = C65 and
var66.all = C66 and
var67.all = C67 and
var68.all = C68 and
var69.all = C69 and
var70.all = C70 and
var71.all = C71 and
var72.all = C72 and
var73.all = C73 and
var74.all = C74 and
var75.all = C75 and
var76.all = C76 )
report "***PASSED TEST: c06s03b00x00p06n01i00988"
severity NOTE;
assert ( var1.all = C1 and
var2.all = C2 and
var3.all = C3 and
var4.all = C4 and
var5.all = C5 and
var6.all = C6 and
var7.all = C7 and
var8.all = C8 and
var9.all = C9 and
var10.all = C10 and
var11.all = C11 and
var12.all = C12 and
var13.all = C13 and
var14.all = C14 and
var15.all = C15 and
var16.all = C16 and
var17.all = C17 and
var18.all = C18 and
var19.all = C19 and
var20.all = C20 and
var21.all = C21 and
var22.all = C22 and
var23.all = C23 and
var24.all = C24 and
var25.all = C25 and
var26.all = C26 and
var27.all = C27 and
var28.all = C28 and
var29.all = C29 and
var30.all = C30 and
var31.all = C31 and
var32.all = C32 and
-- var33.all = C33 and
-- var34.all = C34 and
-- var35.all = C35 and
-- var36.all = C36 and
-- var37.all = C37 and
-- var38.all = C38 and
-- var39.all = C39 and
-- var40.all = C40 and
var41.all = C41 and
var42.all = C42 and
var43.all = C43 and
var44.all = C44 and
var45.all = C45 and
var46.all = C46 and
var47.all = C47 and
var48.all = C48 and
var49.all = C49 and
var50.all = C50 and
var51.all = C51 and
var52.all = C52 and
var53.all = C53 and
-- var54.all = C54 and
-- var54a.all = C54a and
-- var55.all = C55 and
var56.all = C56 and
var57.all = C57 and
var58.all = C58 and
var59.all = C59 and
var60.all = C60 and
var61.all = C61 and
var62.all = C62 and
var63.all = C63 and
var64.all = C64 and
var65.all = C65 and
var66.all = C66 and
var67.all = C67 and
var68.all = C68 and
var69.all = C69 and
var70.all = C70 and
var71.all = C71 and
var72.all = C72 and
var73.all = C73 and
var74.all = C74 and
var75.all = C75 and
var76.all = C76 )
report "***FAILED TEST: c06s03b00x00p06n01i00988 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00988arch;
| gpl-2.0 | ce5f88019075ed1bf118e09c8429ed4d | 0.578261 | 3.871296 | false | false | false | false |
nickg/nvc | test/regress/agg9.vhd | 1 | 546 | entity agg9 is
end entity;
architecture test of agg9 is
type rec is record
x, y : natural;
end record;
type rec_array is array (natural range <>) of rec;
signal s : rec_array(1 to 2);
signal r1, r2 : rec;
begin
s <= (1 => r1, 2 => r2);
process is
begin
assert s = ((0, 0), (0, 0));
r2 <= (2, 4);
wait for 1 ns;
assert s = ((0, 0), (2, 4));
r1.x <= 7;
wait for 1 ns;
assert s = ((7, 0), (2, 4));
wait;
end process;
end architecture;
| gpl-3.0 | 7f08e50fa074ff6f982fe9aa7fabd834 | 0.479853 | 3.156069 | false | false | false | false |
nickg/nvc | test/regress/record13.vhd | 1 | 1,136 | entity record13 is
end entity;
architecture test of record13 is
type rec is record
t : character;
-- Three bytes padding
x, y : integer;
end record;
type rec_array is array (positive range <>) of rec;
function resolve(x : rec_array) return rec is
variable r : rec := ('0', 0, 0);
begin
assert x'left = 1;
assert x'right = x'length;
for i in x'range loop
report "x(" & integer'image(i) & ") = (" & integer'image(x(i).x)
& ", " & integer'image(x(i).y) & ")";
r.x := r.x + x(i).x;
r.y := r.y + x(i).y;
end loop;
return r;
end function;
subtype resolved_rec is resolve rec;
signal sig : resolved_rec := ('0', 0, 0);
begin
p1: process is
begin
sig <= ('a', 1, 2);
wait for 1 ns;
sig.x <= 5;
wait;
end process;
p2: process is
begin
sig <= ('b', 4, 5);
wait for 1 ns;
assert sig = ('0', 5, 7);
wait for 1 ns;
assert sig = ('0', 9, 7);
wait;
end process;
end architecture;
| gpl-3.0 | 4fb8b5b979c3bc74b6b79947bf4f1b6a | 0.479754 | 3.495385 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug077/repro6.vhdl | 1 | 545 | entity repro6 is
end repro6;
architecture behav of repro6 is
type my_rec is record
a : bit;
w : bit_vector (1 to 3);
end record;
procedure check (signal v : my_rec) is
begin
assert v.a = '0' and v.w = "001";
end check;
procedure pack (signal a : bit; signal w : bit_vector) is
begin
check (v.a => a,
v.w => w);
end pack;
signal sa : bit;
signal sw : bit_vector (1 to 2);
begin
process
begin
sa <= '0';
sw <= "01";
wait for 0 ns;
pack (sa, sw);
wait;
end process;
end;
| gpl-2.0 | 4269b533a8e9d7c2b065127361060933 | 0.563303 | 3.061798 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_comps_info_h_samp_factor.vhd | 2 | 1,518 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_h_samp_factor is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end p_jinfo_comps_info_h_samp_factor;
architecture augh of p_jinfo_comps_info_h_samp_factor is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-');
end architecture;
| gpl-2.0 | 09667bf439508879fd2d820aa489fb49 | 0.673913 | 2.858757 | false | false | false | false |
nickg/nvc | test/regress/issue407.vhd | 1 | 1,363 | PACKAGE ecc_top_pkg is
constant engnum : integer:=8;
subtype engrange is integer range 0 to engnum-1;
type bit_array is array(engrange) of bit;
type byte_array is array(engrange) of bit_vector(7 downto 0);
END PACKAGE;
entity issue407 is
end entity;
use work.ecc_top_pkg.all;
architecture test of issue407 is
type mode_t is (RDBMG, C2ENC, C2DEC, C1DEC, WRBMG);
type mode_arr_t is array (natural range <>) of mode_t;
constant ECC_RD_DATA_VAL : bit := '1';
signal buf_ce : bit_vector(engrange);
signal bufmode : mode_arr_t(0 to 0);
signal index : natural := 0;
signal c2enc_ce, c2dec_ce, c1dec_ce : bit_vector(engrange);
signal task4_ce : bit := '1';
begin
ce: with bufmode(index) select buf_ce <=
(engrange => ECC_RD_DATA_VAL) WHEN RDBMG, -- Line 412
c2enc_ce when C2ENC,
c2dec_ce WHEN C2DEC,
c1dec_ce WHEN C1DEC,
(engrange => task4_ce) WHEN WRBMG, -- Line 416
(engrange => '0') WHEN others; -- Line 417
stim: process is
begin
bufmode(0) <= C2DEC;
wait for 1 ns;
assert buf_ce = X"00";
bufmode(0) <= RDBMG;
wait for 1 ns;
assert buf_ce = X"FF";
bufmode(0) <= WRBMG;
task4_ce <= '0';
wait for 1 ns;
assert buf_ce = X"00";
wait;
end process;
end architecture;
| gpl-3.0 | 131abc56ae0a7570221dd108843108b3 | 0.595745 | 3.097727 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/switch_dig.vhd | 4 | 1,752 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity switch_dig is
generic ( r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
trans_time : real := 1.0e-9 );
port ( sw_state : in std_logic;
terminal p1, p2 : electrical );
end entity switch_dig;
----------------------------------------------------------------
architecture linear of switch_dig is
signal r_sig : resistance := r_open;
quantity v across i through p1 to p2;
quantity r : resistance;
begin
-- detect switch state and assign resistance value to r_sig
DetectState: process (sw_state)
begin
if (sw_state'event and sw_state = '0') then
r_sig <= r_open;
elsif (sw_state'event and sw_state = '1') then
r_sig <= r_closed;
end if;
end process DetectState;
r == r_sig'ramp(trans_time, trans_time);
v == r * i;
end architecture linear;
| gpl-2.0 | 243f4c09cf8a94a1c8f993ea62dd1779 | 0.664384 | 3.816993 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc645.vhd | 4 | 3,213 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc645.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:52 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:17 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:30 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00645ent IS
END c03s04b01x00p01n01i00645ent;
ARCHITECTURE c03s04b01x00p01n01i00645arch OF c03s04b01x00p01n01i00645ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C1 : boolean := true;
constant C2 : boolean_vector_range := (others => C1);
type boolean_vector_range_file is file of boolean_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : boolean_vector_range_file open read_mode is "iofile.46";
variable v : boolean_vector_range;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C2) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00645"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00645 - File reading operation (boolean_vector_range_file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00645arch;
| gpl-2.0 | 1663cad7cbb6bcc87f02254847913a57 | 0.556489 | 3.966667 | false | true | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0_inst.vhd | 1 | 4,657 | component ghrd_10as066n2_mm_bridge_0 is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in std_logic := 'X'; -- clk
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount
m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata
m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address
m0_write : out std_logic; -- write
m0_read : out std_logic; -- read
m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
reset : in std_logic := 'X'; -- reset
s0_waitrequest : out std_logic; -- waitrequest
s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata
s0_readdatavalid : out std_logic; -- readdatavalid
s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount
s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata
s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address
s0_write : in std_logic := 'X'; -- write
s0_read : in std_logic := 'X'; -- read
s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
s0_debugaccess : in std_logic := 'X' -- debugaccess
);
end component ghrd_10as066n2_mm_bridge_0;
u0 : component ghrd_10as066n2_mm_bridge_0
generic map (
DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH,
SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH,
HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH,
BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH,
PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND,
PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE
)
port map (
clk => CONNECTED_TO_clk, -- clk.clk
m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest
m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata
m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid
m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount
m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata
m0_address => CONNECTED_TO_m0_address, -- .address
m0_write => CONNECTED_TO_m0_write, -- .write
m0_read => CONNECTED_TO_m0_read, -- .read
m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable
m0_debugaccess => CONNECTED_TO_m0_debugaccess, -- .debugaccess
reset => CONNECTED_TO_reset, -- reset.reset
s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest
s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata
s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid
s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount
s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata
s0_address => CONNECTED_TO_s0_address, -- .address
s0_write => CONNECTED_TO_s0_write, -- .write
s0_read => CONNECTED_TO_s0_read, -- .read
s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable
s0_debugaccess => CONNECTED_TO_s0_debugaccess -- .debugaccess
);
| mit | 38cd666a2353d035a21506a70135b522 | 0.49388 | 3.755645 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xbip_dsp48_addsub_v3_0_2/xbip_dsp48_addsub_v3_0.vhd | 9 | 10,812 | `protect begin_protected
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NNB6YNS2qBtgC7pRLZtxQxYeWrGzsDbtlGOWw9HNFlThjNK0xThgAoiaC7YS5zULc/db0VC8U9oc
+RrFn9NKxiyxI1QMlGRrn81iabS9P8zUq+QSyEutil+lsAcxa/Z1pqbUgmUDYPqphvlzwLy/F3oA
4btcgtRdfrxepVaQFGsraTBJ+iyP0zA6Z2txdSHQS3aoZHwkIesFleVp6Th7miwNPH7uGkCbaJAR
4MOnAReIq3j0jdHQrAC8cGZT54tE3vUpBjZpJlKX0aEUD2ofrX9tJmDVIZd8VQVB3fVIZDsnBZa/
4Bx933Gv8JUjPgEFKuM0URO3e7/1W29kK4TwenYqRfdGcjrqBroc42s29H18K9Xhbmy+Rf3MAGWf
zE6KFRMHZYkXNsDK+a/e2IFzDKGfdoJ4eeg7qNEkRz04Bn81JD9yVs4th1Q1vn+EdjhsR2TWfpbc
2zpWgcYQ7zGMuUHdieTedQmq4ps8BKIaJB7v9BxvisVxc+yCfGxpfT8U21sLfyfWCR/D6fkqZ7nP
01VNXJPEQQzTcj7dGprgYCWe98pNDXlkdT1LzckfqSYyuabd2jaZ67iCo/nuhyr3/sPOuS+bpF0k
xfE2f4DWWdFtEOoTQZANq6JaWWtzkau3F1KvL9xxfh4wOzKiAodRHuqtXMEko2pQoCmL/3H8NqiM
/ribgK7hbXBeXAvxIAcs31MWH/DkY9pRvpWA8/dY/qzbkopErNlutYKqUh782AteK2kWi4mNUeW+
sw==
`protect end_protected
| gpl-3.0 | ab2160d1b4431f330e0fe75acf6dff74 | 0.922863 | 1.936246 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/syn/vhdl/doHistStretch.vhd | 5 | 88,596 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity doHistStretch is
generic (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TKEEP : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TUSER : IN STD_LOGIC_VECTOR (1 downto 0);
inStream_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TID : IN STD_LOGIC_VECTOR (4 downto 0);
inStream_TDEST : IN STD_LOGIC_VECTOR (5 downto 0);
outStream_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TKEEP : OUT STD_LOGIC_VECTOR (0 downto 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR (0 downto 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
outStream_TID : OUT STD_LOGIC_VECTOR (4 downto 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR (5 downto 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_DATA_WIDTH-1 downto 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_DATA_WIDTH/8-1 downto 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_DATA_WIDTH-1 downto 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of doHistStretch is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"doHistStretch,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.133000,HLS_SYN_LAT=262177,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=3,HLS_SYN_FF=1532,HLS_SYN_LUT=2319}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (8 downto 0) := "000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (8 downto 0) := "000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (8 downto 0) := "001000000";
constant ap_ST_pp0_stg0_fsm_7 : STD_LOGIC_VECTOR (8 downto 0) := "010000000";
constant ap_ST_st35_fsm_8 : STD_LOGIC_VECTOR (8 downto 0) := "100000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv19_0 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000000";
constant ap_const_lv32_437F0000 : STD_LOGIC_VECTOR (31 downto 0) := "01000011011111110000000000000000";
constant ap_const_lv19_40000 : STD_LOGIC_VECTOR (18 downto 0) := "1000000000000000000";
constant ap_const_lv19_1 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000001";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv9_181 : STD_LOGIC_VECTOR (8 downto 0) := "110000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv8_7F : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_26 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal xMin : STD_LOGIC_VECTOR (7 downto 0);
signal xMax : STD_LOGIC_VECTOR (7 downto 0);
signal inStream_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_pp0_stg0_fsm_7 : STD_LOGIC;
signal ap_sig_59 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it19 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it20 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it21 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it22 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it23 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it24 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it25 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it26 : STD_LOGIC := '0';
signal exitcond_fu_197_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal outStream_TDATA_blk_n : STD_LOGIC;
signal exitcond_reg_394 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter25 : STD_LOGIC_VECTOR (0 downto 0);
signal idxPixel_reg_157 : STD_LOGIC_VECTOR (18 downto 0);
signal xMax_read_reg_369 : STD_LOGIC_VECTOR (7 downto 0);
signal xMin_read_reg_374 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_cast_fu_180_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_cast_reg_379 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_177 : BOOLEAN;
signal xMax_minus_xMin6_fu_192_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal xMax_minus_xMin_reg_389 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_188 : BOOLEAN;
signal ap_sig_192 : BOOLEAN;
signal ap_sig_ioackin_outStream_TREADY : STD_LOGIC;
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_reg_394_pp0_iter24 : STD_LOGIC_VECTOR (0 downto 0);
signal idxPixel_1_fu_203_p2 : STD_LOGIC_VECTOR (18 downto 0);
signal tmp_keep_V_reg_403 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter25 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_strb_V_reg_408 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter25 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_user_V_reg_413 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter2 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter3 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter4 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter5 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter6 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter7 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter8 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter9 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter10 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter11 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter12 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter13 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter14 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter15 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter16 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter17 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter18 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter19 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter20 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter21 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter22 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter23 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter24 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter25 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_last_V_reg_418 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter25 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_id_V_reg_423 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter2 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter3 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter4 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter5 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter6 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter7 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter8 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter9 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter10 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter11 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter12 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter13 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter14 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter15 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter16 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter17 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter18 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter19 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter20 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter21 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter22 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter23 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter24 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter25 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_dest_V_reg_428 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter1 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter2 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter3 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter4 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter5 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter6 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter7 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter8 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter9 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter10 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter11 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter12 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter13 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter14 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter15 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter16 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter17 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter18 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter19 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter20 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter21 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter22 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter23 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter24 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter25 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_s_fu_246_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_reg_438 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_173_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_443 : STD_LOGIC_VECTOR (31 downto 0);
signal loc_V_reg_448 : STD_LOGIC_VECTOR (7 downto 0);
signal loc_V_1_fu_265_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal loc_V_1_reg_454 : STD_LOGIC_VECTOR (22 downto 0);
signal ap_reg_ioackin_outStream_TREADY : STD_LOGIC := '0';
signal grp_fu_177_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_cast_6_fu_183_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_1_fu_186_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_3_cast_fu_237_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_4_fu_241_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_168_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_s_fu_251_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Result_s_fu_269_p3 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_i_i_i_cast1_fu_280_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_fu_283_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_4_i_i_fu_297_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal isNeg_fu_289_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_i_i_cast_fu_302_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_1_fu_306_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_1_cast_fu_314_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_1_cast_cast_fu_318_p1 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_2_i_i_fu_276_p1 : STD_LOGIC_VECTOR (53 downto 0);
signal tmp_6_i_i_fu_322_p1 : STD_LOGIC_VECTOR (53 downto 0);
signal tmp_7_i_i_fu_326_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_9_fu_338_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_i_i_fu_332_p2 : STD_LOGIC_VECTOR (53 downto 0);
signal tmp_fu_346_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_3_fu_350_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_168_ce : STD_LOGIC;
signal grp_fu_173_ce : STD_LOGIC;
signal grp_fu_177_ce : STD_LOGIC;
signal ap_sig_cseq_ST_st35_fsm_8 : STD_LOGIC;
signal ap_sig_702 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (8 downto 0);
component doHistStretch_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component doHistStretch_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component doHistStretch_sitofp_32s_32_6 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component doHistStretch_CTRL_BUS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
xMin : OUT STD_LOGIC_VECTOR (7 downto 0);
xMax : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
doHistStretch_CTRL_BUS_s_axi_U : component doHistStretch_CTRL_BUS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_BUS_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_BUS_DATA_WIDTH)
port map (
AWVALID => s_axi_CTRL_BUS_AWVALID,
AWREADY => s_axi_CTRL_BUS_AWREADY,
AWADDR => s_axi_CTRL_BUS_AWADDR,
WVALID => s_axi_CTRL_BUS_WVALID,
WREADY => s_axi_CTRL_BUS_WREADY,
WDATA => s_axi_CTRL_BUS_WDATA,
WSTRB => s_axi_CTRL_BUS_WSTRB,
ARVALID => s_axi_CTRL_BUS_ARVALID,
ARREADY => s_axi_CTRL_BUS_ARREADY,
ARADDR => s_axi_CTRL_BUS_ARADDR,
RVALID => s_axi_CTRL_BUS_RVALID,
RREADY => s_axi_CTRL_BUS_RREADY,
RDATA => s_axi_CTRL_BUS_RDATA,
RRESP => s_axi_CTRL_BUS_RRESP,
BVALID => s_axi_CTRL_BUS_BVALID,
BREADY => s_axi_CTRL_BUS_BREADY,
BRESP => s_axi_CTRL_BUS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
xMin => xMin,
xMax => xMax);
doHistStretch_fmul_32ns_32ns_32_4_max_dsp_U1 : component doHistStretch_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_6_reg_443,
din1 => ap_const_lv32_437F0000,
ce => grp_fu_168_ce,
dout => grp_fu_168_p2);
doHistStretch_fdiv_32ns_32ns_32_16_U2 : component doHistStretch_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => tmp_5_reg_438,
din1 => xMax_minus_xMin_reg_389,
ce => grp_fu_173_ce,
dout => grp_fu_173_p2);
doHistStretch_sitofp_32s_32_6_U3 : component doHistStretch_sitofp_32s_32_6
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_177_p0,
ce => grp_fu_177_ce,
dout => grp_fu_177_p1);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_reg_ioackin_outStream_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))))) then
ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192)) and (ap_const_logic_1 = outStream_TREADY)))) then
ap_reg_ioackin_outStream_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) and not((exitcond_fu_197_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and (exitcond_fu_197_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) and not((exitcond_fu_197_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
idxPixel_reg_157_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond_fu_197_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then
idxPixel_reg_157 <= idxPixel_1_fu_203_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
idxPixel_reg_157 <= ap_const_lv19_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then
ap_reg_ppstg_exitcond_reg_394_pp0_iter1 <= exitcond_reg_394;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter1 <= tmp_dest_V_reg_428;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter1 <= tmp_id_V_reg_423;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter1 <= tmp_keep_V_reg_403;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter1 <= tmp_last_V_reg_418;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter1 <= tmp_strb_V_reg_408;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter1 <= tmp_user_V_reg_413;
exitcond_reg_394 <= exitcond_fu_197_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_reg_ppstg_exitcond_reg_394_pp0_iter10 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter9;
ap_reg_ppstg_exitcond_reg_394_pp0_iter11 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter10;
ap_reg_ppstg_exitcond_reg_394_pp0_iter12 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter11;
ap_reg_ppstg_exitcond_reg_394_pp0_iter13 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter12;
ap_reg_ppstg_exitcond_reg_394_pp0_iter14 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter13;
ap_reg_ppstg_exitcond_reg_394_pp0_iter15 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter14;
ap_reg_ppstg_exitcond_reg_394_pp0_iter16 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter15;
ap_reg_ppstg_exitcond_reg_394_pp0_iter17 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter16;
ap_reg_ppstg_exitcond_reg_394_pp0_iter18 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter17;
ap_reg_ppstg_exitcond_reg_394_pp0_iter19 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter18;
ap_reg_ppstg_exitcond_reg_394_pp0_iter2 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter1;
ap_reg_ppstg_exitcond_reg_394_pp0_iter20 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter19;
ap_reg_ppstg_exitcond_reg_394_pp0_iter21 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter20;
ap_reg_ppstg_exitcond_reg_394_pp0_iter22 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter21;
ap_reg_ppstg_exitcond_reg_394_pp0_iter23 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter22;
ap_reg_ppstg_exitcond_reg_394_pp0_iter24 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter23;
ap_reg_ppstg_exitcond_reg_394_pp0_iter25 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter24;
ap_reg_ppstg_exitcond_reg_394_pp0_iter3 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter2;
ap_reg_ppstg_exitcond_reg_394_pp0_iter4 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter3;
ap_reg_ppstg_exitcond_reg_394_pp0_iter5 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter4;
ap_reg_ppstg_exitcond_reg_394_pp0_iter6 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter5;
ap_reg_ppstg_exitcond_reg_394_pp0_iter7 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter6;
ap_reg_ppstg_exitcond_reg_394_pp0_iter8 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter7;
ap_reg_ppstg_exitcond_reg_394_pp0_iter9 <= ap_reg_ppstg_exitcond_reg_394_pp0_iter8;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter10 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter9;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter11 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter10;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter12 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter11;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter13 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter12;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter14 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter13;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter15 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter14;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter16 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter15;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter17 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter16;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter18 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter17;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter19 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter18;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter2 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter1;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter20 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter19;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter21 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter20;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter22 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter21;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter23 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter22;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter24 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter23;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter25 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter24;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter3 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter2;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter4 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter3;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter5 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter4;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter6 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter5;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter7 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter6;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter8 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter7;
ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter9 <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter8;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter10 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter9;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter11 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter10;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter12 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter11;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter13 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter12;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter14 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter13;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter15 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter14;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter16 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter15;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter17 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter16;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter18 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter17;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter19 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter18;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter2 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter1;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter20 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter19;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter21 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter20;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter22 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter21;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter23 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter22;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter24 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter23;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter25 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter24;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter3 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter2;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter4 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter3;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter5 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter4;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter6 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter5;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter7 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter6;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter8 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter7;
ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter9 <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter8;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter10 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter9;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter11 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter10;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter12 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter11;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter13 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter12;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter14 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter13;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter15 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter14;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter16 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter15;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter17 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter16;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter18 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter17;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter19 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter18;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter2 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter1;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter20 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter19;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter21 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter20;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter22 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter21;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter23 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter22;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter24 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter23;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter25 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter24;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter3 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter2;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter4 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter3;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter5 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter4;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter6 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter5;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter7 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter6;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter8 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter7;
ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter9 <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter8;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter10 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter9;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter11 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter10;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter12 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter11;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter13 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter12;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter14 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter13;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter15 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter14;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter16 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter15;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter17 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter16;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter18 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter17;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter19 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter18;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter2 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter1;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter20 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter19;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter21 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter20;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter22 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter21;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter23 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter22;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter24 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter23;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter25 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter24;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter3 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter2;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter4 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter3;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter5 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter4;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter6 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter5;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter7 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter6;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter8 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter7;
ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter9 <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter8;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter10 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter9;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter11 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter10;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter12 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter11;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter13 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter12;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter14 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter13;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter15 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter14;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter16 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter15;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter17 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter16;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter18 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter17;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter19 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter18;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter2 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter1;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter20 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter19;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter21 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter20;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter22 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter21;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter23 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter22;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter24 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter23;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter25 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter24;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter3 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter2;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter4 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter3;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter5 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter4;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter6 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter5;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter7 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter6;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter8 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter7;
ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter9 <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter8;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter10 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter9;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter11 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter10;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter12 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter11;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter13 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter12;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter14 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter13;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter15 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter14;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter16 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter15;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter17 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter16;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter18 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter17;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter19 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter18;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter2 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter1;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter20 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter19;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter21 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter20;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter22 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter21;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter23 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter22;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter24 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter23;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter25 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter24;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter3 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter2;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter4 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter3;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter5 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter4;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter6 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter5;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter7 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter6;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter8 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter7;
ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter9 <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter8;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter24))) then
loc_V_1_reg_454 <= loc_V_1_fu_265_p1;
loc_V_reg_448 <= p_Val2_s_fu_251_p1(30 downto 23);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter4))) then
tmp_5_reg_438 <= grp_fu_177_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter20))) then
tmp_6_reg_443 <= grp_fu_173_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
tmp_cast_reg_379(7 downto 0) <= tmp_cast_fu_180_p1(7 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and (exitcond_fu_197_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then
tmp_dest_V_reg_428 <= inStream_TDEST;
tmp_id_V_reg_423 <= inStream_TID;
tmp_keep_V_reg_403 <= inStream_TKEEP;
tmp_last_V_reg_418 <= inStream_TLAST;
tmp_strb_V_reg_408 <= inStream_TSTRB;
tmp_user_V_reg_413 <= inStream_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
xMax_minus_xMin_reg_389 <= grp_fu_177_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
xMax_read_reg_369 <= xMax;
xMin_read_reg_374 <= xMin;
end if;
end if;
end process;
tmp_cast_reg_379(8) <= '0';
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it25, ap_reg_ppiten_pp0_it26, exitcond_fu_197_p2, ap_reg_ppstg_exitcond_reg_394_pp0_iter25, ap_sig_192, ap_sig_ioackin_outStream_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_7;
when ap_ST_pp0_stg0_fsm_7 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it25)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) and not((exitcond_fu_197_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_7;
elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it25))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) and not((exitcond_fu_197_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
ap_NS_fsm <= ap_ST_st35_fsm_8;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_7;
end if;
when ap_ST_st35_fsm_8 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXX";
end case;
end process;
ap_done_assign_proc : process(ap_sig_cseq_ST_st35_fsm_8)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_8)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_sig_cseq_ST_st35_fsm_8)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_8)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_177_assign_proc : process(ap_CS_fsm)
begin
ap_sig_177 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
ap_sig_188_assign_proc : process(ap_CS_fsm)
begin
ap_sig_188 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
ap_sig_192_assign_proc : process(inStream_TVALID, exitcond_fu_197_p2)
begin
ap_sig_192 <= ((exitcond_fu_197_p2 = ap_const_lv1_0) and (inStream_TVALID = ap_const_logic_0));
end process;
ap_sig_26_assign_proc : process(ap_CS_fsm)
begin
ap_sig_26 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
ap_sig_59_assign_proc : process(ap_CS_fsm)
begin
ap_sig_59 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
ap_sig_702_assign_proc : process(ap_CS_fsm)
begin
ap_sig_702 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
ap_sig_cseq_ST_pp0_stg0_fsm_7_assign_proc : process(ap_sig_59)
begin
if (ap_sig_59) then
ap_sig_cseq_ST_pp0_stg0_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_7 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_26)
begin
if (ap_sig_26) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_177)
begin
if (ap_sig_177) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st35_fsm_8_assign_proc : process(ap_sig_702)
begin
if (ap_sig_702) then
ap_sig_cseq_ST_st35_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st35_fsm_8 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_188)
begin
if (ap_sig_188) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
ap_sig_ioackin_outStream_TREADY_assign_proc : process(outStream_TREADY, ap_reg_ioackin_outStream_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) then
ap_sig_ioackin_outStream_TREADY <= outStream_TREADY;
else
ap_sig_ioackin_outStream_TREADY <= ap_const_logic_1;
end if;
end process;
exitcond_fu_197_p2 <= "1" when (idxPixel_reg_157 = ap_const_lv19_40000) else "0";
grp_fu_168_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_7, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it26, ap_reg_ppstg_exitcond_reg_394_pp0_iter25, ap_sig_192, ap_sig_ioackin_outStream_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then
grp_fu_168_ce <= ap_const_logic_1;
else
grp_fu_168_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_173_ce_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_7, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it26, ap_reg_ppstg_exitcond_reg_394_pp0_iter25, ap_sig_192, ap_sig_ioackin_outStream_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then
grp_fu_173_ce <= ap_const_logic_1;
else
grp_fu_173_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_177_ce_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_pp0_stg0_fsm_7, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it26, ap_reg_ppstg_exitcond_reg_394_pp0_iter25, ap_sig_192, ap_sig_ioackin_outStream_TREADY, ap_sig_cseq_ST_st35_fsm_8)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_8))) then
grp_fu_177_ce <= ap_const_logic_0;
else
grp_fu_177_ce <= ap_const_logic_1;
end if;
end process;
grp_fu_177_p0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_7, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_st2_fsm_1, xMax_minus_xMin6_fu_192_p1, tmp_s_fu_246_p1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
grp_fu_177_p0 <= tmp_s_fu_246_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
grp_fu_177_p0 <= xMax_minus_xMin6_fu_192_p1;
else
grp_fu_177_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
idxPixel_1_fu_203_p2 <= std_logic_vector(unsigned(idxPixel_reg_157) + unsigned(ap_const_lv19_1));
inStream_TDATA_blk_n_assign_proc : process(inStream_TVALID, ap_sig_cseq_ST_pp0_stg0_fsm_7, ap_reg_ppiten_pp0_it0, exitcond_fu_197_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond_fu_197_p2 = ap_const_lv1_0))) then
inStream_TDATA_blk_n <= inStream_TVALID;
else
inStream_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
inStream_TREADY_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_7, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it26, exitcond_fu_197_p2, ap_reg_ppstg_exitcond_reg_394_pp0_iter25, ap_sig_192, ap_sig_ioackin_outStream_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_7) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond_fu_197_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))))) then
inStream_TREADY <= ap_const_logic_1;
else
inStream_TREADY <= ap_const_logic_0;
end if;
end process;
isNeg_fu_289_p3 <= sh_assign_fu_283_p2(8 downto 8);
loc_V_1_fu_265_p1 <= p_Val2_s_fu_251_p1(23 - 1 downto 0);
outStream_TDATA <=
tmp_fu_346_p1 when (isNeg_fu_289_p3(0) = '1') else
tmp_3_fu_350_p4;
outStream_TDATA_blk_n_assign_proc : process(outStream_TREADY, ap_reg_ppiten_pp0_it26, ap_reg_ppstg_exitcond_reg_394_pp0_iter25)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25))) then
outStream_TDATA_blk_n <= outStream_TREADY;
else
outStream_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
outStream_TDEST <= ap_reg_ppstg_tmp_dest_V_reg_428_pp0_iter25;
outStream_TID <= ap_reg_ppstg_tmp_id_V_reg_423_pp0_iter25;
outStream_TKEEP <= ap_reg_ppstg_tmp_keep_V_reg_403_pp0_iter25;
outStream_TLAST <= ap_reg_ppstg_tmp_last_V_reg_418_pp0_iter25;
outStream_TSTRB <= ap_reg_ppstg_tmp_strb_V_reg_408_pp0_iter25;
outStream_TUSER <= ap_reg_ppstg_tmp_user_V_reg_413_pp0_iter25;
outStream_TVALID_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it26, ap_reg_ppstg_exitcond_reg_394_pp0_iter25, ap_sig_192, ap_reg_ioackin_outStream_TREADY)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it26) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_394_pp0_iter25) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_192)) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)))) then
outStream_TVALID <= ap_const_logic_1;
else
outStream_TVALID <= ap_const_logic_0;
end if;
end process;
p_Result_s_fu_269_p3 <= (ap_const_lv1_1 & loc_V_1_reg_454);
p_Val2_s_fu_251_p1 <= grp_fu_168_p2;
sh_assign_1_cast_cast_fu_318_p1 <= std_logic_vector(resize(signed(sh_assign_1_fu_306_p3),24));
sh_assign_1_cast_fu_314_p1 <= std_logic_vector(resize(signed(sh_assign_1_fu_306_p3),32));
sh_assign_1_fu_306_p3 <=
tmp_4_i_i_cast_fu_302_p1 when (isNeg_fu_289_p3(0) = '1') else
sh_assign_fu_283_p2;
sh_assign_fu_283_p2 <= std_logic_vector(signed(ap_const_lv9_181) + signed(tmp_i_i_i_cast1_fu_280_p1));
tmp_1_fu_186_p2 <= std_logic_vector(unsigned(tmp_cast_6_fu_183_p1) - unsigned(tmp_cast_fu_180_p1));
tmp_2_i_i_fu_276_p1 <= std_logic_vector(resize(unsigned(p_Result_s_fu_269_p3),54));
tmp_3_cast_fu_237_p1 <= std_logic_vector(resize(unsigned(inStream_TDATA),9));
tmp_3_fu_350_p4 <= tmp_9_i_i_fu_332_p2(30 downto 23);
tmp_4_fu_241_p2 <= std_logic_vector(unsigned(tmp_3_cast_fu_237_p1) - unsigned(tmp_cast_reg_379));
tmp_4_i_i_cast_fu_302_p1 <= std_logic_vector(resize(signed(tmp_4_i_i_fu_297_p2),9));
tmp_4_i_i_fu_297_p2 <= std_logic_vector(unsigned(ap_const_lv8_7F) - unsigned(loc_V_reg_448));
tmp_6_i_i_fu_322_p1 <= std_logic_vector(resize(unsigned(sh_assign_1_cast_fu_314_p1),54));
tmp_7_i_i_fu_326_p2 <= std_logic_vector(shift_right(unsigned(p_Result_s_fu_269_p3),to_integer(unsigned('0' & sh_assign_1_cast_cast_fu_318_p1(24-1 downto 0)))));
tmp_9_fu_338_p3 <= tmp_7_i_i_fu_326_p2(23 downto 23);
tmp_9_i_i_fu_332_p2 <= std_logic_vector(shift_left(unsigned(tmp_2_i_i_fu_276_p1),to_integer(unsigned('0' & tmp_6_i_i_fu_322_p1(31-1 downto 0)))));
tmp_cast_6_fu_183_p1 <= std_logic_vector(resize(unsigned(xMax_read_reg_369),9));
tmp_cast_fu_180_p1 <= std_logic_vector(resize(unsigned(xMin_read_reg_374),9));
tmp_fu_346_p1 <= std_logic_vector(resize(unsigned(tmp_9_fu_338_p3),8));
tmp_i_i_i_cast1_fu_280_p1 <= std_logic_vector(resize(unsigned(loc_V_reg_448),9));
tmp_s_fu_246_p1 <= std_logic_vector(resize(signed(tmp_4_fu_241_p2),32));
xMax_minus_xMin6_fu_192_p1 <= std_logic_vector(resize(signed(tmp_1_fu_186_p2),32));
end behav;
| gpl-3.0 | 347d32f85e40763771c697f1333eff17 | 0.613504 | 2.671451 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue25/2_SecondaryUnit.vhdl | 2 | 1,356 | -- This snippets reports that the specifications of test2 (line 17 and 26) are not identical.
-- Line 17 was generated by line duplication in my editor ... strange
-- Have I missed something?
--
-- PS H:\Austausch\PoC\temp\bugreport> C:\Tools\GHDL.new\bin\ghdl.exe -a -v .\2_SecondaryUnit.vhd
-- .\2_SecondaryUnit.vhd:25:18: body of procedure "test2" does not conform with specification at .\2_SecondaryUnit.vhd:16:18
--
package pkg is
type T_ANGEL is range INTEGER'low to INTEGER'high units
second;
minute = 60 second;
deg = 60 minute;
end units;
subtype T_PHASE is T_ANGEL range -360 deg to 360 deg;
function test1(Phase : T_PHASE := 10 second) return T_PHASE;
procedure test2(signal output : out T_PHASE; input : T_PHASE := 10.0 second);
end package;
package body pkg is
function test1(Phase : T_PHASE := 10 second) return T_PHASE is
begin
return Phase + 1.0 deg;
end function;
procedure test2(signal output : out T_PHASE; input : T_PHASE := 10.0 second) is
begin
output <= input;
end procedure;
end package body;
use work.pkg.all;
entity SecondaryUnit_tb is
end entity;
architecture test of SecondaryUnit_tb is
signal TestSignal1 : T_PHASE;
signal TestSignal2 : T_PHASE;
begin
TestSignal1 <= test1(50.0 second);
test2(TestSignal2, TestSignal1);
end architecture;
| gpl-2.0 | 2cb488b6933dc079bb980d65a6e2ef4e | 0.69764 | 3.13164 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue2/sortnet_OddEvenSort_tb.vhdl | 2 | 4,464 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: Sorting Network: Odd-Even-Sort (Transposition)
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library PoC;
--use PoC.utils.all;
--use PoC.vectors.all;
use work.vectors.all;
-- library OSVVM;
-- use OSVVM.RandomPkg.all;
entity sortnet_OddEvenSort_tb is
end entity;
architecture tb of sortnet_OddEvenSort_tb is
constant INPUTS : POSITIVE := 8;
constant KEY_BITS : POSITIVE := 8;
constant DATA_BITS : POSITIVE := 8;
subtype T_KEY is STD_LOGIC_VECTOR(KEY_BITS - 1 downto 0);
type T_KEY_VECTOR is array(NATURAL range <>) of T_KEY;
function to_kv(slm : T_SLM) return T_KEY_VECTOR is
variable Result : T_KEY_VECTOR(slm'range(1));
begin
for i in slm'high(1) downto slm'low(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(i)(j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_slm(kv : T_KEY_VECTOR) return T_SLM is
variable Result : T_SLM(kv'range, T_KEY'range);
begin
for i in kv'range loop
for j in T_KEY'range loop
Result(i, j) := kv(i)(j);
end loop;
end loop;
return Result;
end function;
constant CLOCK_PERIOD : TIME := 10 ns;
signal Clock : STD_LOGIC := '1';
signal KeyInputVector : T_KEY_VECTOR(INPUTS - 1 downto 0) := (others => (others => '0'));
signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal KeyOutputVector : T_KEY_VECTOR(INPUTS - 1 downto 0);
signal StopSimulation : STD_LOGIC := '0';
begin
Clock <= Clock xnor StopSimulation after CLOCK_PERIOD;
process
-- variable RandomVar : RandomPType; -- protected type from RandomPkg
begin
-- RandomVar.InitSeed(RandomVar'instance_name); -- Generate initial seeds
wait until rising_edge(Clock);
for i in 0 to 63 loop
wait until rising_edge(Clock);
for j in 0 to INPUTS - 1 loop
-- KeyInputVector(j) <= RandomVar.RandSlv(0, 255), KEY_BITS);
KeyInputVector(j) <= std_logic_vector(unsigned(KeyInputVector(j)) + i + j);
end loop;
end loop;
for i in 0 to 7 loop
wait until rising_edge(Clock);
end loop;
StopSimulation <= '1';
wait;
end process;
DataInputMatrix <= to_slm(KeyInputVector);
sort : entity work.sortnet_OddEvenSort
generic map (
INPUTS => INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS,
PIPELINE_STAGE_AFTER => 2,
ADD_OUTPUT_REGISTERS => TRUE
)
port map (
Clock => Clock,
Reset => '0',
DataInputs => DataInputMatrix,
DataOutputs => DataOutputMatrix
);
KeyOutputVector <= to_kv(DataOutputMatrix);
process
variable Check : BOOLEAN;
begin
for i in 0 to 5 loop
wait until rising_edge(Clock);
end loop;
for i in 0 to 63 loop
Check := TRUE;
for j in 0 to INPUTS - 2 loop
Check := Check and (KeyOutputVector(j) <= KeyOutputVector(j + 1));
end loop;
assert Check report "ERROR: " severity ERROR;
end loop;
wait;
end process;
end architecture;
| gpl-2.0 | cd271ae797348a5a313f1c6f548b50d4 | 0.59879 | 3.361446 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_08.vhd | 4 | 2,972 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity processor_node is
end entity processor_node;
-- code from book
architecture dataflow of processor_node is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_unique ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_unique;
-- end not in book
signal address_bus : resolve_unique word bus;
-- . . .
-- not in book
signal cache_miss, dirty, replace_section,
snoop_hit, flag_update : bit := '0';
constant tag_section0 : bit_vector(11 downto 0) := X"000";
constant tag_section1 : bit_vector(11 downto 0) := X"001";
constant set_index : bit_vector(15 downto 0) := X"6666";
constant snoop_address : word := X"88888888";
-- end not in book
begin
cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
begin
address_bus <= guarded
tag_section0 & set_index & B"0000" when replace_section = '0' else
tag_section1 & set_index & B"0000";
end block cache_to_address_buffer;
snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
begin
address_bus <= guarded snoop_address(31 downto 4) & B"0000";
end block snoop_to_address_buffer;
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
dirty <= '0'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
dirty <= '1'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
replace_section <= '1';
cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture dataflow;
-- end code from book
| gpl-2.0 | 7ebe537226e34a3885df444467e44414 | 0.620794 | 3.642157 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1069/ram3.vhdl | 1 | 1,829 | library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH : positive := 12;
WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
addr_a : in std_logic_vector(ADDRWIDTH - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH - 1 downto 0);
clk_b : in std_logic;
read_b : in std_logic;
write_b : in std_logic;
addr_b : in std_logic_vector(ADDRWIDTH - 1 downto 0);
data_read_b : out std_logic_vector(WIDTH - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
signal reg_a : std_logic_vector(WIDTH - 1 downto 0);
signal reg_b : std_logic_vector(WIDTH - 1 downto 0);
begin
process(clk_a, clk_b)
type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
variable store : ram_t := (others => (others => '0'));
begin
if rising_edge(clk_a) then
if write_a = '1' then
store(to_integer(unsigned(addr_a))) := data_write_a;
end if;
if read_a = '1' then
reg_a <= store(to_integer(unsigned(addr_a)));
end if;
data_read_a <= reg_a;
end if;
if rising_edge(clk_b) then
if write_b = '1' then
store(to_integer(unsigned(addr_b))) := data_write_b;
end if;
if read_b = '1' then
reg_b <= store(to_integer(unsigned(addr_b)));
end if;
data_read_b <= reg_b;
end if;
end process;
end behavioral;
| gpl-2.0 | 05dc5355709177ed645fe992a3ca558a | 0.526517 | 3.301444 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_07.vhd | 4 | 2,671 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity bidir_buffer is
port ( bidir : inout std_logic_vector;
ena : in std_ulogic;
going_out : in std_ulogic_vector;
coming_in : out std_ulogic_vector );
end entity bidir_buffer;
--------------------------------------------------
architecture behavior of bidir_buffer is
-- code from book
constant hi_impedance : std_logic_vector(bidir'range) := (others => 'Z');
-- . . .
-- end code from book
begin
-- code from book
bidir <= To_stdlogicvector(going_out) when ena = '1' else
hi_impedance;
coming_in <= To_stdulogicvector(bidir);
-- end code from book
end architecture behavior;
entity ap_a_07 is
end entity ap_a_07;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_07 is
signal bidir : std_logic_vector(3 downto 0);
signal going_out, coming_in : std_ulogic_vector(3 downto 0);
signal ena : std_ulogic;
begin
dut : entity work.bidir_buffer
port map ( bidir, ena, going_out, coming_in );
ena <= '0', '1' after 10 ns, '0' after 30 ns;
going_out <= "0000", "1111" after 20 ns;
bidir <= "ZZZZ", "0000" after 40 ns, "1111" after 50 ns, "ZZZZ" after 60 ns;
end architecture test;
| gpl-2.0 | 78cf65ef9b96a9f120f1448b332c48d2 | 0.527143 | 4.466555 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1051/psi_tb_activity_pkg.vhd | 1 | 9,938 | ------------------------------------------------------------------------------
-- Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
-- Authors: Oliver Bruendler, Benoit Stef
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
------------------------------------------------------------------------------
-- Package Header
------------------------------------------------------------------------------
package psi_tb_activity_pkg is
-- Wait for a given time and check if the signal is idle
procedure CheckNoActivity(signal Sig : in std_logic;
IdleTime : in time;
Level : in integer range -1 to 1; -- -1 = don't check, 0 = low, 1 = high
Msg : in string := "";
Prefix : in string := "###ERROR###: ");
procedure CheckNoActivityStlv(signal Sig : in std_logic_vector;
IdleTime : in time;
Level : in integer range -1 to integer'high; -- -1 = don't check, otherwise interpreted unsigned
Msg : in string := "";
Prefix : in string := "###ERROR###: ");
-- Check when a signal had its last activity (without waiting)
procedure CheckLastActivity(signal Sig : in std_logic;
IdleTime : in time;
Level : in integer range -1 to 1; -- -1 = don't check, 0 = low, 1 = high
Msg : in string := "";
Prefix : in string := "###ERROR###: ");
procedure CheckLastActivityStlv(signal Sig : in std_logic_vector;
IdleTime : in time;
Level : in integer range -1 to integer'high; -- -1 = don't check, otherwise interpreted unsigned
Msg : in string := "";
Prefix : in string := "###ERROR###: ");
-- pulse a signal
procedure PulseSig(signal Sig : out std_logic;
signal Clk : in std_logic);
-- Clocked wait for a signal
procedure ClockedWaitFor(Val : in std_logic;
signal Sig : in std_logic;
signal Clk : in std_logic);
-- Wait for a number of clock cycles
procedure WaitClockCycles( Cycles : in integer;
signal Clk : in std_logic);
-- Wait for a time and quit on rising edge
procedure ClockedWaitTime( Duration : in time;
signal Clk : in std_logic);
-- Strobe generator
procedure GenerateStrobe( freq_clock : in real := 100.0E6; -- in Hz
freq_str : in real := 1.0E6; -- in Hz
rst_pol_g : in std_logic := '1'; -- reset polarity
signal rst : in std_logic; -- rst
signal clk : in std_logic; -- clk
signal str : out std_logic); -- str
-- check if stdlv is arrived within a defined period of time
procedure WaitForValueStdlv(signal Sig : in std_logic_vector; -- Signal to check
ExpVal : in std_logic_vector; -- expected value
Timeout : in time; -- time to wait for
Msg : in string; -- msg to display
Prefix : in string := "###ERROR###: "); -- bool out to stop Tb for ex.
-- check if std is arrived within a defined period of time
procedure WaitForValueStdl( signal Sig : in std_logic; -- Signal to check
ExpVal : in std_logic; -- expected value
Timeout : in time; -- time to wait for
Msg : in string; -- msg to display
Prefix : in string := "###ERROR###: "); -- bool out to stop Tb for ex.
end psi_tb_activity_pkg;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body psi_tb_activity_pkg is
-- *** CheckNoActivity ***
procedure CheckNoActivity(signal Sig : in std_logic;
IdleTime : in time;
Level : in integer range -1 to 1; -- -1 = don't check, 0 = low, 1 = high
Msg : in string := "";
Prefix : in string := "###ERROR###: ") is
begin
wait for IdleTime;
assert Sig'last_event >= IdleTime
report Prefix & Msg & "[Unexpected Activity]"
severity error;
if Level /= -1 then
StdlCompare(Level, Sig, "CheckNoActivity: " & Msg, Prefix);
end if;
end procedure;
-- *** CheckNoActivityStlv ***
procedure CheckNoActivityStlv(signal Sig : in std_logic_vector;
IdleTime : in time;
Level : in integer range -1 to integer'high; -- -1 = don't check, otherwise interpreted unsigned
Msg : in string := "";
Prefix : in string := "###ERROR###: ") is
begin
wait for IdleTime;
assert Sig'last_event >= IdleTime
report Prefix & Msg & "[Unexpected Activity]"
severity error;
if Level /= -1 then
StdlvCompareInt(Level, Sig, "CheckNoActivityStlv: " & Msg, false, 0, Prefix);
end if;
end procedure;
-- *** CheckLastActivity ***
procedure CheckLastActivity(signal Sig : in std_logic;
IdleTime : in time;
Level : in integer range -1 to 1; -- -1 = don't check, 0 = low, 1 = high
Msg : in string := "";
Prefix : in string := "###ERROR###: ") is
begin
assert Sig'last_event >= IdleTime
report Prefix & Msg & "Unexpected activity, " &
"[Expeced idle " & time'image(IdleTime) &
", Actual idle " & time'image(Sig'last_event) & "]"
severity error;
if Level /= -1 then
StdlCompare(Level, Sig, "CheckLastActivity: " & Msg, Prefix);
end if;
end procedure;
-- *** CheckLastActivityStlv ***
procedure CheckLastActivityStlv(signal Sig : in std_logic_vector;
IdleTime : in time;
Level : in integer range -1 to integer'high; -- -1 = don't check, otherwise interpreted unsigned
Msg : in string := "";
Prefix : in string := "###ERROR###: ") is
begin
assert Sig'last_event >= IdleTime
report Prefix & Msg & "Unexpected activity, " &
"[Expeced idle " & time'image(IdleTime) &
", Actual idle " & time'image(Sig'last_event) & "]"
severity error;
if Level /= -1 then
StdlvCompareInt(Level, Sig, "CheckLastActivityStlv: " & Msg, false, 0, Prefix);
end if;
end procedure;
-- *** PulseSig ***
procedure PulseSig(signal Sig : out std_logic;
signal Clk : in std_logic) is
begin
wait until rising_edge(Clk);
Sig <= '1';
wait until rising_edge(Clk);
Sig <= '0';
end procedure;
-- *** ClockedWaitFor ***
procedure ClockedWaitFor(Val : in std_logic;
signal Sig : in std_logic;
signal Clk : in std_logic) is
begin
wait until rising_edge(Clk) and Sig = Val;
end procedure;
-- *** ClockedWaitFor ***
procedure WaitClockCycles( Cycles : in integer;
signal Clk : in std_logic) is
begin
for i in 0 to Cycles-1 loop
wait until rising_edge(Clk);
end loop;
end procedure;
-- *** ClockedWaitTime ***
procedure ClockedWaitTime( Duration : in time;
signal Clk : in std_logic) is
begin
wait for Duration;
wait until rising_edge(Clk);
end procedure;
-- *** GenerateStrobe ***
procedure GenerateStrobe( freq_clock : in real := 100.0E6;
freq_str : in real := 1.0E6;
rst_pol_g : in std_logic := '1';
signal rst : in std_logic;
signal clk : in std_logic;
signal str : out std_logic) is
variable count_v : integer range 0 to (integer(ceil(freq_clock/freq_str))) := 0;
begin
while true loop
wait until rising_edge(clk);
if rst = rst_pol_g then
count_v := 0;
str <= '0';
else
if count_v /= integer(ceil(freq_clock/freq_str)) - 1 then
str <= '0';
count_v := count_v + 1;
else
str <= '1';
count_v := 0;
end if;
end if;
end loop;
end procedure;
-- *** Wait for Standard logic vector to happen ***
procedure WaitForValueStdlv(signal Sig : in std_logic_vector;
ExpVal : in std_logic_vector;
Timeout : in time;
Msg : in string;
Prefix : in string := "###ERROR###: ") is
begin
wait until ExpVal = Sig for timeout;
if ExpVal /= Sig then
report Prefix & Msg &
" Target state not reached" &
" [Expected " & str(ExpVal) & "(0x" & hstr(ExpVal) & ")" &
", Received " & str(Sig) & "(0x" & hstr(Sig) & ")" & "]"
severity error;
end if;
end procedure;
-- *** Wait for Standard logic to happen ***
procedure WaitForValueStdl( signal Sig : in std_logic;
ExpVal : in std_logic;
Timeout : in time;
Msg : in string;
Prefix : in string := "###ERROR###: ") is
begin
wait until ExpVal = Sig for timeout;
if ExpVal /= Sig then
report Prefix & msg &
" Target state not reached" &
" [Expected " & str(ExpVal) &
", Received " & str(Sig) & "]"
severity error;
end if;
end procedure;
end psi_tb_activity_pkg;
| gpl-2.0 | cab8cd8a072769cacb56a55589e715b8 | 0.501409 | 4.007258 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth76/dff02.vhdl | 1 | 470 | library ieee;
use ieee.std_logic_1164.all;
entity dff02 is
port (q : out std_logic;
d : std_logic;
en : std_logic;
rst : std_logic;
clk : std_logic);
end dff02;
architecture behav of dff02 is
signal t : std_logic := '1';
begin
process (clk, rst) is
begin
if rst = '1' then
t <= '1';
elsif rising_edge (clk) then
if en = '1' then
t <= d;
end if;
end if;
end process;
q <= t;
end behav;
| gpl-2.0 | 5e5c26189151dfeca38fb04154c6e013 | 0.538298 | 3.071895 | false | false | false | false |
nickg/nvc | test/regress/array4.vhd | 5 | 351 | entity array4 is
end entity;
architecture test of array4 is
type ma_t is array (1 downto 0, 7 downto 0) of bit_vector(7 downto 0);
signal ma : ma_t;
begin
process is
begin
ma <= (others => (others => (others => '0')));
wait for 1 ns;
assert ma(1, 2) = X"00";
wait;
end process;
end architecture;
| gpl-3.0 | 650add7e33fcbe6a04cc352815de1401 | 0.57265 | 3.407767 | false | true | false | false |
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