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// SPDX-License-Identifier: GPL-2.0-only
/*
* MFD core driver for the X-Powers' Power Management ICs
*
* AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
* converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
* as well as configurable GPIOs.
*
* This file contains the interface independent core functions.
*
* Copyright (C) 2014 Carlo Caione
*
* Author: Carlo Caione <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/axp20x.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#define AXP20X_OFF BIT(7)
#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0
#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
static const char * const axp20x_model_names[] = {
"AXP152",
"AXP192",
"AXP202",
"AXP209",
"AXP221",
"AXP223",
"AXP288",
"AXP313a",
"AXP803",
"AXP806",
"AXP809",
"AXP813",
"AXP15060",
};
static const struct regmap_range axp152_writeable_ranges[] = {
regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
};
static const struct regmap_range axp152_volatile_ranges[] = {
regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
};
static const struct regmap_access_table axp152_writeable_table = {
.yes_ranges = axp152_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
};
static const struct regmap_access_table axp152_volatile_table = {
.yes_ranges = axp152_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
};
static const struct regmap_range axp20x_writeable_ranges[] = {
regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
};
static const struct regmap_range axp20x_volatile_ranges[] = {
regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
};
static const struct regmap_access_table axp20x_writeable_table = {
.yes_ranges = axp20x_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
};
static const struct regmap_access_table axp20x_volatile_table = {
.yes_ranges = axp20x_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
};
static const struct regmap_range axp192_writeable_ranges[] = {
regmap_reg_range(AXP192_DATACACHE(0), AXP192_DATACACHE(5)),
regmap_reg_range(AXP192_PWR_OUT_CTRL, AXP192_IRQ5_STATE),
regmap_reg_range(AXP20X_DCDC_MODE, AXP192_N_RSTO_CTRL),
regmap_reg_range(AXP20X_CC_CTRL, AXP20X_CC_CTRL),
};
static const struct regmap_range axp192_volatile_ranges[] = {
regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP192_USB_OTG_STATUS),
regmap_reg_range(AXP192_IRQ1_STATE, AXP192_IRQ4_STATE),
regmap_reg_range(AXP192_IRQ5_STATE, AXP192_IRQ5_STATE),
regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
regmap_reg_range(AXP192_GPIO2_0_STATE, AXP192_GPIO2_0_STATE),
regmap_reg_range(AXP192_GPIO4_3_STATE, AXP192_GPIO4_3_STATE),
regmap_reg_range(AXP192_N_RSTO_CTRL, AXP192_N_RSTO_CTRL),
regmap_reg_range(AXP20X_CHRG_CC_31_24, AXP20X_CC_CTRL),
};
static const struct regmap_access_table axp192_writeable_table = {
.yes_ranges = axp192_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(axp192_writeable_ranges),
};
static const struct regmap_access_table axp192_volatile_table = {
.yes_ranges = axp192_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(axp192_volatile_ranges),
};
/* AXP22x ranges are shared with the AXP809, as they cover the same range */
static const struct regmap_range axp22x_writeable_ranges[] = {
regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
regmap_reg_range(AXP20X_CHRG_CTRL1, AXP22X_CHRG_CTRL3),
regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
};
static const struct regmap_range axp22x_volatile_ranges[] = {
regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L),
regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
};
static const struct regmap_access_table axp22x_writeable_table = {
.yes_ranges = axp22x_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
};
static const struct regmap_access_table axp22x_volatile_table = {
.yes_ranges = axp22x_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
};
/* AXP288 ranges are shared with the AXP803, as they cover the same range */
static const struct regmap_range axp288_writeable_ranges[] = {
regmap_reg_range(AXP288_POWER_REASON, AXP288_POWER_REASON),
regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
};
static const struct regmap_range axp288_volatile_ranges[] = {
regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
regmap_reg_range(AXP22X_PWR_OUT_CTRL1, AXP22X_ALDO3_V_OUT),
regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
regmap_reg_range(AXP288_BC_DET_STAT, AXP20X_VBUS_IPSOUT_MGMT),
regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
regmap_reg_range(AXP20X_GPIO1_CTRL, AXP22X_GPIO_STATE),
regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
};
static const struct regmap_access_table axp288_writeable_table = {
.yes_ranges = axp288_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
};
static const struct regmap_access_table axp288_volatile_table = {
.yes_ranges = axp288_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
};
static const struct regmap_range axp806_writeable_ranges[] = {
regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
};
static const struct regmap_range axp313a_writeable_ranges[] = {
regmap_reg_range(AXP313A_ON_INDICATE, AXP313A_IRQ_STATE),
};
static const struct regmap_range axp313a_volatile_ranges[] = {
regmap_reg_range(AXP313A_SHUTDOWN_CTRL, AXP313A_SHUTDOWN_CTRL),
regmap_reg_range(AXP313A_IRQ_STATE, AXP313A_IRQ_STATE),
};
static const struct regmap_access_table axp313a_writeable_table = {
.yes_ranges = axp313a_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(axp313a_writeable_ranges),
};
static const struct regmap_access_table axp313a_volatile_table = {
.yes_ranges = axp313a_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(axp313a_volatile_ranges),
};
static const struct regmap_range axp806_volatile_ranges[] = {
regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
};
static const struct regmap_access_table axp806_writeable_table = {
.yes_ranges = axp806_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges),
};
static const struct regmap_access_table axp806_volatile_table = {
.yes_ranges = axp806_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
};
static const struct regmap_range axp15060_writeable_ranges[] = {
regmap_reg_range(AXP15060_PWR_OUT_CTRL1, AXP15060_DCDC_MODE_CTRL2),
regmap_reg_range(AXP15060_OUTPUT_MONITOR_DISCHARGE, AXP15060_CPUSLDO_V_CTRL),
regmap_reg_range(AXP15060_PWR_WAKEUP_CTRL, AXP15060_PWR_DISABLE_DOWN_SEQ),
regmap_reg_range(AXP15060_PEK_KEY, AXP15060_PEK_KEY),
regmap_reg_range(AXP15060_IRQ1_EN, AXP15060_IRQ2_EN),
regmap_reg_range(AXP15060_IRQ1_STATE, AXP15060_IRQ2_STATE),
};
static const struct regmap_range axp15060_volatile_ranges[] = {
regmap_reg_range(AXP15060_STARTUP_SRC, AXP15060_STARTUP_SRC),
regmap_reg_range(AXP15060_PWR_WAKEUP_CTRL, AXP15060_PWR_DISABLE_DOWN_SEQ),
regmap_reg_range(AXP15060_IRQ1_STATE, AXP15060_IRQ2_STATE),
};
static const struct regmap_access_table axp15060_writeable_table = {
.yes_ranges = axp15060_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(axp15060_writeable_ranges),
};
static const struct regmap_access_table axp15060_volatile_table = {
.yes_ranges = axp15060_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(axp15060_volatile_ranges),
};
static const struct resource axp152_pek_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
};
static const struct resource axp192_ac_power_supply_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
};
static const struct resource axp192_usb_power_supply_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_VALID, "VBUS_VALID"),
DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
};
static const struct resource axp20x_ac_power_supply_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
};
static const struct resource axp20x_pek_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
};
static const struct resource axp20x_usb_power_supply_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
};
static const struct resource axp22x_usb_power_supply_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
};
/* AXP803 and AXP813/AXP818 share the same interrupts */
static const struct resource axp803_usb_power_supply_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
};
static const struct resource axp22x_pek_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
};
static const struct resource axp288_power_button_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKP, "PEK_DBR"),
DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKN, "PEK_DBF"),
};
static const struct resource axp288_fuel_gauge_resources[] = {
DEFINE_RES_IRQ(AXP288_IRQ_QWBTU),
DEFINE_RES_IRQ(AXP288_IRQ_WBTU),
DEFINE_RES_IRQ(AXP288_IRQ_QWBTO),
DEFINE_RES_IRQ(AXP288_IRQ_WBTO),
DEFINE_RES_IRQ(AXP288_IRQ_WL2),
DEFINE_RES_IRQ(AXP288_IRQ_WL1),
};
static const struct resource axp313a_pek_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP313A_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
DEFINE_RES_IRQ_NAMED(AXP313A_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
};
static const struct resource axp803_pek_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
};
static const struct resource axp806_pek_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_RISE, "PEK_DBR"),
DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_FALL, "PEK_DBF"),
};
static const struct resource axp809_pek_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
};
static const struct resource axp15060_pek_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP15060_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
DEFINE_RES_IRQ_NAMED(AXP15060_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
};
static const struct regmap_config axp152_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.wr_table = &axp152_writeable_table,
.volatile_table = &axp152_volatile_table,
.max_register = AXP152_PWM1_DUTY_CYCLE,
.cache_type = REGCACHE_MAPLE,
};
static const struct regmap_config axp192_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.wr_table = &axp192_writeable_table,
.volatile_table = &axp192_volatile_table,
.max_register = AXP20X_CC_CTRL,
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_config axp20x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.wr_table = &axp20x_writeable_table,
.volatile_table = &axp20x_volatile_table,
.max_register = AXP20X_OCV(AXP20X_OCV_MAX),
.cache_type = REGCACHE_MAPLE,
};
static const struct regmap_config axp22x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.wr_table = &axp22x_writeable_table,
.volatile_table = &axp22x_volatile_table,
.max_register = AXP22X_BATLOW_THRES1,
.cache_type = REGCACHE_MAPLE,
};
static const struct regmap_config axp288_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.wr_table = &axp288_writeable_table,
.volatile_table = &axp288_volatile_table,
.max_register = AXP288_FG_TUNE5,
.cache_type = REGCACHE_MAPLE,
};
static const struct regmap_config axp313a_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.wr_table = &axp313a_writeable_table,
.volatile_table = &axp313a_volatile_table,
.max_register = AXP313A_IRQ_STATE,
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_config axp806_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.wr_table = &axp806_writeable_table,
.volatile_table = &axp806_volatile_table,
.max_register = AXP806_REG_ADDR_EXT,
.cache_type = REGCACHE_MAPLE,
};
static const struct regmap_config axp15060_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.wr_table = &axp15060_writeable_table,
.volatile_table = &axp15060_volatile_table,
.max_register = AXP15060_IRQ2_STATE,
.cache_type = REGCACHE_MAPLE,
};
#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
[_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
static const struct regmap_irq axp152_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
};
static const struct regmap_irq axp192_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP192, ACIN_OVER_V, 0, 7),
INIT_REGMAP_IRQ(AXP192, ACIN_PLUGIN, 0, 6),
INIT_REGMAP_IRQ(AXP192, ACIN_REMOVAL, 0, 5),
INIT_REGMAP_IRQ(AXP192, VBUS_OVER_V, 0, 4),
INIT_REGMAP_IRQ(AXP192, VBUS_PLUGIN, 0, 3),
INIT_REGMAP_IRQ(AXP192, VBUS_REMOVAL, 0, 2),
INIT_REGMAP_IRQ(AXP192, VBUS_V_LOW, 0, 1),
INIT_REGMAP_IRQ(AXP192, BATT_PLUGIN, 1, 7),
INIT_REGMAP_IRQ(AXP192, BATT_REMOVAL, 1, 6),
INIT_REGMAP_IRQ(AXP192, BATT_ENT_ACT_MODE, 1, 5),
INIT_REGMAP_IRQ(AXP192, BATT_EXIT_ACT_MODE, 1, 4),
INIT_REGMAP_IRQ(AXP192, CHARG, 1, 3),
INIT_REGMAP_IRQ(AXP192, CHARG_DONE, 1, 2),
INIT_REGMAP_IRQ(AXP192, BATT_TEMP_HIGH, 1, 1),
INIT_REGMAP_IRQ(AXP192, BATT_TEMP_LOW, 1, 0),
INIT_REGMAP_IRQ(AXP192, DIE_TEMP_HIGH, 2, 7),
INIT_REGMAP_IRQ(AXP192, CHARG_I_LOW, 2, 6),
INIT_REGMAP_IRQ(AXP192, DCDC1_V_LONG, 2, 5),
INIT_REGMAP_IRQ(AXP192, DCDC2_V_LONG, 2, 4),
INIT_REGMAP_IRQ(AXP192, DCDC3_V_LONG, 2, 3),
INIT_REGMAP_IRQ(AXP192, PEK_SHORT, 2, 1),
INIT_REGMAP_IRQ(AXP192, PEK_LONG, 2, 0),
INIT_REGMAP_IRQ(AXP192, N_OE_PWR_ON, 3, 7),
INIT_REGMAP_IRQ(AXP192, N_OE_PWR_OFF, 3, 6),
INIT_REGMAP_IRQ(AXP192, VBUS_VALID, 3, 5),
INIT_REGMAP_IRQ(AXP192, VBUS_NOT_VALID, 3, 4),
INIT_REGMAP_IRQ(AXP192, VBUS_SESS_VALID, 3, 3),
INIT_REGMAP_IRQ(AXP192, VBUS_SESS_END, 3, 2),
INIT_REGMAP_IRQ(AXP192, LOW_PWR_LVL, 3, 0),
INIT_REGMAP_IRQ(AXP192, TIMER, 4, 7),
INIT_REGMAP_IRQ(AXP192, GPIO2_INPUT, 4, 2),
INIT_REGMAP_IRQ(AXP192, GPIO1_INPUT, 4, 1),
INIT_REGMAP_IRQ(AXP192, GPIO0_INPUT, 4, 0),
};
static const struct regmap_irq axp20x_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
};
static const struct regmap_irq axp22x_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
};
/* some IRQs are compatible with axp20x models */
static const struct regmap_irq axp288_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5),
INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6),
INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7),
INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
};
static const struct regmap_irq axp313a_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP313A, PEK_RIS_EDGE, 0, 7),
INIT_REGMAP_IRQ(AXP313A, PEK_FAL_EDGE, 0, 6),
INIT_REGMAP_IRQ(AXP313A, PEK_SHORT, 0, 5),
INIT_REGMAP_IRQ(AXP313A, PEK_LONG, 0, 4),
INIT_REGMAP_IRQ(AXP313A, DCDC3_V_LOW, 0, 3),
INIT_REGMAP_IRQ(AXP313A, DCDC2_V_LOW, 0, 2),
INIT_REGMAP_IRQ(AXP313A, DIE_TEMP_HIGH, 0, 0),
};
static const struct regmap_irq axp803_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP803, ACIN_OVER_V, 0, 7),
INIT_REGMAP_IRQ(AXP803, ACIN_PLUGIN, 0, 6),
INIT_REGMAP_IRQ(AXP803, ACIN_REMOVAL, 0, 5),
INIT_REGMAP_IRQ(AXP803, VBUS_OVER_V, 0, 4),
INIT_REGMAP_IRQ(AXP803, VBUS_PLUGIN, 0, 3),
INIT_REGMAP_IRQ(AXP803, VBUS_REMOVAL, 0, 2),
INIT_REGMAP_IRQ(AXP803, BATT_PLUGIN, 1, 7),
INIT_REGMAP_IRQ(AXP803, BATT_REMOVAL, 1, 6),
INIT_REGMAP_IRQ(AXP803, BATT_ENT_ACT_MODE, 1, 5),
INIT_REGMAP_IRQ(AXP803, BATT_EXIT_ACT_MODE, 1, 4),
INIT_REGMAP_IRQ(AXP803, CHARG, 1, 3),
INIT_REGMAP_IRQ(AXP803, CHARG_DONE, 1, 2),
INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH, 2, 7),
INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH_END, 2, 6),
INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW, 2, 5),
INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW_END, 2, 4),
INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH, 2, 3),
INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH_END, 2, 2),
INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW, 2, 1),
INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW_END, 2, 0),
INIT_REGMAP_IRQ(AXP803, DIE_TEMP_HIGH, 3, 7),
INIT_REGMAP_IRQ(AXP803, GPADC, 3, 2),
INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL1, 3, 1),
INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL2, 3, 0),
INIT_REGMAP_IRQ(AXP803, TIMER, 4, 7),
INIT_REGMAP_IRQ(AXP803, PEK_RIS_EDGE, 4, 6),
INIT_REGMAP_IRQ(AXP803, PEK_FAL_EDGE, 4, 5),
INIT_REGMAP_IRQ(AXP803, PEK_SHORT, 4, 4),
INIT_REGMAP_IRQ(AXP803, PEK_LONG, 4, 3),
INIT_REGMAP_IRQ(AXP803, PEK_OVER_OFF, 4, 2),
INIT_REGMAP_IRQ(AXP803, GPIO1_INPUT, 4, 1),
INIT_REGMAP_IRQ(AXP803, GPIO0_INPUT, 4, 0),
INIT_REGMAP_IRQ(AXP803, BC_USB_CHNG, 5, 1),
INIT_REGMAP_IRQ(AXP803, MV_CHNG, 5, 0),
};
static const struct regmap_irq axp806_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0),
INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1),
INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3),
INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4),
INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5),
INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6),
INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7),
INIT_REGMAP_IRQ(AXP806, POK_LONG, 1, 0),
INIT_REGMAP_IRQ(AXP806, POK_SHORT, 1, 1),
INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4),
INIT_REGMAP_IRQ(AXP806, POK_FALL, 1, 5),
INIT_REGMAP_IRQ(AXP806, POK_RISE, 1, 6),
};
static const struct regmap_irq axp809_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
};
static const struct regmap_irq axp15060_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP15060, DIE_TEMP_HIGH_LV1, 0, 0),
INIT_REGMAP_IRQ(AXP15060, DIE_TEMP_HIGH_LV2, 0, 1),
INIT_REGMAP_IRQ(AXP15060, DCDC1_V_LOW, 0, 2),
INIT_REGMAP_IRQ(AXP15060, DCDC2_V_LOW, 0, 3),
INIT_REGMAP_IRQ(AXP15060, DCDC3_V_LOW, 0, 4),
INIT_REGMAP_IRQ(AXP15060, DCDC4_V_LOW, 0, 5),
INIT_REGMAP_IRQ(AXP15060, DCDC5_V_LOW, 0, 6),
INIT_REGMAP_IRQ(AXP15060, DCDC6_V_LOW, 0, 7),
INIT_REGMAP_IRQ(AXP15060, PEK_LONG, 1, 0),
INIT_REGMAP_IRQ(AXP15060, PEK_SHORT, 1, 1),
INIT_REGMAP_IRQ(AXP15060, GPIO1_INPUT, 1, 2),
INIT_REGMAP_IRQ(AXP15060, PEK_FAL_EDGE, 1, 3),
INIT_REGMAP_IRQ(AXP15060, PEK_RIS_EDGE, 1, 4),
INIT_REGMAP_IRQ(AXP15060, GPIO2_INPUT, 1, 5),
};
static const struct regmap_irq_chip axp152_regmap_irq_chip = {
.name = "axp152_irq_chip",
.status_base = AXP152_IRQ1_STATE,
.ack_base = AXP152_IRQ1_STATE,
.unmask_base = AXP152_IRQ1_EN,
.init_ack_masked = true,
.irqs = axp152_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
.num_regs = 3,
};
static unsigned int axp192_get_irq_reg(struct regmap_irq_chip_data *data,
unsigned int base, int index)
{
/* linear mapping for IRQ1 to IRQ4 */
if (index < 4)
return base + index;
/* handle IRQ5 separately */
if (base == AXP192_IRQ1_EN)
return AXP192_IRQ5_EN;
return AXP192_IRQ5_STATE;
}
static const struct regmap_irq_chip axp192_regmap_irq_chip = {
.name = "axp192_irq_chip",
.status_base = AXP192_IRQ1_STATE,
.ack_base = AXP192_IRQ1_STATE,
.unmask_base = AXP192_IRQ1_EN,
.init_ack_masked = true,
.irqs = axp192_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp192_regmap_irqs),
.num_regs = 5,
.get_irq_reg = axp192_get_irq_reg,
};
static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
.name = "axp20x_irq_chip",
.status_base = AXP20X_IRQ1_STATE,
.ack_base = AXP20X_IRQ1_STATE,
.unmask_base = AXP20X_IRQ1_EN,
.init_ack_masked = true,
.irqs = axp20x_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
.num_regs = 5,
};
static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
.name = "axp22x_irq_chip",
.status_base = AXP20X_IRQ1_STATE,
.ack_base = AXP20X_IRQ1_STATE,
.unmask_base = AXP20X_IRQ1_EN,
.init_ack_masked = true,
.irqs = axp22x_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
.num_regs = 5,
};
static const struct regmap_irq_chip axp288_regmap_irq_chip = {
.name = "axp288_irq_chip",
.status_base = AXP20X_IRQ1_STATE,
.ack_base = AXP20X_IRQ1_STATE,
.unmask_base = AXP20X_IRQ1_EN,
.init_ack_masked = true,
.irqs = axp288_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
.num_regs = 6,
};
static const struct regmap_irq_chip axp313a_regmap_irq_chip = {
.name = "axp313a_irq_chip",
.status_base = AXP313A_IRQ_STATE,
.ack_base = AXP313A_IRQ_STATE,
.unmask_base = AXP313A_IRQ_EN,
.init_ack_masked = true,
.irqs = axp313a_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp313a_regmap_irqs),
.num_regs = 1,
};
static const struct regmap_irq_chip axp803_regmap_irq_chip = {
.name = "axp803",
.status_base = AXP20X_IRQ1_STATE,
.ack_base = AXP20X_IRQ1_STATE,
.unmask_base = AXP20X_IRQ1_EN,
.init_ack_masked = true,
.irqs = axp803_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp803_regmap_irqs),
.num_regs = 6,
};
static const struct regmap_irq_chip axp806_regmap_irq_chip = {
.name = "axp806",
.status_base = AXP20X_IRQ1_STATE,
.ack_base = AXP20X_IRQ1_STATE,
.unmask_base = AXP20X_IRQ1_EN,
.init_ack_masked = true,
.irqs = axp806_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp806_regmap_irqs),
.num_regs = 2,
};
static const struct regmap_irq_chip axp809_regmap_irq_chip = {
.name = "axp809",
.status_base = AXP20X_IRQ1_STATE,
.ack_base = AXP20X_IRQ1_STATE,
.unmask_base = AXP20X_IRQ1_EN,
.init_ack_masked = true,
.irqs = axp809_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
.num_regs = 5,
};
static const struct regmap_irq_chip axp15060_regmap_irq_chip = {
.name = "axp15060",
.status_base = AXP15060_IRQ1_STATE,
.ack_base = AXP15060_IRQ1_STATE,
.unmask_base = AXP15060_IRQ1_EN,
.init_ack_masked = true,
.irqs = axp15060_regmap_irqs,
.num_irqs = ARRAY_SIZE(axp15060_regmap_irqs),
.num_regs = 2,
};
static const struct mfd_cell axp192_cells[] = {
{
.name = "axp192-adc",
.of_compatible = "x-powers,axp192-adc",
}, {
.name = "axp20x-battery-power-supply",
.of_compatible = "x-powers,axp192-battery-power-supply",
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp202-ac-power-supply",
.num_resources = ARRAY_SIZE(axp192_ac_power_supply_resources),
.resources = axp192_ac_power_supply_resources,
}, {
.name = "axp20x-usb-power-supply",
.of_compatible = "x-powers,axp192-usb-power-supply",
.num_resources = ARRAY_SIZE(axp192_usb_power_supply_resources),
.resources = axp192_usb_power_supply_resources,
},
{ .name = "axp20x-regulator" },
};
static const struct mfd_cell axp20x_cells[] = {
{
.name = "axp20x-gpio",
.of_compatible = "x-powers,axp209-gpio",
}, {
.name = "axp20x-pek",
.num_resources = ARRAY_SIZE(axp20x_pek_resources),
.resources = axp20x_pek_resources,
}, {
.name = "axp20x-regulator",
}, {
.name = "axp20x-adc",
.of_compatible = "x-powers,axp209-adc",
}, {
.name = "axp20x-battery-power-supply",
.of_compatible = "x-powers,axp209-battery-power-supply",
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp202-ac-power-supply",
.num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
.resources = axp20x_ac_power_supply_resources,
}, {
.name = "axp20x-usb-power-supply",
.of_compatible = "x-powers,axp202-usb-power-supply",
.num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
.resources = axp20x_usb_power_supply_resources,
},
};
static const struct mfd_cell axp221_cells[] = {
{
.name = "axp20x-gpio",
.of_compatible = "x-powers,axp221-gpio",
}, {
.name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp22x_pek_resources),
.resources = axp22x_pek_resources,
}, {
.name = "axp20x-regulator",
}, {
.name = "axp22x-adc",
.of_compatible = "x-powers,axp221-adc",
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp221-ac-power-supply",
.num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
.resources = axp20x_ac_power_supply_resources,
}, {
.name = "axp20x-battery-power-supply",
.of_compatible = "x-powers,axp221-battery-power-supply",
}, {
.name = "axp20x-usb-power-supply",
.of_compatible = "x-powers,axp221-usb-power-supply",
.num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
.resources = axp22x_usb_power_supply_resources,
},
};
static const struct mfd_cell axp223_cells[] = {
{
.name = "axp20x-gpio",
.of_compatible = "x-powers,axp221-gpio",
}, {
.name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp22x_pek_resources),
.resources = axp22x_pek_resources,
}, {
.name = "axp22x-adc",
.of_compatible = "x-powers,axp221-adc",
}, {
.name = "axp20x-battery-power-supply",
.of_compatible = "x-powers,axp221-battery-power-supply",
}, {
.name = "axp20x-regulator",
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp221-ac-power-supply",
.num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
.resources = axp20x_ac_power_supply_resources,
}, {
.name = "axp20x-usb-power-supply",
.of_compatible = "x-powers,axp223-usb-power-supply",
.num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
.resources = axp22x_usb_power_supply_resources,
},
};
static const struct mfd_cell axp152_cells[] = {
{
.name = "axp20x-pek",
.num_resources = ARRAY_SIZE(axp152_pek_resources),
.resources = axp152_pek_resources,
},
};
static struct mfd_cell axp313a_cells[] = {
MFD_CELL_NAME("axp20x-regulator"),
MFD_CELL_RES("axp313a-pek", axp313a_pek_resources),
};
static const struct resource axp288_adc_resources[] = {
DEFINE_RES_IRQ_NAMED(AXP288_IRQ_GPADC, "GPADC"),
};
static const struct resource axp288_extcon_resources[] = {
DEFINE_RES_IRQ(AXP288_IRQ_VBUS_FALL),
DEFINE_RES_IRQ(AXP288_IRQ_VBUS_RISE),
DEFINE_RES_IRQ(AXP288_IRQ_MV_CHNG),
DEFINE_RES_IRQ(AXP288_IRQ_BC_USB_CHNG),
};
static const struct resource axp288_charger_resources[] = {
DEFINE_RES_IRQ(AXP288_IRQ_OV),
DEFINE_RES_IRQ(AXP288_IRQ_DONE),
DEFINE_RES_IRQ(AXP288_IRQ_CHARGING),
DEFINE_RES_IRQ(AXP288_IRQ_SAFE_QUIT),
DEFINE_RES_IRQ(AXP288_IRQ_SAFE_ENTER),
DEFINE_RES_IRQ(AXP288_IRQ_QCBTU),
DEFINE_RES_IRQ(AXP288_IRQ_CBTU),
DEFINE_RES_IRQ(AXP288_IRQ_QCBTO),
DEFINE_RES_IRQ(AXP288_IRQ_CBTO),
};
static const char * const axp288_fuel_gauge_suppliers[] = { "axp288_charger" };
static const struct property_entry axp288_fuel_gauge_properties[] = {
PROPERTY_ENTRY_STRING_ARRAY("supplied-from", axp288_fuel_gauge_suppliers),
{ }
};
static const struct software_node axp288_fuel_gauge_sw_node = {
.name = "axp288_fuel_gauge",
.properties = axp288_fuel_gauge_properties,
};
static const struct mfd_cell axp288_cells[] = {
{
.name = "axp288_adc",
.num_resources = ARRAY_SIZE(axp288_adc_resources),
.resources = axp288_adc_resources,
}, {
.name = "axp288_extcon",
.num_resources = ARRAY_SIZE(axp288_extcon_resources),
.resources = axp288_extcon_resources,
}, {
.name = "axp288_charger",
.num_resources = ARRAY_SIZE(axp288_charger_resources),
.resources = axp288_charger_resources,
}, {
.name = "axp288_fuel_gauge",
.num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
.resources = axp288_fuel_gauge_resources,
.swnode = &axp288_fuel_gauge_sw_node,
}, {
.name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp288_power_button_resources),
.resources = axp288_power_button_resources,
}, {
.name = "axp288_pmic_acpi",
},
};
static const struct mfd_cell axp803_cells[] = {
{
.name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp803_pek_resources),
.resources = axp803_pek_resources,
}, {
.name = "axp20x-gpio",
.of_compatible = "x-powers,axp813-gpio",
}, {
.name = "axp813-adc",
.of_compatible = "x-powers,axp813-adc",
}, {
.name = "axp20x-battery-power-supply",
.of_compatible = "x-powers,axp813-battery-power-supply",
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp813-ac-power-supply",
.num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
.resources = axp20x_ac_power_supply_resources,
}, {
.name = "axp20x-usb-power-supply",
.num_resources = ARRAY_SIZE(axp803_usb_power_supply_resources),
.resources = axp803_usb_power_supply_resources,
.of_compatible = "x-powers,axp813-usb-power-supply",
},
{ .name = "axp20x-regulator" },
};
static const struct mfd_cell axp806_self_working_cells[] = {
{
.name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp806_pek_resources),
.resources = axp806_pek_resources,
},
{ .name = "axp20x-regulator" },
};
static const struct mfd_cell axp806_cells[] = {
{
.id = 2,
.name = "axp20x-regulator",
},
};
static const struct mfd_cell axp809_cells[] = {
{
.name = "axp20x-gpio",
.of_compatible = "x-powers,axp221-gpio",
}, {
.name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp809_pek_resources),
.resources = axp809_pek_resources,
}, {
.id = 1,
.name = "axp20x-regulator",
},
};
static const struct mfd_cell axp813_cells[] = {
{
.name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp803_pek_resources),
.resources = axp803_pek_resources,
}, {
.name = "axp20x-regulator",
}, {
.name = "axp20x-gpio",
.of_compatible = "x-powers,axp813-gpio",
}, {
.name = "axp813-adc",
.of_compatible = "x-powers,axp813-adc",
}, {
.name = "axp20x-battery-power-supply",
.of_compatible = "x-powers,axp813-battery-power-supply",
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp813-ac-power-supply",
.num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
.resources = axp20x_ac_power_supply_resources,
}, {
.name = "axp20x-usb-power-supply",
.num_resources = ARRAY_SIZE(axp803_usb_power_supply_resources),
.resources = axp803_usb_power_supply_resources,
.of_compatible = "x-powers,axp813-usb-power-supply",
},
};
static const struct mfd_cell axp15060_cells[] = {
{
.name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp15060_pek_resources),
.resources = axp15060_pek_resources,
}, {
.name = "axp20x-regulator",
},
};
/* For boards that don't have IRQ line connected to SOC. */
static const struct mfd_cell axp_regulator_only_cells[] = {
{
.name = "axp20x-regulator",
},
};
static int axp20x_power_off(struct sys_off_data *data)
{
struct axp20x_dev *axp20x = data->cb_data;
unsigned int shutdown_reg;
switch (axp20x->variant) {
case AXP313A_ID:
shutdown_reg = AXP313A_SHUTDOWN_CTRL;
break;
default:
shutdown_reg = AXP20X_OFF_CTRL;
break;
}
regmap_write(axp20x->regmap, shutdown_reg, AXP20X_OFF);
/* Give capacitors etc. time to drain to avoid kernel panic msg. */
mdelay(500);
return NOTIFY_DONE;
}
int axp20x_match_device(struct axp20x_dev *axp20x)
{
struct device *dev = axp20x->dev;
const struct acpi_device_id *acpi_id;
const struct of_device_id *of_id;
if (dev->of_node) {
of_id = of_match_device(dev->driver->of_match_table, dev);
if (!of_id) {
dev_err(dev, "Unable to match OF ID\n");
return -ENODEV;
}
axp20x->variant = (long)of_id->data;
} else {
acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!acpi_id || !acpi_id->driver_data) {
dev_err(dev, "Unable to match ACPI ID and data\n");
return -ENODEV;
}
axp20x->variant = (long)acpi_id->driver_data;
}
switch (axp20x->variant) {
case AXP152_ID:
axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
axp20x->cells = axp152_cells;
axp20x->regmap_cfg = &axp152_regmap_config;
axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
break;
case AXP192_ID:
axp20x->nr_cells = ARRAY_SIZE(axp192_cells);
axp20x->cells = axp192_cells;
axp20x->regmap_cfg = &axp192_regmap_config;
axp20x->regmap_irq_chip = &axp192_regmap_irq_chip;
break;
case AXP202_ID:
case AXP209_ID:
axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
axp20x->cells = axp20x_cells;
axp20x->regmap_cfg = &axp20x_regmap_config;
axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
break;
case AXP221_ID:
axp20x->nr_cells = ARRAY_SIZE(axp221_cells);
axp20x->cells = axp221_cells;
axp20x->regmap_cfg = &axp22x_regmap_config;
axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
break;
case AXP223_ID:
axp20x->nr_cells = ARRAY_SIZE(axp223_cells);
axp20x->cells = axp223_cells;
axp20x->regmap_cfg = &axp22x_regmap_config;
axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
break;
case AXP288_ID:
axp20x->cells = axp288_cells;
axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
axp20x->regmap_cfg = &axp288_regmap_config;
axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
axp20x->irq_flags = IRQF_TRIGGER_LOW;
break;
case AXP313A_ID:
axp20x->nr_cells = ARRAY_SIZE(axp313a_cells);
axp20x->cells = axp313a_cells;
axp20x->regmap_cfg = &axp313a_regmap_config;
axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
break;
case AXP803_ID:
axp20x->nr_cells = ARRAY_SIZE(axp803_cells);
axp20x->cells = axp803_cells;
axp20x->regmap_cfg = &axp288_regmap_config;
axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
break;
case AXP806_ID:
/*
* Don't register the power key part if in slave mode or
* if there is no interrupt line.
*/
if (of_property_read_bool(axp20x->dev->of_node,
"x-powers,self-working-mode") &&
axp20x->irq > 0) {
axp20x->nr_cells = ARRAY_SIZE(axp806_self_working_cells);
axp20x->cells = axp806_self_working_cells;
} else {
axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
axp20x->cells = axp806_cells;
}
axp20x->regmap_cfg = &axp806_regmap_config;
axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
break;
case AXP809_ID:
axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
axp20x->cells = axp809_cells;
axp20x->regmap_cfg = &axp22x_regmap_config;
axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
break;
case AXP813_ID:
axp20x->nr_cells = ARRAY_SIZE(axp813_cells);
axp20x->cells = axp813_cells;
axp20x->regmap_cfg = &axp288_regmap_config;
/*
* The IRQ table given in the datasheet is incorrect.
* In IRQ enable/status registers 1, there are separate
* IRQs for ACIN and VBUS, instead of bits [7:5] being
* the same as bits [4:2]. So it shares the same IRQs
* as the AXP803, rather than the AXP288.
*/
axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
break;
case AXP15060_ID:
/*
* Don't register the power key part if there is no interrupt
* line.
*
* Since most use cases of AXP PMICs are Allwinner SOCs, board
* designers follow Allwinner's reference design and connects
* IRQ line to SOC, there's no need for those variants to deal
* with cases that IRQ isn't connected. However, AXP15660 is
* used by some other vendors' SOCs that didn't connect IRQ
* line, we need to deal with this case.
*/
if (axp20x->irq > 0) {
axp20x->nr_cells = ARRAY_SIZE(axp15060_cells);
axp20x->cells = axp15060_cells;
} else {
axp20x->nr_cells = ARRAY_SIZE(axp_regulator_only_cells);
axp20x->cells = axp_regulator_only_cells;
}
axp20x->regmap_cfg = &axp15060_regmap_config;
axp20x->regmap_irq_chip = &axp15060_regmap_irq_chip;
break;
default:
dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
return -EINVAL;
}
dev_info(dev, "AXP20x variant %s found\n",
axp20x_model_names[axp20x->variant]);
return 0;
}
EXPORT_SYMBOL(axp20x_match_device);
int axp20x_device_probe(struct axp20x_dev *axp20x)
{
int ret;
/*
* The AXP806 supports either master/standalone or slave mode.
* Slave mode allows sharing the serial bus, even with multiple
* AXP806 which all have the same hardware address.
*
* This is done with extra "serial interface address extension",
* or AXP806_BUS_ADDR_EXT, and "register address extension", or
* AXP806_REG_ADDR_EXT, registers. The former is read-only, with
* 1 bit customizable at the factory, and 1 bit depending on the
* state of an external pin. The latter is writable. The device
* will only respond to operations to its other registers when
* the these device addressing bits (in the upper 4 bits of the
* registers) match.
*
* By default we support an AXP806 chained to an AXP809 in slave
* mode. Boards which use an AXP806 in master mode can set the
* property "x-powers,master-mode" to override the default.
*/
if (axp20x->variant == AXP806_ID) {
if (of_property_read_bool(axp20x->dev->of_node,
"x-powers,master-mode") ||
of_property_read_bool(axp20x->dev->of_node,
"x-powers,self-working-mode"))
regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
else
regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
}
/* Only if there is an interrupt line connected towards the CPU. */
if (axp20x->irq > 0) {
ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
-1, axp20x->regmap_irq_chip,
&axp20x->regmap_irqc);
if (ret) {
dev_err(axp20x->dev, "failed to add irq chip: %d\n",
ret);
return ret;
}
}
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
axp20x->nr_cells, NULL, 0, NULL);
if (ret) {
dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
return ret;
}
if (axp20x->variant != AXP288_ID)
devm_register_sys_off_handler(axp20x->dev,
SYS_OFF_MODE_POWER_OFF,
SYS_OFF_PRIO_DEFAULT,
axp20x_power_off, axp20x);
dev_info(axp20x->dev, "AXP20X driver loaded\n");
return 0;
}
EXPORT_SYMBOL(axp20x_device_probe);
void axp20x_device_remove(struct axp20x_dev *axp20x)
{
mfd_remove_devices(axp20x->dev);
regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
}
EXPORT_SYMBOL(axp20x_device_remove);
MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
MODULE_AUTHOR("Carlo Caione <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/axp20x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tps65217.c
*
* TPS65217 chip family multi-function driver
*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps65217.h>
static const struct resource charger_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_AC, "AC"),
DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_USB, "USB"),
};
static const struct resource pb_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS65217_IRQ_PB, "PB"),
};
static void tps65217_irq_lock(struct irq_data *data)
{
struct tps65217 *tps = irq_data_get_irq_chip_data(data);
mutex_lock(&tps->irq_lock);
}
static void tps65217_irq_sync_unlock(struct irq_data *data)
{
struct tps65217 *tps = irq_data_get_irq_chip_data(data);
int ret;
ret = tps65217_set_bits(tps, TPS65217_REG_INT, TPS65217_INT_MASK,
tps->irq_mask, TPS65217_PROTECT_NONE);
if (ret != 0)
dev_err(tps->dev, "Failed to sync IRQ masks\n");
mutex_unlock(&tps->irq_lock);
}
static void tps65217_irq_enable(struct irq_data *data)
{
struct tps65217 *tps = irq_data_get_irq_chip_data(data);
u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT;
tps->irq_mask &= ~mask;
}
static void tps65217_irq_disable(struct irq_data *data)
{
struct tps65217 *tps = irq_data_get_irq_chip_data(data);
u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT;
tps->irq_mask |= mask;
}
static struct irq_chip tps65217_irq_chip = {
.name = "tps65217",
.irq_bus_lock = tps65217_irq_lock,
.irq_bus_sync_unlock = tps65217_irq_sync_unlock,
.irq_enable = tps65217_irq_enable,
.irq_disable = tps65217_irq_disable,
};
static struct mfd_cell tps65217s[] = {
{
.name = "tps65217-pmic",
.of_compatible = "ti,tps65217-pmic",
},
{
.name = "tps65217-bl",
.of_compatible = "ti,tps65217-bl",
},
{
.name = "tps65217-charger",
.num_resources = ARRAY_SIZE(charger_resources),
.resources = charger_resources,
.of_compatible = "ti,tps65217-charger",
},
{
.name = "tps65217-pwrbutton",
.num_resources = ARRAY_SIZE(pb_resources),
.resources = pb_resources,
.of_compatible = "ti,tps65217-pwrbutton",
},
};
static irqreturn_t tps65217_irq_thread(int irq, void *data)
{
struct tps65217 *tps = data;
unsigned int status;
bool handled = false;
int i;
int ret;
ret = tps65217_reg_read(tps, TPS65217_REG_INT, &status);
if (ret < 0) {
dev_err(tps->dev, "Failed to read IRQ status: %d\n",
ret);
return IRQ_NONE;
}
for (i = 0; i < TPS65217_NUM_IRQ; i++) {
if (status & BIT(i)) {
handle_nested_irq(irq_find_mapping(tps->irq_domain, i));
handled = true;
}
}
if (handled)
return IRQ_HANDLED;
return IRQ_NONE;
}
static int tps65217_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct tps65217 *tps = h->host_data;
irq_set_chip_data(virq, tps);
irq_set_chip_and_handler(virq, &tps65217_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
irq_set_parent(virq, tps->irq);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops tps65217_irq_domain_ops = {
.map = tps65217_irq_map,
};
static int tps65217_irq_init(struct tps65217 *tps, int irq)
{
int ret;
mutex_init(&tps->irq_lock);
tps->irq = irq;
/* Mask all interrupt sources */
tps->irq_mask = TPS65217_INT_MASK;
tps65217_set_bits(tps, TPS65217_REG_INT, TPS65217_INT_MASK,
TPS65217_INT_MASK, TPS65217_PROTECT_NONE);
tps->irq_domain = irq_domain_add_linear(tps->dev->of_node,
TPS65217_NUM_IRQ, &tps65217_irq_domain_ops, tps);
if (!tps->irq_domain) {
dev_err(tps->dev, "Could not create IRQ domain\n");
return -ENOMEM;
}
ret = devm_request_threaded_irq(tps->dev, irq, NULL,
tps65217_irq_thread, IRQF_ONESHOT,
"tps65217-irq", tps);
if (ret) {
dev_err(tps->dev, "Failed to request IRQ %d: %d\n",
irq, ret);
return ret;
}
enable_irq_wake(irq);
return 0;
}
/**
* tps65217_reg_read: Read a single tps65217 register.
*
* @tps: Device to read from.
* @reg: Register to read.
* @val: Contians the value
*/
int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
unsigned int *val)
{
return regmap_read(tps->regmap, reg, val);
}
EXPORT_SYMBOL_GPL(tps65217_reg_read);
/**
* tps65217_reg_write: Write a single tps65217 register.
*
* @tps: Device to write to.
* @reg: Register to write to.
* @val: Value to write.
* @level: Password protected level
*/
int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
unsigned int val, unsigned int level)
{
int ret;
unsigned int xor_reg_val;
switch (level) {
case TPS65217_PROTECT_NONE:
return regmap_write(tps->regmap, reg, val);
case TPS65217_PROTECT_L1:
xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
xor_reg_val);
if (ret < 0)
return ret;
return regmap_write(tps->regmap, reg, val);
case TPS65217_PROTECT_L2:
xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK;
ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
xor_reg_val);
if (ret < 0)
return ret;
ret = regmap_write(tps->regmap, reg, val);
if (ret < 0)
return ret;
ret = regmap_write(tps->regmap, TPS65217_REG_PASSWORD,
xor_reg_val);
if (ret < 0)
return ret;
return regmap_write(tps->regmap, reg, val);
default:
return -EINVAL;
}
}
EXPORT_SYMBOL_GPL(tps65217_reg_write);
/**
* tps65217_update_bits: Modify bits w.r.t mask, val and level.
*
* @tps: Device to write to.
* @reg: Register to read-write to.
* @mask: Mask.
* @val: Value to write.
* @level: Password protected level
*/
static int tps65217_update_bits(struct tps65217 *tps, unsigned int reg,
unsigned int mask, unsigned int val, unsigned int level)
{
int ret;
unsigned int data;
ret = tps65217_reg_read(tps, reg, &data);
if (ret) {
dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
return ret;
}
data &= ~mask;
data |= val & mask;
ret = tps65217_reg_write(tps, reg, data, level);
if (ret)
dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
return ret;
}
int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
unsigned int mask, unsigned int val, unsigned int level)
{
return tps65217_update_bits(tps, reg, mask, val, level);
}
EXPORT_SYMBOL_GPL(tps65217_set_bits);
int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
unsigned int mask, unsigned int level)
{
return tps65217_update_bits(tps, reg, mask, 0, level);
}
EXPORT_SYMBOL_GPL(tps65217_clear_bits);
static bool tps65217_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TPS65217_REG_INT:
return true;
default:
return false;
}
}
static const struct regmap_config tps65217_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TPS65217_REG_MAX,
.volatile_reg = tps65217_volatile_reg,
};
static const struct of_device_id tps65217_of_match[] = {
{ .compatible = "ti,tps65217"},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, tps65217_of_match);
static int tps65217_probe(struct i2c_client *client)
{
struct tps65217 *tps;
unsigned int version;
bool status_off = false;
int ret;
status_off = of_property_read_bool(client->dev.of_node,
"ti,pmic-shutdown-controller");
tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
i2c_set_clientdata(client, tps);
tps->dev = &client->dev;
tps->regmap = devm_regmap_init_i2c(client, &tps65217_regmap_config);
if (IS_ERR(tps->regmap)) {
ret = PTR_ERR(tps->regmap);
dev_err(tps->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
if (client->irq) {
tps65217_irq_init(tps, client->irq);
} else {
int i;
/* Don't tell children about IRQ resources which won't fire */
for (i = 0; i < ARRAY_SIZE(tps65217s); i++)
tps65217s[i].num_resources = 0;
}
ret = devm_mfd_add_devices(tps->dev, -1, tps65217s,
ARRAY_SIZE(tps65217s), NULL, 0,
tps->irq_domain);
if (ret < 0) {
dev_err(tps->dev, "mfd_add_devices failed: %d\n", ret);
return ret;
}
ret = tps65217_reg_read(tps, TPS65217_REG_CHIPID, &version);
if (ret < 0) {
dev_err(tps->dev, "Failed to read revision register: %d\n",
ret);
return ret;
}
/* Set the PMIC to shutdown on PWR_EN toggle */
if (status_off) {
ret = tps65217_set_bits(tps, TPS65217_REG_STATUS,
TPS65217_STATUS_OFF, TPS65217_STATUS_OFF,
TPS65217_PROTECT_NONE);
if (ret)
dev_warn(tps->dev, "unable to set the status OFF\n");
}
dev_info(tps->dev, "TPS65217 ID %#x version 1.%d\n",
(version & TPS65217_CHIPID_CHIP_MASK) >> 4,
version & TPS65217_CHIPID_REV_MASK);
return 0;
}
static void tps65217_remove(struct i2c_client *client)
{
struct tps65217 *tps = i2c_get_clientdata(client);
unsigned int virq;
int i;
for (i = 0; i < TPS65217_NUM_IRQ; i++) {
virq = irq_find_mapping(tps->irq_domain, i);
if (virq)
irq_dispose_mapping(virq);
}
irq_domain_remove(tps->irq_domain);
tps->irq_domain = NULL;
}
static const struct i2c_device_id tps65217_id_table[] = {
{"tps65217", TPS65217},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, tps65217_id_table);
static struct i2c_driver tps65217_driver = {
.driver = {
.name = "tps65217",
.of_match_table = tps65217_of_match,
},
.id_table = tps65217_id_table,
.probe = tps65217_probe,
.remove = tps65217_remove,
};
static int __init tps65217_init(void)
{
return i2c_add_driver(&tps65217_driver);
}
subsys_initcall(tps65217_init);
static void __exit tps65217_exit(void)
{
i2c_del_driver(&tps65217_driver);
}
module_exit(tps65217_exit);
MODULE_AUTHOR("AnilKumar Ch <[email protected]>");
MODULE_DESCRIPTION("TPS65217 chip family multi-function driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/tps65217.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* SPI driver for Renesas Synchronization Management Unit (SMU) devices.
*
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rsmu.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include "rsmu.h"
#define RSMU_CM_PAGE_ADDR 0x7C
#define RSMU_SABRE_PAGE_ADDR 0x7F
#define RSMU_PAGE_MASK 0xFFFFFF80
#define RSMU_ADDR_MASK 0x7F
static int rsmu_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
{
struct spi_device *client = to_spi_device(rsmu->dev);
struct spi_transfer xfer = {0};
struct spi_message msg;
u8 cmd[RSMU_MAX_READ_COUNT + 1] = {0};
u8 rsp[RSMU_MAX_READ_COUNT + 1] = {0};
int ret;
if (bytes > RSMU_MAX_READ_COUNT)
return -EINVAL;
cmd[0] = reg | 0x80;
xfer.rx_buf = rsp;
xfer.len = bytes + 1;
xfer.tx_buf = cmd;
xfer.bits_per_word = client->bits_per_word;
xfer.speed_hz = client->max_speed_hz;
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
/*
* 4-wire SPI is a shift register, so for every byte you send,
* you get one back at the same time. Example read from 0xC024,
* which has value of 0x2D
*
* MOSI:
* 7C 00 C0 #Set page register
* A4 00 #MSB is set, so this is read command
* MISO:
* XX 2D #XX is a dummy byte from sending A4 and we
* need to throw it away
*/
ret = spi_sync(client, &msg);
if (ret >= 0)
memcpy(buf, &rsp[1], xfer.len-1);
return ret;
}
static int rsmu_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
{
struct spi_device *client = to_spi_device(rsmu->dev);
struct spi_transfer xfer = {0};
struct spi_message msg;
u8 cmd[RSMU_MAX_WRITE_COUNT + 1] = {0};
if (bytes > RSMU_MAX_WRITE_COUNT)
return -EINVAL;
cmd[0] = reg;
memcpy(&cmd[1], buf, bytes);
xfer.len = bytes + 1;
xfer.tx_buf = cmd;
xfer.bits_per_word = client->bits_per_word;
xfer.speed_hz = client->max_speed_hz;
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
return spi_sync(client, &msg);
}
/*
* 1-byte (1B) offset addressing:
* 16-bit register address: the lower 7 bits of the register address come
* from the offset addr byte and the upper 9 bits come from the page register.
*/
static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg)
{
u8 page_reg;
u8 buf[4];
u16 bytes;
u32 page;
int err;
switch (rsmu->type) {
case RSMU_CM:
/* Do not modify page register for none-scsr registers */
if (reg < RSMU_CM_SCSR_BASE)
return 0;
page_reg = RSMU_CM_PAGE_ADDR;
page = reg & RSMU_PAGE_MASK;
buf[0] = (u8)(page & 0xff);
buf[1] = (u8)((page >> 8) & 0xff);
buf[2] = (u8)((page >> 16) & 0xff);
buf[3] = (u8)((page >> 24) & 0xff);
bytes = 4;
break;
case RSMU_SABRE:
/* Do not modify page register if reg is page register itself */
if ((reg & RSMU_ADDR_MASK) == RSMU_ADDR_MASK)
return 0;
page_reg = RSMU_SABRE_PAGE_ADDR;
page = reg & RSMU_PAGE_MASK;
/* The three page bits are located in the single Page Register */
buf[0] = (u8)((page >> 7) & 0x7);
bytes = 1;
break;
default:
dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
return -ENODEV;
}
/* Simply return if we are on the same page */
if (rsmu->page == page)
return 0;
err = rsmu_write_device(rsmu, page_reg, buf, bytes);
if (err)
dev_err(rsmu->dev, "Failed to set page offset 0x%x\n", page);
else
/* Remember the last page */
rsmu->page = page;
return err;
}
static int rsmu_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);
u8 addr = (u8)(reg & RSMU_ADDR_MASK);
int err;
err = rsmu_write_page_register(rsmu, reg);
if (err)
return err;
err = rsmu_read_device(rsmu, addr, (u8 *)val, 1);
if (err)
dev_err(rsmu->dev, "Failed to read offset address 0x%x\n", addr);
return err;
}
static int rsmu_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);
u8 addr = (u8)(reg & RSMU_ADDR_MASK);
u8 data = (u8)val;
int err;
err = rsmu_write_page_register(rsmu, reg);
if (err)
return err;
err = rsmu_write_device(rsmu, addr, &data, 1);
if (err)
dev_err(rsmu->dev,
"Failed to write offset address 0x%x\n", addr);
return err;
}
static const struct regmap_config rsmu_cm_regmap_config = {
.reg_bits = 32,
.val_bits = 8,
.max_register = 0x20120000,
.reg_read = rsmu_reg_read,
.reg_write = rsmu_reg_write,
.cache_type = REGCACHE_NONE,
};
static const struct regmap_config rsmu_sabre_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = 0x400,
.reg_read = rsmu_reg_read,
.reg_write = rsmu_reg_write,
.cache_type = REGCACHE_NONE,
};
static int rsmu_spi_probe(struct spi_device *client)
{
const struct spi_device_id *id = spi_get_device_id(client);
const struct regmap_config *cfg;
struct rsmu_ddata *rsmu;
int ret;
rsmu = devm_kzalloc(&client->dev, sizeof(*rsmu), GFP_KERNEL);
if (!rsmu)
return -ENOMEM;
spi_set_drvdata(client, rsmu);
rsmu->dev = &client->dev;
rsmu->type = (enum rsmu_type)id->driver_data;
/* Initialize regmap */
switch (rsmu->type) {
case RSMU_CM:
cfg = &rsmu_cm_regmap_config;
break;
case RSMU_SABRE:
cfg = &rsmu_sabre_regmap_config;
break;
default:
dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
return -ENODEV;
}
rsmu->regmap = devm_regmap_init(&client->dev, NULL, client, cfg);
if (IS_ERR(rsmu->regmap)) {
ret = PTR_ERR(rsmu->regmap);
dev_err(rsmu->dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
return rsmu_core_init(rsmu);
}
static void rsmu_spi_remove(struct spi_device *client)
{
struct rsmu_ddata *rsmu = spi_get_drvdata(client);
rsmu_core_exit(rsmu);
}
static const struct spi_device_id rsmu_spi_id[] = {
{ "8a34000", RSMU_CM },
{ "8a34001", RSMU_CM },
{ "82p33810", RSMU_SABRE },
{ "82p33811", RSMU_SABRE },
{}
};
MODULE_DEVICE_TABLE(spi, rsmu_spi_id);
static const struct of_device_id rsmu_spi_of_match[] = {
{ .compatible = "idt,8a34000", .data = (void *)RSMU_CM },
{ .compatible = "idt,8a34001", .data = (void *)RSMU_CM },
{ .compatible = "idt,82p33810", .data = (void *)RSMU_SABRE },
{ .compatible = "idt,82p33811", .data = (void *)RSMU_SABRE },
{}
};
MODULE_DEVICE_TABLE(of, rsmu_spi_of_match);
static struct spi_driver rsmu_spi_driver = {
.driver = {
.name = "rsmu-spi",
.of_match_table = rsmu_spi_of_match,
},
.probe = rsmu_spi_probe,
.remove = rsmu_spi_remove,
.id_table = rsmu_spi_id,
};
static int __init rsmu_spi_init(void)
{
return spi_register_driver(&rsmu_spi_driver);
}
subsys_initcall(rsmu_spi_init);
static void __exit rsmu_spi_exit(void)
{
spi_unregister_driver(&rsmu_spi_driver);
}
module_exit(rsmu_spi_exit);
MODULE_DESCRIPTION("Renesas SMU SPI driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/rsmu_spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Copyright (C) 2012 ARM Limited
*/
#include <linux/gpio/driver.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_data/syscon.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/stat.h>
#define SYS_ID 0x000
#define SYS_SW 0x004
#define SYS_LED 0x008
#define SYS_100HZ 0x024
#define SYS_FLAGSSET 0x030
#define SYS_FLAGSCLR 0x034
#define SYS_NVFLAGS 0x038
#define SYS_NVFLAGSSET 0x038
#define SYS_NVFLAGSCLR 0x03c
#define SYS_MCI 0x048
#define SYS_FLASH 0x04c
#define SYS_CFGSW 0x058
#define SYS_24MHZ 0x05c
#define SYS_MISC 0x060
#define SYS_DMA 0x064
#define SYS_PROCID0 0x084
#define SYS_PROCID1 0x088
#define SYS_CFGDATA 0x0a0
#define SYS_CFGCTRL 0x0a4
#define SYS_CFGSTAT 0x0a8
/* The sysreg block is just a random collection of various functions... */
static struct bgpio_pdata vexpress_sysreg_sys_led_pdata = {
.label = "sys_led",
.base = -1,
.ngpio = 8,
};
static struct bgpio_pdata vexpress_sysreg_sys_mci_pdata = {
.label = "sys_mci",
.base = -1,
.ngpio = 2,
};
static struct bgpio_pdata vexpress_sysreg_sys_flash_pdata = {
.label = "sys_flash",
.base = -1,
.ngpio = 1,
};
static struct mfd_cell vexpress_sysreg_cells[] = {
{
.name = "basic-mmio-gpio",
.of_compatible = "arm,vexpress-sysreg,sys_led",
.num_resources = 1,
.resources = &DEFINE_RES_MEM_NAMED(SYS_LED, 0x4, "dat"),
.platform_data = &vexpress_sysreg_sys_led_pdata,
.pdata_size = sizeof(vexpress_sysreg_sys_led_pdata),
}, {
.name = "basic-mmio-gpio",
.of_compatible = "arm,vexpress-sysreg,sys_mci",
.num_resources = 1,
.resources = &DEFINE_RES_MEM_NAMED(SYS_MCI, 0x4, "dat"),
.platform_data = &vexpress_sysreg_sys_mci_pdata,
.pdata_size = sizeof(vexpress_sysreg_sys_mci_pdata),
}, {
.name = "basic-mmio-gpio",
.of_compatible = "arm,vexpress-sysreg,sys_flash",
.num_resources = 1,
.resources = &DEFINE_RES_MEM_NAMED(SYS_FLASH, 0x4, "dat"),
.platform_data = &vexpress_sysreg_sys_flash_pdata,
.pdata_size = sizeof(vexpress_sysreg_sys_flash_pdata),
}, {
.name = "vexpress-syscfg",
.num_resources = 1,
.resources = &DEFINE_RES_MEM(SYS_MISC, 0x4c),
}
};
static int vexpress_sysreg_probe(struct platform_device *pdev)
{
struct resource *mem;
void __iomem *base;
struct gpio_chip *mmc_gpio_chip;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem)
return -EINVAL;
base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
if (!base)
return -ENOMEM;
/*
* Duplicated SYS_MCI pseudo-GPIO controller for compatibility with
* older trees using sysreg node for MMC control lines.
*/
mmc_gpio_chip = devm_kzalloc(&pdev->dev, sizeof(*mmc_gpio_chip),
GFP_KERNEL);
if (!mmc_gpio_chip)
return -ENOMEM;
bgpio_init(mmc_gpio_chip, &pdev->dev, 0x4, base + SYS_MCI,
NULL, NULL, NULL, NULL, 0);
mmc_gpio_chip->ngpio = 2;
devm_gpiochip_add_data(&pdev->dev, mmc_gpio_chip, NULL);
return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
vexpress_sysreg_cells,
ARRAY_SIZE(vexpress_sysreg_cells), mem, 0, NULL);
}
static const struct of_device_id vexpress_sysreg_match[] = {
{ .compatible = "arm,vexpress-sysreg", },
{},
};
MODULE_DEVICE_TABLE(of, vexpress_sysreg_match);
static struct platform_driver vexpress_sysreg_driver = {
.driver = {
.name = "vexpress-sysreg",
.of_match_table = vexpress_sysreg_match,
},
.probe = vexpress_sysreg_probe,
};
module_platform_driver(vexpress_sysreg_driver);
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/vexpress-sysreg.c |
// SPDX-License-Identifier: GPL-2.0
//
// Driver for TPS65219 Integrated Power Management Integrated Chips (PMIC)
//
// Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
#include <linux/i2c.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps65219.h>
static int tps65219_warm_reset(struct tps65219 *tps)
{
return regmap_update_bits(tps->regmap, TPS65219_REG_MFP_CTRL,
TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK,
TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK);
}
static int tps65219_cold_reset(struct tps65219 *tps)
{
return regmap_update_bits(tps->regmap, TPS65219_REG_MFP_CTRL,
TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK,
TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK);
}
static int tps65219_soft_shutdown(struct tps65219 *tps)
{
return regmap_update_bits(tps->regmap, TPS65219_REG_MFP_CTRL,
TPS65219_MFP_I2C_OFF_REQ_MASK,
TPS65219_MFP_I2C_OFF_REQ_MASK);
}
static int tps65219_power_off_handler(struct sys_off_data *data)
{
tps65219_soft_shutdown(data->cb_data);
return NOTIFY_DONE;
}
static int tps65219_restart(struct tps65219 *tps, unsigned long reboot_mode)
{
if (reboot_mode == REBOOT_WARM)
tps65219_warm_reset(tps);
else
tps65219_cold_reset(tps);
return NOTIFY_DONE;
}
static int tps65219_restart_handler(struct sys_off_data *data)
{
tps65219_restart(data->cb_data, data->mode);
return NOTIFY_DONE;
}
static const struct resource tps65219_pwrbutton_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_FALLING_EDGE_DETECT, "falling"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_RISING_EDGE_DETECT, "rising"),
};
static const struct resource tps65219_regulator_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_SCG, "LDO3_SCG"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_OC, "LDO3_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_UV, "LDO3_UV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_SCG, "LDO4_SCG"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_OC, "LDO4_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_UV, "LDO4_UV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_SCG, "LDO1_SCG"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_OC, "LDO1_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_UV, "LDO1_UV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_SCG, "LDO2_SCG"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_OC, "LDO2_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_UV, "LDO2_UV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_SCG, "BUCK3_SCG"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_OC, "BUCK3_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_NEG_OC, "BUCK3_NEG_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_UV, "BUCK3_UV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_SCG, "BUCK1_SCG"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_OC, "BUCK1_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_NEG_OC, "BUCK1_NEG_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_UV, "BUCK1_UV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_SCG, "BUCK2_SCG"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_OC, "BUCK2_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_NEG_OC, "BUCK2_NEG_OC"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_UV, "BUCK2_UV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV, "BUCK1_RV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV, "BUCK2_RV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV, "BUCK3_RV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV, "LDO1_RV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_RV, "LDO2_RV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_RV, "LDO3_RV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_RV, "LDO4_RV"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV_SD, "BUCK1_RV_SD"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV_SD, "BUCK2_RV_SD"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV_SD, "BUCK3_RV_SD"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV_SD, "LDO1_RV_SD"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_RV_SD, "LDO2_RV_SD"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_RV_SD, "LDO3_RV_SD"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_RV_SD, "LDO4_RV_SD"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_TIMEOUT, "TIMEOUT"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_WARM, "SENSOR_3_WARM"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_WARM, "SENSOR_2_WARM"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_WARM, "SENSOR_1_WARM"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_WARM, "SENSOR_0_WARM"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_HOT, "SENSOR_3_HOT"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_HOT, "SENSOR_2_HOT"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_HOT, "SENSOR_1_HOT"),
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"),
};
static const struct mfd_cell tps65219_cells[] = {
{
.name = "tps65219-regulator",
.resources = tps65219_regulator_resources,
.num_resources = ARRAY_SIZE(tps65219_regulator_resources),
},
{ .name = "tps65219-gpio", },
};
static const struct mfd_cell tps65219_pwrbutton_cell = {
.name = "tps65219-pwrbutton",
.resources = tps65219_pwrbutton_resources,
.num_resources = ARRAY_SIZE(tps65219_pwrbutton_resources),
};
static const struct regmap_config tps65219_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TPS65219_REG_FACTORY_CONFIG_2,
};
/*
* Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
* access corect sub-IRQ registers based on bits that are set in main IRQ
* register.
*/
/* Timeout Residual Voltage Shutdown */
static unsigned int bit0_offsets[] = { TPS65219_REG_INT_TO_RV_POS };
static unsigned int bit1_offsets[] = { TPS65219_REG_INT_RV_POS }; /* Residual Voltage */
static unsigned int bit2_offsets[] = { TPS65219_REG_INT_SYS_POS }; /* System */
static unsigned int bit3_offsets[] = { TPS65219_REG_INT_BUCK_1_2_POS }; /* Buck 1-2 */
static unsigned int bit4_offsets[] = { TPS65219_REG_INT_BUCK_3_POS }; /* Buck 3 */
static unsigned int bit5_offsets[] = { TPS65219_REG_INT_LDO_1_2_POS }; /* LDO 1-2 */
static unsigned int bit6_offsets[] = { TPS65219_REG_INT_LDO_3_4_POS }; /* LDO 3-4 */
static unsigned int bit7_offsets[] = { TPS65219_REG_INT_PB_POS }; /* Power Button */
static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = {
REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
};
#define TPS65219_REGMAP_IRQ_REG(int_name, register_position) \
REGMAP_IRQ_REG(int_name, register_position, int_name##_MASK)
static struct regmap_irq tps65219_irqs[] = {
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_SCG, TPS65219_REG_INT_LDO_3_4_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_OC, TPS65219_REG_INT_LDO_3_4_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_UV, TPS65219_REG_INT_LDO_3_4_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_SCG, TPS65219_REG_INT_LDO_3_4_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_OC, TPS65219_REG_INT_LDO_3_4_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_UV, TPS65219_REG_INT_LDO_3_4_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_SCG, TPS65219_REG_INT_LDO_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_OC, TPS65219_REG_INT_LDO_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_UV, TPS65219_REG_INT_LDO_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_SCG, TPS65219_REG_INT_LDO_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_OC, TPS65219_REG_INT_LDO_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_UV, TPS65219_REG_INT_LDO_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_SCG, TPS65219_REG_INT_BUCK_3_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_OC, TPS65219_REG_INT_BUCK_3_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_NEG_OC, TPS65219_REG_INT_BUCK_3_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_UV, TPS65219_REG_INT_BUCK_3_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_SCG, TPS65219_REG_INT_BUCK_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_OC, TPS65219_REG_INT_BUCK_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_UV, TPS65219_REG_INT_BUCK_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_SCG, TPS65219_REG_INT_BUCK_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_OC, TPS65219_REG_INT_BUCK_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_UV, TPS65219_REG_INT_BUCK_1_2_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_WARM, TPS65219_REG_INT_SYS_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_WARM, TPS65219_REG_INT_SYS_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_WARM, TPS65219_REG_INT_SYS_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_WARM, TPS65219_REG_INT_SYS_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_HOT, TPS65219_REG_INT_SYS_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_HOT, TPS65219_REG_INT_SYS_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_HOT, TPS65219_REG_INT_SYS_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_HOT, TPS65219_REG_INT_SYS_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV, TPS65219_REG_INT_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV, TPS65219_REG_INT_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV, TPS65219_REG_INT_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV, TPS65219_REG_INT_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_RV, TPS65219_REG_INT_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_RV, TPS65219_REG_INT_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_RV, TPS65219_REG_INT_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV_SD, TPS65219_REG_INT_TO_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV_SD, TPS65219_REG_INT_TO_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV_SD, TPS65219_REG_INT_TO_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV_SD, TPS65219_REG_INT_TO_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_RV_SD, TPS65219_REG_INT_TO_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_RV_SD, TPS65219_REG_INT_TO_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_RV_SD, TPS65219_REG_INT_TO_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_TIMEOUT, TPS65219_REG_INT_TO_RV_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_FALLING_EDGE_DETECT, TPS65219_REG_INT_PB_POS),
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS),
};
static struct regmap_irq_chip tps65219_irq_chip = {
.name = "tps65219_irq",
.main_status = TPS65219_REG_INT_SOURCE,
.num_main_regs = 1,
.num_main_status_bits = 8,
.irqs = tps65219_irqs,
.num_irqs = ARRAY_SIZE(tps65219_irqs),
.status_base = TPS65219_REG_INT_LDO_3_4,
.ack_base = TPS65219_REG_INT_LDO_3_4,
.clear_ack = 1,
.num_regs = 8,
.sub_reg_offsets = tps65219_sub_irq_offsets,
};
static int tps65219_probe(struct i2c_client *client)
{
struct tps65219 *tps;
unsigned int chipid;
bool pwr_button;
int ret;
tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
i2c_set_clientdata(client, tps);
tps->dev = &client->dev;
tps->regmap = devm_regmap_init_i2c(client, &tps65219_regmap_config);
if (IS_ERR(tps->regmap)) {
ret = PTR_ERR(tps->regmap);
dev_err(tps->dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
ret = devm_regmap_add_irq_chip(&client->dev, tps->regmap, client->irq,
IRQF_ONESHOT, 0, &tps65219_irq_chip,
&tps->irq_data);
if (ret)
return ret;
ret = regmap_read(tps->regmap, TPS65219_REG_TI_DEV_ID, &chipid);
if (ret) {
dev_err(tps->dev, "Failed to read device ID: %d\n", ret);
return ret;
}
ret = devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO,
tps65219_cells, ARRAY_SIZE(tps65219_cells),
NULL, 0, regmap_irq_get_domain(tps->irq_data));
if (ret) {
dev_err(tps->dev, "Failed to add child devices: %d\n", ret);
return ret;
}
pwr_button = of_property_read_bool(tps->dev->of_node, "ti,power-button");
if (pwr_button) {
ret = devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO,
&tps65219_pwrbutton_cell, 1, NULL, 0,
regmap_irq_get_domain(tps->irq_data));
if (ret) {
dev_err(tps->dev, "Failed to add power-button: %d\n", ret);
return ret;
}
}
ret = devm_register_restart_handler(tps->dev,
tps65219_restart_handler,
tps);
if (ret) {
dev_err(tps->dev, "cannot register restart handler, %d\n", ret);
return ret;
}
ret = devm_register_power_off_handler(tps->dev,
tps65219_power_off_handler,
tps);
if (ret) {
dev_err(tps->dev, "failed to register power-off handler: %d\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id of_tps65219_match_table[] = {
{ .compatible = "ti,tps65219", },
{}
};
MODULE_DEVICE_TABLE(of, of_tps65219_match_table);
static struct i2c_driver tps65219_driver = {
.driver = {
.name = "tps65219",
.of_match_table = of_tps65219_match_table,
},
.probe = tps65219_probe,
};
module_i2c_driver(tps65219_driver);
MODULE_AUTHOR("Jerome Neanne <[email protected]>");
MODULE_DESCRIPTION("TPS65219 power management IC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/tps65219.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core MFD support for Cirrus Logic Madera codecs
*
* Copyright (C) 2015-2018 Cirrus Logic
*/
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/of_regulator.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
#define CS47L15_SILICON_ID 0x6370
#define CS47L35_SILICON_ID 0x6360
#define CS47L85_SILICON_ID 0x6338
#define CS47L90_SILICON_ID 0x6364
#define CS47L92_SILICON_ID 0x6371
#define MADERA_32KZ_MCLK2 1
#define MADERA_RESET_MIN_US 2000
#define MADERA_RESET_MAX_US 3000
#define ERRATA_DCVDD_MIN_US 10000
#define ERRATA_DCVDD_MAX_US 15000
static const char * const madera_core_supplies[] = {
"AVDD",
"DBVDD1",
};
static const struct mfd_cell madera_ldo1_devs[] = {
{
.name = "madera-ldo1",
.level = MFD_DEP_LEVEL_HIGH,
},
};
static const char * const cs47l15_supplies[] = {
"MICVDD",
"CPVDD1",
"SPKVDD",
};
static const struct mfd_cell cs47l15_devs[] = {
{ .name = "madera-pinctrl", },
{ .name = "madera-irq", },
{ .name = "madera-gpio", },
{
.name = "madera-extcon",
.parent_supplies = cs47l15_supplies,
.num_parent_supplies = 1, /* We only need MICVDD */
},
{
.name = "cs47l15-codec",
.parent_supplies = cs47l15_supplies,
.num_parent_supplies = ARRAY_SIZE(cs47l15_supplies),
},
};
static const char * const cs47l35_supplies[] = {
"MICVDD",
"DBVDD2",
"CPVDD1",
"CPVDD2",
"SPKVDD",
};
static const struct mfd_cell cs47l35_devs[] = {
{ .name = "madera-pinctrl", },
{ .name = "madera-irq", },
{ .name = "madera-micsupp", },
{ .name = "madera-gpio", },
{
.name = "madera-extcon",
.parent_supplies = cs47l35_supplies,
.num_parent_supplies = 1, /* We only need MICVDD */
},
{
.name = "cs47l35-codec",
.parent_supplies = cs47l35_supplies,
.num_parent_supplies = ARRAY_SIZE(cs47l35_supplies),
},
};
static const char * const cs47l85_supplies[] = {
"MICVDD",
"DBVDD2",
"DBVDD3",
"DBVDD4",
"CPVDD1",
"CPVDD2",
"SPKVDDL",
"SPKVDDR",
};
static const struct mfd_cell cs47l85_devs[] = {
{ .name = "madera-pinctrl", },
{ .name = "madera-irq", },
{ .name = "madera-micsupp", },
{ .name = "madera-gpio", },
{
.name = "madera-extcon",
.parent_supplies = cs47l85_supplies,
.num_parent_supplies = 1, /* We only need MICVDD */
},
{
.name = "cs47l85-codec",
.parent_supplies = cs47l85_supplies,
.num_parent_supplies = ARRAY_SIZE(cs47l85_supplies),
},
};
static const char * const cs47l90_supplies[] = {
"MICVDD",
"DBVDD2",
"DBVDD3",
"DBVDD4",
"CPVDD1",
"CPVDD2",
};
static const struct mfd_cell cs47l90_devs[] = {
{ .name = "madera-pinctrl", },
{ .name = "madera-irq", },
{ .name = "madera-micsupp", },
{ .name = "madera-gpio", },
{
.name = "madera-extcon",
.parent_supplies = cs47l90_supplies,
.num_parent_supplies = 1, /* We only need MICVDD */
},
{
.name = "cs47l90-codec",
.parent_supplies = cs47l90_supplies,
.num_parent_supplies = ARRAY_SIZE(cs47l90_supplies),
},
};
static const char * const cs47l92_supplies[] = {
"MICVDD",
"CPVDD1",
"CPVDD2",
};
static const struct mfd_cell cs47l92_devs[] = {
{ .name = "madera-pinctrl", },
{ .name = "madera-irq", },
{ .name = "madera-micsupp", },
{ .name = "madera-gpio", },
{
.name = "madera-extcon",
.parent_supplies = cs47l92_supplies,
.num_parent_supplies = 1, /* We only need MICVDD */
},
{
.name = "cs47l92-codec",
.parent_supplies = cs47l92_supplies,
.num_parent_supplies = ARRAY_SIZE(cs47l92_supplies),
},
};
/* Used by madera-i2c and madera-spi drivers */
const char *madera_name_from_type(enum madera_type type)
{
switch (type) {
case CS47L15:
return "CS47L15";
case CS47L35:
return "CS47L35";
case CS47L85:
return "CS47L85";
case CS47L90:
return "CS47L90";
case CS47L91:
return "CS47L91";
case CS42L92:
return "CS42L92";
case CS47L92:
return "CS47L92";
case CS47L93:
return "CS47L93";
case WM1840:
return "WM1840";
default:
return "Unknown";
}
}
EXPORT_SYMBOL_GPL(madera_name_from_type);
#define MADERA_BOOT_POLL_INTERVAL_USEC 5000
#define MADERA_BOOT_POLL_TIMEOUT_USEC 25000
static int madera_wait_for_boot_noack(struct madera *madera)
{
ktime_t timeout;
unsigned int val = 0;
int ret = 0;
/*
* We can't use an interrupt as we need to runtime resume to do so,
* so we poll the status bit. This won't race with the interrupt
* handler because it will be blocked on runtime resume.
* The chip could NAK a read request while it is booting so ignore
* errors from regmap_read.
*/
timeout = ktime_add_us(ktime_get(), MADERA_BOOT_POLL_TIMEOUT_USEC);
regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_1, &val);
while (!(val & MADERA_BOOT_DONE_STS1) &&
!ktime_after(ktime_get(), timeout)) {
usleep_range(MADERA_BOOT_POLL_INTERVAL_USEC / 2,
MADERA_BOOT_POLL_INTERVAL_USEC);
regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_1, &val);
}
if (!(val & MADERA_BOOT_DONE_STS1)) {
dev_err(madera->dev, "Polling BOOT_DONE_STS timed out\n");
ret = -ETIMEDOUT;
}
return ret;
}
static int madera_wait_for_boot(struct madera *madera)
{
int ret = madera_wait_for_boot_noack(madera);
/*
* BOOT_DONE defaults to unmasked on boot so we must ack it.
* Do this even after a timeout to avoid interrupt storms.
*/
regmap_write(madera->regmap, MADERA_IRQ1_STATUS_1,
MADERA_BOOT_DONE_EINT1);
pm_runtime_mark_last_busy(madera->dev);
return ret;
}
static int madera_soft_reset(struct madera *madera)
{
int ret;
ret = regmap_write(madera->regmap, MADERA_SOFTWARE_RESET, 0);
if (ret != 0) {
dev_err(madera->dev, "Failed to soft reset device: %d\n", ret);
return ret;
}
/* Allow time for internal clocks to startup after reset */
usleep_range(MADERA_RESET_MIN_US, MADERA_RESET_MAX_US);
return 0;
}
static void madera_enable_hard_reset(struct madera *madera)
{
/*
* There are many existing out-of-tree users of these codecs that we
* can't break so preserve the expected behaviour of setting the line
* low to assert reset.
*/
gpiod_set_raw_value_cansleep(madera->pdata.reset, 0);
}
static void madera_disable_hard_reset(struct madera *madera)
{
gpiod_set_raw_value_cansleep(madera->pdata.reset, 1);
usleep_range(MADERA_RESET_MIN_US, MADERA_RESET_MAX_US);
}
static int __maybe_unused madera_runtime_resume(struct device *dev)
{
struct madera *madera = dev_get_drvdata(dev);
int ret;
dev_dbg(dev, "Leaving sleep mode\n");
if (!madera->reset_errata)
madera_enable_hard_reset(madera);
ret = regulator_enable(madera->dcvdd);
if (ret) {
dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
return ret;
}
regcache_cache_only(madera->regmap, false);
regcache_cache_only(madera->regmap_32bit, false);
if (madera->reset_errata)
usleep_range(ERRATA_DCVDD_MIN_US, ERRATA_DCVDD_MAX_US);
else
madera_disable_hard_reset(madera);
if (!madera->pdata.reset || madera->reset_errata) {
ret = madera_wait_for_boot(madera);
if (ret)
goto err;
ret = madera_soft_reset(madera);
if (ret) {
dev_err(dev, "Failed to reset: %d\n", ret);
goto err;
}
}
ret = madera_wait_for_boot(madera);
if (ret)
goto err;
ret = regcache_sync(madera->regmap);
if (ret) {
dev_err(dev, "Failed to restore 16-bit register cache\n");
goto err;
}
ret = regcache_sync(madera->regmap_32bit);
if (ret) {
dev_err(dev, "Failed to restore 32-bit register cache\n");
goto err;
}
return 0;
err:
regcache_cache_only(madera->regmap_32bit, true);
regcache_cache_only(madera->regmap, true);
regulator_disable(madera->dcvdd);
return ret;
}
static int __maybe_unused madera_runtime_suspend(struct device *dev)
{
struct madera *madera = dev_get_drvdata(dev);
dev_dbg(madera->dev, "Entering sleep mode\n");
regcache_cache_only(madera->regmap, true);
regcache_mark_dirty(madera->regmap);
regcache_cache_only(madera->regmap_32bit, true);
regcache_mark_dirty(madera->regmap_32bit);
regulator_disable(madera->dcvdd);
return 0;
}
const struct dev_pm_ops madera_pm_ops = {
SET_RUNTIME_PM_OPS(madera_runtime_suspend,
madera_runtime_resume,
NULL)
};
EXPORT_SYMBOL_GPL(madera_pm_ops);
const struct of_device_id madera_of_match[] = {
{ .compatible = "cirrus,cs47l15", .data = (void *)CS47L15 },
{ .compatible = "cirrus,cs47l35", .data = (void *)CS47L35 },
{ .compatible = "cirrus,cs47l85", .data = (void *)CS47L85 },
{ .compatible = "cirrus,cs47l90", .data = (void *)CS47L90 },
{ .compatible = "cirrus,cs47l91", .data = (void *)CS47L91 },
{ .compatible = "cirrus,cs42l92", .data = (void *)CS42L92 },
{ .compatible = "cirrus,cs47l92", .data = (void *)CS47L92 },
{ .compatible = "cirrus,cs47l93", .data = (void *)CS47L93 },
{ .compatible = "cirrus,wm1840", .data = (void *)WM1840 },
{}
};
MODULE_DEVICE_TABLE(of, madera_of_match);
EXPORT_SYMBOL_GPL(madera_of_match);
static int madera_get_reset_gpio(struct madera *madera)
{
struct gpio_desc *reset;
if (madera->pdata.reset)
return 0;
reset = devm_gpiod_get_optional(madera->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(reset))
return dev_err_probe(madera->dev, PTR_ERR(reset),
"Failed to request /RESET");
/*
* A hard reset is needed for full reset of the chip. We allow running
* without hard reset only because it can be useful for early
* prototyping and some debugging, but we need to warn it's not ideal.
*/
if (!reset)
dev_warn(madera->dev,
"Running without reset GPIO is not recommended\n");
madera->pdata.reset = reset;
return 0;
}
static void madera_set_micbias_info(struct madera *madera)
{
/*
* num_childbias is an array because future codecs can have different
* childbiases for each micbias. Unspecified values default to 0.
*/
switch (madera->type) {
case CS47L15:
madera->num_micbias = 1;
madera->num_childbias[0] = 3;
return;
case CS47L35:
madera->num_micbias = 2;
madera->num_childbias[0] = 2;
madera->num_childbias[1] = 2;
return;
case CS47L85:
case WM1840:
madera->num_micbias = 4;
/* no child biases */
return;
case CS47L90:
case CS47L91:
madera->num_micbias = 2;
madera->num_childbias[0] = 4;
madera->num_childbias[1] = 4;
return;
case CS42L92:
case CS47L92:
case CS47L93:
madera->num_micbias = 2;
madera->num_childbias[0] = 4;
madera->num_childbias[1] = 2;
return;
default:
return;
}
}
int madera_dev_init(struct madera *madera)
{
struct device *dev = madera->dev;
unsigned int hwid;
int (*patch_fn)(struct madera *) = NULL;
const struct mfd_cell *mfd_devs;
int n_devs = 0;
int i, ret;
dev_set_drvdata(madera->dev, madera);
BLOCKING_INIT_NOTIFIER_HEAD(&madera->notifier);
mutex_init(&madera->dapm_ptr_lock);
madera_set_micbias_info(madera);
/*
* We need writable hw config info that all children can share.
* Simplest to take one shared copy of pdata struct.
*/
if (dev_get_platdata(madera->dev)) {
memcpy(&madera->pdata, dev_get_platdata(madera->dev),
sizeof(madera->pdata));
}
madera->mclk[MADERA_MCLK1].id = "mclk1";
madera->mclk[MADERA_MCLK2].id = "mclk2";
madera->mclk[MADERA_MCLK3].id = "mclk3";
ret = devm_clk_bulk_get_optional(madera->dev, ARRAY_SIZE(madera->mclk),
madera->mclk);
if (ret) {
dev_err(madera->dev, "Failed to get clocks: %d\n", ret);
return ret;
}
/* Not using devm_clk_get to prevent breakage of existing DTs */
if (!madera->mclk[MADERA_MCLK2].clk)
dev_warn(madera->dev, "Missing MCLK2, requires 32kHz clock\n");
ret = madera_get_reset_gpio(madera);
if (ret)
return ret;
regcache_cache_only(madera->regmap, true);
regcache_cache_only(madera->regmap_32bit, true);
for (i = 0; i < ARRAY_SIZE(madera_core_supplies); i++)
madera->core_supplies[i].supply = madera_core_supplies[i];
madera->num_core_supplies = ARRAY_SIZE(madera_core_supplies);
/*
* On some codecs DCVDD could be supplied by the internal LDO1.
* For those we must add the LDO1 driver before requesting DCVDD
* No devm_ because we need to control shutdown order of children.
*/
switch (madera->type) {
case CS47L15:
madera->reset_errata = true;
break;
case CS47L35:
case CS47L90:
case CS47L91:
case CS42L92:
case CS47L92:
case CS47L93:
break;
case CS47L85:
case WM1840:
ret = mfd_add_devices(madera->dev, PLATFORM_DEVID_NONE,
madera_ldo1_devs,
ARRAY_SIZE(madera_ldo1_devs),
NULL, 0, NULL);
if (ret) {
dev_err(dev, "Failed to add LDO1 child: %d\n", ret);
return ret;
}
break;
default:
/* No point continuing if the type is unknown */
dev_err(madera->dev, "Unknown device type %d\n", madera->type);
return -ENODEV;
}
ret = devm_regulator_bulk_get(dev, madera->num_core_supplies,
madera->core_supplies);
if (ret) {
dev_err(dev, "Failed to request core supplies: %d\n", ret);
goto err_devs;
}
/*
* Don't use devres here. If the regulator is one of our children it
* will already have been removed before devres cleanup on this mfd
* driver tries to call put() on it. We need control of shutdown order.
*/
madera->dcvdd = regulator_get(madera->dev, "DCVDD");
if (IS_ERR(madera->dcvdd)) {
ret = PTR_ERR(madera->dcvdd);
dev_err(dev, "Failed to request DCVDD: %d\n", ret);
goto err_devs;
}
ret = regulator_bulk_enable(madera->num_core_supplies,
madera->core_supplies);
if (ret) {
dev_err(dev, "Failed to enable core supplies: %d\n", ret);
goto err_dcvdd;
}
if (madera->reset_errata)
madera_disable_hard_reset(madera);
ret = regulator_enable(madera->dcvdd);
if (ret) {
dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
goto err_enable;
}
if (madera->reset_errata)
usleep_range(ERRATA_DCVDD_MIN_US, ERRATA_DCVDD_MAX_US);
else
madera_disable_hard_reset(madera);
regcache_cache_only(madera->regmap, false);
regcache_cache_only(madera->regmap_32bit, false);
ret = madera_wait_for_boot_noack(madera);
if (ret) {
dev_err(madera->dev, "Device failed initial boot: %d\n", ret);
goto err_reset;
}
/*
* Now we can power up and verify that this is a chip we know about
* before we start doing any writes to its registers.
*/
ret = regmap_read(madera->regmap, MADERA_SOFTWARE_RESET, &hwid);
if (ret) {
dev_err(dev, "Failed to read ID register: %d\n", ret);
goto err_reset;
}
switch (hwid) {
case CS47L15_SILICON_ID:
if (IS_ENABLED(CONFIG_MFD_CS47L15)) {
switch (madera->type) {
case CS47L15:
patch_fn = &cs47l15_patch;
mfd_devs = cs47l15_devs;
n_devs = ARRAY_SIZE(cs47l15_devs);
break;
default:
break;
}
}
break;
case CS47L35_SILICON_ID:
if (IS_ENABLED(CONFIG_MFD_CS47L35)) {
switch (madera->type) {
case CS47L35:
patch_fn = cs47l35_patch;
mfd_devs = cs47l35_devs;
n_devs = ARRAY_SIZE(cs47l35_devs);
break;
default:
break;
}
}
break;
case CS47L85_SILICON_ID:
if (IS_ENABLED(CONFIG_MFD_CS47L85)) {
switch (madera->type) {
case CS47L85:
case WM1840:
patch_fn = cs47l85_patch;
mfd_devs = cs47l85_devs;
n_devs = ARRAY_SIZE(cs47l85_devs);
break;
default:
break;
}
}
break;
case CS47L90_SILICON_ID:
if (IS_ENABLED(CONFIG_MFD_CS47L90)) {
switch (madera->type) {
case CS47L90:
case CS47L91:
patch_fn = cs47l90_patch;
mfd_devs = cs47l90_devs;
n_devs = ARRAY_SIZE(cs47l90_devs);
break;
default:
break;
}
}
break;
case CS47L92_SILICON_ID:
if (IS_ENABLED(CONFIG_MFD_CS47L92)) {
switch (madera->type) {
case CS42L92:
case CS47L92:
case CS47L93:
patch_fn = cs47l92_patch;
mfd_devs = cs47l92_devs;
n_devs = ARRAY_SIZE(cs47l92_devs);
break;
default:
break;
}
}
break;
default:
dev_err(madera->dev, "Unknown device ID: %x\n", hwid);
ret = -EINVAL;
goto err_reset;
}
if (!n_devs) {
dev_err(madera->dev, "Device ID 0x%x not a %s\n", hwid,
madera->type_name);
ret = -ENODEV;
goto err_reset;
}
/*
* It looks like a device we support. If we don't have a hard reset
* we can now attempt a soft reset.
*/
if (!madera->pdata.reset || madera->reset_errata) {
ret = madera_soft_reset(madera);
if (ret)
goto err_reset;
}
ret = madera_wait_for_boot(madera);
if (ret) {
dev_err(madera->dev, "Failed to clear boot done: %d\n", ret);
goto err_reset;
}
ret = regmap_read(madera->regmap, MADERA_HARDWARE_REVISION,
&madera->rev);
if (ret) {
dev_err(dev, "Failed to read revision register: %d\n", ret);
goto err_reset;
}
madera->rev &= MADERA_HW_REVISION_MASK;
dev_info(dev, "%s silicon revision %d\n", madera->type_name,
madera->rev);
/* Apply hardware patch */
if (patch_fn) {
ret = patch_fn(madera);
if (ret) {
dev_err(madera->dev, "Failed to apply patch %d\n", ret);
goto err_reset;
}
}
/* Init 32k clock sourced from MCLK2 */
ret = clk_prepare_enable(madera->mclk[MADERA_MCLK2].clk);
if (ret) {
dev_err(madera->dev, "Failed to enable 32k clock: %d\n", ret);
goto err_reset;
}
ret = regmap_update_bits(madera->regmap,
MADERA_CLOCK_32K_1,
MADERA_CLK_32K_ENA_MASK | MADERA_CLK_32K_SRC_MASK,
MADERA_CLK_32K_ENA | MADERA_32KZ_MCLK2);
if (ret) {
dev_err(madera->dev, "Failed to init 32k clock: %d\n", ret);
goto err_clock;
}
pm_runtime_set_active(madera->dev);
pm_runtime_enable(madera->dev);
pm_runtime_set_autosuspend_delay(madera->dev, 100);
pm_runtime_use_autosuspend(madera->dev);
/* No devm_ because we need to control shutdown order of children */
ret = mfd_add_devices(madera->dev, PLATFORM_DEVID_NONE,
mfd_devs, n_devs,
NULL, 0, NULL);
if (ret) {
dev_err(madera->dev, "Failed to add subdevices: %d\n", ret);
goto err_pm_runtime;
}
return 0;
err_pm_runtime:
pm_runtime_disable(madera->dev);
err_clock:
clk_disable_unprepare(madera->mclk[MADERA_MCLK2].clk);
err_reset:
madera_enable_hard_reset(madera);
regulator_disable(madera->dcvdd);
err_enable:
regulator_bulk_disable(madera->num_core_supplies,
madera->core_supplies);
err_dcvdd:
regulator_put(madera->dcvdd);
err_devs:
mfd_remove_devices(dev);
return ret;
}
EXPORT_SYMBOL_GPL(madera_dev_init);
int madera_dev_exit(struct madera *madera)
{
/* Prevent any IRQs being serviced while we clean up */
disable_irq(madera->irq);
pm_runtime_get_sync(madera->dev);
mfd_remove_devices(madera->dev);
pm_runtime_disable(madera->dev);
regulator_disable(madera->dcvdd);
regulator_put(madera->dcvdd);
mfd_remove_devices_late(madera->dev);
pm_runtime_set_suspended(madera->dev);
pm_runtime_put_noidle(madera->dev);
clk_disable_unprepare(madera->mclk[MADERA_MCLK2].clk);
madera_enable_hard_reset(madera);
regulator_bulk_disable(madera->num_core_supplies,
madera->core_supplies);
return 0;
}
EXPORT_SYMBOL_GPL(madera_dev_exit);
MODULE_DESCRIPTION("Madera core MFD driver");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/madera-core.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* SPI core driver for the Ocelot chip family.
*
* This driver will handle everything necessary to allow for communication over
* SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions
* are to prepare the chip's SPI interface for a specific bus speed, and a host
* processor's endianness. This will create and distribute regmaps for any
* children.
*
* Copyright 2021-2022 Innovative Advantage Inc.
*
* Author: Colin Foster <[email protected]>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/ioport.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/types.h>
#include <linux/units.h>
#include "ocelot.h"
#define REG_DEV_CPUORG_IF_CTRL 0x0000
#define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
#define CFGSTAT_IF_NUM_VCORE (0 << 24)
#define CFGSTAT_IF_NUM_VRAP (1 << 24)
#define CFGSTAT_IF_NUM_SI (2 << 24)
#define CFGSTAT_IF_NUM_MIIM (3 << 24)
#define VSC7512_DEVCPU_ORG_RES_START 0x71000000
#define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
#define VSC7512_CHIP_REGS_RES_START 0x71070000
#define VSC7512_CHIP_REGS_RES_SIZE 0x14
static const struct resource vsc7512_dev_cpuorg_resource =
DEFINE_RES_REG_NAMED(VSC7512_DEVCPU_ORG_RES_START,
VSC7512_DEVCPU_ORG_RES_SIZE,
"devcpu_org");
static const struct resource vsc7512_gcb_resource =
DEFINE_RES_REG_NAMED(VSC7512_CHIP_REGS_RES_START,
VSC7512_CHIP_REGS_RES_SIZE,
"devcpu_gcb_chip_regs");
static int ocelot_spi_initialize(struct device *dev)
{
struct ocelot_ddata *ddata = dev_get_drvdata(dev);
u32 val, check;
int err;
val = OCELOT_SPI_BYTE_ORDER;
/*
* The SPI address must be big-endian, but we want the payload to match
* our CPU. These are two bits (0 and 1) but they're repeated such that
* the write from any configuration will be valid. The four
* configurations are:
*
* 0b00: little-endian, MSB first
* | 111111 | 22221111 | 33222222 |
* | 76543210 | 54321098 | 32109876 | 10987654 |
*
* 0b01: big-endian, MSB first
* | 33222222 | 22221111 | 111111 | |
* | 10987654 | 32109876 | 54321098 | 76543210 |
*
* 0b10: little-endian, LSB first
* | 111111 | 11112222 | 22222233 |
* | 01234567 | 89012345 | 67890123 | 45678901 |
*
* 0b11: big-endian, LSB first
* | 22222233 | 11112222 | 111111 | |
* | 45678901 | 67890123 | 89012345 | 01234567 |
*/
err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CTRL, val);
if (err)
return err;
/*
* Apply the number of padding bytes between a read request and the data
* payload. Some registers have access times of up to 1us, so if the
* first payload bit is shifted out too quickly, the read will fail.
*/
val = ddata->spi_padding_bytes;
err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, val);
if (err)
return err;
/*
* After we write the interface configuration, read it back here. This
* will verify several different things. The first is that the number of
* padding bytes actually got written correctly. These are found in bits
* 0:3.
*
* The second is that bit 16 is cleared. Bit 16 is IF_CFGSTAT:IF_STAT,
* and will be set if the register access is too fast. This would be in
* the condition that the number of padding bytes is insufficient for
* the SPI bus frequency.
*
* The last check is for bits 31:24, which define the interface by which
* the registers are being accessed. Since we're accessing them via the
* serial interface, it must return IF_NUM_SI.
*/
check = val | CFGSTAT_IF_NUM_SI;
err = regmap_read(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, &val);
if (err)
return err;
if (check != val)
return -ENODEV;
return 0;
}
static const struct regmap_config ocelot_spi_regmap_config = {
.reg_bits = 24,
.reg_stride = 4,
.reg_shift = REGMAP_DOWNSHIFT(2),
.val_bits = 32,
.write_flag_mask = 0x80,
.use_single_read = true,
.use_single_write = true,
.can_multi_write = false,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
};
static int ocelot_spi_regmap_bus_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct spi_transfer xfers[3] = {0};
struct device *dev = context;
struct ocelot_ddata *ddata;
struct spi_device *spi;
struct spi_message msg;
unsigned int index = 0;
ddata = dev_get_drvdata(dev);
spi = to_spi_device(dev);
xfers[index].tx_buf = reg;
xfers[index].len = reg_size;
index++;
if (ddata->spi_padding_bytes) {
xfers[index].len = ddata->spi_padding_bytes;
xfers[index].tx_buf = ddata->dummy_buf;
xfers[index].dummy_data = 1;
index++;
}
xfers[index].rx_buf = val;
xfers[index].len = val_size;
index++;
spi_message_init_with_transfers(&msg, xfers, index);
return spi_sync(spi, &msg);
}
static int ocelot_spi_regmap_bus_write(void *context, const void *data, size_t count)
{
struct device *dev = context;
struct spi_device *spi = to_spi_device(dev);
return spi_write(spi, data, count);
}
static const struct regmap_bus ocelot_spi_regmap_bus = {
.write = ocelot_spi_regmap_bus_write,
.read = ocelot_spi_regmap_bus_read,
};
struct regmap *ocelot_spi_init_regmap(struct device *dev, const struct resource *res)
{
struct regmap_config regmap_config;
memcpy(®map_config, &ocelot_spi_regmap_config, sizeof(regmap_config));
regmap_config.name = res->name;
regmap_config.max_register = resource_size(res) - 1;
regmap_config.reg_base = res->start;
return devm_regmap_init(dev, &ocelot_spi_regmap_bus, dev, ®map_config);
}
EXPORT_SYMBOL_NS(ocelot_spi_init_regmap, MFD_OCELOT_SPI);
static int ocelot_spi_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct ocelot_ddata *ddata;
struct regmap *r;
int err;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
spi_set_drvdata(spi, ddata);
if (spi->max_speed_hz <= 500000) {
ddata->spi_padding_bytes = 0;
} else {
/*
* Calculation taken from the manual for IF_CFGSTAT:IF_CFG.
* Register access time is 1us, so we need to configure and send
* out enough padding bytes between the read request and data
* transmission that lasts at least 1 microsecond.
*/
ddata->spi_padding_bytes = 1 + (spi->max_speed_hz / HZ_PER_MHZ + 2) / 8;
ddata->dummy_buf = devm_kzalloc(dev, ddata->spi_padding_bytes, GFP_KERNEL);
if (!ddata->dummy_buf)
return -ENOMEM;
}
spi->bits_per_word = 8;
err = spi_setup(spi);
if (err)
return dev_err_probe(&spi->dev, err, "Error performing SPI setup\n");
r = ocelot_spi_init_regmap(dev, &vsc7512_dev_cpuorg_resource);
if (IS_ERR(r))
return PTR_ERR(r);
ddata->cpuorg_regmap = r;
r = ocelot_spi_init_regmap(dev, &vsc7512_gcb_resource);
if (IS_ERR(r))
return PTR_ERR(r);
ddata->gcb_regmap = r;
/*
* The chip must be set up for SPI before it gets initialized and reset.
* This must be done before calling init, and after a chip reset is
* performed.
*/
err = ocelot_spi_initialize(dev);
if (err)
return dev_err_probe(dev, err, "Error initializing SPI bus\n");
err = ocelot_chip_reset(dev);
if (err)
return dev_err_probe(dev, err, "Error resetting device\n");
/*
* A chip reset will clear the SPI configuration, so it needs to be done
* again before we can access any registers.
*/
err = ocelot_spi_initialize(dev);
if (err)
return dev_err_probe(dev, err, "Error initializing SPI bus after reset\n");
err = ocelot_core_init(dev);
if (err)
return dev_err_probe(dev, err, "Error initializing Ocelot core\n");
return 0;
}
static const struct spi_device_id ocelot_spi_ids[] = {
{ "vsc7512", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, ocelot_spi_ids);
static const struct of_device_id ocelot_spi_of_match[] = {
{ .compatible = "mscc,vsc7512" },
{ }
};
MODULE_DEVICE_TABLE(of, ocelot_spi_of_match);
static struct spi_driver ocelot_spi_driver = {
.driver = {
.name = "ocelot-soc",
.of_match_table = ocelot_spi_of_match,
},
.id_table = ocelot_spi_ids,
.probe = ocelot_spi_probe,
};
module_spi_driver(ocelot_spi_driver);
MODULE_DESCRIPTION("SPI Controlled Ocelot Chip Driver");
MODULE_AUTHOR("Colin Foster <[email protected]>");
MODULE_LICENSE("Dual MIT/GPL");
MODULE_IMPORT_NS(MFD_OCELOT);
| linux-master | drivers/mfd/ocelot-spi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/* NXP PCF50633 Power Management Unit (PMU) driver
*
* (C) 2006-2008 by Openmoko, Inc.
* Author: Harald Welte <[email protected]>
* Balaji Rao <[email protected]>
* All rights reserved.
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/export.h>
#include <linux/slab.h>
#include <linux/mfd/pcf50633/core.h>
#include <linux/mfd/pcf50633/mbc.h>
int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
void (*handler) (int, void *), void *data)
{
if (irq < 0 || irq >= PCF50633_NUM_IRQ || !handler)
return -EINVAL;
if (WARN_ON(pcf->irq_handler[irq].handler))
return -EBUSY;
mutex_lock(&pcf->lock);
pcf->irq_handler[irq].handler = handler;
pcf->irq_handler[irq].data = data;
mutex_unlock(&pcf->lock);
return 0;
}
EXPORT_SYMBOL_GPL(pcf50633_register_irq);
int pcf50633_free_irq(struct pcf50633 *pcf, int irq)
{
if (irq < 0 || irq >= PCF50633_NUM_IRQ)
return -EINVAL;
mutex_lock(&pcf->lock);
pcf->irq_handler[irq].handler = NULL;
mutex_unlock(&pcf->lock);
return 0;
}
EXPORT_SYMBOL_GPL(pcf50633_free_irq);
static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask)
{
u8 reg, bit;
int idx;
idx = irq >> 3;
reg = PCF50633_REG_INT1M + idx;
bit = 1 << (irq & 0x07);
pcf50633_reg_set_bit_mask(pcf, reg, bit, mask ? bit : 0);
mutex_lock(&pcf->lock);
if (mask)
pcf->mask_regs[idx] |= bit;
else
pcf->mask_regs[idx] &= ~bit;
mutex_unlock(&pcf->lock);
return 0;
}
int pcf50633_irq_mask(struct pcf50633 *pcf, int irq)
{
dev_dbg(pcf->dev, "Masking IRQ %d\n", irq);
return __pcf50633_irq_mask_set(pcf, irq, 1);
}
EXPORT_SYMBOL_GPL(pcf50633_irq_mask);
int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq)
{
dev_dbg(pcf->dev, "Unmasking IRQ %d\n", irq);
return __pcf50633_irq_mask_set(pcf, irq, 0);
}
EXPORT_SYMBOL_GPL(pcf50633_irq_unmask);
int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq)
{
u8 reg, bits;
reg = irq >> 3;
bits = 1 << (irq & 0x07);
return pcf->mask_regs[reg] & bits;
}
EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get);
static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq)
{
if (pcf->irq_handler[irq].handler)
pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data);
}
/* Maximum amount of time ONKEY is held before emergency action is taken */
#define PCF50633_ONKEY1S_TIMEOUT 8
static irqreturn_t pcf50633_irq(int irq, void *data)
{
struct pcf50633 *pcf = data;
int ret, i, j;
u8 pcf_int[5], chgstat;
/* Read the 5 INT regs in one transaction */
ret = pcf50633_read_block(pcf, PCF50633_REG_INT1,
ARRAY_SIZE(pcf_int), pcf_int);
if (ret != ARRAY_SIZE(pcf_int)) {
dev_err(pcf->dev, "Error reading INT registers\n");
/*
* If this doesn't ACK the interrupt to the chip, we'll be
* called once again as we're level triggered.
*/
goto out;
}
/* defeat 8s death from lowsys on A5 */
pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN, 0x04);
/* We immediately read the usb and adapter status. We thus make sure
* only of USBINS/USBREM IRQ handlers are called */
if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) {
chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
if (chgstat & (0x3 << 4))
pcf_int[0] &= ~PCF50633_INT1_USBREM;
else
pcf_int[0] &= ~PCF50633_INT1_USBINS;
}
/* Make sure only one of ADPINS or ADPREM is set */
if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) {
chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
if (chgstat & (0x3 << 4))
pcf_int[0] &= ~PCF50633_INT1_ADPREM;
else
pcf_int[0] &= ~PCF50633_INT1_ADPINS;
}
dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
"INT4=0x%02x INT5=0x%02x\n", pcf_int[0],
pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]);
/* Some revisions of the chip don't have a 8s standby mode on
* ONKEY1S press. We try to manually do it in such cases. */
if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) {
dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
pcf->onkey1s_held);
if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT)
if (pcf->pdata->force_shutdown)
pcf->pdata->force_shutdown(pcf);
}
if (pcf_int[2] & PCF50633_INT3_ONKEY1S) {
dev_info(pcf->dev, "ONKEY1S held\n");
pcf->onkey1s_held = 1 ;
/* Unmask IRQ_SECOND */
pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M,
PCF50633_INT1_SECOND);
/* Unmask IRQ_ONKEYR */
pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M,
PCF50633_INT2_ONKEYR);
}
if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) {
pcf->onkey1s_held = 0;
/* Mask SECOND and ONKEYR interrupts */
if (pcf->mask_regs[0] & PCF50633_INT1_SECOND)
pcf50633_reg_set_bit_mask(pcf,
PCF50633_REG_INT1M,
PCF50633_INT1_SECOND,
PCF50633_INT1_SECOND);
if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR)
pcf50633_reg_set_bit_mask(pcf,
PCF50633_REG_INT2M,
PCF50633_INT2_ONKEYR,
PCF50633_INT2_ONKEYR);
}
/* Have we just resumed ? */
if (pcf->is_suspended) {
pcf->is_suspended = 0;
/* Set the resume reason filtering out non resumers */
for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
pcf->resume_reason[i] = pcf_int[i] &
pcf->pdata->resumers[i];
/* Make sure we don't pass on any ONKEY events to
* userspace now */
pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF);
}
for (i = 0; i < ARRAY_SIZE(pcf_int); i++) {
/* Unset masked interrupts */
pcf_int[i] &= ~pcf->mask_regs[i];
for (j = 0; j < 8 ; j++)
if (pcf_int[i] & (1 << j))
pcf50633_irq_call_handler(pcf, (i * 8) + j);
}
out:
return IRQ_HANDLED;
}
static int pcf50633_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct pcf50633 *pcf = i2c_get_clientdata(client);
int ret;
int i;
u8 res[5];
/* Make sure our interrupt handlers are not called
* henceforth */
disable_irq(pcf->irq);
/* Save the masks */
ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M,
ARRAY_SIZE(pcf->suspend_irq_masks),
pcf->suspend_irq_masks);
if (ret < 0) {
dev_err(pcf->dev, "error saving irq masks\n");
goto out;
}
/* Write wakeup irq masks */
for (i = 0; i < ARRAY_SIZE(res); i++)
res[i] = ~pcf->pdata->resumers[i];
ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
ARRAY_SIZE(res), &res[0]);
if (ret < 0) {
dev_err(pcf->dev, "error writing wakeup irq masks\n");
goto out;
}
pcf->is_suspended = 1;
out:
return ret;
}
static int pcf50633_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct pcf50633 *pcf = i2c_get_clientdata(client);
int ret;
/* Write the saved mask registers */
ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
ARRAY_SIZE(pcf->suspend_irq_masks),
pcf->suspend_irq_masks);
if (ret < 0)
dev_err(pcf->dev, "Error restoring saved suspend masks\n");
enable_irq(pcf->irq);
return ret;
}
EXPORT_GPL_SIMPLE_DEV_PM_OPS(pcf50633_pm, pcf50633_suspend, pcf50633_resume);
int pcf50633_irq_init(struct pcf50633 *pcf, int irq)
{
int ret;
pcf->irq = irq;
/* Enable all interrupts except RTC SECOND */
pcf->mask_regs[0] = 0x80;
pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]);
pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
ret = request_threaded_irq(irq, NULL, pcf50633_irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"pcf50633", pcf);
if (ret)
dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
if (enable_irq_wake(irq) < 0)
dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source"
"in this hardware revision", irq);
return ret;
}
void pcf50633_irq_free(struct pcf50633 *pcf)
{
free_irq(pcf->irq, pcf);
}
| linux-master | drivers/mfd/pcf50633-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for Motorola PCAP2 as present in EZX phones
*
* Copyright (C) 2006 Harald Welte <[email protected]>
* Copyright (C) 2009 Daniel Ribeiro <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/ezx-pcap.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#define PCAP_ADC_MAXQ 8
struct pcap_adc_request {
u8 bank;
u8 ch[2];
u32 flags;
void (*callback)(void *, u16[]);
void *data;
};
struct pcap_adc_sync_request {
u16 res[2];
struct completion completion;
};
struct pcap_chip {
struct spi_device *spi;
/* IO */
u32 buf;
spinlock_t io_lock;
/* IRQ */
unsigned int irq_base;
u32 msr;
struct work_struct isr_work;
struct work_struct msr_work;
struct workqueue_struct *workqueue;
/* ADC */
struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
u8 adc_head;
u8 adc_tail;
spinlock_t adc_lock;
};
/* IO */
static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
{
struct spi_transfer t;
struct spi_message m;
int status;
memset(&t, 0, sizeof(t));
spi_message_init(&m);
t.len = sizeof(u32);
spi_message_add_tail(&t, &m);
pcap->buf = *data;
t.tx_buf = (u8 *) &pcap->buf;
t.rx_buf = (u8 *) &pcap->buf;
status = spi_sync(pcap->spi, &m);
if (status == 0)
*data = pcap->buf;
return status;
}
int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
{
unsigned long flags;
int ret;
spin_lock_irqsave(&pcap->io_lock, flags);
value &= PCAP_REGISTER_VALUE_MASK;
value |= PCAP_REGISTER_WRITE_OP_BIT
| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
ret = ezx_pcap_putget(pcap, &value);
spin_unlock_irqrestore(&pcap->io_lock, flags);
return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_write);
int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
{
unsigned long flags;
int ret;
spin_lock_irqsave(&pcap->io_lock, flags);
*value = PCAP_REGISTER_READ_OP_BIT
| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
ret = ezx_pcap_putget(pcap, value);
spin_unlock_irqrestore(&pcap->io_lock, flags);
return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_read);
int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
{
unsigned long flags;
int ret;
u32 tmp = PCAP_REGISTER_READ_OP_BIT |
(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
spin_lock_irqsave(&pcap->io_lock, flags);
ret = ezx_pcap_putget(pcap, &tmp);
if (ret)
goto out_unlock;
tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
ret = ezx_pcap_putget(pcap, &tmp);
out_unlock:
spin_unlock_irqrestore(&pcap->io_lock, flags);
return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
/* IRQ */
int irq_to_pcap(struct pcap_chip *pcap, int irq)
{
return irq - pcap->irq_base;
}
EXPORT_SYMBOL_GPL(irq_to_pcap);
int pcap_to_irq(struct pcap_chip *pcap, int irq)
{
return pcap->irq_base + irq;
}
EXPORT_SYMBOL_GPL(pcap_to_irq);
static void pcap_mask_irq(struct irq_data *d)
{
struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
pcap->msr |= 1 << irq_to_pcap(pcap, d->irq);
queue_work(pcap->workqueue, &pcap->msr_work);
}
static void pcap_unmask_irq(struct irq_data *d)
{
struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
queue_work(pcap->workqueue, &pcap->msr_work);
}
static struct irq_chip pcap_irq_chip = {
.name = "pcap",
.irq_disable = pcap_mask_irq,
.irq_mask = pcap_mask_irq,
.irq_unmask = pcap_unmask_irq,
};
static void pcap_msr_work(struct work_struct *work)
{
struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
}
static void pcap_isr_work(struct work_struct *work)
{
struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);
u32 msr, isr, int_sel, service;
int irq;
do {
ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
/* We can't service/ack irqs that are assigned to port 2 */
if (!(pdata->config & PCAP_SECOND_PORT)) {
ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
isr &= ~int_sel;
}
ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
service = isr & ~msr;
for (irq = pcap->irq_base; service; service >>= 1, irq++) {
if (service & 1)
generic_handle_irq_safe(irq);
}
ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
} while (gpio_get_value(pdata->gpio));
}
static void pcap_irq_handler(struct irq_desc *desc)
{
struct pcap_chip *pcap = irq_desc_get_handler_data(desc);
desc->irq_data.chip->irq_ack(&desc->irq_data);
queue_work(pcap->workqueue, &pcap->isr_work);
}
/* ADC */
void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
{
unsigned long flags;
u32 tmp;
spin_lock_irqsave(&pcap->adc_lock, flags);
ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
spin_unlock_irqrestore(&pcap->adc_lock, flags);
}
EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
static void pcap_disable_adc(struct pcap_chip *pcap)
{
u32 tmp;
ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
}
static void pcap_adc_trigger(struct pcap_chip *pcap)
{
unsigned long flags;
u32 tmp;
u8 head;
spin_lock_irqsave(&pcap->adc_lock, flags);
head = pcap->adc_head;
if (!pcap->adc_queue[head]) {
/* queue is empty, save power */
pcap_disable_adc(pcap);
spin_unlock_irqrestore(&pcap->adc_lock, flags);
return;
}
/* start conversion on requested bank, save TS_M bits */
ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
tmp |= PCAP_ADC_AD_SEL1;
ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
spin_unlock_irqrestore(&pcap->adc_lock, flags);
ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
}
static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
{
struct pcap_chip *pcap = _pcap;
struct pcap_adc_request *req;
u16 res[2];
u32 tmp;
spin_lock(&pcap->adc_lock);
req = pcap->adc_queue[pcap->adc_head];
if (WARN(!req, "adc irq without pending request\n")) {
spin_unlock(&pcap->adc_lock);
return IRQ_HANDLED;
}
/* read requested channels results */
ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
pcap->adc_queue[pcap->adc_head] = NULL;
pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
spin_unlock(&pcap->adc_lock);
/* pass the results and release memory */
req->callback(req->data, res);
kfree(req);
/* trigger next conversion (if any) on queue */
pcap_adc_trigger(pcap);
return IRQ_HANDLED;
}
int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
void *callback, void *data)
{
struct pcap_adc_request *req;
unsigned long irq_flags;
/* This will be freed after we have a result */
req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
if (!req)
return -ENOMEM;
req->bank = bank;
req->flags = flags;
req->ch[0] = ch[0];
req->ch[1] = ch[1];
req->callback = callback;
req->data = data;
spin_lock_irqsave(&pcap->adc_lock, irq_flags);
if (pcap->adc_queue[pcap->adc_tail]) {
spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
kfree(req);
return -EBUSY;
}
pcap->adc_queue[pcap->adc_tail] = req;
pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
/* start conversion */
pcap_adc_trigger(pcap);
return 0;
}
EXPORT_SYMBOL_GPL(pcap_adc_async);
static void pcap_adc_sync_cb(void *param, u16 res[])
{
struct pcap_adc_sync_request *req = param;
req->res[0] = res[0];
req->res[1] = res[1];
complete(&req->completion);
}
int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
u16 res[])
{
struct pcap_adc_sync_request sync_data;
int ret;
init_completion(&sync_data.completion);
ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
&sync_data);
if (ret)
return ret;
wait_for_completion(&sync_data.completion);
res[0] = sync_data.res[0];
res[1] = sync_data.res[1];
return 0;
}
EXPORT_SYMBOL_GPL(pcap_adc_sync);
/* subdevs */
static int pcap_remove_subdev(struct device *dev, void *unused)
{
platform_device_unregister(to_platform_device(dev));
return 0;
}
static int pcap_add_subdev(struct pcap_chip *pcap,
struct pcap_subdev *subdev)
{
struct platform_device *pdev;
int ret;
pdev = platform_device_alloc(subdev->name, subdev->id);
if (!pdev)
return -ENOMEM;
pdev->dev.parent = &pcap->spi->dev;
pdev->dev.platform_data = subdev->platform_data;
ret = platform_device_add(pdev);
if (ret)
platform_device_put(pdev);
return ret;
}
static void ezx_pcap_remove(struct spi_device *spi)
{
struct pcap_chip *pcap = spi_get_drvdata(spi);
unsigned long flags;
int i;
/* remove all registered subdevs */
device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
/* cleanup ADC */
spin_lock_irqsave(&pcap->adc_lock, flags);
for (i = 0; i < PCAP_ADC_MAXQ; i++)
kfree(pcap->adc_queue[i]);
spin_unlock_irqrestore(&pcap->adc_lock, flags);
/* cleanup irqchip */
for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
irq_set_chip_and_handler(i, NULL, NULL);
destroy_workqueue(pcap->workqueue);
}
static int ezx_pcap_probe(struct spi_device *spi)
{
struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);
struct pcap_chip *pcap;
int i, adc_irq;
int ret = -ENODEV;
/* platform data is required */
if (!pdata)
goto ret;
pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
if (!pcap) {
ret = -ENOMEM;
goto ret;
}
spin_lock_init(&pcap->io_lock);
spin_lock_init(&pcap->adc_lock);
INIT_WORK(&pcap->isr_work, pcap_isr_work);
INIT_WORK(&pcap->msr_work, pcap_msr_work);
spi_set_drvdata(spi, pcap);
/* setup spi */
spi->bits_per_word = 32;
spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
ret = spi_setup(spi);
if (ret)
goto ret;
pcap->spi = spi;
/* setup irq */
pcap->irq_base = pdata->irq_base;
pcap->workqueue = create_singlethread_workqueue("pcapd");
if (!pcap->workqueue) {
ret = -ENOMEM;
dev_err(&spi->dev, "can't create pcap thread\n");
goto ret;
}
/* redirect interrupts to AP, except adcdone2 */
if (!(pdata->config & PCAP_SECOND_PORT))
ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
(1 << PCAP_IRQ_ADCDONE2));
/* setup irq chip */
for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
irq_set_chip_data(i, pcap);
irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
}
/* mask/ack all PCAP interrupts */
ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
pcap->msr = PCAP_MASK_ALL_INTERRUPT;
irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);
irq_set_irq_wake(spi->irq, 1);
/* ADC */
adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
pcap);
if (ret)
goto free_irqchip;
/* setup subdevs */
for (i = 0; i < pdata->num_subdevs; i++) {
ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
if (ret)
goto remove_subdevs;
}
/* board specific quirks */
if (pdata->init)
pdata->init(pcap);
return 0;
remove_subdevs:
device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
free_irqchip:
for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
irq_set_chip_and_handler(i, NULL, NULL);
/* destroy_workqueue: */
destroy_workqueue(pcap->workqueue);
ret:
return ret;
}
static struct spi_driver ezxpcap_driver = {
.probe = ezx_pcap_probe,
.remove = ezx_pcap_remove,
.driver = {
.name = "ezx-pcap",
},
};
static int __init ezx_pcap_init(void)
{
return spi_register_driver(&ezxpcap_driver);
}
static void __exit ezx_pcap_exit(void)
{
spi_unregister_driver(&ezxpcap_driver);
}
subsys_initcall(ezx_pcap_init);
module_exit(ezx_pcap_exit);
MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
MODULE_ALIAS("spi:ezx-pcap");
| linux-master | drivers/mfd/ezx-pcap.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm831x-core.c -- Device access for Wolfson WM831x PMICs
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/mfd/core.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/mod_devicetable.h>
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/pdata.h>
#include <linux/mfd/wm831x/irq.h>
#include <linux/mfd/wm831x/auxadc.h>
#include <linux/mfd/wm831x/otp.h>
#include <linux/mfd/wm831x/pmu.h>
#include <linux/mfd/wm831x/regulator.h>
/* Current settings - values are 2*2^(reg_val/4) microamps. These are
* exported since they are used by multiple drivers.
*/
const unsigned int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL + 1] = {
2,
2,
3,
3,
4,
5,
6,
7,
8,
10,
11,
13,
16,
19,
23,
27,
32,
38,
45,
54,
64,
76,
91,
108,
128,
152,
181,
215,
256,
304,
362,
431,
512,
609,
724,
861,
1024,
1218,
1448,
1722,
2048,
2435,
2896,
3444,
4096,
4871,
5793,
6889,
8192,
9742,
11585,
13777,
16384,
19484,
23170,
27554,
};
EXPORT_SYMBOL_GPL(wm831x_isinkv_values);
static int wm831x_reg_locked(struct wm831x *wm831x, unsigned short reg)
{
if (!wm831x->locked)
return 0;
switch (reg) {
case WM831X_WATCHDOG:
case WM831X_DC4_CONTROL:
case WM831X_ON_PIN_CONTROL:
case WM831X_BACKUP_CHARGER_CONTROL:
case WM831X_CHARGER_CONTROL_1:
case WM831X_CHARGER_CONTROL_2:
return 1;
default:
return 0;
}
}
/**
* wm831x_reg_lock: Unlock user keyed registers
*
* The WM831x has a user key preventing writes to particularly
* critical registers. This function locks those registers,
* allowing writes to them.
*
* @wm831x: pointer to local driver data structure
*/
void wm831x_reg_lock(struct wm831x *wm831x)
{
int ret;
ret = wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0);
if (ret == 0) {
dev_vdbg(wm831x->dev, "Registers locked\n");
mutex_lock(&wm831x->io_lock);
WARN_ON(wm831x->locked);
wm831x->locked = 1;
mutex_unlock(&wm831x->io_lock);
} else {
dev_err(wm831x->dev, "Failed to lock registers: %d\n", ret);
}
}
EXPORT_SYMBOL_GPL(wm831x_reg_lock);
/**
* wm831x_reg_unlock: Unlock user keyed registers
*
* The WM831x has a user key preventing writes to particularly
* critical registers. This function locks those registers,
* preventing spurious writes.
*
* @wm831x: pointer to local driver data structure
*/
int wm831x_reg_unlock(struct wm831x *wm831x)
{
int ret;
/* 0x9716 is the value required to unlock the registers */
ret = wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0x9716);
if (ret == 0) {
dev_vdbg(wm831x->dev, "Registers unlocked\n");
mutex_lock(&wm831x->io_lock);
WARN_ON(!wm831x->locked);
wm831x->locked = 0;
mutex_unlock(&wm831x->io_lock);
}
return ret;
}
EXPORT_SYMBOL_GPL(wm831x_reg_unlock);
static bool wm831x_reg_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM831X_RESET_ID:
case WM831X_REVISION:
case WM831X_PARENT_ID:
case WM831X_SYSVDD_CONTROL:
case WM831X_THERMAL_MONITORING:
case WM831X_POWER_STATE:
case WM831X_WATCHDOG:
case WM831X_ON_PIN_CONTROL:
case WM831X_RESET_CONTROL:
case WM831X_CONTROL_INTERFACE:
case WM831X_SECURITY_KEY:
case WM831X_SOFTWARE_SCRATCH:
case WM831X_OTP_CONTROL:
case WM831X_GPIO_LEVEL:
case WM831X_SYSTEM_STATUS:
case WM831X_ON_SOURCE:
case WM831X_OFF_SOURCE:
case WM831X_SYSTEM_INTERRUPTS:
case WM831X_INTERRUPT_STATUS_1:
case WM831X_INTERRUPT_STATUS_2:
case WM831X_INTERRUPT_STATUS_3:
case WM831X_INTERRUPT_STATUS_4:
case WM831X_INTERRUPT_STATUS_5:
case WM831X_IRQ_CONFIG:
case WM831X_SYSTEM_INTERRUPTS_MASK:
case WM831X_INTERRUPT_STATUS_1_MASK:
case WM831X_INTERRUPT_STATUS_2_MASK:
case WM831X_INTERRUPT_STATUS_3_MASK:
case WM831X_INTERRUPT_STATUS_4_MASK:
case WM831X_INTERRUPT_STATUS_5_MASK:
case WM831X_RTC_WRITE_COUNTER:
case WM831X_RTC_TIME_1:
case WM831X_RTC_TIME_2:
case WM831X_RTC_ALARM_1:
case WM831X_RTC_ALARM_2:
case WM831X_RTC_CONTROL:
case WM831X_RTC_TRIM:
case WM831X_TOUCH_CONTROL_1:
case WM831X_TOUCH_CONTROL_2:
case WM831X_TOUCH_DATA_X:
case WM831X_TOUCH_DATA_Y:
case WM831X_TOUCH_DATA_Z:
case WM831X_AUXADC_DATA:
case WM831X_AUXADC_CONTROL:
case WM831X_AUXADC_SOURCE:
case WM831X_COMPARATOR_CONTROL:
case WM831X_COMPARATOR_1:
case WM831X_COMPARATOR_2:
case WM831X_COMPARATOR_3:
case WM831X_COMPARATOR_4:
case WM831X_GPIO1_CONTROL:
case WM831X_GPIO2_CONTROL:
case WM831X_GPIO3_CONTROL:
case WM831X_GPIO4_CONTROL:
case WM831X_GPIO5_CONTROL:
case WM831X_GPIO6_CONTROL:
case WM831X_GPIO7_CONTROL:
case WM831X_GPIO8_CONTROL:
case WM831X_GPIO9_CONTROL:
case WM831X_GPIO10_CONTROL:
case WM831X_GPIO11_CONTROL:
case WM831X_GPIO12_CONTROL:
case WM831X_GPIO13_CONTROL:
case WM831X_GPIO14_CONTROL:
case WM831X_GPIO15_CONTROL:
case WM831X_GPIO16_CONTROL:
case WM831X_CHARGER_CONTROL_1:
case WM831X_CHARGER_CONTROL_2:
case WM831X_CHARGER_STATUS:
case WM831X_BACKUP_CHARGER_CONTROL:
case WM831X_STATUS_LED_1:
case WM831X_STATUS_LED_2:
case WM831X_CURRENT_SINK_1:
case WM831X_CURRENT_SINK_2:
case WM831X_DCDC_ENABLE:
case WM831X_LDO_ENABLE:
case WM831X_DCDC_STATUS:
case WM831X_LDO_STATUS:
case WM831X_DCDC_UV_STATUS:
case WM831X_LDO_UV_STATUS:
case WM831X_DC1_CONTROL_1:
case WM831X_DC1_CONTROL_2:
case WM831X_DC1_ON_CONFIG:
case WM831X_DC1_SLEEP_CONTROL:
case WM831X_DC1_DVS_CONTROL:
case WM831X_DC2_CONTROL_1:
case WM831X_DC2_CONTROL_2:
case WM831X_DC2_ON_CONFIG:
case WM831X_DC2_SLEEP_CONTROL:
case WM831X_DC2_DVS_CONTROL:
case WM831X_DC3_CONTROL_1:
case WM831X_DC3_CONTROL_2:
case WM831X_DC3_ON_CONFIG:
case WM831X_DC3_SLEEP_CONTROL:
case WM831X_DC4_CONTROL:
case WM831X_DC4_SLEEP_CONTROL:
case WM831X_EPE1_CONTROL:
case WM831X_EPE2_CONTROL:
case WM831X_LDO1_CONTROL:
case WM831X_LDO1_ON_CONTROL:
case WM831X_LDO1_SLEEP_CONTROL:
case WM831X_LDO2_CONTROL:
case WM831X_LDO2_ON_CONTROL:
case WM831X_LDO2_SLEEP_CONTROL:
case WM831X_LDO3_CONTROL:
case WM831X_LDO3_ON_CONTROL:
case WM831X_LDO3_SLEEP_CONTROL:
case WM831X_LDO4_CONTROL:
case WM831X_LDO4_ON_CONTROL:
case WM831X_LDO4_SLEEP_CONTROL:
case WM831X_LDO5_CONTROL:
case WM831X_LDO5_ON_CONTROL:
case WM831X_LDO5_SLEEP_CONTROL:
case WM831X_LDO6_CONTROL:
case WM831X_LDO6_ON_CONTROL:
case WM831X_LDO6_SLEEP_CONTROL:
case WM831X_LDO7_CONTROL:
case WM831X_LDO7_ON_CONTROL:
case WM831X_LDO7_SLEEP_CONTROL:
case WM831X_LDO8_CONTROL:
case WM831X_LDO8_ON_CONTROL:
case WM831X_LDO8_SLEEP_CONTROL:
case WM831X_LDO9_CONTROL:
case WM831X_LDO9_ON_CONTROL:
case WM831X_LDO9_SLEEP_CONTROL:
case WM831X_LDO10_CONTROL:
case WM831X_LDO10_ON_CONTROL:
case WM831X_LDO10_SLEEP_CONTROL:
case WM831X_LDO11_ON_CONTROL:
case WM831X_LDO11_SLEEP_CONTROL:
case WM831X_POWER_GOOD_SOURCE_1:
case WM831X_POWER_GOOD_SOURCE_2:
case WM831X_CLOCK_CONTROL_1:
case WM831X_CLOCK_CONTROL_2:
case WM831X_FLL_CONTROL_1:
case WM831X_FLL_CONTROL_2:
case WM831X_FLL_CONTROL_3:
case WM831X_FLL_CONTROL_4:
case WM831X_FLL_CONTROL_5:
case WM831X_UNIQUE_ID_1:
case WM831X_UNIQUE_ID_2:
case WM831X_UNIQUE_ID_3:
case WM831X_UNIQUE_ID_4:
case WM831X_UNIQUE_ID_5:
case WM831X_UNIQUE_ID_6:
case WM831X_UNIQUE_ID_7:
case WM831X_UNIQUE_ID_8:
case WM831X_FACTORY_OTP_ID:
case WM831X_FACTORY_OTP_1:
case WM831X_FACTORY_OTP_2:
case WM831X_FACTORY_OTP_3:
case WM831X_FACTORY_OTP_4:
case WM831X_FACTORY_OTP_5:
case WM831X_CUSTOMER_OTP_ID:
case WM831X_DC1_OTP_CONTROL:
case WM831X_DC2_OTP_CONTROL:
case WM831X_DC3_OTP_CONTROL:
case WM831X_LDO1_2_OTP_CONTROL:
case WM831X_LDO3_4_OTP_CONTROL:
case WM831X_LDO5_6_OTP_CONTROL:
case WM831X_LDO7_8_OTP_CONTROL:
case WM831X_LDO9_10_OTP_CONTROL:
case WM831X_LDO11_EPE_CONTROL:
case WM831X_GPIO1_OTP_CONTROL:
case WM831X_GPIO2_OTP_CONTROL:
case WM831X_GPIO3_OTP_CONTROL:
case WM831X_GPIO4_OTP_CONTROL:
case WM831X_GPIO5_OTP_CONTROL:
case WM831X_GPIO6_OTP_CONTROL:
case WM831X_DBE_CHECK_DATA:
return true;
default:
return false;
}
}
static bool wm831x_reg_writeable(struct device *dev, unsigned int reg)
{
struct wm831x *wm831x = dev_get_drvdata(dev);
if (wm831x_reg_locked(wm831x, reg))
return false;
switch (reg) {
case WM831X_SYSVDD_CONTROL:
case WM831X_THERMAL_MONITORING:
case WM831X_POWER_STATE:
case WM831X_WATCHDOG:
case WM831X_ON_PIN_CONTROL:
case WM831X_RESET_CONTROL:
case WM831X_CONTROL_INTERFACE:
case WM831X_SECURITY_KEY:
case WM831X_SOFTWARE_SCRATCH:
case WM831X_OTP_CONTROL:
case WM831X_GPIO_LEVEL:
case WM831X_INTERRUPT_STATUS_1:
case WM831X_INTERRUPT_STATUS_2:
case WM831X_INTERRUPT_STATUS_3:
case WM831X_INTERRUPT_STATUS_4:
case WM831X_INTERRUPT_STATUS_5:
case WM831X_IRQ_CONFIG:
case WM831X_SYSTEM_INTERRUPTS_MASK:
case WM831X_INTERRUPT_STATUS_1_MASK:
case WM831X_INTERRUPT_STATUS_2_MASK:
case WM831X_INTERRUPT_STATUS_3_MASK:
case WM831X_INTERRUPT_STATUS_4_MASK:
case WM831X_INTERRUPT_STATUS_5_MASK:
case WM831X_RTC_TIME_1:
case WM831X_RTC_TIME_2:
case WM831X_RTC_ALARM_1:
case WM831X_RTC_ALARM_2:
case WM831X_RTC_CONTROL:
case WM831X_RTC_TRIM:
case WM831X_TOUCH_CONTROL_1:
case WM831X_TOUCH_CONTROL_2:
case WM831X_AUXADC_CONTROL:
case WM831X_AUXADC_SOURCE:
case WM831X_COMPARATOR_CONTROL:
case WM831X_COMPARATOR_1:
case WM831X_COMPARATOR_2:
case WM831X_COMPARATOR_3:
case WM831X_COMPARATOR_4:
case WM831X_GPIO1_CONTROL:
case WM831X_GPIO2_CONTROL:
case WM831X_GPIO3_CONTROL:
case WM831X_GPIO4_CONTROL:
case WM831X_GPIO5_CONTROL:
case WM831X_GPIO6_CONTROL:
case WM831X_GPIO7_CONTROL:
case WM831X_GPIO8_CONTROL:
case WM831X_GPIO9_CONTROL:
case WM831X_GPIO10_CONTROL:
case WM831X_GPIO11_CONTROL:
case WM831X_GPIO12_CONTROL:
case WM831X_GPIO13_CONTROL:
case WM831X_GPIO14_CONTROL:
case WM831X_GPIO15_CONTROL:
case WM831X_GPIO16_CONTROL:
case WM831X_CHARGER_CONTROL_1:
case WM831X_CHARGER_CONTROL_2:
case WM831X_CHARGER_STATUS:
case WM831X_BACKUP_CHARGER_CONTROL:
case WM831X_STATUS_LED_1:
case WM831X_STATUS_LED_2:
case WM831X_CURRENT_SINK_1:
case WM831X_CURRENT_SINK_2:
case WM831X_DCDC_ENABLE:
case WM831X_LDO_ENABLE:
case WM831X_DC1_CONTROL_1:
case WM831X_DC1_CONTROL_2:
case WM831X_DC1_ON_CONFIG:
case WM831X_DC1_SLEEP_CONTROL:
case WM831X_DC1_DVS_CONTROL:
case WM831X_DC2_CONTROL_1:
case WM831X_DC2_CONTROL_2:
case WM831X_DC2_ON_CONFIG:
case WM831X_DC2_SLEEP_CONTROL:
case WM831X_DC2_DVS_CONTROL:
case WM831X_DC3_CONTROL_1:
case WM831X_DC3_CONTROL_2:
case WM831X_DC3_ON_CONFIG:
case WM831X_DC3_SLEEP_CONTROL:
case WM831X_DC4_CONTROL:
case WM831X_DC4_SLEEP_CONTROL:
case WM831X_EPE1_CONTROL:
case WM831X_EPE2_CONTROL:
case WM831X_LDO1_CONTROL:
case WM831X_LDO1_ON_CONTROL:
case WM831X_LDO1_SLEEP_CONTROL:
case WM831X_LDO2_CONTROL:
case WM831X_LDO2_ON_CONTROL:
case WM831X_LDO2_SLEEP_CONTROL:
case WM831X_LDO3_CONTROL:
case WM831X_LDO3_ON_CONTROL:
case WM831X_LDO3_SLEEP_CONTROL:
case WM831X_LDO4_CONTROL:
case WM831X_LDO4_ON_CONTROL:
case WM831X_LDO4_SLEEP_CONTROL:
case WM831X_LDO5_CONTROL:
case WM831X_LDO5_ON_CONTROL:
case WM831X_LDO5_SLEEP_CONTROL:
case WM831X_LDO6_CONTROL:
case WM831X_LDO6_ON_CONTROL:
case WM831X_LDO6_SLEEP_CONTROL:
case WM831X_LDO7_CONTROL:
case WM831X_LDO7_ON_CONTROL:
case WM831X_LDO7_SLEEP_CONTROL:
case WM831X_LDO8_CONTROL:
case WM831X_LDO8_ON_CONTROL:
case WM831X_LDO8_SLEEP_CONTROL:
case WM831X_LDO9_CONTROL:
case WM831X_LDO9_ON_CONTROL:
case WM831X_LDO9_SLEEP_CONTROL:
case WM831X_LDO10_CONTROL:
case WM831X_LDO10_ON_CONTROL:
case WM831X_LDO10_SLEEP_CONTROL:
case WM831X_LDO11_ON_CONTROL:
case WM831X_LDO11_SLEEP_CONTROL:
case WM831X_POWER_GOOD_SOURCE_1:
case WM831X_POWER_GOOD_SOURCE_2:
case WM831X_CLOCK_CONTROL_1:
case WM831X_CLOCK_CONTROL_2:
case WM831X_FLL_CONTROL_1:
case WM831X_FLL_CONTROL_2:
case WM831X_FLL_CONTROL_3:
case WM831X_FLL_CONTROL_4:
case WM831X_FLL_CONTROL_5:
return true;
default:
return false;
}
}
static bool wm831x_reg_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM831X_SYSTEM_STATUS:
case WM831X_ON_SOURCE:
case WM831X_OFF_SOURCE:
case WM831X_GPIO_LEVEL:
case WM831X_SYSTEM_INTERRUPTS:
case WM831X_INTERRUPT_STATUS_1:
case WM831X_INTERRUPT_STATUS_2:
case WM831X_INTERRUPT_STATUS_3:
case WM831X_INTERRUPT_STATUS_4:
case WM831X_INTERRUPT_STATUS_5:
case WM831X_RTC_TIME_1:
case WM831X_RTC_TIME_2:
case WM831X_TOUCH_DATA_X:
case WM831X_TOUCH_DATA_Y:
case WM831X_TOUCH_DATA_Z:
case WM831X_AUXADC_DATA:
case WM831X_CHARGER_STATUS:
case WM831X_DCDC_STATUS:
case WM831X_LDO_STATUS:
case WM831X_DCDC_UV_STATUS:
case WM831X_LDO_UV_STATUS:
return true;
default:
return false;
}
}
/**
* wm831x_reg_read: Read a single WM831x register.
*
* @wm831x: Device to read from.
* @reg: Register to read.
*/
int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg)
{
unsigned int val;
int ret;
ret = regmap_read(wm831x->regmap, reg, &val);
if (ret < 0)
return ret;
else
return val;
}
EXPORT_SYMBOL_GPL(wm831x_reg_read);
/**
* wm831x_bulk_read: Read multiple WM831x registers
*
* @wm831x: Device to read from
* @reg: First register
* @count: Number of registers
* @buf: Buffer to fill.
*/
int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
int count, u16 *buf)
{
return regmap_bulk_read(wm831x->regmap, reg, buf, count);
}
EXPORT_SYMBOL_GPL(wm831x_bulk_read);
static int wm831x_write(struct wm831x *wm831x, unsigned short reg,
int bytes, void *src)
{
u16 *buf = src;
int i, ret;
BUG_ON(bytes % 2);
BUG_ON(bytes <= 0);
for (i = 0; i < bytes / 2; i++) {
if (wm831x_reg_locked(wm831x, reg))
return -EPERM;
dev_vdbg(wm831x->dev, "Write %04x to R%d(0x%x)\n",
buf[i], reg + i, reg + i);
ret = regmap_write(wm831x->regmap, reg + i, buf[i]);
if (ret != 0)
return ret;
}
return 0;
}
/**
* wm831x_reg_write: Write a single WM831x register.
*
* @wm831x: Device to write to.
* @reg: Register to write to.
* @val: Value to write.
*/
int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
unsigned short val)
{
int ret;
mutex_lock(&wm831x->io_lock);
ret = wm831x_write(wm831x, reg, 2, &val);
mutex_unlock(&wm831x->io_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm831x_reg_write);
/**
* wm831x_set_bits: Set the value of a bitfield in a WM831x register
*
* @wm831x: Device to write to.
* @reg: Register to write to.
* @mask: Mask of bits to set.
* @val: Value to set (unshifted)
*/
int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
unsigned short mask, unsigned short val)
{
int ret;
mutex_lock(&wm831x->io_lock);
if (!wm831x_reg_locked(wm831x, reg))
ret = regmap_update_bits(wm831x->regmap, reg, mask, val);
else
ret = -EPERM;
mutex_unlock(&wm831x->io_lock);
return ret;
}
EXPORT_SYMBOL_GPL(wm831x_set_bits);
static const struct resource wm831x_dcdc1_resources[] = {
{
.start = WM831X_DC1_CONTROL_1,
.end = WM831X_DC1_DVS_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC1, "UV"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_HC_DC1, "HC"),
};
static const struct resource wm831x_dcdc2_resources[] = {
{
.start = WM831X_DC2_CONTROL_1,
.end = WM831X_DC2_DVS_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC2, "UV"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_HC_DC2, "HC"),
};
static const struct resource wm831x_dcdc3_resources[] = {
{
.start = WM831X_DC3_CONTROL_1,
.end = WM831X_DC3_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC3, "UV"),
};
static const struct resource wm831x_dcdc4_resources[] = {
{
.start = WM831X_DC4_CONTROL,
.end = WM831X_DC4_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC4, "UV"),
};
static const struct resource wm8320_dcdc4_buck_resources[] = {
{
.start = WM831X_DC4_CONTROL,
.end = WM832X_DC4_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_DC4, "UV"),
};
static const struct resource wm831x_gpio_resources[] = {
{
.start = WM831X_IRQ_GPIO_1,
.end = WM831X_IRQ_GPIO_16,
.flags = IORESOURCE_IRQ,
},
};
static const struct resource wm831x_isink1_resources[] = {
{
.start = WM831X_CURRENT_SINK_1,
.end = WM831X_CURRENT_SINK_1,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ(WM831X_IRQ_CS1),
};
static const struct resource wm831x_isink2_resources[] = {
{
.start = WM831X_CURRENT_SINK_2,
.end = WM831X_CURRENT_SINK_2,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ(WM831X_IRQ_CS2),
};
static const struct resource wm831x_ldo1_resources[] = {
{
.start = WM831X_LDO1_CONTROL,
.end = WM831X_LDO1_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO1, "UV"),
};
static const struct resource wm831x_ldo2_resources[] = {
{
.start = WM831X_LDO2_CONTROL,
.end = WM831X_LDO2_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO2, "UV"),
};
static const struct resource wm831x_ldo3_resources[] = {
{
.start = WM831X_LDO3_CONTROL,
.end = WM831X_LDO3_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO3, "UV"),
};
static const struct resource wm831x_ldo4_resources[] = {
{
.start = WM831X_LDO4_CONTROL,
.end = WM831X_LDO4_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO4, "UV"),
};
static const struct resource wm831x_ldo5_resources[] = {
{
.start = WM831X_LDO5_CONTROL,
.end = WM831X_LDO5_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO5, "UV"),
};
static const struct resource wm831x_ldo6_resources[] = {
{
.start = WM831X_LDO6_CONTROL,
.end = WM831X_LDO6_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO6, "UV"),
};
static const struct resource wm831x_ldo7_resources[] = {
{
.start = WM831X_LDO7_CONTROL,
.end = WM831X_LDO7_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO7, "UV"),
};
static const struct resource wm831x_ldo8_resources[] = {
{
.start = WM831X_LDO8_CONTROL,
.end = WM831X_LDO8_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO8, "UV"),
};
static const struct resource wm831x_ldo9_resources[] = {
{
.start = WM831X_LDO9_CONTROL,
.end = WM831X_LDO9_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO9, "UV"),
};
static const struct resource wm831x_ldo10_resources[] = {
{
.start = WM831X_LDO10_CONTROL,
.end = WM831X_LDO10_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_UV_LDO10, "UV"),
};
static const struct resource wm831x_ldo11_resources[] = {
{
.start = WM831X_LDO11_ON_CONTROL,
.end = WM831X_LDO11_SLEEP_CONTROL,
.flags = IORESOURCE_REG,
},
};
static const struct resource wm831x_on_resources[] = {
DEFINE_RES_IRQ(WM831X_IRQ_ON),
};
static const struct resource wm831x_power_resources[] = {
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_PPM_SYSLO, "SYSLO"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_PPM_PWR_SRC, "PWR SRC"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_PPM_USB_CURR, "USB CURR"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_BATT_HOT, "BATT HOT"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_BATT_COLD, "BATT COLD"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_BATT_FAIL, "BATT FAIL"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_OV, "OV"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_END, "END"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_TO, "TO"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_MODE, "MODE"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_CHG_START, "START"),
};
static const struct resource wm831x_rtc_resources[] = {
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_RTC_PER, "PER"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_RTC_ALM, "ALM"),
};
static const struct resource wm831x_status1_resources[] = {
{
.start = WM831X_STATUS_LED_1,
.end = WM831X_STATUS_LED_1,
.flags = IORESOURCE_REG,
},
};
static const struct resource wm831x_status2_resources[] = {
{
.start = WM831X_STATUS_LED_2,
.end = WM831X_STATUS_LED_2,
.flags = IORESOURCE_REG,
},
};
static const struct resource wm831x_touch_resources[] = {
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_TCHPD, "TCHPD"),
DEFINE_RES_IRQ_NAMED(WM831X_IRQ_TCHDATA, "TCHDATA"),
};
static const struct resource wm831x_wdt_resources[] = {
DEFINE_RES_IRQ(WM831X_IRQ_WDOG_TO),
};
static const struct mfd_cell wm8310_devs[] = {
{
.name = "wm831x-backup",
},
{
.name = "wm831x-buckv",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
.resources = wm831x_dcdc1_resources,
},
{
.name = "wm831x-buckv",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
.resources = wm831x_dcdc2_resources,
},
{
.name = "wm831x-buckp",
.id = 3,
.num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
.resources = wm831x_dcdc3_resources,
},
{
.name = "wm831x-boostp",
.id = 4,
.num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
.resources = wm831x_dcdc4_resources,
},
{
.name = "wm831x-clk",
},
{
.name = "wm831x-epe",
.id = 1,
},
{
.name = "wm831x-epe",
.id = 2,
},
{
.name = "wm831x-gpio",
.num_resources = ARRAY_SIZE(wm831x_gpio_resources),
.resources = wm831x_gpio_resources,
},
{
.name = "wm831x-hwmon",
},
{
.name = "wm831x-isink",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_isink1_resources),
.resources = wm831x_isink1_resources,
},
{
.name = "wm831x-isink",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_isink2_resources),
.resources = wm831x_isink2_resources,
},
{
.name = "wm831x-ldo",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
.resources = wm831x_ldo1_resources,
},
{
.name = "wm831x-ldo",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
.resources = wm831x_ldo2_resources,
},
{
.name = "wm831x-ldo",
.id = 3,
.num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
.resources = wm831x_ldo3_resources,
},
{
.name = "wm831x-ldo",
.id = 4,
.num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
.resources = wm831x_ldo4_resources,
},
{
.name = "wm831x-ldo",
.id = 5,
.num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
.resources = wm831x_ldo5_resources,
},
{
.name = "wm831x-ldo",
.id = 6,
.num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
.resources = wm831x_ldo6_resources,
},
{
.name = "wm831x-aldo",
.id = 7,
.num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
.resources = wm831x_ldo7_resources,
},
{
.name = "wm831x-aldo",
.id = 8,
.num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
.resources = wm831x_ldo8_resources,
},
{
.name = "wm831x-aldo",
.id = 9,
.num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
.resources = wm831x_ldo9_resources,
},
{
.name = "wm831x-aldo",
.id = 10,
.num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
.resources = wm831x_ldo10_resources,
},
{
.name = "wm831x-alive-ldo",
.id = 11,
.num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
.resources = wm831x_ldo11_resources,
},
{
.name = "wm831x-on",
.num_resources = ARRAY_SIZE(wm831x_on_resources),
.resources = wm831x_on_resources,
},
{
.name = "wm831x-power",
.num_resources = ARRAY_SIZE(wm831x_power_resources),
.resources = wm831x_power_resources,
},
{
.name = "wm831x-status",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_status1_resources),
.resources = wm831x_status1_resources,
},
{
.name = "wm831x-status",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_status2_resources),
.resources = wm831x_status2_resources,
},
{
.name = "wm831x-watchdog",
.num_resources = ARRAY_SIZE(wm831x_wdt_resources),
.resources = wm831x_wdt_resources,
},
};
static const struct mfd_cell wm8311_devs[] = {
{
.name = "wm831x-backup",
},
{
.name = "wm831x-buckv",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
.resources = wm831x_dcdc1_resources,
},
{
.name = "wm831x-buckv",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
.resources = wm831x_dcdc2_resources,
},
{
.name = "wm831x-buckp",
.id = 3,
.num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
.resources = wm831x_dcdc3_resources,
},
{
.name = "wm831x-boostp",
.id = 4,
.num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
.resources = wm831x_dcdc4_resources,
},
{
.name = "wm831x-clk",
},
{
.name = "wm831x-epe",
.id = 1,
},
{
.name = "wm831x-epe",
.id = 2,
},
{
.name = "wm831x-gpio",
.num_resources = ARRAY_SIZE(wm831x_gpio_resources),
.resources = wm831x_gpio_resources,
},
{
.name = "wm831x-hwmon",
},
{
.name = "wm831x-isink",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_isink1_resources),
.resources = wm831x_isink1_resources,
},
{
.name = "wm831x-isink",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_isink2_resources),
.resources = wm831x_isink2_resources,
},
{
.name = "wm831x-ldo",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
.resources = wm831x_ldo1_resources,
},
{
.name = "wm831x-ldo",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
.resources = wm831x_ldo2_resources,
},
{
.name = "wm831x-ldo",
.id = 3,
.num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
.resources = wm831x_ldo3_resources,
},
{
.name = "wm831x-ldo",
.id = 4,
.num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
.resources = wm831x_ldo4_resources,
},
{
.name = "wm831x-ldo",
.id = 5,
.num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
.resources = wm831x_ldo5_resources,
},
{
.name = "wm831x-aldo",
.id = 7,
.num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
.resources = wm831x_ldo7_resources,
},
{
.name = "wm831x-alive-ldo",
.id = 11,
.num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
.resources = wm831x_ldo11_resources,
},
{
.name = "wm831x-on",
.num_resources = ARRAY_SIZE(wm831x_on_resources),
.resources = wm831x_on_resources,
},
{
.name = "wm831x-power",
.num_resources = ARRAY_SIZE(wm831x_power_resources),
.resources = wm831x_power_resources,
},
{
.name = "wm831x-status",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_status1_resources),
.resources = wm831x_status1_resources,
},
{
.name = "wm831x-status",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_status2_resources),
.resources = wm831x_status2_resources,
},
{
.name = "wm831x-watchdog",
.num_resources = ARRAY_SIZE(wm831x_wdt_resources),
.resources = wm831x_wdt_resources,
},
};
static const struct mfd_cell wm8312_devs[] = {
{
.name = "wm831x-backup",
},
{
.name = "wm831x-buckv",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
.resources = wm831x_dcdc1_resources,
},
{
.name = "wm831x-buckv",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
.resources = wm831x_dcdc2_resources,
},
{
.name = "wm831x-buckp",
.id = 3,
.num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
.resources = wm831x_dcdc3_resources,
},
{
.name = "wm831x-boostp",
.id = 4,
.num_resources = ARRAY_SIZE(wm831x_dcdc4_resources),
.resources = wm831x_dcdc4_resources,
},
{
.name = "wm831x-clk",
},
{
.name = "wm831x-epe",
.id = 1,
},
{
.name = "wm831x-epe",
.id = 2,
},
{
.name = "wm831x-gpio",
.num_resources = ARRAY_SIZE(wm831x_gpio_resources),
.resources = wm831x_gpio_resources,
},
{
.name = "wm831x-hwmon",
},
{
.name = "wm831x-isink",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_isink1_resources),
.resources = wm831x_isink1_resources,
},
{
.name = "wm831x-isink",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_isink2_resources),
.resources = wm831x_isink2_resources,
},
{
.name = "wm831x-ldo",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
.resources = wm831x_ldo1_resources,
},
{
.name = "wm831x-ldo",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
.resources = wm831x_ldo2_resources,
},
{
.name = "wm831x-ldo",
.id = 3,
.num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
.resources = wm831x_ldo3_resources,
},
{
.name = "wm831x-ldo",
.id = 4,
.num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
.resources = wm831x_ldo4_resources,
},
{
.name = "wm831x-ldo",
.id = 5,
.num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
.resources = wm831x_ldo5_resources,
},
{
.name = "wm831x-ldo",
.id = 6,
.num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
.resources = wm831x_ldo6_resources,
},
{
.name = "wm831x-aldo",
.id = 7,
.num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
.resources = wm831x_ldo7_resources,
},
{
.name = "wm831x-aldo",
.id = 8,
.num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
.resources = wm831x_ldo8_resources,
},
{
.name = "wm831x-aldo",
.id = 9,
.num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
.resources = wm831x_ldo9_resources,
},
{
.name = "wm831x-aldo",
.id = 10,
.num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
.resources = wm831x_ldo10_resources,
},
{
.name = "wm831x-alive-ldo",
.id = 11,
.num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
.resources = wm831x_ldo11_resources,
},
{
.name = "wm831x-on",
.num_resources = ARRAY_SIZE(wm831x_on_resources),
.resources = wm831x_on_resources,
},
{
.name = "wm831x-power",
.num_resources = ARRAY_SIZE(wm831x_power_resources),
.resources = wm831x_power_resources,
},
{
.name = "wm831x-status",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_status1_resources),
.resources = wm831x_status1_resources,
},
{
.name = "wm831x-status",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_status2_resources),
.resources = wm831x_status2_resources,
},
{
.name = "wm831x-watchdog",
.num_resources = ARRAY_SIZE(wm831x_wdt_resources),
.resources = wm831x_wdt_resources,
},
};
static const struct mfd_cell wm8320_devs[] = {
{
.name = "wm831x-backup",
},
{
.name = "wm831x-buckv",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_dcdc1_resources),
.resources = wm831x_dcdc1_resources,
},
{
.name = "wm831x-buckv",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_dcdc2_resources),
.resources = wm831x_dcdc2_resources,
},
{
.name = "wm831x-buckp",
.id = 3,
.num_resources = ARRAY_SIZE(wm831x_dcdc3_resources),
.resources = wm831x_dcdc3_resources,
},
{
.name = "wm831x-buckp",
.id = 4,
.num_resources = ARRAY_SIZE(wm8320_dcdc4_buck_resources),
.resources = wm8320_dcdc4_buck_resources,
},
{
.name = "wm831x-clk",
},
{
.name = "wm831x-gpio",
.num_resources = ARRAY_SIZE(wm831x_gpio_resources),
.resources = wm831x_gpio_resources,
},
{
.name = "wm831x-hwmon",
},
{
.name = "wm831x-ldo",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_ldo1_resources),
.resources = wm831x_ldo1_resources,
},
{
.name = "wm831x-ldo",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_ldo2_resources),
.resources = wm831x_ldo2_resources,
},
{
.name = "wm831x-ldo",
.id = 3,
.num_resources = ARRAY_SIZE(wm831x_ldo3_resources),
.resources = wm831x_ldo3_resources,
},
{
.name = "wm831x-ldo",
.id = 4,
.num_resources = ARRAY_SIZE(wm831x_ldo4_resources),
.resources = wm831x_ldo4_resources,
},
{
.name = "wm831x-ldo",
.id = 5,
.num_resources = ARRAY_SIZE(wm831x_ldo5_resources),
.resources = wm831x_ldo5_resources,
},
{
.name = "wm831x-ldo",
.id = 6,
.num_resources = ARRAY_SIZE(wm831x_ldo6_resources),
.resources = wm831x_ldo6_resources,
},
{
.name = "wm831x-aldo",
.id = 7,
.num_resources = ARRAY_SIZE(wm831x_ldo7_resources),
.resources = wm831x_ldo7_resources,
},
{
.name = "wm831x-aldo",
.id = 8,
.num_resources = ARRAY_SIZE(wm831x_ldo8_resources),
.resources = wm831x_ldo8_resources,
},
{
.name = "wm831x-aldo",
.id = 9,
.num_resources = ARRAY_SIZE(wm831x_ldo9_resources),
.resources = wm831x_ldo9_resources,
},
{
.name = "wm831x-aldo",
.id = 10,
.num_resources = ARRAY_SIZE(wm831x_ldo10_resources),
.resources = wm831x_ldo10_resources,
},
{
.name = "wm831x-alive-ldo",
.id = 11,
.num_resources = ARRAY_SIZE(wm831x_ldo11_resources),
.resources = wm831x_ldo11_resources,
},
{
.name = "wm831x-on",
.num_resources = ARRAY_SIZE(wm831x_on_resources),
.resources = wm831x_on_resources,
},
{
.name = "wm831x-status",
.id = 1,
.num_resources = ARRAY_SIZE(wm831x_status1_resources),
.resources = wm831x_status1_resources,
},
{
.name = "wm831x-status",
.id = 2,
.num_resources = ARRAY_SIZE(wm831x_status2_resources),
.resources = wm831x_status2_resources,
},
{
.name = "wm831x-watchdog",
.num_resources = ARRAY_SIZE(wm831x_wdt_resources),
.resources = wm831x_wdt_resources,
},
};
static const struct mfd_cell touch_devs[] = {
{
.name = "wm831x-touch",
.num_resources = ARRAY_SIZE(wm831x_touch_resources),
.resources = wm831x_touch_resources,
},
};
static const struct mfd_cell rtc_devs[] = {
{
.name = "wm831x-rtc",
.num_resources = ARRAY_SIZE(wm831x_rtc_resources),
.resources = wm831x_rtc_resources,
},
};
static const struct mfd_cell backlight_devs[] = {
{
.name = "wm831x-backlight",
},
};
struct regmap_config wm831x_regmap_config = {
.reg_bits = 16,
.val_bits = 16,
.cache_type = REGCACHE_MAPLE,
.max_register = WM831X_DBE_CHECK_DATA,
.readable_reg = wm831x_reg_readable,
.writeable_reg = wm831x_reg_writeable,
.volatile_reg = wm831x_reg_volatile,
};
EXPORT_SYMBOL_GPL(wm831x_regmap_config);
const struct of_device_id wm831x_of_match[] = {
{ .compatible = "wlf,wm8310", .data = (void *)WM8310 },
{ .compatible = "wlf,wm8311", .data = (void *)WM8311 },
{ .compatible = "wlf,wm8312", .data = (void *)WM8312 },
{ .compatible = "wlf,wm8320", .data = (void *)WM8320 },
{ .compatible = "wlf,wm8321", .data = (void *)WM8321 },
{ .compatible = "wlf,wm8325", .data = (void *)WM8325 },
{ .compatible = "wlf,wm8326", .data = (void *)WM8326 },
{ },
};
EXPORT_SYMBOL_GPL(wm831x_of_match);
/*
* Instantiate the generic non-control parts of the device.
*/
int wm831x_device_init(struct wm831x *wm831x, int irq)
{
struct wm831x_pdata *pdata = &wm831x->pdata;
int rev, wm831x_num;
enum wm831x_parent parent;
int ret, i;
mutex_init(&wm831x->io_lock);
mutex_init(&wm831x->key_lock);
dev_set_drvdata(wm831x->dev, wm831x);
wm831x->soft_shutdown = pdata->soft_shutdown;
ret = wm831x_reg_read(wm831x, WM831X_PARENT_ID);
if (ret < 0) {
dev_err(wm831x->dev, "Failed to read parent ID: %d\n", ret);
goto err;
}
switch (ret) {
case 0x6204:
case 0x6246:
break;
default:
dev_err(wm831x->dev, "Device is not a WM831x: ID %x\n", ret);
ret = -EINVAL;
goto err;
}
ret = wm831x_reg_read(wm831x, WM831X_REVISION);
if (ret < 0) {
dev_err(wm831x->dev, "Failed to read revision: %d\n", ret);
goto err;
}
rev = (ret & WM831X_PARENT_REV_MASK) >> WM831X_PARENT_REV_SHIFT;
ret = wm831x_reg_read(wm831x, WM831X_RESET_ID);
if (ret < 0) {
dev_err(wm831x->dev, "Failed to read device ID: %d\n", ret);
goto err;
}
/* Some engineering samples do not have the ID set, rely on
* the device being registered correctly.
*/
if (ret == 0) {
dev_info(wm831x->dev, "Device is an engineering sample\n");
ret = wm831x->type;
}
switch (ret) {
case WM8310:
parent = WM8310;
wm831x->num_gpio = 16;
wm831x->charger_irq_wake = 1;
if (rev > 0) {
wm831x->has_gpio_ena = 1;
wm831x->has_cs_sts = 1;
}
dev_info(wm831x->dev, "WM8310 revision %c\n", 'A' + rev);
break;
case WM8311:
parent = WM8311;
wm831x->num_gpio = 16;
wm831x->charger_irq_wake = 1;
if (rev > 0) {
wm831x->has_gpio_ena = 1;
wm831x->has_cs_sts = 1;
}
dev_info(wm831x->dev, "WM8311 revision %c\n", 'A' + rev);
break;
case WM8312:
parent = WM8312;
wm831x->num_gpio = 16;
wm831x->charger_irq_wake = 1;
if (rev > 0) {
wm831x->has_gpio_ena = 1;
wm831x->has_cs_sts = 1;
}
dev_info(wm831x->dev, "WM8312 revision %c\n", 'A' + rev);
break;
case WM8320:
parent = WM8320;
wm831x->num_gpio = 12;
dev_info(wm831x->dev, "WM8320 revision %c\n", 'A' + rev);
break;
case WM8321:
parent = WM8321;
wm831x->num_gpio = 12;
dev_info(wm831x->dev, "WM8321 revision %c\n", 'A' + rev);
break;
case WM8325:
parent = WM8325;
wm831x->num_gpio = 12;
dev_info(wm831x->dev, "WM8325 revision %c\n", 'A' + rev);
break;
case WM8326:
parent = WM8326;
wm831x->num_gpio = 12;
dev_info(wm831x->dev, "WM8326 revision %c\n", 'A' + rev);
break;
default:
dev_err(wm831x->dev, "Unknown WM831x device %04x\n", ret);
ret = -EINVAL;
goto err;
}
/* This will need revisiting in future but is OK for all
* current parts.
*/
if (parent != wm831x->type)
dev_warn(wm831x->dev, "Device was registered as a WM%x\n",
wm831x->type);
/* Bootstrap the user key */
ret = wm831x_reg_read(wm831x, WM831X_SECURITY_KEY);
if (ret < 0) {
dev_err(wm831x->dev, "Failed to read security key: %d\n", ret);
goto err;
}
if (ret != 0) {
dev_warn(wm831x->dev, "Security key had non-zero value %x\n",
ret);
wm831x_reg_write(wm831x, WM831X_SECURITY_KEY, 0);
}
wm831x->locked = 1;
if (pdata->pre_init) {
ret = pdata->pre_init(wm831x);
if (ret != 0) {
dev_err(wm831x->dev, "pre_init() failed: %d\n", ret);
goto err;
}
}
for (i = 0; i < ARRAY_SIZE(pdata->gpio_defaults); i++) {
if (!pdata->gpio_defaults[i])
continue;
wm831x_reg_write(wm831x,
WM831X_GPIO1_CONTROL + i,
pdata->gpio_defaults[i] & 0xffff);
}
/* Multiply by 10 as we have many subdevices of the same type */
if (pdata->wm831x_num)
wm831x_num = pdata->wm831x_num * 10;
else
wm831x_num = -1;
ret = wm831x_irq_init(wm831x, irq);
if (ret != 0)
goto err;
wm831x_auxadc_init(wm831x);
/* The core device is up, instantiate the subdevices. */
switch (parent) {
case WM8310:
ret = mfd_add_devices(wm831x->dev, wm831x_num,
wm8310_devs, ARRAY_SIZE(wm8310_devs),
NULL, 0, NULL);
break;
case WM8311:
ret = mfd_add_devices(wm831x->dev, wm831x_num,
wm8311_devs, ARRAY_SIZE(wm8311_devs),
NULL, 0, NULL);
if (!pdata->disable_touch)
mfd_add_devices(wm831x->dev, wm831x_num,
touch_devs, ARRAY_SIZE(touch_devs),
NULL, 0, NULL);
break;
case WM8312:
ret = mfd_add_devices(wm831x->dev, wm831x_num,
wm8312_devs, ARRAY_SIZE(wm8312_devs),
NULL, 0, NULL);
if (!pdata->disable_touch)
mfd_add_devices(wm831x->dev, wm831x_num,
touch_devs, ARRAY_SIZE(touch_devs),
NULL, 0, NULL);
break;
case WM8320:
case WM8321:
case WM8325:
case WM8326:
ret = mfd_add_devices(wm831x->dev, wm831x_num,
wm8320_devs, ARRAY_SIZE(wm8320_devs),
NULL, 0, NULL);
break;
default:
/* If this happens the bus probe function is buggy */
BUG();
}
if (ret != 0) {
dev_err(wm831x->dev, "Failed to add children\n");
goto err_irq;
}
/* The RTC can only be used if the 32.768kHz crystal is
* enabled; this can't be controlled by software at runtime.
*/
ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
if (ret < 0) {
dev_err(wm831x->dev, "Failed to read clock status: %d\n", ret);
goto err_irq;
}
if (ret & WM831X_XTAL_ENA) {
ret = mfd_add_devices(wm831x->dev, wm831x_num,
rtc_devs, ARRAY_SIZE(rtc_devs),
NULL, 0, NULL);
if (ret != 0) {
dev_err(wm831x->dev, "Failed to add RTC: %d\n", ret);
goto err_irq;
}
} else {
dev_info(wm831x->dev, "32.768kHz clock disabled, no RTC\n");
}
if (pdata->backlight) {
/* Treat errors as non-critical */
ret = mfd_add_devices(wm831x->dev, wm831x_num, backlight_devs,
ARRAY_SIZE(backlight_devs), NULL,
0, NULL);
if (ret < 0)
dev_err(wm831x->dev, "Failed to add backlight: %d\n",
ret);
}
wm831x_otp_init(wm831x);
if (pdata->post_init) {
ret = pdata->post_init(wm831x);
if (ret != 0) {
dev_err(wm831x->dev, "post_init() failed: %d\n", ret);
goto err_irq;
}
}
return 0;
err_irq:
wm831x_irq_exit(wm831x);
err:
mfd_remove_devices(wm831x->dev);
return ret;
}
int wm831x_device_suspend(struct wm831x *wm831x)
{
int reg, mask;
/* If the charger IRQs are a wake source then make sure we ack
* them even if they're not actively being used (eg, no power
* driver or no IRQ line wired up) then acknowledge the
* interrupts otherwise suspend won't last very long.
*/
if (wm831x->charger_irq_wake) {
reg = wm831x_reg_read(wm831x, WM831X_INTERRUPT_STATUS_2_MASK);
mask = WM831X_CHG_BATT_HOT_EINT |
WM831X_CHG_BATT_COLD_EINT |
WM831X_CHG_BATT_FAIL_EINT |
WM831X_CHG_OV_EINT | WM831X_CHG_END_EINT |
WM831X_CHG_TO_EINT | WM831X_CHG_MODE_EINT |
WM831X_CHG_START_EINT;
/* If any of the interrupts are masked read the statuses */
if (reg & mask)
reg = wm831x_reg_read(wm831x,
WM831X_INTERRUPT_STATUS_2);
if (reg & mask) {
dev_info(wm831x->dev,
"Acknowledging masked charger IRQs: %x\n",
reg & mask);
wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_2,
reg & mask);
}
}
return 0;
}
void wm831x_device_shutdown(struct wm831x *wm831x)
{
if (wm831x->soft_shutdown) {
dev_info(wm831x->dev, "Initiating shutdown...\n");
wm831x_set_bits(wm831x, WM831X_POWER_STATE, WM831X_CHIP_ON, 0);
}
}
EXPORT_SYMBOL_GPL(wm831x_device_shutdown);
| linux-master | drivers/mfd/wm831x-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Ampere Altra Family SMPro core driver
* Copyright (c) 2022, Ampere Computing LLC
*/
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
/* Identification Registers */
#define MANUFACTURER_ID_REG 0x02
#define AMPERE_MANUFACTURER_ID 0xCD3A
#define CORE_CE_ERR_DATA 0x82
#define CORE_UE_ERR_DATA 0x85
#define MEM_CE_ERR_DATA 0x92
#define MEM_UE_ERR_DATA 0x95
#define PCIE_CE_ERR_DATA 0xC2
#define PCIE_UE_ERR_DATA 0xC5
#define OTHER_CE_ERR_DATA 0xD2
#define OTHER_UE_ERR_DATA 0xDA
static int smpro_core_write(void *context, const void *data, size_t count)
{
struct device *dev = context;
struct i2c_client *i2c = to_i2c_client(dev);
int ret;
ret = i2c_master_send(i2c, data, count);
if (unlikely(ret != count))
return (ret < 0) ? ret : -EIO;
return 0;
}
static int smpro_core_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct device *dev = context;
struct i2c_client *i2c = to_i2c_client(dev);
struct i2c_msg xfer[2];
unsigned char buf[2];
int ret;
xfer[0].addr = i2c->addr;
xfer[0].flags = 0;
buf[0] = *(u8 *)reg;
buf[1] = val_size;
xfer[0].len = 2;
xfer[0].buf = buf;
xfer[1].addr = i2c->addr;
xfer[1].flags = I2C_M_RD;
xfer[1].len = val_size;
xfer[1].buf = val;
ret = i2c_transfer(i2c->adapter, xfer, 2);
if (unlikely(ret != 2))
return (ret < 0) ? ret : -EIO;
return 0;
}
static const struct regmap_bus smpro_regmap_bus = {
.read = smpro_core_read,
.write = smpro_core_write,
.val_format_endian_default = REGMAP_ENDIAN_BIG,
};
static bool smpro_core_readable_noinc_reg(struct device *dev, unsigned int reg)
{
return (reg == CORE_CE_ERR_DATA || reg == CORE_UE_ERR_DATA ||
reg == MEM_CE_ERR_DATA || reg == MEM_UE_ERR_DATA ||
reg == PCIE_CE_ERR_DATA || reg == PCIE_UE_ERR_DATA ||
reg == OTHER_CE_ERR_DATA || reg == OTHER_UE_ERR_DATA);
}
static const struct regmap_config smpro_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.readable_noinc_reg = smpro_core_readable_noinc_reg,
};
static const struct mfd_cell smpro_devs[] = {
MFD_CELL_NAME("smpro-hwmon"),
MFD_CELL_NAME("smpro-errmon"),
MFD_CELL_NAME("smpro-misc"),
};
static int smpro_core_probe(struct i2c_client *i2c)
{
const struct regmap_config *config;
struct regmap *regmap;
unsigned int val;
int ret;
config = device_get_match_data(&i2c->dev);
if (!config)
return -EINVAL;
regmap = devm_regmap_init(&i2c->dev, &smpro_regmap_bus, &i2c->dev, config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = regmap_read(regmap, MANUFACTURER_ID_REG, &val);
if (ret)
return ret;
if (val != AMPERE_MANUFACTURER_ID)
return -ENODEV;
return devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
smpro_devs, ARRAY_SIZE(smpro_devs), NULL, 0, NULL);
}
static const struct of_device_id smpro_core_of_match[] = {
{ .compatible = "ampere,smpro", .data = &smpro_regmap_config },
{}
};
MODULE_DEVICE_TABLE(of, smpro_core_of_match);
static struct i2c_driver smpro_core_driver = {
.probe = smpro_core_probe,
.driver = {
.name = "smpro-core",
.of_match_table = smpro_core_of_match,
},
};
module_i2c_driver(smpro_core_driver);
MODULE_AUTHOR("Quan Nguyen <[email protected]>");
MODULE_DESCRIPTION("SMPRO CORE - I2C driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/smpro-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8994-core.c -- Device access for Wolfson WM8994
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/mfd/core.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/wm8994/core.h>
#include <linux/mfd/wm8994/pdata.h>
#include <linux/mfd/wm8994/registers.h>
#include "wm8994.h"
static const struct mfd_cell wm8994_regulator_devs[] = {
{
.name = "wm8994-ldo",
.id = 0,
.pm_runtime_no_callbacks = true,
},
{
.name = "wm8994-ldo",
.id = 1,
.pm_runtime_no_callbacks = true,
},
};
static const struct resource wm8994_codec_resources[] = {
{
.start = WM8994_IRQ_TEMP_SHUT,
.end = WM8994_IRQ_TEMP_WARN,
.flags = IORESOURCE_IRQ,
},
};
static const struct resource wm8994_gpio_resources[] = {
{
.start = WM8994_IRQ_GPIO(1),
.end = WM8994_IRQ_GPIO(11),
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell wm8994_devs[] = {
{
.name = "wm8994-codec",
.num_resources = ARRAY_SIZE(wm8994_codec_resources),
.resources = wm8994_codec_resources,
},
{
.name = "wm8994-gpio",
.num_resources = ARRAY_SIZE(wm8994_gpio_resources),
.resources = wm8994_gpio_resources,
.pm_runtime_no_callbacks = true,
},
};
/*
* Supplies for the main bulk of CODEC; the LDO supplies are ignored
* and should be handled via the standard regulator API supply
* management.
*/
static const char *wm1811_main_supplies[] = {
"DBVDD1",
"DBVDD2",
"DBVDD3",
"DCVDD",
"AVDD1",
"AVDD2",
"CPVDD",
"SPKVDD1",
"SPKVDD2",
};
static const char *wm8994_main_supplies[] = {
"DBVDD",
"DCVDD",
"AVDD1",
"AVDD2",
"CPVDD",
"SPKVDD1",
"SPKVDD2",
};
static const char *wm8958_main_supplies[] = {
"DBVDD1",
"DBVDD2",
"DBVDD3",
"DCVDD",
"AVDD1",
"AVDD2",
"CPVDD",
"SPKVDD1",
"SPKVDD2",
};
static int wm8994_suspend(struct device *dev)
{
struct wm8994 *wm8994 = dev_get_drvdata(dev);
int ret;
/* Don't actually go through with the suspend if the CODEC is
* still active for accessory detect. */
switch (wm8994->type) {
case WM8958:
case WM1811:
ret = wm8994_reg_read(wm8994, WM8958_MIC_DETECT_1);
if (ret < 0) {
dev_err(dev, "Failed to read power status: %d\n", ret);
} else if (ret & WM8958_MICD_ENA) {
dev_dbg(dev, "CODEC still active, ignoring suspend\n");
return 0;
}
break;
default:
break;
}
/* Disable LDO pulldowns while the device is suspended if we
* don't know that something will be driving them. */
if (!wm8994->ldo_ena_always_driven)
wm8994_set_bits(wm8994, WM8994_PULL_CONTROL_2,
WM8994_LDO1ENA_PD | WM8994_LDO2ENA_PD,
WM8994_LDO1ENA_PD | WM8994_LDO2ENA_PD);
/* Explicitly put the device into reset in case regulators
* don't get disabled in order to ensure consistent restart.
*/
wm8994_reg_write(wm8994, WM8994_SOFTWARE_RESET,
wm8994_reg_read(wm8994, WM8994_SOFTWARE_RESET));
regcache_mark_dirty(wm8994->regmap);
/* Restore GPIO registers to prevent problems with mismatched
* pin configurations.
*/
ret = regcache_sync_region(wm8994->regmap, WM8994_GPIO_1,
WM8994_GPIO_11);
if (ret != 0)
dev_err(dev, "Failed to restore GPIO registers: %d\n", ret);
/* In case one of the GPIOs is used as a wake input. */
ret = regcache_sync_region(wm8994->regmap,
WM8994_INTERRUPT_STATUS_1_MASK,
WM8994_INTERRUPT_STATUS_1_MASK);
if (ret != 0)
dev_err(dev, "Failed to restore interrupt mask: %d\n", ret);
regcache_cache_only(wm8994->regmap, true);
wm8994->suspended = true;
ret = regulator_bulk_disable(wm8994->num_supplies,
wm8994->supplies);
if (ret != 0) {
dev_err(dev, "Failed to disable supplies: %d\n", ret);
return ret;
}
return 0;
}
static int wm8994_resume(struct device *dev)
{
struct wm8994 *wm8994 = dev_get_drvdata(dev);
int ret;
/* We may have lied to the PM core about suspending */
if (!wm8994->suspended)
return 0;
ret = regulator_bulk_enable(wm8994->num_supplies,
wm8994->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
regcache_cache_only(wm8994->regmap, false);
ret = regcache_sync(wm8994->regmap);
if (ret != 0) {
dev_err(dev, "Failed to restore register map: %d\n", ret);
goto err_enable;
}
/* Disable LDO pulldowns while the device is active */
wm8994_set_bits(wm8994, WM8994_PULL_CONTROL_2,
WM8994_LDO1ENA_PD | WM8994_LDO2ENA_PD,
0);
wm8994->suspended = false;
return 0;
err_enable:
regulator_bulk_disable(wm8994->num_supplies, wm8994->supplies);
return ret;
}
#ifdef CONFIG_REGULATOR
static int wm8994_ldo_in_use(struct wm8994_pdata *pdata, int ldo)
{
struct wm8994_ldo_pdata *ldo_pdata;
if (!pdata)
return 0;
ldo_pdata = &pdata->ldo[ldo];
if (!ldo_pdata->init_data)
return 0;
return ldo_pdata->init_data->num_consumer_supplies != 0;
}
#else
static int wm8994_ldo_in_use(struct wm8994_pdata *pdata, int ldo)
{
return 0;
}
#endif
static const struct reg_sequence wm8994_revc_patch[] = {
{ 0x102, 0x3 },
{ 0x56, 0x3 },
{ 0x817, 0x0 },
{ 0x102, 0x0 },
};
static const struct reg_sequence wm8958_reva_patch[] = {
{ 0x102, 0x3 },
{ 0xcb, 0x81 },
{ 0x817, 0x0 },
{ 0x102, 0x0 },
};
static const struct reg_sequence wm1811_reva_patch[] = {
{ 0x102, 0x3 },
{ 0x56, 0xc07 },
{ 0x5d, 0x7e },
{ 0x5e, 0x0 },
{ 0x102, 0x0 },
};
#ifdef CONFIG_OF
static int wm8994_set_pdata_from_of(struct wm8994 *wm8994)
{
struct device_node *np = wm8994->dev->of_node;
struct wm8994_pdata *pdata = &wm8994->pdata;
int i;
if (!np)
return 0;
if (of_property_read_u32_array(np, "wlf,gpio-cfg", pdata->gpio_defaults,
ARRAY_SIZE(pdata->gpio_defaults)) >= 0) {
for (i = 0; i < ARRAY_SIZE(pdata->gpio_defaults); i++) {
if (wm8994->pdata.gpio_defaults[i] == 0)
pdata->gpio_defaults[i]
= WM8994_CONFIGURE_GPIO;
}
}
of_property_read_u32_array(np, "wlf,micbias-cfg", pdata->micbias,
ARRAY_SIZE(pdata->micbias));
pdata->lineout1_diff = !of_property_read_bool(np, "wlf,lineout1-se");
pdata->lineout2_diff = !of_property_read_bool(np, "wlf,lineout2-se");
pdata->lineout1fb = of_property_read_bool(np, "wlf,lineout1-feedback");
pdata->lineout2fb = of_property_read_bool(np, "wlf,lineout2-feedback") ||
of_property_read_bool(np, "wlf,ldoena-always-driven");
pdata->spkmode_pu = of_property_read_bool(np, "wlf,spkmode-pu");
pdata->csnaddr_pd = of_property_read_bool(np, "wlf,csnaddr-pd");
return 0;
}
#else
static int wm8994_set_pdata_from_of(struct wm8994 *wm8994)
{
return 0;
}
#endif
/*
* Instantiate the generic non-control parts of the device.
*/
static int wm8994_device_init(struct wm8994 *wm8994, int irq)
{
struct wm8994_pdata *pdata;
struct regmap_config *regmap_config;
const struct reg_sequence *regmap_patch = NULL;
const char *devname;
int ret, i, patch_regs = 0;
int pulls = 0;
if (dev_get_platdata(wm8994->dev)) {
pdata = dev_get_platdata(wm8994->dev);
wm8994->pdata = *pdata;
}
pdata = &wm8994->pdata;
ret = wm8994_set_pdata_from_of(wm8994);
if (ret != 0)
return ret;
/* Add the on-chip regulators first for bootstrapping */
ret = mfd_add_devices(wm8994->dev, 0,
wm8994_regulator_devs,
ARRAY_SIZE(wm8994_regulator_devs),
NULL, 0, NULL);
if (ret != 0) {
dev_err(wm8994->dev, "Failed to add children: %d\n", ret);
goto err;
}
switch (wm8994->type) {
case WM1811:
wm8994->num_supplies = ARRAY_SIZE(wm1811_main_supplies);
break;
case WM8994:
wm8994->num_supplies = ARRAY_SIZE(wm8994_main_supplies);
break;
case WM8958:
wm8994->num_supplies = ARRAY_SIZE(wm8958_main_supplies);
break;
default:
BUG();
goto err;
}
wm8994->supplies = devm_kcalloc(wm8994->dev,
wm8994->num_supplies,
sizeof(struct regulator_bulk_data),
GFP_KERNEL);
if (!wm8994->supplies) {
ret = -ENOMEM;
goto err;
}
switch (wm8994->type) {
case WM1811:
for (i = 0; i < ARRAY_SIZE(wm1811_main_supplies); i++)
wm8994->supplies[i].supply = wm1811_main_supplies[i];
break;
case WM8994:
for (i = 0; i < ARRAY_SIZE(wm8994_main_supplies); i++)
wm8994->supplies[i].supply = wm8994_main_supplies[i];
break;
case WM8958:
for (i = 0; i < ARRAY_SIZE(wm8958_main_supplies); i++)
wm8994->supplies[i].supply = wm8958_main_supplies[i];
break;
default:
BUG();
goto err;
}
/*
* Can't use devres helper here as some of the supplies are provided by
* wm8994->dev's children (regulators) and those regulators are
* unregistered by the devres core before the supplies are freed.
*/
ret = regulator_bulk_get(wm8994->dev, wm8994->num_supplies,
wm8994->supplies);
if (ret != 0) {
if (ret != -EPROBE_DEFER)
dev_err(wm8994->dev, "Failed to get supplies: %d\n",
ret);
goto err;
}
ret = regulator_bulk_enable(wm8994->num_supplies, wm8994->supplies);
if (ret != 0) {
dev_err(wm8994->dev, "Failed to enable supplies: %d\n", ret);
goto err_regulator_free;
}
ret = wm8994_reg_read(wm8994, WM8994_SOFTWARE_RESET);
if (ret < 0) {
dev_err(wm8994->dev, "Failed to read ID register\n");
goto err_enable;
}
switch (ret) {
case 0x1811:
devname = "WM1811";
if (wm8994->type != WM1811)
dev_warn(wm8994->dev, "Device registered as type %d\n",
wm8994->type);
wm8994->type = WM1811;
break;
case 0x8994:
devname = "WM8994";
if (wm8994->type != WM8994)
dev_warn(wm8994->dev, "Device registered as type %d\n",
wm8994->type);
wm8994->type = WM8994;
break;
case 0x8958:
devname = "WM8958";
if (wm8994->type != WM8958)
dev_warn(wm8994->dev, "Device registered as type %d\n",
wm8994->type);
wm8994->type = WM8958;
break;
default:
dev_err(wm8994->dev, "Device is not a WM8994, ID is %x\n",
ret);
ret = -EINVAL;
goto err_enable;
}
ret = wm8994_reg_read(wm8994, WM8994_CHIP_REVISION);
if (ret < 0) {
dev_err(wm8994->dev, "Failed to read revision register: %d\n",
ret);
goto err_enable;
}
wm8994->revision = ret & WM8994_CHIP_REV_MASK;
wm8994->cust_id = (ret & WM8994_CUST_ID_MASK) >> WM8994_CUST_ID_SHIFT;
switch (wm8994->type) {
case WM8994:
switch (wm8994->revision) {
case 0:
case 1:
dev_warn(wm8994->dev,
"revision %c not fully supported\n",
'A' + wm8994->revision);
break;
case 2:
case 3:
default:
regmap_patch = wm8994_revc_patch;
patch_regs = ARRAY_SIZE(wm8994_revc_patch);
break;
}
break;
case WM8958:
switch (wm8994->revision) {
case 0:
regmap_patch = wm8958_reva_patch;
patch_regs = ARRAY_SIZE(wm8958_reva_patch);
break;
default:
break;
}
break;
case WM1811:
/* Revision C did not change the relevant layer */
if (wm8994->revision > 1)
wm8994->revision++;
regmap_patch = wm1811_reva_patch;
patch_regs = ARRAY_SIZE(wm1811_reva_patch);
break;
default:
break;
}
dev_info(wm8994->dev, "%s revision %c CUST_ID %02x\n", devname,
'A' + wm8994->revision, wm8994->cust_id);
switch (wm8994->type) {
case WM1811:
regmap_config = &wm1811_regmap_config;
break;
case WM8994:
regmap_config = &wm8994_regmap_config;
break;
case WM8958:
regmap_config = &wm8958_regmap_config;
break;
default:
dev_err(wm8994->dev, "Unknown device type %d\n", wm8994->type);
ret = -EINVAL;
goto err_enable;
}
ret = regmap_reinit_cache(wm8994->regmap, regmap_config);
if (ret != 0) {
dev_err(wm8994->dev, "Failed to reinit register cache: %d\n",
ret);
goto err_enable;
}
/* Explicitly put the device into reset in case regulators
* don't get disabled in order to ensure we know the device
* state.
*/
ret = wm8994_reg_write(wm8994, WM8994_SOFTWARE_RESET,
wm8994_reg_read(wm8994, WM8994_SOFTWARE_RESET));
if (ret != 0) {
dev_err(wm8994->dev, "Failed to reset device: %d\n", ret);
goto err_enable;
}
if (regmap_patch) {
ret = regmap_register_patch(wm8994->regmap, regmap_patch,
patch_regs);
if (ret != 0) {
dev_err(wm8994->dev, "Failed to register patch: %d\n",
ret);
goto err_enable;
}
}
wm8994->irq_base = pdata->irq_base;
wm8994->gpio_base = pdata->gpio_base;
/* GPIO configuration is only applied if it's non-zero */
for (i = 0; i < ARRAY_SIZE(pdata->gpio_defaults); i++) {
if (pdata->gpio_defaults[i]) {
wm8994_set_bits(wm8994, WM8994_GPIO_1 + i,
0xffff, pdata->gpio_defaults[i]);
}
}
wm8994->ldo_ena_always_driven = pdata->ldo_ena_always_driven;
if (pdata->spkmode_pu)
pulls |= WM8994_SPKMODE_PU;
if (pdata->csnaddr_pd)
pulls |= WM8994_CSNADDR_PD;
/* Disable unneeded pulls */
wm8994_set_bits(wm8994, WM8994_PULL_CONTROL_2,
WM8994_LDO1ENA_PD | WM8994_LDO2ENA_PD |
WM8994_SPKMODE_PU | WM8994_CSNADDR_PD,
pulls);
/* In some system designs where the regulators are not in use,
* we can achieve a small reduction in leakage currents by
* floating LDO outputs. This bit makes no difference if the
* LDOs are enabled, it only affects cases where the LDOs were
* in operation and are then disabled.
*/
for (i = 0; i < WM8994_NUM_LDO_REGS; i++) {
if (wm8994_ldo_in_use(pdata, i))
wm8994_set_bits(wm8994, WM8994_LDO_1 + i,
WM8994_LDO1_DISCH, WM8994_LDO1_DISCH);
else
wm8994_set_bits(wm8994, WM8994_LDO_1 + i,
WM8994_LDO1_DISCH, 0);
}
wm8994_irq_init(wm8994);
ret = mfd_add_devices(wm8994->dev, -1,
wm8994_devs, ARRAY_SIZE(wm8994_devs),
NULL, 0, NULL);
if (ret != 0) {
dev_err(wm8994->dev, "Failed to add children: %d\n", ret);
goto err_irq;
}
pm_runtime_set_active(wm8994->dev);
pm_runtime_enable(wm8994->dev);
pm_runtime_idle(wm8994->dev);
return 0;
err_irq:
wm8994_irq_exit(wm8994);
err_enable:
regulator_bulk_disable(wm8994->num_supplies,
wm8994->supplies);
err_regulator_free:
regulator_bulk_free(wm8994->num_supplies, wm8994->supplies);
err:
mfd_remove_devices(wm8994->dev);
return ret;
}
static void wm8994_device_exit(struct wm8994 *wm8994)
{
pm_runtime_get_sync(wm8994->dev);
pm_runtime_disable(wm8994->dev);
pm_runtime_put_noidle(wm8994->dev);
wm8994_irq_exit(wm8994);
regulator_bulk_disable(wm8994->num_supplies, wm8994->supplies);
regulator_bulk_free(wm8994->num_supplies, wm8994->supplies);
mfd_remove_devices(wm8994->dev);
}
static const struct of_device_id wm8994_of_match[] = {
{ .compatible = "wlf,wm1811", .data = (void *)WM1811 },
{ .compatible = "wlf,wm8994", .data = (void *)WM8994 },
{ .compatible = "wlf,wm8958", .data = (void *)WM8958 },
{ }
};
MODULE_DEVICE_TABLE(of, wm8994_of_match);
static int wm8994_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
const struct of_device_id *of_id;
struct wm8994 *wm8994;
int ret;
wm8994 = devm_kzalloc(&i2c->dev, sizeof(struct wm8994), GFP_KERNEL);
if (wm8994 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, wm8994);
wm8994->dev = &i2c->dev;
wm8994->irq = i2c->irq;
if (i2c->dev.of_node) {
of_id = of_match_device(wm8994_of_match, &i2c->dev);
if (of_id)
wm8994->type = (uintptr_t)of_id->data;
} else {
wm8994->type = id->driver_data;
}
wm8994->regmap = devm_regmap_init_i2c(i2c, &wm8994_base_regmap_config);
if (IS_ERR(wm8994->regmap)) {
ret = PTR_ERR(wm8994->regmap);
dev_err(wm8994->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
return wm8994_device_init(wm8994, i2c->irq);
}
static void wm8994_i2c_remove(struct i2c_client *i2c)
{
struct wm8994 *wm8994 = i2c_get_clientdata(i2c);
wm8994_device_exit(wm8994);
}
static const struct i2c_device_id wm8994_i2c_id[] = {
{ "wm1811", WM1811 },
{ "wm1811a", WM1811 },
{ "wm8994", WM8994 },
{ "wm8958", WM8958 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
static const struct dev_pm_ops wm8994_pm_ops = {
RUNTIME_PM_OPS(wm8994_suspend, wm8994_resume, NULL)
};
static struct i2c_driver wm8994_i2c_driver = {
.driver = {
.name = "wm8994",
.pm = pm_ptr(&wm8994_pm_ops),
.of_match_table = wm8994_of_match,
},
.probe = wm8994_i2c_probe,
.remove = wm8994_i2c_remove,
.id_table = wm8994_i2c_id,
};
module_i2c_driver(wm8994_i2c_driver);
MODULE_DESCRIPTION("Core support for the WM8994 audio CODEC");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_SOFTDEP("pre: wm8994_regulator");
| linux-master | drivers/mfd/wm8994-core.c |
// SPDX-License-Identifier: GPL-2.0+
//
// max8997.c - mfd core driver for the Maxim 8966 and 8997
//
// Copyright (C) 2011 Samsung Electronics
// MyungJoo Ham <[email protected]>
//
// This driver is based on max8998.c
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max8997.h>
#include <linux/mfd/max8997-private.h>
#define I2C_ADDR_PMIC (0xCC >> 1)
#define I2C_ADDR_MUIC (0x4A >> 1)
#define I2C_ADDR_BATTERY (0x6C >> 1)
#define I2C_ADDR_RTC (0x0C >> 1)
#define I2C_ADDR_HAPTIC (0x90 >> 1)
static const struct mfd_cell max8997_devs[] = {
{ .name = "max8997-pmic", },
{ .name = "max8997-rtc", },
{ .name = "max8997-battery", },
{ .name = "max8997-haptic", },
{ .name = "max8997-muic", },
{ .name = "max8997-led", .id = 1 },
{ .name = "max8997-led", .id = 2 },
};
#ifdef CONFIG_OF
static const struct of_device_id max8997_pmic_dt_match[] = {
{ .compatible = "maxim,max8997-pmic", .data = (void *)TYPE_MAX8997 },
{},
};
#endif
int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest)
{
struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8997->iolock);
ret = i2c_smbus_read_byte_data(i2c, reg);
mutex_unlock(&max8997->iolock);
if (ret < 0)
return ret;
ret &= 0xff;
*dest = ret;
return 0;
}
EXPORT_SYMBOL_GPL(max8997_read_reg);
int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf)
{
struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8997->iolock);
ret = i2c_smbus_read_i2c_block_data(i2c, reg, count, buf);
mutex_unlock(&max8997->iolock);
if (ret < 0)
return ret;
return 0;
}
EXPORT_SYMBOL_GPL(max8997_bulk_read);
int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value)
{
struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8997->iolock);
ret = i2c_smbus_write_byte_data(i2c, reg, value);
mutex_unlock(&max8997->iolock);
return ret;
}
EXPORT_SYMBOL_GPL(max8997_write_reg);
int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf)
{
struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8997->iolock);
ret = i2c_smbus_write_i2c_block_data(i2c, reg, count, buf);
mutex_unlock(&max8997->iolock);
if (ret < 0)
return ret;
return 0;
}
EXPORT_SYMBOL_GPL(max8997_bulk_write);
int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask)
{
struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8997->iolock);
ret = i2c_smbus_read_byte_data(i2c, reg);
if (ret >= 0) {
u8 old_val = ret & 0xff;
u8 new_val = (val & mask) | (old_val & (~mask));
ret = i2c_smbus_write_byte_data(i2c, reg, new_val);
}
mutex_unlock(&max8997->iolock);
return ret;
}
EXPORT_SYMBOL_GPL(max8997_update_reg);
/*
* Only the common platform data elements for max8997 are parsed here from the
* device tree. Other sub-modules of max8997 such as pmic, rtc and others have
* to parse their own platform data elements from device tree.
*
* The max8997 platform data structure is instantiated here and the drivers for
* the sub-modules need not instantiate another instance while parsing their
* platform data.
*/
static struct max8997_platform_data *max8997_i2c_parse_dt_pdata(
struct device *dev)
{
struct max8997_platform_data *pd;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return ERR_PTR(-ENOMEM);
pd->ono = irq_of_parse_and_map(dev->of_node, 1);
return pd;
}
static inline unsigned long max8997_i2c_get_driver_data(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
if (i2c->dev.of_node)
return (unsigned long)of_device_get_match_data(&i2c->dev);
return id->driver_data;
}
static int max8997_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct max8997_dev *max8997;
struct max8997_platform_data *pdata = dev_get_platdata(&i2c->dev);
int ret = 0;
max8997 = devm_kzalloc(&i2c->dev, sizeof(struct max8997_dev),
GFP_KERNEL);
if (max8997 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, max8997);
max8997->dev = &i2c->dev;
max8997->i2c = i2c;
max8997->type = max8997_i2c_get_driver_data(i2c, id);
max8997->irq = i2c->irq;
if (IS_ENABLED(CONFIG_OF) && max8997->dev->of_node) {
pdata = max8997_i2c_parse_dt_pdata(max8997->dev);
if (IS_ERR(pdata))
return PTR_ERR(pdata);
}
if (!pdata)
return ret;
max8997->pdata = pdata;
max8997->ono = pdata->ono;
mutex_init(&max8997->iolock);
max8997->rtc = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_RTC);
if (IS_ERR(max8997->rtc)) {
dev_err(max8997->dev, "Failed to allocate I2C device for RTC\n");
return PTR_ERR(max8997->rtc);
}
i2c_set_clientdata(max8997->rtc, max8997);
max8997->haptic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_HAPTIC);
if (IS_ERR(max8997->haptic)) {
dev_err(max8997->dev, "Failed to allocate I2C device for Haptic\n");
ret = PTR_ERR(max8997->haptic);
goto err_i2c_haptic;
}
i2c_set_clientdata(max8997->haptic, max8997);
max8997->muic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_MUIC);
if (IS_ERR(max8997->muic)) {
dev_err(max8997->dev, "Failed to allocate I2C device for MUIC\n");
ret = PTR_ERR(max8997->muic);
goto err_i2c_muic;
}
i2c_set_clientdata(max8997->muic, max8997);
pm_runtime_set_active(max8997->dev);
max8997_irq_init(max8997);
ret = mfd_add_devices(max8997->dev, -1, max8997_devs,
ARRAY_SIZE(max8997_devs),
NULL, 0, NULL);
if (ret < 0) {
dev_err(max8997->dev, "failed to add MFD devices %d\n", ret);
goto err_mfd;
}
/*
* TODO: enable others (flash, muic, rtc, battery, ...) and
* check the return value
*/
/* MAX8997 has a power button input. */
device_init_wakeup(max8997->dev, true);
return ret;
err_mfd:
mfd_remove_devices(max8997->dev);
i2c_unregister_device(max8997->muic);
err_i2c_muic:
i2c_unregister_device(max8997->haptic);
err_i2c_haptic:
i2c_unregister_device(max8997->rtc);
return ret;
}
static const struct i2c_device_id max8997_i2c_id[] = {
{ "max8997", TYPE_MAX8997 },
{ "max8966", TYPE_MAX8966 },
{ }
};
static u8 max8997_dumpaddr_pmic[] = {
MAX8997_REG_INT1MSK,
MAX8997_REG_INT2MSK,
MAX8997_REG_INT3MSK,
MAX8997_REG_INT4MSK,
MAX8997_REG_MAINCON1,
MAX8997_REG_MAINCON2,
MAX8997_REG_BUCKRAMP,
MAX8997_REG_BUCK1CTRL,
MAX8997_REG_BUCK1DVS1,
MAX8997_REG_BUCK1DVS2,
MAX8997_REG_BUCK1DVS3,
MAX8997_REG_BUCK1DVS4,
MAX8997_REG_BUCK1DVS5,
MAX8997_REG_BUCK1DVS6,
MAX8997_REG_BUCK1DVS7,
MAX8997_REG_BUCK1DVS8,
MAX8997_REG_BUCK2CTRL,
MAX8997_REG_BUCK2DVS1,
MAX8997_REG_BUCK2DVS2,
MAX8997_REG_BUCK2DVS3,
MAX8997_REG_BUCK2DVS4,
MAX8997_REG_BUCK2DVS5,
MAX8997_REG_BUCK2DVS6,
MAX8997_REG_BUCK2DVS7,
MAX8997_REG_BUCK2DVS8,
MAX8997_REG_BUCK3CTRL,
MAX8997_REG_BUCK3DVS,
MAX8997_REG_BUCK4CTRL,
MAX8997_REG_BUCK4DVS,
MAX8997_REG_BUCK5CTRL,
MAX8997_REG_BUCK5DVS1,
MAX8997_REG_BUCK5DVS2,
MAX8997_REG_BUCK5DVS3,
MAX8997_REG_BUCK5DVS4,
MAX8997_REG_BUCK5DVS5,
MAX8997_REG_BUCK5DVS6,
MAX8997_REG_BUCK5DVS7,
MAX8997_REG_BUCK5DVS8,
MAX8997_REG_BUCK6CTRL,
MAX8997_REG_BUCK6BPSKIPCTRL,
MAX8997_REG_BUCK7CTRL,
MAX8997_REG_BUCK7DVS,
MAX8997_REG_LDO1CTRL,
MAX8997_REG_LDO2CTRL,
MAX8997_REG_LDO3CTRL,
MAX8997_REG_LDO4CTRL,
MAX8997_REG_LDO5CTRL,
MAX8997_REG_LDO6CTRL,
MAX8997_REG_LDO7CTRL,
MAX8997_REG_LDO8CTRL,
MAX8997_REG_LDO9CTRL,
MAX8997_REG_LDO10CTRL,
MAX8997_REG_LDO11CTRL,
MAX8997_REG_LDO12CTRL,
MAX8997_REG_LDO13CTRL,
MAX8997_REG_LDO14CTRL,
MAX8997_REG_LDO15CTRL,
MAX8997_REG_LDO16CTRL,
MAX8997_REG_LDO17CTRL,
MAX8997_REG_LDO18CTRL,
MAX8997_REG_LDO21CTRL,
MAX8997_REG_MBCCTRL1,
MAX8997_REG_MBCCTRL2,
MAX8997_REG_MBCCTRL3,
MAX8997_REG_MBCCTRL4,
MAX8997_REG_MBCCTRL5,
MAX8997_REG_MBCCTRL6,
MAX8997_REG_OTPCGHCVS,
MAX8997_REG_SAFEOUTCTRL,
MAX8997_REG_LBCNFG1,
MAX8997_REG_LBCNFG2,
MAX8997_REG_BBCCTRL,
MAX8997_REG_FLASH1_CUR,
MAX8997_REG_FLASH2_CUR,
MAX8997_REG_MOVIE_CUR,
MAX8997_REG_GSMB_CUR,
MAX8997_REG_BOOST_CNTL,
MAX8997_REG_LEN_CNTL,
MAX8997_REG_FLASH_CNTL,
MAX8997_REG_WDT_CNTL,
MAX8997_REG_MAXFLASH1,
MAX8997_REG_MAXFLASH2,
MAX8997_REG_FLASHSTATUSMASK,
MAX8997_REG_GPIOCNTL1,
MAX8997_REG_GPIOCNTL2,
MAX8997_REG_GPIOCNTL3,
MAX8997_REG_GPIOCNTL4,
MAX8997_REG_GPIOCNTL5,
MAX8997_REG_GPIOCNTL6,
MAX8997_REG_GPIOCNTL7,
MAX8997_REG_GPIOCNTL8,
MAX8997_REG_GPIOCNTL9,
MAX8997_REG_GPIOCNTL10,
MAX8997_REG_GPIOCNTL11,
MAX8997_REG_GPIOCNTL12,
MAX8997_REG_LDO1CONFIG,
MAX8997_REG_LDO2CONFIG,
MAX8997_REG_LDO3CONFIG,
MAX8997_REG_LDO4CONFIG,
MAX8997_REG_LDO5CONFIG,
MAX8997_REG_LDO6CONFIG,
MAX8997_REG_LDO7CONFIG,
MAX8997_REG_LDO8CONFIG,
MAX8997_REG_LDO9CONFIG,
MAX8997_REG_LDO10CONFIG,
MAX8997_REG_LDO11CONFIG,
MAX8997_REG_LDO12CONFIG,
MAX8997_REG_LDO13CONFIG,
MAX8997_REG_LDO14CONFIG,
MAX8997_REG_LDO15CONFIG,
MAX8997_REG_LDO16CONFIG,
MAX8997_REG_LDO17CONFIG,
MAX8997_REG_LDO18CONFIG,
MAX8997_REG_LDO21CONFIG,
MAX8997_REG_DVSOKTIMER1,
MAX8997_REG_DVSOKTIMER2,
MAX8997_REG_DVSOKTIMER4,
MAX8997_REG_DVSOKTIMER5,
};
static u8 max8997_dumpaddr_muic[] = {
MAX8997_MUIC_REG_INTMASK1,
MAX8997_MUIC_REG_INTMASK2,
MAX8997_MUIC_REG_INTMASK3,
MAX8997_MUIC_REG_CDETCTRL,
MAX8997_MUIC_REG_CONTROL1,
MAX8997_MUIC_REG_CONTROL2,
MAX8997_MUIC_REG_CONTROL3,
};
static u8 max8997_dumpaddr_haptic[] = {
MAX8997_HAPTIC_REG_CONF1,
MAX8997_HAPTIC_REG_CONF2,
MAX8997_HAPTIC_REG_DRVCONF,
MAX8997_HAPTIC_REG_CYCLECONF1,
MAX8997_HAPTIC_REG_CYCLECONF2,
MAX8997_HAPTIC_REG_SIGCONF1,
MAX8997_HAPTIC_REG_SIGCONF2,
MAX8997_HAPTIC_REG_SIGCONF3,
MAX8997_HAPTIC_REG_SIGCONF4,
MAX8997_HAPTIC_REG_SIGDC1,
MAX8997_HAPTIC_REG_SIGDC2,
MAX8997_HAPTIC_REG_SIGPWMDC1,
MAX8997_HAPTIC_REG_SIGPWMDC2,
MAX8997_HAPTIC_REG_SIGPWMDC3,
MAX8997_HAPTIC_REG_SIGPWMDC4,
};
static int max8997_freeze(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
int i;
for (i = 0; i < ARRAY_SIZE(max8997_dumpaddr_pmic); i++)
max8997_read_reg(i2c, max8997_dumpaddr_pmic[i],
&max8997->reg_dump[i]);
for (i = 0; i < ARRAY_SIZE(max8997_dumpaddr_muic); i++)
max8997_read_reg(i2c, max8997_dumpaddr_muic[i],
&max8997->reg_dump[i + MAX8997_REG_PMIC_END]);
for (i = 0; i < ARRAY_SIZE(max8997_dumpaddr_haptic); i++)
max8997_read_reg(i2c, max8997_dumpaddr_haptic[i],
&max8997->reg_dump[i + MAX8997_REG_PMIC_END +
MAX8997_MUIC_REG_END]);
return 0;
}
static int max8997_restore(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
int i;
for (i = 0; i < ARRAY_SIZE(max8997_dumpaddr_pmic); i++)
max8997_write_reg(i2c, max8997_dumpaddr_pmic[i],
max8997->reg_dump[i]);
for (i = 0; i < ARRAY_SIZE(max8997_dumpaddr_muic); i++)
max8997_write_reg(i2c, max8997_dumpaddr_muic[i],
max8997->reg_dump[i + MAX8997_REG_PMIC_END]);
for (i = 0; i < ARRAY_SIZE(max8997_dumpaddr_haptic); i++)
max8997_write_reg(i2c, max8997_dumpaddr_haptic[i],
max8997->reg_dump[i + MAX8997_REG_PMIC_END +
MAX8997_MUIC_REG_END]);
return 0;
}
static int max8997_suspend(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
disable_irq(max8997->irq);
if (device_may_wakeup(dev))
irq_set_irq_wake(max8997->irq, 1);
return 0;
}
static int max8997_resume(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
irq_set_irq_wake(max8997->irq, 0);
enable_irq(max8997->irq);
return max8997_irq_resume(max8997);
}
static const struct dev_pm_ops max8997_pm = {
.suspend = max8997_suspend,
.resume = max8997_resume,
.freeze = max8997_freeze,
.restore = max8997_restore,
};
static struct i2c_driver max8997_i2c_driver = {
.driver = {
.name = "max8997",
.pm = &max8997_pm,
.suppress_bind_attrs = true,
.of_match_table = of_match_ptr(max8997_pmic_dt_match),
},
.probe = max8997_i2c_probe,
.id_table = max8997_i2c_id,
};
static int __init max8997_i2c_init(void)
{
return i2c_add_driver(&max8997_i2c_driver);
}
/* init early so consumer devices can complete system boot */
subsys_initcall(max8997_i2c_init);
| linux-master | drivers/mfd/max8997.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/mfd/mfd-core.c
*
* core MFD support
* Copyright (c) 2006 Ian Molton
* Copyright (c) 2007,2008 Dmitry Baryshkov
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/acpi.h>
#include <linux/list.h>
#include <linux/property.h>
#include <linux/mfd/core.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regulator/consumer.h>
static LIST_HEAD(mfd_of_node_list);
struct mfd_of_node_entry {
struct list_head list;
struct device *dev;
struct device_node *np;
};
static struct device_type mfd_dev_type = {
.name = "mfd_device",
};
#if IS_ENABLED(CONFIG_ACPI)
struct match_ids_walk_data {
struct acpi_device_id *ids;
struct acpi_device *adev;
};
static int match_device_ids(struct acpi_device *adev, void *data)
{
struct match_ids_walk_data *wd = data;
if (!acpi_match_device_ids(adev, wd->ids)) {
wd->adev = adev;
return 1;
}
return 0;
}
static void mfd_acpi_add_device(const struct mfd_cell *cell,
struct platform_device *pdev)
{
const struct mfd_cell_acpi_match *match = cell->acpi_match;
struct acpi_device *adev = NULL;
struct acpi_device *parent;
parent = ACPI_COMPANION(pdev->dev.parent);
if (!parent)
return;
/*
* MFD child device gets its ACPI handle either from the ACPI device
* directly under the parent that matches the either _HID or _CID, or
* _ADR or it will use the parent handle if is no ID is given.
*
* Note that use of _ADR is a grey area in the ACPI specification,
* though at least Intel Galileo Gen 2 is using it to distinguish
* the children devices.
*/
if (match) {
if (match->pnpid) {
struct acpi_device_id ids[2] = {};
struct match_ids_walk_data wd = {
.adev = NULL,
.ids = ids,
};
strscpy(ids[0].id, match->pnpid, sizeof(ids[0].id));
acpi_dev_for_each_child(parent, match_device_ids, &wd);
adev = wd.adev;
} else {
adev = acpi_find_child_device(parent, match->adr, false);
}
}
ACPI_COMPANION_SET(&pdev->dev, adev ?: parent);
}
#else
static inline void mfd_acpi_add_device(const struct mfd_cell *cell,
struct platform_device *pdev)
{
}
#endif
static int mfd_match_of_node_to_dev(struct platform_device *pdev,
struct device_node *np,
const struct mfd_cell *cell)
{
#if IS_ENABLED(CONFIG_OF)
struct mfd_of_node_entry *of_entry;
u64 of_node_addr;
/* Skip if OF node has previously been allocated to a device */
list_for_each_entry(of_entry, &mfd_of_node_list, list)
if (of_entry->np == np)
return -EAGAIN;
if (!cell->use_of_reg)
/* No of_reg defined - allocate first free compatible match */
goto allocate_of_node;
/* We only care about each node's first defined address */
if (of_property_read_reg(np, 0, &of_node_addr, NULL))
/* OF node does not contatin a 'reg' property to match to */
return -EAGAIN;
if (cell->of_reg != of_node_addr)
/* No match */
return -EAGAIN;
allocate_of_node:
of_entry = kzalloc(sizeof(*of_entry), GFP_KERNEL);
if (!of_entry)
return -ENOMEM;
of_entry->dev = &pdev->dev;
of_entry->np = np;
list_add_tail(&of_entry->list, &mfd_of_node_list);
pdev->dev.of_node = np;
pdev->dev.fwnode = &np->fwnode;
#endif
return 0;
}
static int mfd_add_device(struct device *parent, int id,
const struct mfd_cell *cell,
struct resource *mem_base,
int irq_base, struct irq_domain *domain)
{
struct resource *res;
struct platform_device *pdev;
struct device_node *np = NULL;
struct mfd_of_node_entry *of_entry, *tmp;
int ret = -ENOMEM;
int platform_id;
int r;
if (id == PLATFORM_DEVID_AUTO)
platform_id = id;
else
platform_id = id + cell->id;
pdev = platform_device_alloc(cell->name, platform_id);
if (!pdev)
goto fail_alloc;
pdev->mfd_cell = kmemdup(cell, sizeof(*cell), GFP_KERNEL);
if (!pdev->mfd_cell)
goto fail_device;
res = kcalloc(cell->num_resources, sizeof(*res), GFP_KERNEL);
if (!res)
goto fail_device;
pdev->dev.parent = parent;
pdev->dev.type = &mfd_dev_type;
pdev->dev.dma_mask = parent->dma_mask;
pdev->dev.dma_parms = parent->dma_parms;
pdev->dev.coherent_dma_mask = parent->coherent_dma_mask;
ret = regulator_bulk_register_supply_alias(
&pdev->dev, cell->parent_supplies,
parent, cell->parent_supplies,
cell->num_parent_supplies);
if (ret < 0)
goto fail_res;
if (IS_ENABLED(CONFIG_OF) && parent->of_node && cell->of_compatible) {
for_each_child_of_node(parent->of_node, np) {
if (of_device_is_compatible(np, cell->of_compatible)) {
/* Ignore 'disabled' devices error free */
if (!of_device_is_available(np)) {
of_node_put(np);
ret = 0;
goto fail_alias;
}
ret = mfd_match_of_node_to_dev(pdev, np, cell);
if (ret == -EAGAIN)
continue;
of_node_put(np);
if (ret)
goto fail_alias;
break;
}
}
if (!pdev->dev.of_node)
pr_warn("%s: Failed to locate of_node [id: %d]\n",
cell->name, platform_id);
}
mfd_acpi_add_device(cell, pdev);
if (cell->pdata_size) {
ret = platform_device_add_data(pdev,
cell->platform_data, cell->pdata_size);
if (ret)
goto fail_of_entry;
}
if (cell->swnode) {
ret = device_add_software_node(&pdev->dev, cell->swnode);
if (ret)
goto fail_of_entry;
}
for (r = 0; r < cell->num_resources; r++) {
res[r].name = cell->resources[r].name;
res[r].flags = cell->resources[r].flags;
/* Find out base to use */
if ((cell->resources[r].flags & IORESOURCE_MEM) && mem_base) {
res[r].parent = mem_base;
res[r].start = mem_base->start +
cell->resources[r].start;
res[r].end = mem_base->start +
cell->resources[r].end;
} else if (cell->resources[r].flags & IORESOURCE_IRQ) {
if (domain) {
/* Unable to create mappings for IRQ ranges. */
WARN_ON(cell->resources[r].start !=
cell->resources[r].end);
res[r].start = res[r].end = irq_create_mapping(
domain, cell->resources[r].start);
} else {
res[r].start = irq_base +
cell->resources[r].start;
res[r].end = irq_base +
cell->resources[r].end;
}
} else {
res[r].parent = cell->resources[r].parent;
res[r].start = cell->resources[r].start;
res[r].end = cell->resources[r].end;
}
if (!cell->ignore_resource_conflicts) {
if (has_acpi_companion(&pdev->dev)) {
ret = acpi_check_resource_conflict(&res[r]);
if (ret)
goto fail_res_conflict;
}
}
}
ret = platform_device_add_resources(pdev, res, cell->num_resources);
if (ret)
goto fail_res_conflict;
ret = platform_device_add(pdev);
if (ret)
goto fail_res_conflict;
if (cell->pm_runtime_no_callbacks)
pm_runtime_no_callbacks(&pdev->dev);
kfree(res);
return 0;
fail_res_conflict:
if (cell->swnode)
device_remove_software_node(&pdev->dev);
fail_of_entry:
list_for_each_entry_safe(of_entry, tmp, &mfd_of_node_list, list)
if (of_entry->dev == &pdev->dev) {
list_del(&of_entry->list);
kfree(of_entry);
}
fail_alias:
regulator_bulk_unregister_supply_alias(&pdev->dev,
cell->parent_supplies,
cell->num_parent_supplies);
fail_res:
kfree(res);
fail_device:
platform_device_put(pdev);
fail_alloc:
return ret;
}
/**
* mfd_add_devices - register child devices
*
* @parent: Pointer to parent device.
* @id: Can be PLATFORM_DEVID_AUTO to let the Platform API take care
* of device numbering, or will be added to a device's cell_id.
* @cells: Array of (struct mfd_cell)s describing child devices.
* @n_devs: Number of child devices to register.
* @mem_base: Parent register range resource for child devices.
* @irq_base: Base of the range of virtual interrupt numbers allocated for
* this MFD device. Unused if @domain is specified.
* @domain: Interrupt domain to create mappings for hardware interrupts.
*/
int mfd_add_devices(struct device *parent, int id,
const struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base, struct irq_domain *domain)
{
int i;
int ret;
for (i = 0; i < n_devs; i++) {
ret = mfd_add_device(parent, id, cells + i, mem_base,
irq_base, domain);
if (ret)
goto fail;
}
return 0;
fail:
if (i)
mfd_remove_devices(parent);
return ret;
}
EXPORT_SYMBOL(mfd_add_devices);
static int mfd_remove_devices_fn(struct device *dev, void *data)
{
struct platform_device *pdev;
const struct mfd_cell *cell;
struct mfd_of_node_entry *of_entry, *tmp;
int *level = data;
if (dev->type != &mfd_dev_type)
return 0;
pdev = to_platform_device(dev);
cell = mfd_get_cell(pdev);
if (level && cell->level > *level)
return 0;
if (cell->swnode)
device_remove_software_node(&pdev->dev);
list_for_each_entry_safe(of_entry, tmp, &mfd_of_node_list, list)
if (of_entry->dev == &pdev->dev) {
list_del(&of_entry->list);
kfree(of_entry);
}
regulator_bulk_unregister_supply_alias(dev, cell->parent_supplies,
cell->num_parent_supplies);
platform_device_unregister(pdev);
return 0;
}
void mfd_remove_devices_late(struct device *parent)
{
int level = MFD_DEP_LEVEL_HIGH;
device_for_each_child_reverse(parent, &level, mfd_remove_devices_fn);
}
EXPORT_SYMBOL(mfd_remove_devices_late);
void mfd_remove_devices(struct device *parent)
{
int level = MFD_DEP_LEVEL_NORMAL;
device_for_each_child_reverse(parent, &level, mfd_remove_devices_fn);
}
EXPORT_SYMBOL(mfd_remove_devices);
static void devm_mfd_dev_release(struct device *dev, void *res)
{
mfd_remove_devices(dev);
}
/**
* devm_mfd_add_devices - Resource managed version of mfd_add_devices()
*
* Returns 0 on success or an appropriate negative error number on failure.
* All child-devices of the MFD will automatically be removed when it gets
* unbinded.
*
* @dev: Pointer to parent device.
* @id: Can be PLATFORM_DEVID_AUTO to let the Platform API take care
* of device numbering, or will be added to a device's cell_id.
* @cells: Array of (struct mfd_cell)s describing child devices.
* @n_devs: Number of child devices to register.
* @mem_base: Parent register range resource for child devices.
* @irq_base: Base of the range of virtual interrupt numbers allocated for
* this MFD device. Unused if @domain is specified.
* @domain: Interrupt domain to create mappings for hardware interrupts.
*/
int devm_mfd_add_devices(struct device *dev, int id,
const struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base, struct irq_domain *domain)
{
struct device **ptr;
int ret;
ptr = devres_alloc(devm_mfd_dev_release, sizeof(*ptr), GFP_KERNEL);
if (!ptr)
return -ENOMEM;
ret = mfd_add_devices(dev, id, cells, n_devs, mem_base,
irq_base, domain);
if (ret < 0) {
devres_free(ptr);
return ret;
}
*ptr = dev;
devres_add(dev, ptr);
return ret;
}
EXPORT_SYMBOL(devm_mfd_add_devices);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov");
| linux-master | drivers/mfd/mfd-core.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Device access for Dialog DA9063 modules
*
* Copyright 2012 Dialog Semiconductors Ltd.
* Copyright 2013 Philipp Zabel, Pengutronix
*
* Author: Krystian Garbaciak, Dialog Semiconductor
* Author: Michal Hajduk, Dialog Semiconductor
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/regmap.h>
#include <linux/mfd/da9063/core.h>
#include <linux/mfd/da9063/registers.h>
#include <linux/proc_fs.h>
#include <linux/kthread.h>
#include <linux/uaccess.h>
static const struct resource da9063_regulators_resources[] = {
{
.name = "LDO_LIM",
.start = DA9063_IRQ_LDO_LIM,
.end = DA9063_IRQ_LDO_LIM,
.flags = IORESOURCE_IRQ,
},
};
static const struct resource da9063_rtc_resources[] = {
{
.name = "ALARM",
.start = DA9063_IRQ_ALARM,
.end = DA9063_IRQ_ALARM,
.flags = IORESOURCE_IRQ,
},
{
.name = "TICK",
.start = DA9063_IRQ_TICK,
.end = DA9063_IRQ_TICK,
.flags = IORESOURCE_IRQ,
}
};
static const struct resource da9063_onkey_resources[] = {
{
.name = "ONKEY",
.start = DA9063_IRQ_ONKEY,
.end = DA9063_IRQ_ONKEY,
.flags = IORESOURCE_IRQ,
},
};
static const struct resource da9063_hwmon_resources[] = {
{
.start = DA9063_IRQ_ADC_RDY,
.end = DA9063_IRQ_ADC_RDY,
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell da9063_common_devs[] = {
{
.name = DA9063_DRVNAME_REGULATORS,
.num_resources = ARRAY_SIZE(da9063_regulators_resources),
.resources = da9063_regulators_resources,
},
{
.name = DA9063_DRVNAME_LEDS,
},
{
.name = DA9063_DRVNAME_WATCHDOG,
.of_compatible = "dlg,da9063-watchdog",
},
{
.name = DA9063_DRVNAME_HWMON,
.num_resources = ARRAY_SIZE(da9063_hwmon_resources),
.resources = da9063_hwmon_resources,
},
{
.name = DA9063_DRVNAME_ONKEY,
.num_resources = ARRAY_SIZE(da9063_onkey_resources),
.resources = da9063_onkey_resources,
.of_compatible = "dlg,da9063-onkey",
},
{
.name = DA9063_DRVNAME_VIBRATION,
},
};
/* Only present on DA9063 , not on DA9063L */
static const struct mfd_cell da9063_devs[] = {
{
.name = DA9063_DRVNAME_RTC,
.num_resources = ARRAY_SIZE(da9063_rtc_resources),
.resources = da9063_rtc_resources,
.of_compatible = "dlg,da9063-rtc",
},
};
static int da9063_clear_fault_log(struct da9063 *da9063)
{
int ret = 0;
int fault_log = 0;
ret = regmap_read(da9063->regmap, DA9063_REG_FAULT_LOG, &fault_log);
if (ret < 0) {
dev_err(da9063->dev, "Cannot read FAULT_LOG.\n");
return -EIO;
}
if (fault_log) {
if (fault_log & DA9063_TWD_ERROR)
dev_dbg(da9063->dev,
"Fault log entry detected: DA9063_TWD_ERROR\n");
if (fault_log & DA9063_POR)
dev_dbg(da9063->dev,
"Fault log entry detected: DA9063_POR\n");
if (fault_log & DA9063_VDD_FAULT)
dev_dbg(da9063->dev,
"Fault log entry detected: DA9063_VDD_FAULT\n");
if (fault_log & DA9063_VDD_START)
dev_dbg(da9063->dev,
"Fault log entry detected: DA9063_VDD_START\n");
if (fault_log & DA9063_TEMP_CRIT)
dev_dbg(da9063->dev,
"Fault log entry detected: DA9063_TEMP_CRIT\n");
if (fault_log & DA9063_KEY_RESET)
dev_dbg(da9063->dev,
"Fault log entry detected: DA9063_KEY_RESET\n");
if (fault_log & DA9063_NSHUTDOWN)
dev_dbg(da9063->dev,
"Fault log entry detected: DA9063_NSHUTDOWN\n");
if (fault_log & DA9063_WAIT_SHUT)
dev_dbg(da9063->dev,
"Fault log entry detected: DA9063_WAIT_SHUT\n");
}
ret = regmap_write(da9063->regmap,
DA9063_REG_FAULT_LOG,
fault_log);
if (ret < 0)
dev_err(da9063->dev,
"Cannot reset FAULT_LOG values %d\n", ret);
return ret;
}
int da9063_device_init(struct da9063 *da9063, unsigned int irq)
{
int ret;
ret = da9063_clear_fault_log(da9063);
if (ret < 0)
dev_err(da9063->dev, "Cannot clear fault log\n");
da9063->flags = 0;
da9063->irq_base = -1;
da9063->chip_irq = irq;
ret = da9063_irq_init(da9063);
if (ret) {
dev_err(da9063->dev, "Cannot initialize interrupts.\n");
return ret;
}
da9063->irq_base = regmap_irq_chip_get_base(da9063->regmap_irq);
ret = devm_mfd_add_devices(da9063->dev, PLATFORM_DEVID_NONE,
da9063_common_devs,
ARRAY_SIZE(da9063_common_devs),
NULL, da9063->irq_base, NULL);
if (ret) {
dev_err(da9063->dev, "Failed to add child devices\n");
return ret;
}
if (da9063->type == PMIC_TYPE_DA9063) {
ret = devm_mfd_add_devices(da9063->dev, PLATFORM_DEVID_NONE,
da9063_devs, ARRAY_SIZE(da9063_devs),
NULL, da9063->irq_base, NULL);
if (ret) {
dev_err(da9063->dev, "Failed to add child devices\n");
return ret;
}
}
return ret;
}
MODULE_DESCRIPTION("PMIC driver for Dialog DA9063");
MODULE_AUTHOR("Krystian Garbaciak");
MODULE_AUTHOR("Michal Hajduk");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/da9063-core.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* MP2629 parent driver for ADC and battery charger
*
* Copyright 2020 Monolithic Power Systems, Inc
*
* Author: Saravanan Sekar <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mp2629.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
static const struct mfd_cell mp2629_cell[] = {
{
.name = "mp2629_adc",
.of_compatible = "mps,mp2629_adc",
},
{
.name = "mp2629_charger",
.of_compatible = "mps,mp2629_charger",
}
};
static const struct regmap_config mp2629_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x17,
};
static int mp2629_probe(struct i2c_client *client)
{
struct mp2629_data *ddata;
int ret;
ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
ddata->dev = &client->dev;
i2c_set_clientdata(client, ddata);
ddata->regmap = devm_regmap_init_i2c(client, &mp2629_regmap_config);
if (IS_ERR(ddata->regmap)) {
dev_err(ddata->dev, "Failed to allocate regmap\n");
return PTR_ERR(ddata->regmap);
}
ret = devm_mfd_add_devices(ddata->dev, PLATFORM_DEVID_AUTO, mp2629_cell,
ARRAY_SIZE(mp2629_cell), NULL, 0, NULL);
if (ret)
dev_err(ddata->dev, "Failed to register sub-devices %d\n", ret);
return ret;
}
static const struct of_device_id mp2629_of_match[] = {
{ .compatible = "mps,mp2629"},
{ }
};
MODULE_DEVICE_TABLE(of, mp2629_of_match);
static struct i2c_driver mp2629_driver = {
.driver = {
.name = "mp2629",
.of_match_table = mp2629_of_match,
},
.probe = mp2629_probe,
};
module_i2c_driver(mp2629_driver);
MODULE_AUTHOR("Saravanan Sekar <[email protected]>");
MODULE_DESCRIPTION("MP2629 Battery charger parent driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/mp2629.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MEN 14F021P00 Board Management Controller (BMC) MFD Core Driver.
*
* Copyright (C) 2014 MEN Mikro Elektronik Nuernberg GmbH
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#define BMC_CMD_WDT_EXIT_PROD 0x18
#define BMC_CMD_WDT_PROD_STAT 0x19
#define BMC_CMD_REV_MAJOR 0x80
#define BMC_CMD_REV_MINOR 0x81
#define BMC_CMD_REV_MAIN 0x82
static struct mfd_cell menf21bmc_cell[] = {
{ .name = "menf21bmc_wdt", },
{ .name = "menf21bmc_led", },
{ .name = "menf21bmc_hwmon", }
};
static int menf21bmc_wdt_exit_prod_mode(struct i2c_client *client)
{
int val, ret;
val = i2c_smbus_read_byte_data(client, BMC_CMD_WDT_PROD_STAT);
if (val < 0)
return val;
/*
* Production mode should be not active after delivery of the Board.
* To be sure we check it, inform the user and exit the mode
* if active.
*/
if (val == 0x00) {
dev_info(&client->dev,
"BMC in production mode. Exit production mode\n");
ret = i2c_smbus_write_byte(client, BMC_CMD_WDT_EXIT_PROD);
if (ret < 0)
return ret;
}
return 0;
}
static int
menf21bmc_probe(struct i2c_client *client)
{
int rev_major, rev_minor, rev_main;
int ret;
ret = i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_WORD_DATA |
I2C_FUNC_SMBUS_BYTE);
if (!ret)
return -ENODEV;
rev_major = i2c_smbus_read_word_data(client, BMC_CMD_REV_MAJOR);
if (rev_major < 0) {
dev_err(&client->dev, "failed to get BMC major revision\n");
return rev_major;
}
rev_minor = i2c_smbus_read_word_data(client, BMC_CMD_REV_MINOR);
if (rev_minor < 0) {
dev_err(&client->dev, "failed to get BMC minor revision\n");
return rev_minor;
}
rev_main = i2c_smbus_read_word_data(client, BMC_CMD_REV_MAIN);
if (rev_main < 0) {
dev_err(&client->dev, "failed to get BMC main revision\n");
return rev_main;
}
dev_info(&client->dev, "FW Revision: %02d.%02d.%02d\n",
rev_major, rev_minor, rev_main);
/*
* We have to exit the Production Mode of the BMC to activate the
* Watchdog functionality and the BIOS life sign monitoring.
*/
ret = menf21bmc_wdt_exit_prod_mode(client);
if (ret < 0) {
dev_err(&client->dev, "failed to leave production mode\n");
return ret;
}
ret = devm_mfd_add_devices(&client->dev, 0, menf21bmc_cell,
ARRAY_SIZE(menf21bmc_cell), NULL, 0, NULL);
if (ret < 0) {
dev_err(&client->dev, "failed to add BMC sub-devices\n");
return ret;
}
return 0;
}
static const struct i2c_device_id menf21bmc_id_table[] = {
{ "menf21bmc" },
{ }
};
MODULE_DEVICE_TABLE(i2c, menf21bmc_id_table);
static struct i2c_driver menf21bmc_driver = {
.driver.name = "menf21bmc",
.id_table = menf21bmc_id_table,
.probe = menf21bmc_probe,
};
module_i2c_driver(menf21bmc_driver);
MODULE_DESCRIPTION("MEN 14F021P00 BMC mfd core driver");
MODULE_AUTHOR("Andreas Werner <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/menf21bmc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Touchscreen driver for UCB1x00-based touchscreens
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
* Copyright (C) 2005 Pavel Machek
*
* 21-Jan-2002 <[email protected]> :
*
* Added support for synchronous A/D mode. This mode is useful to
* avoid noise induced in the touchpanel by the LCD, provided that
* the UCB1x00 has a valid LCD sync signal routed to its ADCSYNC pin.
* It is important to note that the signal connected to the ADCSYNC
* pin should provide pulses even when the LCD is blanked, otherwise
* a pen touch needed to unblank the LCD will never be read.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/input.h>
#include <linux/device.h>
#include <linux/freezer.h>
#include <linux/slab.h>
#include <linux/kthread.h>
#include <linux/mfd/ucb1x00.h>
#include <mach/collie.h>
#include <asm/mach-types.h>
struct ucb1x00_ts {
struct input_dev *idev;
struct ucb1x00 *ucb;
spinlock_t irq_lock;
unsigned irq_disabled;
wait_queue_head_t irq_wait;
struct task_struct *rtask;
u16 x_res;
u16 y_res;
unsigned int adcsync:1;
};
static int adcsync;
static inline void ucb1x00_ts_evt_add(struct ucb1x00_ts *ts, u16 pressure, u16 x, u16 y)
{
struct input_dev *idev = ts->idev;
input_report_abs(idev, ABS_X, x);
input_report_abs(idev, ABS_Y, y);
input_report_abs(idev, ABS_PRESSURE, pressure);
input_report_key(idev, BTN_TOUCH, 1);
input_sync(idev);
}
static inline void ucb1x00_ts_event_release(struct ucb1x00_ts *ts)
{
struct input_dev *idev = ts->idev;
input_report_abs(idev, ABS_PRESSURE, 0);
input_report_key(idev, BTN_TOUCH, 0);
input_sync(idev);
}
/*
* Switch to interrupt mode.
*/
static inline void ucb1x00_ts_mode_int(struct ucb1x00_ts *ts)
{
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
UCB_TS_CR_MODE_INT);
}
/*
* Switch to pressure mode, and read pressure. We don't need to wait
* here, since both plates are being driven.
*/
static inline unsigned int ucb1x00_ts_read_pressure(struct ucb1x00_ts *ts)
{
if (machine_is_collie()) {
ucb1x00_io_write(ts->ucb, COLLIE_TC35143_GPIO_TBL_CHK, 0);
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSPX_POW | UCB_TS_CR_TSMX_POW |
UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
udelay(55);
return ucb1x00_adc_read(ts->ucb, UCB_ADC_INP_AD2, ts->adcsync);
} else {
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
return ucb1x00_adc_read(ts->ucb, UCB_ADC_INP_TSPY, ts->adcsync);
}
}
/*
* Switch to X position mode and measure Y plate. We switch the plate
* configuration in pressure mode, then switch to position mode. This
* gives a faster response time. Even so, we need to wait about 55us
* for things to stabilise.
*/
static inline unsigned int ucb1x00_ts_read_xpos(struct ucb1x00_ts *ts)
{
if (machine_is_collie())
ucb1x00_io_write(ts->ucb, 0, COLLIE_TC35143_GPIO_TBL_CHK);
else {
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
}
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
udelay(55);
return ucb1x00_adc_read(ts->ucb, UCB_ADC_INP_TSPY, ts->adcsync);
}
/*
* Switch to Y position mode and measure X plate. We switch the plate
* configuration in pressure mode, then switch to position mode. This
* gives a faster response time. Even so, we need to wait about 55us
* for things to stabilise.
*/
static inline unsigned int ucb1x00_ts_read_ypos(struct ucb1x00_ts *ts)
{
if (machine_is_collie())
ucb1x00_io_write(ts->ucb, 0, COLLIE_TC35143_GPIO_TBL_CHK);
else {
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
}
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
udelay(55);
return ucb1x00_adc_read(ts->ucb, UCB_ADC_INP_TSPX, ts->adcsync);
}
/*
* Switch to X plate resistance mode. Set MX to ground, PX to
* supply. Measure current.
*/
static inline unsigned int ucb1x00_ts_read_xres(struct ucb1x00_ts *ts)
{
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
return ucb1x00_adc_read(ts->ucb, 0, ts->adcsync);
}
/*
* Switch to Y plate resistance mode. Set MY to ground, PY to
* supply. Measure current.
*/
static inline unsigned int ucb1x00_ts_read_yres(struct ucb1x00_ts *ts)
{
ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
return ucb1x00_adc_read(ts->ucb, 0, ts->adcsync);
}
static inline int ucb1x00_ts_pen_down(struct ucb1x00_ts *ts)
{
unsigned int val = ucb1x00_reg_read(ts->ucb, UCB_TS_CR);
if (machine_is_collie())
return (!(val & (UCB_TS_CR_TSPX_LOW)));
else
return (val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW));
}
/*
* This is a RT kernel thread that handles the ADC accesses
* (mainly so we can use semaphores in the UCB1200 core code
* to serialise accesses to the ADC).
*/
static int ucb1x00_thread(void *_ts)
{
struct ucb1x00_ts *ts = _ts;
DECLARE_WAITQUEUE(wait, current);
bool frozen, ignore = false;
int valid = 0;
set_freezable();
add_wait_queue(&ts->irq_wait, &wait);
while (!kthread_freezable_should_stop(&frozen)) {
unsigned int x, y, p;
signed long timeout;
if (frozen)
ignore = true;
ucb1x00_adc_enable(ts->ucb);
x = ucb1x00_ts_read_xpos(ts);
y = ucb1x00_ts_read_ypos(ts);
p = ucb1x00_ts_read_pressure(ts);
/*
* Switch back to interrupt mode.
*/
ucb1x00_ts_mode_int(ts);
ucb1x00_adc_disable(ts->ucb);
msleep(10);
ucb1x00_enable(ts->ucb);
if (ucb1x00_ts_pen_down(ts)) {
set_current_state(TASK_INTERRUPTIBLE);
spin_lock_irq(&ts->irq_lock);
if (ts->irq_disabled) {
ts->irq_disabled = 0;
enable_irq(ts->ucb->irq_base + UCB_IRQ_TSPX);
}
spin_unlock_irq(&ts->irq_lock);
ucb1x00_disable(ts->ucb);
/*
* If we spat out a valid sample set last time,
* spit out a "pen off" sample here.
*/
if (valid) {
ucb1x00_ts_event_release(ts);
valid = 0;
}
timeout = MAX_SCHEDULE_TIMEOUT;
} else {
ucb1x00_disable(ts->ucb);
/*
* Filtering is policy. Policy belongs in user
* space. We therefore leave it to user space
* to do any filtering they please.
*/
if (!ignore) {
ucb1x00_ts_evt_add(ts, p, x, y);
valid = 1;
}
set_current_state(TASK_INTERRUPTIBLE);
timeout = HZ / 100;
}
schedule_timeout(timeout);
}
remove_wait_queue(&ts->irq_wait, &wait);
ts->rtask = NULL;
return 0;
}
/*
* We only detect touch screen _touches_ with this interrupt
* handler, and even then we just schedule our task.
*/
static irqreturn_t ucb1x00_ts_irq(int irq, void *id)
{
struct ucb1x00_ts *ts = id;
spin_lock(&ts->irq_lock);
ts->irq_disabled = 1;
disable_irq_nosync(ts->ucb->irq_base + UCB_IRQ_TSPX);
spin_unlock(&ts->irq_lock);
wake_up(&ts->irq_wait);
return IRQ_HANDLED;
}
static int ucb1x00_ts_open(struct input_dev *idev)
{
struct ucb1x00_ts *ts = input_get_drvdata(idev);
unsigned long flags = 0;
int ret = 0;
BUG_ON(ts->rtask);
if (machine_is_collie())
flags = IRQF_TRIGGER_RISING;
else
flags = IRQF_TRIGGER_FALLING;
ts->irq_disabled = 0;
init_waitqueue_head(&ts->irq_wait);
ret = request_irq(ts->ucb->irq_base + UCB_IRQ_TSPX, ucb1x00_ts_irq,
flags, "ucb1x00-ts", ts);
if (ret < 0)
goto out;
/*
* If we do this at all, we should allow the user to
* measure and read the X and Y resistance at any time.
*/
ucb1x00_adc_enable(ts->ucb);
ts->x_res = ucb1x00_ts_read_xres(ts);
ts->y_res = ucb1x00_ts_read_yres(ts);
ucb1x00_adc_disable(ts->ucb);
ts->rtask = kthread_run(ucb1x00_thread, ts, "ktsd");
if (!IS_ERR(ts->rtask)) {
ret = 0;
} else {
free_irq(ts->ucb->irq_base + UCB_IRQ_TSPX, ts);
ts->rtask = NULL;
ret = -EFAULT;
}
out:
return ret;
}
/*
* Release touchscreen resources. Disable IRQs.
*/
static void ucb1x00_ts_close(struct input_dev *idev)
{
struct ucb1x00_ts *ts = input_get_drvdata(idev);
if (ts->rtask)
kthread_stop(ts->rtask);
ucb1x00_enable(ts->ucb);
free_irq(ts->ucb->irq_base + UCB_IRQ_TSPX, ts);
ucb1x00_reg_write(ts->ucb, UCB_TS_CR, 0);
ucb1x00_disable(ts->ucb);
}
/*
* Initialisation.
*/
static int ucb1x00_ts_add(struct ucb1x00_dev *dev)
{
struct ucb1x00_ts *ts;
struct input_dev *idev;
int err;
ts = kzalloc(sizeof(struct ucb1x00_ts), GFP_KERNEL);
idev = input_allocate_device();
if (!ts || !idev) {
err = -ENOMEM;
goto fail;
}
ts->ucb = dev->ucb;
ts->idev = idev;
ts->adcsync = adcsync ? UCB_SYNC : UCB_NOSYNC;
spin_lock_init(&ts->irq_lock);
idev->name = "Touchscreen panel";
idev->id.product = ts->ucb->id;
idev->open = ucb1x00_ts_open;
idev->close = ucb1x00_ts_close;
idev->dev.parent = &ts->ucb->dev;
idev->evbit[0] = BIT_MASK(EV_ABS) | BIT_MASK(EV_KEY);
idev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
input_set_drvdata(idev, ts);
ucb1x00_adc_enable(ts->ucb);
ts->x_res = ucb1x00_ts_read_xres(ts);
ts->y_res = ucb1x00_ts_read_yres(ts);
ucb1x00_adc_disable(ts->ucb);
input_set_abs_params(idev, ABS_X, 0, ts->x_res, 0, 0);
input_set_abs_params(idev, ABS_Y, 0, ts->y_res, 0, 0);
input_set_abs_params(idev, ABS_PRESSURE, 0, 0, 0, 0);
err = input_register_device(idev);
if (err)
goto fail;
dev->priv = ts;
return 0;
fail:
input_free_device(idev);
kfree(ts);
return err;
}
static void ucb1x00_ts_remove(struct ucb1x00_dev *dev)
{
struct ucb1x00_ts *ts = dev->priv;
input_unregister_device(ts->idev);
kfree(ts);
}
static struct ucb1x00_driver ucb1x00_ts_driver = {
.add = ucb1x00_ts_add,
.remove = ucb1x00_ts_remove,
};
static int __init ucb1x00_ts_init(void)
{
return ucb1x00_register_driver(&ucb1x00_ts_driver);
}
static void __exit ucb1x00_ts_exit(void)
{
ucb1x00_unregister_driver(&ucb1x00_ts_driver);
}
module_param(adcsync, int, 0444);
module_init(ucb1x00_ts_init);
module_exit(ucb1x00_ts_exit);
MODULE_AUTHOR("Russell King <[email protected]>");
MODULE_DESCRIPTION("UCB1x00 touchscreen driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/ucb1x00-ts.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* twl4030-irq.c - TWL4030/TPS659x0 irq support
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* Modifications to defer interrupt handling to a kernel thread:
* Copyright (C) 2006 MontaVista Software, Inc.
*
* Based on tlv320aic23.c:
* Copyright (c) by Kai Svahn <[email protected]>
*
* Code cleanup and modifications to IRQ handler.
* by syed khasim <[email protected]>
*/
#include <linux/device.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/irqdomain.h>
#include <linux/mfd/twl.h>
#include "twl-core.h"
/*
* TWL4030 IRQ handling has two stages in hardware, and thus in software.
* The Primary Interrupt Handler (PIH) stage exposes status bits saying
* which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
* SIH modules are more traditional IRQ components, which support per-IRQ
* enable/disable and trigger controls; they do most of the work.
*
* These chips are designed to support IRQ handling from two different
* I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
* and mask registers in the PIH and SIH modules.
*
* We set up IRQs starting at a platform-specified base, always starting
* with PIH and the SIH for PWR_INT and then usually adding GPIO:
* base + 0 .. base + 7 PIH
* base + 8 .. base + 15 SIH for PWR_INT
* base + 16 .. base + 33 SIH for GPIO
*/
#define TWL4030_CORE_NR_IRQS 8
#define TWL4030_PWR_NR_IRQS 8
/* PIH register offsets */
#define REG_PIH_ISR_P1 0x01
#define REG_PIH_ISR_P2 0x02
#define REG_PIH_SIR 0x03 /* for testing */
/* Linux could (eventually) use either IRQ line */
static int irq_line;
struct sih {
char name[8];
u8 module; /* module id */
u8 control_offset; /* for SIH_CTRL */
bool set_cor;
u8 bits; /* valid in isr/imr */
u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
u8 edr_offset;
u8 bytes_edr; /* bytelen of EDR */
u8 irq_lines; /* number of supported irq lines */
/* SIR ignored -- set interrupt, for testing only */
struct sih_irq_data {
u8 isr_offset;
u8 imr_offset;
} mask[2];
/* + 2 bytes padding */
};
static const struct sih *sih_modules;
static int nr_sih_modules;
#define SIH_INITIALIZER(modname, nbits) \
.module = TWL4030_MODULE_ ## modname, \
.control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
.bits = nbits, \
.bytes_ixr = DIV_ROUND_UP(nbits, 8), \
.edr_offset = TWL4030_ ## modname ## _EDR, \
.bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
.irq_lines = 2, \
.mask = { { \
.isr_offset = TWL4030_ ## modname ## _ISR1, \
.imr_offset = TWL4030_ ## modname ## _IMR1, \
}, \
{ \
.isr_offset = TWL4030_ ## modname ## _ISR2, \
.imr_offset = TWL4030_ ## modname ## _IMR2, \
}, },
/* register naming policies are inconsistent ... */
#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
/*
* Order in this table matches order in PIH_ISR. That is,
* BIT(n) in PIH_ISR is sih_modules[n].
*/
/* sih_modules_twl4030 is used both in twl4030 and twl5030 */
static const struct sih sih_modules_twl4030[6] = {
[0] = {
.name = "gpio",
.module = TWL4030_MODULE_GPIO,
.control_offset = REG_GPIO_SIH_CTRL,
.set_cor = true,
.bits = TWL4030_GPIO_MAX,
.bytes_ixr = 3,
/* Note: *all* of these IRQs default to no-trigger */
.edr_offset = REG_GPIO_EDR1,
.bytes_edr = 5,
.irq_lines = 2,
.mask = { {
.isr_offset = REG_GPIO_ISR1A,
.imr_offset = REG_GPIO_IMR1A,
}, {
.isr_offset = REG_GPIO_ISR1B,
.imr_offset = REG_GPIO_IMR1B,
}, },
},
[1] = {
.name = "keypad",
.set_cor = true,
SIH_INITIALIZER(KEYPAD_KEYP, 4)
},
[2] = {
.name = "bci",
.module = TWL4030_MODULE_INTERRUPTS,
.control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
.set_cor = true,
.bits = 12,
.bytes_ixr = 2,
.edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
/* Note: most of these IRQs default to no-trigger */
.bytes_edr = 3,
.irq_lines = 2,
.mask = { {
.isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
.imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
}, {
.isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
.imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
}, },
},
[3] = {
.name = "madc",
SIH_INITIALIZER(MADC, 4)
},
[4] = {
/* USB doesn't use the same SIH organization */
.name = "usb",
},
[5] = {
.name = "power",
.set_cor = true,
SIH_INITIALIZER(INT_PWR, 8)
},
/* there are no SIH modules #6 or #7 ... */
};
static const struct sih sih_modules_twl5031[8] = {
[0] = {
.name = "gpio",
.module = TWL4030_MODULE_GPIO,
.control_offset = REG_GPIO_SIH_CTRL,
.set_cor = true,
.bits = TWL4030_GPIO_MAX,
.bytes_ixr = 3,
/* Note: *all* of these IRQs default to no-trigger */
.edr_offset = REG_GPIO_EDR1,
.bytes_edr = 5,
.irq_lines = 2,
.mask = { {
.isr_offset = REG_GPIO_ISR1A,
.imr_offset = REG_GPIO_IMR1A,
}, {
.isr_offset = REG_GPIO_ISR1B,
.imr_offset = REG_GPIO_IMR1B,
}, },
},
[1] = {
.name = "keypad",
.set_cor = true,
SIH_INITIALIZER(KEYPAD_KEYP, 4)
},
[2] = {
.name = "bci",
.module = TWL5031_MODULE_INTERRUPTS,
.control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
.bits = 7,
.bytes_ixr = 1,
.edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
/* Note: most of these IRQs default to no-trigger */
.bytes_edr = 2,
.irq_lines = 2,
.mask = { {
.isr_offset = TWL5031_INTERRUPTS_BCIISR1,
.imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
}, {
.isr_offset = TWL5031_INTERRUPTS_BCIISR2,
.imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
}, },
},
[3] = {
.name = "madc",
SIH_INITIALIZER(MADC, 4)
},
[4] = {
/* USB doesn't use the same SIH organization */
.name = "usb",
},
[5] = {
.name = "power",
.set_cor = true,
SIH_INITIALIZER(INT_PWR, 8)
},
[6] = {
/*
* ECI/DBI doesn't use the same SIH organization.
* For example, it supports only one interrupt output line.
* That is, the interrupts are seen on both INT1 and INT2 lines.
*/
.name = "eci_dbi",
.module = TWL5031_MODULE_ACCESSORY,
.bits = 9,
.bytes_ixr = 2,
.irq_lines = 1,
.mask = { {
.isr_offset = TWL5031_ACIIDR_LSB,
.imr_offset = TWL5031_ACIIMR_LSB,
}, },
},
[7] = {
/* Audio accessory */
.name = "audio",
.module = TWL5031_MODULE_ACCESSORY,
.control_offset = TWL5031_ACCSIHCTRL,
.bits = 2,
.bytes_ixr = 1,
.edr_offset = TWL5031_ACCEDR1,
/* Note: most of these IRQs default to no-trigger */
.bytes_edr = 1,
.irq_lines = 2,
.mask = { {
.isr_offset = TWL5031_ACCISR1,
.imr_offset = TWL5031_ACCIMR1,
}, {
.isr_offset = TWL5031_ACCISR2,
.imr_offset = TWL5031_ACCIMR2,
}, },
},
};
#undef TWL4030_MODULE_KEYPAD_KEYP
#undef TWL4030_MODULE_INT_PWR
#undef TWL4030_INT_PWR_EDR
/*----------------------------------------------------------------------*/
static unsigned twl4030_irq_base;
/*
* handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
* This is a chained interrupt, so there is no desc->action method for it.
* Now we need to query the interrupt controller in the twl4030 to determine
* which module is generating the interrupt request. However, we can't do i2c
* transactions in interrupt context, so we must defer that work to a kernel
* thread. All we do here is acknowledge and mask the interrupt and wakeup
* the kernel thread.
*/
static irqreturn_t handle_twl4030_pih(int irq, void *devid)
{
irqreturn_t ret;
u8 pih_isr;
ret = twl_i2c_read_u8(TWL_MODULE_PIH, &pih_isr,
REG_PIH_ISR_P1);
if (ret) {
pr_warn("twl4030: I2C error %d reading PIH ISR\n", ret);
return IRQ_NONE;
}
while (pih_isr) {
unsigned long pending = __ffs(pih_isr);
unsigned int irq;
pih_isr &= ~BIT(pending);
irq = pending + twl4030_irq_base;
handle_nested_irq(irq);
}
return IRQ_HANDLED;
}
/*----------------------------------------------------------------------*/
/*
* twl4030_init_sih_modules() ... start from a known state where no
* IRQs will be coming in, and where we can quickly enable them then
* handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
*
* NOTE: we don't touch EDR registers here; they stay with hardware
* defaults or whatever the last value was. Note that when both EDR
* bits for an IRQ are clear, that's as if its IMR bit is set...
*/
static int twl4030_init_sih_modules(unsigned line)
{
const struct sih *sih;
u8 buf[4];
int i;
int status;
/* line 0 == int1_n signal; line 1 == int2_n signal */
if (line > 1)
return -EINVAL;
irq_line = line;
/* disable all interrupts on our line */
memset(buf, 0xff, sizeof(buf));
sih = sih_modules;
for (i = 0; i < nr_sih_modules; i++, sih++) {
/* skip USB -- it's funky */
if (!sih->bytes_ixr)
continue;
/* Not all the SIH modules support multiple interrupt lines */
if (sih->irq_lines <= line)
continue;
status = twl_i2c_write(sih->module, buf,
sih->mask[line].imr_offset, sih->bytes_ixr);
if (status < 0)
pr_err("twl4030: err %d initializing %s %s\n",
status, sih->name, "IMR");
/*
* Maybe disable "exclusive" mode; buffer second pending irq;
* set Clear-On-Read (COR) bit.
*
* NOTE that sometimes COR polarity is documented as being
* inverted: for MADC, COR=1 means "clear on write".
* And for PWR_INT it's not documented...
*/
if (sih->set_cor) {
status = twl_i2c_write_u8(sih->module,
TWL4030_SIH_CTRL_COR_MASK,
sih->control_offset);
if (status < 0)
pr_err("twl4030: err %d initializing %s %s\n",
status, sih->name, "SIH_CTRL");
}
}
sih = sih_modules;
for (i = 0; i < nr_sih_modules; i++, sih++) {
u8 rxbuf[4];
int j;
/* skip USB */
if (!sih->bytes_ixr)
continue;
/* Not all the SIH modules support multiple interrupt lines */
if (sih->irq_lines <= line)
continue;
/*
* Clear pending interrupt status. Either the read was
* enough, or we need to write those bits. Repeat, in
* case an IRQ is pending (PENDDIS=0) ... that's not
* uncommon with PWR_INT.PWRON.
*/
for (j = 0; j < 2; j++) {
status = twl_i2c_read(sih->module, rxbuf,
sih->mask[line].isr_offset, sih->bytes_ixr);
if (status < 0)
pr_warn("twl4030: err %d initializing %s %s\n",
status, sih->name, "ISR");
if (!sih->set_cor) {
status = twl_i2c_write(sih->module, buf,
sih->mask[line].isr_offset,
sih->bytes_ixr);
if (status < 0)
pr_warn("twl4030: write failed: %d\n",
status);
}
/*
* else COR=1 means read sufficed.
* (for most SIH modules...)
*/
}
}
return 0;
}
static inline void activate_irq(int irq)
{
irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
/*----------------------------------------------------------------------*/
struct sih_agent {
int irq_base;
const struct sih *sih;
u32 imr;
bool imr_change_pending;
u32 edge_change;
struct mutex irq_lock;
char *irq_name;
};
/*----------------------------------------------------------------------*/
/*
* All irq_chip methods get issued from code holding irq_desc[irq].lock,
* which can't perform the underlying I2C operations (because they sleep).
* So we must hand them off to a thread (workqueue) and cope with asynch
* completion, potentially including some re-ordering, of these requests.
*/
static void twl4030_sih_mask(struct irq_data *data)
{
struct sih_agent *agent = irq_data_get_irq_chip_data(data);
agent->imr |= BIT(data->irq - agent->irq_base);
agent->imr_change_pending = true;
}
static void twl4030_sih_unmask(struct irq_data *data)
{
struct sih_agent *agent = irq_data_get_irq_chip_data(data);
agent->imr &= ~BIT(data->irq - agent->irq_base);
agent->imr_change_pending = true;
}
static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
{
struct sih_agent *agent = irq_data_get_irq_chip_data(data);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL;
if (irqd_get_trigger_type(data) != trigger)
agent->edge_change |= BIT(data->irq - agent->irq_base);
return 0;
}
static void twl4030_sih_bus_lock(struct irq_data *data)
{
struct sih_agent *agent = irq_data_get_irq_chip_data(data);
mutex_lock(&agent->irq_lock);
}
static void twl4030_sih_bus_sync_unlock(struct irq_data *data)
{
struct sih_agent *agent = irq_data_get_irq_chip_data(data);
const struct sih *sih = agent->sih;
int status;
if (agent->imr_change_pending) {
union {
__le32 word;
u8 bytes[4];
} imr;
/* byte[0] gets overwritten as we write ... */
imr.word = cpu_to_le32(agent->imr);
agent->imr_change_pending = false;
/* write the whole mask ... simpler than subsetting it */
status = twl_i2c_write(sih->module, imr.bytes,
sih->mask[irq_line].imr_offset,
sih->bytes_ixr);
if (status)
pr_err("twl4030: %s, %s --> %d\n", __func__,
"write", status);
}
if (agent->edge_change) {
u32 edge_change;
u8 bytes[6];
edge_change = agent->edge_change;
agent->edge_change = 0;
/*
* Read, reserving first byte for write scratch. Yes, this
* could be cached for some speedup ... but be careful about
* any processor on the other IRQ line, EDR registers are
* shared.
*/
status = twl_i2c_read(sih->module, bytes,
sih->edr_offset, sih->bytes_edr);
if (status) {
pr_err("twl4030: %s, %s --> %d\n", __func__,
"read", status);
return;
}
/* Modify only the bits we know must change */
while (edge_change) {
int i = fls(edge_change) - 1;
int byte = i >> 2;
int off = (i & 0x3) * 2;
unsigned int type;
bytes[byte] &= ~(0x03 << off);
type = irq_get_trigger_type(i + agent->irq_base);
if (type & IRQ_TYPE_EDGE_RISING)
bytes[byte] |= BIT(off + 1);
if (type & IRQ_TYPE_EDGE_FALLING)
bytes[byte] |= BIT(off + 0);
edge_change &= ~BIT(i);
}
/* Write */
status = twl_i2c_write(sih->module, bytes,
sih->edr_offset, sih->bytes_edr);
if (status)
pr_err("twl4030: %s, %s --> %d\n", __func__,
"write", status);
}
mutex_unlock(&agent->irq_lock);
}
static struct irq_chip twl4030_sih_irq_chip = {
.name = "twl4030",
.irq_mask = twl4030_sih_mask,
.irq_unmask = twl4030_sih_unmask,
.irq_set_type = twl4030_sih_set_type,
.irq_bus_lock = twl4030_sih_bus_lock,
.irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
/*----------------------------------------------------------------------*/
static inline int sih_read_isr(const struct sih *sih)
{
int status;
union {
u8 bytes[4];
__le32 word;
} isr;
/* FIXME need retry-on-error ... */
isr.word = 0;
status = twl_i2c_read(sih->module, isr.bytes,
sih->mask[irq_line].isr_offset, sih->bytes_ixr);
return (status < 0) ? status : le32_to_cpu(isr.word);
}
/*
* Generic handler for SIH interrupts ... we "know" this is called
* in task context, with IRQs enabled.
*/
static irqreturn_t handle_twl4030_sih(int irq, void *data)
{
struct sih_agent *agent = irq_get_handler_data(irq);
const struct sih *sih = agent->sih;
int isr;
/* reading ISR acks the IRQs, using clear-on-read mode */
isr = sih_read_isr(sih);
if (isr < 0) {
pr_err("twl4030: %s SIH, read ISR error %d\n",
sih->name, isr);
/* REVISIT: recover; eventually mask it all, etc */
return IRQ_HANDLED;
}
while (isr) {
irq = fls(isr);
irq--;
isr &= ~BIT(irq);
if (irq < sih->bits)
handle_nested_irq(agent->irq_base + irq);
else
pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
sih->name, irq);
}
return IRQ_HANDLED;
}
/* returns the first IRQ used by this SIH bank, or negative errno */
int twl4030_sih_setup(struct device *dev, int module, int irq_base)
{
int sih_mod;
const struct sih *sih = NULL;
struct sih_agent *agent;
int i, irq;
int status = -EINVAL;
/* only support modules with standard clear-on-read for now */
for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules;
sih_mod++, sih++) {
if (sih->module == module && sih->set_cor) {
status = 0;
break;
}
}
if (status < 0) {
dev_err(dev, "module to setup SIH for not found\n");
return status;
}
agent = kzalloc(sizeof(*agent), GFP_KERNEL);
if (!agent)
return -ENOMEM;
agent->irq_base = irq_base;
agent->sih = sih;
agent->imr = ~0;
mutex_init(&agent->irq_lock);
for (i = 0; i < sih->bits; i++) {
irq = irq_base + i;
irq_set_chip_data(irq, agent);
irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
handle_edge_irq);
irq_set_nested_thread(irq, 1);
activate_irq(irq);
}
/* replace generic PIH handler (handle_simple_irq) */
irq = sih_mod + twl4030_irq_base;
irq_set_handler_data(irq, agent);
agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name);
status = request_threaded_irq(irq, NULL, handle_twl4030_sih,
IRQF_EARLY_RESUME | IRQF_ONESHOT,
agent->irq_name ?: sih->name, NULL);
dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
irq, irq_base, irq_base + i - 1);
return status < 0 ? status : irq_base;
}
/* FIXME need a call to reverse twl4030_sih_setup() ... */
/*----------------------------------------------------------------------*/
/* FIXME pass in which interrupt line we'll use ... */
#define twl_irq_line 0
int twl4030_init_irq(struct device *dev, int irq_num)
{
static struct irq_chip twl4030_irq_chip;
int status, i;
int irq_base, irq_end, nr_irqs;
struct device_node *node = dev->of_node;
/*
* TWL core and pwr interrupts must be contiguous because
* the hwirqs numbers are defined contiguously from 1 to 15.
* Create only one domain for both.
*/
nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS;
irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
if (irq_base < 0) {
dev_err(dev, "Fail to allocate IRQ descs\n");
return irq_base;
}
irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
&irq_domain_simple_ops, NULL);
irq_end = irq_base + TWL4030_CORE_NR_IRQS;
/*
* Mask and clear all TWL4030 interrupts since initially we do
* not have any TWL4030 module interrupt handlers present
*/
status = twl4030_init_sih_modules(twl_irq_line);
if (status < 0)
return status;
twl4030_irq_base = irq_base;
/*
* Install an irq handler for each of the SIH modules;
* clone dummy irq_chip since PIH can't *do* anything
*/
twl4030_irq_chip = dummy_irq_chip;
twl4030_irq_chip.name = "twl4030";
twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
for (i = irq_base; i < irq_end; i++) {
irq_set_chip_and_handler(i, &twl4030_irq_chip,
handle_simple_irq);
irq_set_nested_thread(i, 1);
activate_irq(i);
}
dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
irq_num, irq_base, irq_end);
/* ... and the PWR_INT module ... */
status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
if (status < 0) {
dev_err(dev, "sih_setup PWR INT --> %d\n", status);
goto fail;
}
/* install an irq handler to demultiplex the TWL4030 interrupt */
status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
IRQF_ONESHOT,
"TWL4030-PIH", NULL);
if (status < 0) {
dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
goto fail_rqirq;
}
enable_irq_wake(irq_num);
return irq_base;
fail_rqirq:
/* clean up twl4030_sih_setup */
fail:
for (i = irq_base; i < irq_end; i++) {
irq_set_nested_thread(i, 0);
irq_set_chip_and_handler(i, NULL, NULL);
}
return status;
}
void twl4030_exit_irq(void)
{
/* FIXME undo twl_init_irq() */
if (twl4030_irq_base)
pr_err("twl4030: can't yet clean up IRQs?\n");
}
int twl4030_init_chip_irq(const char *chip)
{
if (!strcmp(chip, "twl5031")) {
sih_modules = sih_modules_twl5031;
nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
} else {
sih_modules = sih_modules_twl4030;
nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
}
return 0;
}
| linux-master | drivers/mfd/twl4030-irq.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Device access for Dialog DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <[email protected]>
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/input.h>
#include <linux/irq.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/mfd/da9055/core.h>
#include <linux/mfd/da9055/pdata.h>
#include <linux/mfd/da9055/reg.h>
#define DA9055_IRQ_NONKEY_MASK 0x01
#define DA9055_IRQ_ALM_MASK 0x02
#define DA9055_IRQ_TICK_MASK 0x04
#define DA9055_IRQ_ADC_MASK 0x08
#define DA9055_IRQ_BUCK_ILIM_MASK 0x08
static bool da9055_register_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA9055_REG_STATUS_A:
case DA9055_REG_STATUS_B:
case DA9055_REG_EVENT_A:
case DA9055_REG_EVENT_B:
case DA9055_REG_EVENT_C:
case DA9055_REG_IRQ_MASK_A:
case DA9055_REG_IRQ_MASK_B:
case DA9055_REG_IRQ_MASK_C:
case DA9055_REG_CONTROL_A:
case DA9055_REG_CONTROL_B:
case DA9055_REG_CONTROL_C:
case DA9055_REG_CONTROL_D:
case DA9055_REG_CONTROL_E:
case DA9055_REG_ADC_MAN:
case DA9055_REG_ADC_CONT:
case DA9055_REG_VSYS_MON:
case DA9055_REG_ADC_RES_L:
case DA9055_REG_ADC_RES_H:
case DA9055_REG_VSYS_RES:
case DA9055_REG_ADCIN1_RES:
case DA9055_REG_ADCIN2_RES:
case DA9055_REG_ADCIN3_RES:
case DA9055_REG_COUNT_S:
case DA9055_REG_COUNT_MI:
case DA9055_REG_COUNT_H:
case DA9055_REG_COUNT_D:
case DA9055_REG_COUNT_MO:
case DA9055_REG_COUNT_Y:
case DA9055_REG_ALARM_H:
case DA9055_REG_ALARM_D:
case DA9055_REG_ALARM_MI:
case DA9055_REG_ALARM_MO:
case DA9055_REG_ALARM_Y:
case DA9055_REG_GPIO0_1:
case DA9055_REG_GPIO2:
case DA9055_REG_GPIO_MODE0_2:
case DA9055_REG_BCORE_CONT:
case DA9055_REG_BMEM_CONT:
case DA9055_REG_LDO1_CONT:
case DA9055_REG_LDO2_CONT:
case DA9055_REG_LDO3_CONT:
case DA9055_REG_LDO4_CONT:
case DA9055_REG_LDO5_CONT:
case DA9055_REG_LDO6_CONT:
case DA9055_REG_BUCK_LIM:
case DA9055_REG_BCORE_MODE:
case DA9055_REG_VBCORE_A:
case DA9055_REG_VBMEM_A:
case DA9055_REG_VLDO1_A:
case DA9055_REG_VLDO2_A:
case DA9055_REG_VLDO3_A:
case DA9055_REG_VLDO4_A:
case DA9055_REG_VLDO5_A:
case DA9055_REG_VLDO6_A:
case DA9055_REG_VBCORE_B:
case DA9055_REG_VBMEM_B:
case DA9055_REG_VLDO1_B:
case DA9055_REG_VLDO2_B:
case DA9055_REG_VLDO3_B:
case DA9055_REG_VLDO4_B:
case DA9055_REG_VLDO5_B:
case DA9055_REG_VLDO6_B:
return true;
default:
return false;
}
}
static bool da9055_register_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA9055_REG_STATUS_A:
case DA9055_REG_STATUS_B:
case DA9055_REG_EVENT_A:
case DA9055_REG_EVENT_B:
case DA9055_REG_EVENT_C:
case DA9055_REG_IRQ_MASK_A:
case DA9055_REG_IRQ_MASK_B:
case DA9055_REG_IRQ_MASK_C:
case DA9055_REG_CONTROL_A:
case DA9055_REG_CONTROL_B:
case DA9055_REG_CONTROL_C:
case DA9055_REG_CONTROL_D:
case DA9055_REG_CONTROL_E:
case DA9055_REG_ADC_MAN:
case DA9055_REG_ADC_CONT:
case DA9055_REG_VSYS_MON:
case DA9055_REG_ADC_RES_L:
case DA9055_REG_ADC_RES_H:
case DA9055_REG_VSYS_RES:
case DA9055_REG_ADCIN1_RES:
case DA9055_REG_ADCIN2_RES:
case DA9055_REG_ADCIN3_RES:
case DA9055_REG_COUNT_S:
case DA9055_REG_COUNT_MI:
case DA9055_REG_COUNT_H:
case DA9055_REG_COUNT_D:
case DA9055_REG_COUNT_MO:
case DA9055_REG_COUNT_Y:
case DA9055_REG_ALARM_H:
case DA9055_REG_ALARM_D:
case DA9055_REG_ALARM_MI:
case DA9055_REG_ALARM_MO:
case DA9055_REG_ALARM_Y:
case DA9055_REG_GPIO0_1:
case DA9055_REG_GPIO2:
case DA9055_REG_GPIO_MODE0_2:
case DA9055_REG_BCORE_CONT:
case DA9055_REG_BMEM_CONT:
case DA9055_REG_LDO1_CONT:
case DA9055_REG_LDO2_CONT:
case DA9055_REG_LDO3_CONT:
case DA9055_REG_LDO4_CONT:
case DA9055_REG_LDO5_CONT:
case DA9055_REG_LDO6_CONT:
case DA9055_REG_BUCK_LIM:
case DA9055_REG_BCORE_MODE:
case DA9055_REG_VBCORE_A:
case DA9055_REG_VBMEM_A:
case DA9055_REG_VLDO1_A:
case DA9055_REG_VLDO2_A:
case DA9055_REG_VLDO3_A:
case DA9055_REG_VLDO4_A:
case DA9055_REG_VLDO5_A:
case DA9055_REG_VLDO6_A:
case DA9055_REG_VBCORE_B:
case DA9055_REG_VBMEM_B:
case DA9055_REG_VLDO1_B:
case DA9055_REG_VLDO2_B:
case DA9055_REG_VLDO3_B:
case DA9055_REG_VLDO4_B:
case DA9055_REG_VLDO5_B:
case DA9055_REG_VLDO6_B:
return true;
default:
return false;
}
}
static bool da9055_register_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA9055_REG_STATUS_A:
case DA9055_REG_STATUS_B:
case DA9055_REG_EVENT_A:
case DA9055_REG_EVENT_B:
case DA9055_REG_EVENT_C:
case DA9055_REG_CONTROL_A:
case DA9055_REG_CONTROL_E:
case DA9055_REG_ADC_MAN:
case DA9055_REG_ADC_RES_L:
case DA9055_REG_ADC_RES_H:
case DA9055_REG_VSYS_RES:
case DA9055_REG_ADCIN1_RES:
case DA9055_REG_ADCIN2_RES:
case DA9055_REG_ADCIN3_RES:
case DA9055_REG_COUNT_S:
case DA9055_REG_COUNT_MI:
case DA9055_REG_COUNT_H:
case DA9055_REG_COUNT_D:
case DA9055_REG_COUNT_MO:
case DA9055_REG_COUNT_Y:
case DA9055_REG_ALARM_MI:
case DA9055_REG_BCORE_CONT:
case DA9055_REG_BMEM_CONT:
case DA9055_REG_LDO1_CONT:
case DA9055_REG_LDO2_CONT:
case DA9055_REG_LDO3_CONT:
case DA9055_REG_LDO4_CONT:
case DA9055_REG_LDO5_CONT:
case DA9055_REG_LDO6_CONT:
return true;
default:
return false;
}
}
static const struct regmap_irq da9055_irqs[] = {
[DA9055_IRQ_NONKEY] = {
.reg_offset = 0,
.mask = DA9055_IRQ_NONKEY_MASK,
},
[DA9055_IRQ_ALARM] = {
.reg_offset = 0,
.mask = DA9055_IRQ_ALM_MASK,
},
[DA9055_IRQ_TICK] = {
.reg_offset = 0,
.mask = DA9055_IRQ_TICK_MASK,
},
[DA9055_IRQ_HWMON] = {
.reg_offset = 0,
.mask = DA9055_IRQ_ADC_MASK,
},
[DA9055_IRQ_REGULATOR] = {
.reg_offset = 1,
.mask = DA9055_IRQ_BUCK_ILIM_MASK,
},
};
const struct regmap_config da9055_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.max_register = DA9055_MAX_REGISTER_CNT,
.readable_reg = da9055_register_readable,
.writeable_reg = da9055_register_writeable,
.volatile_reg = da9055_register_volatile,
};
EXPORT_SYMBOL_GPL(da9055_regmap_config);
static const struct resource da9055_onkey_resource =
DEFINE_RES_IRQ_NAMED(DA9055_IRQ_NONKEY, "ONKEY");
static const struct resource da9055_rtc_resource[] = {
DEFINE_RES_IRQ_NAMED(DA9055_IRQ_ALARM, "ALM"),
DEFINE_RES_IRQ_NAMED(DA9055_IRQ_TICK, "TICK"),
};
static const struct resource da9055_hwmon_resource =
DEFINE_RES_IRQ_NAMED(DA9055_IRQ_HWMON, "HWMON");
static const struct resource da9055_ld05_6_resource =
DEFINE_RES_IRQ_NAMED(DA9055_IRQ_REGULATOR, "REGULATOR");
static const struct mfd_cell da9055_devs[] = {
{
.of_compatible = "dlg,da9055-gpio",
.name = "da9055-gpio",
},
{
.of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator",
.id = 1,
},
{
.of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator",
.id = 2,
},
{
.of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator",
.id = 3,
},
{
.of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator",
.id = 4,
},
{
.of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator",
.id = 5,
},
{
.of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator",
.id = 6,
},
{
.of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator",
.id = 7,
.resources = &da9055_ld05_6_resource,
.num_resources = 1,
},
{
.of_compatible = "dlg,da9055-regulator",
.name = "da9055-regulator",
.resources = &da9055_ld05_6_resource,
.num_resources = 1,
.id = 8,
},
{
.of_compatible = "dlg,da9055-onkey",
.name = "da9055-onkey",
.resources = &da9055_onkey_resource,
.num_resources = 1,
},
{
.of_compatible = "dlg,da9055-rtc",
.name = "da9055-rtc",
.resources = da9055_rtc_resource,
.num_resources = ARRAY_SIZE(da9055_rtc_resource),
},
{
.of_compatible = "dlg,da9055-hwmon",
.name = "da9055-hwmon",
.resources = &da9055_hwmon_resource,
.num_resources = 1,
},
{
.of_compatible = "dlg,da9055-watchdog",
.name = "da9055-watchdog",
},
};
static const struct regmap_irq_chip da9055_regmap_irq_chip = {
.name = "da9055_irq",
.status_base = DA9055_REG_EVENT_A,
.mask_base = DA9055_REG_IRQ_MASK_A,
.ack_base = DA9055_REG_EVENT_A,
.num_regs = 3,
.irqs = da9055_irqs,
.num_irqs = ARRAY_SIZE(da9055_irqs),
};
int da9055_device_init(struct da9055 *da9055)
{
struct da9055_pdata *pdata = dev_get_platdata(da9055->dev);
int ret;
uint8_t clear_events[3] = {0xFF, 0xFF, 0xFF};
if (pdata && pdata->init != NULL)
pdata->init(da9055);
if (!pdata || !pdata->irq_base)
da9055->irq_base = -1;
else
da9055->irq_base = pdata->irq_base;
ret = da9055_group_write(da9055, DA9055_REG_EVENT_A, 3, clear_events);
if (ret < 0)
return ret;
ret = regmap_add_irq_chip(da9055->regmap, da9055->chip_irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
da9055->irq_base, &da9055_regmap_irq_chip,
&da9055->irq_data);
if (ret < 0)
return ret;
da9055->irq_base = regmap_irq_chip_get_base(da9055->irq_data);
ret = mfd_add_devices(da9055->dev, -1,
da9055_devs, ARRAY_SIZE(da9055_devs),
NULL, da9055->irq_base, NULL);
if (ret)
goto err;
return 0;
err:
mfd_remove_devices(da9055->dev);
return ret;
}
void da9055_device_exit(struct da9055 *da9055)
{
regmap_del_irq_chip(da9055->chip_irq, da9055->irq_data);
mfd_remove_devices(da9055->dev);
}
MODULE_DESCRIPTION("Core support for the DA9055 PMIC");
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
| linux-master | drivers/mfd/da9055-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* Author: Keerthy <[email protected]>
*/
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/mfd/lp87565.h>
static const struct regmap_config lp87565_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = LP87565_REG_MAX,
};
static const struct mfd_cell lp87565_cells[] = {
{ .name = "lp87565-q1-regulator", },
{ .name = "lp87565-q1-gpio", },
};
static const struct of_device_id of_lp87565_match_table[] = {
{ .compatible = "ti,lp87565", },
{
.compatible = "ti,lp87524-q1",
.data = (void *)LP87565_DEVICE_TYPE_LP87524_Q1,
},
{
.compatible = "ti,lp87565-q1",
.data = (void *)LP87565_DEVICE_TYPE_LP87565_Q1,
},
{
.compatible = "ti,lp87561-q1",
.data = (void *)LP87565_DEVICE_TYPE_LP87561_Q1,
},
{}
};
MODULE_DEVICE_TABLE(of, of_lp87565_match_table);
static int lp87565_probe(struct i2c_client *client)
{
struct lp87565 *lp87565;
const struct of_device_id *of_id;
int ret;
unsigned int otpid;
lp87565 = devm_kzalloc(&client->dev, sizeof(*lp87565), GFP_KERNEL);
if (!lp87565)
return -ENOMEM;
lp87565->dev = &client->dev;
lp87565->regmap = devm_regmap_init_i2c(client, &lp87565_regmap_config);
if (IS_ERR(lp87565->regmap)) {
ret = PTR_ERR(lp87565->regmap);
dev_err(lp87565->dev,
"Failed to initialize register map: %d\n", ret);
return ret;
}
lp87565->reset_gpio = devm_gpiod_get_optional(lp87565->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(lp87565->reset_gpio)) {
ret = PTR_ERR(lp87565->reset_gpio);
if (ret == -EPROBE_DEFER)
return ret;
}
if (lp87565->reset_gpio) {
gpiod_set_value_cansleep(lp87565->reset_gpio, 1);
/* The minimum assertion time is undocumented, just guess */
usleep_range(2000, 4000);
gpiod_set_value_cansleep(lp87565->reset_gpio, 0);
/* Min 1.2 ms before first I2C transaction */
usleep_range(1500, 3000);
}
ret = regmap_read(lp87565->regmap, LP87565_REG_OTP_REV, &otpid);
if (ret) {
dev_err(lp87565->dev, "Failed to read OTP ID\n");
return ret;
}
lp87565->rev = otpid & LP87565_OTP_REV_OTP_ID;
of_id = of_match_device(of_lp87565_match_table, &client->dev);
if (of_id)
lp87565->dev_type = (uintptr_t)of_id->data;
i2c_set_clientdata(client, lp87565);
return devm_mfd_add_devices(lp87565->dev, PLATFORM_DEVID_AUTO,
lp87565_cells, ARRAY_SIZE(lp87565_cells),
NULL, 0, NULL);
}
static void lp87565_shutdown(struct i2c_client *client)
{
struct lp87565 *lp87565 = i2c_get_clientdata(client);
gpiod_set_value_cansleep(lp87565->reset_gpio, 1);
}
static const struct i2c_device_id lp87565_id_table[] = {
{ "lp87565-q1", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, lp87565_id_table);
static struct i2c_driver lp87565_driver = {
.driver = {
.name = "lp87565",
.of_match_table = of_lp87565_match_table,
},
.probe = lp87565_probe,
.shutdown = lp87565_shutdown,
.id_table = lp87565_id_table,
};
module_i2c_driver(lp87565_driver);
MODULE_AUTHOR("J Keerthy <[email protected]>");
MODULE_DESCRIPTION("lp87565 chip family Multi-Function Device driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/lp87565.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Multifunction core driver for Zodiac Inflight Innovations RAVE
* Supervisory Processor(SP) MCU that is connected via dedicated UART
* port
*
* Copyright (C) 2017 Zodiac Inflight Innovations
*/
#include <linux/atomic.h>
#include <linux/crc-ccitt.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/mfd/rave-sp.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/sched.h>
#include <linux/serdev.h>
#include <asm/unaligned.h>
/*
* UART protocol using following entities:
* - message to MCU => ACK response
* - event from MCU => event ACK
*
* Frame structure:
* <STX> <DATA> <CHECKSUM> <ETX>
* Where:
* - STX - is start of transmission character
* - ETX - end of transmission
* - DATA - payload
* - CHECKSUM - checksum calculated on <DATA>
*
* If <DATA> or <CHECKSUM> contain one of control characters, then it is
* escaped using <DLE> control code. Added <DLE> does not participate in
* checksum calculation.
*/
#define RAVE_SP_STX 0x02
#define RAVE_SP_ETX 0x03
#define RAVE_SP_DLE 0x10
#define RAVE_SP_MAX_DATA_SIZE 64
#define RAVE_SP_CHECKSUM_8B2C 1
#define RAVE_SP_CHECKSUM_CCITT 2
#define RAVE_SP_CHECKSUM_SIZE RAVE_SP_CHECKSUM_CCITT
/*
* We don't store STX, ETX and unescaped bytes, so Rx is only
* DATA + CSUM
*/
#define RAVE_SP_RX_BUFFER_SIZE \
(RAVE_SP_MAX_DATA_SIZE + RAVE_SP_CHECKSUM_SIZE)
#define RAVE_SP_STX_ETX_SIZE 2
/*
* For Tx we have to have space for everything, STX, EXT and
* potentially stuffed DATA + CSUM data + csum
*/
#define RAVE_SP_TX_BUFFER_SIZE \
(RAVE_SP_STX_ETX_SIZE + 2 * RAVE_SP_RX_BUFFER_SIZE)
/**
* enum rave_sp_deframer_state - Possible state for de-framer
*
* @RAVE_SP_EXPECT_SOF: Scanning input for start-of-frame marker
* @RAVE_SP_EXPECT_DATA: Got start of frame marker, collecting frame
* @RAVE_SP_EXPECT_ESCAPED_DATA: Got escape character, collecting escaped byte
*/
enum rave_sp_deframer_state {
RAVE_SP_EXPECT_SOF,
RAVE_SP_EXPECT_DATA,
RAVE_SP_EXPECT_ESCAPED_DATA,
};
/**
* struct rave_sp_deframer - Device protocol deframer
*
* @state: Current state of the deframer
* @data: Buffer used to collect deframed data
* @length: Number of bytes de-framed so far
*/
struct rave_sp_deframer {
enum rave_sp_deframer_state state;
unsigned char data[RAVE_SP_RX_BUFFER_SIZE];
size_t length;
};
/**
* struct rave_sp_reply - Reply as per RAVE device protocol
*
* @length: Expected reply length
* @data: Buffer to store reply payload in
* @code: Expected reply code
* @ackid: Expected reply ACK ID
* @received: Successful reply reception completion
*/
struct rave_sp_reply {
size_t length;
void *data;
u8 code;
u8 ackid;
struct completion received;
};
/**
* struct rave_sp_checksum - Variant specific checksum implementation details
*
* @length: Calculated checksum length
* @subroutine: Utilized checksum algorithm implementation
*/
struct rave_sp_checksum {
size_t length;
void (*subroutine)(const u8 *, size_t, u8 *);
};
struct rave_sp_version {
u8 hardware;
__le16 major;
u8 minor;
u8 letter[2];
} __packed;
struct rave_sp_status {
struct rave_sp_version bootloader_version;
struct rave_sp_version firmware_version;
u16 rdu_eeprom_flag;
u16 dds_eeprom_flag;
u8 pic_flag;
u8 orientation;
u32 etc;
s16 temp[2];
u8 backlight_current[3];
u8 dip_switch;
u8 host_interrupt;
u16 voltage_28;
u8 i2c_device_status;
u8 power_status;
u8 general_status;
u8 deprecated1;
u8 power_led_status;
u8 deprecated2;
u8 periph_power_shutoff;
} __packed;
/**
* struct rave_sp_variant_cmds - Variant specific command routines
*
* @translate: Generic to variant specific command mapping routine
* @get_status: Variant specific implementation of CMD_GET_STATUS
*/
struct rave_sp_variant_cmds {
int (*translate)(enum rave_sp_command);
int (*get_status)(struct rave_sp *sp, struct rave_sp_status *);
};
/**
* struct rave_sp_variant - RAVE supervisory processor core variant
*
* @checksum: Variant specific checksum implementation
* @cmd: Variant specific command pointer table
*
*/
struct rave_sp_variant {
const struct rave_sp_checksum *checksum;
struct rave_sp_variant_cmds cmd;
};
/**
* struct rave_sp - RAVE supervisory processor core
*
* @serdev: Pointer to underlying serdev
* @deframer: Stored state of the protocol deframer
* @ackid: ACK ID used in last reply sent to the device
* @bus_lock: Lock to serialize access to the device
* @reply_lock: Lock protecting @reply
* @reply: Pointer to memory to store reply payload
*
* @variant: Device variant specific information
* @event_notifier_list: Input event notification chain
*
* @part_number_firmware: Firmware version
* @part_number_bootloader: Bootloader version
*/
struct rave_sp {
struct serdev_device *serdev;
struct rave_sp_deframer deframer;
atomic_t ackid;
struct mutex bus_lock;
struct mutex reply_lock;
struct rave_sp_reply *reply;
const struct rave_sp_variant *variant;
struct blocking_notifier_head event_notifier_list;
const char *part_number_firmware;
const char *part_number_bootloader;
};
static bool rave_sp_id_is_event(u8 code)
{
return (code & 0xF0) == RAVE_SP_EVNT_BASE;
}
static void rave_sp_unregister_event_notifier(struct device *dev, void *res)
{
struct rave_sp *sp = dev_get_drvdata(dev->parent);
struct notifier_block *nb = *(struct notifier_block **)res;
struct blocking_notifier_head *bnh = &sp->event_notifier_list;
WARN_ON(blocking_notifier_chain_unregister(bnh, nb));
}
int devm_rave_sp_register_event_notifier(struct device *dev,
struct notifier_block *nb)
{
struct rave_sp *sp = dev_get_drvdata(dev->parent);
struct notifier_block **rcnb;
int ret;
rcnb = devres_alloc(rave_sp_unregister_event_notifier,
sizeof(*rcnb), GFP_KERNEL);
if (!rcnb)
return -ENOMEM;
ret = blocking_notifier_chain_register(&sp->event_notifier_list, nb);
if (!ret) {
*rcnb = nb;
devres_add(dev, rcnb);
} else {
devres_free(rcnb);
}
return ret;
}
EXPORT_SYMBOL_GPL(devm_rave_sp_register_event_notifier);
static void csum_8b2c(const u8 *buf, size_t size, u8 *crc)
{
*crc = *buf++;
size--;
while (size--)
*crc += *buf++;
*crc = 1 + ~(*crc);
}
static void csum_ccitt(const u8 *buf, size_t size, u8 *crc)
{
const u16 calculated = crc_ccitt_false(0xffff, buf, size);
/*
* While the rest of the wire protocol is little-endian,
* CCITT-16 CRC in RDU2 device is sent out in big-endian order.
*/
put_unaligned_be16(calculated, crc);
}
static void *stuff(unsigned char *dest, const unsigned char *src, size_t n)
{
while (n--) {
const unsigned char byte = *src++;
switch (byte) {
case RAVE_SP_STX:
case RAVE_SP_ETX:
case RAVE_SP_DLE:
*dest++ = RAVE_SP_DLE;
fallthrough;
default:
*dest++ = byte;
}
}
return dest;
}
static int rave_sp_write(struct rave_sp *sp, const u8 *data, u8 data_size)
{
const size_t checksum_length = sp->variant->checksum->length;
unsigned char frame[RAVE_SP_TX_BUFFER_SIZE];
unsigned char crc[RAVE_SP_CHECKSUM_SIZE];
unsigned char *dest = frame;
size_t length;
if (WARN_ON(checksum_length > sizeof(crc)))
return -ENOMEM;
if (WARN_ON(data_size > sizeof(frame)))
return -ENOMEM;
sp->variant->checksum->subroutine(data, data_size, crc);
*dest++ = RAVE_SP_STX;
dest = stuff(dest, data, data_size);
dest = stuff(dest, crc, checksum_length);
*dest++ = RAVE_SP_ETX;
length = dest - frame;
print_hex_dump_debug("rave-sp tx: ", DUMP_PREFIX_NONE,
16, 1, frame, length, false);
return serdev_device_write(sp->serdev, frame, length, HZ);
}
static u8 rave_sp_reply_code(u8 command)
{
/*
* There isn't a single rule that describes command code ->
* ACK code transformation, but, going through various
* versions of ICDs, there appear to be three distinct groups
* that can be described by simple transformation.
*/
switch (command) {
case 0xA0 ... 0xBE:
/*
* Commands implemented by firmware found in RDU1 and
* older devices all seem to obey the following rule
*/
return command + 0x20;
case 0xE0 ... 0xEF:
/*
* Events emitted by all versions of the firmare use
* least significant bit to get an ACK code
*/
return command | 0x01;
default:
/*
* Commands implemented by firmware found in RDU2 are
* similar to "old" commands, but they use slightly
* different offset
*/
return command + 0x40;
}
}
int rave_sp_exec(struct rave_sp *sp,
void *__data, size_t data_size,
void *reply_data, size_t reply_data_size)
{
struct rave_sp_reply reply = {
.data = reply_data,
.length = reply_data_size,
.received = COMPLETION_INITIALIZER_ONSTACK(reply.received),
};
unsigned char *data = __data;
int command, ret = 0;
u8 ackid;
command = sp->variant->cmd.translate(data[0]);
if (command < 0)
return command;
ackid = atomic_inc_return(&sp->ackid);
reply.ackid = ackid;
reply.code = rave_sp_reply_code((u8)command),
mutex_lock(&sp->bus_lock);
mutex_lock(&sp->reply_lock);
sp->reply = &reply;
mutex_unlock(&sp->reply_lock);
data[0] = command;
data[1] = ackid;
rave_sp_write(sp, data, data_size);
if (!wait_for_completion_timeout(&reply.received, HZ)) {
dev_err(&sp->serdev->dev, "Command timeout\n");
ret = -ETIMEDOUT;
mutex_lock(&sp->reply_lock);
sp->reply = NULL;
mutex_unlock(&sp->reply_lock);
}
mutex_unlock(&sp->bus_lock);
return ret;
}
EXPORT_SYMBOL_GPL(rave_sp_exec);
static void rave_sp_receive_event(struct rave_sp *sp,
const unsigned char *data, size_t length)
{
u8 cmd[] = {
[0] = rave_sp_reply_code(data[0]),
[1] = data[1],
};
rave_sp_write(sp, cmd, sizeof(cmd));
blocking_notifier_call_chain(&sp->event_notifier_list,
rave_sp_action_pack(data[0], data[2]),
NULL);
}
static void rave_sp_receive_reply(struct rave_sp *sp,
const unsigned char *data, size_t length)
{
struct device *dev = &sp->serdev->dev;
struct rave_sp_reply *reply;
const size_t payload_length = length - 2;
mutex_lock(&sp->reply_lock);
reply = sp->reply;
if (reply) {
if (reply->code == data[0] && reply->ackid == data[1] &&
payload_length >= reply->length) {
/*
* We are relying on memcpy(dst, src, 0) to be a no-op
* when handling commands that have a no-payload reply
*/
memcpy(reply->data, &data[2], reply->length);
complete(&reply->received);
sp->reply = NULL;
} else {
dev_err(dev, "Ignoring incorrect reply\n");
dev_dbg(dev, "Code: expected = 0x%08x received = 0x%08x\n",
reply->code, data[0]);
dev_dbg(dev, "ACK ID: expected = 0x%08x received = 0x%08x\n",
reply->ackid, data[1]);
dev_dbg(dev, "Length: expected = %zu received = %zu\n",
reply->length, payload_length);
}
}
mutex_unlock(&sp->reply_lock);
}
static void rave_sp_receive_frame(struct rave_sp *sp,
const unsigned char *data,
size_t length)
{
const size_t checksum_length = sp->variant->checksum->length;
const size_t payload_length = length - checksum_length;
const u8 *crc_reported = &data[payload_length];
struct device *dev = &sp->serdev->dev;
u8 crc_calculated[RAVE_SP_CHECKSUM_SIZE];
if (unlikely(checksum_length > sizeof(crc_calculated))) {
dev_warn(dev, "Checksum too long, dropping\n");
return;
}
print_hex_dump_debug("rave-sp rx: ", DUMP_PREFIX_NONE,
16, 1, data, length, false);
if (unlikely(length <= checksum_length)) {
dev_warn(dev, "Dropping short frame\n");
return;
}
sp->variant->checksum->subroutine(data, payload_length,
crc_calculated);
if (memcmp(crc_calculated, crc_reported, checksum_length)) {
dev_warn(dev, "Dropping bad frame\n");
return;
}
if (rave_sp_id_is_event(data[0]))
rave_sp_receive_event(sp, data, length);
else
rave_sp_receive_reply(sp, data, length);
}
static int rave_sp_receive_buf(struct serdev_device *serdev,
const unsigned char *buf, size_t size)
{
struct device *dev = &serdev->dev;
struct rave_sp *sp = dev_get_drvdata(dev);
struct rave_sp_deframer *deframer = &sp->deframer;
const unsigned char *src = buf;
const unsigned char *end = buf + size;
while (src < end) {
const unsigned char byte = *src++;
switch (deframer->state) {
case RAVE_SP_EXPECT_SOF:
if (byte == RAVE_SP_STX)
deframer->state = RAVE_SP_EXPECT_DATA;
break;
case RAVE_SP_EXPECT_DATA:
/*
* Treat special byte values first
*/
switch (byte) {
case RAVE_SP_ETX:
rave_sp_receive_frame(sp,
deframer->data,
deframer->length);
/*
* Once we extracted a complete frame
* out of a stream, we call it done
* and proceed to bailing out while
* resetting the framer to initial
* state, regardless if we've consumed
* all of the stream or not.
*/
goto reset_framer;
case RAVE_SP_STX:
dev_warn(dev, "Bad frame: STX before ETX\n");
/*
* If we encounter second "start of
* the frame" marker before seeing
* corresponding "end of frame", we
* reset the framer and ignore both:
* frame started by first SOF and
* frame started by current SOF.
*
* NOTE: The above means that only the
* frame started by third SOF, sent
* after this one will have a chance
* to get throught.
*/
goto reset_framer;
case RAVE_SP_DLE:
deframer->state = RAVE_SP_EXPECT_ESCAPED_DATA;
/*
* If we encounter escape sequence we
* need to skip it and collect the
* byte that follows. We do it by
* forcing the next iteration of the
* encompassing while loop.
*/
continue;
}
/*
* For the rest of the bytes, that are not
* speical snoflakes, we do the same thing
* that we do to escaped data - collect it in
* deframer buffer
*/
fallthrough;
case RAVE_SP_EXPECT_ESCAPED_DATA:
if (deframer->length == sizeof(deframer->data)) {
dev_warn(dev, "Bad frame: Too long\n");
/*
* If the amount of data we've
* accumulated for current frame so
* far starts to exceed the capacity
* of deframer's buffer, there's
* nothing else we can do but to
* discard that data and start
* assemblying a new frame again
*/
goto reset_framer;
}
deframer->data[deframer->length++] = byte;
/*
* We've extracted out special byte, now we
* can go back to regular data collecting
*/
deframer->state = RAVE_SP_EXPECT_DATA;
break;
}
}
/*
* The only way to get out of the above loop and end up here
* is throught consuming all of the supplied data, so here we
* report that we processed it all.
*/
return size;
reset_framer:
/*
* NOTE: A number of codepaths that will drop us here will do
* so before consuming all 'size' bytes of the data passed by
* serdev layer. We rely on the fact that serdev layer will
* re-execute this handler with the remainder of the Rx bytes
* once we report actual number of bytes that we processed.
*/
deframer->state = RAVE_SP_EXPECT_SOF;
deframer->length = 0;
return src - buf;
}
static int rave_sp_rdu1_cmd_translate(enum rave_sp_command command)
{
if (command >= RAVE_SP_CMD_STATUS &&
command <= RAVE_SP_CMD_CONTROL_EVENTS)
return command;
return -EINVAL;
}
static int rave_sp_rdu2_cmd_translate(enum rave_sp_command command)
{
if (command >= RAVE_SP_CMD_GET_FIRMWARE_VERSION &&
command <= RAVE_SP_CMD_GET_GPIO_STATE)
return command;
if (command == RAVE_SP_CMD_REQ_COPPER_REV) {
/*
* As per RDU2 ICD 3.4.47 CMD_GET_COPPER_REV code is
* different from that for RDU1 and it is set to 0x28.
*/
return 0x28;
}
return rave_sp_rdu1_cmd_translate(command);
}
static int rave_sp_default_cmd_translate(enum rave_sp_command command)
{
/*
* All of the following command codes were taken from "Table :
* Communications Protocol Message Types" in section 3.3
* "MESSAGE TYPES" of Rave PIC24 ICD.
*/
switch (command) {
case RAVE_SP_CMD_GET_FIRMWARE_VERSION:
return 0x11;
case RAVE_SP_CMD_GET_BOOTLOADER_VERSION:
return 0x12;
case RAVE_SP_CMD_BOOT_SOURCE:
return 0x14;
case RAVE_SP_CMD_SW_WDT:
return 0x1C;
case RAVE_SP_CMD_PET_WDT:
return 0x1D;
case RAVE_SP_CMD_RESET:
return 0x1E;
case RAVE_SP_CMD_RESET_REASON:
return 0x1F;
case RAVE_SP_CMD_RMB_EEPROM:
return 0x20;
default:
return -EINVAL;
}
}
static const char *devm_rave_sp_version(struct device *dev,
struct rave_sp_version *version)
{
/*
* NOTE: The format string below uses %02d to display u16
* intentionally for the sake of backwards compatibility with
* legacy software.
*/
return devm_kasprintf(dev, GFP_KERNEL, "%02d%02d%02d.%c%c\n",
version->hardware,
le16_to_cpu(version->major),
version->minor,
version->letter[0],
version->letter[1]);
}
static int rave_sp_rdu1_get_status(struct rave_sp *sp,
struct rave_sp_status *status)
{
u8 cmd[] = {
[0] = RAVE_SP_CMD_STATUS,
[1] = 0
};
return rave_sp_exec(sp, cmd, sizeof(cmd), status, sizeof(*status));
}
static int rave_sp_emulated_get_status(struct rave_sp *sp,
struct rave_sp_status *status)
{
u8 cmd[] = {
[0] = RAVE_SP_CMD_GET_FIRMWARE_VERSION,
[1] = 0,
};
int ret;
ret = rave_sp_exec(sp, cmd, sizeof(cmd), &status->firmware_version,
sizeof(status->firmware_version));
if (ret)
return ret;
cmd[0] = RAVE_SP_CMD_GET_BOOTLOADER_VERSION;
return rave_sp_exec(sp, cmd, sizeof(cmd), &status->bootloader_version,
sizeof(status->bootloader_version));
}
static int rave_sp_get_status(struct rave_sp *sp)
{
struct device *dev = &sp->serdev->dev;
struct rave_sp_status status;
const char *version;
int ret;
ret = sp->variant->cmd.get_status(sp, &status);
if (ret)
return ret;
version = devm_rave_sp_version(dev, &status.firmware_version);
if (!version)
return -ENOMEM;
sp->part_number_firmware = version;
version = devm_rave_sp_version(dev, &status.bootloader_version);
if (!version)
return -ENOMEM;
sp->part_number_bootloader = version;
return 0;
}
static const struct rave_sp_checksum rave_sp_checksum_8b2c = {
.length = 1,
.subroutine = csum_8b2c,
};
static const struct rave_sp_checksum rave_sp_checksum_ccitt = {
.length = 2,
.subroutine = csum_ccitt,
};
static const struct rave_sp_variant rave_sp_legacy = {
.checksum = &rave_sp_checksum_ccitt,
.cmd = {
.translate = rave_sp_default_cmd_translate,
.get_status = rave_sp_emulated_get_status,
},
};
static const struct rave_sp_variant rave_sp_rdu1 = {
.checksum = &rave_sp_checksum_8b2c,
.cmd = {
.translate = rave_sp_rdu1_cmd_translate,
.get_status = rave_sp_rdu1_get_status,
},
};
static const struct rave_sp_variant rave_sp_rdu2 = {
.checksum = &rave_sp_checksum_ccitt,
.cmd = {
.translate = rave_sp_rdu2_cmd_translate,
.get_status = rave_sp_emulated_get_status,
},
};
static const struct of_device_id rave_sp_dt_ids[] = {
{ .compatible = "zii,rave-sp-niu", .data = &rave_sp_legacy },
{ .compatible = "zii,rave-sp-mezz", .data = &rave_sp_legacy },
{ .compatible = "zii,rave-sp-esb", .data = &rave_sp_legacy },
{ .compatible = "zii,rave-sp-rdu1", .data = &rave_sp_rdu1 },
{ .compatible = "zii,rave-sp-rdu2", .data = &rave_sp_rdu2 },
{ /* sentinel */ }
};
static const struct serdev_device_ops rave_sp_serdev_device_ops = {
.receive_buf = rave_sp_receive_buf,
.write_wakeup = serdev_device_write_wakeup,
};
static int rave_sp_probe(struct serdev_device *serdev)
{
struct device *dev = &serdev->dev;
const char *unknown = "unknown\n";
struct rave_sp *sp;
u32 baud;
int ret;
if (of_property_read_u32(dev->of_node, "current-speed", &baud)) {
dev_err(dev,
"'current-speed' is not specified in device node\n");
return -EINVAL;
}
sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
if (!sp)
return -ENOMEM;
sp->serdev = serdev;
dev_set_drvdata(dev, sp);
sp->variant = of_device_get_match_data(dev);
if (!sp->variant)
return -ENODEV;
mutex_init(&sp->bus_lock);
mutex_init(&sp->reply_lock);
BLOCKING_INIT_NOTIFIER_HEAD(&sp->event_notifier_list);
serdev_device_set_client_ops(serdev, &rave_sp_serdev_device_ops);
ret = devm_serdev_device_open(dev, serdev);
if (ret)
return ret;
serdev_device_set_baudrate(serdev, baud);
serdev_device_set_flow_control(serdev, false);
ret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE);
if (ret) {
dev_err(dev, "Failed to set parity\n");
return ret;
}
ret = rave_sp_get_status(sp);
if (ret) {
dev_warn(dev, "Failed to get firmware status: %d\n", ret);
sp->part_number_firmware = unknown;
sp->part_number_bootloader = unknown;
}
/*
* Those strings already have a \n embedded, so there's no
* need to have one in format string.
*/
dev_info(dev, "Firmware version: %s", sp->part_number_firmware);
dev_info(dev, "Bootloader version: %s", sp->part_number_bootloader);
return devm_of_platform_populate(dev);
}
MODULE_DEVICE_TABLE(of, rave_sp_dt_ids);
static struct serdev_device_driver rave_sp_drv = {
.probe = rave_sp_probe,
.driver = {
.name = "rave-sp",
.of_match_table = rave_sp_dt_ids,
},
};
module_serdev_device_driver(rave_sp_drv);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Andrey Vostrikov <[email protected]>");
MODULE_AUTHOR("Nikita Yushchenko <[email protected]>");
MODULE_AUTHOR("Andrey Smirnov <[email protected]>");
MODULE_DESCRIPTION("RAVE SP core driver");
| linux-master | drivers/mfd/rave-sp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Hanumath Prasad <[email protected]> for ST-Ericsson
* Author: Rabin Vincent <[email protected]> for ST-Ericsson
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tc3589x.h>
#include <linux/err.h>
/*
* enum tc3589x_version - indicates the TC3589x version
*/
enum tc3589x_version {
TC3589X_TC35890,
TC3589X_TC35892,
TC3589X_TC35893,
TC3589X_TC35894,
TC3589X_TC35895,
TC3589X_TC35896,
TC3589X_UNKNOWN,
};
#define TC3589x_CLKMODE_MODCTL_SLEEP 0x0
#define TC3589x_CLKMODE_MODCTL_OPERATION (1 << 0)
/**
* tc3589x_reg_read() - read a single TC3589x register
* @tc3589x: Device to read from
* @reg: Register to read
*/
int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg)
{
int ret;
ret = i2c_smbus_read_byte_data(tc3589x->i2c, reg);
if (ret < 0)
dev_err(tc3589x->dev, "failed to read reg %#x: %d\n",
reg, ret);
return ret;
}
EXPORT_SYMBOL_GPL(tc3589x_reg_read);
/**
* tc3589x_reg_write() - write a single TC3589x register
* @tc3589x: Device to write to
* @reg: Register to read
* @data: Value to write
*/
int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data)
{
int ret;
ret = i2c_smbus_write_byte_data(tc3589x->i2c, reg, data);
if (ret < 0)
dev_err(tc3589x->dev, "failed to write reg %#x: %d\n",
reg, ret);
return ret;
}
EXPORT_SYMBOL_GPL(tc3589x_reg_write);
/**
* tc3589x_block_read() - read multiple TC3589x registers
* @tc3589x: Device to read from
* @reg: First register
* @length: Number of registers
* @values: Buffer to write to
*/
int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length, u8 *values)
{
int ret;
ret = i2c_smbus_read_i2c_block_data(tc3589x->i2c, reg, length, values);
if (ret < 0)
dev_err(tc3589x->dev, "failed to read regs %#x: %d\n",
reg, ret);
return ret;
}
EXPORT_SYMBOL_GPL(tc3589x_block_read);
/**
* tc3589x_block_write() - write multiple TC3589x registers
* @tc3589x: Device to write to
* @reg: First register
* @length: Number of registers
* @values: Values to write
*/
int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length,
const u8 *values)
{
int ret;
ret = i2c_smbus_write_i2c_block_data(tc3589x->i2c, reg, length,
values);
if (ret < 0)
dev_err(tc3589x->dev, "failed to write regs %#x: %d\n",
reg, ret);
return ret;
}
EXPORT_SYMBOL_GPL(tc3589x_block_write);
/**
* tc3589x_set_bits() - set the value of a bitfield in a TC3589x register
* @tc3589x: Device to write to
* @reg: Register to write
* @mask: Mask of bits to set
* @val: Value to set
*/
int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val)
{
int ret;
mutex_lock(&tc3589x->lock);
ret = tc3589x_reg_read(tc3589x, reg);
if (ret < 0)
goto out;
ret &= ~mask;
ret |= val;
ret = tc3589x_reg_write(tc3589x, reg, ret);
out:
mutex_unlock(&tc3589x->lock);
return ret;
}
EXPORT_SYMBOL_GPL(tc3589x_set_bits);
static const struct resource gpio_resources[] = {
{
.start = TC3589x_INT_GPIIRQ,
.end = TC3589x_INT_GPIIRQ,
.flags = IORESOURCE_IRQ,
},
};
static const struct resource keypad_resources[] = {
{
.start = TC3589x_INT_KBDIRQ,
.end = TC3589x_INT_KBDIRQ,
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell tc3589x_dev_gpio[] = {
{
.name = "tc3589x-gpio",
.num_resources = ARRAY_SIZE(gpio_resources),
.resources = &gpio_resources[0],
.of_compatible = "toshiba,tc3589x-gpio",
},
};
static const struct mfd_cell tc3589x_dev_keypad[] = {
{
.name = "tc3589x-keypad",
.num_resources = ARRAY_SIZE(keypad_resources),
.resources = &keypad_resources[0],
.of_compatible = "toshiba,tc3589x-keypad",
},
};
static irqreturn_t tc3589x_irq(int irq, void *data)
{
struct tc3589x *tc3589x = data;
int status;
again:
status = tc3589x_reg_read(tc3589x, TC3589x_IRQST);
if (status < 0)
return IRQ_NONE;
while (status) {
int bit = __ffs(status);
int virq = irq_find_mapping(tc3589x->domain, bit);
handle_nested_irq(virq);
status &= ~(1 << bit);
}
/*
* A dummy read or write (to any register) appears to be necessary to
* have the last interrupt clear (for example, GPIO IC write) take
* effect. In such a case, recheck for any interrupt which is still
* pending.
*/
status = tc3589x_reg_read(tc3589x, TC3589x_IRQST);
if (status)
goto again;
return IRQ_HANDLED;
}
static int tc3589x_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hwirq)
{
struct tc3589x *tc3589x = d->host_data;
irq_set_chip_data(virq, tc3589x);
irq_set_chip_and_handler(virq, &dummy_irq_chip,
handle_edge_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static void tc3589x_irq_unmap(struct irq_domain *d, unsigned int virq)
{
irq_set_chip_and_handler(virq, NULL, NULL);
irq_set_chip_data(virq, NULL);
}
static const struct irq_domain_ops tc3589x_irq_ops = {
.map = tc3589x_irq_map,
.unmap = tc3589x_irq_unmap,
.xlate = irq_domain_xlate_onecell,
};
static int tc3589x_irq_init(struct tc3589x *tc3589x, struct device_node *np)
{
tc3589x->domain = irq_domain_add_simple(
np, TC3589x_NR_INTERNAL_IRQS, 0,
&tc3589x_irq_ops, tc3589x);
if (!tc3589x->domain) {
dev_err(tc3589x->dev, "Failed to create irqdomain\n");
return -ENOSYS;
}
return 0;
}
static int tc3589x_chip_init(struct tc3589x *tc3589x)
{
int manf, ver, ret;
manf = tc3589x_reg_read(tc3589x, TC3589x_MANFCODE);
if (manf < 0)
return manf;
ver = tc3589x_reg_read(tc3589x, TC3589x_VERSION);
if (ver < 0)
return ver;
if (manf != TC3589x_MANFCODE_MAGIC) {
dev_err(tc3589x->dev, "unknown manufacturer: %#x\n", manf);
return -EINVAL;
}
dev_info(tc3589x->dev, "manufacturer: %#x, version: %#x\n", manf, ver);
/*
* Put everything except the IRQ module into reset;
* also spare the GPIO module for any pin initialization
* done during pre-kernel boot
*/
ret = tc3589x_reg_write(tc3589x, TC3589x_RSTCTRL,
TC3589x_RSTCTRL_TIMRST
| TC3589x_RSTCTRL_ROTRST
| TC3589x_RSTCTRL_KBDRST);
if (ret < 0)
return ret;
/* Clear the reset interrupt. */
return tc3589x_reg_write(tc3589x, TC3589x_RSTINTCLR, 0x1);
}
static int tc3589x_device_init(struct tc3589x *tc3589x)
{
int ret = 0;
unsigned int blocks = tc3589x->pdata->block;
if (blocks & TC3589x_BLOCK_GPIO) {
ret = mfd_add_devices(tc3589x->dev, -1, tc3589x_dev_gpio,
ARRAY_SIZE(tc3589x_dev_gpio), NULL,
0, tc3589x->domain);
if (ret) {
dev_err(tc3589x->dev, "failed to add gpio child\n");
return ret;
}
dev_info(tc3589x->dev, "added gpio block\n");
}
if (blocks & TC3589x_BLOCK_KEYPAD) {
ret = mfd_add_devices(tc3589x->dev, -1, tc3589x_dev_keypad,
ARRAY_SIZE(tc3589x_dev_keypad), NULL,
0, tc3589x->domain);
if (ret) {
dev_err(tc3589x->dev, "failed to keypad child\n");
return ret;
}
dev_info(tc3589x->dev, "added keypad block\n");
}
return ret;
}
static const struct of_device_id tc3589x_match[] = {
/* Legacy compatible string */
{ .compatible = "tc3589x", .data = (void *) TC3589X_UNKNOWN },
{ .compatible = "toshiba,tc35890", .data = (void *) TC3589X_TC35890 },
{ .compatible = "toshiba,tc35892", .data = (void *) TC3589X_TC35892 },
{ .compatible = "toshiba,tc35893", .data = (void *) TC3589X_TC35893 },
{ .compatible = "toshiba,tc35894", .data = (void *) TC3589X_TC35894 },
{ .compatible = "toshiba,tc35895", .data = (void *) TC3589X_TC35895 },
{ .compatible = "toshiba,tc35896", .data = (void *) TC3589X_TC35896 },
{ }
};
MODULE_DEVICE_TABLE(of, tc3589x_match);
static struct tc3589x_platform_data *
tc3589x_of_probe(struct device *dev, enum tc3589x_version *version)
{
struct device_node *np = dev->of_node;
struct tc3589x_platform_data *pdata;
struct device_node *child;
const struct of_device_id *of_id;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return ERR_PTR(-ENOMEM);
of_id = of_match_device(tc3589x_match, dev);
if (!of_id)
return ERR_PTR(-ENODEV);
*version = (uintptr_t) of_id->data;
for_each_child_of_node(np, child) {
if (of_device_is_compatible(child, "toshiba,tc3589x-gpio"))
pdata->block |= TC3589x_BLOCK_GPIO;
if (of_device_is_compatible(child, "toshiba,tc3589x-keypad"))
pdata->block |= TC3589x_BLOCK_KEYPAD;
}
return pdata;
}
static int tc3589x_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct device_node *np = i2c->dev.of_node;
struct tc3589x_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct tc3589x *tc3589x;
enum tc3589x_version version;
int ret;
if (!pdata) {
pdata = tc3589x_of_probe(&i2c->dev, &version);
if (IS_ERR(pdata)) {
dev_err(&i2c->dev, "No platform data or DT found\n");
return PTR_ERR(pdata);
}
} else {
/* When not probing from device tree we have this ID */
version = id->driver_data;
}
if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_I2C_BLOCK))
return -EIO;
tc3589x = devm_kzalloc(&i2c->dev, sizeof(struct tc3589x),
GFP_KERNEL);
if (!tc3589x)
return -ENOMEM;
mutex_init(&tc3589x->lock);
tc3589x->dev = &i2c->dev;
tc3589x->i2c = i2c;
tc3589x->pdata = pdata;
switch (version) {
case TC3589X_TC35893:
case TC3589X_TC35895:
case TC3589X_TC35896:
tc3589x->num_gpio = 20;
break;
case TC3589X_TC35890:
case TC3589X_TC35892:
case TC3589X_TC35894:
case TC3589X_UNKNOWN:
default:
tc3589x->num_gpio = 24;
break;
}
i2c_set_clientdata(i2c, tc3589x);
ret = tc3589x_chip_init(tc3589x);
if (ret)
return ret;
ret = tc3589x_irq_init(tc3589x, np);
if (ret)
return ret;
ret = request_threaded_irq(tc3589x->i2c->irq, NULL, tc3589x_irq,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"tc3589x", tc3589x);
if (ret) {
dev_err(tc3589x->dev, "failed to request IRQ: %d\n", ret);
return ret;
}
ret = tc3589x_device_init(tc3589x);
if (ret) {
dev_err(tc3589x->dev, "failed to add child devices\n");
return ret;
}
return 0;
}
static void tc3589x_remove(struct i2c_client *client)
{
struct tc3589x *tc3589x = i2c_get_clientdata(client);
mfd_remove_devices(tc3589x->dev);
}
static int tc3589x_suspend(struct device *dev)
{
struct tc3589x *tc3589x = dev_get_drvdata(dev);
struct i2c_client *client = tc3589x->i2c;
int ret = 0;
/* put the system to sleep mode */
if (!device_may_wakeup(&client->dev))
ret = tc3589x_reg_write(tc3589x, TC3589x_CLKMODE,
TC3589x_CLKMODE_MODCTL_SLEEP);
return ret;
}
static int tc3589x_resume(struct device *dev)
{
struct tc3589x *tc3589x = dev_get_drvdata(dev);
struct i2c_client *client = tc3589x->i2c;
int ret = 0;
/* enable the system into operation */
if (!device_may_wakeup(&client->dev))
ret = tc3589x_reg_write(tc3589x, TC3589x_CLKMODE,
TC3589x_CLKMODE_MODCTL_OPERATION);
return ret;
}
static DEFINE_SIMPLE_DEV_PM_OPS(tc3589x_dev_pm_ops,
tc3589x_suspend, tc3589x_resume);
static const struct i2c_device_id tc3589x_id[] = {
{ "tc35890", TC3589X_TC35890 },
{ "tc35892", TC3589X_TC35892 },
{ "tc35893", TC3589X_TC35893 },
{ "tc35894", TC3589X_TC35894 },
{ "tc35895", TC3589X_TC35895 },
{ "tc35896", TC3589X_TC35896 },
{ "tc3589x", TC3589X_UNKNOWN },
{ }
};
MODULE_DEVICE_TABLE(i2c, tc3589x_id);
static struct i2c_driver tc3589x_driver = {
.driver = {
.name = "tc3589x",
.pm = pm_sleep_ptr(&tc3589x_dev_pm_ops),
.of_match_table = tc3589x_match,
},
.probe = tc3589x_probe,
.remove = tc3589x_remove,
.id_table = tc3589x_id,
};
static int __init tc3589x_init(void)
{
return i2c_add_driver(&tc3589x_driver);
}
subsys_initcall(tc3589x_init);
static void __exit tc3589x_exit(void)
{
i2c_del_driver(&tc3589x_driver);
}
module_exit(tc3589x_exit);
MODULE_DESCRIPTION("TC3589x MFD core driver");
MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");
| linux-master | drivers/mfd/tc3589x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core driver for TI TPS6586x PMIC family
*
* Copyright (c) 2010 CompuLab Ltd.
* Mike Rapoport <[email protected]>
*
* Based on da903x.c.
* Copyright (C) 2008 Compulab, Ltd.
* Mike Rapoport <[email protected]>
* Copyright (C) 2006-2008 Marvell International Ltd.
* Eric Miao <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps6586x.h>
#define TPS6586X_SUPPLYENE 0x14
#define EXITSLREQ_BIT BIT(1)
#define SLEEP_MODE_BIT BIT(3)
/* interrupt control registers */
#define TPS6586X_INT_ACK1 0xb5
#define TPS6586X_INT_ACK2 0xb6
#define TPS6586X_INT_ACK3 0xb7
#define TPS6586X_INT_ACK4 0xb8
/* interrupt mask registers */
#define TPS6586X_INT_MASK1 0xb0
#define TPS6586X_INT_MASK2 0xb1
#define TPS6586X_INT_MASK3 0xb2
#define TPS6586X_INT_MASK4 0xb3
#define TPS6586X_INT_MASK5 0xb4
/* device id */
#define TPS6586X_VERSIONCRC 0xcd
/* Maximum register */
#define TPS6586X_MAX_REGISTER TPS6586X_VERSIONCRC
struct tps6586x_irq_data {
u8 mask_reg;
u8 mask_mask;
};
#define TPS6586X_IRQ(_reg, _mask) \
{ \
.mask_reg = (_reg) - TPS6586X_INT_MASK1, \
.mask_mask = (_mask), \
}
static const struct tps6586x_irq_data tps6586x_irqs[] = {
[TPS6586X_INT_PLDO_0] = TPS6586X_IRQ(TPS6586X_INT_MASK1, 1 << 0),
[TPS6586X_INT_PLDO_1] = TPS6586X_IRQ(TPS6586X_INT_MASK1, 1 << 1),
[TPS6586X_INT_PLDO_2] = TPS6586X_IRQ(TPS6586X_INT_MASK1, 1 << 2),
[TPS6586X_INT_PLDO_3] = TPS6586X_IRQ(TPS6586X_INT_MASK1, 1 << 3),
[TPS6586X_INT_PLDO_4] = TPS6586X_IRQ(TPS6586X_INT_MASK1, 1 << 4),
[TPS6586X_INT_PLDO_5] = TPS6586X_IRQ(TPS6586X_INT_MASK1, 1 << 5),
[TPS6586X_INT_PLDO_6] = TPS6586X_IRQ(TPS6586X_INT_MASK1, 1 << 6),
[TPS6586X_INT_PLDO_7] = TPS6586X_IRQ(TPS6586X_INT_MASK1, 1 << 7),
[TPS6586X_INT_COMP_DET] = TPS6586X_IRQ(TPS6586X_INT_MASK4, 1 << 0),
[TPS6586X_INT_ADC] = TPS6586X_IRQ(TPS6586X_INT_MASK2, 1 << 1),
[TPS6586X_INT_PLDO_8] = TPS6586X_IRQ(TPS6586X_INT_MASK2, 1 << 2),
[TPS6586X_INT_PLDO_9] = TPS6586X_IRQ(TPS6586X_INT_MASK2, 1 << 3),
[TPS6586X_INT_PSM_0] = TPS6586X_IRQ(TPS6586X_INT_MASK2, 1 << 4),
[TPS6586X_INT_PSM_1] = TPS6586X_IRQ(TPS6586X_INT_MASK2, 1 << 5),
[TPS6586X_INT_PSM_2] = TPS6586X_IRQ(TPS6586X_INT_MASK2, 1 << 6),
[TPS6586X_INT_PSM_3] = TPS6586X_IRQ(TPS6586X_INT_MASK2, 1 << 7),
[TPS6586X_INT_RTC_ALM1] = TPS6586X_IRQ(TPS6586X_INT_MASK5, 1 << 4),
[TPS6586X_INT_ACUSB_OVP] = TPS6586X_IRQ(TPS6586X_INT_MASK5, 0x03),
[TPS6586X_INT_USB_DET] = TPS6586X_IRQ(TPS6586X_INT_MASK5, 1 << 2),
[TPS6586X_INT_AC_DET] = TPS6586X_IRQ(TPS6586X_INT_MASK5, 1 << 3),
[TPS6586X_INT_BAT_DET] = TPS6586X_IRQ(TPS6586X_INT_MASK3, 1 << 0),
[TPS6586X_INT_CHG_STAT] = TPS6586X_IRQ(TPS6586X_INT_MASK4, 0xfc),
[TPS6586X_INT_CHG_TEMP] = TPS6586X_IRQ(TPS6586X_INT_MASK3, 0x06),
[TPS6586X_INT_PP] = TPS6586X_IRQ(TPS6586X_INT_MASK3, 0xf0),
[TPS6586X_INT_RESUME] = TPS6586X_IRQ(TPS6586X_INT_MASK5, 1 << 5),
[TPS6586X_INT_LOW_SYS] = TPS6586X_IRQ(TPS6586X_INT_MASK5, 1 << 6),
[TPS6586X_INT_RTC_ALM2] = TPS6586X_IRQ(TPS6586X_INT_MASK4, 1 << 1),
};
static const struct resource tps6586x_rtc_resources[] = {
{
.start = TPS6586X_INT_RTC_ALM1,
.end = TPS6586X_INT_RTC_ALM1,
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell tps6586x_cell[] = {
{
.name = "tps6586x-gpio",
},
{
.name = "tps6586x-regulator",
},
{
.name = "tps6586x-rtc",
.num_resources = ARRAY_SIZE(tps6586x_rtc_resources),
.resources = &tps6586x_rtc_resources[0],
},
{
.name = "tps6586x-onkey",
},
};
struct tps6586x {
struct device *dev;
struct i2c_client *client;
struct regmap *regmap;
int version;
int irq;
struct irq_chip irq_chip;
struct mutex irq_lock;
int irq_base;
u32 irq_en;
u8 mask_reg[5];
struct irq_domain *irq_domain;
};
static inline struct tps6586x *dev_to_tps6586x(struct device *dev)
{
return i2c_get_clientdata(to_i2c_client(dev));
}
int tps6586x_write(struct device *dev, int reg, uint8_t val)
{
struct tps6586x *tps6586x = dev_to_tps6586x(dev);
return regmap_write(tps6586x->regmap, reg, val);
}
EXPORT_SYMBOL_GPL(tps6586x_write);
int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val)
{
struct tps6586x *tps6586x = dev_to_tps6586x(dev);
return regmap_bulk_write(tps6586x->regmap, reg, val, len);
}
EXPORT_SYMBOL_GPL(tps6586x_writes);
int tps6586x_read(struct device *dev, int reg, uint8_t *val)
{
struct tps6586x *tps6586x = dev_to_tps6586x(dev);
unsigned int rval;
int ret;
ret = regmap_read(tps6586x->regmap, reg, &rval);
if (!ret)
*val = rval;
return ret;
}
EXPORT_SYMBOL_GPL(tps6586x_read);
int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val)
{
struct tps6586x *tps6586x = dev_to_tps6586x(dev);
return regmap_bulk_read(tps6586x->regmap, reg, val, len);
}
EXPORT_SYMBOL_GPL(tps6586x_reads);
int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask)
{
struct tps6586x *tps6586x = dev_to_tps6586x(dev);
return regmap_update_bits(tps6586x->regmap, reg, bit_mask, bit_mask);
}
EXPORT_SYMBOL_GPL(tps6586x_set_bits);
int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask)
{
struct tps6586x *tps6586x = dev_to_tps6586x(dev);
return regmap_update_bits(tps6586x->regmap, reg, bit_mask, 0);
}
EXPORT_SYMBOL_GPL(tps6586x_clr_bits);
int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask)
{
struct tps6586x *tps6586x = dev_to_tps6586x(dev);
return regmap_update_bits(tps6586x->regmap, reg, mask, val);
}
EXPORT_SYMBOL_GPL(tps6586x_update);
int tps6586x_irq_get_virq(struct device *dev, int irq)
{
struct tps6586x *tps6586x = dev_to_tps6586x(dev);
return irq_create_mapping(tps6586x->irq_domain, irq);
}
EXPORT_SYMBOL_GPL(tps6586x_irq_get_virq);
int tps6586x_get_version(struct device *dev)
{
struct tps6586x *tps6586x = dev_get_drvdata(dev);
return tps6586x->version;
}
EXPORT_SYMBOL_GPL(tps6586x_get_version);
static int __remove_subdev(struct device *dev, void *unused)
{
platform_device_unregister(to_platform_device(dev));
return 0;
}
static int tps6586x_remove_subdevs(struct tps6586x *tps6586x)
{
return device_for_each_child(tps6586x->dev, NULL, __remove_subdev);
}
static void tps6586x_irq_lock(struct irq_data *data)
{
struct tps6586x *tps6586x = irq_data_get_irq_chip_data(data);
mutex_lock(&tps6586x->irq_lock);
}
static void tps6586x_irq_enable(struct irq_data *irq_data)
{
struct tps6586x *tps6586x = irq_data_get_irq_chip_data(irq_data);
unsigned int __irq = irq_data->hwirq;
const struct tps6586x_irq_data *data = &tps6586x_irqs[__irq];
tps6586x->mask_reg[data->mask_reg] &= ~data->mask_mask;
tps6586x->irq_en |= (1 << __irq);
}
static void tps6586x_irq_disable(struct irq_data *irq_data)
{
struct tps6586x *tps6586x = irq_data_get_irq_chip_data(irq_data);
unsigned int __irq = irq_data->hwirq;
const struct tps6586x_irq_data *data = &tps6586x_irqs[__irq];
tps6586x->mask_reg[data->mask_reg] |= data->mask_mask;
tps6586x->irq_en &= ~(1 << __irq);
}
static void tps6586x_irq_sync_unlock(struct irq_data *data)
{
struct tps6586x *tps6586x = irq_data_get_irq_chip_data(data);
int i;
for (i = 0; i < ARRAY_SIZE(tps6586x->mask_reg); i++) {
int ret;
ret = tps6586x_write(tps6586x->dev,
TPS6586X_INT_MASK1 + i,
tps6586x->mask_reg[i]);
WARN_ON(ret);
}
mutex_unlock(&tps6586x->irq_lock);
}
static int tps6586x_irq_set_wake(struct irq_data *irq_data, unsigned int on)
{
struct tps6586x *tps6586x = irq_data_get_irq_chip_data(irq_data);
return irq_set_irq_wake(tps6586x->irq, on);
}
static struct irq_chip tps6586x_irq_chip = {
.name = "tps6586x",
.irq_bus_lock = tps6586x_irq_lock,
.irq_bus_sync_unlock = tps6586x_irq_sync_unlock,
.irq_disable = tps6586x_irq_disable,
.irq_enable = tps6586x_irq_enable,
.irq_set_wake = pm_sleep_ptr(tps6586x_irq_set_wake),
};
static int tps6586x_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct tps6586x *tps6586x = h->host_data;
irq_set_chip_data(virq, tps6586x);
irq_set_chip_and_handler(virq, &tps6586x_irq_chip, handle_simple_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops tps6586x_domain_ops = {
.map = tps6586x_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static irqreturn_t tps6586x_irq(int irq, void *data)
{
struct tps6586x *tps6586x = data;
uint32_t acks;
__le32 val;
int ret = 0;
ret = tps6586x_reads(tps6586x->dev, TPS6586X_INT_ACK1,
sizeof(acks), (uint8_t *)&val);
if (ret < 0) {
dev_err(tps6586x->dev, "failed to read interrupt status\n");
return IRQ_NONE;
}
acks = le32_to_cpu(val);
while (acks) {
int i = __ffs(acks);
if (tps6586x->irq_en & (1 << i))
handle_nested_irq(
irq_find_mapping(tps6586x->irq_domain, i));
acks &= ~(1 << i);
}
return IRQ_HANDLED;
}
static int tps6586x_irq_init(struct tps6586x *tps6586x, int irq,
int irq_base)
{
int i, ret;
u8 tmp[4];
int new_irq_base;
int irq_num = ARRAY_SIZE(tps6586x_irqs);
tps6586x->irq = irq;
mutex_init(&tps6586x->irq_lock);
for (i = 0; i < 5; i++) {
tps6586x->mask_reg[i] = 0xff;
tps6586x_write(tps6586x->dev, TPS6586X_INT_MASK1 + i, 0xff);
}
tps6586x_reads(tps6586x->dev, TPS6586X_INT_ACK1, sizeof(tmp), tmp);
if (irq_base > 0) {
new_irq_base = irq_alloc_descs(irq_base, 0, irq_num, -1);
if (new_irq_base < 0) {
dev_err(tps6586x->dev,
"Failed to alloc IRQs: %d\n", new_irq_base);
return new_irq_base;
}
} else {
new_irq_base = 0;
}
tps6586x->irq_domain = irq_domain_add_simple(tps6586x->dev->of_node,
irq_num, new_irq_base, &tps6586x_domain_ops,
tps6586x);
if (!tps6586x->irq_domain) {
dev_err(tps6586x->dev, "Failed to create IRQ domain\n");
return -ENOMEM;
}
ret = request_threaded_irq(irq, NULL, tps6586x_irq, IRQF_ONESHOT,
"tps6586x", tps6586x);
if (!ret)
device_init_wakeup(tps6586x->dev, 1);
return ret;
}
static int tps6586x_add_subdevs(struct tps6586x *tps6586x,
struct tps6586x_platform_data *pdata)
{
struct tps6586x_subdev_info *subdev;
struct platform_device *pdev;
int i, ret = 0;
for (i = 0; i < pdata->num_subdevs; i++) {
subdev = &pdata->subdevs[i];
pdev = platform_device_alloc(subdev->name, subdev->id);
if (!pdev) {
ret = -ENOMEM;
goto failed;
}
pdev->dev.parent = tps6586x->dev;
pdev->dev.platform_data = subdev->platform_data;
pdev->dev.of_node = subdev->of_node;
ret = platform_device_add(pdev);
if (ret) {
platform_device_put(pdev);
goto failed;
}
}
return 0;
failed:
tps6586x_remove_subdevs(tps6586x);
return ret;
}
#ifdef CONFIG_OF
static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *client)
{
struct device_node *np = client->dev.of_node;
struct tps6586x_platform_data *pdata;
pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return NULL;
pdata->num_subdevs = 0;
pdata->subdevs = NULL;
pdata->gpio_base = -1;
pdata->irq_base = -1;
pdata->pm_off = of_property_read_bool(np, "ti,system-power-controller");
return pdata;
}
static const struct of_device_id tps6586x_of_match[] = {
{ .compatible = "ti,tps6586x", },
{ },
};
#else
static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *client)
{
return NULL;
}
#endif
static bool is_volatile_reg(struct device *dev, unsigned int reg)
{
/* Cache all interrupt mask register */
if ((reg >= TPS6586X_INT_MASK1) && (reg <= TPS6586X_INT_MASK5))
return false;
return true;
}
static const struct regmap_config tps6586x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TPS6586X_MAX_REGISTER,
.volatile_reg = is_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static struct device *tps6586x_dev;
static void tps6586x_power_off(void)
{
if (tps6586x_clr_bits(tps6586x_dev, TPS6586X_SUPPLYENE, EXITSLREQ_BIT))
return;
tps6586x_set_bits(tps6586x_dev, TPS6586X_SUPPLYENE, SLEEP_MODE_BIT);
}
static void tps6586x_print_version(struct i2c_client *client, int version)
{
const char *name;
switch (version) {
case TPS658621A:
name = "TPS658621A";
break;
case TPS658621CD:
name = "TPS658621C/D";
break;
case TPS658623:
name = "TPS658623";
break;
case TPS658640:
case TPS658640v2:
name = "TPS658640";
break;
case TPS658643:
name = "TPS658643";
break;
default:
name = "TPS6586X";
break;
}
dev_info(&client->dev, "Found %s, VERSIONCRC is %02x\n", name, version);
}
static int tps6586x_i2c_probe(struct i2c_client *client)
{
struct tps6586x_platform_data *pdata = dev_get_platdata(&client->dev);
struct tps6586x *tps6586x;
int ret;
int version;
if (!pdata && client->dev.of_node)
pdata = tps6586x_parse_dt(client);
if (!pdata) {
dev_err(&client->dev, "tps6586x requires platform data\n");
return -ENOTSUPP;
}
version = i2c_smbus_read_byte_data(client, TPS6586X_VERSIONCRC);
if (version < 0) {
dev_err(&client->dev, "Chip ID read failed: %d\n", version);
return -EIO;
}
tps6586x = devm_kzalloc(&client->dev, sizeof(*tps6586x), GFP_KERNEL);
if (!tps6586x)
return -ENOMEM;
tps6586x->version = version;
tps6586x_print_version(client, tps6586x->version);
tps6586x->client = client;
tps6586x->dev = &client->dev;
i2c_set_clientdata(client, tps6586x);
tps6586x->regmap = devm_regmap_init_i2c(client,
&tps6586x_regmap_config);
if (IS_ERR(tps6586x->regmap)) {
ret = PTR_ERR(tps6586x->regmap);
dev_err(&client->dev, "regmap init failed: %d\n", ret);
return ret;
}
if (client->irq) {
ret = tps6586x_irq_init(tps6586x, client->irq,
pdata->irq_base);
if (ret) {
dev_err(&client->dev, "IRQ init failed: %d\n", ret);
return ret;
}
}
ret = mfd_add_devices(tps6586x->dev, -1,
tps6586x_cell, ARRAY_SIZE(tps6586x_cell),
NULL, 0, tps6586x->irq_domain);
if (ret < 0) {
dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret);
goto err_mfd_add;
}
ret = tps6586x_add_subdevs(tps6586x, pdata);
if (ret) {
dev_err(&client->dev, "add devices failed: %d\n", ret);
goto err_add_devs;
}
if (pdata->pm_off && !pm_power_off) {
tps6586x_dev = &client->dev;
pm_power_off = tps6586x_power_off;
}
return 0;
err_add_devs:
mfd_remove_devices(tps6586x->dev);
err_mfd_add:
if (client->irq)
free_irq(client->irq, tps6586x);
return ret;
}
static void tps6586x_i2c_remove(struct i2c_client *client)
{
struct tps6586x *tps6586x = i2c_get_clientdata(client);
tps6586x_remove_subdevs(tps6586x);
mfd_remove_devices(tps6586x->dev);
if (client->irq)
free_irq(client->irq, tps6586x);
}
static int __maybe_unused tps6586x_i2c_suspend(struct device *dev)
{
struct tps6586x *tps6586x = dev_get_drvdata(dev);
if (tps6586x->client->irq)
disable_irq(tps6586x->client->irq);
return 0;
}
static int __maybe_unused tps6586x_i2c_resume(struct device *dev)
{
struct tps6586x *tps6586x = dev_get_drvdata(dev);
if (tps6586x->client->irq)
enable_irq(tps6586x->client->irq);
return 0;
}
static SIMPLE_DEV_PM_OPS(tps6586x_pm_ops, tps6586x_i2c_suspend,
tps6586x_i2c_resume);
static const struct i2c_device_id tps6586x_id_table[] = {
{ "tps6586x", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, tps6586x_id_table);
static struct i2c_driver tps6586x_driver = {
.driver = {
.name = "tps6586x",
.of_match_table = of_match_ptr(tps6586x_of_match),
.pm = &tps6586x_pm_ops,
},
.probe = tps6586x_i2c_probe,
.remove = tps6586x_i2c_remove,
.id_table = tps6586x_id_table,
};
static int __init tps6586x_init(void)
{
return i2c_add_driver(&tps6586x_driver);
}
subsys_initcall(tps6586x_init);
static void __exit tps6586x_exit(void)
{
i2c_del_driver(&tps6586x_driver);
}
module_exit(tps6586x_exit);
MODULE_DESCRIPTION("TPS6586X core driver");
MODULE_AUTHOR("Mike Rapoport <[email protected]>");
| linux-master | drivers/mfd/tps6586x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Core driver for WM8400.
*
* Copyright 2008 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/init.h>
#include <linux/bug.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/wm8400-private.h>
#include <linux/mfd/wm8400-audio.h>
#include <linux/regmap.h>
#include <linux/slab.h>
static bool wm8400_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8400_INTERRUPT_STATUS_1:
case WM8400_INTERRUPT_LEVELS:
case WM8400_SHUTDOWN_REASON:
return true;
default:
return false;
}
}
static int wm8400_register_codec(struct wm8400 *wm8400)
{
const struct mfd_cell cell = {
.name = "wm8400-codec",
.platform_data = wm8400,
.pdata_size = sizeof(*wm8400),
};
return devm_mfd_add_devices(wm8400->dev, -1, &cell, 1, NULL, 0, NULL);
}
/*
* wm8400_init - Generic initialisation
*
* The WM8400 can be configured as either an I2C or SPI device. Probe
* functions for each bus set up the accessors then call into this to
* set up the device itself.
*/
static int wm8400_init(struct wm8400 *wm8400,
struct wm8400_platform_data *pdata)
{
unsigned int reg;
int ret;
/* Check that this is actually a WM8400 */
ret = regmap_read(wm8400->regmap, WM8400_RESET_ID, ®);
if (ret != 0) {
dev_err(wm8400->dev, "Chip ID register read failed\n");
return -EIO;
}
if (reg != 0x6172) {
dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n",
reg);
return -ENODEV;
}
ret = regmap_read(wm8400->regmap, WM8400_ID, ®);
if (ret != 0) {
dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
return ret;
}
reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
ret = wm8400_register_codec(wm8400);
if (ret != 0) {
dev_err(wm8400->dev, "Failed to register codec\n");
return ret;
}
if (pdata && pdata->platform_init) {
ret = pdata->platform_init(wm8400->dev);
if (ret != 0) {
dev_err(wm8400->dev, "Platform init failed: %d\n",
ret);
return ret;
}
} else
dev_warn(wm8400->dev, "No platform initialisation supplied\n");
return 0;
}
static const struct regmap_config wm8400_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8400_REGISTER_COUNT - 1,
.volatile_reg = wm8400_volatile,
.cache_type = REGCACHE_RBTREE,
};
/**
* wm8400_reset_codec_reg_cache - Reset cached codec registers to
* their default values.
*
* @wm8400: pointer to local driver data structure
*/
void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
{
regmap_reinit_cache(wm8400->regmap, &wm8400_regmap_config);
}
EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
#if IS_ENABLED(CONFIG_I2C)
static int wm8400_i2c_probe(struct i2c_client *i2c)
{
struct wm8400 *wm8400;
wm8400 = devm_kzalloc(&i2c->dev, sizeof(struct wm8400), GFP_KERNEL);
if (!wm8400)
return -ENOMEM;
wm8400->regmap = devm_regmap_init_i2c(i2c, &wm8400_regmap_config);
if (IS_ERR(wm8400->regmap))
return PTR_ERR(wm8400->regmap);
wm8400->dev = &i2c->dev;
i2c_set_clientdata(i2c, wm8400);
return wm8400_init(wm8400, dev_get_platdata(&i2c->dev));
}
static const struct i2c_device_id wm8400_i2c_id[] = {
{ "wm8400", 0 },
{ }
};
static struct i2c_driver wm8400_i2c_driver = {
.driver = {
.name = "WM8400",
},
.probe = wm8400_i2c_probe,
.id_table = wm8400_i2c_id,
};
#endif
static int __init wm8400_driver_init(void)
{
int ret = -ENODEV;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8400_i2c_driver);
if (ret != 0)
pr_err("Failed to register I2C driver: %d\n", ret);
#endif
return ret;
}
subsys_initcall(wm8400_driver_init);
| linux-master | drivers/mfd/wm8400-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/mfd/ucb1x00-assabet.c
*
* Copyright (C) 2001-2003 Russell King, All Rights Reserved.
*
* We handle the machine-specific bits of the UCB1x00 driver here.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/platform_device.h>
#include <linux/proc_fs.h>
#include <linux/mfd/ucb1x00.h>
#define UCB1X00_ATTR(name,input)\
static ssize_t name##_show(struct device *dev, struct device_attribute *attr, \
char *buf) \
{ \
struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); \
int val; \
ucb1x00_adc_enable(ucb); \
val = ucb1x00_adc_read(ucb, input, UCB_NOSYNC); \
ucb1x00_adc_disable(ucb); \
return sprintf(buf, "%d\n", val); \
} \
static DEVICE_ATTR_RO(name)
UCB1X00_ATTR(vbatt, UCB_ADC_INP_AD1);
UCB1X00_ATTR(vcharger, UCB_ADC_INP_AD0);
UCB1X00_ATTR(batt_temp, UCB_ADC_INP_AD2);
static int ucb1x00_assabet_add(struct ucb1x00_dev *dev)
{
struct ucb1x00 *ucb = dev->ucb;
struct platform_device *pdev;
struct gpio_keys_platform_data keys;
static struct gpio_keys_button buttons[6];
unsigned i;
memset(buttons, 0, sizeof(buttons));
memset(&keys, 0, sizeof(keys));
for (i = 0; i < ARRAY_SIZE(buttons); i++) {
buttons[i].code = BTN_0 + i;
buttons[i].gpio = ucb->gpio.base + i;
buttons[i].type = EV_KEY;
buttons[i].can_disable = true;
}
keys.buttons = buttons;
keys.nbuttons = ARRAY_SIZE(buttons);
keys.poll_interval = 50;
keys.name = "ucb1x00";
pdev = platform_device_register_data(&ucb->dev, "gpio-keys", -1,
&keys, sizeof(keys));
device_create_file(&ucb->dev, &dev_attr_vbatt);
device_create_file(&ucb->dev, &dev_attr_vcharger);
device_create_file(&ucb->dev, &dev_attr_batt_temp);
dev->priv = pdev;
return 0;
}
static void ucb1x00_assabet_remove(struct ucb1x00_dev *dev)
{
struct platform_device *pdev = dev->priv;
if (!IS_ERR(pdev))
platform_device_unregister(pdev);
device_remove_file(&dev->ucb->dev, &dev_attr_batt_temp);
device_remove_file(&dev->ucb->dev, &dev_attr_vcharger);
device_remove_file(&dev->ucb->dev, &dev_attr_vbatt);
}
static struct ucb1x00_driver ucb1x00_assabet_driver = {
.add = ucb1x00_assabet_add,
.remove = ucb1x00_assabet_remove,
};
static int __init ucb1x00_assabet_init(void)
{
return ucb1x00_register_driver(&ucb1x00_assabet_driver);
}
static void __exit ucb1x00_assabet_exit(void)
{
ucb1x00_unregister_driver(&ucb1x00_assabet_driver);
}
module_init(ucb1x00_assabet_init);
module_exit(ucb1x00_assabet_exit);
MODULE_AUTHOR("Russell King <[email protected]>");
MODULE_DESCRIPTION("Assabet noddy testing only example ADC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/ucb1x00-assabet.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Lochnagar I2C bus interface
*
* Copyright (c) 2012-2018 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*
* Author: Charles Keepax <[email protected]>
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/lockdep.h>
#include <linux/mfd/core.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/mfd/lochnagar.h>
#include <linux/mfd/lochnagar1_regs.h>
#include <linux/mfd/lochnagar2_regs.h>
#define LOCHNAGAR_BOOT_RETRIES 10
#define LOCHNAGAR_BOOT_DELAY_MS 350
#define LOCHNAGAR_CONFIG_POLL_US 10000
static bool lochnagar1_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case LOCHNAGAR_SOFTWARE_RESET:
case LOCHNAGAR_FIRMWARE_ID1...LOCHNAGAR_FIRMWARE_ID2:
case LOCHNAGAR1_CDC_AIF1_SEL...LOCHNAGAR1_CDC_AIF3_SEL:
case LOCHNAGAR1_CDC_MCLK1_SEL...LOCHNAGAR1_CDC_MCLK2_SEL:
case LOCHNAGAR1_CDC_AIF_CTRL1...LOCHNAGAR1_CDC_AIF_CTRL2:
case LOCHNAGAR1_EXT_AIF_CTRL:
case LOCHNAGAR1_DSP_AIF1_SEL...LOCHNAGAR1_DSP_AIF2_SEL:
case LOCHNAGAR1_DSP_CLKIN_SEL:
case LOCHNAGAR1_DSP_AIF:
case LOCHNAGAR1_GF_AIF1...LOCHNAGAR1_GF_AIF2:
case LOCHNAGAR1_PSIA_AIF:
case LOCHNAGAR1_PSIA1_SEL...LOCHNAGAR1_PSIA2_SEL:
case LOCHNAGAR1_SPDIF_AIF_SEL:
case LOCHNAGAR1_GF_AIF3_SEL...LOCHNAGAR1_GF_AIF4_SEL:
case LOCHNAGAR1_GF_CLKOUT1_SEL:
case LOCHNAGAR1_GF_AIF1_SEL...LOCHNAGAR1_GF_AIF2_SEL:
case LOCHNAGAR1_GF_GPIO2...LOCHNAGAR1_GF_GPIO7:
case LOCHNAGAR1_RST:
case LOCHNAGAR1_LED1...LOCHNAGAR1_LED2:
case LOCHNAGAR1_I2C_CTRL:
return true;
default:
return false;
}
}
static const struct regmap_config lochnagar1_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = 0x50,
.readable_reg = lochnagar1_readable_register,
.use_single_read = true,
.use_single_write = true,
.cache_type = REGCACHE_RBTREE,
};
static const struct reg_sequence lochnagar1_patch[] = {
{ 0x40, 0x0083 },
{ 0x47, 0x0018 },
{ 0x50, 0x0000 },
};
static bool lochnagar2_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case LOCHNAGAR_SOFTWARE_RESET:
case LOCHNAGAR_FIRMWARE_ID1...LOCHNAGAR_FIRMWARE_ID2:
case LOCHNAGAR2_CDC_AIF1_CTRL...LOCHNAGAR2_CDC_AIF3_CTRL:
case LOCHNAGAR2_DSP_AIF1_CTRL...LOCHNAGAR2_DSP_AIF2_CTRL:
case LOCHNAGAR2_PSIA1_CTRL...LOCHNAGAR2_PSIA2_CTRL:
case LOCHNAGAR2_GF_AIF3_CTRL...LOCHNAGAR2_GF_AIF4_CTRL:
case LOCHNAGAR2_GF_AIF1_CTRL...LOCHNAGAR2_GF_AIF2_CTRL:
case LOCHNAGAR2_SPDIF_AIF_CTRL:
case LOCHNAGAR2_USB_AIF1_CTRL...LOCHNAGAR2_USB_AIF2_CTRL:
case LOCHNAGAR2_ADAT_AIF_CTRL:
case LOCHNAGAR2_CDC_MCLK1_CTRL...LOCHNAGAR2_CDC_MCLK2_CTRL:
case LOCHNAGAR2_DSP_CLKIN_CTRL:
case LOCHNAGAR2_PSIA1_MCLK_CTRL...LOCHNAGAR2_PSIA2_MCLK_CTRL:
case LOCHNAGAR2_SPDIF_MCLK_CTRL:
case LOCHNAGAR2_GF_CLKOUT1_CTRL...LOCHNAGAR2_GF_CLKOUT2_CTRL:
case LOCHNAGAR2_ADAT_MCLK_CTRL:
case LOCHNAGAR2_SOUNDCARD_MCLK_CTRL:
case LOCHNAGAR2_GPIO_FPGA_GPIO1...LOCHNAGAR2_GPIO_FPGA_GPIO6:
case LOCHNAGAR2_GPIO_CDC_GPIO1...LOCHNAGAR2_GPIO_CDC_GPIO8:
case LOCHNAGAR2_GPIO_DSP_GPIO1...LOCHNAGAR2_GPIO_DSP_GPIO6:
case LOCHNAGAR2_GPIO_GF_GPIO2...LOCHNAGAR2_GPIO_GF_GPIO7:
case LOCHNAGAR2_GPIO_CDC_AIF1_BCLK...LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT:
case LOCHNAGAR2_GPIO_DSP_AIF1_BCLK...LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT:
case LOCHNAGAR2_GPIO_PSIA1_BCLK...LOCHNAGAR2_GPIO_PSIA2_TXDAT:
case LOCHNAGAR2_GPIO_GF_AIF3_BCLK...LOCHNAGAR2_GPIO_GF_AIF4_TXDAT:
case LOCHNAGAR2_GPIO_GF_AIF1_BCLK...LOCHNAGAR2_GPIO_GF_AIF2_TXDAT:
case LOCHNAGAR2_GPIO_DSP_UART1_RX...LOCHNAGAR2_GPIO_DSP_UART2_TX:
case LOCHNAGAR2_GPIO_GF_UART2_RX...LOCHNAGAR2_GPIO_GF_UART2_TX:
case LOCHNAGAR2_GPIO_USB_UART_RX:
case LOCHNAGAR2_GPIO_CDC_PDMCLK1...LOCHNAGAR2_GPIO_CDC_PDMDAT2:
case LOCHNAGAR2_GPIO_CDC_DMICCLK1...LOCHNAGAR2_GPIO_CDC_DMICDAT4:
case LOCHNAGAR2_GPIO_DSP_DMICCLK1...LOCHNAGAR2_GPIO_DSP_DMICDAT2:
case LOCHNAGAR2_GPIO_I2C2_SCL...LOCHNAGAR2_GPIO_I2C4_SDA:
case LOCHNAGAR2_GPIO_DSP_STANDBY:
case LOCHNAGAR2_GPIO_CDC_MCLK1...LOCHNAGAR2_GPIO_CDC_MCLK2:
case LOCHNAGAR2_GPIO_DSP_CLKIN:
case LOCHNAGAR2_GPIO_PSIA1_MCLK...LOCHNAGAR2_GPIO_PSIA2_MCLK:
case LOCHNAGAR2_GPIO_GF_GPIO1...LOCHNAGAR2_GPIO_GF_GPIO5:
case LOCHNAGAR2_GPIO_DSP_GPIO20:
case LOCHNAGAR2_GPIO_CHANNEL1...LOCHNAGAR2_GPIO_CHANNEL16:
case LOCHNAGAR2_MINICARD_RESETS:
case LOCHNAGAR2_ANALOGUE_PATH_CTRL1...LOCHNAGAR2_ANALOGUE_PATH_CTRL2:
case LOCHNAGAR2_COMMS_CTRL4:
case LOCHNAGAR2_SPDIF_CTRL:
case LOCHNAGAR2_IMON_CTRL1...LOCHNAGAR2_IMON_CTRL4:
case LOCHNAGAR2_IMON_DATA1...LOCHNAGAR2_IMON_DATA2:
case LOCHNAGAR2_POWER_CTRL:
case LOCHNAGAR2_MICVDD_CTRL1:
case LOCHNAGAR2_MICVDD_CTRL2:
case LOCHNAGAR2_VDDCORE_CDC_CTRL1:
case LOCHNAGAR2_VDDCORE_CDC_CTRL2:
case LOCHNAGAR2_SOUNDCARD_AIF_CTRL:
return true;
default:
return false;
}
}
static bool lochnagar2_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case LOCHNAGAR2_GPIO_CHANNEL1...LOCHNAGAR2_GPIO_CHANNEL16:
case LOCHNAGAR2_ANALOGUE_PATH_CTRL1:
case LOCHNAGAR2_IMON_CTRL3...LOCHNAGAR2_IMON_CTRL4:
case LOCHNAGAR2_IMON_DATA1...LOCHNAGAR2_IMON_DATA2:
return true;
default:
return false;
}
}
static const struct regmap_config lochnagar2_i2c_regmap = {
.reg_bits = 16,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = 0x1F1F,
.readable_reg = lochnagar2_readable_register,
.volatile_reg = lochnagar2_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
static const struct reg_sequence lochnagar2_patch[] = {
{ 0x00EE, 0x0000 },
};
struct lochnagar_config {
int id;
const char * const name;
enum lochnagar_type type;
const struct regmap_config *regmap;
const struct reg_sequence *patch;
int npatch;
};
static struct lochnagar_config lochnagar_configs[] = {
{
.id = 0x50,
.name = "lochnagar1",
.type = LOCHNAGAR1,
.regmap = &lochnagar1_i2c_regmap,
.patch = lochnagar1_patch,
.npatch = ARRAY_SIZE(lochnagar1_patch),
},
{
.id = 0xCB58,
.name = "lochnagar2",
.type = LOCHNAGAR2,
.regmap = &lochnagar2_i2c_regmap,
.patch = lochnagar2_patch,
.npatch = ARRAY_SIZE(lochnagar2_patch),
},
};
static const struct of_device_id lochnagar_of_match[] = {
{ .compatible = "cirrus,lochnagar1", .data = &lochnagar_configs[0] },
{ .compatible = "cirrus,lochnagar2", .data = &lochnagar_configs[1] },
{},
};
static int lochnagar_wait_for_boot(struct regmap *regmap, unsigned int *id)
{
int i, ret;
for (i = 0; i < LOCHNAGAR_BOOT_RETRIES; ++i) {
msleep(LOCHNAGAR_BOOT_DELAY_MS);
/* The reset register will return the device ID when read */
ret = regmap_read(regmap, LOCHNAGAR_SOFTWARE_RESET, id);
if (!ret)
return ret;
}
return -ETIMEDOUT;
}
/**
* lochnagar_update_config - Synchronise the boards analogue configuration to
* the hardware.
*
* @lochnagar: A pointer to the primary core data structure.
*
* Return: Zero on success or an appropriate negative error code on failure.
*/
int lochnagar_update_config(struct lochnagar *lochnagar)
{
struct regmap *regmap = lochnagar->regmap;
unsigned int done = LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK;
int timeout_ms = LOCHNAGAR_BOOT_DELAY_MS * LOCHNAGAR_BOOT_RETRIES;
unsigned int val = 0;
int ret;
lockdep_assert_held(&lochnagar->analogue_config_lock);
if (lochnagar->type != LOCHNAGAR2)
return 0;
/*
* Toggle the ANALOGUE_PATH_UPDATE bit and wait for the device to
* acknowledge that any outstanding changes to the analogue
* configuration have been applied.
*/
ret = regmap_write(regmap, LOCHNAGAR2_ANALOGUE_PATH_CTRL1, 0);
if (ret < 0)
return ret;
ret = regmap_write(regmap, LOCHNAGAR2_ANALOGUE_PATH_CTRL1,
LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK);
if (ret < 0)
return ret;
ret = regmap_read_poll_timeout(regmap,
LOCHNAGAR2_ANALOGUE_PATH_CTRL1, val,
(val & done), LOCHNAGAR_CONFIG_POLL_US,
timeout_ms * 1000);
if (ret < 0)
return ret;
return 0;
}
EXPORT_SYMBOL_GPL(lochnagar_update_config);
static int lochnagar_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
const struct lochnagar_config *config = NULL;
const struct of_device_id *of_id;
struct lochnagar *lochnagar;
struct gpio_desc *reset, *present;
unsigned int val;
unsigned int firmwareid;
unsigned int devid, rev;
int ret;
lochnagar = devm_kzalloc(dev, sizeof(*lochnagar), GFP_KERNEL);
if (!lochnagar)
return -ENOMEM;
of_id = of_match_device(lochnagar_of_match, dev);
if (!of_id)
return -EINVAL;
config = of_id->data;
lochnagar->dev = dev;
mutex_init(&lochnagar->analogue_config_lock);
dev_set_drvdata(dev, lochnagar);
reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(reset)) {
ret = PTR_ERR(reset);
dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
return ret;
}
present = devm_gpiod_get_optional(dev, "present", GPIOD_OUT_HIGH);
if (IS_ERR(present)) {
ret = PTR_ERR(present);
dev_err(dev, "Failed to get present GPIO: %d\n", ret);
return ret;
}
/* Leave the Lochnagar in reset for a reasonable amount of time */
msleep(20);
/* Bring Lochnagar out of reset */
gpiod_set_value_cansleep(reset, 1);
/* Identify Lochnagar */
lochnagar->type = config->type;
lochnagar->regmap = devm_regmap_init_i2c(i2c, config->regmap);
if (IS_ERR(lochnagar->regmap)) {
ret = PTR_ERR(lochnagar->regmap);
dev_err(dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
/* Wait for Lochnagar to boot */
ret = lochnagar_wait_for_boot(lochnagar->regmap, &val);
if (ret < 0) {
dev_err(dev, "Failed to read device ID: %d\n", ret);
return ret;
}
devid = val & LOCHNAGAR_DEVICE_ID_MASK;
rev = val & LOCHNAGAR_REV_ID_MASK;
if (devid != config->id) {
dev_err(dev,
"ID does not match %s (expected 0x%x got 0x%x)\n",
config->name, config->id, devid);
return -ENODEV;
}
/* Identify firmware */
ret = regmap_read(lochnagar->regmap, LOCHNAGAR_FIRMWARE_ID1, &val);
if (ret < 0) {
dev_err(dev, "Failed to read firmware id 1: %d\n", ret);
return ret;
}
firmwareid = val;
ret = regmap_read(lochnagar->regmap, LOCHNAGAR_FIRMWARE_ID2, &val);
if (ret < 0) {
dev_err(dev, "Failed to read firmware id 2: %d\n", ret);
return ret;
}
firmwareid |= (val << config->regmap->val_bits);
dev_info(dev, "Found %s (0x%x) revision %u firmware 0x%.6x\n",
config->name, devid, rev + 1, firmwareid);
ret = regmap_register_patch(lochnagar->regmap, config->patch,
config->npatch);
if (ret < 0) {
dev_err(dev, "Failed to register patch: %d\n", ret);
return ret;
}
ret = devm_of_platform_populate(dev);
if (ret < 0) {
dev_err(dev, "Failed to populate child nodes: %d\n", ret);
return ret;
}
return ret;
}
static struct i2c_driver lochnagar_i2c_driver = {
.driver = {
.name = "lochnagar",
.of_match_table = lochnagar_of_match,
.suppress_bind_attrs = true,
},
.probe = lochnagar_i2c_probe,
};
static int __init lochnagar_i2c_init(void)
{
int ret;
ret = i2c_add_driver(&lochnagar_i2c_driver);
if (ret)
pr_err("Failed to register Lochnagar driver: %d\n", ret);
return ret;
}
subsys_initcall(lochnagar_i2c_init);
| linux-master | drivers/mfd/lochnagar-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Wolfson WM97xx -- Core device
*
* Copyright (C) 2017 Robert Jarzmik
*
* Features:
* - an AC97 audio codec
* - a touchscreen driver
* - a GPIO block
*/
#include <linux/device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/wm97xx.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/wm97xx.h>
#include <sound/ac97/codec.h>
#include <sound/ac97/compat.h>
#define WM9705_VENDOR_ID 0x574d4c05
#define WM9712_VENDOR_ID 0x574d4c12
#define WM9713_VENDOR_ID 0x574d4c13
#define WM97xx_VENDOR_ID_MASK 0xffffffff
struct wm97xx_priv {
struct regmap *regmap;
struct snd_ac97 *ac97;
struct device *dev;
struct wm97xx_platform_data codec_pdata;
};
static bool wm97xx_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AC97_RESET ... AC97_PCM_SURR_DAC_RATE:
case AC97_PCM_LR_ADC_RATE:
case AC97_CENTER_LFE_MASTER:
case AC97_SPDIF ... AC97_LINE1_LEVEL:
case AC97_GPIO_CFG ... 0x5c:
case AC97_CODEC_CLASS_REV ... AC97_PCI_SID:
case 0x74 ... AC97_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool wm97xx_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AC97_VENDOR_ID1:
case AC97_VENDOR_ID2:
return false;
default:
return wm97xx_readable_reg(dev, reg);
}
}
static const struct reg_default wm9705_reg_defaults[] = {
{ 0x02, 0x8000 },
{ 0x04, 0x8000 },
{ 0x06, 0x8000 },
{ 0x0a, 0x8000 },
{ 0x0c, 0x8008 },
{ 0x0e, 0x8008 },
{ 0x10, 0x8808 },
{ 0x12, 0x8808 },
{ 0x14, 0x8808 },
{ 0x16, 0x8808 },
{ 0x18, 0x8808 },
{ 0x1a, 0x0000 },
{ 0x1c, 0x8000 },
{ 0x20, 0x0000 },
{ 0x22, 0x0000 },
{ 0x26, 0x000f },
{ 0x28, 0x0605 },
{ 0x2a, 0x0000 },
{ 0x2c, 0xbb80 },
{ 0x32, 0xbb80 },
{ 0x34, 0x2000 },
{ 0x5a, 0x0000 },
{ 0x5c, 0x0000 },
{ 0x72, 0x0808 },
{ 0x74, 0x0000 },
{ 0x76, 0x0006 },
{ 0x78, 0x0000 },
{ 0x7a, 0x0000 },
};
static const struct regmap_config wm9705_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.max_register = 0x7e,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wm9705_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm9705_reg_defaults),
.volatile_reg = regmap_ac97_default_volatile,
.readable_reg = wm97xx_readable_reg,
.writeable_reg = wm97xx_writeable_reg,
};
static struct mfd_cell wm9705_cells[] = {
{ .name = "wm9705-codec", },
{ .name = "wm97xx-ts", },
};
static bool wm9712_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AC97_REC_GAIN:
return true;
default:
return regmap_ac97_default_volatile(dev, reg);
}
}
static const struct reg_default wm9712_reg_defaults[] = {
{ 0x02, 0x8000 },
{ 0x04, 0x8000 },
{ 0x06, 0x8000 },
{ 0x08, 0x0f0f },
{ 0x0a, 0xaaa0 },
{ 0x0c, 0xc008 },
{ 0x0e, 0x6808 },
{ 0x10, 0xe808 },
{ 0x12, 0xaaa0 },
{ 0x14, 0xad00 },
{ 0x16, 0x8000 },
{ 0x18, 0xe808 },
{ 0x1a, 0x3000 },
{ 0x1c, 0x8000 },
{ 0x20, 0x0000 },
{ 0x22, 0x0000 },
{ 0x26, 0x000f },
{ 0x28, 0x0605 },
{ 0x2a, 0x0410 },
{ 0x2c, 0xbb80 },
{ 0x2e, 0xbb80 },
{ 0x32, 0xbb80 },
{ 0x34, 0x2000 },
{ 0x4c, 0xf83e },
{ 0x4e, 0xffff },
{ 0x50, 0x0000 },
{ 0x52, 0x0000 },
{ 0x56, 0xf83e },
{ 0x58, 0x0008 },
{ 0x5c, 0x0000 },
{ 0x60, 0xb032 },
{ 0x62, 0x3e00 },
{ 0x64, 0x0000 },
{ 0x76, 0x0006 },
{ 0x78, 0x0001 },
{ 0x7a, 0x0000 },
};
static const struct regmap_config wm9712_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.max_register = 0x7e,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wm9712_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm9712_reg_defaults),
.volatile_reg = wm9712_volatile_reg,
.readable_reg = wm97xx_readable_reg,
.writeable_reg = wm97xx_writeable_reg,
};
static struct mfd_cell wm9712_cells[] = {
{ .name = "wm9712-codec", },
{ .name = "wm97xx-ts", },
};
static const struct reg_default wm9713_reg_defaults[] = {
{ 0x02, 0x8080 }, /* Speaker Output Volume */
{ 0x04, 0x8080 }, /* Headphone Output Volume */
{ 0x06, 0x8080 }, /* Out3/OUT4 Volume */
{ 0x08, 0xc880 }, /* Mono Volume */
{ 0x0a, 0xe808 }, /* LINEIN Volume */
{ 0x0c, 0xe808 }, /* DAC PGA Volume */
{ 0x0e, 0x0808 }, /* MIC PGA Volume */
{ 0x10, 0x00da }, /* MIC Routing Control */
{ 0x12, 0x8000 }, /* Record PGA Volume */
{ 0x14, 0xd600 }, /* Record Routing */
{ 0x16, 0xaaa0 }, /* PCBEEP Volume */
{ 0x18, 0xaaa0 }, /* VxDAC Volume */
{ 0x1a, 0xaaa0 }, /* AUXDAC Volume */
{ 0x1c, 0x0000 }, /* Output PGA Mux */
{ 0x1e, 0x0000 }, /* DAC 3D control */
{ 0x20, 0x0f0f }, /* DAC Tone Control*/
{ 0x22, 0x0040 }, /* MIC Input Select & Bias */
{ 0x24, 0x0000 }, /* Output Volume Mapping & Jack */
{ 0x26, 0x7f00 }, /* Powerdown Ctrl/Stat*/
{ 0x28, 0x0405 }, /* Extended Audio ID */
{ 0x2a, 0x0410 }, /* Extended Audio Start/Ctrl */
{ 0x2c, 0xbb80 }, /* Audio DACs Sample Rate */
{ 0x2e, 0xbb80 }, /* AUXDAC Sample Rate */
{ 0x32, 0xbb80 }, /* Audio ADCs Sample Rate */
{ 0x36, 0x4523 }, /* PCM codec control */
{ 0x3a, 0x2000 }, /* SPDIF control */
{ 0x3c, 0xfdff }, /* Powerdown 1 */
{ 0x3e, 0xffff }, /* Powerdown 2 */
{ 0x40, 0x0000 }, /* General Purpose */
{ 0x42, 0x0000 }, /* Fast Power-Up Control */
{ 0x44, 0x0080 }, /* MCLK/PLL Control */
{ 0x46, 0x0000 }, /* MCLK/PLL Control */
{ 0x4c, 0xfffe }, /* GPIO Pin Configuration */
{ 0x4e, 0xffff }, /* GPIO Pin Polarity / Type */
{ 0x50, 0x0000 }, /* GPIO Pin Sticky */
{ 0x52, 0x0000 }, /* GPIO Pin Wake-Up */
/* GPIO Pin Status */
{ 0x56, 0xfffe }, /* GPIO Pin Sharing */
{ 0x58, 0x4000 }, /* GPIO PullUp/PullDown */
{ 0x5a, 0x0000 }, /* Additional Functions 1 */
{ 0x5c, 0x0000 }, /* Additional Functions 2 */
{ 0x60, 0xb032 }, /* ALC Control */
{ 0x62, 0x3e00 }, /* ALC / Noise Gate Control */
{ 0x64, 0x0000 }, /* AUXDAC input control */
{ 0x74, 0x0000 }, /* Digitiser Reg 1 */
{ 0x76, 0x0006 }, /* Digitiser Reg 2 */
{ 0x78, 0x0001 }, /* Digitiser Reg 3 */
{ 0x7a, 0x0000 }, /* Digitiser Read Back */
};
static const struct regmap_config wm9713_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.max_register = 0x7e,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wm9713_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm9713_reg_defaults),
.volatile_reg = regmap_ac97_default_volatile,
.readable_reg = wm97xx_readable_reg,
.writeable_reg = wm97xx_writeable_reg,
};
static struct mfd_cell wm9713_cells[] = {
{ .name = "wm9713-codec", },
{ .name = "wm97xx-ts", },
};
static int wm97xx_ac97_probe(struct ac97_codec_device *adev)
{
struct wm97xx_priv *wm97xx;
const struct regmap_config *config;
struct wm97xx_platform_data *codec_pdata;
struct mfd_cell *cells;
int ret = -ENODEV, nb_cells, i;
struct wm97xx_pdata *pdata = snd_ac97_codec_get_platdata(adev);
wm97xx = devm_kzalloc(ac97_codec_dev2dev(adev),
sizeof(*wm97xx), GFP_KERNEL);
if (!wm97xx)
return -ENOMEM;
wm97xx->dev = ac97_codec_dev2dev(adev);
wm97xx->ac97 = snd_ac97_compat_alloc(adev);
if (IS_ERR(wm97xx->ac97))
return PTR_ERR(wm97xx->ac97);
ac97_set_drvdata(adev, wm97xx);
dev_info(wm97xx->dev, "wm97xx core found, id=0x%x\n",
adev->vendor_id);
codec_pdata = &wm97xx->codec_pdata;
codec_pdata->ac97 = wm97xx->ac97;
codec_pdata->batt_pdata = pdata ? pdata->batt_pdata : NULL;
switch (adev->vendor_id) {
case WM9705_VENDOR_ID:
config = &wm9705_regmap_config;
cells = wm9705_cells;
nb_cells = ARRAY_SIZE(wm9705_cells);
break;
case WM9712_VENDOR_ID:
config = &wm9712_regmap_config;
cells = wm9712_cells;
nb_cells = ARRAY_SIZE(wm9712_cells);
break;
case WM9713_VENDOR_ID:
config = &wm9713_regmap_config;
cells = wm9713_cells;
nb_cells = ARRAY_SIZE(wm9713_cells);
break;
default:
goto err_free_compat;
}
for (i = 0; i < nb_cells; i++) {
cells[i].platform_data = codec_pdata;
cells[i].pdata_size = sizeof(*codec_pdata);
}
codec_pdata->regmap = devm_regmap_init_ac97(wm97xx->ac97, config);
if (IS_ERR(codec_pdata->regmap)) {
ret = PTR_ERR(codec_pdata->regmap);
goto err_free_compat;
}
ret = devm_mfd_add_devices(wm97xx->dev, PLATFORM_DEVID_NONE,
cells, nb_cells, NULL, 0, NULL);
if (ret)
goto err_free_compat;
return ret;
err_free_compat:
snd_ac97_compat_release(wm97xx->ac97);
return ret;
}
static void wm97xx_ac97_remove(struct ac97_codec_device *adev)
{
struct wm97xx_priv *wm97xx = ac97_get_drvdata(adev);
snd_ac97_compat_release(wm97xx->ac97);
}
static const struct ac97_id wm97xx_ac97_ids[] = {
{ .id = WM9705_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK },
{ .id = WM9712_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK },
{ .id = WM9713_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK },
{ }
};
static struct ac97_codec_driver wm97xx_ac97_driver = {
.driver = {
.name = "wm97xx-core",
},
.probe = wm97xx_ac97_probe,
.remove = wm97xx_ac97_remove,
.id_table = wm97xx_ac97_ids,
};
static int __init wm97xx_module_init(void)
{
return snd_ac97_codec_driver_register(&wm97xx_ac97_driver);
}
module_init(wm97xx_module_init);
static void __exit wm97xx_module_exit(void)
{
snd_ac97_codec_driver_unregister(&wm97xx_ac97_driver);
}
module_exit(wm97xx_module_exit);
MODULE_DESCRIPTION("WM9712, WM9713 core driver");
MODULE_AUTHOR("Robert Jarzmik <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/wm97xx-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/mfd/aat2870-core.c
*
* Copyright (c) 2011, NVIDIA Corporation.
* Author: Jin Park <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/debugfs.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/mfd/core.h>
#include <linux/mfd/aat2870.h>
#include <linux/regulator/machine.h>
static struct aat2870_register aat2870_regs[AAT2870_REG_NUM] = {
/* readable, writeable, value */
{ 0, 1, 0x00 }, /* 0x00 AAT2870_BL_CH_EN */
{ 0, 1, 0x16 }, /* 0x01 AAT2870_BLM */
{ 0, 1, 0x16 }, /* 0x02 AAT2870_BLS */
{ 0, 1, 0x56 }, /* 0x03 AAT2870_BL1 */
{ 0, 1, 0x56 }, /* 0x04 AAT2870_BL2 */
{ 0, 1, 0x56 }, /* 0x05 AAT2870_BL3 */
{ 0, 1, 0x56 }, /* 0x06 AAT2870_BL4 */
{ 0, 1, 0x56 }, /* 0x07 AAT2870_BL5 */
{ 0, 1, 0x56 }, /* 0x08 AAT2870_BL6 */
{ 0, 1, 0x56 }, /* 0x09 AAT2870_BL7 */
{ 0, 1, 0x56 }, /* 0x0A AAT2870_BL8 */
{ 0, 1, 0x00 }, /* 0x0B AAT2870_FLR */
{ 0, 1, 0x03 }, /* 0x0C AAT2870_FM */
{ 0, 1, 0x03 }, /* 0x0D AAT2870_FS */
{ 0, 1, 0x10 }, /* 0x0E AAT2870_ALS_CFG0 */
{ 0, 1, 0x06 }, /* 0x0F AAT2870_ALS_CFG1 */
{ 0, 1, 0x00 }, /* 0x10 AAT2870_ALS_CFG2 */
{ 1, 0, 0x00 }, /* 0x11 AAT2870_AMB */
{ 0, 1, 0x00 }, /* 0x12 AAT2870_ALS0 */
{ 0, 1, 0x00 }, /* 0x13 AAT2870_ALS1 */
{ 0, 1, 0x00 }, /* 0x14 AAT2870_ALS2 */
{ 0, 1, 0x00 }, /* 0x15 AAT2870_ALS3 */
{ 0, 1, 0x00 }, /* 0x16 AAT2870_ALS4 */
{ 0, 1, 0x00 }, /* 0x17 AAT2870_ALS5 */
{ 0, 1, 0x00 }, /* 0x18 AAT2870_ALS6 */
{ 0, 1, 0x00 }, /* 0x19 AAT2870_ALS7 */
{ 0, 1, 0x00 }, /* 0x1A AAT2870_ALS8 */
{ 0, 1, 0x00 }, /* 0x1B AAT2870_ALS9 */
{ 0, 1, 0x00 }, /* 0x1C AAT2870_ALSA */
{ 0, 1, 0x00 }, /* 0x1D AAT2870_ALSB */
{ 0, 1, 0x00 }, /* 0x1E AAT2870_ALSC */
{ 0, 1, 0x00 }, /* 0x1F AAT2870_ALSD */
{ 0, 1, 0x00 }, /* 0x20 AAT2870_ALSE */
{ 0, 1, 0x00 }, /* 0x21 AAT2870_ALSF */
{ 0, 1, 0x00 }, /* 0x22 AAT2870_SUB_SET */
{ 0, 1, 0x00 }, /* 0x23 AAT2870_SUB_CTRL */
{ 0, 1, 0x00 }, /* 0x24 AAT2870_LDO_AB */
{ 0, 1, 0x00 }, /* 0x25 AAT2870_LDO_CD */
{ 0, 1, 0x00 }, /* 0x26 AAT2870_LDO_EN */
};
static struct mfd_cell aat2870_devs[] = {
{
.name = "aat2870-backlight",
.id = AAT2870_ID_BL,
.pdata_size = sizeof(struct aat2870_bl_platform_data),
},
{
.name = "aat2870-regulator",
.id = AAT2870_ID_LDOA,
.pdata_size = sizeof(struct regulator_init_data),
},
{
.name = "aat2870-regulator",
.id = AAT2870_ID_LDOB,
.pdata_size = sizeof(struct regulator_init_data),
},
{
.name = "aat2870-regulator",
.id = AAT2870_ID_LDOC,
.pdata_size = sizeof(struct regulator_init_data),
},
{
.name = "aat2870-regulator",
.id = AAT2870_ID_LDOD,
.pdata_size = sizeof(struct regulator_init_data),
},
};
static int __aat2870_read(struct aat2870_data *aat2870, u8 addr, u8 *val)
{
int ret;
if (addr >= AAT2870_REG_NUM) {
dev_err(aat2870->dev, "Invalid address, 0x%02x\n", addr);
return -EINVAL;
}
if (!aat2870->reg_cache[addr].readable) {
*val = aat2870->reg_cache[addr].value;
goto out;
}
ret = i2c_master_send(aat2870->client, &addr, 1);
if (ret < 0)
return ret;
if (ret != 1)
return -EIO;
ret = i2c_master_recv(aat2870->client, val, 1);
if (ret < 0)
return ret;
if (ret != 1)
return -EIO;
out:
dev_dbg(aat2870->dev, "read: addr=0x%02x, val=0x%02x\n", addr, *val);
return 0;
}
static int __aat2870_write(struct aat2870_data *aat2870, u8 addr, u8 val)
{
u8 msg[2];
int ret;
if (addr >= AAT2870_REG_NUM) {
dev_err(aat2870->dev, "Invalid address, 0x%02x\n", addr);
return -EINVAL;
}
if (!aat2870->reg_cache[addr].writeable) {
dev_err(aat2870->dev, "Address 0x%02x is not writeable\n",
addr);
return -EINVAL;
}
msg[0] = addr;
msg[1] = val;
ret = i2c_master_send(aat2870->client, msg, 2);
if (ret < 0)
return ret;
if (ret != 2)
return -EIO;
aat2870->reg_cache[addr].value = val;
dev_dbg(aat2870->dev, "write: addr=0x%02x, val=0x%02x\n", addr, val);
return 0;
}
static int aat2870_read(struct aat2870_data *aat2870, u8 addr, u8 *val)
{
int ret;
mutex_lock(&aat2870->io_lock);
ret = __aat2870_read(aat2870, addr, val);
mutex_unlock(&aat2870->io_lock);
return ret;
}
static int aat2870_write(struct aat2870_data *aat2870, u8 addr, u8 val)
{
int ret;
mutex_lock(&aat2870->io_lock);
ret = __aat2870_write(aat2870, addr, val);
mutex_unlock(&aat2870->io_lock);
return ret;
}
static int aat2870_update(struct aat2870_data *aat2870, u8 addr, u8 mask,
u8 val)
{
int change;
u8 old_val, new_val;
int ret;
mutex_lock(&aat2870->io_lock);
ret = __aat2870_read(aat2870, addr, &old_val);
if (ret)
goto out_unlock;
new_val = (old_val & ~mask) | (val & mask);
change = old_val != new_val;
if (change)
ret = __aat2870_write(aat2870, addr, new_val);
out_unlock:
mutex_unlock(&aat2870->io_lock);
return ret;
}
static inline void aat2870_enable(struct aat2870_data *aat2870)
{
if (aat2870->en_pin >= 0)
gpio_set_value(aat2870->en_pin, 1);
aat2870->is_enable = 1;
}
static inline void aat2870_disable(struct aat2870_data *aat2870)
{
if (aat2870->en_pin >= 0)
gpio_set_value(aat2870->en_pin, 0);
aat2870->is_enable = 0;
}
#ifdef CONFIG_DEBUG_FS
static ssize_t aat2870_dump_reg(struct aat2870_data *aat2870, char *buf)
{
u8 addr, val;
ssize_t count = 0;
int ret;
count += sprintf(buf, "aat2870 registers\n");
for (addr = 0; addr < AAT2870_REG_NUM; addr++) {
count += snprintf(buf + count, PAGE_SIZE - count, "0x%02x: ", addr);
if (count >= PAGE_SIZE - 1)
break;
ret = aat2870->read(aat2870, addr, &val);
if (ret == 0)
count += snprintf(buf + count, PAGE_SIZE - count,
"0x%02x", val);
else
count += snprintf(buf + count, PAGE_SIZE - count,
"<read fail: %d>", ret);
if (count >= PAGE_SIZE - 1)
break;
count += snprintf(buf + count, PAGE_SIZE - count, "\n");
if (count >= PAGE_SIZE - 1)
break;
}
/* Truncate count; min() would cause a warning */
if (count >= PAGE_SIZE)
count = PAGE_SIZE - 1;
return count;
}
static ssize_t aat2870_reg_read_file(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
struct aat2870_data *aat2870 = file->private_data;
char *buf;
ssize_t ret;
buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = aat2870_dump_reg(aat2870, buf);
if (ret >= 0)
ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
kfree(buf);
return ret;
}
static ssize_t aat2870_reg_write_file(struct file *file,
const char __user *user_buf, size_t count,
loff_t *ppos)
{
struct aat2870_data *aat2870 = file->private_data;
char buf[32];
ssize_t buf_size;
char *start = buf;
unsigned long addr, val;
int ret;
buf_size = min(count, (size_t)(sizeof(buf)-1));
if (copy_from_user(buf, user_buf, buf_size)) {
dev_err(aat2870->dev, "Failed to copy from user\n");
return -EFAULT;
}
buf[buf_size] = 0;
while (*start == ' ')
start++;
ret = kstrtoul(start, 16, &addr);
if (ret)
return ret;
if (addr >= AAT2870_REG_NUM) {
dev_err(aat2870->dev, "Invalid address, 0x%lx\n", addr);
return -EINVAL;
}
while (*start == ' ')
start++;
ret = kstrtoul(start, 16, &val);
if (ret)
return ret;
ret = aat2870->write(aat2870, (u8)addr, (u8)val);
if (ret)
return ret;
return buf_size;
}
static const struct file_operations aat2870_reg_fops = {
.open = simple_open,
.read = aat2870_reg_read_file,
.write = aat2870_reg_write_file,
};
static void aat2870_init_debugfs(struct aat2870_data *aat2870)
{
aat2870->dentry_root = debugfs_create_dir("aat2870", NULL);
debugfs_create_file("regs", 0644, aat2870->dentry_root, aat2870,
&aat2870_reg_fops);
}
#else
static inline void aat2870_init_debugfs(struct aat2870_data *aat2870)
{
}
#endif /* CONFIG_DEBUG_FS */
static int aat2870_i2c_probe(struct i2c_client *client)
{
struct aat2870_platform_data *pdata = dev_get_platdata(&client->dev);
struct aat2870_data *aat2870;
int i, j;
int ret = 0;
aat2870 = devm_kzalloc(&client->dev, sizeof(struct aat2870_data),
GFP_KERNEL);
if (!aat2870)
return -ENOMEM;
aat2870->dev = &client->dev;
aat2870->client = client;
i2c_set_clientdata(client, aat2870);
aat2870->reg_cache = aat2870_regs;
if (pdata->en_pin < 0)
aat2870->en_pin = -1;
else
aat2870->en_pin = pdata->en_pin;
aat2870->init = pdata->init;
aat2870->uninit = pdata->uninit;
aat2870->read = aat2870_read;
aat2870->write = aat2870_write;
aat2870->update = aat2870_update;
mutex_init(&aat2870->io_lock);
if (aat2870->init)
aat2870->init(aat2870);
if (aat2870->en_pin >= 0) {
ret = devm_gpio_request_one(&client->dev, aat2870->en_pin,
GPIOF_OUT_INIT_HIGH, "aat2870-en");
if (ret < 0) {
dev_err(&client->dev,
"Failed to request GPIO %d\n", aat2870->en_pin);
return ret;
}
}
aat2870_enable(aat2870);
for (i = 0; i < pdata->num_subdevs; i++) {
for (j = 0; j < ARRAY_SIZE(aat2870_devs); j++) {
if ((pdata->subdevs[i].id == aat2870_devs[j].id) &&
!strcmp(pdata->subdevs[i].name,
aat2870_devs[j].name)) {
aat2870_devs[j].platform_data =
pdata->subdevs[i].platform_data;
break;
}
}
}
ret = mfd_add_devices(aat2870->dev, 0, aat2870_devs,
ARRAY_SIZE(aat2870_devs), NULL, 0, NULL);
if (ret != 0) {
dev_err(aat2870->dev, "Failed to add subdev: %d\n", ret);
goto out_disable;
}
aat2870_init_debugfs(aat2870);
return 0;
out_disable:
aat2870_disable(aat2870);
return ret;
}
static int aat2870_i2c_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct aat2870_data *aat2870 = i2c_get_clientdata(client);
aat2870_disable(aat2870);
return 0;
}
static int aat2870_i2c_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct aat2870_data *aat2870 = i2c_get_clientdata(client);
struct aat2870_register *reg = NULL;
int i;
aat2870_enable(aat2870);
/* restore registers */
for (i = 0; i < AAT2870_REG_NUM; i++) {
reg = &aat2870->reg_cache[i];
if (reg->writeable)
aat2870->write(aat2870, i, reg->value);
}
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(aat2870_pm_ops, aat2870_i2c_suspend,
aat2870_i2c_resume);
static const struct i2c_device_id aat2870_i2c_id_table[] = {
{ "aat2870", 0 },
{ }
};
static struct i2c_driver aat2870_i2c_driver = {
.driver = {
.name = "aat2870",
.pm = pm_sleep_ptr(&aat2870_pm_ops),
.suppress_bind_attrs = true,
},
.probe = aat2870_i2c_probe,
.id_table = aat2870_i2c_id_table,
};
static int __init aat2870_init(void)
{
return i2c_add_driver(&aat2870_i2c_driver);
}
subsys_initcall(aat2870_init);
| linux-master | drivers/mfd/aat2870-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Motorola CPCAP PMIC core driver
*
* Copyright (C) 2016 Tony Lindgren <[email protected]>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/mfd/core.h>
#include <linux/mfd/motorola-cpcap.h>
#include <linux/spi/spi.h>
#define CPCAP_NR_IRQ_REG_BANKS 6
#define CPCAP_NR_IRQ_CHIPS 3
#define CPCAP_REGISTER_SIZE 4
#define CPCAP_REGISTER_BITS 16
struct cpcap_ddata {
struct spi_device *spi;
struct regmap_irq *irqs;
struct regmap_irq_chip_data *irqdata[CPCAP_NR_IRQ_CHIPS];
const struct regmap_config *regmap_conf;
struct regmap *regmap;
};
static int cpcap_sense_irq(struct regmap *regmap, int irq)
{
int regnum = irq / CPCAP_REGISTER_BITS;
int mask = BIT(irq % CPCAP_REGISTER_BITS);
int reg = CPCAP_REG_INTS1 + (regnum * CPCAP_REGISTER_SIZE);
int err, val;
if (reg < CPCAP_REG_INTS1 || reg > CPCAP_REG_INTS4)
return -EINVAL;
err = regmap_read(regmap, reg, &val);
if (err)
return err;
return !!(val & mask);
}
int cpcap_sense_virq(struct regmap *regmap, int virq)
{
struct regmap_irq_chip_data *d = irq_get_chip_data(virq);
int irq_base = regmap_irq_chip_get_base(d);
return cpcap_sense_irq(regmap, virq - irq_base);
}
EXPORT_SYMBOL_GPL(cpcap_sense_virq);
static int cpcap_check_revision(struct cpcap_ddata *cpcap)
{
u16 vendor, rev;
int ret;
ret = cpcap_get_vendor(&cpcap->spi->dev, cpcap->regmap, &vendor);
if (ret)
return ret;
ret = cpcap_get_revision(&cpcap->spi->dev, cpcap->regmap, &rev);
if (ret)
return ret;
dev_info(&cpcap->spi->dev, "CPCAP vendor: %s rev: %i.%i (%x)\n",
vendor == CPCAP_VENDOR_ST ? "ST" : "TI",
CPCAP_REVISION_MAJOR(rev), CPCAP_REVISION_MINOR(rev),
rev);
if (rev < CPCAP_REVISION_2_1) {
dev_info(&cpcap->spi->dev,
"Please add old CPCAP revision support as needed\n");
return -ENODEV;
}
return 0;
}
/*
* First two irq chips are the two private macro interrupt chips, the third
* irq chip is for register banks 1 - 4 and is available for drivers to use.
*/
static struct regmap_irq_chip cpcap_irq_chip[CPCAP_NR_IRQ_CHIPS] = {
{
.name = "cpcap-m2",
.num_regs = 1,
.status_base = CPCAP_REG_MI1,
.ack_base = CPCAP_REG_MI1,
.mask_base = CPCAP_REG_MIM1,
.use_ack = true,
.clear_ack = true,
},
{
.name = "cpcap-m2",
.num_regs = 1,
.status_base = CPCAP_REG_MI2,
.ack_base = CPCAP_REG_MI2,
.mask_base = CPCAP_REG_MIM2,
.use_ack = true,
.clear_ack = true,
},
{
.name = "cpcap1-4",
.num_regs = 4,
.status_base = CPCAP_REG_INT1,
.ack_base = CPCAP_REG_INT1,
.mask_base = CPCAP_REG_INTM1,
.use_ack = true,
.clear_ack = true,
},
};
static void cpcap_init_one_regmap_irq(struct cpcap_ddata *cpcap,
struct regmap_irq *rirq,
int irq_base, int irq)
{
unsigned int reg_offset;
unsigned int bit, mask;
reg_offset = irq - irq_base;
reg_offset /= cpcap->regmap_conf->val_bits;
reg_offset *= cpcap->regmap_conf->reg_stride;
bit = irq % cpcap->regmap_conf->val_bits;
mask = (1 << bit);
rirq->reg_offset = reg_offset;
rirq->mask = mask;
}
static int cpcap_init_irq_chip(struct cpcap_ddata *cpcap, int irq_chip,
int irq_start, int nr_irqs)
{
struct regmap_irq_chip *chip = &cpcap_irq_chip[irq_chip];
int i, ret;
for (i = irq_start; i < irq_start + nr_irqs; i++) {
struct regmap_irq *rirq = &cpcap->irqs[i];
cpcap_init_one_regmap_irq(cpcap, rirq, irq_start, i);
}
chip->irqs = &cpcap->irqs[irq_start];
chip->num_irqs = nr_irqs;
chip->irq_drv_data = cpcap;
ret = devm_regmap_add_irq_chip(&cpcap->spi->dev, cpcap->regmap,
cpcap->spi->irq,
irq_get_trigger_type(cpcap->spi->irq) |
IRQF_SHARED, -1,
chip, &cpcap->irqdata[irq_chip]);
if (ret) {
dev_err(&cpcap->spi->dev, "could not add irq chip %i: %i\n",
irq_chip, ret);
return ret;
}
return 0;
}
static int cpcap_init_irq(struct cpcap_ddata *cpcap)
{
int ret;
cpcap->irqs = devm_kzalloc(&cpcap->spi->dev,
array3_size(sizeof(*cpcap->irqs),
CPCAP_NR_IRQ_REG_BANKS,
cpcap->regmap_conf->val_bits),
GFP_KERNEL);
if (!cpcap->irqs)
return -ENOMEM;
ret = cpcap_init_irq_chip(cpcap, 0, 0, 16);
if (ret)
return ret;
ret = cpcap_init_irq_chip(cpcap, 1, 16, 16);
if (ret)
return ret;
ret = cpcap_init_irq_chip(cpcap, 2, 32, 64);
if (ret)
return ret;
enable_irq_wake(cpcap->spi->irq);
return 0;
}
static const struct of_device_id cpcap_of_match[] = {
{ .compatible = "motorola,cpcap", },
{ .compatible = "st,6556002", },
{},
};
MODULE_DEVICE_TABLE(of, cpcap_of_match);
static const struct spi_device_id cpcap_spi_ids[] = {
{ .name = "cpcap", },
{ .name = "6556002", },
{},
};
MODULE_DEVICE_TABLE(spi, cpcap_spi_ids);
static const struct regmap_config cpcap_regmap_config = {
.reg_bits = 16,
.reg_stride = 4,
.pad_bits = 0,
.val_bits = 16,
.write_flag_mask = 0x8000,
.max_register = CPCAP_REG_ST_TEST2,
.cache_type = REGCACHE_NONE,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
static int cpcap_suspend(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
disable_irq(spi->irq);
return 0;
}
static int cpcap_resume(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
enable_irq(spi->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(cpcap_pm, cpcap_suspend, cpcap_resume);
static const struct mfd_cell cpcap_mfd_devices[] = {
{
.name = "cpcap_adc",
.of_compatible = "motorola,mapphone-cpcap-adc",
}, {
.name = "cpcap_battery",
.of_compatible = "motorola,cpcap-battery",
}, {
.name = "cpcap-charger",
.of_compatible = "motorola,mapphone-cpcap-charger",
}, {
.name = "cpcap-regulator",
.of_compatible = "motorola,mapphone-cpcap-regulator",
}, {
.name = "cpcap-rtc",
.of_compatible = "motorola,cpcap-rtc",
}, {
.name = "cpcap-pwrbutton",
.of_compatible = "motorola,cpcap-pwrbutton",
}, {
.name = "cpcap-usb-phy",
.of_compatible = "motorola,mapphone-cpcap-usb-phy",
}, {
.name = "cpcap-led",
.id = 0,
.of_compatible = "motorola,cpcap-led-red",
}, {
.name = "cpcap-led",
.id = 1,
.of_compatible = "motorola,cpcap-led-green",
}, {
.name = "cpcap-led",
.id = 2,
.of_compatible = "motorola,cpcap-led-blue",
}, {
.name = "cpcap-led",
.id = 3,
.of_compatible = "motorola,cpcap-led-adl",
}, {
.name = "cpcap-led",
.id = 4,
.of_compatible = "motorola,cpcap-led-cp",
}, {
.name = "cpcap-codec",
}
};
static int cpcap_probe(struct spi_device *spi)
{
const struct of_device_id *match;
struct cpcap_ddata *cpcap;
int ret;
match = of_match_device(cpcap_of_match, &spi->dev);
if (!match)
return -ENODEV;
cpcap = devm_kzalloc(&spi->dev, sizeof(*cpcap), GFP_KERNEL);
if (!cpcap)
return -ENOMEM;
cpcap->spi = spi;
spi_set_drvdata(spi, cpcap);
spi->bits_per_word = 16;
spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
ret = spi_setup(spi);
if (ret)
return ret;
cpcap->regmap_conf = &cpcap_regmap_config;
cpcap->regmap = devm_regmap_init_spi(spi, &cpcap_regmap_config);
if (IS_ERR(cpcap->regmap)) {
ret = PTR_ERR(cpcap->regmap);
dev_err(&cpcap->spi->dev, "Failed to initialize regmap: %d\n",
ret);
return ret;
}
ret = cpcap_check_revision(cpcap);
if (ret) {
dev_err(&cpcap->spi->dev, "Failed to detect CPCAP: %i\n", ret);
return ret;
}
ret = cpcap_init_irq(cpcap);
if (ret)
return ret;
/* Parent SPI controller uses DMA, CPCAP and child devices do not */
spi->dev.coherent_dma_mask = 0;
spi->dev.dma_mask = &spi->dev.coherent_dma_mask;
return devm_mfd_add_devices(&spi->dev, 0, cpcap_mfd_devices,
ARRAY_SIZE(cpcap_mfd_devices), NULL, 0, NULL);
}
static struct spi_driver cpcap_driver = {
.driver = {
.name = "cpcap-core",
.of_match_table = cpcap_of_match,
.pm = pm_sleep_ptr(&cpcap_pm),
},
.probe = cpcap_probe,
.id_table = cpcap_spi_ids,
};
module_spi_driver(cpcap_driver);
MODULE_ALIAS("platform:cpcap");
MODULE_DESCRIPTION("CPCAP driver");
MODULE_AUTHOR("Tony Lindgren <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/motorola-cpcap.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AS3711 PMIC MFC driver
*
* Copyright (C) 2012 Renesas Electronics Corporation
* Author: Guennadi Liakhovetski, <[email protected]>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/as3711.h>
#include <linux/mfd/core.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
enum {
AS3711_REGULATOR,
AS3711_BACKLIGHT,
};
/*
* Ok to have it static: it is only used during probing and multiple I2C devices
* cannot be probed simultaneously. Just make sure to avoid stale data.
*/
static struct mfd_cell as3711_subdevs[] = {
[AS3711_REGULATOR] = {.name = "as3711-regulator",},
[AS3711_BACKLIGHT] = {.name = "as3711-backlight",},
};
static bool as3711_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AS3711_GPIO_SIGNAL_IN:
case AS3711_INTERRUPT_STATUS_1:
case AS3711_INTERRUPT_STATUS_2:
case AS3711_INTERRUPT_STATUS_3:
case AS3711_CHARGER_STATUS_1:
case AS3711_CHARGER_STATUS_2:
case AS3711_REG_STATUS:
return true;
}
return false;
}
static bool as3711_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AS3711_INTERRUPT_STATUS_1:
case AS3711_INTERRUPT_STATUS_2:
case AS3711_INTERRUPT_STATUS_3:
return true;
}
return false;
}
static bool as3711_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AS3711_SD_1_VOLTAGE:
case AS3711_SD_2_VOLTAGE:
case AS3711_SD_3_VOLTAGE:
case AS3711_SD_4_VOLTAGE:
case AS3711_LDO_1_VOLTAGE:
case AS3711_LDO_2_VOLTAGE:
case AS3711_LDO_3_VOLTAGE:
case AS3711_LDO_4_VOLTAGE:
case AS3711_LDO_5_VOLTAGE:
case AS3711_LDO_6_VOLTAGE:
case AS3711_LDO_7_VOLTAGE:
case AS3711_LDO_8_VOLTAGE:
case AS3711_SD_CONTROL:
case AS3711_GPIO_SIGNAL_OUT:
case AS3711_GPIO_SIGNAL_IN:
case AS3711_SD_CONTROL_1:
case AS3711_SD_CONTROL_2:
case AS3711_CURR_CONTROL:
case AS3711_CURR1_VALUE:
case AS3711_CURR2_VALUE:
case AS3711_CURR3_VALUE:
case AS3711_STEPUP_CONTROL_1:
case AS3711_STEPUP_CONTROL_2:
case AS3711_STEPUP_CONTROL_4:
case AS3711_STEPUP_CONTROL_5:
case AS3711_REG_STATUS:
case AS3711_INTERRUPT_STATUS_1:
case AS3711_INTERRUPT_STATUS_2:
case AS3711_INTERRUPT_STATUS_3:
case AS3711_CHARGER_STATUS_1:
case AS3711_CHARGER_STATUS_2:
case AS3711_ASIC_ID_1:
case AS3711_ASIC_ID_2:
return true;
}
return false;
}
static const struct regmap_config as3711_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = as3711_volatile_reg,
.readable_reg = as3711_readable_reg,
.precious_reg = as3711_precious_reg,
.max_register = AS3711_MAX_REG,
.num_reg_defaults_raw = AS3711_NUM_REGS,
.cache_type = REGCACHE_RBTREE,
};
#ifdef CONFIG_OF
static const struct of_device_id as3711_of_match[] = {
{.compatible = "ams,as3711",},
{}
};
#endif
static int as3711_i2c_probe(struct i2c_client *client)
{
struct as3711 *as3711;
struct as3711_platform_data *pdata;
unsigned int id1, id2;
int ret;
if (!client->dev.of_node) {
pdata = dev_get_platdata(&client->dev);
if (!pdata)
dev_dbg(&client->dev, "Platform data not found\n");
} else {
pdata = devm_kzalloc(&client->dev,
sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
}
as3711 = devm_kzalloc(&client->dev, sizeof(struct as3711), GFP_KERNEL);
if (!as3711)
return -ENOMEM;
as3711->dev = &client->dev;
i2c_set_clientdata(client, as3711);
if (client->irq)
dev_notice(&client->dev, "IRQ not supported yet\n");
as3711->regmap = devm_regmap_init_i2c(client, &as3711_regmap_config);
if (IS_ERR(as3711->regmap)) {
ret = PTR_ERR(as3711->regmap);
dev_err(&client->dev,
"regmap initialization failed: %d\n", ret);
return ret;
}
ret = regmap_read(as3711->regmap, AS3711_ASIC_ID_1, &id1);
if (!ret)
ret = regmap_read(as3711->regmap, AS3711_ASIC_ID_2, &id2);
if (ret < 0) {
dev_err(&client->dev, "regmap_read() failed: %d\n", ret);
return ret;
}
if (id1 != 0x8b)
return -ENODEV;
dev_info(as3711->dev, "AS3711 detected: %x:%x\n", id1, id2);
/*
* We can reuse as3711_subdevs[],
* it will be copied in mfd_add_devices()
*/
if (pdata) {
as3711_subdevs[AS3711_REGULATOR].platform_data =
&pdata->regulator;
as3711_subdevs[AS3711_REGULATOR].pdata_size =
sizeof(pdata->regulator);
as3711_subdevs[AS3711_BACKLIGHT].platform_data =
&pdata->backlight;
as3711_subdevs[AS3711_BACKLIGHT].pdata_size =
sizeof(pdata->backlight);
} else {
as3711_subdevs[AS3711_REGULATOR].platform_data = NULL;
as3711_subdevs[AS3711_REGULATOR].pdata_size = 0;
as3711_subdevs[AS3711_BACKLIGHT].platform_data = NULL;
as3711_subdevs[AS3711_BACKLIGHT].pdata_size = 0;
}
ret = devm_mfd_add_devices(as3711->dev, -1, as3711_subdevs,
ARRAY_SIZE(as3711_subdevs), NULL, 0, NULL);
if (ret < 0)
dev_err(&client->dev, "add mfd devices failed: %d\n", ret);
return ret;
}
static const struct i2c_device_id as3711_i2c_id[] = {
{.name = "as3711", .driver_data = 0},
{}
};
static struct i2c_driver as3711_i2c_driver = {
.driver = {
.name = "as3711",
.of_match_table = of_match_ptr(as3711_of_match),
},
.probe = as3711_i2c_probe,
.id_table = as3711_i2c_id,
};
static int __init as3711_i2c_init(void)
{
return i2c_add_driver(&as3711_i2c_driver);
}
/* Initialise early */
subsys_initcall(as3711_i2c_init);
| linux-master | drivers/mfd/as3711.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* I2C driver for Marvell 88PM860x
*
* Copyright (C) 2009 Marvell International Ltd.
*
* Author: Haojian Zhuang <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/mfd/88pm860x.h>
int pm860x_reg_read(struct i2c_client *i2c, int reg)
{
struct pm860x_chip *chip = i2c_get_clientdata(i2c);
struct regmap *map = (i2c == chip->client) ? chip->regmap
: chip->regmap_companion;
unsigned int data;
int ret;
ret = regmap_read(map, reg, &data);
if (ret < 0)
return ret;
else
return (int)data;
}
EXPORT_SYMBOL(pm860x_reg_read);
int pm860x_reg_write(struct i2c_client *i2c, int reg,
unsigned char data)
{
struct pm860x_chip *chip = i2c_get_clientdata(i2c);
struct regmap *map = (i2c == chip->client) ? chip->regmap
: chip->regmap_companion;
int ret;
ret = regmap_write(map, reg, data);
return ret;
}
EXPORT_SYMBOL(pm860x_reg_write);
int pm860x_bulk_read(struct i2c_client *i2c, int reg,
int count, unsigned char *buf)
{
struct pm860x_chip *chip = i2c_get_clientdata(i2c);
struct regmap *map = (i2c == chip->client) ? chip->regmap
: chip->regmap_companion;
int ret;
ret = regmap_raw_read(map, reg, buf, count);
return ret;
}
EXPORT_SYMBOL(pm860x_bulk_read);
int pm860x_bulk_write(struct i2c_client *i2c, int reg,
int count, unsigned char *buf)
{
struct pm860x_chip *chip = i2c_get_clientdata(i2c);
struct regmap *map = (i2c == chip->client) ? chip->regmap
: chip->regmap_companion;
int ret;
ret = regmap_raw_write(map, reg, buf, count);
return ret;
}
EXPORT_SYMBOL(pm860x_bulk_write);
int pm860x_set_bits(struct i2c_client *i2c, int reg,
unsigned char mask, unsigned char data)
{
struct pm860x_chip *chip = i2c_get_clientdata(i2c);
struct regmap *map = (i2c == chip->client) ? chip->regmap
: chip->regmap_companion;
int ret;
ret = regmap_update_bits(map, reg, mask, data);
return ret;
}
EXPORT_SYMBOL(pm860x_set_bits);
static int read_device(struct i2c_client *i2c, int reg,
int bytes, void *dest)
{
unsigned char msgbuf0[I2C_SMBUS_BLOCK_MAX + 3];
unsigned char msgbuf1[I2C_SMBUS_BLOCK_MAX + 2];
struct i2c_adapter *adap = i2c->adapter;
struct i2c_msg msg[2] = {
{
.addr = i2c->addr,
.flags = 0,
.len = 1,
.buf = msgbuf0
},
{ .addr = i2c->addr,
.flags = I2C_M_RD,
.len = 0,
.buf = msgbuf1
},
};
int num = 1, ret = 0;
if (dest == NULL)
return -EINVAL;
msgbuf0[0] = (unsigned char)reg; /* command */
msg[1].len = bytes;
/* if data needs to read back, num should be 2 */
if (bytes > 0)
num = 2;
ret = adap->algo->master_xfer(adap, msg, num);
memcpy(dest, msgbuf1, bytes);
if (ret < 0)
return ret;
return 0;
}
static int write_device(struct i2c_client *i2c, int reg,
int bytes, void *src)
{
unsigned char buf[2];
struct i2c_adapter *adap = i2c->adapter;
struct i2c_msg msg;
int ret;
buf[0] = (unsigned char)reg;
memcpy(&buf[1], src, bytes);
msg.addr = i2c->addr;
msg.flags = 0;
msg.len = bytes + 1;
msg.buf = buf;
ret = adap->algo->master_xfer(adap, &msg, 1);
if (ret < 0)
return ret;
return 0;
}
int pm860x_page_reg_write(struct i2c_client *i2c, int reg,
unsigned char data)
{
unsigned char zero;
int ret;
i2c_lock_bus(i2c->adapter, I2C_LOCK_SEGMENT);
read_device(i2c, 0xFA, 0, &zero);
read_device(i2c, 0xFB, 0, &zero);
read_device(i2c, 0xFF, 0, &zero);
ret = write_device(i2c, reg, 1, &data);
read_device(i2c, 0xFE, 0, &zero);
read_device(i2c, 0xFC, 0, &zero);
i2c_unlock_bus(i2c->adapter, I2C_LOCK_SEGMENT);
return ret;
}
EXPORT_SYMBOL(pm860x_page_reg_write);
int pm860x_page_bulk_read(struct i2c_client *i2c, int reg,
int count, unsigned char *buf)
{
unsigned char zero = 0;
int ret;
i2c_lock_bus(i2c->adapter, I2C_LOCK_SEGMENT);
read_device(i2c, 0xfa, 0, &zero);
read_device(i2c, 0xfb, 0, &zero);
read_device(i2c, 0xff, 0, &zero);
ret = read_device(i2c, reg, count, buf);
read_device(i2c, 0xFE, 0, &zero);
read_device(i2c, 0xFC, 0, &zero);
i2c_unlock_bus(i2c->adapter, I2C_LOCK_SEGMENT);
return ret;
}
EXPORT_SYMBOL(pm860x_page_bulk_read);
| linux-master | drivers/mfd/88pm860x-i2c.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* PM MFD driver for Broadcom BCM2835
*
* This driver binds to the PM block and creates the MFD device for
* the WDT and power drivers.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mfd/bcm2835-pm.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/watchdog.h>
static const struct mfd_cell bcm2835_pm_devs[] = {
{ .name = "bcm2835-wdt" },
};
static const struct mfd_cell bcm2835_power_devs[] = {
{ .name = "bcm2835-power" },
};
static int bcm2835_pm_get_pdata(struct platform_device *pdev,
struct bcm2835_pm *pm)
{
if (of_property_present(pm->dev->of_node, "reg-names")) {
struct resource *res;
pm->base = devm_platform_ioremap_resource_byname(pdev, "pm");
if (IS_ERR(pm->base))
return PTR_ERR(pm->base);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "asb");
if (res) {
pm->asb = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pm->asb))
pm->asb = NULL;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"rpivid_asb");
if (res) {
pm->rpivid_asb = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pm->rpivid_asb))
pm->rpivid_asb = NULL;
}
return 0;
}
/* If no 'reg-names' property is found we can assume we're using old DTB. */
pm->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pm->base))
return PTR_ERR(pm->base);
pm->asb = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(pm->asb))
pm->asb = NULL;
pm->rpivid_asb = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(pm->rpivid_asb))
pm->rpivid_asb = NULL;
return 0;
}
static int bcm2835_pm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct bcm2835_pm *pm;
int ret;
pm = devm_kzalloc(dev, sizeof(*pm), GFP_KERNEL);
if (!pm)
return -ENOMEM;
platform_set_drvdata(pdev, pm);
pm->dev = dev;
ret = bcm2835_pm_get_pdata(pdev, pm);
if (ret)
return ret;
ret = devm_mfd_add_devices(dev, -1,
bcm2835_pm_devs, ARRAY_SIZE(bcm2835_pm_devs),
NULL, 0, NULL);
if (ret)
return ret;
/*
* We'll use the presence of the AXI ASB regs in the
* bcm2835-pm binding as the key for whether we can reference
* the full PM register range and support power domains.
*/
if (pm->asb)
return devm_mfd_add_devices(dev, -1, bcm2835_power_devs,
ARRAY_SIZE(bcm2835_power_devs),
NULL, 0, NULL);
return 0;
}
static const struct of_device_id bcm2835_pm_of_match[] = {
{ .compatible = "brcm,bcm2835-pm-wdt", },
{ .compatible = "brcm,bcm2835-pm", },
{ .compatible = "brcm,bcm2711-pm", },
{},
};
MODULE_DEVICE_TABLE(of, bcm2835_pm_of_match);
static struct platform_driver bcm2835_pm_driver = {
.probe = bcm2835_pm_probe,
.driver = {
.name = "bcm2835-pm",
.of_match_table = bcm2835_pm_of_match,
},
};
module_platform_driver(bcm2835_pm_driver);
MODULE_AUTHOR("Eric Anholt <[email protected]>");
MODULE_DESCRIPTION("Driver for Broadcom BCM2835 PM MFD");
| linux-master | drivers/mfd/bcm2835-pm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MFD core driver for Ricoh RN5T618 PMIC
*
* Copyright (C) 2014 Beniamino Galvani <[email protected]>
* Copyright (C) 2016 Toradex AG
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rn5t618.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
static const struct mfd_cell rn5t618_cells[] = {
{ .name = "rn5t618-regulator" },
{ .name = "rn5t618-wdt" },
};
static const struct mfd_cell rc5t619_cells[] = {
{ .name = "rn5t618-adc" },
{ .name = "rn5t618-power" },
{ .name = "rn5t618-regulator" },
{ .name = "rc5t619-rtc" },
{ .name = "rn5t618-wdt" },
};
static bool rn5t618_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case RN5T618_WATCHDOGCNT:
case RN5T618_DCIRQ:
case RN5T618_ILIMDATAH ... RN5T618_AIN0DATAL:
case RN5T618_ADCCNT3:
case RN5T618_IR_ADC1 ... RN5T618_IR_ADC3:
case RN5T618_IR_GPR:
case RN5T618_IR_GPF:
case RN5T618_MON_IOIN:
case RN5T618_INTMON:
case RN5T618_RTC_CTRL1 ... RN5T618_RTC_CTRL2:
case RN5T618_RTC_SECONDS ... RN5T618_RTC_YEAR:
case RN5T618_CHGCTL1:
case RN5T618_REGISET1 ... RN5T618_REGISET2:
case RN5T618_CHGSTATE:
case RN5T618_CHGCTRL_IRR ... RN5T618_CHGERR_MONI:
case RN5T618_GCHGDET:
case RN5T618_CONTROL ... RN5T618_CC_AVEREG0:
return true;
default:
return false;
}
}
static const struct regmap_config rn5t618_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = rn5t618_volatile_reg,
.max_register = RN5T618_MAX_REG,
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_irq rc5t619_irqs[] = {
REGMAP_IRQ_REG(RN5T618_IRQ_SYS, 0, BIT(0)),
REGMAP_IRQ_REG(RN5T618_IRQ_DCDC, 0, BIT(1)),
REGMAP_IRQ_REG(RN5T618_IRQ_RTC, 0, BIT(2)),
REGMAP_IRQ_REG(RN5T618_IRQ_ADC, 0, BIT(3)),
REGMAP_IRQ_REG(RN5T618_IRQ_GPIO, 0, BIT(4)),
REGMAP_IRQ_REG(RN5T618_IRQ_CHG, 0, BIT(6)),
};
static const struct regmap_irq_chip rc5t619_irq_chip = {
.name = "rc5t619",
.irqs = rc5t619_irqs,
.num_irqs = ARRAY_SIZE(rc5t619_irqs),
.num_regs = 1,
.status_base = RN5T618_INTMON,
.unmask_base = RN5T618_INTEN,
};
static struct i2c_client *rn5t618_pm_power_off;
static struct notifier_block rn5t618_restart_handler;
static int rn5t618_irq_init(struct rn5t618 *rn5t618)
{
const struct regmap_irq_chip *irq_chip = NULL;
int ret;
if (!rn5t618->irq)
return 0;
switch (rn5t618->variant) {
case RC5T619:
irq_chip = &rc5t619_irq_chip;
break;
default:
dev_err(rn5t618->dev, "Currently no IRQ support for variant %d\n",
(int)rn5t618->variant);
return -ENOENT;
}
ret = devm_regmap_add_irq_chip(rn5t618->dev, rn5t618->regmap,
rn5t618->irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
0, irq_chip, &rn5t618->irq_data);
if (ret)
dev_err(rn5t618->dev, "Failed to register IRQ chip\n");
return ret;
}
static void rn5t618_trigger_poweroff_sequence(bool repower)
{
int ret;
/* disable automatic repower-on */
ret = i2c_smbus_read_byte_data(rn5t618_pm_power_off, RN5T618_REPCNT);
if (ret < 0)
goto err;
ret &= ~RN5T618_REPCNT_REPWRON;
if (repower)
ret |= RN5T618_REPCNT_REPWRON;
ret = i2c_smbus_write_byte_data(rn5t618_pm_power_off,
RN5T618_REPCNT, (u8)ret);
if (ret < 0)
goto err;
/* start power-off sequence */
ret = i2c_smbus_read_byte_data(rn5t618_pm_power_off, RN5T618_SLPCNT);
if (ret < 0)
goto err;
ret |= RN5T618_SLPCNT_SWPWROFF;
ret = i2c_smbus_write_byte_data(rn5t618_pm_power_off,
RN5T618_SLPCNT, (u8)ret);
if (ret < 0)
goto err;
return;
err:
dev_alert(&rn5t618_pm_power_off->dev, "Failed to shutdown (err = %d)\n", ret);
}
static void rn5t618_power_off(void)
{
rn5t618_trigger_poweroff_sequence(false);
}
static int rn5t618_restart(struct notifier_block *this,
unsigned long mode, void *cmd)
{
rn5t618_trigger_poweroff_sequence(true);
/*
* Re-power factor detection on PMIC side is not instant. 1ms
* proved to be enough time until reset takes effect.
*/
mdelay(1);
return NOTIFY_DONE;
}
static const struct of_device_id rn5t618_of_match[] = {
{ .compatible = "ricoh,rn5t567", .data = (void *)RN5T567 },
{ .compatible = "ricoh,rn5t618", .data = (void *)RN5T618 },
{ .compatible = "ricoh,rc5t619", .data = (void *)RC5T619 },
{ }
};
MODULE_DEVICE_TABLE(of, rn5t618_of_match);
static int rn5t618_i2c_probe(struct i2c_client *i2c)
{
const struct of_device_id *of_id;
struct rn5t618 *priv;
int ret;
of_id = of_match_device(rn5t618_of_match, &i2c->dev);
if (!of_id) {
dev_err(&i2c->dev, "Failed to find matching DT ID\n");
return -EINVAL;
}
priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
i2c_set_clientdata(i2c, priv);
priv->variant = (long)of_id->data;
priv->irq = i2c->irq;
priv->dev = &i2c->dev;
priv->regmap = devm_regmap_init_i2c(i2c, &rn5t618_regmap_config);
if (IS_ERR(priv->regmap)) {
ret = PTR_ERR(priv->regmap);
dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
return ret;
}
if (priv->variant == RC5T619)
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_NONE,
rc5t619_cells,
ARRAY_SIZE(rc5t619_cells),
NULL, 0, NULL);
else
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_NONE,
rn5t618_cells,
ARRAY_SIZE(rn5t618_cells),
NULL, 0, NULL);
if (ret) {
dev_err(&i2c->dev, "failed to add sub-devices: %d\n", ret);
return ret;
}
rn5t618_pm_power_off = i2c;
if (of_device_is_system_power_controller(i2c->dev.of_node)) {
if (!pm_power_off)
pm_power_off = rn5t618_power_off;
else
dev_warn(&i2c->dev, "Poweroff callback already assigned\n");
}
rn5t618_restart_handler.notifier_call = rn5t618_restart;
rn5t618_restart_handler.priority = 192;
ret = register_restart_handler(&rn5t618_restart_handler);
if (ret) {
dev_err(&i2c->dev, "cannot register restart handler, %d\n", ret);
return ret;
}
return rn5t618_irq_init(priv);
}
static void rn5t618_i2c_remove(struct i2c_client *i2c)
{
if (i2c == rn5t618_pm_power_off) {
rn5t618_pm_power_off = NULL;
pm_power_off = NULL;
}
unregister_restart_handler(&rn5t618_restart_handler);
}
static int __maybe_unused rn5t618_i2c_suspend(struct device *dev)
{
struct rn5t618 *priv = dev_get_drvdata(dev);
if (priv->irq)
disable_irq(priv->irq);
return 0;
}
static int __maybe_unused rn5t618_i2c_resume(struct device *dev)
{
struct rn5t618 *priv = dev_get_drvdata(dev);
if (priv->irq)
enable_irq(priv->irq);
return 0;
}
static SIMPLE_DEV_PM_OPS(rn5t618_i2c_dev_pm_ops,
rn5t618_i2c_suspend,
rn5t618_i2c_resume);
static struct i2c_driver rn5t618_i2c_driver = {
.driver = {
.name = "rn5t618",
.of_match_table = rn5t618_of_match,
.pm = &rn5t618_i2c_dev_pm_ops,
},
.probe = rn5t618_i2c_probe,
.remove = rn5t618_i2c_remove,
};
module_i2c_driver(rn5t618_i2c_driver);
MODULE_AUTHOR("Beniamino Galvani <[email protected]>");
MODULE_DESCRIPTION("Ricoh RN5T567/618 MFD driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/rn5t618.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/ssbi.h>
#include <linux/regmap.h>
#include <linux/of_platform.h>
#include <linux/mfd/core.h>
#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
#define PM8821_SSBI_REG(m, b, offset) \
((m == 0) ? \
(PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
(PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
#define PM8821_BLOCKS_PER_MASTER 7
#define PM_IRQF_LVL_SEL 0x01 /* level select */
#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
#define PM_IRQF_CLR 0x08 /* clear interrupt */
#define PM_IRQF_BITS_MASK 0x70
#define PM_IRQF_BITS_SHIFT 4
#define PM_IRQF_WRITE 0x80
#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
PM_IRQF_MASK_RE)
#define REG_HWREV 0x002 /* PMIC4 revision */
#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
#define PM8XXX_NR_IRQS 256
#define PM8821_NR_IRQS 112
struct pm_irq_data {
int num_irqs;
struct irq_chip *irq_chip;
irq_handler_t irq_handler;
};
struct pm_irq_chip {
struct regmap *regmap;
spinlock_t pm_irq_lock;
struct irq_domain *irqdomain;
unsigned int num_blocks;
unsigned int num_masters;
const struct pm_irq_data *pm_irq_data;
/* MUST BE AT THE END OF THIS STRUCT */
u8 config[];
};
static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
unsigned int *ip)
{
int rc;
spin_lock(&chip->pm_irq_lock);
rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
if (rc) {
pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
goto bail;
}
rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
if (rc)
pr_err("Failed Reading Status rc=%d\n", rc);
bail:
spin_unlock(&chip->pm_irq_lock);
return rc;
}
static int
pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
{
int rc;
unsigned long flags;
spin_lock_irqsave(&chip->pm_irq_lock, flags);
rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
if (rc) {
pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
goto bail;
}
cp |= PM_IRQF_WRITE;
rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
if (rc)
pr_err("Failed Configuring IRQ rc=%d\n", rc);
bail:
spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
return rc;
}
static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
{
int pmirq, i, ret = 0;
unsigned int bits;
ret = pm8xxx_read_block_irq(chip, block, &bits);
if (ret) {
pr_err("Failed reading %d block ret=%d", block, ret);
return ret;
}
if (!bits) {
pr_err("block bit set in master but no irqs: %d", block);
return 0;
}
/* Check IRQ bits */
for (i = 0; i < 8; i++) {
if (bits & (1 << i)) {
pmirq = block * 8 + i;
generic_handle_domain_irq(chip->irqdomain, pmirq);
}
}
return 0;
}
static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
{
unsigned int blockbits;
int block_number, i, ret = 0;
ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
&blockbits);
if (ret) {
pr_err("Failed to read master %d ret=%d\n", master, ret);
return ret;
}
if (!blockbits) {
pr_err("master bit set in root but no blocks: %d", master);
return 0;
}
for (i = 0; i < 8; i++)
if (blockbits & (1 << i)) {
block_number = master * 8 + i; /* block # */
ret |= pm8xxx_irq_block_handler(chip, block_number);
}
return ret;
}
static irqreturn_t pm8xxx_irq_handler(int irq, void *data)
{
struct pm_irq_chip *chip = data;
unsigned int root;
int i, ret, masters = 0;
ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
if (ret) {
pr_err("Can't read root status ret=%d\n", ret);
return IRQ_NONE;
}
/* on pm8xxx series masters start from bit 1 of the root */
masters = root >> 1;
/* Read allowed masters for blocks. */
for (i = 0; i < chip->num_masters; i++)
if (masters & (1 << i))
pm8xxx_irq_master_handler(chip, i);
return IRQ_HANDLED;
}
static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
int master, int block)
{
int pmirq, i, ret;
unsigned int bits;
ret = regmap_read(chip->regmap,
PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
if (ret) {
pr_err("Reading block %d failed ret=%d", block, ret);
return;
}
/* Convert block offset to global block number */
block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
/* Check IRQ bits */
for (i = 0; i < 8; i++) {
if (bits & BIT(i)) {
pmirq = block * 8 + i;
generic_handle_domain_irq(chip->irqdomain, pmirq);
}
}
}
static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
int master, u8 master_val)
{
int block;
for (block = 1; block < 8; block++)
if (master_val & BIT(block))
pm8821_irq_block_handler(chip, master, block);
}
static irqreturn_t pm8821_irq_handler(int irq, void *data)
{
struct pm_irq_chip *chip = data;
unsigned int master;
int ret;
ret = regmap_read(chip->regmap,
PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
if (ret) {
pr_err("Failed to read master 0 ret=%d\n", ret);
return IRQ_NONE;
}
/* bits 1 through 7 marks the first 7 blocks in master 0 */
if (master & GENMASK(7, 1))
pm8821_irq_master_handler(chip, 0, master);
/* bit 0 marks if master 1 contains any bits */
if (!(master & BIT(0)))
return IRQ_NONE;
ret = regmap_read(chip->regmap,
PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
if (ret) {
pr_err("Failed to read master 1 ret=%d\n", ret);
return IRQ_NONE;
}
pm8821_irq_master_handler(chip, 1, master);
return IRQ_HANDLED;
}
static void pm8xxx_irq_mask_ack(struct irq_data *d)
{
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
unsigned int pmirq = irqd_to_hwirq(d);
u8 block, config;
block = pmirq / 8;
config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
pm8xxx_config_irq(chip, block, config);
}
static void pm8xxx_irq_unmask(struct irq_data *d)
{
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
unsigned int pmirq = irqd_to_hwirq(d);
u8 block, config;
block = pmirq / 8;
config = chip->config[pmirq];
pm8xxx_config_irq(chip, block, config);
}
static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
unsigned int pmirq = irqd_to_hwirq(d);
int irq_bit;
u8 block, config;
block = pmirq / 8;
irq_bit = pmirq % 8;
chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
| PM_IRQF_MASK_ALL;
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
if (flow_type & IRQF_TRIGGER_RISING)
chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
if (flow_type & IRQF_TRIGGER_FALLING)
chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
} else {
chip->config[pmirq] |= PM_IRQF_LVL_SEL;
if (flow_type & IRQF_TRIGGER_HIGH)
chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
else
chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
}
config = chip->config[pmirq] | PM_IRQF_CLR;
return pm8xxx_config_irq(chip, block, config);
}
static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
enum irqchip_irq_state which,
bool *state)
{
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
unsigned int pmirq = irqd_to_hwirq(d);
unsigned int bits;
unsigned long flags;
int irq_bit;
u8 block;
int rc;
if (which != IRQCHIP_STATE_LINE_LEVEL)
return -EINVAL;
block = pmirq / 8;
irq_bit = pmirq % 8;
spin_lock_irqsave(&chip->pm_irq_lock, flags);
rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
if (rc) {
pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
goto bail;
}
rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
if (rc) {
pr_err("Failed Reading Status rc=%d\n", rc);
goto bail;
}
*state = !!(bits & BIT(irq_bit));
bail:
spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
return rc;
}
static struct irq_chip pm8xxx_irq_chip = {
.name = "pm8xxx",
.irq_mask_ack = pm8xxx_irq_mask_ack,
.irq_unmask = pm8xxx_irq_unmask,
.irq_set_type = pm8xxx_irq_set_type,
.irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};
static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq, unsigned int type)
{
irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
chip, handle_level_irq, NULL, NULL);
irq_set_noprobe(irq);
}
static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *data)
{
struct pm_irq_chip *chip = domain->host_data;
struct irq_fwspec *fwspec = data;
irq_hw_number_t hwirq;
unsigned int type;
int ret, i;
ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
if (ret)
return ret;
for (i = 0; i < nr_irqs; i++)
pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
return 0;
}
static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
.alloc = pm8xxx_irq_domain_alloc,
.free = irq_domain_free_irqs_common,
.translate = irq_domain_translate_twocell,
};
static void pm8821_irq_mask_ack(struct irq_data *d)
{
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
unsigned int pmirq = irqd_to_hwirq(d);
u8 block, master;
int irq_bit, rc;
block = pmirq / 8;
master = block / PM8821_BLOCKS_PER_MASTER;
irq_bit = pmirq % 8;
block %= PM8821_BLOCKS_PER_MASTER;
rc = regmap_update_bits(chip->regmap,
PM8821_SSBI_ADDR_IRQ_MASK(master, block),
BIT(irq_bit), BIT(irq_bit));
if (rc) {
pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
return;
}
rc = regmap_update_bits(chip->regmap,
PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
BIT(irq_bit), BIT(irq_bit));
if (rc)
pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
}
static void pm8821_irq_unmask(struct irq_data *d)
{
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
unsigned int pmirq = irqd_to_hwirq(d);
int irq_bit, rc;
u8 block, master;
block = pmirq / 8;
master = block / PM8821_BLOCKS_PER_MASTER;
irq_bit = pmirq % 8;
block %= PM8821_BLOCKS_PER_MASTER;
rc = regmap_update_bits(chip->regmap,
PM8821_SSBI_ADDR_IRQ_MASK(master, block),
BIT(irq_bit), ~BIT(irq_bit));
if (rc)
pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
}
static int pm8821_irq_get_irqchip_state(struct irq_data *d,
enum irqchip_irq_state which,
bool *state)
{
struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
int rc, pmirq = irqd_to_hwirq(d);
u8 block, irq_bit, master;
unsigned int bits;
block = pmirq / 8;
master = block / PM8821_BLOCKS_PER_MASTER;
irq_bit = pmirq % 8;
block %= PM8821_BLOCKS_PER_MASTER;
rc = regmap_read(chip->regmap,
PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
if (rc) {
pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
return rc;
}
*state = !!(bits & BIT(irq_bit));
return rc;
}
static struct irq_chip pm8821_irq_chip = {
.name = "pm8821",
.irq_mask_ack = pm8821_irq_mask_ack,
.irq_unmask = pm8821_irq_unmask,
.irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};
static const struct regmap_config ssbi_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = 0x3ff,
.fast_io = true,
.reg_read = ssbi_reg_read,
.reg_write = ssbi_reg_write
};
static const struct pm_irq_data pm8xxx_data = {
.num_irqs = PM8XXX_NR_IRQS,
.irq_chip = &pm8xxx_irq_chip,
.irq_handler = pm8xxx_irq_handler,
};
static const struct pm_irq_data pm8821_data = {
.num_irqs = PM8821_NR_IRQS,
.irq_chip = &pm8821_irq_chip,
.irq_handler = pm8821_irq_handler,
};
static const struct of_device_id pm8xxx_id_table[] = {
{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
{ .compatible = "qcom,pm8821", .data = &pm8821_data},
{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
{ }
};
MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
static int pm8xxx_probe(struct platform_device *pdev)
{
const struct pm_irq_data *data;
struct regmap *regmap;
int irq, rc;
unsigned int val;
struct pm_irq_chip *chip;
data = of_device_get_match_data(&pdev->dev);
if (!data) {
dev_err(&pdev->dev, "No matching driver data found\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
&ssbi_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Read PMIC chip revision */
rc = regmap_read(regmap, REG_HWREV, &val);
if (rc) {
pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
return rc;
}
pr_info("PMIC revision 1: %02X\n", val);
/* Read PMIC chip revision 2 */
rc = regmap_read(regmap, REG_HWREV_2, &val);
if (rc) {
pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
REG_HWREV_2, rc);
return rc;
}
pr_info("PMIC revision 2: %02X\n", val);
chip = devm_kzalloc(&pdev->dev,
struct_size(chip, config, data->num_irqs),
GFP_KERNEL);
if (!chip)
return -ENOMEM;
platform_set_drvdata(pdev, chip);
chip->regmap = regmap;
chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
chip->pm_irq_data = data;
spin_lock_init(&chip->pm_irq_lock);
chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
data->num_irqs,
&pm8xxx_irq_domain_ops,
chip);
if (!chip->irqdomain)
return -ENODEV;
rc = devm_request_irq(&pdev->dev, irq, data->irq_handler, 0, dev_name(&pdev->dev), chip);
if (rc)
return rc;
irq_set_irq_wake(irq, 1);
rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
if (rc)
irq_domain_remove(chip->irqdomain);
return rc;
}
static int pm8xxx_remove_child(struct device *dev, void *unused)
{
platform_device_unregister(to_platform_device(dev));
return 0;
}
static int pm8xxx_remove(struct platform_device *pdev)
{
struct pm_irq_chip *chip = platform_get_drvdata(pdev);
device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
irq_domain_remove(chip->irqdomain);
return 0;
}
static struct platform_driver pm8xxx_driver = {
.probe = pm8xxx_probe,
.remove = pm8xxx_remove,
.driver = {
.name = "pm8xxx-core",
.of_match_table = pm8xxx_id_table,
},
};
static int __init pm8xxx_init(void)
{
return platform_driver_register(&pm8xxx_driver);
}
subsys_initcall(pm8xxx_init);
static void __exit pm8xxx_exit(void)
{
platform_driver_unregister(&pm8xxx_driver);
}
module_exit(pm8xxx_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("PMIC 8xxx core driver");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:pm8xxx-core");
| linux-master | drivers/mfd/qcom-pm8xxx.c |
// SPDX-License-Identifier: GPL-2.0+
//
// max77693.c - mfd core driver for the MAX 77693
//
// Copyright (C) 2012 Samsung Electronics
// SangYoung Son <[email protected]>
//
// This program is not provided / owned by Maxim Integrated Products.
//
// This driver is based on max8997.c
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/pm_runtime.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max77693.h>
#include <linux/mfd/max77693-common.h>
#include <linux/mfd/max77693-private.h>
#include <linux/regulator/machine.h>
#include <linux/regmap.h>
#define I2C_ADDR_PMIC (0xCC >> 1) /* Charger, Flash LED */
#define I2C_ADDR_MUIC (0x4A >> 1)
#define I2C_ADDR_HAPTIC (0x90 >> 1)
static const struct mfd_cell max77693_devs[] = {
{ .name = "max77693-pmic", },
{
.name = "max77693-charger",
.of_compatible = "maxim,max77693-charger",
},
{
.name = "max77693-muic",
.of_compatible = "maxim,max77693-muic",
},
{
.name = "max77693-haptic",
.of_compatible = "maxim,max77693-haptic",
},
{
.name = "max77693-led",
.of_compatible = "maxim,max77693-led",
},
};
static const struct regmap_config max77693_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX77693_PMIC_REG_END,
};
static const struct regmap_irq max77693_led_irqs[] = {
{ .mask = LED_IRQ_FLED2_OPEN, },
{ .mask = LED_IRQ_FLED2_SHORT, },
{ .mask = LED_IRQ_FLED1_OPEN, },
{ .mask = LED_IRQ_FLED1_SHORT, },
{ .mask = LED_IRQ_MAX_FLASH, },
};
static const struct regmap_irq_chip max77693_led_irq_chip = {
.name = "max77693-led",
.status_base = MAX77693_LED_REG_FLASH_INT,
.mask_base = MAX77693_LED_REG_FLASH_INT_MASK,
.num_regs = 1,
.irqs = max77693_led_irqs,
.num_irqs = ARRAY_SIZE(max77693_led_irqs),
};
static const struct regmap_irq max77693_topsys_irqs[] = {
{ .mask = TOPSYS_IRQ_T120C_INT, },
{ .mask = TOPSYS_IRQ_T140C_INT, },
{ .mask = TOPSYS_IRQ_LOWSYS_INT, },
};
static const struct regmap_irq_chip max77693_topsys_irq_chip = {
.name = "max77693-topsys",
.status_base = MAX77693_PMIC_REG_TOPSYS_INT,
.mask_base = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
.num_regs = 1,
.irqs = max77693_topsys_irqs,
.num_irqs = ARRAY_SIZE(max77693_topsys_irqs),
};
static const struct regmap_irq max77693_charger_irqs[] = {
{ .mask = CHG_IRQ_BYP_I, },
{ .mask = CHG_IRQ_THM_I, },
{ .mask = CHG_IRQ_BAT_I, },
{ .mask = CHG_IRQ_CHG_I, },
{ .mask = CHG_IRQ_CHGIN_I, },
};
static const struct regmap_irq_chip max77693_charger_irq_chip = {
.name = "max77693-charger",
.status_base = MAX77693_CHG_REG_CHG_INT,
.mask_base = MAX77693_CHG_REG_CHG_INT_MASK,
.num_regs = 1,
.irqs = max77693_charger_irqs,
.num_irqs = ARRAY_SIZE(max77693_charger_irqs),
};
static const struct regmap_config max77693_regmap_muic_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX77693_MUIC_REG_END,
};
static const struct regmap_irq max77693_muic_irqs[] = {
{ .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, },
{ .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, },
{ .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, },
{ .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, },
{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, },
{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, },
{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, },
{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, },
{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, },
{ .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, },
{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_EOC, },
{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_CGMBC, },
{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_OVP, },
{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_MBCCHG_ERR, },
{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_CHG_ENABLED, },
{ .reg_offset = 2, .mask = MUIC_IRQ_INT3_BAT_DET, },
};
static const struct regmap_irq_chip max77693_muic_irq_chip = {
.name = "max77693-muic",
.status_base = MAX77693_MUIC_REG_INT1,
.unmask_base = MAX77693_MUIC_REG_INTMASK1,
.num_regs = 3,
.irqs = max77693_muic_irqs,
.num_irqs = ARRAY_SIZE(max77693_muic_irqs),
};
static const struct regmap_config max77693_regmap_haptic_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX77693_HAPTIC_REG_END,
};
static int max77693_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct max77693_dev *max77693;
unsigned int reg_data;
int ret = 0;
max77693 = devm_kzalloc(&i2c->dev,
sizeof(struct max77693_dev), GFP_KERNEL);
if (max77693 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, max77693);
max77693->dev = &i2c->dev;
max77693->i2c = i2c;
max77693->irq = i2c->irq;
max77693->type = id->driver_data;
max77693->regmap = devm_regmap_init_i2c(i2c, &max77693_regmap_config);
if (IS_ERR(max77693->regmap)) {
ret = PTR_ERR(max77693->regmap);
dev_err(max77693->dev, "failed to allocate register map: %d\n",
ret);
return ret;
}
ret = regmap_read(max77693->regmap, MAX77693_PMIC_REG_PMIC_ID2,
®_data);
if (ret < 0) {
dev_err(max77693->dev, "device not found on this channel\n");
return ret;
} else
dev_info(max77693->dev, "device ID: 0x%x\n", reg_data);
max77693->i2c_muic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_MUIC);
if (IS_ERR(max77693->i2c_muic)) {
dev_err(max77693->dev, "Failed to allocate I2C device for MUIC\n");
return PTR_ERR(max77693->i2c_muic);
}
i2c_set_clientdata(max77693->i2c_muic, max77693);
max77693->i2c_haptic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_HAPTIC);
if (IS_ERR(max77693->i2c_haptic)) {
dev_err(max77693->dev, "Failed to allocate I2C device for Haptic\n");
ret = PTR_ERR(max77693->i2c_haptic);
goto err_i2c_haptic;
}
i2c_set_clientdata(max77693->i2c_haptic, max77693);
max77693->regmap_haptic = devm_regmap_init_i2c(max77693->i2c_haptic,
&max77693_regmap_haptic_config);
if (IS_ERR(max77693->regmap_haptic)) {
ret = PTR_ERR(max77693->regmap_haptic);
dev_err(max77693->dev,
"failed to initialize haptic register map: %d\n", ret);
goto err_regmap;
}
/*
* Initialize register map for MUIC device because use regmap-muic
* instance of MUIC device when irq of max77693 is initialized
* before call max77693-muic probe() function.
*/
max77693->regmap_muic = devm_regmap_init_i2c(max77693->i2c_muic,
&max77693_regmap_muic_config);
if (IS_ERR(max77693->regmap_muic)) {
ret = PTR_ERR(max77693->regmap_muic);
dev_err(max77693->dev,
"failed to allocate register map: %d\n", ret);
goto err_regmap;
}
ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77693_led_irq_chip,
&max77693->irq_data_led);
if (ret) {
dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
goto err_regmap;
}
ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77693_topsys_irq_chip,
&max77693->irq_data_topsys);
if (ret) {
dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
goto err_irq_topsys;
}
ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77693_charger_irq_chip,
&max77693->irq_data_chg);
if (ret) {
dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
goto err_irq_charger;
}
ret = regmap_add_irq_chip(max77693->regmap_muic, max77693->irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77693_muic_irq_chip,
&max77693->irq_data_muic);
if (ret) {
dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
goto err_irq_muic;
}
/* Unmask interrupts from all blocks in interrupt source register */
ret = regmap_update_bits(max77693->regmap,
MAX77693_PMIC_REG_INTSRC_MASK,
SRC_IRQ_ALL, (unsigned int)~SRC_IRQ_ALL);
if (ret < 0) {
dev_err(max77693->dev,
"Could not unmask interrupts in INTSRC: %d\n",
ret);
goto err_intsrc;
}
pm_runtime_set_active(max77693->dev);
ret = mfd_add_devices(max77693->dev, -1, max77693_devs,
ARRAY_SIZE(max77693_devs), NULL, 0, NULL);
if (ret < 0)
goto err_mfd;
return ret;
err_mfd:
mfd_remove_devices(max77693->dev);
err_intsrc:
regmap_del_irq_chip(max77693->irq, max77693->irq_data_muic);
err_irq_muic:
regmap_del_irq_chip(max77693->irq, max77693->irq_data_chg);
err_irq_charger:
regmap_del_irq_chip(max77693->irq, max77693->irq_data_topsys);
err_irq_topsys:
regmap_del_irq_chip(max77693->irq, max77693->irq_data_led);
err_regmap:
i2c_unregister_device(max77693->i2c_haptic);
err_i2c_haptic:
i2c_unregister_device(max77693->i2c_muic);
return ret;
}
static void max77693_i2c_remove(struct i2c_client *i2c)
{
struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
mfd_remove_devices(max77693->dev);
regmap_del_irq_chip(max77693->irq, max77693->irq_data_muic);
regmap_del_irq_chip(max77693->irq, max77693->irq_data_chg);
regmap_del_irq_chip(max77693->irq, max77693->irq_data_topsys);
regmap_del_irq_chip(max77693->irq, max77693->irq_data_led);
i2c_unregister_device(max77693->i2c_muic);
i2c_unregister_device(max77693->i2c_haptic);
}
static const struct i2c_device_id max77693_i2c_id[] = {
{ "max77693", TYPE_MAX77693 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max77693_i2c_id);
static int max77693_suspend(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev)) {
enable_irq_wake(max77693->irq);
disable_irq(max77693->irq);
}
return 0;
}
static int max77693_resume(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev)) {
disable_irq_wake(max77693->irq);
enable_irq(max77693->irq);
}
return 0;
}
static const struct dev_pm_ops max77693_pm = {
.suspend = max77693_suspend,
.resume = max77693_resume,
};
#ifdef CONFIG_OF
static const struct of_device_id max77693_dt_match[] = {
{ .compatible = "maxim,max77693" },
{},
};
MODULE_DEVICE_TABLE(of, max77693_dt_match);
#endif
static struct i2c_driver max77693_i2c_driver = {
.driver = {
.name = "max77693",
.pm = &max77693_pm,
.of_match_table = of_match_ptr(max77693_dt_match),
},
.probe = max77693_i2c_probe,
.remove = max77693_i2c_remove,
.id_table = max77693_i2c_id,
};
module_i2c_driver(max77693_i2c_driver);
MODULE_DESCRIPTION("MAXIM 77693 multi-function core driver");
MODULE_AUTHOR("SangYoung, Son <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/max77693.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Rockchip RK806 Core (SPI) driver
*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 Collabora Ltd.
*
* Author: Xu Shengfei <[email protected]>
* Author: Sebastian Reichel <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rk808.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#define RK806_ADDR_SIZE 2
#define RK806_CMD_WITH_SIZE(CMD, VALUE_BYTES) \
(RK806_CMD_##CMD | RK806_CMD_CRC_DIS | (VALUE_BYTES - 1))
static const struct regmap_range rk806_volatile_ranges[] = {
regmap_reg_range(RK806_POWER_EN0, RK806_POWER_EN5),
regmap_reg_range(RK806_DVS_START_CTRL, RK806_INT_MSK1),
};
static const struct regmap_access_table rk806_volatile_table = {
.yes_ranges = rk806_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(rk806_volatile_ranges),
};
static const struct regmap_config rk806_regmap_config_spi = {
.reg_bits = 16,
.val_bits = 8,
.max_register = RK806_BUCK_RSERVE_REG5,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &rk806_volatile_table,
};
static int rk806_spi_bus_write(void *context, const void *vdata, size_t count)
{
struct device *dev = context;
struct spi_device *spi = to_spi_device(dev);
struct spi_transfer xfer[2] = { 0 };
/* data and thus count includes the register address */
size_t val_size = count - RK806_ADDR_SIZE;
char cmd;
if (val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1))
return -EINVAL;
cmd = RK806_CMD_WITH_SIZE(WRITE, val_size);
xfer[0].tx_buf = &cmd;
xfer[0].len = sizeof(cmd);
xfer[1].tx_buf = vdata;
xfer[1].len = count;
return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
}
static int rk806_spi_bus_read(void *context, const void *vreg, size_t reg_size,
void *val, size_t val_size)
{
struct device *dev = context;
struct spi_device *spi = to_spi_device(dev);
char txbuf[3] = { 0 };
if (reg_size != RK806_ADDR_SIZE ||
val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1))
return -EINVAL;
/* TX buffer contains command byte followed by two address bytes */
txbuf[0] = RK806_CMD_WITH_SIZE(READ, val_size);
memcpy(txbuf+1, vreg, reg_size);
return spi_write_then_read(spi, txbuf, sizeof(txbuf), val, val_size);
}
static const struct regmap_bus rk806_regmap_bus_spi = {
.write = rk806_spi_bus_write,
.read = rk806_spi_bus_read,
.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
};
static int rk8xx_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
regmap = devm_regmap_init(&spi->dev, &rk806_regmap_bus_spi,
&spi->dev, &rk806_regmap_config_spi);
if (IS_ERR(regmap))
return dev_err_probe(&spi->dev, PTR_ERR(regmap),
"Failed to init regmap\n");
return rk8xx_probe(&spi->dev, RK806_ID, spi->irq, regmap);
}
static const struct of_device_id rk8xx_spi_of_match[] = {
{ .compatible = "rockchip,rk806", },
{ }
};
MODULE_DEVICE_TABLE(of, rk8xx_spi_of_match);
static const struct spi_device_id rk8xx_spi_id_table[] = {
{ "rk806", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, rk8xx_spi_id_table);
static struct spi_driver rk8xx_spi_driver = {
.driver = {
.name = "rk8xx-spi",
.of_match_table = rk8xx_spi_of_match,
},
.probe = rk8xx_spi_probe,
.id_table = rk8xx_spi_id_table,
};
module_spi_driver(rk8xx_spi_driver);
MODULE_AUTHOR("Xu Shengfei <[email protected]>");
MODULE_DESCRIPTION("RK8xx SPI PMIC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/rk8xx-spi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8350-irq.c -- IRQ support for Wolfson WM8350
*
* Copyright 2007, 2008, 2009 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood, Mark Brown
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/bug.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/comparator.h>
#include <linux/mfd/wm8350/gpio.h>
#include <linux/mfd/wm8350/pmic.h>
#include <linux/mfd/wm8350/rtc.h>
#include <linux/mfd/wm8350/supply.h>
#include <linux/mfd/wm8350/wdt.h>
#define WM8350_INT_OFFSET_1 0
#define WM8350_INT_OFFSET_2 1
#define WM8350_POWER_UP_INT_OFFSET 2
#define WM8350_UNDER_VOLTAGE_INT_OFFSET 3
#define WM8350_OVER_CURRENT_INT_OFFSET 4
#define WM8350_GPIO_INT_OFFSET 5
#define WM8350_COMPARATOR_INT_OFFSET 6
struct wm8350_irq_data {
int primary;
int reg;
int mask;
int primary_only;
};
static struct wm8350_irq_data wm8350_irqs[] = {
[WM8350_IRQ_OC_LS] = {
.primary = WM8350_OC_INT,
.reg = WM8350_OVER_CURRENT_INT_OFFSET,
.mask = WM8350_OC_LS_EINT,
.primary_only = 1,
},
[WM8350_IRQ_UV_DC1] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_DC1_EINT,
},
[WM8350_IRQ_UV_DC2] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_DC2_EINT,
},
[WM8350_IRQ_UV_DC3] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_DC3_EINT,
},
[WM8350_IRQ_UV_DC4] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_DC4_EINT,
},
[WM8350_IRQ_UV_DC5] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_DC5_EINT,
},
[WM8350_IRQ_UV_DC6] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_DC6_EINT,
},
[WM8350_IRQ_UV_LDO1] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_LDO1_EINT,
},
[WM8350_IRQ_UV_LDO2] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_LDO2_EINT,
},
[WM8350_IRQ_UV_LDO3] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_LDO3_EINT,
},
[WM8350_IRQ_UV_LDO4] = {
.primary = WM8350_UV_INT,
.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
.mask = WM8350_UV_LDO4_EINT,
},
[WM8350_IRQ_CHG_BAT_HOT] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_BAT_HOT_EINT,
},
[WM8350_IRQ_CHG_BAT_COLD] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_BAT_COLD_EINT,
},
[WM8350_IRQ_CHG_BAT_FAIL] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_BAT_FAIL_EINT,
},
[WM8350_IRQ_CHG_TO] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_TO_EINT,
},
[WM8350_IRQ_CHG_END] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_END_EINT,
},
[WM8350_IRQ_CHG_START] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_START_EINT,
},
[WM8350_IRQ_CHG_FAST_RDY] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_FAST_RDY_EINT,
},
[WM8350_IRQ_CHG_VBATT_LT_3P9] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_VBATT_LT_3P9_EINT,
},
[WM8350_IRQ_CHG_VBATT_LT_3P1] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_VBATT_LT_3P1_EINT,
},
[WM8350_IRQ_CHG_VBATT_LT_2P85] = {
.primary = WM8350_CHG_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_CHG_VBATT_LT_2P85_EINT,
},
[WM8350_IRQ_RTC_ALM] = {
.primary = WM8350_RTC_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_RTC_ALM_EINT,
},
[WM8350_IRQ_RTC_SEC] = {
.primary = WM8350_RTC_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_RTC_SEC_EINT,
},
[WM8350_IRQ_RTC_PER] = {
.primary = WM8350_RTC_INT,
.reg = WM8350_INT_OFFSET_1,
.mask = WM8350_RTC_PER_EINT,
},
[WM8350_IRQ_CS1] = {
.primary = WM8350_CS_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_CS1_EINT,
},
[WM8350_IRQ_CS2] = {
.primary = WM8350_CS_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_CS2_EINT,
},
[WM8350_IRQ_SYS_HYST_COMP_FAIL] = {
.primary = WM8350_SYS_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_SYS_HYST_COMP_FAIL_EINT,
},
[WM8350_IRQ_SYS_CHIP_GT115] = {
.primary = WM8350_SYS_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_SYS_CHIP_GT115_EINT,
},
[WM8350_IRQ_SYS_CHIP_GT140] = {
.primary = WM8350_SYS_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_SYS_CHIP_GT140_EINT,
},
[WM8350_IRQ_SYS_WDOG_TO] = {
.primary = WM8350_SYS_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_SYS_WDOG_TO_EINT,
},
[WM8350_IRQ_AUXADC_DATARDY] = {
.primary = WM8350_AUXADC_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_AUXADC_DATARDY_EINT,
},
[WM8350_IRQ_AUXADC_DCOMP4] = {
.primary = WM8350_AUXADC_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_AUXADC_DCOMP4_EINT,
},
[WM8350_IRQ_AUXADC_DCOMP3] = {
.primary = WM8350_AUXADC_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_AUXADC_DCOMP3_EINT,
},
[WM8350_IRQ_AUXADC_DCOMP2] = {
.primary = WM8350_AUXADC_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_AUXADC_DCOMP2_EINT,
},
[WM8350_IRQ_AUXADC_DCOMP1] = {
.primary = WM8350_AUXADC_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_AUXADC_DCOMP1_EINT,
},
[WM8350_IRQ_USB_LIMIT] = {
.primary = WM8350_USB_INT,
.reg = WM8350_INT_OFFSET_2,
.mask = WM8350_USB_LIMIT_EINT,
.primary_only = 1,
},
[WM8350_IRQ_WKUP_OFF_STATE] = {
.primary = WM8350_WKUP_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_WKUP_OFF_STATE_EINT,
},
[WM8350_IRQ_WKUP_HIB_STATE] = {
.primary = WM8350_WKUP_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_WKUP_HIB_STATE_EINT,
},
[WM8350_IRQ_WKUP_CONV_FAULT] = {
.primary = WM8350_WKUP_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_WKUP_CONV_FAULT_EINT,
},
[WM8350_IRQ_WKUP_WDOG_RST] = {
.primary = WM8350_WKUP_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_WKUP_WDOG_RST_EINT,
},
[WM8350_IRQ_WKUP_GP_PWR_ON] = {
.primary = WM8350_WKUP_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_WKUP_GP_PWR_ON_EINT,
},
[WM8350_IRQ_WKUP_ONKEY] = {
.primary = WM8350_WKUP_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_WKUP_ONKEY_EINT,
},
[WM8350_IRQ_WKUP_GP_WAKEUP] = {
.primary = WM8350_WKUP_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_WKUP_GP_WAKEUP_EINT,
},
[WM8350_IRQ_CODEC_JCK_DET_L] = {
.primary = WM8350_CODEC_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_CODEC_JCK_DET_L_EINT,
},
[WM8350_IRQ_CODEC_JCK_DET_R] = {
.primary = WM8350_CODEC_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_CODEC_JCK_DET_R_EINT,
},
[WM8350_IRQ_CODEC_MICSCD] = {
.primary = WM8350_CODEC_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_CODEC_MICSCD_EINT,
},
[WM8350_IRQ_CODEC_MICD] = {
.primary = WM8350_CODEC_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_CODEC_MICD_EINT,
},
[WM8350_IRQ_EXT_USB_FB] = {
.primary = WM8350_EXT_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_EXT_USB_FB_EINT,
},
[WM8350_IRQ_EXT_WALL_FB] = {
.primary = WM8350_EXT_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_EXT_WALL_FB_EINT,
},
[WM8350_IRQ_EXT_BAT_FB] = {
.primary = WM8350_EXT_INT,
.reg = WM8350_COMPARATOR_INT_OFFSET,
.mask = WM8350_EXT_BAT_FB_EINT,
},
[WM8350_IRQ_GPIO(0)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP0_EINT,
},
[WM8350_IRQ_GPIO(1)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP1_EINT,
},
[WM8350_IRQ_GPIO(2)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP2_EINT,
},
[WM8350_IRQ_GPIO(3)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP3_EINT,
},
[WM8350_IRQ_GPIO(4)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP4_EINT,
},
[WM8350_IRQ_GPIO(5)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP5_EINT,
},
[WM8350_IRQ_GPIO(6)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP6_EINT,
},
[WM8350_IRQ_GPIO(7)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP7_EINT,
},
[WM8350_IRQ_GPIO(8)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP8_EINT,
},
[WM8350_IRQ_GPIO(9)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP9_EINT,
},
[WM8350_IRQ_GPIO(10)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP10_EINT,
},
[WM8350_IRQ_GPIO(11)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP11_EINT,
},
[WM8350_IRQ_GPIO(12)] = {
.primary = WM8350_GP_INT,
.reg = WM8350_GPIO_INT_OFFSET,
.mask = WM8350_GP12_EINT,
},
};
static inline struct wm8350_irq_data *irq_to_wm8350_irq(struct wm8350 *wm8350,
int irq)
{
return &wm8350_irqs[irq - wm8350->irq_base];
}
/*
* This is a threaded IRQ handler so can access I2C/SPI. Since all
* interrupts are clear on read the IRQ line will be reasserted and
* the physical IRQ will be handled again if another interrupt is
* asserted while we run - in the normal course of events this is a
* rare occurrence so we save I2C/SPI reads. We're also assuming that
* it's rare to get lots of interrupts firing simultaneously so try to
* minimise I/O.
*/
static irqreturn_t wm8350_irq(int irq, void *irq_data)
{
struct wm8350 *wm8350 = irq_data;
u16 level_one;
u16 sub_reg[WM8350_NUM_IRQ_REGS];
int read_done[WM8350_NUM_IRQ_REGS];
struct wm8350_irq_data *data;
int i;
level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
& ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
if (!level_one)
return IRQ_NONE;
memset(&read_done, 0, sizeof(read_done));
for (i = 0; i < ARRAY_SIZE(wm8350_irqs); i++) {
data = &wm8350_irqs[i];
if (!(level_one & data->primary))
continue;
if (!read_done[data->reg]) {
sub_reg[data->reg] =
wm8350_reg_read(wm8350, WM8350_INT_STATUS_1 +
data->reg);
sub_reg[data->reg] &= ~wm8350->irq_masks[data->reg];
read_done[data->reg] = 1;
}
if (sub_reg[data->reg] & data->mask)
handle_nested_irq(wm8350->irq_base + i);
}
return IRQ_HANDLED;
}
static void wm8350_irq_lock(struct irq_data *data)
{
struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
mutex_lock(&wm8350->irq_lock);
}
static void wm8350_irq_sync_unlock(struct irq_data *data)
{
struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
int i;
for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) {
/* If there's been a change in the mask write it back
* to the hardware. */
WARN_ON(regmap_update_bits(wm8350->regmap,
WM8350_INT_STATUS_1_MASK + i,
0xffff, wm8350->irq_masks[i]));
}
mutex_unlock(&wm8350->irq_lock);
}
static void wm8350_irq_enable(struct irq_data *data)
{
struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350,
data->irq);
wm8350->irq_masks[irq_data->reg] &= ~irq_data->mask;
}
static void wm8350_irq_disable(struct irq_data *data)
{
struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350,
data->irq);
wm8350->irq_masks[irq_data->reg] |= irq_data->mask;
}
static struct irq_chip wm8350_irq_chip = {
.name = "wm8350",
.irq_bus_lock = wm8350_irq_lock,
.irq_bus_sync_unlock = wm8350_irq_sync_unlock,
.irq_disable = wm8350_irq_disable,
.irq_enable = wm8350_irq_enable,
};
int wm8350_irq_init(struct wm8350 *wm8350, int irq,
struct wm8350_platform_data *pdata)
{
int ret, cur_irq, i;
int flags = IRQF_ONESHOT;
int irq_base = -1;
if (!irq) {
dev_warn(wm8350->dev, "No interrupt support, no core IRQ\n");
return 0;
}
/* Mask top level interrupts */
wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0xFFFF);
/* Mask all individual interrupts by default and cache the
* masks. We read the masks back since there are unwritable
* bits in the mask registers. */
for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) {
wm8350_reg_write(wm8350, WM8350_INT_STATUS_1_MASK + i,
0xFFFF);
wm8350->irq_masks[i] =
wm8350_reg_read(wm8350,
WM8350_INT_STATUS_1_MASK + i);
}
mutex_init(&wm8350->irq_lock);
wm8350->chip_irq = irq;
if (pdata && pdata->irq_base > 0)
irq_base = pdata->irq_base;
wm8350->irq_base =
irq_alloc_descs(irq_base, 0, ARRAY_SIZE(wm8350_irqs), 0);
if (wm8350->irq_base < 0) {
dev_warn(wm8350->dev, "Allocating irqs failed with %d\n",
wm8350->irq_base);
return 0;
}
if (pdata && pdata->irq_high) {
flags |= IRQF_TRIGGER_HIGH;
wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
WM8350_IRQ_POL);
} else {
flags |= IRQF_TRIGGER_LOW;
wm8350_clear_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
WM8350_IRQ_POL);
}
/* Register with genirq */
for (cur_irq = wm8350->irq_base;
cur_irq < ARRAY_SIZE(wm8350_irqs) + wm8350->irq_base;
cur_irq++) {
irq_set_chip_data(cur_irq, wm8350);
irq_set_chip_and_handler(cur_irq, &wm8350_irq_chip,
handle_edge_irq);
irq_set_nested_thread(cur_irq, 1);
irq_clear_status_flags(cur_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
}
ret = request_threaded_irq(irq, NULL, wm8350_irq, flags,
"wm8350", wm8350);
if (ret != 0)
dev_err(wm8350->dev, "Failed to request IRQ: %d\n", ret);
/* Allow interrupts to fire */
wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0);
return ret;
}
int wm8350_irq_exit(struct wm8350 *wm8350)
{
free_irq(wm8350->chip_irq, wm8350);
return 0;
}
| linux-master | drivers/mfd/wm8350-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <[email protected]>
*
* Based on the TPS65912 driver
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/mfd/tps65086.h>
static const struct mfd_cell tps65086_cells[] = {
{ .name = "tps65086-regulator", },
{ .name = "tps65086-gpio", },
{ .name = "tps65086-reset", },
};
static const struct regmap_range tps65086_yes_ranges[] = {
regmap_reg_range(TPS65086_IRQ, TPS65086_IRQ),
regmap_reg_range(TPS65086_PMICSTAT, TPS65086_SHUTDNSRC),
regmap_reg_range(TPS65086_GPOCTRL, TPS65086_GPOCTRL),
regmap_reg_range(TPS65086_PG_STATUS1, TPS65086_OC_STATUS),
};
static const struct regmap_access_table tps65086_volatile_table = {
.yes_ranges = tps65086_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(tps65086_yes_ranges),
};
static const struct regmap_config tps65086_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &tps65086_volatile_table,
};
static const struct regmap_irq tps65086_irqs[] = {
REGMAP_IRQ_REG(TPS65086_IRQ_DIETEMP, 0, TPS65086_IRQ_DIETEMP_MASK),
REGMAP_IRQ_REG(TPS65086_IRQ_SHUTDN, 0, TPS65086_IRQ_SHUTDN_MASK),
REGMAP_IRQ_REG(TPS65086_IRQ_FAULT, 0, TPS65086_IRQ_FAULT_MASK),
};
static struct regmap_irq_chip tps65086_irq_chip = {
.name = "tps65086",
.status_base = TPS65086_IRQ,
.mask_base = TPS65086_IRQ_MASK,
.ack_base = TPS65086_IRQ,
.init_ack_masked = true,
.num_regs = 1,
.irqs = tps65086_irqs,
.num_irqs = ARRAY_SIZE(tps65086_irqs),
};
static const struct of_device_id tps65086_of_match_table[] = {
{ .compatible = "ti,tps65086", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tps65086_of_match_table);
static int tps65086_probe(struct i2c_client *client)
{
struct tps65086 *tps;
unsigned int version;
int ret;
tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
i2c_set_clientdata(client, tps);
tps->dev = &client->dev;
tps->irq = client->irq;
tps->regmap = devm_regmap_init_i2c(client, &tps65086_regmap_config);
if (IS_ERR(tps->regmap)) {
dev_err(tps->dev, "Failed to initialize register map\n");
return PTR_ERR(tps->regmap);
}
/* Store device ID to load regulator configuration that fit to IC variant */
ret = regmap_read(tps->regmap, TPS65086_DEVICEID1, &tps->chip_id);
if (ret) {
dev_err(tps->dev, "Failed to read revision register 1\n");
return ret;
}
ret = regmap_read(tps->regmap, TPS65086_DEVICEID2, &version);
if (ret) {
dev_err(tps->dev, "Failed to read revision register 2\n");
return ret;
}
dev_info(tps->dev, "Device: TPS65086%01lX, OTP: %c, Rev: %ld\n",
(version & TPS65086_DEVICEID2_PART_MASK),
(char)((version & TPS65086_DEVICEID2_OTP_MASK) >> 4) + 'A',
(version & TPS65086_DEVICEID2_REV_MASK) >> 6);
if (tps->irq > 0) {
ret = regmap_add_irq_chip(tps->regmap, tps->irq, IRQF_ONESHOT, 0,
&tps65086_irq_chip, &tps->irq_data);
if (ret) {
dev_err(tps->dev, "Failed to register IRQ chip\n");
return ret;
}
}
ret = mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65086_cells,
ARRAY_SIZE(tps65086_cells), NULL, 0,
regmap_irq_get_domain(tps->irq_data));
if (ret && tps->irq > 0)
regmap_del_irq_chip(tps->irq, tps->irq_data);
return ret;
}
static void tps65086_remove(struct i2c_client *client)
{
struct tps65086 *tps = i2c_get_clientdata(client);
if (tps->irq > 0)
regmap_del_irq_chip(tps->irq, tps->irq_data);
}
static const struct i2c_device_id tps65086_id_table[] = {
{ "tps65086", 0 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, tps65086_id_table);
static struct i2c_driver tps65086_driver = {
.driver = {
.name = "tps65086",
.of_match_table = tps65086_of_match_table,
},
.probe = tps65086_probe,
.remove = tps65086_remove,
.id_table = tps65086_id_table,
};
module_i2c_driver(tps65086_driver);
MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
MODULE_DESCRIPTION("TPS65086 PMIC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/tps65086.c |
/*
* Base driver for Marvell 88PM805
*
* Copyright (C) 2012 Marvell International Ltd.
* Haojian Zhuang <[email protected]>
* Joseph(Yossi) Hanin <[email protected]>
* Qiao Zhou <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
* archive for more details.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/88pm80x.h>
#include <linux/slab.h>
#include <linux/delay.h>
static const struct i2c_device_id pm80x_id_table[] = {
{"88PM805", 0},
{} /* NULL terminated */
};
MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
/* Interrupt Number in 88PM805 */
enum {
PM805_IRQ_LDO_OFF, /*0 */
PM805_IRQ_SRC_DPLL_LOCK, /*1 */
PM805_IRQ_CLIP_FAULT,
PM805_IRQ_MIC_CONFLICT,
PM805_IRQ_HP2_SHRT,
PM805_IRQ_HP1_SHRT, /*5 */
PM805_IRQ_FINE_PLL_FAULT,
PM805_IRQ_RAW_PLL_FAULT,
PM805_IRQ_VOLP_BTN_DET,
PM805_IRQ_VOLM_BTN_DET,
PM805_IRQ_SHRT_BTN_DET, /*10 */
PM805_IRQ_MIC_DET, /*11 */
PM805_MAX_IRQ,
};
static struct resource codec_resources[] = {
/* Headset microphone insertion or removal */
DEFINE_RES_IRQ_NAMED(PM805_IRQ_MIC_DET, "micin"),
/* Audio short HP1 */
DEFINE_RES_IRQ_NAMED(PM805_IRQ_HP1_SHRT, "audio-short1"),
/* Audio short HP2 */
DEFINE_RES_IRQ_NAMED(PM805_IRQ_HP2_SHRT, "audio-short2"),
};
static const struct mfd_cell codec_devs[] = {
{
.name = "88pm80x-codec",
.num_resources = ARRAY_SIZE(codec_resources),
.resources = &codec_resources[0],
.id = -1,
},
};
static struct regmap_irq pm805_irqs[] = {
/* INT0 */
[PM805_IRQ_LDO_OFF] = {
.mask = PM805_INT1_HP1_SHRT,
},
[PM805_IRQ_SRC_DPLL_LOCK] = {
.mask = PM805_INT1_HP2_SHRT,
},
[PM805_IRQ_CLIP_FAULT] = {
.mask = PM805_INT1_MIC_CONFLICT,
},
[PM805_IRQ_MIC_CONFLICT] = {
.mask = PM805_INT1_CLIP_FAULT,
},
[PM805_IRQ_HP2_SHRT] = {
.mask = PM805_INT1_LDO_OFF,
},
[PM805_IRQ_HP1_SHRT] = {
.mask = PM805_INT1_SRC_DPLL_LOCK,
},
/* INT1 */
[PM805_IRQ_FINE_PLL_FAULT] = {
.reg_offset = 1,
.mask = PM805_INT2_MIC_DET,
},
[PM805_IRQ_RAW_PLL_FAULT] = {
.reg_offset = 1,
.mask = PM805_INT2_SHRT_BTN_DET,
},
[PM805_IRQ_VOLP_BTN_DET] = {
.reg_offset = 1,
.mask = PM805_INT2_VOLM_BTN_DET,
},
[PM805_IRQ_VOLM_BTN_DET] = {
.reg_offset = 1,
.mask = PM805_INT2_VOLP_BTN_DET,
},
[PM805_IRQ_SHRT_BTN_DET] = {
.reg_offset = 1,
.mask = PM805_INT2_RAW_PLL_FAULT,
},
[PM805_IRQ_MIC_DET] = {
.reg_offset = 1,
.mask = PM805_INT2_FINE_PLL_FAULT,
},
};
static int device_irq_init_805(struct pm80x_chip *chip)
{
struct regmap *map = chip->regmap;
unsigned long flags = IRQF_ONESHOT;
int data, mask, ret = -EINVAL;
if (!map || !chip->irq) {
dev_err(chip->dev, "incorrect parameters\n");
return -EINVAL;
}
/*
* irq_mode defines the way of clearing interrupt. it's read-clear by
* default.
*/
mask =
PM805_STATUS0_INT_CLEAR | PM805_STATUS0_INV_INT |
PM800_STATUS0_INT_MASK;
data = PM805_STATUS0_INT_CLEAR;
ret = regmap_update_bits(map, PM805_INT_STATUS0, mask, data);
/*
* PM805_INT_STATUS is under 32K clock domain, so need to
* add proper delay before the next I2C register access.
*/
usleep_range(1000, 3000);
if (ret < 0)
goto out;
ret =
regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
chip->regmap_irq_chip, &chip->irq_data);
out:
return ret;
}
static void device_irq_exit_805(struct pm80x_chip *chip)
{
regmap_del_irq_chip(chip->irq, chip->irq_data);
}
static struct regmap_irq_chip pm805_irq_chip = {
.name = "88pm805",
.irqs = pm805_irqs,
.num_irqs = ARRAY_SIZE(pm805_irqs),
.num_regs = 2,
.status_base = PM805_INT_STATUS1,
.mask_base = PM805_INT_MASK1,
.ack_base = PM805_INT_STATUS1,
};
static int device_805_init(struct pm80x_chip *chip)
{
int ret = 0;
struct regmap *map = chip->regmap;
if (!map) {
dev_err(chip->dev, "regmap is invalid\n");
return -EINVAL;
}
chip->regmap_irq_chip = &pm805_irq_chip;
ret = device_irq_init_805(chip);
if (ret < 0) {
dev_err(chip->dev, "Failed to init pm805 irq!\n");
goto out_irq_init;
}
ret = mfd_add_devices(chip->dev, 0, &codec_devs[0],
ARRAY_SIZE(codec_devs), &codec_resources[0], 0,
NULL);
if (ret < 0) {
dev_err(chip->dev, "Failed to add codec subdev\n");
goto out_codec;
} else
dev_info(chip->dev, "[%s]:Added mfd codec_devs\n", __func__);
return 0;
out_codec:
device_irq_exit_805(chip);
out_irq_init:
return ret;
}
static int pm805_probe(struct i2c_client *client)
{
int ret = 0;
struct pm80x_chip *chip;
struct pm80x_platform_data *pdata = dev_get_platdata(&client->dev);
ret = pm80x_init(client);
if (ret) {
dev_err(&client->dev, "pm805_init fail!\n");
goto out_init;
}
chip = i2c_get_clientdata(client);
ret = device_805_init(chip);
if (ret) {
dev_err(chip->dev, "Failed to initialize 88pm805 devices\n");
goto err_805_init;
}
if (pdata && pdata->plat_config)
pdata->plat_config(chip, pdata);
err_805_init:
pm80x_deinit();
out_init:
return ret;
}
static void pm805_remove(struct i2c_client *client)
{
struct pm80x_chip *chip = i2c_get_clientdata(client);
mfd_remove_devices(chip->dev);
device_irq_exit_805(chip);
pm80x_deinit();
}
static struct i2c_driver pm805_driver = {
.driver = {
.name = "88PM805",
.pm = pm_sleep_ptr(&pm80x_pm_ops),
},
.probe = pm805_probe,
.remove = pm805_remove,
.id_table = pm80x_id_table,
};
static int __init pm805_i2c_init(void)
{
return i2c_add_driver(&pm805_driver);
}
subsys_initcall(pm805_i2c_init);
static void __exit pm805_i2c_exit(void)
{
i2c_del_driver(&pm805_driver);
}
module_exit(pm805_i2c_exit);
MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM805");
MODULE_AUTHOR("Qiao Zhou <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/88pm805.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SPI access for Dialog DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <[email protected]>
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/input.h>
#include <linux/mfd/core.h>
#include <linux/spi/spi.h>
#include <linux/err.h>
#include <linux/mfd/da9052/da9052.h>
static int da9052_spi_probe(struct spi_device *spi)
{
struct regmap_config config;
int ret;
const struct spi_device_id *id = spi_get_device_id(spi);
struct da9052 *da9052;
da9052 = devm_kzalloc(&spi->dev, sizeof(struct da9052), GFP_KERNEL);
if (!da9052)
return -ENOMEM;
spi->mode = SPI_MODE_0;
spi->bits_per_word = 8;
spi_setup(spi);
da9052->dev = &spi->dev;
da9052->chip_irq = spi->irq;
spi_set_drvdata(spi, da9052);
config = da9052_regmap_config;
config.read_flag_mask = 1;
config.reg_bits = 7;
config.pad_bits = 1;
config.val_bits = 8;
config.use_single_read = true;
config.use_single_write = true;
da9052->regmap = devm_regmap_init_spi(spi, &config);
if (IS_ERR(da9052->regmap)) {
ret = PTR_ERR(da9052->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
return da9052_device_init(da9052, id->driver_data);
}
static void da9052_spi_remove(struct spi_device *spi)
{
struct da9052 *da9052 = spi_get_drvdata(spi);
da9052_device_exit(da9052);
}
static const struct spi_device_id da9052_spi_id[] = {
{"da9052", DA9052},
{"da9053-aa", DA9053_AA},
{"da9053-ba", DA9053_BA},
{"da9053-bb", DA9053_BB},
{"da9053-bc", DA9053_BC},
{}
};
static struct spi_driver da9052_spi_driver = {
.probe = da9052_spi_probe,
.remove = da9052_spi_remove,
.id_table = da9052_spi_id,
.driver = {
.name = "da9052",
},
};
static int __init da9052_spi_init(void)
{
int ret;
ret = spi_register_driver(&da9052_spi_driver);
if (ret != 0) {
pr_err("Failed to register DA9052 SPI driver, %d\n", ret);
return ret;
}
return 0;
}
subsys_initcall(da9052_spi_init);
static void __exit da9052_spi_exit(void)
{
spi_unregister_driver(&da9052_spi_driver);
}
module_exit(da9052_spi_exit);
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
MODULE_DESCRIPTION("SPI driver for Dialog DA9052 PMIC");
| linux-master | drivers/mfd/da9052-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* DA9052 interrupt support
*
* Author: Fabio Estevam <[email protected]>
* Based on arizona-irq.c, which is:
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/mfd/da9052/da9052.h>
#include <linux/mfd/da9052/reg.h>
#define DA9052_NUM_IRQ_REGS 4
#define DA9052_IRQ_MASK_POS_1 0x01
#define DA9052_IRQ_MASK_POS_2 0x02
#define DA9052_IRQ_MASK_POS_3 0x04
#define DA9052_IRQ_MASK_POS_4 0x08
#define DA9052_IRQ_MASK_POS_5 0x10
#define DA9052_IRQ_MASK_POS_6 0x20
#define DA9052_IRQ_MASK_POS_7 0x40
#define DA9052_IRQ_MASK_POS_8 0x80
static const struct regmap_irq da9052_irqs[] = {
[DA9052_IRQ_DCIN] = {
.reg_offset = 0,
.mask = DA9052_IRQ_MASK_POS_1,
},
[DA9052_IRQ_VBUS] = {
.reg_offset = 0,
.mask = DA9052_IRQ_MASK_POS_2,
},
[DA9052_IRQ_DCINREM] = {
.reg_offset = 0,
.mask = DA9052_IRQ_MASK_POS_3,
},
[DA9052_IRQ_VBUSREM] = {
.reg_offset = 0,
.mask = DA9052_IRQ_MASK_POS_4,
},
[DA9052_IRQ_VDDLOW] = {
.reg_offset = 0,
.mask = DA9052_IRQ_MASK_POS_5,
},
[DA9052_IRQ_ALARM] = {
.reg_offset = 0,
.mask = DA9052_IRQ_MASK_POS_6,
},
[DA9052_IRQ_SEQRDY] = {
.reg_offset = 0,
.mask = DA9052_IRQ_MASK_POS_7,
},
[DA9052_IRQ_COMP1V2] = {
.reg_offset = 0,
.mask = DA9052_IRQ_MASK_POS_8,
},
[DA9052_IRQ_NONKEY] = {
.reg_offset = 1,
.mask = DA9052_IRQ_MASK_POS_1,
},
[DA9052_IRQ_IDFLOAT] = {
.reg_offset = 1,
.mask = DA9052_IRQ_MASK_POS_2,
},
[DA9052_IRQ_IDGND] = {
.reg_offset = 1,
.mask = DA9052_IRQ_MASK_POS_3,
},
[DA9052_IRQ_CHGEND] = {
.reg_offset = 1,
.mask = DA9052_IRQ_MASK_POS_4,
},
[DA9052_IRQ_TBAT] = {
.reg_offset = 1,
.mask = DA9052_IRQ_MASK_POS_5,
},
[DA9052_IRQ_ADC_EOM] = {
.reg_offset = 1,
.mask = DA9052_IRQ_MASK_POS_6,
},
[DA9052_IRQ_PENDOWN] = {
.reg_offset = 1,
.mask = DA9052_IRQ_MASK_POS_7,
},
[DA9052_IRQ_TSIREADY] = {
.reg_offset = 1,
.mask = DA9052_IRQ_MASK_POS_8,
},
[DA9052_IRQ_GPI0] = {
.reg_offset = 2,
.mask = DA9052_IRQ_MASK_POS_1,
},
[DA9052_IRQ_GPI1] = {
.reg_offset = 2,
.mask = DA9052_IRQ_MASK_POS_2,
},
[DA9052_IRQ_GPI2] = {
.reg_offset = 2,
.mask = DA9052_IRQ_MASK_POS_3,
},
[DA9052_IRQ_GPI3] = {
.reg_offset = 2,
.mask = DA9052_IRQ_MASK_POS_4,
},
[DA9052_IRQ_GPI4] = {
.reg_offset = 2,
.mask = DA9052_IRQ_MASK_POS_5,
},
[DA9052_IRQ_GPI5] = {
.reg_offset = 2,
.mask = DA9052_IRQ_MASK_POS_6,
},
[DA9052_IRQ_GPI6] = {
.reg_offset = 2,
.mask = DA9052_IRQ_MASK_POS_7,
},
[DA9052_IRQ_GPI7] = {
.reg_offset = 2,
.mask = DA9052_IRQ_MASK_POS_8,
},
[DA9052_IRQ_GPI8] = {
.reg_offset = 3,
.mask = DA9052_IRQ_MASK_POS_1,
},
[DA9052_IRQ_GPI9] = {
.reg_offset = 3,
.mask = DA9052_IRQ_MASK_POS_2,
},
[DA9052_IRQ_GPI10] = {
.reg_offset = 3,
.mask = DA9052_IRQ_MASK_POS_3,
},
[DA9052_IRQ_GPI11] = {
.reg_offset = 3,
.mask = DA9052_IRQ_MASK_POS_4,
},
[DA9052_IRQ_GPI12] = {
.reg_offset = 3,
.mask = DA9052_IRQ_MASK_POS_5,
},
[DA9052_IRQ_GPI13] = {
.reg_offset = 3,
.mask = DA9052_IRQ_MASK_POS_6,
},
[DA9052_IRQ_GPI14] = {
.reg_offset = 3,
.mask = DA9052_IRQ_MASK_POS_7,
},
[DA9052_IRQ_GPI15] = {
.reg_offset = 3,
.mask = DA9052_IRQ_MASK_POS_8,
},
};
static const struct regmap_irq_chip da9052_regmap_irq_chip = {
.name = "da9052_irq",
.status_base = DA9052_EVENT_A_REG,
.mask_base = DA9052_IRQ_MASK_A_REG,
.ack_base = DA9052_EVENT_A_REG,
.num_regs = DA9052_NUM_IRQ_REGS,
.irqs = da9052_irqs,
.num_irqs = ARRAY_SIZE(da9052_irqs),
};
static int da9052_map_irq(struct da9052 *da9052, int irq)
{
return regmap_irq_get_virq(da9052->irq_data, irq);
}
int da9052_enable_irq(struct da9052 *da9052, int irq)
{
irq = da9052_map_irq(da9052, irq);
if (irq < 0)
return irq;
enable_irq(irq);
return 0;
}
EXPORT_SYMBOL_GPL(da9052_enable_irq);
int da9052_disable_irq(struct da9052 *da9052, int irq)
{
irq = da9052_map_irq(da9052, irq);
if (irq < 0)
return irq;
disable_irq(irq);
return 0;
}
EXPORT_SYMBOL_GPL(da9052_disable_irq);
int da9052_disable_irq_nosync(struct da9052 *da9052, int irq)
{
irq = da9052_map_irq(da9052, irq);
if (irq < 0)
return irq;
disable_irq_nosync(irq);
return 0;
}
EXPORT_SYMBOL_GPL(da9052_disable_irq_nosync);
int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
irq_handler_t handler, void *data)
{
irq = da9052_map_irq(da9052, irq);
if (irq < 0)
return irq;
return request_threaded_irq(irq, NULL, handler,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
name, data);
}
EXPORT_SYMBOL_GPL(da9052_request_irq);
void da9052_free_irq(struct da9052 *da9052, int irq, void *data)
{
irq = da9052_map_irq(da9052, irq);
if (irq < 0)
return;
free_irq(irq, data);
}
EXPORT_SYMBOL_GPL(da9052_free_irq);
static irqreturn_t da9052_auxadc_irq(int irq, void *irq_data)
{
struct da9052 *da9052 = irq_data;
complete(&da9052->done);
return IRQ_HANDLED;
}
int da9052_irq_init(struct da9052 *da9052)
{
int ret;
ret = regmap_add_irq_chip(da9052->regmap, da9052->chip_irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
-1, &da9052_regmap_irq_chip,
&da9052->irq_data);
if (ret < 0) {
dev_err(da9052->dev, "regmap_add_irq_chip failed: %d\n", ret);
goto regmap_err;
}
enable_irq_wake(da9052->chip_irq);
ret = da9052_request_irq(da9052, DA9052_IRQ_ADC_EOM, "adc-irq",
da9052_auxadc_irq, da9052);
if (ret != 0) {
dev_err(da9052->dev, "DA9052_IRQ_ADC_EOM failed: %d\n", ret);
goto request_irq_err;
}
return 0;
request_irq_err:
regmap_del_irq_chip(da9052->chip_irq, da9052->irq_data);
regmap_err:
return ret;
}
int da9052_irq_exit(struct da9052 *da9052)
{
da9052_free_irq(da9052, DA9052_IRQ_ADC_EOM, da9052);
regmap_del_irq_chip(da9052->chip_irq, da9052->irq_data);
return 0;
}
| linux-master | drivers/mfd/da9052-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* STA2x11 mfd for GPIO, SCTL and APBREG
*
* Copyright (c) 2009-2011 Wind River Systems, Inc.
* Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/seq_file.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/sta2x11-mfd.h>
#include <linux/regmap.h>
#include <asm/sta2x11.h>
static inline int __reg_within_range(unsigned int r,
unsigned int start,
unsigned int end)
{
return ((r >= start) && (r <= end));
}
/* This describes STA2X11 MFD chip for us, we may have several */
struct sta2x11_mfd {
struct sta2x11_instance *instance;
struct regmap *regmap[sta2x11_n_mfd_plat_devs];
spinlock_t lock[sta2x11_n_mfd_plat_devs];
struct list_head list;
void __iomem *regs[sta2x11_n_mfd_plat_devs];
};
static LIST_HEAD(sta2x11_mfd_list);
/* Three functions to act on the list */
static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev)
{
struct sta2x11_instance *instance;
struct sta2x11_mfd *mfd;
if (!pdev && !list_empty(&sta2x11_mfd_list)) {
pr_warn("%s: Unspecified device, using first instance\n",
__func__);
return list_entry(sta2x11_mfd_list.next,
struct sta2x11_mfd, list);
}
instance = sta2x11_get_instance(pdev);
if (!instance)
return NULL;
list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
if (mfd->instance == instance)
return mfd;
}
return NULL;
}
static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
{
int i;
struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
struct sta2x11_instance *instance;
if (mfd)
return -EBUSY;
instance = sta2x11_get_instance(pdev);
if (!instance)
return -EINVAL;
mfd = kzalloc(sizeof(*mfd), flags);
if (!mfd)
return -ENOMEM;
INIT_LIST_HEAD(&mfd->list);
for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
spin_lock_init(&mfd->lock[i]);
mfd->instance = instance;
list_add(&mfd->list, &sta2x11_mfd_list);
return 0;
}
/* This function is exported and is not expected to fail */
u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
enum sta2x11_mfd_plat_dev index)
{
struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
u32 r;
unsigned long flags;
void __iomem *regs;
if (!mfd) {
dev_warn(&pdev->dev, ": can't access sctl regs\n");
return 0;
}
regs = mfd->regs[index];
if (!regs) {
dev_warn(&pdev->dev, ": system ctl not initialized\n");
return 0;
}
spin_lock_irqsave(&mfd->lock[index], flags);
r = readl(regs + reg);
r &= ~mask;
r |= val;
if (mask)
writel(r, regs + reg);
spin_unlock_irqrestore(&mfd->lock[index], flags);
return r;
}
EXPORT_SYMBOL(__sta2x11_mfd_mask);
int sta2x11_mfd_get_regs_data(struct platform_device *dev,
enum sta2x11_mfd_plat_dev index,
void __iomem **regs,
spinlock_t **lock)
{
struct pci_dev *pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
struct sta2x11_mfd *mfd;
if (!pdev)
return -ENODEV;
mfd = sta2x11_mfd_find(pdev);
if (!mfd)
return -ENODEV;
if (index >= sta2x11_n_mfd_plat_devs)
return -ENODEV;
*regs = mfd->regs[index];
*lock = &mfd->lock[index];
pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs);
return *regs ? 0 : -ENODEV;
}
EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);
/*
* Special sta2x11-mfd regmap lock/unlock functions
*/
static void sta2x11_regmap_lock(void *__lock)
{
spinlock_t *lock = __lock;
spin_lock(lock);
}
static void sta2x11_regmap_unlock(void *__lock)
{
spinlock_t *lock = __lock;
spin_unlock(lock);
}
/* OTP (one time programmable registers do not require locking */
static void sta2x11_regmap_nolock(void *__lock)
{
}
static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
};
static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
{
return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
}
static struct regmap_config sta2x11_sctl_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.lock = sta2x11_regmap_lock,
.unlock = sta2x11_regmap_unlock,
.max_register = SCTL_SCRSTSTA,
.writeable_reg = sta2x11_sctl_writeable_reg,
};
static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
{
return (reg == STA2X11_SECR_CR) ||
__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
}
static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
{
return false;
}
static struct regmap_config sta2x11_scr_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.lock = sta2x11_regmap_nolock,
.unlock = sta2x11_regmap_nolock,
.max_register = STA2X11_SECR_FVR1,
.readable_reg = sta2x11_scr_readable_reg,
.writeable_reg = sta2x11_scr_writeable_reg,
};
static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
{
/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
if (reg >= APBREG_BSR_SARAC)
reg -= APBREG_BSR_SARAC;
switch (reg) {
case APBREG_BSR:
case APBREG_PAER:
case APBREG_PWAC:
case APBREG_PRAC:
case APBREG_PCG:
case APBREG_PUR:
case APBREG_EMU_PCG:
return true;
default:
return false;
}
}
static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
{
if (reg >= APBREG_BSR_SARAC)
reg -= APBREG_BSR_SARAC;
if (!sta2x11_apbreg_readable_reg(dev, reg))
return false;
return reg != APBREG_PAER;
}
static struct regmap_config sta2x11_apbreg_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.lock = sta2x11_regmap_lock,
.unlock = sta2x11_regmap_unlock,
.max_register = APBREG_EMU_PCG_SARAC,
.readable_reg = sta2x11_apbreg_readable_reg,
.writeable_reg = sta2x11_apbreg_writeable_reg,
};
static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
unsigned int reg)
{
return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG ||
__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) ||
__reg_within_range(reg, MASTER_LOCK_REG,
SYSTEM_CONFIG_STATUS_REG) ||
reg == MSP_CLK_CTRL_REG ||
__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
}
static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
unsigned int reg)
{
if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
return false;
switch (reg) {
case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
case SYSTEM_CONFIG_STATUS_REG:
case COMPENSATION_REG1:
case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
return false;
default:
return true;
}
}
static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.lock = sta2x11_regmap_lock,
.unlock = sta2x11_regmap_unlock,
.max_register = TEST_CTL_REG,
.readable_reg = sta2x11_apb_soc_regs_readable_reg,
.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
};
static struct regmap_config *
sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
[sta2x11_scr] = &sta2x11_scr_regmap_config,
};
/* Probe for the four platform devices */
static int sta2x11_mfd_platform_probe(struct platform_device *dev,
enum sta2x11_mfd_plat_dev index)
{
struct pci_dev **pdev;
struct sta2x11_mfd *mfd;
struct resource *res;
const char *name = sta2x11_mfd_names[index];
struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];
pdev = dev_get_platdata(&dev->dev);
mfd = sta2x11_mfd_find(*pdev);
if (!mfd)
return -ENODEV;
if (!regmap_config)
return -ENODEV;
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (!res)
return -ENOMEM;
if (!request_mem_region(res->start, resource_size(res), name))
return -EBUSY;
mfd->regs[index] = ioremap(res->start, resource_size(res));
if (!mfd->regs[index]) {
release_mem_region(res->start, resource_size(res));
return -ENOMEM;
}
regmap_config->lock_arg = &mfd->lock;
/*
No caching, registers could be reached both via regmap and via
void __iomem *
*/
regmap_config->cache_type = REGCACHE_NONE;
mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
regmap_config);
WARN_ON(IS_ERR(mfd->regmap[index]));
return 0;
}
static int sta2x11_sctl_probe(struct platform_device *dev)
{
return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
}
static int sta2x11_apbreg_probe(struct platform_device *dev)
{
return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
}
static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
{
return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
}
static int sta2x11_scr_probe(struct platform_device *dev)
{
return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
}
/* The three platform drivers */
static struct platform_driver sta2x11_sctl_platform_driver = {
.driver = {
.name = STA2X11_MFD_SCTL_NAME,
},
.probe = sta2x11_sctl_probe,
};
static struct platform_driver sta2x11_platform_driver = {
.driver = {
.name = STA2X11_MFD_APBREG_NAME,
},
.probe = sta2x11_apbreg_probe,
};
static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
.driver = {
.name = STA2X11_MFD_APB_SOC_REGS_NAME,
},
.probe = sta2x11_apb_soc_regs_probe,
};
static struct platform_driver sta2x11_scr_platform_driver = {
.driver = {
.name = STA2X11_MFD_SCR_NAME,
},
.probe = sta2x11_scr_probe,
};
static struct platform_driver * const drivers[] = {
&sta2x11_platform_driver,
&sta2x11_sctl_platform_driver,
&sta2x11_apb_soc_regs_platform_driver,
&sta2x11_scr_platform_driver,
};
static int __init sta2x11_drivers_init(void)
{
return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
}
/*
* What follows are the PCI devices that host the above pdevs.
* Each logic block is 4kB and they are all consecutive: we use this info.
*/
/* Mfd 0 device */
/* Mfd 0, Bar 0 */
enum mfd0_bar0_cells {
STA2X11_GPIO_0 = 0,
STA2X11_GPIO_1,
STA2X11_GPIO_2,
STA2X11_GPIO_3,
STA2X11_SCTL,
STA2X11_SCR,
STA2X11_TIME,
};
/* Mfd 0 , Bar 1 */
enum mfd0_bar1_cells {
STA2X11_APBREG = 0,
};
#define CELL_4K(_name, _cell) { \
.name = _name, \
.start = _cell * 4096, .end = _cell * 4096 + 4095, \
.flags = IORESOURCE_MEM, \
}
static const struct resource gpio_resources[] = {
{
/* 4 consecutive cells, 1 driver */
.name = STA2X11_MFD_GPIO_NAME,
.start = 0,
.end = (4 * 4096) - 1,
.flags = IORESOURCE_MEM,
}
};
static const struct resource sctl_resources[] = {
CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
};
static const struct resource scr_resources[] = {
CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
};
static const struct resource time_resources[] = {
CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
};
static const struct resource apbreg_resources[] = {
CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
};
#define DEV(_name, _r) \
{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }
static struct mfd_cell sta2x11_mfd0_bar0[] = {
/* offset 0: we add pdata later */
DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
DEV(STA2X11_MFD_SCR_NAME, scr_resources),
DEV(STA2X11_MFD_TIME_NAME, time_resources),
};
static struct mfd_cell sta2x11_mfd0_bar1[] = {
DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
};
/* Mfd 1 devices */
/* Mfd 1, Bar 0 */
enum mfd1_bar0_cells {
STA2X11_VIC = 0,
};
/* Mfd 1, Bar 1 */
enum mfd1_bar1_cells {
STA2X11_APB_SOC_REGS = 0,
};
static const struct resource vic_resources[] = {
CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
};
static const struct resource apb_soc_regs_resources[] = {
CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
};
static struct mfd_cell sta2x11_mfd1_bar0[] = {
DEV(STA2X11_MFD_VIC_NAME, vic_resources),
};
static struct mfd_cell sta2x11_mfd1_bar1[] = {
DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
};
static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
{
pci_save_state(pdev);
pci_disable_device(pdev);
pci_set_power_state(pdev, pci_choose_state(pdev, state));
return 0;
}
static int sta2x11_mfd_resume(struct pci_dev *pdev)
{
int err;
pci_set_power_state(pdev, PCI_D0);
err = pci_enable_device(pdev);
if (err)
return err;
pci_restore_state(pdev);
return 0;
}
struct sta2x11_mfd_bar_setup_data {
struct mfd_cell *cells;
int ncells;
};
struct sta2x11_mfd_setup_data {
struct sta2x11_mfd_bar_setup_data bars[2];
};
#define STA2X11_MFD0 0
#define STA2X11_MFD1 1
static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
/* Mfd 0: gpio, sctl, scr, timers / apbregs */
[STA2X11_MFD0] = {
.bars = {
[0] = {
.cells = sta2x11_mfd0_bar0,
.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
},
[1] = {
.cells = sta2x11_mfd0_bar1,
.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
},
},
},
/* Mfd 1: vic / apb-soc-regs */
[STA2X11_MFD1] = {
.bars = {
[0] = {
.cells = sta2x11_mfd1_bar0,
.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
},
[1] = {
.cells = sta2x11_mfd1_bar1,
.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
},
},
},
};
static void sta2x11_mfd_setup(struct pci_dev *pdev,
struct sta2x11_mfd_setup_data *sd)
{
int i, j;
for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
for (j = 0; j < sd->bars[i].ncells; j++) {
sd->bars[i].cells[j].pdata_size = sizeof(pdev);
sd->bars[i].cells[j].platform_data = &pdev;
}
}
static int sta2x11_mfd_probe(struct pci_dev *pdev,
const struct pci_device_id *pci_id)
{
int err, i;
struct sta2x11_mfd_setup_data *setup_data;
dev_info(&pdev->dev, "%s\n", __func__);
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "Can't enable device.\n");
return err;
}
err = pci_enable_msi(pdev);
if (err)
dev_info(&pdev->dev, "Enable msi failed\n");
setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
&mfd_setup_data[STA2X11_MFD0] :
&mfd_setup_data[STA2X11_MFD1];
/* platform data is the pci device for all of them */
sta2x11_mfd_setup(pdev, setup_data);
/* Record this pdev before mfd_add_devices: their probe looks for it */
if (!sta2x11_mfd_find(pdev))
sta2x11_mfd_add(pdev, GFP_KERNEL);
/* Just 2 bars for all mfd's at present */
for (i = 0; i < 2; i++) {
err = mfd_add_devices(&pdev->dev, -1,
setup_data->bars[i].cells,
setup_data->bars[i].ncells,
&pdev->resource[i],
0, NULL);
if (err) {
dev_err(&pdev->dev,
"mfd_add_devices[%d] failed: %d\n", i, err);
goto err_disable;
}
}
return 0;
err_disable:
mfd_remove_devices(&pdev->dev);
pci_disable_device(pdev);
pci_disable_msi(pdev);
return err;
}
static const struct pci_device_id sta2x11_mfd_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
{0,},
};
static struct pci_driver sta2x11_mfd_driver = {
.name = "sta2x11-mfd",
.id_table = sta2x11_mfd_tbl,
.probe = sta2x11_mfd_probe,
.suspend = sta2x11_mfd_suspend,
.resume = sta2x11_mfd_resume,
};
static int __init sta2x11_mfd_init(void)
{
pr_info("%s\n", __func__);
return pci_register_driver(&sta2x11_mfd_driver);
}
/*
* All of this must be ready before "normal" devices like MMCI appear.
* But MFD (the pci device) can't be too early. The following choice
* prepares platform drivers very early and probe the PCI device later,
* but before other PCI devices.
*/
subsys_initcall(sta2x11_drivers_init);
rootfs_initcall(sta2x11_mfd_init);
| linux-master | drivers/mfd/sta2x11-mfd.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Base driver for Dialog Semiconductor DA9030/DA9034
*
* Copyright (C) 2008 Compulab, Ltd.
* Mike Rapoport <[email protected]>
*
* Copyright (C) 2006-2008 Marvell International Ltd.
* Eric Miao <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/mfd/da903x.h>
#include <linux/slab.h>
#define DA9030_CHIP_ID 0x00
#define DA9030_EVENT_A 0x01
#define DA9030_EVENT_B 0x02
#define DA9030_EVENT_C 0x03
#define DA9030_STATUS 0x04
#define DA9030_IRQ_MASK_A 0x05
#define DA9030_IRQ_MASK_B 0x06
#define DA9030_IRQ_MASK_C 0x07
#define DA9030_SYS_CTRL_A 0x08
#define DA9030_SYS_CTRL_B 0x09
#define DA9030_FAULT_LOG 0x0a
#define DA9034_CHIP_ID 0x00
#define DA9034_EVENT_A 0x01
#define DA9034_EVENT_B 0x02
#define DA9034_EVENT_C 0x03
#define DA9034_EVENT_D 0x04
#define DA9034_STATUS_A 0x05
#define DA9034_STATUS_B 0x06
#define DA9034_IRQ_MASK_A 0x07
#define DA9034_IRQ_MASK_B 0x08
#define DA9034_IRQ_MASK_C 0x09
#define DA9034_IRQ_MASK_D 0x0a
#define DA9034_SYS_CTRL_A 0x0b
#define DA9034_SYS_CTRL_B 0x0c
#define DA9034_FAULT_LOG 0x0d
struct da903x_chip;
struct da903x_chip_ops {
int (*init_chip)(struct da903x_chip *);
int (*unmask_events)(struct da903x_chip *, unsigned int events);
int (*mask_events)(struct da903x_chip *, unsigned int events);
int (*read_events)(struct da903x_chip *, unsigned int *events);
int (*read_status)(struct da903x_chip *, unsigned int *status);
};
struct da903x_chip {
struct i2c_client *client;
struct device *dev;
const struct da903x_chip_ops *ops;
int type;
uint32_t events_mask;
struct mutex lock;
struct work_struct irq_work;
struct blocking_notifier_head notifier_list;
};
static inline int __da903x_read(struct i2c_client *client,
int reg, uint8_t *val)
{
int ret;
ret = i2c_smbus_read_byte_data(client, reg);
if (ret < 0) {
dev_err(&client->dev, "failed reading at 0x%02x\n", reg);
return ret;
}
*val = (uint8_t)ret;
return 0;
}
static inline int __da903x_reads(struct i2c_client *client, int reg,
int len, uint8_t *val)
{
int ret;
ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
if (ret < 0) {
dev_err(&client->dev, "failed reading from 0x%02x\n", reg);
return ret;
}
return 0;
}
static inline int __da903x_write(struct i2c_client *client,
int reg, uint8_t val)
{
int ret;
ret = i2c_smbus_write_byte_data(client, reg, val);
if (ret < 0) {
dev_err(&client->dev, "failed writing 0x%02x to 0x%02x\n",
val, reg);
return ret;
}
return 0;
}
static inline int __da903x_writes(struct i2c_client *client, int reg,
int len, uint8_t *val)
{
int ret;
ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
if (ret < 0) {
dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
return ret;
}
return 0;
}
int da903x_register_notifier(struct device *dev, struct notifier_block *nb,
unsigned int events)
{
struct da903x_chip *chip = dev_get_drvdata(dev);
chip->ops->unmask_events(chip, events);
return blocking_notifier_chain_register(&chip->notifier_list, nb);
}
EXPORT_SYMBOL_GPL(da903x_register_notifier);
int da903x_unregister_notifier(struct device *dev, struct notifier_block *nb,
unsigned int events)
{
struct da903x_chip *chip = dev_get_drvdata(dev);
chip->ops->mask_events(chip, events);
return blocking_notifier_chain_unregister(&chip->notifier_list, nb);
}
EXPORT_SYMBOL_GPL(da903x_unregister_notifier);
int da903x_write(struct device *dev, int reg, uint8_t val)
{
return __da903x_write(to_i2c_client(dev), reg, val);
}
EXPORT_SYMBOL_GPL(da903x_write);
int da903x_writes(struct device *dev, int reg, int len, uint8_t *val)
{
return __da903x_writes(to_i2c_client(dev), reg, len, val);
}
EXPORT_SYMBOL_GPL(da903x_writes);
int da903x_read(struct device *dev, int reg, uint8_t *val)
{
return __da903x_read(to_i2c_client(dev), reg, val);
}
EXPORT_SYMBOL_GPL(da903x_read);
int da903x_reads(struct device *dev, int reg, int len, uint8_t *val)
{
return __da903x_reads(to_i2c_client(dev), reg, len, val);
}
EXPORT_SYMBOL_GPL(da903x_reads);
int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask)
{
struct da903x_chip *chip = dev_get_drvdata(dev);
uint8_t reg_val;
int ret = 0;
mutex_lock(&chip->lock);
ret = __da903x_read(chip->client, reg, ®_val);
if (ret)
goto out;
if ((reg_val & bit_mask) != bit_mask) {
reg_val |= bit_mask;
ret = __da903x_write(chip->client, reg, reg_val);
}
out:
mutex_unlock(&chip->lock);
return ret;
}
EXPORT_SYMBOL_GPL(da903x_set_bits);
int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask)
{
struct da903x_chip *chip = dev_get_drvdata(dev);
uint8_t reg_val;
int ret = 0;
mutex_lock(&chip->lock);
ret = __da903x_read(chip->client, reg, ®_val);
if (ret)
goto out;
if (reg_val & bit_mask) {
reg_val &= ~bit_mask;
ret = __da903x_write(chip->client, reg, reg_val);
}
out:
mutex_unlock(&chip->lock);
return ret;
}
EXPORT_SYMBOL_GPL(da903x_clr_bits);
int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask)
{
struct da903x_chip *chip = dev_get_drvdata(dev);
uint8_t reg_val;
int ret = 0;
mutex_lock(&chip->lock);
ret = __da903x_read(chip->client, reg, ®_val);
if (ret)
goto out;
if ((reg_val & mask) != val) {
reg_val = (reg_val & ~mask) | val;
ret = __da903x_write(chip->client, reg, reg_val);
}
out:
mutex_unlock(&chip->lock);
return ret;
}
EXPORT_SYMBOL_GPL(da903x_update);
int da903x_query_status(struct device *dev, unsigned int sbits)
{
struct da903x_chip *chip = dev_get_drvdata(dev);
unsigned int status = 0;
chip->ops->read_status(chip, &status);
return ((status & sbits) == sbits);
}
EXPORT_SYMBOL(da903x_query_status);
static int da9030_init_chip(struct da903x_chip *chip)
{
uint8_t chip_id;
int err;
err = __da903x_read(chip->client, DA9030_CHIP_ID, &chip_id);
if (err)
return err;
err = __da903x_write(chip->client, DA9030_SYS_CTRL_A, 0xE8);
if (err)
return err;
dev_info(chip->dev, "DA9030 (CHIP ID: 0x%02x) detected\n", chip_id);
return 0;
}
static int da9030_unmask_events(struct da903x_chip *chip, unsigned int events)
{
uint8_t v[3];
chip->events_mask &= ~events;
v[0] = (chip->events_mask & 0xff);
v[1] = (chip->events_mask >> 8) & 0xff;
v[2] = (chip->events_mask >> 16) & 0xff;
return __da903x_writes(chip->client, DA9030_IRQ_MASK_A, 3, v);
}
static int da9030_mask_events(struct da903x_chip *chip, unsigned int events)
{
uint8_t v[3];
chip->events_mask |= events;
v[0] = (chip->events_mask & 0xff);
v[1] = (chip->events_mask >> 8) & 0xff;
v[2] = (chip->events_mask >> 16) & 0xff;
return __da903x_writes(chip->client, DA9030_IRQ_MASK_A, 3, v);
}
static int da9030_read_events(struct da903x_chip *chip, unsigned int *events)
{
uint8_t v[3] = {0, 0, 0};
int ret;
ret = __da903x_reads(chip->client, DA9030_EVENT_A, 3, v);
if (ret < 0)
return ret;
*events = (v[2] << 16) | (v[1] << 8) | v[0];
return 0;
}
static int da9030_read_status(struct da903x_chip *chip, unsigned int *status)
{
return __da903x_read(chip->client, DA9030_STATUS, (uint8_t *)status);
}
static int da9034_init_chip(struct da903x_chip *chip)
{
uint8_t chip_id;
int err;
err = __da903x_read(chip->client, DA9034_CHIP_ID, &chip_id);
if (err)
return err;
err = __da903x_write(chip->client, DA9034_SYS_CTRL_A, 0xE8);
if (err)
return err;
/* avoid SRAM power off during sleep*/
__da903x_write(chip->client, 0x10, 0x07);
__da903x_write(chip->client, 0x11, 0xff);
__da903x_write(chip->client, 0x12, 0xff);
/* Enable the ONKEY power down functionality */
__da903x_write(chip->client, DA9034_SYS_CTRL_B, 0x20);
__da903x_write(chip->client, DA9034_SYS_CTRL_A, 0x60);
/* workaround to make LEDs work */
__da903x_write(chip->client, 0x90, 0x01);
__da903x_write(chip->client, 0xB0, 0x08);
/* make ADTV1 and SDTV1 effective */
__da903x_write(chip->client, 0x20, 0x00);
dev_info(chip->dev, "DA9034 (CHIP ID: 0x%02x) detected\n", chip_id);
return 0;
}
static int da9034_unmask_events(struct da903x_chip *chip, unsigned int events)
{
uint8_t v[4];
chip->events_mask &= ~events;
v[0] = (chip->events_mask & 0xff);
v[1] = (chip->events_mask >> 8) & 0xff;
v[2] = (chip->events_mask >> 16) & 0xff;
v[3] = (chip->events_mask >> 24) & 0xff;
return __da903x_writes(chip->client, DA9034_IRQ_MASK_A, 4, v);
}
static int da9034_mask_events(struct da903x_chip *chip, unsigned int events)
{
uint8_t v[4];
chip->events_mask |= events;
v[0] = (chip->events_mask & 0xff);
v[1] = (chip->events_mask >> 8) & 0xff;
v[2] = (chip->events_mask >> 16) & 0xff;
v[3] = (chip->events_mask >> 24) & 0xff;
return __da903x_writes(chip->client, DA9034_IRQ_MASK_A, 4, v);
}
static int da9034_read_events(struct da903x_chip *chip, unsigned int *events)
{
uint8_t v[4] = {0, 0, 0, 0};
int ret;
ret = __da903x_reads(chip->client, DA9034_EVENT_A, 4, v);
if (ret < 0)
return ret;
*events = (v[3] << 24) | (v[2] << 16) | (v[1] << 8) | v[0];
return 0;
}
static int da9034_read_status(struct da903x_chip *chip, unsigned int *status)
{
uint8_t v[2] = {0, 0};
int ret = 0;
ret = __da903x_reads(chip->client, DA9034_STATUS_A, 2, v);
if (ret)
return ret;
*status = (v[1] << 8) | v[0];
return 0;
}
static void da903x_irq_work(struct work_struct *work)
{
struct da903x_chip *chip =
container_of(work, struct da903x_chip, irq_work);
unsigned int events = 0;
while (1) {
if (chip->ops->read_events(chip, &events))
break;
events &= ~chip->events_mask;
if (events == 0)
break;
blocking_notifier_call_chain(
&chip->notifier_list, events, NULL);
}
enable_irq(chip->client->irq);
}
static irqreturn_t da903x_irq_handler(int irq, void *data)
{
struct da903x_chip *chip = data;
disable_irq_nosync(irq);
(void)schedule_work(&chip->irq_work);
return IRQ_HANDLED;
}
static const struct da903x_chip_ops da903x_ops[] = {
[0] = {
.init_chip = da9030_init_chip,
.unmask_events = da9030_unmask_events,
.mask_events = da9030_mask_events,
.read_events = da9030_read_events,
.read_status = da9030_read_status,
},
[1] = {
.init_chip = da9034_init_chip,
.unmask_events = da9034_unmask_events,
.mask_events = da9034_mask_events,
.read_events = da9034_read_events,
.read_status = da9034_read_status,
}
};
static const struct i2c_device_id da903x_id_table[] = {
{ "da9030", 0 },
{ "da9034", 1 },
{ },
};
MODULE_DEVICE_TABLE(i2c, da903x_id_table);
static int __remove_subdev(struct device *dev, void *unused)
{
platform_device_unregister(to_platform_device(dev));
return 0;
}
static int da903x_remove_subdevs(struct da903x_chip *chip)
{
return device_for_each_child(chip->dev, NULL, __remove_subdev);
}
static int da903x_add_subdevs(struct da903x_chip *chip,
struct da903x_platform_data *pdata)
{
struct da903x_subdev_info *subdev;
struct platform_device *pdev;
int i, ret = 0;
for (i = 0; i < pdata->num_subdevs; i++) {
subdev = &pdata->subdevs[i];
pdev = platform_device_alloc(subdev->name, subdev->id);
if (!pdev) {
ret = -ENOMEM;
goto failed;
}
pdev->dev.parent = chip->dev;
pdev->dev.platform_data = subdev->platform_data;
ret = platform_device_add(pdev);
if (ret) {
platform_device_put(pdev);
goto failed;
}
}
return 0;
failed:
da903x_remove_subdevs(chip);
return ret;
}
static int da903x_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct da903x_platform_data *pdata = dev_get_platdata(&client->dev);
struct da903x_chip *chip;
unsigned int tmp;
int ret;
chip = devm_kzalloc(&client->dev, sizeof(struct da903x_chip),
GFP_KERNEL);
if (chip == NULL)
return -ENOMEM;
chip->client = client;
chip->dev = &client->dev;
chip->ops = &da903x_ops[id->driver_data];
mutex_init(&chip->lock);
INIT_WORK(&chip->irq_work, da903x_irq_work);
BLOCKING_INIT_NOTIFIER_HEAD(&chip->notifier_list);
i2c_set_clientdata(client, chip);
ret = chip->ops->init_chip(chip);
if (ret)
return ret;
/* mask and clear all IRQs */
chip->events_mask = 0xffffffff;
chip->ops->mask_events(chip, chip->events_mask);
chip->ops->read_events(chip, &tmp);
ret = devm_request_irq(&client->dev, client->irq, da903x_irq_handler,
IRQF_TRIGGER_FALLING,
"da903x", chip);
if (ret) {
dev_err(&client->dev, "failed to request irq %d\n",
client->irq);
return ret;
}
return da903x_add_subdevs(chip, pdata);
}
static void da903x_remove(struct i2c_client *client)
{
struct da903x_chip *chip = i2c_get_clientdata(client);
da903x_remove_subdevs(chip);
}
static struct i2c_driver da903x_driver = {
.driver = {
.name = "da903x",
},
.probe = da903x_probe,
.remove = da903x_remove,
.id_table = da903x_id_table,
};
static int __init da903x_init(void)
{
return i2c_add_driver(&da903x_driver);
}
subsys_initcall(da903x_init);
static void __exit da903x_exit(void)
{
i2c_del_driver(&da903x_driver);
}
module_exit(da903x_exit);
MODULE_DESCRIPTION("PMIC Driver for Dialog Semiconductor DA9034");
MODULE_AUTHOR("Eric Miao <[email protected]>");
MODULE_AUTHOR("Mike Rapoport <[email protected]>");
| linux-master | drivers/mfd/da903x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/mfd/mcp-sa11x0.c
*
* Copyright (C) 2001-2005 Russell King
*
* SA11x0 MCP (Multimedia Communications Port) driver.
*
* MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
*/
#include <linux/module.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/mfd/mcp.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <linux/platform_data/mfd-mcp-sa11x0.h>
#define DRIVER_NAME "sa11x0-mcp"
struct mcp_sa11x0 {
void __iomem *base0;
void __iomem *base1;
u32 mccr0;
u32 mccr1;
};
/* Register offsets */
#define MCCR0(m) ((m)->base0 + 0x00)
#define MCDR0(m) ((m)->base0 + 0x08)
#define MCDR1(m) ((m)->base0 + 0x0c)
#define MCDR2(m) ((m)->base0 + 0x10)
#define MCSR(m) ((m)->base0 + 0x18)
#define MCCR1(m) ((m)->base1 + 0x00)
#define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp))
static void
mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
{
struct mcp_sa11x0 *m = priv(mcp);
divisor /= 32;
m->mccr0 &= ~0x00007f00;
m->mccr0 |= divisor << 8;
writel_relaxed(m->mccr0, MCCR0(m));
}
static void
mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
{
struct mcp_sa11x0 *m = priv(mcp);
divisor /= 32;
m->mccr0 &= ~0x0000007f;
m->mccr0 |= divisor;
writel_relaxed(m->mccr0, MCCR0(m));
}
/*
* Write data to the device. The bit should be set after 3 subframe
* times (each frame is 64 clocks). We wait a maximum of 6 subframes.
* We really should try doing something more productive while we
* wait.
*/
static void
mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
{
struct mcp_sa11x0 *m = priv(mcp);
int ret = -ETIME;
int i;
writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m));
for (i = 0; i < 2; i++) {
udelay(mcp->rw_timeout);
if (readl_relaxed(MCSR(m)) & MCSR_CWC) {
ret = 0;
break;
}
}
if (ret < 0)
printk(KERN_WARNING "mcp: write timed out\n");
}
/*
* Read data from the device. The bit should be set after 3 subframe
* times (each frame is 64 clocks). We wait a maximum of 6 subframes.
* We really should try doing something more productive while we
* wait.
*/
static unsigned int
mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
{
struct mcp_sa11x0 *m = priv(mcp);
int ret = -ETIME;
int i;
writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m));
for (i = 0; i < 2; i++) {
udelay(mcp->rw_timeout);
if (readl_relaxed(MCSR(m)) & MCSR_CRC) {
ret = readl_relaxed(MCDR2(m)) & 0xffff;
break;
}
}
if (ret < 0)
printk(KERN_WARNING "mcp: read timed out\n");
return ret;
}
static void mcp_sa11x0_enable(struct mcp *mcp)
{
struct mcp_sa11x0 *m = priv(mcp);
writel(-1, MCSR(m));
m->mccr0 |= MCCR0_MCE;
writel_relaxed(m->mccr0, MCCR0(m));
}
static void mcp_sa11x0_disable(struct mcp *mcp)
{
struct mcp_sa11x0 *m = priv(mcp);
m->mccr0 &= ~MCCR0_MCE;
writel_relaxed(m->mccr0, MCCR0(m));
}
/*
* Our methods.
*/
static struct mcp_ops mcp_sa11x0 = {
.set_telecom_divisor = mcp_sa11x0_set_telecom_divisor,
.set_audio_divisor = mcp_sa11x0_set_audio_divisor,
.reg_write = mcp_sa11x0_write,
.reg_read = mcp_sa11x0_read,
.enable = mcp_sa11x0_enable,
.disable = mcp_sa11x0_disable,
};
static int mcp_sa11x0_probe(struct platform_device *dev)
{
struct mcp_plat_data *data = dev_get_platdata(&dev->dev);
struct resource *mem0, *mem1;
struct mcp_sa11x0 *m;
struct mcp *mcp;
int ret;
if (!data)
return -ENODEV;
mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
if (!mem0 || !mem1)
return -ENXIO;
if (!request_mem_region(mem0->start, resource_size(mem0),
DRIVER_NAME)) {
ret = -EBUSY;
goto err_mem0;
}
if (!request_mem_region(mem1->start, resource_size(mem1),
DRIVER_NAME)) {
ret = -EBUSY;
goto err_mem1;
}
mcp = mcp_host_alloc(&dev->dev, sizeof(struct mcp_sa11x0));
if (!mcp) {
ret = -ENOMEM;
goto err_alloc;
}
mcp->owner = THIS_MODULE;
mcp->ops = &mcp_sa11x0;
mcp->sclk_rate = data->sclk_rate;
m = priv(mcp);
m->mccr0 = data->mccr0 | 0x7f7f;
m->mccr1 = data->mccr1;
m->base0 = ioremap(mem0->start, resource_size(mem0));
m->base1 = ioremap(mem1->start, resource_size(mem1));
if (!m->base0 || !m->base1) {
ret = -ENOMEM;
goto err_ioremap;
}
platform_set_drvdata(dev, mcp);
/*
* Initialise device. Note that we initially
* set the sampling rate to minimum.
*/
writel_relaxed(-1, MCSR(m));
writel_relaxed(m->mccr1, MCCR1(m));
writel_relaxed(m->mccr0, MCCR0(m));
/*
* Calculate the read/write timeout (us) from the bit clock
* rate. This is the period for 3 64-bit frames. Always
* round this time up.
*/
mcp->rw_timeout = DIV_ROUND_UP(64 * 3 * 1000000, mcp->sclk_rate);
ret = mcp_host_add(mcp, data->codec_pdata);
if (ret == 0)
return 0;
err_ioremap:
iounmap(m->base1);
iounmap(m->base0);
mcp_host_free(mcp);
err_alloc:
release_mem_region(mem1->start, resource_size(mem1));
err_mem1:
release_mem_region(mem0->start, resource_size(mem0));
err_mem0:
return ret;
}
static int mcp_sa11x0_remove(struct platform_device *dev)
{
struct mcp *mcp = platform_get_drvdata(dev);
struct mcp_sa11x0 *m = priv(mcp);
struct resource *mem0, *mem1;
if (m->mccr0 & MCCR0_MCE)
dev_warn(&dev->dev,
"device left active (missing disable call?)\n");
mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
mcp_host_del(mcp);
iounmap(m->base1);
iounmap(m->base0);
mcp_host_free(mcp);
release_mem_region(mem1->start, resource_size(mem1));
release_mem_region(mem0->start, resource_size(mem0));
return 0;
}
static int mcp_sa11x0_suspend(struct device *dev)
{
struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));
if (m->mccr0 & MCCR0_MCE)
dev_warn(dev, "device left active (missing disable call?)\n");
writel(m->mccr0 & ~MCCR0_MCE, MCCR0(m));
return 0;
}
static int mcp_sa11x0_resume(struct device *dev)
{
struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));
writel_relaxed(m->mccr1, MCCR1(m));
writel_relaxed(m->mccr0, MCCR0(m));
return 0;
}
static const struct dev_pm_ops mcp_sa11x0_pm_ops = {
.suspend = mcp_sa11x0_suspend,
.freeze = mcp_sa11x0_suspend,
.poweroff = mcp_sa11x0_suspend,
.resume_noirq = mcp_sa11x0_resume,
.thaw_noirq = mcp_sa11x0_resume,
.restore_noirq = mcp_sa11x0_resume,
};
static struct platform_driver mcp_sa11x0_driver = {
.probe = mcp_sa11x0_probe,
.remove = mcp_sa11x0_remove,
.driver = {
.name = DRIVER_NAME,
.pm = pm_sleep_ptr(&mcp_sa11x0_pm_ops),
},
};
/*
* This needs re-working
*/
module_platform_driver(mcp_sa11x0_driver);
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_AUTHOR("Russell King <[email protected]>");
MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/mcp-sa11x0.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* lpc_sch.c - LPC interface for Intel Poulsbo SCH
*
* LPC bridge function of the Intel SCH contains many other
* functional units, such as Interrupt controllers, Timers,
* Power Management, System Management, GPIO, RTC, and LPC
* Configuration Registers.
*
* Copyright (c) 2010 CompuLab Ltd
* Copyright (c) 2014 Intel Corp.
* Author: Denis Turischev <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/acpi.h>
#include <linux/pci.h>
#include <linux/mfd/core.h>
#define SMBASE 0x40
#define SMBUS_IO_SIZE 64
#define GPIO_BASE 0x44
#define GPIO_IO_SIZE 64
#define GPIO_IO_SIZE_CENTERTON 128
#define WDTBASE 0x84
#define WDT_IO_SIZE 64
enum sch_chipsets {
LPC_SCH = 0, /* Intel Poulsbo SCH */
LPC_ITC, /* Intel Tunnel Creek */
LPC_CENTERTON, /* Intel Centerton */
LPC_QUARK_X1000, /* Intel Quark X1000 */
};
struct lpc_sch_info {
unsigned int io_size_smbus;
unsigned int io_size_gpio;
unsigned int io_size_wdt;
};
static struct lpc_sch_info sch_chipset_info[] = {
[LPC_SCH] = {
.io_size_smbus = SMBUS_IO_SIZE,
.io_size_gpio = GPIO_IO_SIZE,
},
[LPC_ITC] = {
.io_size_smbus = SMBUS_IO_SIZE,
.io_size_gpio = GPIO_IO_SIZE,
.io_size_wdt = WDT_IO_SIZE,
},
[LPC_CENTERTON] = {
.io_size_smbus = SMBUS_IO_SIZE,
.io_size_gpio = GPIO_IO_SIZE_CENTERTON,
.io_size_wdt = WDT_IO_SIZE,
},
[LPC_QUARK_X1000] = {
.io_size_gpio = GPIO_IO_SIZE,
.io_size_wdt = WDT_IO_SIZE,
},
};
static const struct pci_device_id lpc_sch_ids[] = {
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC), LPC_SCH },
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC), LPC_ITC },
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CENTERTON_ILB), LPC_CENTERTON },
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB), LPC_QUARK_X1000 },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, lpc_sch_ids);
#define LPC_NO_RESOURCE 1
#define LPC_SKIP_RESOURCE 2
static int lpc_sch_get_io(struct pci_dev *pdev, int where, const char *name,
struct resource *res, int size)
{
unsigned int base_addr_cfg;
unsigned short base_addr;
if (size == 0)
return LPC_NO_RESOURCE;
pci_read_config_dword(pdev, where, &base_addr_cfg);
base_addr = 0;
if (!(base_addr_cfg & (1 << 31)))
dev_warn(&pdev->dev, "Decode of the %s I/O range disabled\n",
name);
else
base_addr = (unsigned short)base_addr_cfg;
if (base_addr == 0) {
dev_warn(&pdev->dev, "I/O space for %s uninitialized\n", name);
return LPC_SKIP_RESOURCE;
}
res->start = base_addr;
res->end = base_addr + size - 1;
res->flags = IORESOURCE_IO;
return 0;
}
static int lpc_sch_populate_cell(struct pci_dev *pdev, int where,
const char *name, int size, int id,
struct mfd_cell *cell)
{
struct resource *res;
int ret;
res = devm_kzalloc(&pdev->dev, sizeof(*res), GFP_KERNEL);
if (!res)
return -ENOMEM;
ret = lpc_sch_get_io(pdev, where, name, res, size);
if (ret)
return ret;
memset(cell, 0, sizeof(*cell));
cell->name = name;
cell->resources = res;
cell->num_resources = 1;
cell->ignore_resource_conflicts = true;
cell->id = id;
return 0;
}
static int lpc_sch_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct mfd_cell lpc_sch_cells[3];
struct lpc_sch_info *info = &sch_chipset_info[id->driver_data];
unsigned int cells = 0;
int ret;
ret = lpc_sch_populate_cell(dev, SMBASE, "isch_smbus",
info->io_size_smbus,
id->device, &lpc_sch_cells[cells]);
if (ret < 0)
return ret;
if (ret == 0)
cells++;
ret = lpc_sch_populate_cell(dev, GPIO_BASE, "sch_gpio",
info->io_size_gpio,
id->device, &lpc_sch_cells[cells]);
if (ret < 0)
return ret;
if (ret == 0)
cells++;
ret = lpc_sch_populate_cell(dev, WDTBASE, "ie6xx_wdt",
info->io_size_wdt,
id->device, &lpc_sch_cells[cells]);
if (ret < 0)
return ret;
if (ret == 0)
cells++;
if (cells == 0) {
dev_err(&dev->dev, "All decode registers disabled.\n");
return -ENODEV;
}
return mfd_add_devices(&dev->dev, 0, lpc_sch_cells, cells, NULL, 0, NULL);
}
static void lpc_sch_remove(struct pci_dev *dev)
{
mfd_remove_devices(&dev->dev);
}
static struct pci_driver lpc_sch_driver = {
.name = "lpc_sch",
.id_table = lpc_sch_ids,
.probe = lpc_sch_probe,
.remove = lpc_sch_remove,
};
module_pci_driver(lpc_sch_driver);
MODULE_AUTHOR("Denis Turischev <[email protected]>");
MODULE_DESCRIPTION("LPC interface for Intel Poulsbo SCH");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/lpc_sch.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* System Control Driver
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng <[email protected]>
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/hwspinlock.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_data/syscon.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/mfd/syscon.h>
#include <linux/slab.h>
static struct platform_driver syscon_driver;
static DEFINE_SPINLOCK(syscon_list_slock);
static LIST_HEAD(syscon_list);
struct syscon {
struct device_node *np;
struct regmap *regmap;
struct reset_control *reset;
struct list_head list;
};
static const struct regmap_config syscon_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static struct syscon *of_syscon_register(struct device_node *np, bool check_res)
{
struct clk *clk;
struct syscon *syscon;
struct regmap *regmap;
void __iomem *base;
u32 reg_io_width;
int ret;
struct regmap_config syscon_config = syscon_regmap_config;
struct resource res;
struct reset_control *reset;
syscon = kzalloc(sizeof(*syscon), GFP_KERNEL);
if (!syscon)
return ERR_PTR(-ENOMEM);
if (of_address_to_resource(np, 0, &res)) {
ret = -ENOMEM;
goto err_map;
}
base = of_iomap(np, 0);
if (!base) {
ret = -ENOMEM;
goto err_map;
}
/* Parse the device's DT node for an endianness specification */
if (of_property_read_bool(np, "big-endian"))
syscon_config.val_format_endian = REGMAP_ENDIAN_BIG;
else if (of_property_read_bool(np, "little-endian"))
syscon_config.val_format_endian = REGMAP_ENDIAN_LITTLE;
else if (of_property_read_bool(np, "native-endian"))
syscon_config.val_format_endian = REGMAP_ENDIAN_NATIVE;
/*
* search for reg-io-width property in DT. If it is not provided,
* default to 4 bytes. regmap_init_mmio will return an error if values
* are invalid so there is no need to check them here.
*/
ret = of_property_read_u32(np, "reg-io-width", ®_io_width);
if (ret)
reg_io_width = 4;
ret = of_hwspin_lock_get_id(np, 0);
if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
syscon_config.use_hwlock = true;
syscon_config.hwlock_id = ret;
syscon_config.hwlock_mode = HWLOCK_IRQSTATE;
} else if (ret < 0) {
switch (ret) {
case -ENOENT:
/* Ignore missing hwlock, it's optional. */
break;
default:
pr_err("Failed to retrieve valid hwlock: %d\n", ret);
fallthrough;
case -EPROBE_DEFER:
goto err_regmap;
}
}
syscon_config.name = kasprintf(GFP_KERNEL, "%pOFn@%pa", np, &res.start);
syscon_config.reg_stride = reg_io_width;
syscon_config.val_bits = reg_io_width * 8;
syscon_config.max_register = resource_size(&res) - reg_io_width;
regmap = regmap_init_mmio(NULL, base, &syscon_config);
kfree(syscon_config.name);
if (IS_ERR(regmap)) {
pr_err("regmap init failed\n");
ret = PTR_ERR(regmap);
goto err_regmap;
}
if (check_res) {
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
/* clock is optional */
if (ret != -ENOENT)
goto err_clk;
} else {
ret = regmap_mmio_attach_clk(regmap, clk);
if (ret)
goto err_attach_clk;
}
reset = of_reset_control_get_optional_exclusive(np, NULL);
if (IS_ERR(reset)) {
ret = PTR_ERR(reset);
goto err_attach_clk;
}
ret = reset_control_deassert(reset);
if (ret)
goto err_reset;
}
syscon->regmap = regmap;
syscon->np = np;
spin_lock(&syscon_list_slock);
list_add_tail(&syscon->list, &syscon_list);
spin_unlock(&syscon_list_slock);
return syscon;
err_reset:
reset_control_put(reset);
err_attach_clk:
if (!IS_ERR(clk))
clk_put(clk);
err_clk:
regmap_exit(regmap);
err_regmap:
iounmap(base);
err_map:
kfree(syscon);
return ERR_PTR(ret);
}
static struct regmap *device_node_get_regmap(struct device_node *np,
bool check_res)
{
struct syscon *entry, *syscon = NULL;
spin_lock(&syscon_list_slock);
list_for_each_entry(entry, &syscon_list, list)
if (entry->np == np) {
syscon = entry;
break;
}
spin_unlock(&syscon_list_slock);
if (!syscon)
syscon = of_syscon_register(np, check_res);
if (IS_ERR(syscon))
return ERR_CAST(syscon);
return syscon->regmap;
}
struct regmap *device_node_to_regmap(struct device_node *np)
{
return device_node_get_regmap(np, false);
}
EXPORT_SYMBOL_GPL(device_node_to_regmap);
struct regmap *syscon_node_to_regmap(struct device_node *np)
{
if (!of_device_is_compatible(np, "syscon"))
return ERR_PTR(-EINVAL);
return device_node_get_regmap(np, true);
}
EXPORT_SYMBOL_GPL(syscon_node_to_regmap);
struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
{
struct device_node *syscon_np;
struct regmap *regmap;
syscon_np = of_find_compatible_node(NULL, NULL, s);
if (!syscon_np)
return ERR_PTR(-ENODEV);
regmap = syscon_node_to_regmap(syscon_np);
of_node_put(syscon_np);
return regmap;
}
EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_compatible);
struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,
const char *property)
{
struct device_node *syscon_np;
struct regmap *regmap;
if (property)
syscon_np = of_parse_phandle(np, property, 0);
else
syscon_np = np;
if (!syscon_np)
return ERR_PTR(-ENODEV);
regmap = syscon_node_to_regmap(syscon_np);
of_node_put(syscon_np);
return regmap;
}
EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_phandle);
struct regmap *syscon_regmap_lookup_by_phandle_args(struct device_node *np,
const char *property,
int arg_count,
unsigned int *out_args)
{
struct device_node *syscon_np;
struct of_phandle_args args;
struct regmap *regmap;
unsigned int index;
int rc;
rc = of_parse_phandle_with_fixed_args(np, property, arg_count,
0, &args);
if (rc)
return ERR_PTR(rc);
syscon_np = args.np;
if (!syscon_np)
return ERR_PTR(-ENODEV);
regmap = syscon_node_to_regmap(syscon_np);
for (index = 0; index < arg_count; index++)
out_args[index] = args.args[index];
of_node_put(syscon_np);
return regmap;
}
EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_phandle_args);
/*
* It behaves the same as syscon_regmap_lookup_by_phandle() except where
* there is no regmap phandle. In this case, instead of returning -ENODEV,
* the function returns NULL.
*/
struct regmap *syscon_regmap_lookup_by_phandle_optional(struct device_node *np,
const char *property)
{
struct regmap *regmap;
regmap = syscon_regmap_lookup_by_phandle(np, property);
if (IS_ERR(regmap) && PTR_ERR(regmap) == -ENODEV)
return NULL;
return regmap;
}
EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_phandle_optional);
static int syscon_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct syscon_platform_data *pdata = dev_get_platdata(dev);
struct syscon *syscon;
struct regmap_config syscon_config = syscon_regmap_config;
struct resource *res;
void __iomem *base;
syscon = devm_kzalloc(dev, sizeof(*syscon), GFP_KERNEL);
if (!syscon)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
base = devm_ioremap(dev, res->start, resource_size(res));
if (!base)
return -ENOMEM;
syscon_config.max_register = resource_size(res) - 4;
if (pdata)
syscon_config.name = pdata->label;
syscon->regmap = devm_regmap_init_mmio(dev, base, &syscon_config);
if (IS_ERR(syscon->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(syscon->regmap);
}
platform_set_drvdata(pdev, syscon);
dev_dbg(dev, "regmap %pR registered\n", res);
return 0;
}
static const struct platform_device_id syscon_ids[] = {
{ "syscon", },
{ }
};
static struct platform_driver syscon_driver = {
.driver = {
.name = "syscon",
},
.probe = syscon_probe,
.id_table = syscon_ids,
};
static int __init syscon_init(void)
{
return platform_driver_register(&syscon_driver);
}
postcore_initcall(syscon_init);
| linux-master | drivers/mfd/syscon.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Base driver for Analog Devices ADP5520/ADP5501 MFD PMICs
* LCD Backlight: drivers/video/backlight/adp5520_bl
* LEDs : drivers/led/leds-adp5520
* GPIO : drivers/gpio/adp5520-gpio (ADP5520 only)
* Keys : drivers/input/keyboard/adp5520-keys (ADP5520 only)
*
* Copyright 2009 Analog Devices Inc.
*
* Author: Michael Hennerich <[email protected]>
*
* Derived from da903x:
* Copyright (C) 2008 Compulab, Ltd.
* Mike Rapoport <[email protected]>
*
* Copyright (C) 2006-2008 Marvell International Ltd.
* Eric Miao <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/mfd/adp5520.h>
struct adp5520_chip {
struct i2c_client *client;
struct device *dev;
struct mutex lock;
struct blocking_notifier_head notifier_list;
int irq;
unsigned long id;
uint8_t mode;
};
static int __adp5520_read(struct i2c_client *client,
int reg, uint8_t *val)
{
int ret;
ret = i2c_smbus_read_byte_data(client, reg);
if (ret < 0) {
dev_err(&client->dev, "failed reading at 0x%02x\n", reg);
return ret;
}
*val = (uint8_t)ret;
return 0;
}
static int __adp5520_write(struct i2c_client *client,
int reg, uint8_t val)
{
int ret;
ret = i2c_smbus_write_byte_data(client, reg, val);
if (ret < 0) {
dev_err(&client->dev, "failed writing 0x%02x to 0x%02x\n",
val, reg);
return ret;
}
return 0;
}
static int __adp5520_ack_bits(struct i2c_client *client, int reg,
uint8_t bit_mask)
{
struct adp5520_chip *chip = i2c_get_clientdata(client);
uint8_t reg_val;
int ret;
mutex_lock(&chip->lock);
ret = __adp5520_read(client, reg, ®_val);
if (!ret) {
reg_val |= bit_mask;
ret = __adp5520_write(client, reg, reg_val);
}
mutex_unlock(&chip->lock);
return ret;
}
int adp5520_write(struct device *dev, int reg, uint8_t val)
{
return __adp5520_write(to_i2c_client(dev), reg, val);
}
EXPORT_SYMBOL_GPL(adp5520_write);
int adp5520_read(struct device *dev, int reg, uint8_t *val)
{
return __adp5520_read(to_i2c_client(dev), reg, val);
}
EXPORT_SYMBOL_GPL(adp5520_read);
int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask)
{
struct adp5520_chip *chip = dev_get_drvdata(dev);
uint8_t reg_val;
int ret;
mutex_lock(&chip->lock);
ret = __adp5520_read(chip->client, reg, ®_val);
if (!ret && ((reg_val & bit_mask) != bit_mask)) {
reg_val |= bit_mask;
ret = __adp5520_write(chip->client, reg, reg_val);
}
mutex_unlock(&chip->lock);
return ret;
}
EXPORT_SYMBOL_GPL(adp5520_set_bits);
int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask)
{
struct adp5520_chip *chip = dev_get_drvdata(dev);
uint8_t reg_val;
int ret;
mutex_lock(&chip->lock);
ret = __adp5520_read(chip->client, reg, ®_val);
if (!ret && (reg_val & bit_mask)) {
reg_val &= ~bit_mask;
ret = __adp5520_write(chip->client, reg, reg_val);
}
mutex_unlock(&chip->lock);
return ret;
}
EXPORT_SYMBOL_GPL(adp5520_clr_bits);
int adp5520_register_notifier(struct device *dev, struct notifier_block *nb,
unsigned int events)
{
struct adp5520_chip *chip = dev_get_drvdata(dev);
if (chip->irq) {
adp5520_set_bits(chip->dev, ADP5520_INTERRUPT_ENABLE,
events & (ADP5520_KP_IEN | ADP5520_KR_IEN |
ADP5520_OVP_IEN | ADP5520_CMPR_IEN));
return blocking_notifier_chain_register(&chip->notifier_list,
nb);
}
return -ENODEV;
}
EXPORT_SYMBOL_GPL(adp5520_register_notifier);
int adp5520_unregister_notifier(struct device *dev, struct notifier_block *nb,
unsigned int events)
{
struct adp5520_chip *chip = dev_get_drvdata(dev);
adp5520_clr_bits(chip->dev, ADP5520_INTERRUPT_ENABLE,
events & (ADP5520_KP_IEN | ADP5520_KR_IEN |
ADP5520_OVP_IEN | ADP5520_CMPR_IEN));
return blocking_notifier_chain_unregister(&chip->notifier_list, nb);
}
EXPORT_SYMBOL_GPL(adp5520_unregister_notifier);
static irqreturn_t adp5520_irq_thread(int irq, void *data)
{
struct adp5520_chip *chip = data;
unsigned int events;
uint8_t reg_val;
int ret;
ret = __adp5520_read(chip->client, ADP5520_MODE_STATUS, ®_val);
if (ret)
goto out;
events = reg_val & (ADP5520_OVP_INT | ADP5520_CMPR_INT |
ADP5520_GPI_INT | ADP5520_KR_INT | ADP5520_KP_INT);
blocking_notifier_call_chain(&chip->notifier_list, events, NULL);
/* ACK, Sticky bits are W1C */
__adp5520_ack_bits(chip->client, ADP5520_MODE_STATUS, events);
out:
return IRQ_HANDLED;
}
static int __remove_subdev(struct device *dev, void *unused)
{
platform_device_unregister(to_platform_device(dev));
return 0;
}
static int adp5520_remove_subdevs(struct adp5520_chip *chip)
{
return device_for_each_child(chip->dev, NULL, __remove_subdev);
}
static int adp5520_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct adp5520_platform_data *pdata = dev_get_platdata(&client->dev);
struct platform_device *pdev;
struct adp5520_chip *chip;
int ret;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA)) {
dev_err(&client->dev, "SMBUS Word Data not Supported\n");
return -EIO;
}
if (pdata == NULL) {
dev_err(&client->dev, "missing platform data\n");
return -ENODEV;
}
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
i2c_set_clientdata(client, chip);
chip->client = client;
chip->dev = &client->dev;
chip->irq = client->irq;
chip->id = id->driver_data;
mutex_init(&chip->lock);
if (chip->irq) {
BLOCKING_INIT_NOTIFIER_HEAD(&chip->notifier_list);
ret = request_threaded_irq(chip->irq, NULL, adp5520_irq_thread,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"adp5520", chip);
if (ret) {
dev_err(&client->dev, "failed to request irq %d\n",
chip->irq);
return ret;
}
}
ret = adp5520_write(chip->dev, ADP5520_MODE_STATUS, ADP5520_nSTNBY);
if (ret) {
dev_err(&client->dev, "failed to write\n");
goto out_free_irq;
}
if (pdata->keys) {
pdev = platform_device_register_data(chip->dev, "adp5520-keys",
chip->id, pdata->keys, sizeof(*pdata->keys));
if (IS_ERR(pdev)) {
ret = PTR_ERR(pdev);
goto out_remove_subdevs;
}
}
if (pdata->gpio) {
pdev = platform_device_register_data(chip->dev, "adp5520-gpio",
chip->id, pdata->gpio, sizeof(*pdata->gpio));
if (IS_ERR(pdev)) {
ret = PTR_ERR(pdev);
goto out_remove_subdevs;
}
}
if (pdata->leds) {
pdev = platform_device_register_data(chip->dev, "adp5520-led",
chip->id, pdata->leds, sizeof(*pdata->leds));
if (IS_ERR(pdev)) {
ret = PTR_ERR(pdev);
goto out_remove_subdevs;
}
}
if (pdata->backlight) {
pdev = platform_device_register_data(chip->dev,
"adp5520-backlight",
chip->id,
pdata->backlight,
sizeof(*pdata->backlight));
if (IS_ERR(pdev)) {
ret = PTR_ERR(pdev);
goto out_remove_subdevs;
}
}
return 0;
out_remove_subdevs:
adp5520_remove_subdevs(chip);
out_free_irq:
if (chip->irq)
free_irq(chip->irq, chip);
return ret;
}
static int adp5520_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct adp5520_chip *chip = dev_get_drvdata(&client->dev);
adp5520_read(chip->dev, ADP5520_MODE_STATUS, &chip->mode);
/* All other bits are W1C */
chip->mode &= ADP5520_BL_EN | ADP5520_DIM_EN | ADP5520_nSTNBY;
adp5520_write(chip->dev, ADP5520_MODE_STATUS, 0);
return 0;
}
static int adp5520_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct adp5520_chip *chip = dev_get_drvdata(&client->dev);
adp5520_write(chip->dev, ADP5520_MODE_STATUS, chip->mode);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(adp5520_pm, adp5520_suspend, adp5520_resume);
static const struct i2c_device_id adp5520_id[] = {
{ "pmic-adp5520", ID_ADP5520 },
{ "pmic-adp5501", ID_ADP5501 },
{ }
};
static struct i2c_driver adp5520_driver = {
.driver = {
.name = "adp5520",
.pm = pm_sleep_ptr(&adp5520_pm),
.suppress_bind_attrs = true,
},
.probe = adp5520_probe,
.id_table = adp5520_id,
};
builtin_i2c_driver(adp5520_driver);
| linux-master | drivers/mfd/adp5520.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* TQ-Systems PLD MFD core driver, based on vendor driver by
* Vadim V.Vlasov <[email protected]>
*
* Copyright (c) 2015 TQ-Systems GmbH
* Copyright (c) 2019 Andrew Lunn <[email protected]>
*/
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/platform_data/i2c-ocores.h>
#include <linux/platform_device.h>
#define TQMX86_IOBASE 0x180
#define TQMX86_IOSIZE 0x20
#define TQMX86_IOBASE_I2C 0x1a0
#define TQMX86_IOSIZE_I2C 0xa
#define TQMX86_IOBASE_WATCHDOG 0x18b
#define TQMX86_IOSIZE_WATCHDOG 0x2
#define TQMX86_IOBASE_GPIO 0x18d
#define TQMX86_IOSIZE_GPIO 0x4
#define TQMX86_REG_BOARD_ID 0x00
#define TQMX86_REG_BOARD_ID_E38M 1
#define TQMX86_REG_BOARD_ID_50UC 2
#define TQMX86_REG_BOARD_ID_E38C 3
#define TQMX86_REG_BOARD_ID_60EB 4
#define TQMX86_REG_BOARD_ID_E39MS 5
#define TQMX86_REG_BOARD_ID_E39C1 6
#define TQMX86_REG_BOARD_ID_E39C2 7
#define TQMX86_REG_BOARD_ID_70EB 8
#define TQMX86_REG_BOARD_ID_80UC 9
#define TQMX86_REG_BOARD_ID_110EB 11
#define TQMX86_REG_BOARD_ID_E40M 12
#define TQMX86_REG_BOARD_ID_E40S 13
#define TQMX86_REG_BOARD_ID_E40C1 14
#define TQMX86_REG_BOARD_ID_E40C2 15
#define TQMX86_REG_BOARD_REV 0x01
#define TQMX86_REG_IO_EXT_INT 0x06
#define TQMX86_REG_IO_EXT_INT_NONE 0
#define TQMX86_REG_IO_EXT_INT_7 1
#define TQMX86_REG_IO_EXT_INT_9 2
#define TQMX86_REG_IO_EXT_INT_12 3
#define TQMX86_REG_IO_EXT_INT_MASK 0x3
#define TQMX86_REG_IO_EXT_INT_GPIO_SHIFT 4
#define TQMX86_REG_SAUC 0x17
#define TQMX86_REG_I2C_DETECT 0x1a7
#define TQMX86_REG_I2C_DETECT_SOFT 0xa5
static uint gpio_irq;
module_param(gpio_irq, uint, 0);
MODULE_PARM_DESC(gpio_irq, "GPIO IRQ number (7, 9, 12)");
static const struct resource tqmx_i2c_soft_resources[] = {
DEFINE_RES_IO(TQMX86_IOBASE_I2C, TQMX86_IOSIZE_I2C),
};
static const struct resource tqmx_watchdog_resources[] = {
DEFINE_RES_IO(TQMX86_IOBASE_WATCHDOG, TQMX86_IOSIZE_WATCHDOG),
};
/*
* The IRQ resource must be first, since it is updated with the
* configured IRQ in the probe function.
*/
static struct resource tqmx_gpio_resources[] = {
DEFINE_RES_IRQ(0),
DEFINE_RES_IO(TQMX86_IOBASE_GPIO, TQMX86_IOSIZE_GPIO),
};
static struct i2c_board_info tqmx86_i2c_devices[] = {
{
/* 4K EEPROM at 0x50 */
I2C_BOARD_INFO("24c32", 0x50),
},
};
static struct ocores_i2c_platform_data ocores_platform_data = {
.num_devices = ARRAY_SIZE(tqmx86_i2c_devices),
.devices = tqmx86_i2c_devices,
};
static const struct mfd_cell tqmx86_i2c_soft_dev[] = {
{
.name = "ocores-i2c",
.platform_data = &ocores_platform_data,
.pdata_size = sizeof(ocores_platform_data),
.resources = tqmx_i2c_soft_resources,
.num_resources = ARRAY_SIZE(tqmx_i2c_soft_resources),
},
};
static const struct mfd_cell tqmx86_devs[] = {
{
.name = "tqmx86-wdt",
.resources = tqmx_watchdog_resources,
.num_resources = ARRAY_SIZE(tqmx_watchdog_resources),
.ignore_resource_conflicts = true,
},
{
.name = "tqmx86-gpio",
.resources = tqmx_gpio_resources,
.num_resources = ARRAY_SIZE(tqmx_gpio_resources),
.ignore_resource_conflicts = true,
},
};
static const char *tqmx86_board_id_to_name(u8 board_id, u8 sauc)
{
switch (board_id) {
case TQMX86_REG_BOARD_ID_E38M:
return "TQMxE38M";
case TQMX86_REG_BOARD_ID_50UC:
return "TQMx50UC";
case TQMX86_REG_BOARD_ID_E38C:
return "TQMxE38C";
case TQMX86_REG_BOARD_ID_60EB:
return "TQMx60EB";
case TQMX86_REG_BOARD_ID_E39MS:
return (sauc == 0xff) ? "TQMxE39M" : "TQMxE39S";
case TQMX86_REG_BOARD_ID_E39C1:
return "TQMxE39C1";
case TQMX86_REG_BOARD_ID_E39C2:
return "TQMxE39C2";
case TQMX86_REG_BOARD_ID_70EB:
return "TQMx70EB";
case TQMX86_REG_BOARD_ID_80UC:
return "TQMx80UC";
case TQMX86_REG_BOARD_ID_110EB:
return "TQMx110EB";
case TQMX86_REG_BOARD_ID_E40M:
return "TQMxE40M";
case TQMX86_REG_BOARD_ID_E40S:
return "TQMxE40S";
case TQMX86_REG_BOARD_ID_E40C1:
return "TQMxE40C1";
case TQMX86_REG_BOARD_ID_E40C2:
return "TQMxE40C2";
default:
return "Unknown";
}
}
static int tqmx86_board_id_to_clk_rate(struct device *dev, u8 board_id)
{
switch (board_id) {
case TQMX86_REG_BOARD_ID_50UC:
case TQMX86_REG_BOARD_ID_60EB:
case TQMX86_REG_BOARD_ID_70EB:
case TQMX86_REG_BOARD_ID_80UC:
case TQMX86_REG_BOARD_ID_110EB:
case TQMX86_REG_BOARD_ID_E40M:
case TQMX86_REG_BOARD_ID_E40S:
case TQMX86_REG_BOARD_ID_E40C1:
case TQMX86_REG_BOARD_ID_E40C2:
return 24000;
case TQMX86_REG_BOARD_ID_E39MS:
case TQMX86_REG_BOARD_ID_E39C1:
case TQMX86_REG_BOARD_ID_E39C2:
return 25000;
case TQMX86_REG_BOARD_ID_E38M:
case TQMX86_REG_BOARD_ID_E38C:
return 33000;
default:
dev_warn(dev, "unknown board %d, assuming 24MHz LPC clock\n",
board_id);
return 24000;
}
}
static int tqmx86_probe(struct platform_device *pdev)
{
u8 board_id, sauc, rev, i2c_det, io_ext_int_val;
struct device *dev = &pdev->dev;
u8 gpio_irq_cfg, readback;
const char *board_name;
void __iomem *io_base;
int err;
switch (gpio_irq) {
case 0:
gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_NONE;
break;
case 7:
gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_7;
break;
case 9:
gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_9;
break;
case 12:
gpio_irq_cfg = TQMX86_REG_IO_EXT_INT_12;
break;
default:
pr_err("tqmx86: Invalid GPIO IRQ (%d)\n", gpio_irq);
return -EINVAL;
}
io_base = devm_ioport_map(dev, TQMX86_IOBASE, TQMX86_IOSIZE);
if (!io_base)
return -ENOMEM;
board_id = ioread8(io_base + TQMX86_REG_BOARD_ID);
sauc = ioread8(io_base + TQMX86_REG_SAUC);
board_name = tqmx86_board_id_to_name(board_id, sauc);
rev = ioread8(io_base + TQMX86_REG_BOARD_REV);
dev_info(dev,
"Found %s - Board ID %d, PCB Revision %d, PLD Revision %d\n",
board_name, board_id, rev >> 4, rev & 0xf);
/*
* The I2C_DETECT register is in the range assigned to the I2C driver
* later, so we don't extend TQMX86_IOSIZE. Use inb() for this one-off
* access instead of ioport_map + unmap.
*/
i2c_det = inb(TQMX86_REG_I2C_DETECT);
if (gpio_irq_cfg) {
io_ext_int_val =
gpio_irq_cfg << TQMX86_REG_IO_EXT_INT_GPIO_SHIFT;
iowrite8(io_ext_int_val, io_base + TQMX86_REG_IO_EXT_INT);
readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT);
if (readback != io_ext_int_val) {
dev_warn(dev, "GPIO interrupts not supported.\n");
return -EINVAL;
}
/* Assumes the IRQ resource is first. */
tqmx_gpio_resources[0].start = gpio_irq;
} else {
tqmx_gpio_resources[0].flags = 0;
}
ocores_platform_data.clock_khz = tqmx86_board_id_to_clk_rate(dev, board_id);
if (i2c_det == TQMX86_REG_I2C_DETECT_SOFT) {
err = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
tqmx86_i2c_soft_dev,
ARRAY_SIZE(tqmx86_i2c_soft_dev),
NULL, 0, NULL);
if (err)
return err;
}
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
tqmx86_devs,
ARRAY_SIZE(tqmx86_devs),
NULL, 0, NULL);
}
static int tqmx86_create_platform_device(const struct dmi_system_id *id)
{
struct platform_device *pdev;
int err;
pdev = platform_device_alloc("tqmx86", -1);
if (!pdev)
return -ENOMEM;
err = platform_device_add(pdev);
if (err)
platform_device_put(pdev);
return err;
}
static const struct dmi_system_id tqmx86_dmi_table[] __initconst = {
{
.ident = "TQMX86",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "TQ-Group"),
DMI_MATCH(DMI_PRODUCT_NAME, "TQMx"),
},
.callback = tqmx86_create_platform_device,
},
{
.ident = "TQMX86",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "TQ-Systems"),
DMI_MATCH(DMI_PRODUCT_NAME, "TQMx"),
},
.callback = tqmx86_create_platform_device,
},
{}
};
MODULE_DEVICE_TABLE(dmi, tqmx86_dmi_table);
static struct platform_driver tqmx86_driver = {
.driver = {
.name = "tqmx86",
},
.probe = tqmx86_probe,
};
static int __init tqmx86_init(void)
{
if (!dmi_check_system(tqmx86_dmi_table))
return -ENODEV;
return platform_driver_register(&tqmx86_driver);
}
module_init(tqmx86_init);
MODULE_DESCRIPTION("TQMx86 PLD Core Driver");
MODULE_AUTHOR("Andrew Lunn <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:tqmx86");
| linux-master | drivers/mfd/tqmx86.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* tps65010 - driver for tps6501x power management chips
*
* Copyright (C) 2004 Texas Instruments
* Copyright (C) 2004-2005 David Brownell
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/mfd/tps65010.h>
#include <linux/gpio/driver.h>
/*-------------------------------------------------------------------------*/
#define DRIVER_VERSION "2 May 2005"
#define DRIVER_NAME (tps65010_driver.driver.name)
MODULE_DESCRIPTION("TPS6501x Power Management Driver");
MODULE_LICENSE("GPL");
static struct i2c_driver tps65010_driver;
/*-------------------------------------------------------------------------*/
/* This driver handles a family of multipurpose chips, which incorporate
* voltage regulators, lithium ion/polymer battery charging, GPIOs, LEDs,
* and other features often needed in portable devices like cell phones
* or digital cameras.
*
* The tps65011 and tps65013 have different voltage settings compared
* to tps65010 and tps65012. The tps65013 has a NO_CHG status/irq.
* All except tps65010 have "wait" mode, possibly defaulted so that
* battery-insert != device-on.
*
* We could distinguish between some models by checking VDCDC1.UVLO or
* other registers, unless they've been changed already after powerup
* as part of board setup by a bootloader.
*/
enum tps_model {
TPS65010,
TPS65011,
TPS65012,
TPS65013,
};
struct tps65010 {
struct i2c_client *client;
struct mutex lock;
struct delayed_work work;
struct dentry *file;
unsigned charging:1;
unsigned por:1;
unsigned model:8;
u16 vbus;
unsigned long flags;
#define FLAG_VBUS_CHANGED 0
#define FLAG_IRQ_ENABLE 1
/* copies of last register state */
u8 chgstatus, regstatus, chgconf;
u8 nmask1, nmask2;
u8 outmask;
struct gpio_chip chip;
struct platform_device *leds;
};
#define POWER_POLL_DELAY msecs_to_jiffies(5000)
/*-------------------------------------------------------------------------*/
#if defined(DEBUG) || defined(CONFIG_DEBUG_FS)
static void dbg_chgstat(char *buf, size_t len, u8 chgstatus)
{
snprintf(buf, len, "%02x%s%s%s%s%s%s%s%s\n",
chgstatus,
(chgstatus & TPS_CHG_USB) ? " USB" : "",
(chgstatus & TPS_CHG_AC) ? " AC" : "",
(chgstatus & TPS_CHG_THERM) ? " therm" : "",
(chgstatus & TPS_CHG_TERM) ? " done" :
((chgstatus & (TPS_CHG_USB|TPS_CHG_AC))
? " (charging)" : ""),
(chgstatus & TPS_CHG_TAPER_TMO) ? " taper_tmo" : "",
(chgstatus & TPS_CHG_CHG_TMO) ? " charge_tmo" : "",
(chgstatus & TPS_CHG_PRECHG_TMO) ? " prechg_tmo" : "",
(chgstatus & TPS_CHG_TEMP_ERR) ? " temp_err" : "");
}
static void dbg_regstat(char *buf, size_t len, u8 regstatus)
{
snprintf(buf, len, "%02x %s%s%s%s%s%s%s%s\n",
regstatus,
(regstatus & TPS_REG_ONOFF) ? "off" : "(on)",
(regstatus & TPS_REG_COVER) ? " uncover" : "",
(regstatus & TPS_REG_UVLO) ? " UVLO" : "",
(regstatus & TPS_REG_NO_CHG) ? " NO_CHG" : "",
(regstatus & TPS_REG_PG_LD02) ? " ld02_bad" : "",
(regstatus & TPS_REG_PG_LD01) ? " ld01_bad" : "",
(regstatus & TPS_REG_PG_MAIN) ? " main_bad" : "",
(regstatus & TPS_REG_PG_CORE) ? " core_bad" : "");
}
static void dbg_chgconf(int por, char *buf, size_t len, u8 chgconfig)
{
const char *hibit;
if (por)
hibit = (chgconfig & TPS_CHARGE_POR)
? "POR=69ms" : "POR=1sec";
else
hibit = (chgconfig & TPS65013_AUA) ? "AUA" : "";
snprintf(buf, len, "%02x %s%s%s AC=%d%% USB=%dmA %sCharge\n",
chgconfig, hibit,
(chgconfig & TPS_CHARGE_RESET) ? " reset" : "",
(chgconfig & TPS_CHARGE_FAST) ? " fast" : "",
({int p; switch ((chgconfig >> 3) & 3) {
case 3: p = 100; break;
case 2: p = 75; break;
case 1: p = 50; break;
default: p = 25; break;
}; p; }),
(chgconfig & TPS_VBUS_CHARGING)
? ((chgconfig & TPS_VBUS_500MA) ? 500 : 100)
: 0,
(chgconfig & TPS_CHARGE_ENABLE) ? "" : "No");
}
#endif
#ifdef DEBUG
static void show_chgstatus(const char *label, u8 chgstatus)
{
char buf [100];
dbg_chgstat(buf, sizeof buf, chgstatus);
pr_debug("%s: %s %s", DRIVER_NAME, label, buf);
}
static void show_regstatus(const char *label, u8 regstatus)
{
char buf [100];
dbg_regstat(buf, sizeof buf, regstatus);
pr_debug("%s: %s %s", DRIVER_NAME, label, buf);
}
static void show_chgconfig(int por, const char *label, u8 chgconfig)
{
char buf [100];
dbg_chgconf(por, buf, sizeof buf, chgconfig);
pr_debug("%s: %s %s", DRIVER_NAME, label, buf);
}
#else
static inline void show_chgstatus(const char *label, u8 chgstatus) { }
static inline void show_regstatus(const char *label, u8 chgstatus) { }
static inline void show_chgconfig(int por, const char *label, u8 chgconfig) { }
#endif
#ifdef CONFIG_DEBUG_FS
static int dbg_show(struct seq_file *s, void *_)
{
struct tps65010 *tps = s->private;
u8 value, v2;
unsigned i;
char buf[100];
const char *chip;
switch (tps->model) {
case TPS65010: chip = "tps65010"; break;
case TPS65011: chip = "tps65011"; break;
case TPS65012: chip = "tps65012"; break;
case TPS65013: chip = "tps65013"; break;
default: chip = NULL; break;
}
seq_printf(s, "driver %s\nversion %s\nchip %s\n\n",
DRIVER_NAME, DRIVER_VERSION, chip);
mutex_lock(&tps->lock);
/* FIXME how can we tell whether a battery is present?
* likely involves a charge gauging chip (like BQ26501).
*/
seq_printf(s, "%scharging\n\n", tps->charging ? "" : "(not) ");
/* registers for monitoring battery charging and status; note
* that reading chgstat and regstat may ack IRQs...
*/
value = i2c_smbus_read_byte_data(tps->client, TPS_CHGCONFIG);
dbg_chgconf(tps->por, buf, sizeof buf, value);
seq_printf(s, "chgconfig %s", buf);
value = i2c_smbus_read_byte_data(tps->client, TPS_CHGSTATUS);
dbg_chgstat(buf, sizeof buf, value);
seq_printf(s, "chgstat %s", buf);
value = i2c_smbus_read_byte_data(tps->client, TPS_MASK1);
dbg_chgstat(buf, sizeof buf, value);
seq_printf(s, "mask1 %s", buf);
/* ignore ackint1 */
value = i2c_smbus_read_byte_data(tps->client, TPS_REGSTATUS);
dbg_regstat(buf, sizeof buf, value);
seq_printf(s, "regstat %s", buf);
value = i2c_smbus_read_byte_data(tps->client, TPS_MASK2);
dbg_regstat(buf, sizeof buf, value);
seq_printf(s, "mask2 %s\n", buf);
/* ignore ackint2 */
queue_delayed_work(system_power_efficient_wq, &tps->work,
POWER_POLL_DELAY);
/* VMAIN voltage, enable lowpower, etc */
value = i2c_smbus_read_byte_data(tps->client, TPS_VDCDC1);
seq_printf(s, "vdcdc1 %02x\n", value);
/* VCORE voltage, vibrator on/off */
value = i2c_smbus_read_byte_data(tps->client, TPS_VDCDC2);
seq_printf(s, "vdcdc2 %02x\n", value);
/* both LD0s, and their lowpower behavior */
value = i2c_smbus_read_byte_data(tps->client, TPS_VREGS1);
seq_printf(s, "vregs1 %02x\n\n", value);
/* LEDs and GPIOs */
value = i2c_smbus_read_byte_data(tps->client, TPS_LED1_ON);
v2 = i2c_smbus_read_byte_data(tps->client, TPS_LED1_PER);
seq_printf(s, "led1 %s, on=%02x, per=%02x, %d/%d msec\n",
(value & 0x80)
? ((v2 & 0x80) ? "on" : "off")
: ((v2 & 0x80) ? "blink" : "(nPG)"),
value, v2,
(value & 0x7f) * 10, (v2 & 0x7f) * 100);
value = i2c_smbus_read_byte_data(tps->client, TPS_LED2_ON);
v2 = i2c_smbus_read_byte_data(tps->client, TPS_LED2_PER);
seq_printf(s, "led2 %s, on=%02x, per=%02x, %d/%d msec\n",
(value & 0x80)
? ((v2 & 0x80) ? "on" : "off")
: ((v2 & 0x80) ? "blink" : "off"),
value, v2,
(value & 0x7f) * 10, (v2 & 0x7f) * 100);
value = i2c_smbus_read_byte_data(tps->client, TPS_DEFGPIO);
v2 = i2c_smbus_read_byte_data(tps->client, TPS_MASK3);
seq_printf(s, "defgpio %02x mask3 %02x\n", value, v2);
for (i = 0; i < 4; i++) {
if (value & (1 << (4 + i)))
seq_printf(s, " gpio%d-out %s\n", i + 1,
(value & (1 << i)) ? "low" : "hi ");
else
seq_printf(s, " gpio%d-in %s %s %s\n", i + 1,
(value & (1 << i)) ? "hi " : "low",
(v2 & (1 << i)) ? "no-irq" : "irq",
(v2 & (1 << (4 + i))) ? "rising" : "falling");
}
mutex_unlock(&tps->lock);
return 0;
}
static int dbg_tps_open(struct inode *inode, struct file *file)
{
return single_open(file, dbg_show, inode->i_private);
}
static const struct file_operations debug_fops = {
.open = dbg_tps_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
#define DEBUG_FOPS &debug_fops
#else
#define DEBUG_FOPS NULL
#endif
/*-------------------------------------------------------------------------*/
/* handle IRQS in a task context, so we can use I2C calls */
static void tps65010_interrupt(struct tps65010 *tps)
{
u8 tmp = 0, mask, poll;
/* IRQs won't trigger for certain events, but we can get
* others by polling (normally, with external power applied).
*/
poll = 0;
/* regstatus irqs */
if (tps->nmask2) {
tmp = i2c_smbus_read_byte_data(tps->client, TPS_REGSTATUS);
mask = tmp ^ tps->regstatus;
tps->regstatus = tmp;
mask &= tps->nmask2;
} else
mask = 0;
if (mask) {
tps->regstatus = tmp;
/* may need to shut something down ... */
/* "off" usually means deep sleep */
if (tmp & TPS_REG_ONOFF) {
pr_info("%s: power off button\n", DRIVER_NAME);
#if 0
/* REVISIT: this might need its own workqueue
* plus tweaks including deadlock avoidance ...
* also needs to get error handling and probably
* an #ifdef CONFIG_HIBERNATION
*/
hibernate();
#endif
poll = 1;
}
}
/* chgstatus irqs */
if (tps->nmask1) {
tmp = i2c_smbus_read_byte_data(tps->client, TPS_CHGSTATUS);
mask = tmp ^ tps->chgstatus;
tps->chgstatus = tmp;
mask &= tps->nmask1;
} else
mask = 0;
if (mask) {
unsigned charging = 0;
show_chgstatus("chg/irq", tmp);
if (tmp & (TPS_CHG_USB|TPS_CHG_AC))
show_chgconfig(tps->por, "conf", tps->chgconf);
/* Unless it was turned off or disabled, we charge any
* battery whenever there's power available for it
* and the charger hasn't been disabled.
*/
if (!(tps->chgstatus & ~(TPS_CHG_USB|TPS_CHG_AC))
&& (tps->chgstatus & (TPS_CHG_USB|TPS_CHG_AC))
&& (tps->chgconf & TPS_CHARGE_ENABLE)
) {
if (tps->chgstatus & TPS_CHG_USB) {
/* VBUS options are readonly until reconnect */
if (mask & TPS_CHG_USB)
set_bit(FLAG_VBUS_CHANGED, &tps->flags);
charging = 1;
} else if (tps->chgstatus & TPS_CHG_AC)
charging = 1;
}
if (charging != tps->charging) {
tps->charging = charging;
pr_info("%s: battery %scharging\n",
DRIVER_NAME, charging ? "" :
((tps->chgstatus & (TPS_CHG_USB|TPS_CHG_AC))
? "NOT " : "dis"));
}
}
/* always poll to detect (a) power removal, without tps65013
* NO_CHG IRQ; or (b) restart of charging after stop.
*/
if ((tps->model != TPS65013 || !tps->charging)
&& (tps->chgstatus & (TPS_CHG_USB|TPS_CHG_AC)))
poll = 1;
if (poll)
queue_delayed_work(system_power_efficient_wq, &tps->work,
POWER_POLL_DELAY);
/* also potentially gpio-in rise or fall */
}
/* handle IRQs and polling using keventd for now */
static void tps65010_work(struct work_struct *work)
{
struct tps65010 *tps;
tps = container_of(to_delayed_work(work), struct tps65010, work);
mutex_lock(&tps->lock);
tps65010_interrupt(tps);
if (test_and_clear_bit(FLAG_VBUS_CHANGED, &tps->flags)) {
u8 chgconfig, tmp;
chgconfig = i2c_smbus_read_byte_data(tps->client,
TPS_CHGCONFIG);
chgconfig &= ~(TPS_VBUS_500MA | TPS_VBUS_CHARGING);
if (tps->vbus == 500)
chgconfig |= TPS_VBUS_500MA | TPS_VBUS_CHARGING;
else if (tps->vbus >= 100)
chgconfig |= TPS_VBUS_CHARGING;
i2c_smbus_write_byte_data(tps->client,
TPS_CHGCONFIG, chgconfig);
/* vbus update fails unless VBUS is connected! */
tmp = i2c_smbus_read_byte_data(tps->client, TPS_CHGCONFIG);
tps->chgconf = tmp;
show_chgconfig(tps->por, "update vbus", tmp);
}
if (test_and_clear_bit(FLAG_IRQ_ENABLE, &tps->flags))
enable_irq(tps->client->irq);
mutex_unlock(&tps->lock);
}
static irqreturn_t tps65010_irq(int irq, void *_tps)
{
struct tps65010 *tps = _tps;
disable_irq_nosync(irq);
set_bit(FLAG_IRQ_ENABLE, &tps->flags);
queue_delayed_work(system_power_efficient_wq, &tps->work, 0);
return IRQ_HANDLED;
}
/*-------------------------------------------------------------------------*/
/* offsets 0..3 == GPIO1..GPIO4
* offsets 4..5 == LED1/nPG, LED2 (we set one of the non-BLINK modes)
* offset 6 == vibrator motor driver
*/
static void
tps65010_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
if (offset < 4)
tps65010_set_gpio_out_value(offset + 1, value);
else if (offset < 6)
tps65010_set_led(offset - 3, value ? ON : OFF);
else
tps65010_set_vib(value);
}
static int
tps65010_output(struct gpio_chip *chip, unsigned offset, int value)
{
/* GPIOs may be input-only */
if (offset < 4) {
struct tps65010 *tps;
tps = gpiochip_get_data(chip);
if (!(tps->outmask & (1 << offset)))
return -EINVAL;
tps65010_set_gpio_out_value(offset + 1, value);
} else if (offset < 6)
tps65010_set_led(offset - 3, value ? ON : OFF);
else
tps65010_set_vib(value);
return 0;
}
static int tps65010_gpio_get(struct gpio_chip *chip, unsigned offset)
{
int value;
struct tps65010 *tps;
tps = gpiochip_get_data(chip);
if (offset < 4) {
value = i2c_smbus_read_byte_data(tps->client, TPS_DEFGPIO);
if (value < 0)
return value;
if (value & (1 << (offset + 4))) /* output */
return !(value & (1 << offset));
else /* input */
return !!(value & (1 << offset));
}
/* REVISIT we *could* report LED1/nPG and LED2 state ... */
return 0;
}
/*-------------------------------------------------------------------------*/
static struct tps65010 *the_tps;
static void tps65010_remove(struct i2c_client *client)
{
struct tps65010 *tps = i2c_get_clientdata(client);
struct tps65010_board *board = dev_get_platdata(&client->dev);
if (board && board->teardown)
board->teardown(client, &tps->chip);
if (client->irq > 0)
free_irq(client->irq, tps);
cancel_delayed_work_sync(&tps->work);
debugfs_remove(tps->file);
the_tps = NULL;
}
static int tps65010_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct tps65010 *tps;
int status;
struct tps65010_board *board = dev_get_platdata(&client->dev);
if (the_tps) {
dev_dbg(&client->dev, "only one tps6501x chip allowed\n");
return -ENODEV;
}
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -EINVAL;
tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
mutex_init(&tps->lock);
INIT_DELAYED_WORK(&tps->work, tps65010_work);
tps->client = client;
tps->model = id->driver_data;
/* the IRQ is active low, but many gpio lines can't support that
* so this driver uses falling-edge triggers instead.
*/
if (client->irq > 0) {
status = request_irq(client->irq, tps65010_irq,
IRQF_TRIGGER_FALLING, DRIVER_NAME, tps);
if (status < 0) {
dev_dbg(&client->dev, "can't get IRQ %d, err %d\n",
client->irq, status);
return status;
}
/* annoying race here, ideally we'd have an option
* to claim the irq now and enable it later.
* FIXME genirq IRQF_NOAUTOEN now solves that ...
*/
disable_irq(client->irq);
set_bit(FLAG_IRQ_ENABLE, &tps->flags);
} else
dev_warn(&client->dev, "IRQ not configured!\n");
switch (tps->model) {
case TPS65010:
case TPS65012:
tps->por = 1;
break;
/* else CHGCONFIG.POR is replaced by AUA, enabling a WAIT mode */
}
tps->chgconf = i2c_smbus_read_byte_data(client, TPS_CHGCONFIG);
show_chgconfig(tps->por, "conf/init", tps->chgconf);
show_chgstatus("chg/init",
i2c_smbus_read_byte_data(client, TPS_CHGSTATUS));
show_regstatus("reg/init",
i2c_smbus_read_byte_data(client, TPS_REGSTATUS));
pr_debug("%s: vdcdc1 0x%02x, vdcdc2 %02x, vregs1 %02x\n", DRIVER_NAME,
i2c_smbus_read_byte_data(client, TPS_VDCDC1),
i2c_smbus_read_byte_data(client, TPS_VDCDC2),
i2c_smbus_read_byte_data(client, TPS_VREGS1));
pr_debug("%s: defgpio 0x%02x, mask3 0x%02x\n", DRIVER_NAME,
i2c_smbus_read_byte_data(client, TPS_DEFGPIO),
i2c_smbus_read_byte_data(client, TPS_MASK3));
i2c_set_clientdata(client, tps);
the_tps = tps;
#if defined(CONFIG_USB_GADGET) && !defined(CONFIG_USB_OTG)
/* USB hosts can't draw VBUS. OTG devices could, later
* when OTG infrastructure enables it. USB peripherals
* could be relying on VBUS while booting, though.
*/
tps->vbus = 100;
#endif
/* unmask the "interesting" irqs, then poll once to
* kickstart monitoring, initialize shadowed status
* registers, and maybe disable VBUS draw.
*/
tps->nmask1 = ~0;
(void) i2c_smbus_write_byte_data(client, TPS_MASK1, ~tps->nmask1);
tps->nmask2 = TPS_REG_ONOFF;
if (tps->model == TPS65013)
tps->nmask2 |= TPS_REG_NO_CHG;
(void) i2c_smbus_write_byte_data(client, TPS_MASK2, ~tps->nmask2);
(void) i2c_smbus_write_byte_data(client, TPS_MASK3, 0x0f
| i2c_smbus_read_byte_data(client, TPS_MASK3));
tps65010_work(&tps->work.work);
tps->file = debugfs_create_file(DRIVER_NAME, S_IRUGO, NULL,
tps, DEBUG_FOPS);
/* optionally register GPIOs */
if (board) {
tps->outmask = board->outmask;
tps->chip.label = client->name;
tps->chip.parent = &client->dev;
tps->chip.owner = THIS_MODULE;
tps->chip.set = tps65010_gpio_set;
tps->chip.direction_output = tps65010_output;
/* NOTE: only partial support for inputs; nyet IRQs */
tps->chip.get = tps65010_gpio_get;
tps->chip.base = -1;
tps->chip.ngpio = 7;
tps->chip.can_sleep = 1;
status = gpiochip_add_data(&tps->chip, tps);
if (status < 0)
dev_err(&client->dev, "can't add gpiochip, err %d\n",
status);
else if (board->setup) {
status = board->setup(client, &tps->chip);
if (status < 0) {
dev_dbg(&client->dev,
"board %s %s err %d\n",
"setup", client->name, status);
status = 0;
}
}
}
return 0;
}
static const struct i2c_device_id tps65010_id[] = {
{ "tps65010", TPS65010 },
{ "tps65011", TPS65011 },
{ "tps65012", TPS65012 },
{ "tps65013", TPS65013 },
{ "tps65014", TPS65011 }, /* tps65011 charging at 6.5V max */
{ }
};
MODULE_DEVICE_TABLE(i2c, tps65010_id);
static struct i2c_driver tps65010_driver = {
.driver = {
.name = "tps65010",
},
.probe = tps65010_probe,
.remove = tps65010_remove,
.id_table = tps65010_id,
};
/*-------------------------------------------------------------------------*/
/* Draw from VBUS:
* 0 mA -- DON'T DRAW (might supply power instead)
* 100 mA -- usb unit load (slowest charge rate)
* 500 mA -- usb high power (fast battery charge)
*/
int tps65010_set_vbus_draw(unsigned mA)
{
unsigned long flags;
if (!the_tps)
return -ENODEV;
/* assumes non-SMP */
local_irq_save(flags);
if (mA >= 500)
mA = 500;
else if (mA >= 100)
mA = 100;
else
mA = 0;
the_tps->vbus = mA;
if ((the_tps->chgstatus & TPS_CHG_USB)
&& test_and_set_bit(
FLAG_VBUS_CHANGED, &the_tps->flags)) {
/* gadget drivers call this in_irq() */
queue_delayed_work(system_power_efficient_wq, &the_tps->work,
0);
}
local_irq_restore(flags);
return 0;
}
EXPORT_SYMBOL(tps65010_set_vbus_draw);
/*-------------------------------------------------------------------------*/
/* tps65010_set_gpio_out_value parameter:
* gpio: GPIO1, GPIO2, GPIO3 or GPIO4
* value: LOW or HIGH
*/
int tps65010_set_gpio_out_value(unsigned gpio, unsigned value)
{
int status;
unsigned defgpio;
if (!the_tps)
return -ENODEV;
if ((gpio < GPIO1) || (gpio > GPIO4))
return -EINVAL;
mutex_lock(&the_tps->lock);
defgpio = i2c_smbus_read_byte_data(the_tps->client, TPS_DEFGPIO);
/* Configure GPIO for output */
defgpio |= 1 << (gpio + 3);
/* Writing 1 forces a logic 0 on that GPIO and vice versa */
switch (value) {
case LOW:
defgpio |= 1 << (gpio - 1); /* set GPIO low by writing 1 */
break;
/* case HIGH: */
default:
defgpio &= ~(1 << (gpio - 1)); /* set GPIO high by writing 0 */
break;
}
status = i2c_smbus_write_byte_data(the_tps->client,
TPS_DEFGPIO, defgpio);
pr_debug("%s: gpio%dout = %s, defgpio 0x%02x\n", DRIVER_NAME,
gpio, value ? "high" : "low",
i2c_smbus_read_byte_data(the_tps->client, TPS_DEFGPIO));
mutex_unlock(&the_tps->lock);
return status;
}
EXPORT_SYMBOL(tps65010_set_gpio_out_value);
/*-------------------------------------------------------------------------*/
/* tps65010_set_led parameter:
* led: LED1 or LED2
* mode: ON, OFF or BLINK
*/
int tps65010_set_led(unsigned led, unsigned mode)
{
int status;
unsigned led_on, led_per, offs;
if (!the_tps)
return -ENODEV;
if (led == LED1)
offs = 0;
else {
offs = 2;
led = LED2;
}
mutex_lock(&the_tps->lock);
pr_debug("%s: led%i_on 0x%02x\n", DRIVER_NAME, led,
i2c_smbus_read_byte_data(the_tps->client,
TPS_LED1_ON + offs));
pr_debug("%s: led%i_per 0x%02x\n", DRIVER_NAME, led,
i2c_smbus_read_byte_data(the_tps->client,
TPS_LED1_PER + offs));
switch (mode) {
case OFF:
led_on = 1 << 7;
led_per = 0 << 7;
break;
case ON:
led_on = 1 << 7;
led_per = 1 << 7;
break;
case BLINK:
led_on = 0x30 | (0 << 7);
led_per = 0x08 | (1 << 7);
break;
default:
printk(KERN_ERR "%s: Wrong mode parameter for set_led()\n",
DRIVER_NAME);
mutex_unlock(&the_tps->lock);
return -EINVAL;
}
status = i2c_smbus_write_byte_data(the_tps->client,
TPS_LED1_ON + offs, led_on);
if (status != 0) {
printk(KERN_ERR "%s: Failed to write led%i_on register\n",
DRIVER_NAME, led);
mutex_unlock(&the_tps->lock);
return status;
}
pr_debug("%s: led%i_on 0x%02x\n", DRIVER_NAME, led,
i2c_smbus_read_byte_data(the_tps->client, TPS_LED1_ON + offs));
status = i2c_smbus_write_byte_data(the_tps->client,
TPS_LED1_PER + offs, led_per);
if (status != 0) {
printk(KERN_ERR "%s: Failed to write led%i_per register\n",
DRIVER_NAME, led);
mutex_unlock(&the_tps->lock);
return status;
}
pr_debug("%s: led%i_per 0x%02x\n", DRIVER_NAME, led,
i2c_smbus_read_byte_data(the_tps->client,
TPS_LED1_PER + offs));
mutex_unlock(&the_tps->lock);
return status;
}
EXPORT_SYMBOL(tps65010_set_led);
/*-------------------------------------------------------------------------*/
/* tps65010_set_vib parameter:
* value: ON or OFF
*/
int tps65010_set_vib(unsigned value)
{
int status;
unsigned vdcdc2;
if (!the_tps)
return -ENODEV;
mutex_lock(&the_tps->lock);
vdcdc2 = i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC2);
vdcdc2 &= ~(1 << 1);
if (value)
vdcdc2 |= (1 << 1);
status = i2c_smbus_write_byte_data(the_tps->client,
TPS_VDCDC2, vdcdc2);
pr_debug("%s: vibrator %s\n", DRIVER_NAME, value ? "on" : "off");
mutex_unlock(&the_tps->lock);
return status;
}
EXPORT_SYMBOL(tps65010_set_vib);
/*-------------------------------------------------------------------------*/
/* tps65010_set_low_pwr parameter:
* mode: ON or OFF
*/
int tps65010_set_low_pwr(unsigned mode)
{
int status;
unsigned vdcdc1;
if (!the_tps)
return -ENODEV;
mutex_lock(&the_tps->lock);
pr_debug("%s: %s low_pwr, vdcdc1 0x%02x\n", DRIVER_NAME,
mode ? "enable" : "disable",
i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1));
vdcdc1 = i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1);
switch (mode) {
case OFF:
vdcdc1 &= ~TPS_ENABLE_LP; /* disable ENABLE_LP bit */
break;
/* case ON: */
default:
vdcdc1 |= TPS_ENABLE_LP; /* enable ENABLE_LP bit */
break;
}
status = i2c_smbus_write_byte_data(the_tps->client,
TPS_VDCDC1, vdcdc1);
if (status != 0)
printk(KERN_ERR "%s: Failed to write vdcdc1 register\n",
DRIVER_NAME);
else
pr_debug("%s: vdcdc1 0x%02x\n", DRIVER_NAME,
i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1));
mutex_unlock(&the_tps->lock);
return status;
}
EXPORT_SYMBOL(tps65010_set_low_pwr);
/*-------------------------------------------------------------------------*/
/* tps65010_config_vregs1 parameter:
* value to be written to VREGS1 register
* Note: The complete register is written, set all bits you need
*/
int tps65010_config_vregs1(unsigned value)
{
int status;
if (!the_tps)
return -ENODEV;
mutex_lock(&the_tps->lock);
pr_debug("%s: vregs1 0x%02x\n", DRIVER_NAME,
i2c_smbus_read_byte_data(the_tps->client, TPS_VREGS1));
status = i2c_smbus_write_byte_data(the_tps->client,
TPS_VREGS1, value);
if (status != 0)
printk(KERN_ERR "%s: Failed to write vregs1 register\n",
DRIVER_NAME);
else
pr_debug("%s: vregs1 0x%02x\n", DRIVER_NAME,
i2c_smbus_read_byte_data(the_tps->client, TPS_VREGS1));
mutex_unlock(&the_tps->lock);
return status;
}
EXPORT_SYMBOL(tps65010_config_vregs1);
int tps65010_config_vdcdc2(unsigned value)
{
struct i2c_client *c;
int status;
if (!the_tps)
return -ENODEV;
c = the_tps->client;
mutex_lock(&the_tps->lock);
pr_debug("%s: vdcdc2 0x%02x\n", DRIVER_NAME,
i2c_smbus_read_byte_data(c, TPS_VDCDC2));
status = i2c_smbus_write_byte_data(c, TPS_VDCDC2, value);
if (status != 0)
printk(KERN_ERR "%s: Failed to write vdcdc2 register\n",
DRIVER_NAME);
else
pr_debug("%s: vregs1 0x%02x\n", DRIVER_NAME,
i2c_smbus_read_byte_data(c, TPS_VDCDC2));
mutex_unlock(&the_tps->lock);
return status;
}
EXPORT_SYMBOL(tps65010_config_vdcdc2);
/*-------------------------------------------------------------------------*/
/* tps65013_set_low_pwr parameter:
* mode: ON or OFF
*/
/* FIXME: Assumes AC or USB power is present. Setting AUA bit is not
required if power supply is through a battery */
int tps65013_set_low_pwr(unsigned mode)
{
int status;
unsigned vdcdc1, chgconfig;
if (!the_tps || the_tps->por)
return -ENODEV;
mutex_lock(&the_tps->lock);
pr_debug("%s: %s low_pwr, chgconfig 0x%02x vdcdc1 0x%02x\n",
DRIVER_NAME,
mode ? "enable" : "disable",
i2c_smbus_read_byte_data(the_tps->client, TPS_CHGCONFIG),
i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1));
chgconfig = i2c_smbus_read_byte_data(the_tps->client, TPS_CHGCONFIG);
vdcdc1 = i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1);
switch (mode) {
case OFF:
chgconfig &= ~TPS65013_AUA; /* disable AUA bit */
vdcdc1 &= ~TPS_ENABLE_LP; /* disable ENABLE_LP bit */
break;
/* case ON: */
default:
chgconfig |= TPS65013_AUA; /* enable AUA bit */
vdcdc1 |= TPS_ENABLE_LP; /* enable ENABLE_LP bit */
break;
}
status = i2c_smbus_write_byte_data(the_tps->client,
TPS_CHGCONFIG, chgconfig);
if (status != 0) {
printk(KERN_ERR "%s: Failed to write chconfig register\n",
DRIVER_NAME);
mutex_unlock(&the_tps->lock);
return status;
}
chgconfig = i2c_smbus_read_byte_data(the_tps->client, TPS_CHGCONFIG);
the_tps->chgconf = chgconfig;
show_chgconfig(0, "chgconf", chgconfig);
status = i2c_smbus_write_byte_data(the_tps->client,
TPS_VDCDC1, vdcdc1);
if (status != 0)
printk(KERN_ERR "%s: Failed to write vdcdc1 register\n",
DRIVER_NAME);
else
pr_debug("%s: vdcdc1 0x%02x\n", DRIVER_NAME,
i2c_smbus_read_byte_data(the_tps->client, TPS_VDCDC1));
mutex_unlock(&the_tps->lock);
return status;
}
EXPORT_SYMBOL(tps65013_set_low_pwr);
/*-------------------------------------------------------------------------*/
static int __init tps_init(void)
{
return i2c_add_driver(&tps65010_driver);
}
/* NOTE: this MUST be initialized before the other parts of the system
* that rely on it ... but after the i2c bus on which this relies.
* That is, much earlier than on PC-type systems, which don't often use
* I2C as a core system bus.
*/
subsys_initcall(tps_init);
static void __exit tps_exit(void)
{
i2c_del_driver(&tps65010_driver);
}
module_exit(tps_exit);
| linux-master | drivers/mfd/tps65010.c |
/*
* Retu/Tahvo MFD driver
*
* Copyright (C) 2004, 2005 Nokia Corporation
*
* Based on code written by Juha Yrjölä, David Weinehall and Mikko Ylinen.
* Rewritten by Aaro Koskinen.
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
* archive for more details.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/retu.h>
#include <linux/interrupt.h>
#include <linux/moduleparam.h>
/* Registers */
#define RETU_REG_ASICR 0x00 /* ASIC ID and revision */
#define RETU_REG_ASICR_VILMA (1 << 7) /* Bit indicating Vilma */
#define RETU_REG_IDR 0x01 /* Interrupt ID */
#define RETU_REG_IMR 0x02 /* Interrupt mask (Retu) */
#define TAHVO_REG_IMR 0x03 /* Interrupt mask (Tahvo) */
/* Interrupt sources */
#define RETU_INT_PWR 0 /* Power button */
struct retu_dev {
struct regmap *regmap;
struct device *dev;
struct mutex mutex;
struct regmap_irq_chip_data *irq_data;
};
static const struct resource retu_pwrbutton_res[] = {
{
.name = "retu-pwrbutton",
.start = RETU_INT_PWR,
.end = RETU_INT_PWR,
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell retu_devs[] = {
{
.name = "retu-wdt"
},
{
.name = "retu-pwrbutton",
.resources = retu_pwrbutton_res,
.num_resources = ARRAY_SIZE(retu_pwrbutton_res),
}
};
static struct regmap_irq retu_irqs[] = {
[RETU_INT_PWR] = {
.mask = 1 << RETU_INT_PWR,
}
};
static struct regmap_irq_chip retu_irq_chip = {
.name = "RETU",
.irqs = retu_irqs,
.num_irqs = ARRAY_SIZE(retu_irqs),
.num_regs = 1,
.status_base = RETU_REG_IDR,
.mask_base = RETU_REG_IMR,
.ack_base = RETU_REG_IDR,
};
/* Retu device registered for the power off. */
static struct retu_dev *retu_pm_power_off;
static const struct resource tahvo_usb_res[] = {
{
.name = "tahvo-usb",
.start = TAHVO_INT_VBUS,
.end = TAHVO_INT_VBUS,
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell tahvo_devs[] = {
{
.name = "tahvo-usb",
.resources = tahvo_usb_res,
.num_resources = ARRAY_SIZE(tahvo_usb_res),
},
};
static struct regmap_irq tahvo_irqs[] = {
[TAHVO_INT_VBUS] = {
.mask = 1 << TAHVO_INT_VBUS,
}
};
static struct regmap_irq_chip tahvo_irq_chip = {
.name = "TAHVO",
.irqs = tahvo_irqs,
.num_irqs = ARRAY_SIZE(tahvo_irqs),
.num_regs = 1,
.status_base = RETU_REG_IDR,
.mask_base = TAHVO_REG_IMR,
.ack_base = RETU_REG_IDR,
};
static const struct retu_data {
char *chip_name;
char *companion_name;
struct regmap_irq_chip *irq_chip;
const struct mfd_cell *children;
int nchildren;
} retu_data[] = {
[0] = {
.chip_name = "Retu",
.companion_name = "Vilma",
.irq_chip = &retu_irq_chip,
.children = retu_devs,
.nchildren = ARRAY_SIZE(retu_devs),
},
[1] = {
.chip_name = "Tahvo",
.companion_name = "Betty",
.irq_chip = &tahvo_irq_chip,
.children = tahvo_devs,
.nchildren = ARRAY_SIZE(tahvo_devs),
}
};
int retu_read(struct retu_dev *rdev, u8 reg)
{
int ret;
int value;
mutex_lock(&rdev->mutex);
ret = regmap_read(rdev->regmap, reg, &value);
mutex_unlock(&rdev->mutex);
return ret ? ret : value;
}
EXPORT_SYMBOL_GPL(retu_read);
int retu_write(struct retu_dev *rdev, u8 reg, u16 data)
{
int ret;
mutex_lock(&rdev->mutex);
ret = regmap_write(rdev->regmap, reg, data);
mutex_unlock(&rdev->mutex);
return ret;
}
EXPORT_SYMBOL_GPL(retu_write);
static void retu_power_off(void)
{
struct retu_dev *rdev = retu_pm_power_off;
int reg;
mutex_lock(&retu_pm_power_off->mutex);
/* Ignore power button state */
regmap_read(rdev->regmap, RETU_REG_CC1, ®);
regmap_write(rdev->regmap, RETU_REG_CC1, reg | 2);
/* Expire watchdog immediately */
regmap_write(rdev->regmap, RETU_REG_WATCHDOG, 0);
/* Wait for poweroff */
for (;;)
cpu_relax();
mutex_unlock(&retu_pm_power_off->mutex);
}
static int retu_regmap_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
int ret;
struct device *dev = context;
struct i2c_client *i2c = to_i2c_client(dev);
BUG_ON(reg_size != 1 || val_size != 2);
ret = i2c_smbus_read_word_data(i2c, *(u8 const *)reg);
if (ret < 0)
return ret;
*(u16 *)val = ret;
return 0;
}
static int retu_regmap_write(void *context, const void *data, size_t count)
{
u8 reg;
u16 val;
struct device *dev = context;
struct i2c_client *i2c = to_i2c_client(dev);
BUG_ON(count != sizeof(reg) + sizeof(val));
memcpy(®, data, sizeof(reg));
memcpy(&val, data + sizeof(reg), sizeof(val));
return i2c_smbus_write_word_data(i2c, reg, val);
}
static struct regmap_bus retu_bus = {
.read = retu_regmap_read,
.write = retu_regmap_write,
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
};
static const struct regmap_config retu_config = {
.reg_bits = 8,
.val_bits = 16,
};
static int retu_probe(struct i2c_client *i2c)
{
struct retu_data const *rdat;
struct retu_dev *rdev;
int ret;
if (i2c->addr > ARRAY_SIZE(retu_data))
return -ENODEV;
rdat = &retu_data[i2c->addr - 1];
rdev = devm_kzalloc(&i2c->dev, sizeof(*rdev), GFP_KERNEL);
if (rdev == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rdev);
rdev->dev = &i2c->dev;
mutex_init(&rdev->mutex);
rdev->regmap = devm_regmap_init(&i2c->dev, &retu_bus, &i2c->dev,
&retu_config);
if (IS_ERR(rdev->regmap))
return PTR_ERR(rdev->regmap);
ret = retu_read(rdev, RETU_REG_ASICR);
if (ret < 0) {
dev_err(rdev->dev, "could not read %s revision: %d\n",
rdat->chip_name, ret);
return ret;
}
dev_info(rdev->dev, "%s%s%s v%d.%d found\n", rdat->chip_name,
(ret & RETU_REG_ASICR_VILMA) ? " & " : "",
(ret & RETU_REG_ASICR_VILMA) ? rdat->companion_name : "",
(ret >> 4) & 0x7, ret & 0xf);
/* Mask all interrupts. */
ret = retu_write(rdev, rdat->irq_chip->mask_base, 0xffff);
if (ret < 0)
return ret;
ret = regmap_add_irq_chip(rdev->regmap, i2c->irq, IRQF_ONESHOT, -1,
rdat->irq_chip, &rdev->irq_data);
if (ret < 0)
return ret;
ret = mfd_add_devices(rdev->dev, -1, rdat->children, rdat->nchildren,
NULL, regmap_irq_chip_get_base(rdev->irq_data),
NULL);
if (ret < 0) {
regmap_del_irq_chip(i2c->irq, rdev->irq_data);
return ret;
}
if (i2c->addr == 1 && !pm_power_off) {
retu_pm_power_off = rdev;
pm_power_off = retu_power_off;
}
return 0;
}
static void retu_remove(struct i2c_client *i2c)
{
struct retu_dev *rdev = i2c_get_clientdata(i2c);
if (retu_pm_power_off == rdev) {
pm_power_off = NULL;
retu_pm_power_off = NULL;
}
mfd_remove_devices(rdev->dev);
regmap_del_irq_chip(i2c->irq, rdev->irq_data);
}
static const struct i2c_device_id retu_id[] = {
{ "retu", 0 },
{ "tahvo", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, retu_id);
static const struct of_device_id retu_of_match[] = {
{ .compatible = "nokia,retu" },
{ .compatible = "nokia,tahvo" },
{ }
};
MODULE_DEVICE_TABLE(of, retu_of_match);
static struct i2c_driver retu_driver = {
.driver = {
.name = "retu-mfd",
.of_match_table = retu_of_match,
},
.probe = retu_probe,
.remove = retu_remove,
.id_table = retu_id,
};
module_i2c_driver(retu_driver);
MODULE_DESCRIPTION("Retu MFD driver");
MODULE_AUTHOR("Juha Yrjölä");
MODULE_AUTHOR("David Weinehall");
MODULE_AUTHOR("Mikko Ylinen");
MODULE_AUTHOR("Aaro Koskinen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/retu-mfd.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Flora Fu, MediaTek
*/
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6331/core.h>
#include <linux/mfd/mt6357/core.h>
#include <linux/mfd/mt6358/core.h>
#include <linux/mfd/mt6359/core.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6331/registers.h>
#include <linux/mfd/mt6357/registers.h>
#include <linux/mfd/mt6358/registers.h>
#include <linux/mfd/mt6359/registers.h>
#include <linux/mfd/mt6397/registers.h>
#define MT6323_RTC_BASE 0x8000
#define MT6323_RTC_SIZE 0x40
#define MT6357_RTC_BASE 0x0588
#define MT6357_RTC_SIZE 0x3c
#define MT6331_RTC_BASE 0x4000
#define MT6331_RTC_SIZE 0x40
#define MT6358_RTC_BASE 0x0588
#define MT6358_RTC_SIZE 0x3c
#define MT6397_RTC_BASE 0xe000
#define MT6397_RTC_SIZE 0x3e
#define MT6323_PWRC_BASE 0x8000
#define MT6323_PWRC_SIZE 0x40
static const struct resource mt6323_rtc_resources[] = {
DEFINE_RES_MEM(MT6323_RTC_BASE, MT6323_RTC_SIZE),
DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC),
};
static const struct resource mt6357_rtc_resources[] = {
DEFINE_RES_MEM(MT6357_RTC_BASE, MT6357_RTC_SIZE),
DEFINE_RES_IRQ(MT6357_IRQ_RTC),
};
static const struct resource mt6331_rtc_resources[] = {
DEFINE_RES_MEM(MT6331_RTC_BASE, MT6331_RTC_SIZE),
DEFINE_RES_IRQ(MT6331_IRQ_STATUS_RTC),
};
static const struct resource mt6358_rtc_resources[] = {
DEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE),
DEFINE_RES_IRQ(MT6358_IRQ_RTC),
};
static const struct resource mt6397_rtc_resources[] = {
DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
DEFINE_RES_IRQ(MT6397_IRQ_RTC),
};
static const struct resource mt6358_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6358_IRQ_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6358_IRQ_HOMEKEY, "homekey"),
DEFINE_RES_IRQ_NAMED(MT6358_IRQ_PWRKEY_R, "powerkey_r"),
DEFINE_RES_IRQ_NAMED(MT6358_IRQ_HOMEKEY_R, "homekey_r"),
};
static const struct resource mt6359_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6359_IRQ_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6359_IRQ_HOMEKEY, "homekey"),
DEFINE_RES_IRQ_NAMED(MT6359_IRQ_PWRKEY_R, "powerkey_r"),
DEFINE_RES_IRQ_NAMED(MT6359_IRQ_HOMEKEY_R, "homekey_r"),
};
static const struct resource mt6323_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_FCHRKEY, "homekey"),
};
static const struct resource mt6357_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY, "homekey"),
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY_R, "powerkey_r"),
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY_R, "homekey_r"),
};
static const struct resource mt6331_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_HOMEKEY, "homekey"),
};
static const struct resource mt6397_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, "homekey"),
};
static const struct resource mt6323_pwrc_resources[] = {
DEFINE_RES_MEM(MT6323_PWRC_BASE, MT6323_PWRC_SIZE),
};
static const struct mfd_cell mt6323_devs[] = {
{
.name = "mt6323-rtc",
.num_resources = ARRAY_SIZE(mt6323_rtc_resources),
.resources = mt6323_rtc_resources,
.of_compatible = "mediatek,mt6323-rtc",
}, {
.name = "mt6323-regulator",
.of_compatible = "mediatek,mt6323-regulator"
}, {
.name = "mt6323-led",
.of_compatible = "mediatek,mt6323-led"
}, {
.name = "mtk-pmic-keys",
.num_resources = ARRAY_SIZE(mt6323_keys_resources),
.resources = mt6323_keys_resources,
.of_compatible = "mediatek,mt6323-keys"
}, {
.name = "mt6323-pwrc",
.num_resources = ARRAY_SIZE(mt6323_pwrc_resources),
.resources = mt6323_pwrc_resources,
.of_compatible = "mediatek,mt6323-pwrc"
},
};
static const struct mfd_cell mt6357_devs[] = {
{
.name = "mt6357-regulator",
}, {
.name = "mt6357-rtc",
.num_resources = ARRAY_SIZE(mt6357_rtc_resources),
.resources = mt6357_rtc_resources,
.of_compatible = "mediatek,mt6357-rtc",
}, {
.name = "mtk-pmic-keys",
.num_resources = ARRAY_SIZE(mt6357_keys_resources),
.resources = mt6357_keys_resources,
.of_compatible = "mediatek,mt6357-keys"
},
};
/* MT6331 is always used in combination with MT6332 */
static const struct mfd_cell mt6331_mt6332_devs[] = {
{
.name = "mt6331-rtc",
.num_resources = ARRAY_SIZE(mt6331_rtc_resources),
.resources = mt6331_rtc_resources,
.of_compatible = "mediatek,mt6331-rtc",
}, {
.name = "mt6331-regulator",
.of_compatible = "mediatek,mt6331-regulator"
}, {
.name = "mt6332-regulator",
.of_compatible = "mediatek,mt6332-regulator"
}, {
.name = "mtk-pmic-keys",
.num_resources = ARRAY_SIZE(mt6331_keys_resources),
.resources = mt6331_keys_resources,
.of_compatible = "mediatek,mt6331-keys"
},
};
static const struct mfd_cell mt6358_devs[] = {
{
.name = "mt6358-regulator",
.of_compatible = "mediatek,mt6358-regulator"
}, {
.name = "mt6358-rtc",
.num_resources = ARRAY_SIZE(mt6358_rtc_resources),
.resources = mt6358_rtc_resources,
.of_compatible = "mediatek,mt6358-rtc",
}, {
.name = "mt6358-sound",
.of_compatible = "mediatek,mt6358-sound"
}, {
.name = "mt6358-keys",
.num_resources = ARRAY_SIZE(mt6358_keys_resources),
.resources = mt6358_keys_resources,
.of_compatible = "mediatek,mt6358-keys"
},
};
static const struct mfd_cell mt6359_devs[] = {
{ .name = "mt6359-regulator", },
{
.name = "mt6359-rtc",
.num_resources = ARRAY_SIZE(mt6358_rtc_resources),
.resources = mt6358_rtc_resources,
.of_compatible = "mediatek,mt6358-rtc",
},
{ .name = "mt6359-sound", },
{
.name = "mtk-pmic-keys",
.num_resources = ARRAY_SIZE(mt6359_keys_resources),
.resources = mt6359_keys_resources,
.of_compatible = "mediatek,mt6359-keys"
},
};
static const struct mfd_cell mt6397_devs[] = {
{
.name = "mt6397-rtc",
.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
.resources = mt6397_rtc_resources,
.of_compatible = "mediatek,mt6397-rtc",
}, {
.name = "mt6397-regulator",
.of_compatible = "mediatek,mt6397-regulator",
}, {
.name = "mt6397-codec",
.of_compatible = "mediatek,mt6397-codec",
}, {
.name = "mt6397-clk",
.of_compatible = "mediatek,mt6397-clk",
}, {
.name = "mt6397-pinctrl",
.of_compatible = "mediatek,mt6397-pinctrl",
}, {
.name = "mtk-pmic-keys",
.num_resources = ARRAY_SIZE(mt6397_keys_resources),
.resources = mt6397_keys_resources,
.of_compatible = "mediatek,mt6397-keys"
}
};
struct chip_data {
u32 cid_addr;
u32 cid_shift;
const struct mfd_cell *cells;
int cell_size;
int (*irq_init)(struct mt6397_chip *chip);
};
static const struct chip_data mt6323_core = {
.cid_addr = MT6323_CID,
.cid_shift = 0,
.cells = mt6323_devs,
.cell_size = ARRAY_SIZE(mt6323_devs),
.irq_init = mt6397_irq_init,
};
static const struct chip_data mt6357_core = {
.cid_addr = MT6357_SWCID,
.cid_shift = 8,
.cells = mt6357_devs,
.cell_size = ARRAY_SIZE(mt6357_devs),
.irq_init = mt6358_irq_init,
};
static const struct chip_data mt6331_mt6332_core = {
.cid_addr = MT6331_HWCID,
.cid_shift = 0,
.cells = mt6331_mt6332_devs,
.cell_size = ARRAY_SIZE(mt6331_mt6332_devs),
.irq_init = mt6397_irq_init,
};
static const struct chip_data mt6358_core = {
.cid_addr = MT6358_SWCID,
.cid_shift = 8,
.cells = mt6358_devs,
.cell_size = ARRAY_SIZE(mt6358_devs),
.irq_init = mt6358_irq_init,
};
static const struct chip_data mt6359_core = {
.cid_addr = MT6359_SWCID,
.cid_shift = 8,
.cells = mt6359_devs,
.cell_size = ARRAY_SIZE(mt6359_devs),
.irq_init = mt6358_irq_init,
};
static const struct chip_data mt6397_core = {
.cid_addr = MT6397_CID,
.cid_shift = 0,
.cells = mt6397_devs,
.cell_size = ARRAY_SIZE(mt6397_devs),
.irq_init = mt6397_irq_init,
};
static int mt6397_probe(struct platform_device *pdev)
{
int ret;
unsigned int id = 0;
struct mt6397_chip *pmic;
const struct chip_data *pmic_core;
pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
pmic->dev = &pdev->dev;
/*
* mt6397 MFD is child device of soc pmic wrapper.
* Regmap is set from its parent.
*/
pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!pmic->regmap)
return -ENODEV;
pmic_core = of_device_get_match_data(&pdev->dev);
if (!pmic_core)
return -ENODEV;
ret = regmap_read(pmic->regmap, pmic_core->cid_addr, &id);
if (ret) {
dev_err(&pdev->dev, "Failed to read chip id: %d\n", ret);
return ret;
}
pmic->chip_id = (id >> pmic_core->cid_shift) & 0xff;
platform_set_drvdata(pdev, pmic);
pmic->irq = platform_get_irq(pdev, 0);
if (pmic->irq <= 0)
return pmic->irq;
ret = pmic_core->irq_init(pmic);
if (ret)
return ret;
ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
pmic_core->cells, pmic_core->cell_size,
NULL, 0, pmic->irq_domain);
if (ret) {
irq_domain_remove(pmic->irq_domain);
dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
}
return ret;
}
static const struct of_device_id mt6397_of_match[] = {
{
.compatible = "mediatek,mt6323",
.data = &mt6323_core,
}, {
.compatible = "mediatek,mt6331",
.data = &mt6331_mt6332_core,
}, {
.compatible = "mediatek,mt6357",
.data = &mt6357_core,
}, {
.compatible = "mediatek,mt6358",
.data = &mt6358_core,
}, {
.compatible = "mediatek,mt6359",
.data = &mt6359_core,
}, {
.compatible = "mediatek,mt6397",
.data = &mt6397_core,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, mt6397_of_match);
static const struct platform_device_id mt6397_id[] = {
{ "mt6397", 0 },
{ },
};
MODULE_DEVICE_TABLE(platform, mt6397_id);
static struct platform_driver mt6397_driver = {
.probe = mt6397_probe,
.driver = {
.name = "mt6397",
.of_match_table = mt6397_of_match,
},
.id_table = mt6397_id,
};
module_platform_driver(mt6397_driver);
MODULE_AUTHOR("Flora Fu, MediaTek");
MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/mt6397-core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SPI access driver for TI TPS6594/TPS6593/LP8764 PMICs
*
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
*/
#include <linux/crc8.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/mfd/tps6594.h>
#define TPS6594_SPI_PAGE_SHIFT 5
#define TPS6594_SPI_READ_BIT BIT(4)
static bool enable_crc;
module_param(enable_crc, bool, 0444);
MODULE_PARM_DESC(enable_crc, "Enable CRC feature for SPI interface");
DECLARE_CRC8_TABLE(tps6594_spi_crc_table);
static int tps6594_spi_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct spi_device *spi = context;
struct tps6594 *tps = spi_get_drvdata(spi);
u8 buf[4] = { 0 };
size_t count_rx = 1;
int ret;
buf[0] = reg;
buf[1] = TPS6594_REG_TO_PAGE(reg) << TPS6594_SPI_PAGE_SHIFT | TPS6594_SPI_READ_BIT;
if (tps->use_crc)
count_rx++;
ret = spi_write_then_read(spi, buf, 2, buf + 2, count_rx);
if (ret < 0)
return ret;
if (tps->use_crc && buf[3] != crc8(tps6594_spi_crc_table, buf, 3, CRC8_INIT_VALUE))
return -EIO;
*val = buf[2];
return 0;
}
static int tps6594_spi_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct spi_device *spi = context;
struct tps6594 *tps = spi_get_drvdata(spi);
u8 buf[4] = { 0 };
size_t count = 3;
buf[0] = reg;
buf[1] = TPS6594_REG_TO_PAGE(reg) << TPS6594_SPI_PAGE_SHIFT;
buf[2] = val;
if (tps->use_crc)
buf[3] = crc8(tps6594_spi_crc_table, buf, count++, CRC8_INIT_VALUE);
return spi_write(spi, buf, count);
}
static const struct regmap_config tps6594_spi_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = TPS6594_REG_DWD_FAIL_CNT_REG,
.volatile_reg = tps6594_is_volatile_reg,
.reg_read = tps6594_spi_reg_read,
.reg_write = tps6594_spi_reg_write,
.use_single_read = true,
.use_single_write = true,
};
static const struct of_device_id tps6594_spi_of_match_table[] = {
{ .compatible = "ti,tps6594-q1", .data = (void *)TPS6594, },
{ .compatible = "ti,tps6593-q1", .data = (void *)TPS6593, },
{ .compatible = "ti,lp8764-q1", .data = (void *)LP8764, },
{}
};
MODULE_DEVICE_TABLE(of, tps6594_spi_of_match_table);
static int tps6594_spi_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct tps6594 *tps;
const struct of_device_id *match;
tps = devm_kzalloc(dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
spi_set_drvdata(spi, tps);
tps->dev = dev;
tps->reg = spi->chip_select;
tps->irq = spi->irq;
tps->regmap = devm_regmap_init(dev, NULL, spi, &tps6594_spi_regmap_config);
if (IS_ERR(tps->regmap))
return dev_err_probe(dev, PTR_ERR(tps->regmap), "Failed to init regmap\n");
match = of_match_device(tps6594_spi_of_match_table, dev);
if (!match)
return dev_err_probe(dev, -EINVAL, "Failed to find matching chip ID\n");
tps->chip_id = (unsigned long)match->data;
crc8_populate_msb(tps6594_spi_crc_table, TPS6594_CRC8_POLYNOMIAL);
return tps6594_device_init(tps, enable_crc);
}
static struct spi_driver tps6594_spi_driver = {
.driver = {
.name = "tps6594",
.of_match_table = tps6594_spi_of_match_table,
},
.probe = tps6594_spi_probe,
};
module_spi_driver(tps6594_spi_driver);
MODULE_AUTHOR("Julien Panis <[email protected]>");
MODULE_DESCRIPTION("TPS6594 SPI Interface Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/tps6594-spi.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
// http://www.samsung.com
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/mfd/samsung/core.h>
#include <linux/mfd/samsung/irq.h>
#include <linux/mfd/samsung/s2mps11.h>
#include <linux/mfd/samsung/s2mps14.h>
#include <linux/mfd/samsung/s2mpu02.h>
#include <linux/mfd/samsung/s5m8767.h>
static const struct regmap_irq s2mps11_irqs[] = {
[S2MPS11_IRQ_PWRONF] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_PWRONF_MASK,
},
[S2MPS11_IRQ_PWRONR] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_PWRONR_MASK,
},
[S2MPS11_IRQ_JIGONBF] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_JIGONBF_MASK,
},
[S2MPS11_IRQ_JIGONBR] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_JIGONBR_MASK,
},
[S2MPS11_IRQ_ACOKBF] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_ACOKBF_MASK,
},
[S2MPS11_IRQ_ACOKBR] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_ACOKBR_MASK,
},
[S2MPS11_IRQ_PWRON1S] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_PWRON1S_MASK,
},
[S2MPS11_IRQ_MRB] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_MRB_MASK,
},
[S2MPS11_IRQ_RTC60S] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTC60S_MASK,
},
[S2MPS11_IRQ_RTCA1] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA1_MASK,
},
[S2MPS11_IRQ_RTCA0] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA0_MASK,
},
[S2MPS11_IRQ_SMPL] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_SMPL_MASK,
},
[S2MPS11_IRQ_RTC1S] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTC1S_MASK,
},
[S2MPS11_IRQ_WTSR] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_WTSR_MASK,
},
[S2MPS11_IRQ_INT120C] = {
.reg_offset = 2,
.mask = S2MPS11_IRQ_INT120C_MASK,
},
[S2MPS11_IRQ_INT140C] = {
.reg_offset = 2,
.mask = S2MPS11_IRQ_INT140C_MASK,
},
};
static const struct regmap_irq s2mps14_irqs[] = {
[S2MPS14_IRQ_PWRONF] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_PWRONF_MASK,
},
[S2MPS14_IRQ_PWRONR] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_PWRONR_MASK,
},
[S2MPS14_IRQ_JIGONBF] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_JIGONBF_MASK,
},
[S2MPS14_IRQ_JIGONBR] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_JIGONBR_MASK,
},
[S2MPS14_IRQ_ACOKBF] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_ACOKBF_MASK,
},
[S2MPS14_IRQ_ACOKBR] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_ACOKBR_MASK,
},
[S2MPS14_IRQ_PWRON1S] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_PWRON1S_MASK,
},
[S2MPS14_IRQ_MRB] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_MRB_MASK,
},
[S2MPS14_IRQ_RTC60S] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTC60S_MASK,
},
[S2MPS14_IRQ_RTCA1] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA1_MASK,
},
[S2MPS14_IRQ_RTCA0] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA0_MASK,
},
[S2MPS14_IRQ_SMPL] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_SMPL_MASK,
},
[S2MPS14_IRQ_RTC1S] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTC1S_MASK,
},
[S2MPS14_IRQ_WTSR] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_WTSR_MASK,
},
[S2MPS14_IRQ_INT120C] = {
.reg_offset = 2,
.mask = S2MPS11_IRQ_INT120C_MASK,
},
[S2MPS14_IRQ_INT140C] = {
.reg_offset = 2,
.mask = S2MPS11_IRQ_INT140C_MASK,
},
[S2MPS14_IRQ_TSD] = {
.reg_offset = 2,
.mask = S2MPS14_IRQ_TSD_MASK,
},
};
static const struct regmap_irq s2mpu02_irqs[] = {
[S2MPU02_IRQ_PWRONF] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_PWRONF_MASK,
},
[S2MPU02_IRQ_PWRONR] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_PWRONR_MASK,
},
[S2MPU02_IRQ_JIGONBF] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_JIGONBF_MASK,
},
[S2MPU02_IRQ_JIGONBR] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_JIGONBR_MASK,
},
[S2MPU02_IRQ_ACOKBF] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_ACOKBF_MASK,
},
[S2MPU02_IRQ_ACOKBR] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_ACOKBR_MASK,
},
[S2MPU02_IRQ_PWRON1S] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_PWRON1S_MASK,
},
[S2MPU02_IRQ_MRB] = {
.reg_offset = 0,
.mask = S2MPS11_IRQ_MRB_MASK,
},
[S2MPU02_IRQ_RTC60S] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTC60S_MASK,
},
[S2MPU02_IRQ_RTCA1] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA1_MASK,
},
[S2MPU02_IRQ_RTCA0] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA0_MASK,
},
[S2MPU02_IRQ_SMPL] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_SMPL_MASK,
},
[S2MPU02_IRQ_RTC1S] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTC1S_MASK,
},
[S2MPU02_IRQ_WTSR] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_WTSR_MASK,
},
[S2MPU02_IRQ_INT120C] = {
.reg_offset = 2,
.mask = S2MPS11_IRQ_INT120C_MASK,
},
[S2MPU02_IRQ_INT140C] = {
.reg_offset = 2,
.mask = S2MPS11_IRQ_INT140C_MASK,
},
[S2MPU02_IRQ_TSD] = {
.reg_offset = 2,
.mask = S2MPS14_IRQ_TSD_MASK,
},
};
static const struct regmap_irq s5m8767_irqs[] = {
[S5M8767_IRQ_PWRR] = {
.reg_offset = 0,
.mask = S5M8767_IRQ_PWRR_MASK,
},
[S5M8767_IRQ_PWRF] = {
.reg_offset = 0,
.mask = S5M8767_IRQ_PWRF_MASK,
},
[S5M8767_IRQ_PWR1S] = {
.reg_offset = 0,
.mask = S5M8767_IRQ_PWR1S_MASK,
},
[S5M8767_IRQ_JIGR] = {
.reg_offset = 0,
.mask = S5M8767_IRQ_JIGR_MASK,
},
[S5M8767_IRQ_JIGF] = {
.reg_offset = 0,
.mask = S5M8767_IRQ_JIGF_MASK,
},
[S5M8767_IRQ_LOWBAT2] = {
.reg_offset = 0,
.mask = S5M8767_IRQ_LOWBAT2_MASK,
},
[S5M8767_IRQ_LOWBAT1] = {
.reg_offset = 0,
.mask = S5M8767_IRQ_LOWBAT1_MASK,
},
[S5M8767_IRQ_MRB] = {
.reg_offset = 1,
.mask = S5M8767_IRQ_MRB_MASK,
},
[S5M8767_IRQ_DVSOK2] = {
.reg_offset = 1,
.mask = S5M8767_IRQ_DVSOK2_MASK,
},
[S5M8767_IRQ_DVSOK3] = {
.reg_offset = 1,
.mask = S5M8767_IRQ_DVSOK3_MASK,
},
[S5M8767_IRQ_DVSOK4] = {
.reg_offset = 1,
.mask = S5M8767_IRQ_DVSOK4_MASK,
},
[S5M8767_IRQ_RTC60S] = {
.reg_offset = 2,
.mask = S5M8767_IRQ_RTC60S_MASK,
},
[S5M8767_IRQ_RTCA1] = {
.reg_offset = 2,
.mask = S5M8767_IRQ_RTCA1_MASK,
},
[S5M8767_IRQ_RTCA2] = {
.reg_offset = 2,
.mask = S5M8767_IRQ_RTCA2_MASK,
},
[S5M8767_IRQ_SMPL] = {
.reg_offset = 2,
.mask = S5M8767_IRQ_SMPL_MASK,
},
[S5M8767_IRQ_RTC1S] = {
.reg_offset = 2,
.mask = S5M8767_IRQ_RTC1S_MASK,
},
[S5M8767_IRQ_WTSR] = {
.reg_offset = 2,
.mask = S5M8767_IRQ_WTSR_MASK,
},
};
static const struct regmap_irq_chip s2mps11_irq_chip = {
.name = "s2mps11",
.irqs = s2mps11_irqs,
.num_irqs = ARRAY_SIZE(s2mps11_irqs),
.num_regs = 3,
.status_base = S2MPS11_REG_INT1,
.mask_base = S2MPS11_REG_INT1M,
.ack_base = S2MPS11_REG_INT1,
};
#define S2MPS1X_IRQ_CHIP_COMMON_DATA \
.irqs = s2mps14_irqs, \
.num_irqs = ARRAY_SIZE(s2mps14_irqs), \
.num_regs = 3, \
.status_base = S2MPS14_REG_INT1, \
.mask_base = S2MPS14_REG_INT1M, \
.ack_base = S2MPS14_REG_INT1 \
static const struct regmap_irq_chip s2mps13_irq_chip = {
.name = "s2mps13",
S2MPS1X_IRQ_CHIP_COMMON_DATA,
};
static const struct regmap_irq_chip s2mps14_irq_chip = {
.name = "s2mps14",
S2MPS1X_IRQ_CHIP_COMMON_DATA,
};
static const struct regmap_irq_chip s2mps15_irq_chip = {
.name = "s2mps15",
S2MPS1X_IRQ_CHIP_COMMON_DATA,
};
static const struct regmap_irq_chip s2mpu02_irq_chip = {
.name = "s2mpu02",
.irqs = s2mpu02_irqs,
.num_irqs = ARRAY_SIZE(s2mpu02_irqs),
.num_regs = 3,
.status_base = S2MPU02_REG_INT1,
.mask_base = S2MPU02_REG_INT1M,
.ack_base = S2MPU02_REG_INT1,
};
static const struct regmap_irq_chip s5m8767_irq_chip = {
.name = "s5m8767",
.irqs = s5m8767_irqs,
.num_irqs = ARRAY_SIZE(s5m8767_irqs),
.num_regs = 3,
.status_base = S5M8767_REG_INT1,
.mask_base = S5M8767_REG_INT1M,
.ack_base = S5M8767_REG_INT1,
};
int sec_irq_init(struct sec_pmic_dev *sec_pmic)
{
int ret = 0;
int type = sec_pmic->device_type;
const struct regmap_irq_chip *sec_irq_chip;
if (!sec_pmic->irq) {
dev_warn(sec_pmic->dev,
"No interrupt specified, no interrupts\n");
return 0;
}
switch (type) {
case S5M8767X:
sec_irq_chip = &s5m8767_irq_chip;
break;
case S2MPA01:
sec_irq_chip = &s2mps14_irq_chip;
break;
case S2MPS11X:
sec_irq_chip = &s2mps11_irq_chip;
break;
case S2MPS13X:
sec_irq_chip = &s2mps13_irq_chip;
break;
case S2MPS14X:
sec_irq_chip = &s2mps14_irq_chip;
break;
case S2MPS15X:
sec_irq_chip = &s2mps15_irq_chip;
break;
case S2MPU02:
sec_irq_chip = &s2mpu02_irq_chip;
break;
default:
dev_err(sec_pmic->dev, "Unknown device type %lu\n",
sec_pmic->device_type);
return -EINVAL;
}
ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic,
sec_pmic->irq, IRQF_ONESHOT,
0, sec_irq_chip, &sec_pmic->irq_data);
if (ret != 0) {
dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
return ret;
}
/*
* The rtc-s5m driver requests S2MPS14_IRQ_RTCA0 also for S2MPS11
* so the interrupt number must be consistent.
*/
BUILD_BUG_ON(((enum s2mps14_irq)S2MPS11_IRQ_RTCA0) != S2MPS14_IRQ_RTCA0);
return 0;
}
EXPORT_SYMBOL_GPL(sec_irq_init);
MODULE_AUTHOR("Sangbeom Kim <[email protected]>");
MODULE_AUTHOR("Chanwoo Choi <[email protected]>");
MODULE_AUTHOR("Krzysztof Kozlowski <[email protected]>");
MODULE_DESCRIPTION("Interrupt support for the S5M MFD");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/sec-irq.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8350-core.c -- Device access for Wolfson WM8350
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/gpio.h>
#include <linux/mfd/wm8350/pmic.h>
static int gpio_set_dir(struct wm8350 *wm8350, int gpio, int dir)
{
int ret;
wm8350_reg_unlock(wm8350);
if (dir == WM8350_GPIO_DIR_OUT)
ret = wm8350_clear_bits(wm8350,
WM8350_GPIO_CONFIGURATION_I_O,
1 << gpio);
else
ret = wm8350_set_bits(wm8350,
WM8350_GPIO_CONFIGURATION_I_O,
1 << gpio);
wm8350_reg_lock(wm8350);
return ret;
}
static int wm8350_gpio_set_debounce(struct wm8350 *wm8350, int gpio, int db)
{
if (db == WM8350_GPIO_DEBOUNCE_ON)
return wm8350_set_bits(wm8350, WM8350_GPIO_DEBOUNCE,
1 << gpio);
else
return wm8350_clear_bits(wm8350,
WM8350_GPIO_DEBOUNCE, 1 << gpio);
}
static int gpio_set_func(struct wm8350 *wm8350, int gpio, int func)
{
u16 reg;
wm8350_reg_unlock(wm8350);
switch (gpio) {
case 0:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
& ~WM8350_GP0_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1,
reg | ((func & 0xf) << 0));
break;
case 1:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
& ~WM8350_GP1_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1,
reg | ((func & 0xf) << 4));
break;
case 2:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
& ~WM8350_GP2_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1,
reg | ((func & 0xf) << 8));
break;
case 3:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1)
& ~WM8350_GP3_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_1,
reg | ((func & 0xf) << 12));
break;
case 4:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2)
& ~WM8350_GP4_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2,
reg | ((func & 0xf) << 0));
break;
case 5:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2)
& ~WM8350_GP5_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2,
reg | ((func & 0xf) << 4));
break;
case 6:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2)
& ~WM8350_GP6_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2,
reg | ((func & 0xf) << 8));
break;
case 7:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2)
& ~WM8350_GP7_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_2,
reg | ((func & 0xf) << 12));
break;
case 8:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3)
& ~WM8350_GP8_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3,
reg | ((func & 0xf) << 0));
break;
case 9:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3)
& ~WM8350_GP9_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3,
reg | ((func & 0xf) << 4));
break;
case 10:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3)
& ~WM8350_GP10_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3,
reg | ((func & 0xf) << 8));
break;
case 11:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3)
& ~WM8350_GP11_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_3,
reg | ((func & 0xf) << 12));
break;
case 12:
reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_4)
& ~WM8350_GP12_FN_MASK;
wm8350_reg_write(wm8350, WM8350_GPIO_FUNCTION_SELECT_4,
reg | ((func & 0xf) << 0));
break;
default:
wm8350_reg_lock(wm8350);
return -EINVAL;
}
wm8350_reg_lock(wm8350);
return 0;
}
static int gpio_set_pull_up(struct wm8350 *wm8350, int gpio, int up)
{
if (up)
return wm8350_set_bits(wm8350,
WM8350_GPIO_PIN_PULL_UP_CONTROL,
1 << gpio);
else
return wm8350_clear_bits(wm8350,
WM8350_GPIO_PIN_PULL_UP_CONTROL,
1 << gpio);
}
static int gpio_set_pull_down(struct wm8350 *wm8350, int gpio, int down)
{
if (down)
return wm8350_set_bits(wm8350,
WM8350_GPIO_PULL_DOWN_CONTROL,
1 << gpio);
else
return wm8350_clear_bits(wm8350,
WM8350_GPIO_PULL_DOWN_CONTROL,
1 << gpio);
}
static int gpio_set_polarity(struct wm8350 *wm8350, int gpio, int pol)
{
if (pol == WM8350_GPIO_ACTIVE_HIGH)
return wm8350_set_bits(wm8350,
WM8350_GPIO_PIN_POLARITY_TYPE,
1 << gpio);
else
return wm8350_clear_bits(wm8350,
WM8350_GPIO_PIN_POLARITY_TYPE,
1 << gpio);
}
static int gpio_set_invert(struct wm8350 *wm8350, int gpio, int invert)
{
if (invert == WM8350_GPIO_INVERT_ON)
return wm8350_set_bits(wm8350, WM8350_GPIO_INT_MODE, 1 << gpio);
else
return wm8350_clear_bits(wm8350,
WM8350_GPIO_INT_MODE, 1 << gpio);
}
int wm8350_gpio_config(struct wm8350 *wm8350, int gpio, int dir, int func,
int pol, int pull, int invert, int debounce)
{
/* make sure we never pull up and down at the same time */
if (pull == WM8350_GPIO_PULL_NONE) {
if (gpio_set_pull_up(wm8350, gpio, 0))
goto err;
if (gpio_set_pull_down(wm8350, gpio, 0))
goto err;
} else if (pull == WM8350_GPIO_PULL_UP) {
if (gpio_set_pull_down(wm8350, gpio, 0))
goto err;
if (gpio_set_pull_up(wm8350, gpio, 1))
goto err;
} else if (pull == WM8350_GPIO_PULL_DOWN) {
if (gpio_set_pull_up(wm8350, gpio, 0))
goto err;
if (gpio_set_pull_down(wm8350, gpio, 1))
goto err;
}
if (gpio_set_invert(wm8350, gpio, invert))
goto err;
if (gpio_set_polarity(wm8350, gpio, pol))
goto err;
if (wm8350_gpio_set_debounce(wm8350, gpio, debounce))
goto err;
if (gpio_set_dir(wm8350, gpio, dir))
goto err;
return gpio_set_func(wm8350, gpio, func);
err:
return -EIO;
}
EXPORT_SYMBOL_GPL(wm8350_gpio_config);
| linux-master | drivers/mfd/wm8350-gpio.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/* I2C access for DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <[email protected]>
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/mfd/da9055/core.h>
static int da9055_i2c_probe(struct i2c_client *i2c)
{
struct da9055 *da9055;
int ret;
da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055), GFP_KERNEL);
if (!da9055)
return -ENOMEM;
da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);
if (IS_ERR(da9055->regmap)) {
ret = PTR_ERR(da9055->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
da9055->dev = &i2c->dev;
da9055->chip_irq = i2c->irq;
i2c_set_clientdata(i2c, da9055);
return da9055_device_init(da9055);
}
static void da9055_i2c_remove(struct i2c_client *i2c)
{
struct da9055 *da9055 = i2c_get_clientdata(i2c);
da9055_device_exit(da9055);
}
/*
* DO NOT change the device Ids. The naming is intentionally specific as both
* the PMIC and CODEC parts of this chip are instantiated separately as I2C
* devices (both have configurable I2C addresses, and are to all intents and
* purposes separate). As a result there are specific DA9055 ids for PMIC
* and CODEC, which must be different to operate together.
*/
static const struct i2c_device_id da9055_i2c_id[] = {
{"da9055-pmic", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, da9055_i2c_id);
static const struct of_device_id da9055_of_match[] = {
{ .compatible = "dlg,da9055-pmic", },
{ }
};
static struct i2c_driver da9055_i2c_driver = {
.probe = da9055_i2c_probe,
.remove = da9055_i2c_remove,
.id_table = da9055_i2c_id,
.driver = {
.name = "da9055-pmic",
.of_match_table = da9055_of_match,
},
};
static int __init da9055_i2c_init(void)
{
int ret;
ret = i2c_add_driver(&da9055_i2c_driver);
if (ret != 0) {
pr_err("DA9055 I2C registration failed %d\n", ret);
return ret;
}
return 0;
}
subsys_initcall(da9055_i2c_init);
static void __exit da9055_i2c_exit(void)
{
i2c_del_driver(&da9055_i2c_driver);
}
module_exit(da9055_i2c_exit);
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
MODULE_DESCRIPTION("I2C driver for Dialog DA9055 PMIC");
| linux-master | drivers/mfd/da9055-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Maxim MAX77620 MFD Driver
*
* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Laxman Dewangan <[email protected]>
* Chaitanya Bandi <[email protected]>
* Mallikarjun Kasoju <[email protected]>
*/
/****************** Teminology used in driver ********************
* Here are some terminology used from datasheet for quick reference:
* Flexible Power Sequence (FPS):
* The Flexible Power Sequencer (FPS) allows each regulator to power up under
* hardware or software control. Additionally, each regulator can power on
* independently or among a group of other regulators with an adjustable
* power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
* be programmed to be part of a sequence allowing external regulators to be
* sequenced along with internal regulators. 32KHz clock can be programmed to
* be part of a sequence.
* There is 3 FPS confguration registers and all resources are configured to
* any of these FPS or no FPS.
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max77620.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
static struct max77620_chip *max77620_scratch;
static const struct resource gpio_resources[] = {
DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
};
static const struct resource power_resources[] = {
DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
};
static const struct resource rtc_resources[] = {
DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
};
static const struct resource thermal_resources[] = {
DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
};
static const struct regmap_irq max77620_top_irqs[] = {
REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
};
static const struct mfd_cell max77620_children[] = {
{ .name = "max77620-pinctrl", },
{ .name = "max77620-clock", },
{ .name = "max77620-pmic", },
{ .name = "max77620-watchdog", },
{
.name = "max77620-gpio",
.resources = gpio_resources,
.num_resources = ARRAY_SIZE(gpio_resources),
}, {
.name = "max77620-rtc",
.resources = rtc_resources,
.num_resources = ARRAY_SIZE(rtc_resources),
}, {
.name = "max77620-power",
.resources = power_resources,
.num_resources = ARRAY_SIZE(power_resources),
}, {
.name = "max77620-thermal",
.resources = thermal_resources,
.num_resources = ARRAY_SIZE(thermal_resources),
},
};
static const struct mfd_cell max20024_children[] = {
{ .name = "max20024-pinctrl", },
{ .name = "max77620-clock", },
{ .name = "max20024-pmic", },
{ .name = "max77620-watchdog", },
{
.name = "max77620-gpio",
.resources = gpio_resources,
.num_resources = ARRAY_SIZE(gpio_resources),
}, {
.name = "max77620-rtc",
.resources = rtc_resources,
.num_resources = ARRAY_SIZE(rtc_resources),
}, {
.name = "max20024-power",
.resources = power_resources,
.num_resources = ARRAY_SIZE(power_resources),
},
};
static const struct mfd_cell max77663_children[] = {
{ .name = "max77620-pinctrl", },
{ .name = "max77620-clock", },
{ .name = "max77663-pmic", },
{ .name = "max77620-watchdog", },
{
.name = "max77620-gpio",
.resources = gpio_resources,
.num_resources = ARRAY_SIZE(gpio_resources),
}, {
.name = "max77620-rtc",
.resources = rtc_resources,
.num_resources = ARRAY_SIZE(rtc_resources),
}, {
.name = "max77663-power",
.resources = power_resources,
.num_resources = ARRAY_SIZE(power_resources),
},
};
static const struct regmap_range max77620_readable_ranges[] = {
regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
};
static const struct regmap_access_table max77620_readable_table = {
.yes_ranges = max77620_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
};
static const struct regmap_range max20024_readable_ranges[] = {
regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
};
static const struct regmap_access_table max20024_readable_table = {
.yes_ranges = max20024_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
};
static const struct regmap_range max77620_writable_ranges[] = {
regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
};
static const struct regmap_access_table max77620_writable_table = {
.yes_ranges = max77620_writable_ranges,
.n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
};
static const struct regmap_range max77620_cacheable_ranges[] = {
regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
};
static const struct regmap_access_table max77620_volatile_table = {
.no_ranges = max77620_cacheable_ranges,
.n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
};
static const struct regmap_config max77620_regmap_config = {
.name = "power-slave",
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX77620_REG_DVSSD4 + 1,
.cache_type = REGCACHE_RBTREE,
.rd_table = &max77620_readable_table,
.wr_table = &max77620_writable_table,
.volatile_table = &max77620_volatile_table,
.use_single_write = true,
};
static const struct regmap_config max20024_regmap_config = {
.name = "power-slave",
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX20024_REG_MAX_ADD + 1,
.cache_type = REGCACHE_RBTREE,
.rd_table = &max20024_readable_table,
.wr_table = &max77620_writable_table,
.volatile_table = &max77620_volatile_table,
};
static const struct regmap_range max77663_readable_ranges[] = {
regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
};
static const struct regmap_access_table max77663_readable_table = {
.yes_ranges = max77663_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges),
};
static const struct regmap_range max77663_writable_ranges[] = {
regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),
};
static const struct regmap_access_table max77663_writable_table = {
.yes_ranges = max77663_writable_ranges,
.n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges),
};
static const struct regmap_config max77663_regmap_config = {
.name = "power-slave",
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX77620_REG_CID5 + 1,
.cache_type = REGCACHE_RBTREE,
.rd_table = &max77663_readable_table,
.wr_table = &max77663_writable_table,
.volatile_table = &max77620_volatile_table,
};
/*
* MAX77620 and MAX20024 has the following steps of the interrupt handling
* for TOP interrupts:
* 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM.
* 2. Read IRQTOP and service the interrupt.
* 3. Once all interrupts has been checked and serviced, the interrupt service
* routine un-masks the hardware interrupt line by clearing GLBLM.
*/
static int max77620_irq_global_mask(void *irq_drv_data)
{
struct max77620_chip *chip = irq_drv_data;
int ret;
ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK);
if (ret < 0)
dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);
return ret;
}
static int max77620_irq_global_unmask(void *irq_drv_data)
{
struct max77620_chip *chip = irq_drv_data;
int ret;
ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
MAX77620_GLBLM_MASK, 0);
if (ret < 0)
dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);
return ret;
}
static struct regmap_irq_chip max77620_top_irq_chip = {
.name = "max77620-top",
.irqs = max77620_top_irqs,
.num_irqs = ARRAY_SIZE(max77620_top_irqs),
.num_regs = 2,
.status_base = MAX77620_REG_IRQTOP,
.mask_base = MAX77620_REG_IRQTOPM,
.handle_pre_irq = max77620_irq_global_mask,
.handle_post_irq = max77620_irq_global_unmask,
};
/* max77620_get_fps_period_reg_value: Get FPS bit field value from
* requested periods.
* MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
* and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
* 160, 320, 540, 1280 and 2560 microseconds.
* The FPS register has 3 bits field to set the FPS period as
* bits max77620 max20024
* 000 40 20
* 001 80 40
* :::
*/
static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
int tperiod)
{
int fps_min_period;
int i;
switch (chip->chip_id) {
case MAX20024:
fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
break;
case MAX77620:
fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
break;
case MAX77663:
fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
break;
default:
return -EINVAL;
}
for (i = 0; i < 7; i++) {
if (fps_min_period >= tperiod)
return i;
fps_min_period *= 2;
}
return i;
}
/* max77620_config_fps: Configure FPS configuration registers
* based on platform specific information.
*/
static int max77620_config_fps(struct max77620_chip *chip,
struct device_node *fps_np)
{
struct device *dev = chip->dev;
unsigned int mask = 0, config = 0;
u32 fps_max_period;
u32 param_val;
int tperiod, fps_id;
int ret;
char fps_name[10];
switch (chip->chip_id) {
case MAX20024:
fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
break;
case MAX77620:
fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
break;
case MAX77663:
fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
break;
default:
return -EINVAL;
}
for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
sprintf(fps_name, "fps%d", fps_id);
if (of_node_name_eq(fps_np, fps_name))
break;
}
if (fps_id == MAX77620_FPS_COUNT) {
dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np);
return -EINVAL;
}
ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
¶m_val);
if (!ret) {
mask |= MAX77620_FPS_TIME_PERIOD_MASK;
chip->shutdown_fps_period[fps_id] = min(param_val,
fps_max_period);
tperiod = max77620_get_fps_period_reg_value(chip,
chip->shutdown_fps_period[fps_id]);
config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
}
ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
¶m_val);
if (!ret)
chip->suspend_fps_period[fps_id] = min(param_val,
fps_max_period);
ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
¶m_val);
if (!ret) {
if (param_val > 2) {
dev_err(dev, "FPS%d event-source invalid\n", fps_id);
return -EINVAL;
}
mask |= MAX77620_FPS_EN_SRC_MASK;
config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
if (param_val == 2) {
mask |= MAX77620_FPS_ENFPS_SW_MASK;
config |= MAX77620_FPS_ENFPS_SW;
}
}
if (!chip->sleep_enable && !chip->enable_global_lpm) {
ret = of_property_read_u32(fps_np,
"maxim,device-state-on-disabled-event",
¶m_val);
if (!ret) {
if (param_val == 0)
chip->sleep_enable = true;
else if (param_val == 1)
chip->enable_global_lpm = true;
}
}
ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
mask, config);
if (ret < 0) {
dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
return ret;
}
return 0;
}
static int max77620_initialise_fps(struct max77620_chip *chip)
{
struct device *dev = chip->dev;
struct device_node *fps_np, *fps_child;
u8 config;
int fps_id;
int ret;
for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
chip->shutdown_fps_period[fps_id] = -1;
chip->suspend_fps_period[fps_id] = -1;
}
fps_np = of_get_child_by_name(dev->of_node, "fps");
if (!fps_np)
goto skip_fps;
for_each_child_of_node(fps_np, fps_child) {
ret = max77620_config_fps(chip, fps_child);
if (ret < 0) {
of_node_put(fps_child);
of_node_put(fps_np);
return ret;
}
}
of_node_put(fps_np);
config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
if (ret < 0) {
dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
return ret;
}
skip_fps:
if (chip->chip_id == MAX77663)
return 0;
/* Enable wake on EN0 pin */
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
MAX77620_ONOFFCNFG2_WK_EN0,
MAX77620_ONOFFCNFG2_WK_EN0);
if (ret < 0) {
dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
return ret;
}
/* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
config, config);
if (ret < 0) {
dev_err(dev, "Failed to update SLPEN: %d\n", ret);
return ret;
}
}
return 0;
}
static int max77620_read_es_version(struct max77620_chip *chip)
{
unsigned int val;
u8 cid_val[6];
int i;
int ret;
for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
ret = regmap_read(chip->rmap, i, &val);
if (ret < 0) {
dev_err(chip->dev, "Failed to read CID: %d\n", ret);
return ret;
}
dev_dbg(chip->dev, "CID%d: 0x%02x\n",
i - MAX77620_REG_CID0, val);
cid_val[i - MAX77620_REG_CID0] = val;
}
/* CID4 is OTP Version and CID5 is ES version */
dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
return ret;
}
static void max77620_pm_power_off(void)
{
struct max77620_chip *chip = max77620_scratch;
regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
MAX77620_ONOFFCNFG1_SFT_RST,
MAX77620_ONOFFCNFG1_SFT_RST);
}
static int max77620_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
const struct regmap_config *rmap_config;
struct max77620_chip *chip;
const struct mfd_cell *mfd_cells;
int n_mfd_cells;
bool pm_off;
int ret;
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
i2c_set_clientdata(client, chip);
chip->dev = &client->dev;
chip->chip_irq = client->irq;
chip->chip_id = (enum max77620_chip_id)id->driver_data;
switch (chip->chip_id) {
case MAX77620:
mfd_cells = max77620_children;
n_mfd_cells = ARRAY_SIZE(max77620_children);
rmap_config = &max77620_regmap_config;
break;
case MAX20024:
mfd_cells = max20024_children;
n_mfd_cells = ARRAY_SIZE(max20024_children);
rmap_config = &max20024_regmap_config;
break;
case MAX77663:
mfd_cells = max77663_children;
n_mfd_cells = ARRAY_SIZE(max77663_children);
rmap_config = &max77663_regmap_config;
break;
default:
dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
return -EINVAL;
}
chip->rmap = devm_regmap_init_i2c(client, rmap_config);
if (IS_ERR(chip->rmap)) {
ret = PTR_ERR(chip->rmap);
dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret);
return ret;
}
ret = max77620_read_es_version(chip);
if (ret < 0)
return ret;
max77620_top_irq_chip.irq_drv_data = chip;
ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77620_top_irq_chip,
&chip->top_irq_data);
if (ret < 0) {
dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
return ret;
}
ret = max77620_initialise_fps(chip);
if (ret < 0)
return ret;
ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
mfd_cells, n_mfd_cells, NULL, 0,
regmap_irq_get_domain(chip->top_irq_data));
if (ret < 0) {
dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
return ret;
}
pm_off = of_device_is_system_power_controller(client->dev.of_node);
if (pm_off && !pm_power_off) {
max77620_scratch = chip;
pm_power_off = max77620_pm_power_off;
}
return 0;
}
static int max77620_set_fps_period(struct max77620_chip *chip,
int fps_id, int time_period)
{
int period = max77620_get_fps_period_reg_value(chip, time_period);
int ret;
ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
MAX77620_FPS_TIME_PERIOD_MASK,
period << MAX77620_FPS_TIME_PERIOD_SHIFT);
if (ret < 0) {
dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
return ret;
}
return 0;
}
static int max77620_i2c_suspend(struct device *dev)
{
struct max77620_chip *chip = dev_get_drvdata(dev);
struct i2c_client *client = to_i2c_client(dev);
unsigned int config;
int fps;
int ret;
for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
if (chip->suspend_fps_period[fps] < 0)
continue;
ret = max77620_set_fps_period(chip, fps,
chip->suspend_fps_period[fps]);
if (ret < 0)
return ret;
}
/*
* For MAX20024: No need to configure SLPEN on suspend as
* it will be configured on Init.
*/
if (chip->chip_id == MAX20024)
goto out;
config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
MAX77620_ONOFFCNFG1_SLPEN,
config);
if (ret < 0) {
dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
return ret;
}
if (chip->chip_id == MAX77663)
goto out;
/* Disable WK_EN0 */
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
MAX77620_ONOFFCNFG2_WK_EN0, 0);
if (ret < 0) {
dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
return ret;
}
out:
disable_irq(client->irq);
return 0;
}
static int max77620_i2c_resume(struct device *dev)
{
struct max77620_chip *chip = dev_get_drvdata(dev);
struct i2c_client *client = to_i2c_client(dev);
int ret;
int fps;
for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
if (chip->shutdown_fps_period[fps] < 0)
continue;
ret = max77620_set_fps_period(chip, fps,
chip->shutdown_fps_period[fps]);
if (ret < 0)
return ret;
}
/*
* For MAX20024: No need to configure WKEN0 on resume as
* it is configured on Init.
*/
if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663)
goto out;
/* Enable WK_EN0 */
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
MAX77620_ONOFFCNFG2_WK_EN0,
MAX77620_ONOFFCNFG2_WK_EN0);
if (ret < 0) {
dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
return ret;
}
out:
enable_irq(client->irq);
return 0;
}
static const struct i2c_device_id max77620_id[] = {
{"max77620", MAX77620},
{"max20024", MAX20024},
{"max77663", MAX77663},
{},
};
static DEFINE_SIMPLE_DEV_PM_OPS(max77620_pm_ops,
max77620_i2c_suspend, max77620_i2c_resume);
static struct i2c_driver max77620_driver = {
.driver = {
.name = "max77620",
.pm = pm_sleep_ptr(&max77620_pm_ops),
},
.probe = max77620_probe,
.id_table = max77620_id,
};
builtin_i2c_driver(max77620_driver);
| linux-master | drivers/mfd/max77620.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MFD core driver for Intel Broxton Whiskey Cove PMIC
*
* Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
*/
#include <linux/acpi.h>
#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/mfd/intel_soc_pmic_bxtwc.h>
#include <linux/module.h>
#include <asm/intel_scu_ipc.h>
/* PMIC device registers */
#define REG_ADDR_MASK GENMASK(15, 8)
#define REG_ADDR_SHIFT 8
#define REG_OFFSET_MASK GENMASK(7, 0)
/* Interrupt Status Registers */
#define BXTWC_IRQLVL1 0x4E02
#define BXTWC_PWRBTNIRQ 0x4E03
#define BXTWC_THRM0IRQ 0x4E04
#define BXTWC_THRM1IRQ 0x4E05
#define BXTWC_THRM2IRQ 0x4E06
#define BXTWC_BCUIRQ 0x4E07
#define BXTWC_ADCIRQ 0x4E08
#define BXTWC_CHGR0IRQ 0x4E09
#define BXTWC_CHGR1IRQ 0x4E0A
#define BXTWC_GPIOIRQ0 0x4E0B
#define BXTWC_GPIOIRQ1 0x4E0C
#define BXTWC_CRITIRQ 0x4E0D
#define BXTWC_TMUIRQ 0x4FB6
/* Interrupt MASK Registers */
#define BXTWC_MIRQLVL1 0x4E0E
#define BXTWC_MIRQLVL1_MCHGR BIT(5)
#define BXTWC_MPWRBTNIRQ 0x4E0F
#define BXTWC_MTHRM0IRQ 0x4E12
#define BXTWC_MTHRM1IRQ 0x4E13
#define BXTWC_MTHRM2IRQ 0x4E14
#define BXTWC_MBCUIRQ 0x4E15
#define BXTWC_MADCIRQ 0x4E16
#define BXTWC_MCHGR0IRQ 0x4E17
#define BXTWC_MCHGR1IRQ 0x4E18
#define BXTWC_MGPIO0IRQ 0x4E19
#define BXTWC_MGPIO1IRQ 0x4E1A
#define BXTWC_MCRITIRQ 0x4E1B
#define BXTWC_MTMUIRQ 0x4FB7
/* Whiskey Cove PMIC share same ACPI ID between different platforms */
#define BROXTON_PMIC_WC_HRV 4
#define PMC_PMIC_ACCESS 0xFF
#define PMC_PMIC_READ 0x0
#define PMC_PMIC_WRITE 0x1
enum bxtwc_irqs {
BXTWC_PWRBTN_LVL1_IRQ = 0,
BXTWC_TMU_LVL1_IRQ,
BXTWC_THRM_LVL1_IRQ,
BXTWC_BCU_LVL1_IRQ,
BXTWC_ADC_LVL1_IRQ,
BXTWC_CHGR_LVL1_IRQ,
BXTWC_GPIO_LVL1_IRQ,
BXTWC_CRIT_LVL1_IRQ,
};
enum bxtwc_irqs_pwrbtn {
BXTWC_PWRBTN_IRQ = 0,
BXTWC_UIBTN_IRQ,
};
enum bxtwc_irqs_bcu {
BXTWC_BCU_IRQ = 0,
};
enum bxtwc_irqs_adc {
BXTWC_ADC_IRQ = 0,
};
enum bxtwc_irqs_chgr {
BXTWC_USBC_IRQ = 0,
BXTWC_CHGR0_IRQ,
BXTWC_CHGR1_IRQ,
};
enum bxtwc_irqs_tmu {
BXTWC_TMU_IRQ = 0,
};
enum bxtwc_irqs_crit {
BXTWC_CRIT_IRQ = 0,
};
static const struct regmap_irq bxtwc_regmap_irqs[] = {
REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
};
static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, BIT(0)),
};
static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)),
};
static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)),
};
static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)),
REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)),
};
static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)),
};
static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)),
};
static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
.name = "bxtwc_irq_chip",
.status_base = BXTWC_IRQLVL1,
.mask_base = BXTWC_MIRQLVL1,
.irqs = bxtwc_regmap_irqs,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
.num_regs = 1,
};
static struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
.name = "bxtwc_irq_chip_pwrbtn",
.status_base = BXTWC_PWRBTNIRQ,
.mask_base = BXTWC_MPWRBTNIRQ,
.irqs = bxtwc_regmap_irqs_pwrbtn,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn),
.num_regs = 1,
};
static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
.name = "bxtwc_irq_chip_tmu",
.status_base = BXTWC_TMUIRQ,
.mask_base = BXTWC_MTMUIRQ,
.irqs = bxtwc_regmap_irqs_tmu,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
.num_regs = 1,
};
static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
.name = "bxtwc_irq_chip_bcu",
.status_base = BXTWC_BCUIRQ,
.mask_base = BXTWC_MBCUIRQ,
.irqs = bxtwc_regmap_irqs_bcu,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
.num_regs = 1,
};
static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
.name = "bxtwc_irq_chip_adc",
.status_base = BXTWC_ADCIRQ,
.mask_base = BXTWC_MADCIRQ,
.irqs = bxtwc_regmap_irqs_adc,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
.num_regs = 1,
};
static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
.name = "bxtwc_irq_chip_chgr",
.status_base = BXTWC_CHGR0IRQ,
.mask_base = BXTWC_MCHGR0IRQ,
.irqs = bxtwc_regmap_irqs_chgr,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
.num_regs = 2,
};
static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
.name = "bxtwc_irq_chip_crit",
.status_base = BXTWC_CRITIRQ,
.mask_base = BXTWC_MCRITIRQ,
.irqs = bxtwc_regmap_irqs_crit,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
.num_regs = 1,
};
static const struct resource gpio_resources[] = {
DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
};
static const struct resource adc_resources[] = {
DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
};
static const struct resource usbc_resources[] = {
DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
};
static const struct resource charger_resources[] = {
DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
};
static const struct resource thermal_resources[] = {
DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
};
static const struct resource bcu_resources[] = {
DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
};
static const struct resource tmu_resources[] = {
DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
};
static struct mfd_cell bxt_wc_dev[] = {
{
.name = "bxt_wcove_gpadc",
.num_resources = ARRAY_SIZE(adc_resources),
.resources = adc_resources,
},
{
.name = "bxt_wcove_thermal",
.num_resources = ARRAY_SIZE(thermal_resources),
.resources = thermal_resources,
},
{
.name = "bxt_wcove_usbc",
.num_resources = ARRAY_SIZE(usbc_resources),
.resources = usbc_resources,
},
{
.name = "bxt_wcove_ext_charger",
.num_resources = ARRAY_SIZE(charger_resources),
.resources = charger_resources,
},
{
.name = "bxt_wcove_bcu",
.num_resources = ARRAY_SIZE(bcu_resources),
.resources = bcu_resources,
},
{
.name = "bxt_wcove_tmu",
.num_resources = ARRAY_SIZE(tmu_resources),
.resources = tmu_resources,
},
{
.name = "bxt_wcove_gpio",
.num_resources = ARRAY_SIZE(gpio_resources),
.resources = gpio_resources,
},
{
.name = "bxt_wcove_region",
},
};
static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
int ret;
int i2c_addr;
u8 ipc_in[2];
u8 ipc_out[4];
struct intel_soc_pmic *pmic = context;
if (!pmic)
return -EINVAL;
if (reg & REG_ADDR_MASK)
i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
else
i2c_addr = BXTWC_DEVICE1_ADDR;
reg &= REG_OFFSET_MASK;
ipc_in[0] = reg;
ipc_in[1] = i2c_addr;
ret = intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,
PMC_PMIC_READ, ipc_in, sizeof(ipc_in),
ipc_out, sizeof(ipc_out));
if (ret)
return ret;
*val = ipc_out[0];
return 0;
}
static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
unsigned int val)
{
int i2c_addr;
u8 ipc_in[3];
struct intel_soc_pmic *pmic = context;
if (!pmic)
return -EINVAL;
if (reg & REG_ADDR_MASK)
i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
else
i2c_addr = BXTWC_DEVICE1_ADDR;
reg &= REG_OFFSET_MASK;
ipc_in[0] = reg;
ipc_in[1] = i2c_addr;
ipc_in[2] = val;
return intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,
PMC_PMIC_WRITE, ipc_in, sizeof(ipc_in),
NULL, 0);
}
/* sysfs interfaces to r/w PMIC registers, required by initial script */
static unsigned long bxtwc_reg_addr;
static ssize_t addr_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return sysfs_emit(buf, "0x%lx\n", bxtwc_reg_addr);
}
static ssize_t addr_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
int ret;
ret = kstrtoul(buf, 0, &bxtwc_reg_addr);
if (ret)
return ret;
return count;
}
static ssize_t val_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret;
unsigned int val;
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
if (ret) {
dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
return ret;
}
return sysfs_emit(buf, "0x%02x\n", val);
}
static ssize_t val_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
int ret;
unsigned int val;
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
ret = kstrtouint(buf, 0, &val);
if (ret)
return ret;
ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
if (ret) {
dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
val, bxtwc_reg_addr);
return ret;
}
return count;
}
static DEVICE_ATTR_ADMIN_RW(addr);
static DEVICE_ATTR_ADMIN_RW(val);
static struct attribute *bxtwc_attrs[] = {
&dev_attr_addr.attr,
&dev_attr_val.attr,
NULL
};
static const struct attribute_group bxtwc_group = {
.attrs = bxtwc_attrs,
};
static const struct attribute_group *bxtwc_groups[] = {
&bxtwc_group,
NULL
};
static const struct regmap_config bxtwc_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.reg_write = regmap_ipc_byte_reg_write,
.reg_read = regmap_ipc_byte_reg_read,
};
static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
struct regmap_irq_chip_data *pdata,
int pirq, int irq_flags,
const struct regmap_irq_chip *chip,
struct regmap_irq_chip_data **data)
{
int irq;
irq = regmap_irq_get_virq(pdata, pirq);
if (irq < 0)
return dev_err_probe(pmic->dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
pirq, chip->name);
return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
0, chip, data);
}
static int bxtwc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret;
acpi_status status;
unsigned long long hrv;
struct intel_soc_pmic *pmic;
status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
if (ACPI_FAILURE(status))
return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");
if (hrv != BROXTON_PMIC_WC_HRV)
return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);
pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
pmic->irq = ret;
platform_set_drvdata(pdev, pmic);
pmic->dev = dev;
pmic->scu = devm_intel_scu_ipc_dev_get(dev);
if (!pmic->scu)
return -EPROBE_DEFER;
pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bxtwc_regmap_config);
if (IS_ERR(pmic->regmap))
return dev_err_probe(dev, PTR_ERR(pmic->regmap), "Failed to initialise regmap\n");
ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
IRQF_ONESHOT | IRQF_SHARED,
0, &bxtwc_regmap_irq_chip,
&pmic->irq_chip_data);
if (ret)
return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_PWRBTN_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_pwrbtn,
&pmic->irq_chip_data_pwrbtn);
if (ret)
return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n");
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_TMU_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_tmu,
&pmic->irq_chip_data_tmu);
if (ret)
return dev_err_probe(dev, ret, "Failed to add TMU IRQ chip\n");
/* Add chained IRQ handler for BCU IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_BCU_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_bcu,
&pmic->irq_chip_data_bcu);
if (ret)
return dev_err_probe(dev, ret, "Failed to add BUC IRQ chip\n");
/* Add chained IRQ handler for ADC IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_ADC_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_adc,
&pmic->irq_chip_data_adc);
if (ret)
return dev_err_probe(dev, ret, "Failed to add ADC IRQ chip\n");
/* Add chained IRQ handler for CHGR IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_CHGR_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_chgr,
&pmic->irq_chip_data_chgr);
if (ret)
return dev_err_probe(dev, ret, "Failed to add CHGR IRQ chip\n");
/* Add chained IRQ handler for CRIT IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_CRIT_LVL1_IRQ,
IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_crit,
&pmic->irq_chip_data_crit);
if (ret)
return dev_err_probe(dev, ret, "Failed to add CRIT IRQ chip\n");
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),
NULL, 0, NULL);
if (ret)
return dev_err_probe(dev, ret, "Failed to add devices\n");
/*
* There is a known H/W bug. Upon reset, BIT 5 of register
* BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
* later it's set to 1(masked) automatically by hardware. So we
* place the software workaround here to unmask it again in order
* to re-enable the charger interrupt.
*/
regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, BXTWC_MIRQLVL1_MCHGR, 0);
return 0;
}
static void bxtwc_shutdown(struct platform_device *pdev)
{
struct intel_soc_pmic *pmic = platform_get_drvdata(pdev);
disable_irq(pmic->irq);
}
static int bxtwc_suspend(struct device *dev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
disable_irq(pmic->irq);
return 0;
}
static int bxtwc_resume(struct device *dev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
enable_irq(pmic->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
static const struct acpi_device_id bxtwc_acpi_ids[] = {
{ "INT34D3", },
{ }
};
MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
static struct platform_driver bxtwc_driver = {
.probe = bxtwc_probe,
.shutdown = bxtwc_shutdown,
.driver = {
.name = "BXTWC PMIC",
.pm = pm_sleep_ptr(&bxtwc_pm_ops),
.acpi_match_table = bxtwc_acpi_ids,
.dev_groups = bxtwc_groups,
},
};
module_platform_driver(bxtwc_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Qipeng Zha <[email protected]>");
| linux-master | drivers/mfd/intel_soc_pmic_bxtwc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* tps65910.c -- TI TPS6591x
*
* Copyright 2010 Texas Instruments Inc.
*
* Author: Jorge Eduardo Candelaria <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/debugfs.h>
#include <linux/gpio.h>
#include <linux/mfd/tps65910.h>
#define COMP1 0
#define COMP2 1
/* Comparator 1 voltage selection table in millivolts */
static const u16 COMP_VSEL_TABLE[] = {
0, 2500, 2500, 2500, 2500, 2550, 2600, 2650,
2700, 2750, 2800, 2850, 2900, 2950, 3000, 3050,
3100, 3150, 3200, 3250, 3300, 3350, 3400, 3450,
3500,
};
struct comparator {
const char *name;
int reg;
int uV_max;
const u16 *vsel_table;
};
static struct comparator tps_comparators[] = {
{
.name = "COMP1",
.reg = TPS65911_VMBCH,
.uV_max = 3500,
.vsel_table = COMP_VSEL_TABLE,
},
{
.name = "COMP2",
.reg = TPS65911_VMBCH2,
.uV_max = 3500,
.vsel_table = COMP_VSEL_TABLE,
},
};
static int comp_threshold_set(struct tps65910 *tps65910, int id, int voltage)
{
struct comparator tps_comp = tps_comparators[id];
int curr_voltage = 0;
int ret;
u8 index = 0, val;
while (curr_voltage < tps_comp.uV_max) {
curr_voltage = tps_comp.vsel_table[index];
if (curr_voltage >= voltage)
break;
else if (curr_voltage < voltage)
index ++;
}
if (curr_voltage > tps_comp.uV_max)
return -EINVAL;
val = index << 1;
ret = regmap_write(tps65910->regmap, tps_comp.reg, val);
return ret;
}
static int comp_threshold_get(struct tps65910 *tps65910, int id)
{
struct comparator tps_comp = tps_comparators[id];
unsigned int val;
int ret;
ret = regmap_read(tps65910->regmap, tps_comp.reg, &val);
if (ret < 0)
return ret;
val >>= 1;
return tps_comp.vsel_table[val];
}
static ssize_t comp_threshold_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct tps65910 *tps65910 = dev_get_drvdata(dev->parent);
struct attribute comp_attr = attr->attr;
int id, uVolt;
if (!strcmp(comp_attr.name, "comp1_threshold"))
id = COMP1;
else if (!strcmp(comp_attr.name, "comp2_threshold"))
id = COMP2;
else
return -EINVAL;
uVolt = comp_threshold_get(tps65910, id);
return sprintf(buf, "%d\n", uVolt);
}
static DEVICE_ATTR(comp1_threshold, S_IRUGO, comp_threshold_show, NULL);
static DEVICE_ATTR(comp2_threshold, S_IRUGO, comp_threshold_show, NULL);
static int tps65911_comparator_probe(struct platform_device *pdev)
{
struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
struct tps65910_board *pdata = dev_get_platdata(tps65910->dev);
int ret;
ret = comp_threshold_set(tps65910, COMP1, pdata->vmbch_threshold);
if (ret < 0) {
dev_err(&pdev->dev, "cannot set COMP1 threshold\n");
return ret;
}
ret = comp_threshold_set(tps65910, COMP2, pdata->vmbch2_threshold);
if (ret < 0) {
dev_err(&pdev->dev, "cannot set COMP2 threshold\n");
return ret;
}
/* Create sysfs entry */
ret = device_create_file(&pdev->dev, &dev_attr_comp1_threshold);
if (ret < 0)
dev_err(&pdev->dev, "failed to add COMP1 sysfs file\n");
ret = device_create_file(&pdev->dev, &dev_attr_comp2_threshold);
if (ret < 0)
dev_err(&pdev->dev, "failed to add COMP2 sysfs file\n");
return ret;
}
static int tps65911_comparator_remove(struct platform_device *pdev)
{
struct tps65910 *tps65910;
tps65910 = dev_get_drvdata(pdev->dev.parent);
device_remove_file(&pdev->dev, &dev_attr_comp2_threshold);
device_remove_file(&pdev->dev, &dev_attr_comp1_threshold);
return 0;
}
static struct platform_driver tps65911_comparator_driver = {
.driver = {
.name = "tps65911-comparator",
},
.probe = tps65911_comparator_probe,
.remove = tps65911_comparator_remove,
};
static int __init tps65911_comparator_init(void)
{
return platform_driver_register(&tps65911_comparator_driver);
}
subsys_initcall(tps65911_comparator_init);
static void __exit tps65911_comparator_exit(void)
{
platform_driver_unregister(&tps65911_comparator_driver);
}
module_exit(tps65911_comparator_exit);
MODULE_AUTHOR("Jorge Eduardo Candelaria <[email protected]>");
MODULE_DESCRIPTION("TPS65911 comparator driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:tps65911-comparator");
| linux-master | drivers/mfd/tps65911-comparator.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2022 Analog Devices, Inc.
* Driver for the MAX77540 and MAX77541
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max77541.h>
#include <linux/property.h>
#include <linux/regmap.h>
static const struct regmap_config max77541_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static const struct regmap_irq max77541_src_irqs[] = {
{ .mask = MAX77541_BIT_INT_SRC_TOPSYS },
{ .mask = MAX77541_BIT_INT_SRC_BUCK },
};
static const struct regmap_irq_chip max77541_src_irq_chip = {
.name = "max77541-src",
.status_base = MAX77541_REG_INT_SRC,
.mask_base = MAX77541_REG_INT_SRC_M,
.num_regs = 1,
.irqs = max77541_src_irqs,
.num_irqs = ARRAY_SIZE(max77541_src_irqs),
};
static const struct regmap_irq max77541_topsys_irqs[] = {
{ .mask = MAX77541_BIT_TOPSYS_INT_TJ_120C },
{ .mask = MAX77541_BIT_TOPSYS_INT_TJ_140C },
{ .mask = MAX77541_BIT_TOPSYS_INT_TSHDN },
{ .mask = MAX77541_BIT_TOPSYS_INT_UVLO },
{ .mask = MAX77541_BIT_TOPSYS_INT_ALT_SWO },
{ .mask = MAX77541_BIT_TOPSYS_INT_EXT_FREQ_DET },
};
static const struct regmap_irq_chip max77541_topsys_irq_chip = {
.name = "max77541-topsys",
.status_base = MAX77541_REG_TOPSYS_INT,
.mask_base = MAX77541_REG_TOPSYS_INT_M,
.num_regs = 1,
.irqs = max77541_topsys_irqs,
.num_irqs = ARRAY_SIZE(max77541_topsys_irqs),
};
static const struct regmap_irq max77541_buck_irqs[] = {
{ .mask = MAX77541_BIT_BUCK_INT_M1_POK_FLT },
{ .mask = MAX77541_BIT_BUCK_INT_M2_POK_FLT },
{ .mask = MAX77541_BIT_BUCK_INT_M1_SCFLT },
{ .mask = MAX77541_BIT_BUCK_INT_M2_SCFLT },
};
static const struct regmap_irq_chip max77541_buck_irq_chip = {
.name = "max77541-buck",
.status_base = MAX77541_REG_BUCK_INT,
.mask_base = MAX77541_REG_BUCK_INT_M,
.num_regs = 1,
.irqs = max77541_buck_irqs,
.num_irqs = ARRAY_SIZE(max77541_buck_irqs),
};
static const struct regmap_irq max77541_adc_irqs[] = {
{ .mask = MAX77541_BIT_ADC_INT_CH1_I },
{ .mask = MAX77541_BIT_ADC_INT_CH2_I },
{ .mask = MAX77541_BIT_ADC_INT_CH3_I },
{ .mask = MAX77541_BIT_ADC_INT_CH6_I },
};
static const struct regmap_irq_chip max77541_adc_irq_chip = {
.name = "max77541-adc",
.status_base = MAX77541_REG_ADC_INT,
.mask_base = MAX77541_REG_ADC_INT_M,
.num_regs = 1,
.irqs = max77541_adc_irqs,
.num_irqs = ARRAY_SIZE(max77541_adc_irqs),
};
static const struct mfd_cell max77540_devs[] = {
MFD_CELL_OF("max77540-regulator", NULL, NULL, 0, 0, NULL),
};
static const struct mfd_cell max77541_devs[] = {
MFD_CELL_OF("max77541-regulator", NULL, NULL, 0, 0, NULL),
MFD_CELL_OF("max77541-adc", NULL, NULL, 0, 0, NULL),
};
static int max77541_pmic_irq_init(struct device *dev)
{
struct max77541 *max77541 = dev_get_drvdata(dev);
int irq = max77541->i2c->irq;
int ret;
ret = devm_regmap_add_irq_chip(dev, max77541->regmap, irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77541_src_irq_chip,
&max77541->irq_data);
if (ret)
return ret;
ret = devm_regmap_add_irq_chip(dev, max77541->regmap, irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77541_topsys_irq_chip,
&max77541->irq_topsys);
if (ret)
return ret;
ret = devm_regmap_add_irq_chip(dev, max77541->regmap, irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77541_buck_irq_chip,
&max77541->irq_buck);
if (ret)
return ret;
if (max77541->id == MAX77541) {
ret = devm_regmap_add_irq_chip(dev, max77541->regmap, irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77541_adc_irq_chip,
&max77541->irq_adc);
if (ret)
return ret;
}
return 0;
}
static int max77541_pmic_setup(struct device *dev)
{
struct max77541 *max77541 = dev_get_drvdata(dev);
const struct mfd_cell *cells;
int n_devs;
int ret;
switch (max77541->id) {
case MAX77540:
cells = max77540_devs;
n_devs = ARRAY_SIZE(max77540_devs);
break;
case MAX77541:
cells = max77541_devs;
n_devs = ARRAY_SIZE(max77541_devs);
break;
default:
return -EINVAL;
}
ret = max77541_pmic_irq_init(dev);
if (ret)
return dev_err_probe(dev, ret, "Failed to initialize IRQ\n");
ret = device_init_wakeup(dev, true);
if (ret)
return dev_err_probe(dev, ret, "Unable to init wakeup\n");
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
cells, n_devs, NULL, 0, NULL);
}
static int max77541_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct device *dev = &client->dev;
struct max77541 *max77541;
max77541 = devm_kzalloc(dev, sizeof(*max77541), GFP_KERNEL);
if (!max77541)
return -ENOMEM;
i2c_set_clientdata(client, max77541);
max77541->i2c = client;
max77541->id = (uintptr_t)device_get_match_data(dev);
if (!max77541->id)
max77541->id = (enum max7754x_ids)id->driver_data;
if (!max77541->id)
return -EINVAL;
max77541->regmap = devm_regmap_init_i2c(client,
&max77541_regmap_config);
if (IS_ERR(max77541->regmap))
return dev_err_probe(dev, PTR_ERR(max77541->regmap),
"Failed to allocate register map\n");
return max77541_pmic_setup(dev);
}
static const struct of_device_id max77541_of_id[] = {
{
.compatible = "adi,max77540",
.data = (void *)MAX77540,
},
{
.compatible = "adi,max77541",
.data = (void *)MAX77541,
},
{ }
};
MODULE_DEVICE_TABLE(of, max77541_of_id);
static const struct i2c_device_id max77541_id[] = {
{ "max77540", MAX77540 },
{ "max77541", MAX77541 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max77541_id);
static struct i2c_driver max77541_driver = {
.driver = {
.name = "max77541",
.of_match_table = max77541_of_id,
},
.probe = max77541_probe,
.id_table = max77541_id,
};
module_i2c_driver(max77541_driver);
MODULE_DESCRIPTION("MAX7740/MAX7741 Driver");
MODULE_AUTHOR("Okan Sahin <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/max77541.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* I2C driver for Renesas Synchronization Management Unit (SMU) devices.
*
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
*/
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rsmu.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "rsmu.h"
/*
* 32-bit register address: the lower 8 bits of the register address come
* from the offset addr byte and the upper 24 bits come from the page register.
*/
#define RSMU_CM_PAGE_ADDR 0xFC
#define RSMU_CM_PAGE_MASK 0xFFFFFF00
#define RSMU_CM_ADDRESS_MASK 0x000000FF
/*
* 15-bit register address: the lower 7 bits of the register address come
* from the offset addr byte and the upper 8 bits come from the page register.
*/
#define RSMU_SABRE_PAGE_ADDR 0x7F
#define RSMU_SABRE_PAGE_WINDOW 128
static const struct regmap_range_cfg rsmu_sabre_range_cfg[] = {
{
.range_min = 0,
.range_max = 0x400,
.selector_reg = RSMU_SABRE_PAGE_ADDR,
.selector_mask = 0xFF,
.selector_shift = 0,
.window_start = 0,
.window_len = RSMU_SABRE_PAGE_WINDOW,
}
};
static bool rsmu_sabre_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case RSMU_SABRE_PAGE_ADDR:
return false;
default:
return true;
}
}
static int rsmu_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
{
struct i2c_client *client = to_i2c_client(rsmu->dev);
struct i2c_msg msg[2];
int cnt;
msg[0].addr = client->addr;
msg[0].flags = 0;
msg[0].len = 1;
msg[0].buf = ®
msg[1].addr = client->addr;
msg[1].flags = I2C_M_RD;
msg[1].len = bytes;
msg[1].buf = buf;
cnt = i2c_transfer(client->adapter, msg, 2);
if (cnt < 0) {
dev_err(rsmu->dev, "i2c_transfer failed at addr: %04x!", reg);
return cnt;
} else if (cnt != 2) {
dev_err(rsmu->dev,
"i2c_transfer sent only %d of 2 messages", cnt);
return -EIO;
}
return 0;
}
static int rsmu_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
{
struct i2c_client *client = to_i2c_client(rsmu->dev);
u8 msg[RSMU_MAX_WRITE_COUNT + 1]; /* 1 Byte added for the device register */
int cnt;
if (bytes > RSMU_MAX_WRITE_COUNT)
return -EINVAL;
msg[0] = reg;
memcpy(&msg[1], buf, bytes);
cnt = i2c_master_send(client, msg, bytes + 1);
if (cnt < 0) {
dev_err(&client->dev,
"i2c_master_send failed at addr: %04x!", reg);
return cnt;
}
return 0;
}
static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg)
{
u32 page = reg & RSMU_CM_PAGE_MASK;
u8 buf[4];
int err;
/* Do not modify offset register for none-scsr registers */
if (reg < RSMU_CM_SCSR_BASE)
return 0;
/* Simply return if we are on the same page */
if (rsmu->page == page)
return 0;
buf[0] = 0x0;
buf[1] = (u8)((page >> 8) & 0xFF);
buf[2] = (u8)((page >> 16) & 0xFF);
buf[3] = (u8)((page >> 24) & 0xFF);
err = rsmu_write_device(rsmu, RSMU_CM_PAGE_ADDR, buf, sizeof(buf));
if (err)
dev_err(rsmu->dev, "Failed to set page offset 0x%x\n", page);
else
/* Remember the last page */
rsmu->page = page;
return err;
}
static int rsmu_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct rsmu_ddata *rsmu = i2c_get_clientdata((struct i2c_client *)context);
u8 addr = (u8)(reg & RSMU_CM_ADDRESS_MASK);
int err;
err = rsmu_write_page_register(rsmu, reg);
if (err)
return err;
err = rsmu_read_device(rsmu, addr, (u8 *)val, 1);
if (err)
dev_err(rsmu->dev, "Failed to read offset address 0x%x\n", addr);
return err;
}
static int rsmu_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct rsmu_ddata *rsmu = i2c_get_clientdata((struct i2c_client *)context);
u8 addr = (u8)(reg & RSMU_CM_ADDRESS_MASK);
u8 data = (u8)val;
int err;
err = rsmu_write_page_register(rsmu, reg);
if (err)
return err;
err = rsmu_write_device(rsmu, addr, &data, 1);
if (err)
dev_err(rsmu->dev,
"Failed to write offset address 0x%x\n", addr);
return err;
}
static const struct regmap_config rsmu_cm_regmap_config = {
.reg_bits = 32,
.val_bits = 8,
.max_register = 0x20120000,
.reg_read = rsmu_reg_read,
.reg_write = rsmu_reg_write,
.cache_type = REGCACHE_NONE,
};
static const struct regmap_config rsmu_sabre_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x400,
.ranges = rsmu_sabre_range_cfg,
.num_ranges = ARRAY_SIZE(rsmu_sabre_range_cfg),
.volatile_reg = rsmu_sabre_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.can_multi_write = true,
};
static const struct regmap_config rsmu_sl_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.max_register = 0x340,
.cache_type = REGCACHE_NONE,
.can_multi_write = true,
};
static int rsmu_i2c_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
const struct regmap_config *cfg;
struct rsmu_ddata *rsmu;
int ret;
rsmu = devm_kzalloc(&client->dev, sizeof(*rsmu), GFP_KERNEL);
if (!rsmu)
return -ENOMEM;
i2c_set_clientdata(client, rsmu);
rsmu->dev = &client->dev;
rsmu->type = (enum rsmu_type)id->driver_data;
switch (rsmu->type) {
case RSMU_CM:
cfg = &rsmu_cm_regmap_config;
break;
case RSMU_SABRE:
cfg = &rsmu_sabre_regmap_config;
break;
case RSMU_SL:
cfg = &rsmu_sl_regmap_config;
break;
default:
dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
return -ENODEV;
}
if (rsmu->type == RSMU_CM)
rsmu->regmap = devm_regmap_init(&client->dev, NULL, client, cfg);
else
rsmu->regmap = devm_regmap_init_i2c(client, cfg);
if (IS_ERR(rsmu->regmap)) {
ret = PTR_ERR(rsmu->regmap);
dev_err(rsmu->dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
return rsmu_core_init(rsmu);
}
static void rsmu_i2c_remove(struct i2c_client *client)
{
struct rsmu_ddata *rsmu = i2c_get_clientdata(client);
rsmu_core_exit(rsmu);
}
static const struct i2c_device_id rsmu_i2c_id[] = {
{ "8a34000", RSMU_CM },
{ "8a34001", RSMU_CM },
{ "82p33810", RSMU_SABRE },
{ "82p33811", RSMU_SABRE },
{ "8v19n850", RSMU_SL },
{ "8v19n851", RSMU_SL },
{}
};
MODULE_DEVICE_TABLE(i2c, rsmu_i2c_id);
static const struct of_device_id rsmu_i2c_of_match[] = {
{ .compatible = "idt,8a34000", .data = (void *)RSMU_CM },
{ .compatible = "idt,8a34001", .data = (void *)RSMU_CM },
{ .compatible = "idt,82p33810", .data = (void *)RSMU_SABRE },
{ .compatible = "idt,82p33811", .data = (void *)RSMU_SABRE },
{ .compatible = "idt,8v19n850", .data = (void *)RSMU_SL },
{ .compatible = "idt,8v19n851", .data = (void *)RSMU_SL },
{}
};
MODULE_DEVICE_TABLE(of, rsmu_i2c_of_match);
static struct i2c_driver rsmu_i2c_driver = {
.driver = {
.name = "rsmu-i2c",
.of_match_table = rsmu_i2c_of_match,
},
.probe = rsmu_i2c_probe,
.remove = rsmu_i2c_remove,
.id_table = rsmu_i2c_id,
};
static int __init rsmu_i2c_init(void)
{
return i2c_add_driver(&rsmu_i2c_driver);
}
subsys_initcall(rsmu_i2c_init);
static void __exit rsmu_i2c_exit(void)
{
i2c_del_driver(&rsmu_i2c_driver);
}
module_exit(rsmu_i2c_exit);
MODULE_DESCRIPTION("Renesas SMU I2C driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/rsmu_i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Compaq iPAQ h3xxx Atmel microcontroller companion support
*
* This is an Atmel AT90LS8535 with a special flashed-in firmware that
* implements the special protocol used by this driver.
*
* based on previous kernel 2.4 version by Andrew Christian
* Author : Alessandro Gardich <[email protected]>
* Author : Dmitry Artamonow <[email protected]>
* Author : Linus Walleij <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pm.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mfd/core.h>
#include <linux/mfd/ipaq-micro.h>
#include <linux/string.h>
#include <linux/random.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <mach/hardware.h>
static void ipaq_micro_trigger_tx(struct ipaq_micro *micro)
{
struct ipaq_micro_txdev *tx = µ->tx;
struct ipaq_micro_msg *msg = micro->msg;
int i, bp;
u8 checksum;
u32 val;
bp = 0;
tx->buf[bp++] = CHAR_SOF;
checksum = ((msg->id & 0x0f) << 4) | (msg->tx_len & 0x0f);
tx->buf[bp++] = checksum;
for (i = 0; i < msg->tx_len; i++) {
tx->buf[bp++] = msg->tx_data[i];
checksum += msg->tx_data[i];
}
tx->buf[bp++] = checksum;
tx->len = bp;
tx->index = 0;
/* Enable interrupt */
val = readl(micro->base + UTCR3);
val |= UTCR3_TIE;
writel(val, micro->base + UTCR3);
}
int ipaq_micro_tx_msg(struct ipaq_micro *micro, struct ipaq_micro_msg *msg)
{
unsigned long flags;
dev_dbg(micro->dev, "TX msg: %02x, %d bytes\n", msg->id, msg->tx_len);
spin_lock_irqsave(µ->lock, flags);
if (micro->msg) {
list_add_tail(&msg->node, µ->queue);
spin_unlock_irqrestore(µ->lock, flags);
return 0;
}
micro->msg = msg;
ipaq_micro_trigger_tx(micro);
spin_unlock_irqrestore(µ->lock, flags);
return 0;
}
EXPORT_SYMBOL(ipaq_micro_tx_msg);
static void micro_rx_msg(struct ipaq_micro *micro, u8 id, int len, u8 *data)
{
dev_dbg(micro->dev, "RX msg: %02x, %d bytes\n", id, len);
spin_lock(µ->lock);
switch (id) {
case MSG_VERSION:
case MSG_EEPROM_READ:
case MSG_EEPROM_WRITE:
case MSG_BACKLIGHT:
case MSG_NOTIFY_LED:
case MSG_THERMAL_SENSOR:
case MSG_BATTERY:
/* Handle synchronous messages */
if (micro->msg && micro->msg->id == id) {
struct ipaq_micro_msg *msg = micro->msg;
memcpy(msg->rx_data, data, len);
msg->rx_len = len;
complete(µ->msg->ack);
if (!list_empty(µ->queue)) {
micro->msg = list_entry(micro->queue.next,
struct ipaq_micro_msg,
node);
list_del_init(µ->msg->node);
ipaq_micro_trigger_tx(micro);
} else
micro->msg = NULL;
dev_dbg(micro->dev, "OK RX message 0x%02x\n", id);
} else {
dev_err(micro->dev,
"out of band RX message 0x%02x\n", id);
if (!micro->msg)
dev_info(micro->dev, "no message queued\n");
else
dev_info(micro->dev, "expected message %02x\n",
micro->msg->id);
}
break;
case MSG_KEYBOARD:
if (micro->key)
micro->key(micro->key_data, len, data);
else
dev_dbg(micro->dev, "key message ignored, no handle\n");
break;
case MSG_TOUCHSCREEN:
if (micro->ts)
micro->ts(micro->ts_data, len, data);
else
dev_dbg(micro->dev, "touchscreen message ignored, no handle\n");
break;
default:
dev_err(micro->dev,
"unknown msg %d [%d] %*ph\n", id, len, len, data);
}
spin_unlock(µ->lock);
}
static void micro_process_char(struct ipaq_micro *micro, u8 ch)
{
struct ipaq_micro_rxdev *rx = µ->rx;
switch (rx->state) {
case STATE_SOF: /* Looking for SOF */
if (ch == CHAR_SOF)
rx->state = STATE_ID; /* Next byte is the id and len */
break;
case STATE_ID: /* Looking for id and len byte */
rx->id = (ch & 0xf0) >> 4;
rx->len = (ch & 0x0f);
rx->index = 0;
rx->chksum = ch;
rx->state = (rx->len > 0) ? STATE_DATA : STATE_CHKSUM;
break;
case STATE_DATA: /* Looking for 'len' data bytes */
rx->chksum += ch;
rx->buf[rx->index] = ch;
if (++rx->index == rx->len)
rx->state = STATE_CHKSUM;
break;
case STATE_CHKSUM: /* Looking for the checksum */
if (ch == rx->chksum)
micro_rx_msg(micro, rx->id, rx->len, rx->buf);
rx->state = STATE_SOF;
break;
}
}
static void micro_rx_chars(struct ipaq_micro *micro)
{
u32 status, ch;
while ((status = readl(micro->base + UTSR1)) & UTSR1_RNE) {
ch = readl(micro->base + UTDR);
if (status & UTSR1_PRE)
dev_err(micro->dev, "rx: parity error\n");
else if (status & UTSR1_FRE)
dev_err(micro->dev, "rx: framing error\n");
else if (status & UTSR1_ROR)
dev_err(micro->dev, "rx: overrun error\n");
micro_process_char(micro, ch);
}
}
static void ipaq_micro_get_version(struct ipaq_micro *micro)
{
struct ipaq_micro_msg msg = {
.id = MSG_VERSION,
};
ipaq_micro_tx_msg_sync(micro, &msg);
if (msg.rx_len == 4) {
memcpy(micro->version, msg.rx_data, 4);
micro->version[4] = '\0';
} else if (msg.rx_len == 9) {
memcpy(micro->version, msg.rx_data, 4);
micro->version[4] = '\0';
/* Bytes 4-7 are "pack", byte 8 is "boot type" */
} else {
dev_err(micro->dev,
"illegal version message %d bytes\n", msg.rx_len);
}
}
static void ipaq_micro_eeprom_read(struct ipaq_micro *micro,
u8 address, u8 len, u8 *data)
{
struct ipaq_micro_msg msg = {
.id = MSG_EEPROM_READ,
};
u8 i;
for (i = 0; i < len; i++) {
msg.tx_data[0] = address + i;
msg.tx_data[1] = 1;
msg.tx_len = 2;
ipaq_micro_tx_msg_sync(micro, &msg);
memcpy(data + (i * 2), msg.rx_data, 2);
}
}
static char *ipaq_micro_str(u8 *wchar, u8 len)
{
char retstr[256];
u8 i;
for (i = 0; i < len / 2; i++)
retstr[i] = wchar[i * 2];
return kstrdup(retstr, GFP_KERNEL);
}
static u16 ipaq_micro_to_u16(u8 *data)
{
return data[1] << 8 | data[0];
}
static void __init ipaq_micro_eeprom_dump(struct ipaq_micro *micro)
{
u8 dump[256];
char *str;
ipaq_micro_eeprom_read(micro, 0, 128, dump);
str = ipaq_micro_str(dump, 10);
if (str) {
dev_info(micro->dev, "HW version %s\n", str);
kfree(str);
}
str = ipaq_micro_str(dump+10, 40);
if (str) {
dev_info(micro->dev, "serial number: %s\n", str);
/* Feed the random pool with this */
add_device_randomness(str, strlen(str));
kfree(str);
}
str = ipaq_micro_str(dump+50, 20);
if (str) {
dev_info(micro->dev, "module ID: %s\n", str);
kfree(str);
}
str = ipaq_micro_str(dump+70, 10);
if (str) {
dev_info(micro->dev, "product revision: %s\n", str);
kfree(str);
}
dev_info(micro->dev, "product ID: %u\n", ipaq_micro_to_u16(dump+80));
dev_info(micro->dev, "frame rate: %u fps\n",
ipaq_micro_to_u16(dump+82));
dev_info(micro->dev, "page mode: %u\n", ipaq_micro_to_u16(dump+84));
dev_info(micro->dev, "country ID: %u\n", ipaq_micro_to_u16(dump+86));
dev_info(micro->dev, "color display: %s\n",
ipaq_micro_to_u16(dump+88) ? "yes" : "no");
dev_info(micro->dev, "ROM size: %u MiB\n", ipaq_micro_to_u16(dump+90));
dev_info(micro->dev, "RAM size: %u KiB\n", ipaq_micro_to_u16(dump+92));
dev_info(micro->dev, "screen: %u x %u\n",
ipaq_micro_to_u16(dump+94), ipaq_micro_to_u16(dump+96));
}
static void micro_tx_chars(struct ipaq_micro *micro)
{
struct ipaq_micro_txdev *tx = µ->tx;
u32 val;
while ((tx->index < tx->len) &&
(readl(micro->base + UTSR1) & UTSR1_TNF)) {
writel(tx->buf[tx->index], micro->base + UTDR);
tx->index++;
}
/* Stop interrupts */
val = readl(micro->base + UTCR3);
val &= ~UTCR3_TIE;
writel(val, micro->base + UTCR3);
}
static void micro_reset_comm(struct ipaq_micro *micro)
{
struct ipaq_micro_rxdev *rx = µ->rx;
u32 val;
if (micro->msg)
complete(µ->msg->ack);
/* Initialize Serial channel protocol frame */
rx->state = STATE_SOF; /* Reset the state machine */
/* Set up interrupts */
writel(0x01, micro->sdlc + 0x0); /* Select UART mode */
/* Clean up CR3 */
writel(0x0, micro->base + UTCR3);
/* Format: 8N1 */
writel(UTCR0_8BitData | UTCR0_1StpBit, micro->base + UTCR0);
/* Baud rate: 115200 */
writel(0x0, micro->base + UTCR1);
writel(0x1, micro->base + UTCR2);
/* Clear SR0 */
writel(0xff, micro->base + UTSR0);
/* Enable RX int, disable TX int */
writel(UTCR3_TXE | UTCR3_RXE | UTCR3_RIE, micro->base + UTCR3);
val = readl(micro->base + UTCR3);
val &= ~UTCR3_TIE;
writel(val, micro->base + UTCR3);
}
static irqreturn_t micro_serial_isr(int irq, void *dev_id)
{
struct ipaq_micro *micro = dev_id;
struct ipaq_micro_txdev *tx = µ->tx;
u32 status;
status = readl(micro->base + UTSR0);
do {
if (status & (UTSR0_RID | UTSR0_RFS)) {
if (status & UTSR0_RID)
/* Clear the Receiver IDLE bit */
writel(UTSR0_RID, micro->base + UTSR0);
micro_rx_chars(micro);
}
/* Clear break bits */
if (status & (UTSR0_RBB | UTSR0_REB))
writel(status & (UTSR0_RBB | UTSR0_REB),
micro->base + UTSR0);
if (status & UTSR0_TFS)
micro_tx_chars(micro);
status = readl(micro->base + UTSR0);
} while (((tx->index < tx->len) && (status & UTSR0_TFS)) ||
(status & (UTSR0_RFS | UTSR0_RID)));
return IRQ_HANDLED;
}
static const struct mfd_cell micro_cells[] = {
{ .name = "ipaq-micro-backlight", },
{ .name = "ipaq-micro-battery", },
{ .name = "ipaq-micro-keys", },
{ .name = "ipaq-micro-ts", },
{ .name = "ipaq-micro-leds", },
};
static int __maybe_unused micro_resume(struct device *dev)
{
struct ipaq_micro *micro = dev_get_drvdata(dev);
micro_reset_comm(micro);
mdelay(10);
return 0;
}
static int __init micro_probe(struct platform_device *pdev)
{
struct ipaq_micro *micro;
int ret;
int irq;
micro = devm_kzalloc(&pdev->dev, sizeof(*micro), GFP_KERNEL);
if (!micro)
return -ENOMEM;
micro->dev = &pdev->dev;
micro->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(micro->base))
return PTR_ERR(micro->base);
micro->sdlc = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(micro->sdlc))
return PTR_ERR(micro->sdlc);
micro_reset_comm(micro);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -EINVAL;
ret = devm_request_irq(&pdev->dev, irq, micro_serial_isr,
IRQF_SHARED, "ipaq-micro",
micro);
if (ret) {
dev_err(&pdev->dev, "unable to grab serial port IRQ\n");
return ret;
} else
dev_info(&pdev->dev, "grabbed serial port IRQ\n");
spin_lock_init(µ->lock);
INIT_LIST_HEAD(µ->queue);
platform_set_drvdata(pdev, micro);
ret = mfd_add_devices(&pdev->dev, pdev->id, micro_cells,
ARRAY_SIZE(micro_cells), NULL, 0, NULL);
if (ret) {
dev_err(&pdev->dev, "error adding MFD cells");
return ret;
}
/* Check version */
ipaq_micro_get_version(micro);
dev_info(&pdev->dev, "Atmel micro ASIC version %s\n", micro->version);
ipaq_micro_eeprom_dump(micro);
return 0;
}
static const struct dev_pm_ops micro_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(NULL, micro_resume)
};
static struct platform_driver micro_device_driver = {
.driver = {
.name = "ipaq-h3xxx-micro",
.pm = µ_dev_pm_ops,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(micro_device_driver, micro_probe);
| linux-master | drivers/mfd/ipaq-micro.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2021 ROHM Semiconductors
*
* ROHM BD9576MUF and BD9573MUF PMIC driver
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rohm-bd957x.h>
#include <linux/mfd/rohm-generic.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/types.h>
enum {
BD957X_REGULATOR_CELL,
BD957X_WDT_CELL,
};
/*
* Due to the BD9576MUF nasty IRQ behaviour we don't always populate IRQs.
* These will be added to regulator resources only if IRQ information for the
* PMIC is populated in device-tree.
*/
static const struct resource bd9576_regulator_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD9576_INT_THERM, "bd9576-temp"),
DEFINE_RES_IRQ_NAMED(BD9576_INT_OVD, "bd9576-ovd"),
DEFINE_RES_IRQ_NAMED(BD9576_INT_UVD, "bd9576-uvd"),
};
static struct mfd_cell bd9573_mfd_cells[] = {
[BD957X_REGULATOR_CELL] = { .name = "bd9573-regulator", },
[BD957X_WDT_CELL] = { .name = "bd9576-wdt", },
};
static struct mfd_cell bd9576_mfd_cells[] = {
[BD957X_REGULATOR_CELL] = { .name = "bd9576-regulator", },
[BD957X_WDT_CELL] = { .name = "bd9576-wdt", },
};
static const struct regmap_range volatile_ranges[] = {
regmap_reg_range(BD957X_REG_SMRB_ASSERT, BD957X_REG_SMRB_ASSERT),
regmap_reg_range(BD957X_REG_PMIC_INTERNAL_STAT,
BD957X_REG_PMIC_INTERNAL_STAT),
regmap_reg_range(BD957X_REG_INT_THERM_STAT, BD957X_REG_INT_THERM_STAT),
regmap_reg_range(BD957X_REG_INT_OVP_STAT, BD957X_REG_INT_SYS_STAT),
regmap_reg_range(BD957X_REG_INT_MAIN_STAT, BD957X_REG_INT_MAIN_STAT),
};
static const struct regmap_access_table volatile_regs = {
.yes_ranges = &volatile_ranges[0],
.n_yes_ranges = ARRAY_SIZE(volatile_ranges),
};
static struct regmap_config bd957x_regmap = {
.reg_bits = 8,
.val_bits = 8,
.volatile_table = &volatile_regs,
.max_register = BD957X_MAX_REGISTER,
.cache_type = REGCACHE_RBTREE,
};
static struct regmap_irq bd9576_irqs[] = {
REGMAP_IRQ_REG(BD9576_INT_THERM, 0, BD957X_MASK_INT_MAIN_THERM),
REGMAP_IRQ_REG(BD9576_INT_OVP, 0, BD957X_MASK_INT_MAIN_OVP),
REGMAP_IRQ_REG(BD9576_INT_SCP, 0, BD957X_MASK_INT_MAIN_SCP),
REGMAP_IRQ_REG(BD9576_INT_OCP, 0, BD957X_MASK_INT_MAIN_OCP),
REGMAP_IRQ_REG(BD9576_INT_OVD, 0, BD957X_MASK_INT_MAIN_OVD),
REGMAP_IRQ_REG(BD9576_INT_UVD, 0, BD957X_MASK_INT_MAIN_UVD),
REGMAP_IRQ_REG(BD9576_INT_UVP, 0, BD957X_MASK_INT_MAIN_UVP),
REGMAP_IRQ_REG(BD9576_INT_SYS, 0, BD957X_MASK_INT_MAIN_SYS),
};
static struct regmap_irq_chip bd9576_irq_chip = {
.name = "bd9576_irq",
.irqs = &bd9576_irqs[0],
.num_irqs = ARRAY_SIZE(bd9576_irqs),
.status_base = BD957X_REG_INT_MAIN_STAT,
.mask_base = BD957X_REG_INT_MAIN_MASK,
.ack_base = BD957X_REG_INT_MAIN_STAT,
.init_ack_masked = true,
.num_regs = 1,
.irq_reg_stride = 1,
};
static int bd957x_i2c_probe(struct i2c_client *i2c)
{
int ret;
struct regmap *regmap;
struct mfd_cell *cells;
int num_cells;
unsigned long chip_type;
struct irq_domain *domain;
bool usable_irqs;
chip_type = (unsigned long)of_device_get_match_data(&i2c->dev);
switch (chip_type) {
case ROHM_CHIP_TYPE_BD9576:
cells = bd9576_mfd_cells;
num_cells = ARRAY_SIZE(bd9576_mfd_cells);
usable_irqs = !!i2c->irq;
break;
case ROHM_CHIP_TYPE_BD9573:
cells = bd9573_mfd_cells;
num_cells = ARRAY_SIZE(bd9573_mfd_cells);
/*
* BD9573 only supports fatal IRQs which we can not handle
* because SoC is going to lose the power.
*/
usable_irqs = false;
break;
default:
dev_err(&i2c->dev, "Unknown device type");
return -EINVAL;
}
regmap = devm_regmap_init_i2c(i2c, &bd957x_regmap);
if (IS_ERR(regmap))
return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
"Failed to initialize Regmap\n");
/*
* BD9576 behaves badly. It kepts IRQ line asserted for the whole
* duration of detected HW condition (like over temperature). So we
* don't require IRQ to be populated.
* If IRQ information is not given, then we mask all IRQs and do not
* provide IRQ resources to regulator driver - which then just omits
* the notifiers.
*/
if (usable_irqs) {
struct regmap_irq_chip_data *irq_data;
struct mfd_cell *regulators;
regulators = &bd9576_mfd_cells[BD957X_REGULATOR_CELL];
regulators->resources = bd9576_regulator_irqs;
regulators->num_resources = ARRAY_SIZE(bd9576_regulator_irqs);
ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
IRQF_ONESHOT, 0,
&bd9576_irq_chip, &irq_data);
if (ret)
return dev_err_probe(&i2c->dev, ret,
"Failed to add IRQ chip\n");
domain = regmap_irq_get_domain(irq_data);
} else {
ret = regmap_update_bits(regmap, BD957X_REG_INT_MAIN_MASK,
BD957X_MASK_INT_ALL,
BD957X_MASK_INT_ALL);
if (ret)
return ret;
domain = NULL;
}
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, cells,
num_cells, NULL, 0, domain);
if (ret)
dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
return ret;
}
static const struct of_device_id bd957x_of_match[] = {
{ .compatible = "rohm,bd9576", .data = (void *)ROHM_CHIP_TYPE_BD9576, },
{ .compatible = "rohm,bd9573", .data = (void *)ROHM_CHIP_TYPE_BD9573, },
{ },
};
MODULE_DEVICE_TABLE(of, bd957x_of_match);
static struct i2c_driver bd957x_drv = {
.driver = {
.name = "rohm-bd957x",
.of_match_table = bd957x_of_match,
},
.probe = bd957x_i2c_probe,
};
module_i2c_driver(bd957x_drv);
MODULE_AUTHOR("Matti Vaittinen <[email protected]>");
MODULE_DESCRIPTION("ROHM BD9576MUF and BD9573MUF Power Management IC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/rohm-bd9576.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <[email protected]>
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdesc.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/mfd/imx25-tsadc.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
static struct regmap_config mx25_tsadc_regmap_config = {
.fast_io = true,
.max_register = 8,
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static void mx25_tsadc_irq_handler(struct irq_desc *desc)
{
struct mx25_tsadc *tsadc = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
u32 status;
chained_irq_enter(chip, desc);
regmap_read(tsadc->regs, MX25_TSC_TGSR, &status);
if (status & MX25_TGSR_GCQ_INT)
generic_handle_domain_irq(tsadc->domain, 1);
if (status & MX25_TGSR_TCQ_INT)
generic_handle_domain_irq(tsadc->domain, 0);
chained_irq_exit(chip, desc);
}
static int mx25_tsadc_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct mx25_tsadc *tsadc = d->host_data;
irq_set_chip_data(irq, tsadc);
irq_set_chip_and_handler(irq, &dummy_irq_chip,
handle_level_irq);
irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE);
return 0;
}
static const struct irq_domain_ops mx25_tsadc_domain_ops = {
.map = mx25_tsadc_domain_map,
.xlate = irq_domain_xlate_onecell,
};
static int mx25_tsadc_setup_irq(struct platform_device *pdev,
struct mx25_tsadc *tsadc)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
int irq;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_domain_ops,
tsadc);
if (!tsadc->domain) {
dev_err(dev, "Failed to add irq domain\n");
return -ENOMEM;
}
irq_set_chained_handler_and_data(irq, mx25_tsadc_irq_handler, tsadc);
return 0;
}
static int mx25_tsadc_unset_irq(struct platform_device *pdev)
{
struct mx25_tsadc *tsadc = platform_get_drvdata(pdev);
int irq = platform_get_irq(pdev, 0);
if (irq >= 0) {
irq_set_chained_handler_and_data(irq, NULL, NULL);
irq_domain_remove(tsadc->domain);
}
return 0;
}
static void mx25_tsadc_setup_clk(struct platform_device *pdev,
struct mx25_tsadc *tsadc)
{
unsigned clk_div;
/*
* According to the datasheet the ADC clock should never
* exceed 1,75 MHz. Base clock is the IPG and the ADC unit uses
* a funny clock divider. To keep the ADC conversion time constant
* adapt the ADC internal clock divider to the IPG clock rate.
*/
dev_dbg(&pdev->dev, "Found master clock at %lu Hz\n",
clk_get_rate(tsadc->clk));
clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000);
dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div);
/* adc clock = IPG clock / (2 * div + 2) */
clk_div -= 2;
clk_div /= 2;
/*
* the ADC clock divider changes its behaviour when values below 4
* are used: it is fixed to "/ 10" in this case
*/
clk_div = max_t(unsigned, 4, clk_div);
dev_dbg(&pdev->dev, "Resulting ADC conversion clock at %lu Hz\n",
clk_get_rate(tsadc->clk) / (2 * clk_div + 2));
regmap_update_bits(tsadc->regs, MX25_TSC_TGCR,
MX25_TGCR_ADCCLKCFG(0x1f),
MX25_TGCR_ADCCLKCFG(clk_div));
}
static int mx25_tsadc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mx25_tsadc *tsadc;
int ret;
void __iomem *iomem;
tsadc = devm_kzalloc(dev, sizeof(*tsadc), GFP_KERNEL);
if (!tsadc)
return -ENOMEM;
iomem = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(iomem))
return PTR_ERR(iomem);
tsadc->regs = devm_regmap_init_mmio(dev, iomem,
&mx25_tsadc_regmap_config);
if (IS_ERR(tsadc->regs)) {
dev_err(dev, "Failed to initialize regmap\n");
return PTR_ERR(tsadc->regs);
}
tsadc->clk = devm_clk_get(dev, "ipg");
if (IS_ERR(tsadc->clk)) {
dev_err(dev, "Failed to get ipg clock\n");
return PTR_ERR(tsadc->clk);
}
/* setup clock according to the datasheet */
mx25_tsadc_setup_clk(pdev, tsadc);
/* Enable clock and reset the component */
regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_CLK_EN,
MX25_TGCR_CLK_EN);
regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_TSC_RST,
MX25_TGCR_TSC_RST);
/* Setup powersaving mode, but enable internal reference voltage */
regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_POWERMODE_MASK,
MX25_TGCR_POWERMODE_SAVE);
regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_INTREFEN,
MX25_TGCR_INTREFEN);
ret = mx25_tsadc_setup_irq(pdev, tsadc);
if (ret)
return ret;
platform_set_drvdata(pdev, tsadc);
ret = devm_of_platform_populate(dev);
if (ret)
goto err_irq;
return 0;
err_irq:
mx25_tsadc_unset_irq(pdev);
return ret;
}
static int mx25_tsadc_remove(struct platform_device *pdev)
{
mx25_tsadc_unset_irq(pdev);
return 0;
}
static const struct of_device_id mx25_tsadc_ids[] = {
{ .compatible = "fsl,imx25-tsadc" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, mx25_tsadc_ids);
static struct platform_driver mx25_tsadc_driver = {
.driver = {
.name = "mx25-tsadc",
.of_match_table = mx25_tsadc_ids,
},
.probe = mx25_tsadc_probe,
.remove = mx25_tsadc_remove,
};
module_platform_driver(mx25_tsadc_driver);
MODULE_DESCRIPTION("MFD for ADC/TSC for Freescale mx25");
MODULE_AUTHOR("Markus Pargmann <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mx25-tsadc");
| linux-master | drivers/mfd/fsl-imx25-tsadc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2004 Texas Instruments, Inc.
*
* Some parts based tps65010.c:
* Copyright (C) 2004 Texas Instruments and
* Copyright (C) 2004-2005 David Brownell
*
* Some parts based on tlv320aic24.c:
* Copyright (C) by Kai Svahn <[email protected]>
*
* Changes for interrupt handling and clean-up by
* Tony Lindgren <[email protected]> and Imre Deak <[email protected]>
* Cleanup and generalized support for voltage setting by
* Juha Yrjola
* Added support for controlling VCORE and regulator sleep states,
* Amit Kucheria <[email protected]>
* Copyright (C) 2005, 2006 Nokia Corporation
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/slab.h>
#include <linux/mfd/menelaus.h>
#include <linux/gpio.h>
#include <asm/mach/irq.h>
#define DRIVER_NAME "menelaus"
#define MENELAUS_I2C_ADDRESS 0x72
#define MENELAUS_REV 0x01
#define MENELAUS_VCORE_CTRL1 0x02
#define MENELAUS_VCORE_CTRL2 0x03
#define MENELAUS_VCORE_CTRL3 0x04
#define MENELAUS_VCORE_CTRL4 0x05
#define MENELAUS_VCORE_CTRL5 0x06
#define MENELAUS_DCDC_CTRL1 0x07
#define MENELAUS_DCDC_CTRL2 0x08
#define MENELAUS_DCDC_CTRL3 0x09
#define MENELAUS_LDO_CTRL1 0x0A
#define MENELAUS_LDO_CTRL2 0x0B
#define MENELAUS_LDO_CTRL3 0x0C
#define MENELAUS_LDO_CTRL4 0x0D
#define MENELAUS_LDO_CTRL5 0x0E
#define MENELAUS_LDO_CTRL6 0x0F
#define MENELAUS_LDO_CTRL7 0x10
#define MENELAUS_LDO_CTRL8 0x11
#define MENELAUS_SLEEP_CTRL1 0x12
#define MENELAUS_SLEEP_CTRL2 0x13
#define MENELAUS_DEVICE_OFF 0x14
#define MENELAUS_OSC_CTRL 0x15
#define MENELAUS_DETECT_CTRL 0x16
#define MENELAUS_INT_MASK1 0x17
#define MENELAUS_INT_MASK2 0x18
#define MENELAUS_INT_STATUS1 0x19
#define MENELAUS_INT_STATUS2 0x1A
#define MENELAUS_INT_ACK1 0x1B
#define MENELAUS_INT_ACK2 0x1C
#define MENELAUS_GPIO_CTRL 0x1D
#define MENELAUS_GPIO_IN 0x1E
#define MENELAUS_GPIO_OUT 0x1F
#define MENELAUS_BBSMS 0x20
#define MENELAUS_RTC_CTRL 0x21
#define MENELAUS_RTC_UPDATE 0x22
#define MENELAUS_RTC_SEC 0x23
#define MENELAUS_RTC_MIN 0x24
#define MENELAUS_RTC_HR 0x25
#define MENELAUS_RTC_DAY 0x26
#define MENELAUS_RTC_MON 0x27
#define MENELAUS_RTC_YR 0x28
#define MENELAUS_RTC_WKDAY 0x29
#define MENELAUS_RTC_AL_SEC 0x2A
#define MENELAUS_RTC_AL_MIN 0x2B
#define MENELAUS_RTC_AL_HR 0x2C
#define MENELAUS_RTC_AL_DAY 0x2D
#define MENELAUS_RTC_AL_MON 0x2E
#define MENELAUS_RTC_AL_YR 0x2F
#define MENELAUS_RTC_COMP_MSB 0x30
#define MENELAUS_RTC_COMP_LSB 0x31
#define MENELAUS_S1_PULL_EN 0x32
#define MENELAUS_S1_PULL_DIR 0x33
#define MENELAUS_S2_PULL_EN 0x34
#define MENELAUS_S2_PULL_DIR 0x35
#define MENELAUS_MCT_CTRL1 0x36
#define MENELAUS_MCT_CTRL2 0x37
#define MENELAUS_MCT_CTRL3 0x38
#define MENELAUS_MCT_PIN_ST 0x39
#define MENELAUS_DEBOUNCE1 0x3A
#define IH_MENELAUS_IRQS 12
#define MENELAUS_MMC_S1CD_IRQ 0 /* MMC slot 1 card change */
#define MENELAUS_MMC_S2CD_IRQ 1 /* MMC slot 2 card change */
#define MENELAUS_MMC_S1D1_IRQ 2 /* MMC DAT1 low in slot 1 */
#define MENELAUS_MMC_S2D1_IRQ 3 /* MMC DAT1 low in slot 2 */
#define MENELAUS_LOWBAT_IRQ 4 /* Low battery */
#define MENELAUS_HOTDIE_IRQ 5 /* Hot die detect */
#define MENELAUS_UVLO_IRQ 6 /* UVLO detect */
#define MENELAUS_TSHUT_IRQ 7 /* Thermal shutdown */
#define MENELAUS_RTCTMR_IRQ 8 /* RTC timer */
#define MENELAUS_RTCALM_IRQ 9 /* RTC alarm */
#define MENELAUS_RTCERR_IRQ 10 /* RTC error */
#define MENELAUS_PSHBTN_IRQ 11 /* Push button */
#define MENELAUS_RESERVED12_IRQ 12 /* Reserved */
#define MENELAUS_RESERVED13_IRQ 13 /* Reserved */
#define MENELAUS_RESERVED14_IRQ 14 /* Reserved */
#define MENELAUS_RESERVED15_IRQ 15 /* Reserved */
/* VCORE_CTRL1 register */
#define VCORE_CTRL1_BYP_COMP (1 << 5)
#define VCORE_CTRL1_HW_NSW (1 << 7)
/* GPIO_CTRL register */
#define GPIO_CTRL_SLOTSELEN (1 << 5)
#define GPIO_CTRL_SLPCTLEN (1 << 6)
#define GPIO1_DIR_INPUT (1 << 0)
#define GPIO2_DIR_INPUT (1 << 1)
#define GPIO3_DIR_INPUT (1 << 2)
/* MCT_CTRL1 register */
#define MCT_CTRL1_S1_CMD_OD (1 << 2)
#define MCT_CTRL1_S2_CMD_OD (1 << 3)
/* MCT_CTRL2 register */
#define MCT_CTRL2_VS2_SEL_D0 (1 << 0)
#define MCT_CTRL2_VS2_SEL_D1 (1 << 1)
#define MCT_CTRL2_S1CD_BUFEN (1 << 4)
#define MCT_CTRL2_S2CD_BUFEN (1 << 5)
#define MCT_CTRL2_S1CD_DBEN (1 << 6)
#define MCT_CTRL2_S2CD_BEN (1 << 7)
/* MCT_CTRL3 register */
#define MCT_CTRL3_SLOT1_EN (1 << 0)
#define MCT_CTRL3_SLOT2_EN (1 << 1)
#define MCT_CTRL3_S1_AUTO_EN (1 << 2)
#define MCT_CTRL3_S2_AUTO_EN (1 << 3)
/* MCT_PIN_ST register */
#define MCT_PIN_ST_S1_CD_ST (1 << 0)
#define MCT_PIN_ST_S2_CD_ST (1 << 1)
static void menelaus_work(struct work_struct *_menelaus);
struct menelaus_chip {
struct mutex lock;
struct i2c_client *client;
struct work_struct work;
#ifdef CONFIG_RTC_DRV_TWL92330
struct rtc_device *rtc;
u8 rtc_control;
unsigned uie:1;
#endif
unsigned vcore_hw_mode:1;
u8 mask1, mask2;
void (*handlers[16])(struct menelaus_chip *);
void (*mmc_callback)(void *data, u8 mask);
void *mmc_callback_data;
};
static struct menelaus_chip *the_menelaus;
static int menelaus_write_reg(int reg, u8 value)
{
int val = i2c_smbus_write_byte_data(the_menelaus->client, reg, value);
if (val < 0) {
pr_err(DRIVER_NAME ": write error");
return val;
}
return 0;
}
static int menelaus_read_reg(int reg)
{
int val = i2c_smbus_read_byte_data(the_menelaus->client, reg);
if (val < 0)
pr_err(DRIVER_NAME ": read error");
return val;
}
static int menelaus_enable_irq(int irq)
{
if (irq > 7) {
irq -= 8;
the_menelaus->mask2 &= ~(1 << irq);
return menelaus_write_reg(MENELAUS_INT_MASK2,
the_menelaus->mask2);
} else {
the_menelaus->mask1 &= ~(1 << irq);
return menelaus_write_reg(MENELAUS_INT_MASK1,
the_menelaus->mask1);
}
}
static int menelaus_disable_irq(int irq)
{
if (irq > 7) {
irq -= 8;
the_menelaus->mask2 |= (1 << irq);
return menelaus_write_reg(MENELAUS_INT_MASK2,
the_menelaus->mask2);
} else {
the_menelaus->mask1 |= (1 << irq);
return menelaus_write_reg(MENELAUS_INT_MASK1,
the_menelaus->mask1);
}
}
static int menelaus_ack_irq(int irq)
{
if (irq > 7)
return menelaus_write_reg(MENELAUS_INT_ACK2, 1 << (irq - 8));
else
return menelaus_write_reg(MENELAUS_INT_ACK1, 1 << irq);
}
/* Adds a handler for an interrupt. Does not run in interrupt context */
static int menelaus_add_irq_work(int irq,
void (*handler)(struct menelaus_chip *))
{
int ret = 0;
mutex_lock(&the_menelaus->lock);
the_menelaus->handlers[irq] = handler;
ret = menelaus_enable_irq(irq);
mutex_unlock(&the_menelaus->lock);
return ret;
}
/* Removes handler for an interrupt */
static int menelaus_remove_irq_work(int irq)
{
int ret = 0;
mutex_lock(&the_menelaus->lock);
ret = menelaus_disable_irq(irq);
the_menelaus->handlers[irq] = NULL;
mutex_unlock(&the_menelaus->lock);
return ret;
}
/*
* Gets scheduled when a card detect interrupt happens. Note that in some cases
* this line is wired to card cover switch rather than the card detect switch
* in each slot. In this case the cards are not seen by menelaus.
* FIXME: Add handling for D1 too
*/
static void menelaus_mmc_cd_work(struct menelaus_chip *menelaus_hw)
{
int reg;
unsigned char card_mask = 0;
reg = menelaus_read_reg(MENELAUS_MCT_PIN_ST);
if (reg < 0)
return;
if (!(reg & 0x1))
card_mask |= MCT_PIN_ST_S1_CD_ST;
if (!(reg & 0x2))
card_mask |= MCT_PIN_ST_S2_CD_ST;
if (menelaus_hw->mmc_callback)
menelaus_hw->mmc_callback(menelaus_hw->mmc_callback_data,
card_mask);
}
/*
* Toggles the MMC slots between open-drain and push-pull mode.
*/
int menelaus_set_mmc_opendrain(int slot, int enable)
{
int ret, val;
if (slot != 1 && slot != 2)
return -EINVAL;
mutex_lock(&the_menelaus->lock);
ret = menelaus_read_reg(MENELAUS_MCT_CTRL1);
if (ret < 0) {
mutex_unlock(&the_menelaus->lock);
return ret;
}
val = ret;
if (slot == 1) {
if (enable)
val |= MCT_CTRL1_S1_CMD_OD;
else
val &= ~MCT_CTRL1_S1_CMD_OD;
} else {
if (enable)
val |= MCT_CTRL1_S2_CMD_OD;
else
val &= ~MCT_CTRL1_S2_CMD_OD;
}
ret = menelaus_write_reg(MENELAUS_MCT_CTRL1, val);
mutex_unlock(&the_menelaus->lock);
return ret;
}
EXPORT_SYMBOL(menelaus_set_mmc_opendrain);
int menelaus_set_slot_sel(int enable)
{
int ret;
mutex_lock(&the_menelaus->lock);
ret = menelaus_read_reg(MENELAUS_GPIO_CTRL);
if (ret < 0)
goto out;
ret |= GPIO2_DIR_INPUT;
if (enable)
ret |= GPIO_CTRL_SLOTSELEN;
else
ret &= ~GPIO_CTRL_SLOTSELEN;
ret = menelaus_write_reg(MENELAUS_GPIO_CTRL, ret);
out:
mutex_unlock(&the_menelaus->lock);
return ret;
}
EXPORT_SYMBOL(menelaus_set_slot_sel);
int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_en)
{
int ret, val;
if (slot != 1 && slot != 2)
return -EINVAL;
if (power >= 3)
return -EINVAL;
mutex_lock(&the_menelaus->lock);
ret = menelaus_read_reg(MENELAUS_MCT_CTRL2);
if (ret < 0)
goto out;
val = ret;
if (slot == 1) {
if (cd_en)
val |= MCT_CTRL2_S1CD_BUFEN | MCT_CTRL2_S1CD_DBEN;
else
val &= ~(MCT_CTRL2_S1CD_BUFEN | MCT_CTRL2_S1CD_DBEN);
} else {
if (cd_en)
val |= MCT_CTRL2_S2CD_BUFEN | MCT_CTRL2_S2CD_BEN;
else
val &= ~(MCT_CTRL2_S2CD_BUFEN | MCT_CTRL2_S2CD_BEN);
}
ret = menelaus_write_reg(MENELAUS_MCT_CTRL2, val);
if (ret < 0)
goto out;
ret = menelaus_read_reg(MENELAUS_MCT_CTRL3);
if (ret < 0)
goto out;
val = ret;
if (slot == 1) {
if (enable)
val |= MCT_CTRL3_SLOT1_EN;
else
val &= ~MCT_CTRL3_SLOT1_EN;
} else {
int b;
if (enable)
val |= MCT_CTRL3_SLOT2_EN;
else
val &= ~MCT_CTRL3_SLOT2_EN;
b = menelaus_read_reg(MENELAUS_MCT_CTRL2);
b &= ~(MCT_CTRL2_VS2_SEL_D0 | MCT_CTRL2_VS2_SEL_D1);
b |= power;
ret = menelaus_write_reg(MENELAUS_MCT_CTRL2, b);
if (ret < 0)
goto out;
}
/* Disable autonomous shutdown */
val &= ~(MCT_CTRL3_S1_AUTO_EN | MCT_CTRL3_S2_AUTO_EN);
ret = menelaus_write_reg(MENELAUS_MCT_CTRL3, val);
out:
mutex_unlock(&the_menelaus->lock);
return ret;
}
EXPORT_SYMBOL(menelaus_set_mmc_slot);
int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
void *data)
{
int ret = 0;
the_menelaus->mmc_callback_data = data;
the_menelaus->mmc_callback = callback;
ret = menelaus_add_irq_work(MENELAUS_MMC_S1CD_IRQ,
menelaus_mmc_cd_work);
if (ret < 0)
return ret;
ret = menelaus_add_irq_work(MENELAUS_MMC_S2CD_IRQ,
menelaus_mmc_cd_work);
if (ret < 0)
return ret;
ret = menelaus_add_irq_work(MENELAUS_MMC_S1D1_IRQ,
menelaus_mmc_cd_work);
if (ret < 0)
return ret;
ret = menelaus_add_irq_work(MENELAUS_MMC_S2D1_IRQ,
menelaus_mmc_cd_work);
return ret;
}
EXPORT_SYMBOL(menelaus_register_mmc_callback);
void menelaus_unregister_mmc_callback(void)
{
menelaus_remove_irq_work(MENELAUS_MMC_S1CD_IRQ);
menelaus_remove_irq_work(MENELAUS_MMC_S2CD_IRQ);
menelaus_remove_irq_work(MENELAUS_MMC_S1D1_IRQ);
menelaus_remove_irq_work(MENELAUS_MMC_S2D1_IRQ);
the_menelaus->mmc_callback = NULL;
the_menelaus->mmc_callback_data = NULL;
}
EXPORT_SYMBOL(menelaus_unregister_mmc_callback);
struct menelaus_vtg {
const char *name;
u8 vtg_reg;
u8 vtg_shift;
u8 vtg_bits;
u8 mode_reg;
};
struct menelaus_vtg_value {
u16 vtg;
u16 val;
};
static int menelaus_set_voltage(const struct menelaus_vtg *vtg, int mV,
int vtg_val, int mode)
{
int val, ret;
struct i2c_client *c = the_menelaus->client;
mutex_lock(&the_menelaus->lock);
ret = menelaus_read_reg(vtg->vtg_reg);
if (ret < 0)
goto out;
val = ret & ~(((1 << vtg->vtg_bits) - 1) << vtg->vtg_shift);
val |= vtg_val << vtg->vtg_shift;
dev_dbg(&c->dev, "Setting voltage '%s'"
"to %d mV (reg 0x%02x, val 0x%02x)\n",
vtg->name, mV, vtg->vtg_reg, val);
ret = menelaus_write_reg(vtg->vtg_reg, val);
if (ret < 0)
goto out;
ret = menelaus_write_reg(vtg->mode_reg, mode);
out:
mutex_unlock(&the_menelaus->lock);
if (ret == 0) {
/* Wait for voltage to stabilize */
msleep(1);
}
return ret;
}
static int menelaus_get_vtg_value(int vtg, const struct menelaus_vtg_value *tbl,
int n)
{
int i;
for (i = 0; i < n; i++, tbl++)
if (tbl->vtg == vtg)
return tbl->val;
return -EINVAL;
}
/*
* Vcore can be programmed in two ways:
* SW-controlled: Required voltage is programmed into VCORE_CTRL1
* HW-controlled: Required range (roof-floor) is programmed into VCORE_CTRL3
* and VCORE_CTRL4
*
* Call correct 'set' function accordingly
*/
static const struct menelaus_vtg_value vcore_values[] = {
{ 1000, 0 },
{ 1025, 1 },
{ 1050, 2 },
{ 1075, 3 },
{ 1100, 4 },
{ 1125, 5 },
{ 1150, 6 },
{ 1175, 7 },
{ 1200, 8 },
{ 1225, 9 },
{ 1250, 10 },
{ 1275, 11 },
{ 1300, 12 },
{ 1325, 13 },
{ 1350, 14 },
{ 1375, 15 },
{ 1400, 16 },
{ 1425, 17 },
{ 1450, 18 },
};
int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV)
{
int fval, rval, val, ret;
struct i2c_client *c = the_menelaus->client;
rval = menelaus_get_vtg_value(roof_mV, vcore_values,
ARRAY_SIZE(vcore_values));
if (rval < 0)
return -EINVAL;
fval = menelaus_get_vtg_value(floor_mV, vcore_values,
ARRAY_SIZE(vcore_values));
if (fval < 0)
return -EINVAL;
dev_dbg(&c->dev, "Setting VCORE FLOOR to %d mV and ROOF to %d mV\n",
floor_mV, roof_mV);
mutex_lock(&the_menelaus->lock);
ret = menelaus_write_reg(MENELAUS_VCORE_CTRL3, fval);
if (ret < 0)
goto out;
ret = menelaus_write_reg(MENELAUS_VCORE_CTRL4, rval);
if (ret < 0)
goto out;
if (!the_menelaus->vcore_hw_mode) {
val = menelaus_read_reg(MENELAUS_VCORE_CTRL1);
/* HW mode, turn OFF byte comparator */
val |= (VCORE_CTRL1_HW_NSW | VCORE_CTRL1_BYP_COMP);
ret = menelaus_write_reg(MENELAUS_VCORE_CTRL1, val);
the_menelaus->vcore_hw_mode = 1;
}
msleep(1);
out:
mutex_unlock(&the_menelaus->lock);
return ret;
}
static const struct menelaus_vtg vmem_vtg = {
.name = "VMEM",
.vtg_reg = MENELAUS_LDO_CTRL1,
.vtg_shift = 0,
.vtg_bits = 2,
.mode_reg = MENELAUS_LDO_CTRL3,
};
static const struct menelaus_vtg_value vmem_values[] = {
{ 1500, 0 },
{ 1800, 1 },
{ 1900, 2 },
{ 2500, 3 },
};
int menelaus_set_vmem(unsigned int mV)
{
int val;
if (mV == 0)
return menelaus_set_voltage(&vmem_vtg, 0, 0, 0);
val = menelaus_get_vtg_value(mV, vmem_values, ARRAY_SIZE(vmem_values));
if (val < 0)
return -EINVAL;
return menelaus_set_voltage(&vmem_vtg, mV, val, 0x02);
}
EXPORT_SYMBOL(menelaus_set_vmem);
static const struct menelaus_vtg vio_vtg = {
.name = "VIO",
.vtg_reg = MENELAUS_LDO_CTRL1,
.vtg_shift = 2,
.vtg_bits = 2,
.mode_reg = MENELAUS_LDO_CTRL4,
};
static const struct menelaus_vtg_value vio_values[] = {
{ 1500, 0 },
{ 1800, 1 },
{ 2500, 2 },
{ 2800, 3 },
};
int menelaus_set_vio(unsigned int mV)
{
int val;
if (mV == 0)
return menelaus_set_voltage(&vio_vtg, 0, 0, 0);
val = menelaus_get_vtg_value(mV, vio_values, ARRAY_SIZE(vio_values));
if (val < 0)
return -EINVAL;
return menelaus_set_voltage(&vio_vtg, mV, val, 0x02);
}
EXPORT_SYMBOL(menelaus_set_vio);
static const struct menelaus_vtg_value vdcdc_values[] = {
{ 1500, 0 },
{ 1800, 1 },
{ 2000, 2 },
{ 2200, 3 },
{ 2400, 4 },
{ 2800, 5 },
{ 3000, 6 },
{ 3300, 7 },
};
static const struct menelaus_vtg vdcdc2_vtg = {
.name = "VDCDC2",
.vtg_reg = MENELAUS_DCDC_CTRL1,
.vtg_shift = 0,
.vtg_bits = 3,
.mode_reg = MENELAUS_DCDC_CTRL2,
};
static const struct menelaus_vtg vdcdc3_vtg = {
.name = "VDCDC3",
.vtg_reg = MENELAUS_DCDC_CTRL1,
.vtg_shift = 3,
.vtg_bits = 3,
.mode_reg = MENELAUS_DCDC_CTRL3,
};
int menelaus_set_vdcdc(int dcdc, unsigned int mV)
{
const struct menelaus_vtg *vtg;
int val;
if (dcdc != 2 && dcdc != 3)
return -EINVAL;
if (dcdc == 2)
vtg = &vdcdc2_vtg;
else
vtg = &vdcdc3_vtg;
if (mV == 0)
return menelaus_set_voltage(vtg, 0, 0, 0);
val = menelaus_get_vtg_value(mV, vdcdc_values,
ARRAY_SIZE(vdcdc_values));
if (val < 0)
return -EINVAL;
return menelaus_set_voltage(vtg, mV, val, 0x03);
}
static const struct menelaus_vtg_value vmmc_values[] = {
{ 1850, 0 },
{ 2800, 1 },
{ 3000, 2 },
{ 3100, 3 },
};
static const struct menelaus_vtg vmmc_vtg = {
.name = "VMMC",
.vtg_reg = MENELAUS_LDO_CTRL1,
.vtg_shift = 6,
.vtg_bits = 2,
.mode_reg = MENELAUS_LDO_CTRL7,
};
int menelaus_set_vmmc(unsigned int mV)
{
int val;
if (mV == 0)
return menelaus_set_voltage(&vmmc_vtg, 0, 0, 0);
val = menelaus_get_vtg_value(mV, vmmc_values, ARRAY_SIZE(vmmc_values));
if (val < 0)
return -EINVAL;
return menelaus_set_voltage(&vmmc_vtg, mV, val, 0x02);
}
EXPORT_SYMBOL(menelaus_set_vmmc);
static const struct menelaus_vtg_value vaux_values[] = {
{ 1500, 0 },
{ 1800, 1 },
{ 2500, 2 },
{ 2800, 3 },
};
static const struct menelaus_vtg vaux_vtg = {
.name = "VAUX",
.vtg_reg = MENELAUS_LDO_CTRL1,
.vtg_shift = 4,
.vtg_bits = 2,
.mode_reg = MENELAUS_LDO_CTRL6,
};
int menelaus_set_vaux(unsigned int mV)
{
int val;
if (mV == 0)
return menelaus_set_voltage(&vaux_vtg, 0, 0, 0);
val = menelaus_get_vtg_value(mV, vaux_values, ARRAY_SIZE(vaux_values));
if (val < 0)
return -EINVAL;
return menelaus_set_voltage(&vaux_vtg, mV, val, 0x02);
}
EXPORT_SYMBOL(menelaus_set_vaux);
int menelaus_get_slot_pin_states(void)
{
return menelaus_read_reg(MENELAUS_MCT_PIN_ST);
}
EXPORT_SYMBOL(menelaus_get_slot_pin_states);
int menelaus_set_regulator_sleep(int enable, u32 val)
{
int t, ret;
struct i2c_client *c = the_menelaus->client;
mutex_lock(&the_menelaus->lock);
ret = menelaus_write_reg(MENELAUS_SLEEP_CTRL2, val);
if (ret < 0)
goto out;
dev_dbg(&c->dev, "regulator sleep configuration: %02x\n", val);
ret = menelaus_read_reg(MENELAUS_GPIO_CTRL);
if (ret < 0)
goto out;
t = (GPIO_CTRL_SLPCTLEN | GPIO3_DIR_INPUT);
if (enable)
ret |= t;
else
ret &= ~t;
ret = menelaus_write_reg(MENELAUS_GPIO_CTRL, ret);
out:
mutex_unlock(&the_menelaus->lock);
return ret;
}
/*-----------------------------------------------------------------------*/
/* Handles Menelaus interrupts. Does not run in interrupt context */
static void menelaus_work(struct work_struct *_menelaus)
{
struct menelaus_chip *menelaus =
container_of(_menelaus, struct menelaus_chip, work);
void (*handler)(struct menelaus_chip *menelaus);
while (1) {
unsigned isr;
isr = (menelaus_read_reg(MENELAUS_INT_STATUS2)
& ~menelaus->mask2) << 8;
isr |= menelaus_read_reg(MENELAUS_INT_STATUS1)
& ~menelaus->mask1;
if (!isr)
break;
while (isr) {
int irq = fls(isr) - 1;
isr &= ~(1 << irq);
mutex_lock(&menelaus->lock);
menelaus_disable_irq(irq);
menelaus_ack_irq(irq);
handler = menelaus->handlers[irq];
if (handler)
handler(menelaus);
menelaus_enable_irq(irq);
mutex_unlock(&menelaus->lock);
}
}
enable_irq(menelaus->client->irq);
}
/*
* We cannot use I2C in interrupt context, so we just schedule work.
*/
static irqreturn_t menelaus_irq(int irq, void *_menelaus)
{
struct menelaus_chip *menelaus = _menelaus;
disable_irq_nosync(irq);
(void)schedule_work(&menelaus->work);
return IRQ_HANDLED;
}
/*-----------------------------------------------------------------------*/
/*
* The RTC needs to be set once, then it runs on backup battery power.
* It supports alarms, including system wake alarms (from some modes);
* and 1/second IRQs if requested.
*/
#ifdef CONFIG_RTC_DRV_TWL92330
#define RTC_CTRL_RTC_EN (1 << 0)
#define RTC_CTRL_AL_EN (1 << 1)
#define RTC_CTRL_MODE12 (1 << 2)
#define RTC_CTRL_EVERY_MASK (3 << 3)
#define RTC_CTRL_EVERY_SEC (0 << 3)
#define RTC_CTRL_EVERY_MIN (1 << 3)
#define RTC_CTRL_EVERY_HR (2 << 3)
#define RTC_CTRL_EVERY_DAY (3 << 3)
#define RTC_UPDATE_EVERY 0x08
#define RTC_HR_PM (1 << 7)
static void menelaus_to_time(char *regs, struct rtc_time *t)
{
t->tm_sec = bcd2bin(regs[0]);
t->tm_min = bcd2bin(regs[1]);
if (the_menelaus->rtc_control & RTC_CTRL_MODE12) {
t->tm_hour = bcd2bin(regs[2] & 0x1f) - 1;
if (regs[2] & RTC_HR_PM)
t->tm_hour += 12;
} else
t->tm_hour = bcd2bin(regs[2] & 0x3f);
t->tm_mday = bcd2bin(regs[3]);
t->tm_mon = bcd2bin(regs[4]) - 1;
t->tm_year = bcd2bin(regs[5]) + 100;
}
static int time_to_menelaus(struct rtc_time *t, int regnum)
{
int hour, status;
status = menelaus_write_reg(regnum++, bin2bcd(t->tm_sec));
if (status < 0)
goto fail;
status = menelaus_write_reg(regnum++, bin2bcd(t->tm_min));
if (status < 0)
goto fail;
if (the_menelaus->rtc_control & RTC_CTRL_MODE12) {
hour = t->tm_hour + 1;
if (hour > 12)
hour = RTC_HR_PM | bin2bcd(hour - 12);
else
hour = bin2bcd(hour);
} else
hour = bin2bcd(t->tm_hour);
status = menelaus_write_reg(regnum++, hour);
if (status < 0)
goto fail;
status = menelaus_write_reg(regnum++, bin2bcd(t->tm_mday));
if (status < 0)
goto fail;
status = menelaus_write_reg(regnum++, bin2bcd(t->tm_mon + 1));
if (status < 0)
goto fail;
status = menelaus_write_reg(regnum++, bin2bcd(t->tm_year - 100));
if (status < 0)
goto fail;
return 0;
fail:
dev_err(&the_menelaus->client->dev, "rtc write reg %02x, err %d\n",
--regnum, status);
return status;
}
static int menelaus_read_time(struct device *dev, struct rtc_time *t)
{
struct i2c_msg msg[2];
char regs[7];
int status;
/* block read date and time registers */
regs[0] = MENELAUS_RTC_SEC;
msg[0].addr = MENELAUS_I2C_ADDRESS;
msg[0].flags = 0;
msg[0].len = 1;
msg[0].buf = regs;
msg[1].addr = MENELAUS_I2C_ADDRESS;
msg[1].flags = I2C_M_RD;
msg[1].len = sizeof(regs);
msg[1].buf = regs;
status = i2c_transfer(the_menelaus->client->adapter, msg, 2);
if (status != 2) {
dev_err(dev, "%s error %d\n", "read", status);
return -EIO;
}
menelaus_to_time(regs, t);
t->tm_wday = bcd2bin(regs[6]);
return 0;
}
static int menelaus_set_time(struct device *dev, struct rtc_time *t)
{
int status;
/* write date and time registers */
status = time_to_menelaus(t, MENELAUS_RTC_SEC);
if (status < 0)
return status;
status = menelaus_write_reg(MENELAUS_RTC_WKDAY, bin2bcd(t->tm_wday));
if (status < 0) {
dev_err(&the_menelaus->client->dev, "rtc write reg %02x "
"err %d\n", MENELAUS_RTC_WKDAY, status);
return status;
}
/* now commit the write */
status = menelaus_write_reg(MENELAUS_RTC_UPDATE, RTC_UPDATE_EVERY);
if (status < 0)
dev_err(&the_menelaus->client->dev, "rtc commit time, err %d\n",
status);
return 0;
}
static int menelaus_read_alarm(struct device *dev, struct rtc_wkalrm *w)
{
struct i2c_msg msg[2];
char regs[6];
int status;
/* block read alarm registers */
regs[0] = MENELAUS_RTC_AL_SEC;
msg[0].addr = MENELAUS_I2C_ADDRESS;
msg[0].flags = 0;
msg[0].len = 1;
msg[0].buf = regs;
msg[1].addr = MENELAUS_I2C_ADDRESS;
msg[1].flags = I2C_M_RD;
msg[1].len = sizeof(regs);
msg[1].buf = regs;
status = i2c_transfer(the_menelaus->client->adapter, msg, 2);
if (status != 2) {
dev_err(dev, "%s error %d\n", "alarm read", status);
return -EIO;
}
menelaus_to_time(regs, &w->time);
w->enabled = !!(the_menelaus->rtc_control & RTC_CTRL_AL_EN);
/* NOTE we *could* check if actually pending... */
w->pending = 0;
return 0;
}
static int menelaus_set_alarm(struct device *dev, struct rtc_wkalrm *w)
{
int status;
if (the_menelaus->client->irq <= 0 && w->enabled)
return -ENODEV;
/* clear previous alarm enable */
if (the_menelaus->rtc_control & RTC_CTRL_AL_EN) {
the_menelaus->rtc_control &= ~RTC_CTRL_AL_EN;
status = menelaus_write_reg(MENELAUS_RTC_CTRL,
the_menelaus->rtc_control);
if (status < 0)
return status;
}
/* write alarm registers */
status = time_to_menelaus(&w->time, MENELAUS_RTC_AL_SEC);
if (status < 0)
return status;
/* enable alarm if requested */
if (w->enabled) {
the_menelaus->rtc_control |= RTC_CTRL_AL_EN;
status = menelaus_write_reg(MENELAUS_RTC_CTRL,
the_menelaus->rtc_control);
}
return status;
}
#ifdef CONFIG_RTC_INTF_DEV
static void menelaus_rtc_update_work(struct menelaus_chip *m)
{
/* report 1/sec update */
rtc_update_irq(m->rtc, 1, RTC_IRQF | RTC_UF);
}
static int menelaus_ioctl(struct device *dev, unsigned cmd, unsigned long arg)
{
int status;
if (the_menelaus->client->irq <= 0)
return -ENOIOCTLCMD;
switch (cmd) {
/* alarm IRQ */
case RTC_AIE_ON:
if (the_menelaus->rtc_control & RTC_CTRL_AL_EN)
return 0;
the_menelaus->rtc_control |= RTC_CTRL_AL_EN;
break;
case RTC_AIE_OFF:
if (!(the_menelaus->rtc_control & RTC_CTRL_AL_EN))
return 0;
the_menelaus->rtc_control &= ~RTC_CTRL_AL_EN;
break;
/* 1/second "update" IRQ */
case RTC_UIE_ON:
if (the_menelaus->uie)
return 0;
status = menelaus_remove_irq_work(MENELAUS_RTCTMR_IRQ);
status = menelaus_add_irq_work(MENELAUS_RTCTMR_IRQ,
menelaus_rtc_update_work);
if (status == 0)
the_menelaus->uie = 1;
return status;
case RTC_UIE_OFF:
if (!the_menelaus->uie)
return 0;
status = menelaus_remove_irq_work(MENELAUS_RTCTMR_IRQ);
if (status == 0)
the_menelaus->uie = 0;
return status;
default:
return -ENOIOCTLCMD;
}
return menelaus_write_reg(MENELAUS_RTC_CTRL, the_menelaus->rtc_control);
}
#else
#define menelaus_ioctl NULL
#endif
/* REVISIT no compensation register support ... */
static const struct rtc_class_ops menelaus_rtc_ops = {
.ioctl = menelaus_ioctl,
.read_time = menelaus_read_time,
.set_time = menelaus_set_time,
.read_alarm = menelaus_read_alarm,
.set_alarm = menelaus_set_alarm,
};
static void menelaus_rtc_alarm_work(struct menelaus_chip *m)
{
/* report alarm */
rtc_update_irq(m->rtc, 1, RTC_IRQF | RTC_AF);
/* then disable it; alarms are oneshot */
the_menelaus->rtc_control &= ~RTC_CTRL_AL_EN;
menelaus_write_reg(MENELAUS_RTC_CTRL, the_menelaus->rtc_control);
}
static inline void menelaus_rtc_init(struct menelaus_chip *m)
{
int alarm = (m->client->irq > 0);
int err;
/* assume 32KDETEN pin is pulled high */
if (!(menelaus_read_reg(MENELAUS_OSC_CTRL) & 0x80)) {
dev_dbg(&m->client->dev, "no 32k oscillator\n");
return;
}
m->rtc = devm_rtc_allocate_device(&m->client->dev);
if (IS_ERR(m->rtc))
return;
m->rtc->ops = &menelaus_rtc_ops;
/* support RTC alarm; it can issue wakeups */
if (alarm) {
if (menelaus_add_irq_work(MENELAUS_RTCALM_IRQ,
menelaus_rtc_alarm_work) < 0) {
dev_err(&m->client->dev, "can't handle RTC alarm\n");
return;
}
device_init_wakeup(&m->client->dev, 1);
}
/* be sure RTC is enabled; allow 1/sec irqs; leave 12hr mode alone */
m->rtc_control = menelaus_read_reg(MENELAUS_RTC_CTRL);
if (!(m->rtc_control & RTC_CTRL_RTC_EN)
|| (m->rtc_control & RTC_CTRL_AL_EN)
|| (m->rtc_control & RTC_CTRL_EVERY_MASK)) {
if (!(m->rtc_control & RTC_CTRL_RTC_EN)) {
dev_warn(&m->client->dev, "rtc clock needs setting\n");
m->rtc_control |= RTC_CTRL_RTC_EN;
}
m->rtc_control &= ~RTC_CTRL_EVERY_MASK;
m->rtc_control &= ~RTC_CTRL_AL_EN;
menelaus_write_reg(MENELAUS_RTC_CTRL, m->rtc_control);
}
err = devm_rtc_register_device(m->rtc);
if (err) {
if (alarm) {
menelaus_remove_irq_work(MENELAUS_RTCALM_IRQ);
device_init_wakeup(&m->client->dev, 0);
}
the_menelaus->rtc = NULL;
}
}
#else
static inline void menelaus_rtc_init(struct menelaus_chip *m)
{
/* nothing */
}
#endif
/*-----------------------------------------------------------------------*/
static struct i2c_driver menelaus_i2c_driver;
static int menelaus_probe(struct i2c_client *client)
{
struct menelaus_chip *menelaus;
int rev = 0;
int err = 0;
struct menelaus_platform_data *menelaus_pdata =
dev_get_platdata(&client->dev);
if (the_menelaus) {
dev_dbg(&client->dev, "only one %s for now\n",
DRIVER_NAME);
return -ENODEV;
}
menelaus = devm_kzalloc(&client->dev, sizeof(*menelaus), GFP_KERNEL);
if (!menelaus)
return -ENOMEM;
i2c_set_clientdata(client, menelaus);
the_menelaus = menelaus;
menelaus->client = client;
/* If a true probe check the device */
rev = menelaus_read_reg(MENELAUS_REV);
if (rev < 0) {
pr_err(DRIVER_NAME ": device not found");
return -ENODEV;
}
/* Ack and disable all Menelaus interrupts */
menelaus_write_reg(MENELAUS_INT_ACK1, 0xff);
menelaus_write_reg(MENELAUS_INT_ACK2, 0xff);
menelaus_write_reg(MENELAUS_INT_MASK1, 0xff);
menelaus_write_reg(MENELAUS_INT_MASK2, 0xff);
menelaus->mask1 = 0xff;
menelaus->mask2 = 0xff;
/* Set output buffer strengths */
menelaus_write_reg(MENELAUS_MCT_CTRL1, 0x73);
if (client->irq > 0) {
err = request_irq(client->irq, menelaus_irq, 0,
DRIVER_NAME, menelaus);
if (err) {
dev_dbg(&client->dev, "can't get IRQ %d, err %d\n",
client->irq, err);
return err;
}
}
mutex_init(&menelaus->lock);
INIT_WORK(&menelaus->work, menelaus_work);
pr_info("Menelaus rev %d.%d\n", rev >> 4, rev & 0x0f);
err = menelaus_read_reg(MENELAUS_VCORE_CTRL1);
if (err < 0)
goto fail;
if (err & VCORE_CTRL1_HW_NSW)
menelaus->vcore_hw_mode = 1;
else
menelaus->vcore_hw_mode = 0;
if (menelaus_pdata != NULL && menelaus_pdata->late_init != NULL) {
err = menelaus_pdata->late_init(&client->dev);
if (err < 0)
goto fail;
}
menelaus_rtc_init(menelaus);
return 0;
fail:
free_irq(client->irq, menelaus);
flush_work(&menelaus->work);
return err;
}
static void menelaus_remove(struct i2c_client *client)
{
struct menelaus_chip *menelaus = i2c_get_clientdata(client);
free_irq(client->irq, menelaus);
flush_work(&menelaus->work);
the_menelaus = NULL;
}
static const struct i2c_device_id menelaus_id[] = {
{ "menelaus", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, menelaus_id);
static struct i2c_driver menelaus_i2c_driver = {
.driver = {
.name = DRIVER_NAME,
},
.probe = menelaus_probe,
.remove = menelaus_remove,
.id_table = menelaus_id,
};
module_i2c_driver(menelaus_i2c_driver);
MODULE_AUTHOR("Texas Instruments, Inc. (and others)");
MODULE_DESCRIPTION("I2C interface for Menelaus.");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/menelaus.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
*
* Authors: Inha Song <[email protected]>
* Sylwester Nawrocki <[email protected]>
*
* Samsung Exynos SoC series Low Power Audio Subsystem driver.
*
* This module provides regmap for the Top SFR region and instantiates
* devices for IP blocks like DMAC, I2S, UART.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <linux/types.h>
/* LPASS Top register definitions */
#define SFR_LPASS_CORE_SW_RESET 0x08
#define LPASS_SB_SW_RESET BIT(11)
#define LPASS_UART_SW_RESET BIT(10)
#define LPASS_PCM_SW_RESET BIT(9)
#define LPASS_I2S_SW_RESET BIT(8)
#define LPASS_WDT1_SW_RESET BIT(4)
#define LPASS_WDT0_SW_RESET BIT(3)
#define LPASS_TIMER_SW_RESET BIT(2)
#define LPASS_MEM_SW_RESET BIT(1)
#define LPASS_DMA_SW_RESET BIT(0)
#define SFR_LPASS_INTR_CA5_MASK 0x48
#define SFR_LPASS_INTR_CPU_MASK 0x58
#define LPASS_INTR_APM BIT(9)
#define LPASS_INTR_MIF BIT(8)
#define LPASS_INTR_TIMER BIT(7)
#define LPASS_INTR_DMA BIT(6)
#define LPASS_INTR_GPIO BIT(5)
#define LPASS_INTR_I2S BIT(4)
#define LPASS_INTR_PCM BIT(3)
#define LPASS_INTR_SLIMBUS BIT(2)
#define LPASS_INTR_UART BIT(1)
#define LPASS_INTR_SFR BIT(0)
struct exynos_lpass {
/* pointer to the LPASS TOP regmap */
struct regmap *top;
struct clk *sfr0_clk;
};
static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
{
unsigned int val = 0;
regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);
val &= ~mask;
regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
usleep_range(100, 150);
val |= mask;
regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
}
static void exynos_lpass_enable(struct exynos_lpass *lpass)
{
clk_prepare_enable(lpass->sfr0_clk);
/* Unmask SFR, DMA and I2S interrupt */
regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S |
LPASS_INTR_UART);
exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);
}
static void exynos_lpass_disable(struct exynos_lpass *lpass)
{
/* Mask any unmasked IP interrupt sources */
regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
clk_disable_unprepare(lpass->sfr0_clk);
}
static const struct regmap_config exynos_lpass_reg_conf = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xfc,
.fast_io = true,
};
static int exynos_lpass_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct exynos_lpass *lpass;
void __iomem *base_top;
lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
if (!lpass)
return -ENOMEM;
base_top = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base_top))
return PTR_ERR(base_top);
lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
if (IS_ERR(lpass->sfr0_clk))
return PTR_ERR(lpass->sfr0_clk);
lpass->top = regmap_init_mmio(dev, base_top,
&exynos_lpass_reg_conf);
if (IS_ERR(lpass->top)) {
dev_err(dev, "LPASS top regmap initialization failed\n");
return PTR_ERR(lpass->top);
}
platform_set_drvdata(pdev, lpass);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
exynos_lpass_enable(lpass);
return devm_of_platform_populate(dev);
}
static int exynos_lpass_remove(struct platform_device *pdev)
{
struct exynos_lpass *lpass = platform_get_drvdata(pdev);
exynos_lpass_disable(lpass);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
exynos_lpass_disable(lpass);
regmap_exit(lpass->top);
return 0;
}
static int __maybe_unused exynos_lpass_suspend(struct device *dev)
{
struct exynos_lpass *lpass = dev_get_drvdata(dev);
exynos_lpass_disable(lpass);
return 0;
}
static int __maybe_unused exynos_lpass_resume(struct device *dev)
{
struct exynos_lpass *lpass = dev_get_drvdata(dev);
exynos_lpass_enable(lpass);
return 0;
}
static const struct dev_pm_ops lpass_pm_ops = {
SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static const struct of_device_id exynos_lpass_of_match[] = {
{ .compatible = "samsung,exynos5433-lpass" },
{ },
};
MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
static struct platform_driver exynos_lpass_driver = {
.driver = {
.name = "exynos-lpass",
.pm = &lpass_pm_ops,
.of_match_table = exynos_lpass_of_match,
},
.probe = exynos_lpass_probe,
.remove = exynos_lpass_remove,
};
module_platform_driver(exynos_lpass_driver);
MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/exynos-lpass.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* I2C driver for the X-Powers' Power Management ICs
*
* AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
* converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
* as well as configurable GPIOs.
*
* This driver supports the I2C variants.
*
* Copyright (C) 2014 Carlo Caione
*
* Author: Carlo Caione <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/mfd/axp20x.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
static int axp20x_i2c_probe(struct i2c_client *i2c)
{
struct axp20x_dev *axp20x;
int ret;
axp20x = devm_kzalloc(&i2c->dev, sizeof(*axp20x), GFP_KERNEL);
if (!axp20x)
return -ENOMEM;
axp20x->dev = &i2c->dev;
axp20x->irq = i2c->irq;
dev_set_drvdata(axp20x->dev, axp20x);
ret = axp20x_match_device(axp20x);
if (ret)
return ret;
axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg);
if (IS_ERR(axp20x->regmap)) {
ret = PTR_ERR(axp20x->regmap);
dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
return ret;
}
return axp20x_device_probe(axp20x);
}
static void axp20x_i2c_remove(struct i2c_client *i2c)
{
struct axp20x_dev *axp20x = i2c_get_clientdata(i2c);
axp20x_device_remove(axp20x);
}
#ifdef CONFIG_OF
static const struct of_device_id axp20x_i2c_of_match[] = {
{ .compatible = "x-powers,axp152", .data = (void *)AXP152_ID },
{ .compatible = "x-powers,axp192", .data = (void *)AXP192_ID },
{ .compatible = "x-powers,axp202", .data = (void *)AXP202_ID },
{ .compatible = "x-powers,axp209", .data = (void *)AXP209_ID },
{ .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
{ .compatible = "x-powers,axp313a", .data = (void *)AXP313A_ID },
{ .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
{ .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },
{ .compatible = "x-powers,axp15060", .data = (void *)AXP15060_ID },
{ },
};
MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
#endif
static const struct i2c_device_id axp20x_i2c_id[] = {
{ "axp152", 0 },
{ "axp192", 0 },
{ "axp202", 0 },
{ "axp209", 0 },
{ "axp221", 0 },
{ "axp223", 0 },
{ "axp313a", 0 },
{ "axp803", 0 },
{ "axp806", 0 },
{ "axp15060", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, axp20x_i2c_id);
#ifdef CONFIG_ACPI
static const struct acpi_device_id axp20x_i2c_acpi_match[] = {
{
.id = "INT33F4",
.driver_data = AXP288_ID,
},
{ },
};
MODULE_DEVICE_TABLE(acpi, axp20x_i2c_acpi_match);
#endif
static struct i2c_driver axp20x_i2c_driver = {
.driver = {
.name = "axp20x-i2c",
.of_match_table = of_match_ptr(axp20x_i2c_of_match),
.acpi_match_table = ACPI_PTR(axp20x_i2c_acpi_match),
},
.probe = axp20x_i2c_probe,
.remove = axp20x_i2c_remove,
.id_table = axp20x_i2c_id,
};
module_i2c_driver(axp20x_i2c_driver);
MODULE_DESCRIPTION("PMIC MFD I2C driver for AXP20X");
MODULE_AUTHOR("Carlo Caione <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/axp20x-i2c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MFD core driver for Intel Cherrytrail Whiskey Cove PMIC
*
* Copyright (C) 2017 Hans de Goede <[email protected]>
*
* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
* Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
*/
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/regmap.h>
/* PMIC device registers */
#define REG_OFFSET_MASK GENMASK(7, 0)
#define REG_ADDR_MASK GENMASK(15, 8)
#define REG_ADDR_SHIFT 8
#define CHT_WC_IRQLVL1 0x6e02
#define CHT_WC_IRQLVL1_MASK 0x6e0e
/* Whiskey Cove PMIC share same ACPI ID between different platforms */
#define CHT_WC_HRV 3
/* Level 1 IRQs (level 2 IRQs are handled in the child device drivers) */
enum {
CHT_WC_PWRSRC_IRQ = 0,
CHT_WC_THRM_IRQ,
CHT_WC_BCU_IRQ,
CHT_WC_ADC_IRQ,
CHT_WC_EXT_CHGR_IRQ,
CHT_WC_GPIO_IRQ,
/* There is no irq 6 */
CHT_WC_CRIT_IRQ = 7,
};
static const struct resource cht_wc_pwrsrc_resources[] = {
DEFINE_RES_IRQ(CHT_WC_PWRSRC_IRQ),
};
static const struct resource cht_wc_ext_charger_resources[] = {
DEFINE_RES_IRQ(CHT_WC_EXT_CHGR_IRQ),
};
static struct mfd_cell cht_wc_dev[] = {
{
.name = "cht_wcove_pwrsrc",
.num_resources = ARRAY_SIZE(cht_wc_pwrsrc_resources),
.resources = cht_wc_pwrsrc_resources,
}, {
.name = "cht_wcove_ext_chgr",
.num_resources = ARRAY_SIZE(cht_wc_ext_charger_resources),
.resources = cht_wc_ext_charger_resources,
},
{ .name = "cht_wcove_region", },
{ .name = "cht_wcove_leds", },
};
/*
* The CHT Whiskey Cove covers multiple I2C addresses, with a 1 Byte
* register address space per I2C address, so we use 16 bit register
* addresses where the high 8 bits contain the I2C client address.
*/
static int cht_wc_byte_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct i2c_client *client = context;
int ret, orig_addr = client->addr;
if (!(reg & REG_ADDR_MASK)) {
dev_err(&client->dev, "Error I2C address not specified\n");
return -EINVAL;
}
client->addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
ret = i2c_smbus_read_byte_data(client, reg & REG_OFFSET_MASK);
client->addr = orig_addr;
if (ret < 0)
return ret;
*val = ret;
return 0;
}
static int cht_wc_byte_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct i2c_client *client = context;
int ret, orig_addr = client->addr;
if (!(reg & REG_ADDR_MASK)) {
dev_err(&client->dev, "Error I2C address not specified\n");
return -EINVAL;
}
client->addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
ret = i2c_smbus_write_byte_data(client, reg & REG_OFFSET_MASK, val);
client->addr = orig_addr;
return ret;
}
static const struct regmap_config cht_wc_regmap_cfg = {
.reg_bits = 16,
.val_bits = 8,
.reg_write = cht_wc_byte_reg_write,
.reg_read = cht_wc_byte_reg_read,
};
static const struct regmap_irq cht_wc_regmap_irqs[] = {
REGMAP_IRQ_REG(CHT_WC_PWRSRC_IRQ, 0, BIT(CHT_WC_PWRSRC_IRQ)),
REGMAP_IRQ_REG(CHT_WC_THRM_IRQ, 0, BIT(CHT_WC_THRM_IRQ)),
REGMAP_IRQ_REG(CHT_WC_BCU_IRQ, 0, BIT(CHT_WC_BCU_IRQ)),
REGMAP_IRQ_REG(CHT_WC_ADC_IRQ, 0, BIT(CHT_WC_ADC_IRQ)),
REGMAP_IRQ_REG(CHT_WC_EXT_CHGR_IRQ, 0, BIT(CHT_WC_EXT_CHGR_IRQ)),
REGMAP_IRQ_REG(CHT_WC_GPIO_IRQ, 0, BIT(CHT_WC_GPIO_IRQ)),
REGMAP_IRQ_REG(CHT_WC_CRIT_IRQ, 0, BIT(CHT_WC_CRIT_IRQ)),
};
static const struct regmap_irq_chip cht_wc_regmap_irq_chip = {
.name = "cht_wc_irq_chip",
.status_base = CHT_WC_IRQLVL1,
.mask_base = CHT_WC_IRQLVL1_MASK,
.irqs = cht_wc_regmap_irqs,
.num_irqs = ARRAY_SIZE(cht_wc_regmap_irqs),
.num_regs = 1,
};
static const struct dmi_system_id cht_wc_model_dmi_ids[] = {
{
/* GPD win / GPD pocket mini laptops */
.driver_data = (void *)(long)INTEL_CHT_WC_GPD_WIN_POCKET,
/*
* This DMI match may not seem unique, but it is. In the 67000+
* DMI decode dumps from linux-hardware.org only 116 have
* board_vendor set to "AMI Corporation" and of those 116 only
* the GPD win's and pocket's board_name is "Default string".
*/
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
DMI_EXACT_MATCH(DMI_BOARD_SERIAL, "Default string"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
},
}, {
/* Xiaomi Mi Pad 2 */
.driver_data = (void *)(long)INTEL_CHT_WC_XIAOMI_MIPAD2,
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Xiaomi Inc"),
DMI_MATCH(DMI_PRODUCT_NAME, "Mipad2"),
},
}, {
/* Lenovo Yoga Book X90F / X90L */
.driver_data = (void *)(long)INTEL_CHT_WC_LENOVO_YOGABOOK1,
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "YETI-11"),
},
}, {
/* Lenovo Yoga Book X91F / X91L */
.driver_data = (void *)(long)INTEL_CHT_WC_LENOVO_YOGABOOK1,
.matches = {
/* Non exact match to match F + L versions */
DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X91"),
},
}, {
/* Lenovo Yoga Tab 3 Pro YT3-X90F */
.driver_data = (void *)(long)INTEL_CHT_WC_LENOVO_YT3_X90,
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
DMI_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
},
},
{ }
};
static int cht_wc_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
const struct dmi_system_id *id;
struct intel_soc_pmic *pmic;
acpi_status status;
unsigned long long hrv;
int ret;
status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
if (ACPI_FAILURE(status))
return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");
if (hrv != CHT_WC_HRV)
return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);
if (client->irq < 0)
return dev_err_probe(dev, -EINVAL, "Invalid IRQ\n");
pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
id = dmi_first_match(cht_wc_model_dmi_ids);
if (id)
pmic->cht_wc_model = (long)id->driver_data;
pmic->irq = client->irq;
pmic->dev = dev;
i2c_set_clientdata(client, pmic);
pmic->regmap = devm_regmap_init(dev, NULL, client, &cht_wc_regmap_cfg);
if (IS_ERR(pmic->regmap))
return PTR_ERR(pmic->regmap);
ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&cht_wc_regmap_irq_chip,
&pmic->irq_chip_data);
if (ret)
return ret;
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
cht_wc_dev, ARRAY_SIZE(cht_wc_dev), NULL, 0,
regmap_irq_get_domain(pmic->irq_chip_data));
}
static void cht_wc_shutdown(struct i2c_client *client)
{
struct intel_soc_pmic *pmic = i2c_get_clientdata(client);
disable_irq(pmic->irq);
}
static int cht_wc_suspend(struct device *dev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
disable_irq(pmic->irq);
return 0;
}
static int cht_wc_resume(struct device *dev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
enable_irq(pmic->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(cht_wc_pm_ops, cht_wc_suspend, cht_wc_resume);
static const struct i2c_device_id cht_wc_i2c_id[] = {
{ }
};
static const struct acpi_device_id cht_wc_acpi_ids[] = {
{ "INT34D3", },
{ }
};
static struct i2c_driver cht_wc_driver = {
.driver = {
.name = "CHT Whiskey Cove PMIC",
.pm = pm_sleep_ptr(&cht_wc_pm_ops),
.acpi_match_table = cht_wc_acpi_ids,
},
.probe = cht_wc_probe,
.shutdown = cht_wc_shutdown,
.id_table = cht_wc_i2c_id,
};
builtin_i2c_driver(cht_wc_driver);
| linux-master | drivers/mfd/intel_soc_pmic_chtwc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018-2019, Intel Corporation.
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Based on syscon driver.
*/
#include <linux/arm-smccc.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mfd/altera-sysmgr.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
/**
* struct altr_sysmgr - Altera SOCFPGA System Manager
* @regmap: the regmap used for System Manager accesses.
*/
struct altr_sysmgr {
struct regmap *regmap;
};
static struct platform_driver altr_sysmgr_driver;
/**
* s10_protected_reg_write
* Write to a protected SMC register.
* @base: Base address of System Manager
* @reg: Address offset of register
* @val: Value to write
* Return: INTEL_SIP_SMC_STATUS_OK (0) on success
* INTEL_SIP_SMC_REG_ERROR on error
* INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
*/
static int s10_protected_reg_write(void *base,
unsigned int reg, unsigned int val)
{
struct arm_smccc_res result;
unsigned long sysmgr_base = (unsigned long)base;
arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, sysmgr_base + reg,
val, 0, 0, 0, 0, 0, &result);
return (int)result.a0;
}
/**
* s10_protected_reg_read
* Read the status of a protected SMC register
* @base: Base address of System Manager.
* @reg: Address of register
* @val: Value read.
* Return: INTEL_SIP_SMC_STATUS_OK (0) on success
* INTEL_SIP_SMC_REG_ERROR on error
* INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
*/
static int s10_protected_reg_read(void *base,
unsigned int reg, unsigned int *val)
{
struct arm_smccc_res result;
unsigned long sysmgr_base = (unsigned long)base;
arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sysmgr_base + reg,
0, 0, 0, 0, 0, 0, &result);
*val = (unsigned int)result.a1;
return (int)result.a0;
}
static struct regmap_config altr_sysmgr_regmap_cfg = {
.name = "altr_sysmgr",
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
.use_single_read = true,
.use_single_write = true,
};
/**
* altr_sysmgr_regmap_lookup_by_phandle
* Find the sysmgr previous configured in probe() and return regmap property.
* Return: regmap if found or error if not found.
*
* @np: Pointer to device's Device Tree node
* @property: Device Tree property name which references the sysmgr
*/
struct regmap *altr_sysmgr_regmap_lookup_by_phandle(struct device_node *np,
const char *property)
{
struct device *dev;
struct altr_sysmgr *sysmgr;
struct device_node *sysmgr_np;
if (property)
sysmgr_np = of_parse_phandle(np, property, 0);
else
sysmgr_np = np;
if (!sysmgr_np)
return ERR_PTR(-ENODEV);
dev = driver_find_device_by_of_node(&altr_sysmgr_driver.driver,
(void *)sysmgr_np);
of_node_put(sysmgr_np);
if (!dev)
return ERR_PTR(-EPROBE_DEFER);
sysmgr = dev_get_drvdata(dev);
return sysmgr->regmap;
}
EXPORT_SYMBOL_GPL(altr_sysmgr_regmap_lookup_by_phandle);
static int sysmgr_probe(struct platform_device *pdev)
{
struct altr_sysmgr *sysmgr;
struct regmap *regmap;
struct resource *res;
struct regmap_config sysmgr_config = altr_sysmgr_regmap_cfg;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
void __iomem *base;
sysmgr = devm_kzalloc(dev, sizeof(*sysmgr), GFP_KERNEL);
if (!sysmgr)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
sysmgr_config.max_register = resource_size(res) -
sysmgr_config.reg_stride;
if (of_device_is_compatible(np, "altr,sys-mgr-s10")) {
sysmgr_config.reg_read = s10_protected_reg_read;
sysmgr_config.reg_write = s10_protected_reg_write;
/* Need physical address for SMCC call */
regmap = devm_regmap_init(dev, NULL,
(void *)(uintptr_t)res->start,
&sysmgr_config);
} else {
base = devm_ioremap(dev, res->start, resource_size(res));
if (!base)
return -ENOMEM;
sysmgr_config.max_register = resource_size(res) - 4;
regmap = devm_regmap_init_mmio(dev, base, &sysmgr_config);
}
if (IS_ERR(regmap)) {
pr_err("regmap init failed\n");
return PTR_ERR(regmap);
}
sysmgr->regmap = regmap;
platform_set_drvdata(pdev, sysmgr);
return 0;
}
static const struct of_device_id altr_sysmgr_of_match[] = {
{ .compatible = "altr,sys-mgr" },
{ .compatible = "altr,sys-mgr-s10" },
{},
};
MODULE_DEVICE_TABLE(of, altr_sysmgr_of_match);
static struct platform_driver altr_sysmgr_driver = {
.probe = sysmgr_probe,
.driver = {
.name = "altr,system_manager",
.of_match_table = altr_sysmgr_of_match,
},
};
static int __init altr_sysmgr_init(void)
{
return platform_driver_register(&altr_sysmgr_driver);
}
core_initcall(altr_sysmgr_init);
static void __exit altr_sysmgr_exit(void)
{
platform_driver_unregister(&altr_sysmgr_driver);
}
module_exit(altr_sysmgr_exit);
MODULE_AUTHOR("Thor Thayer <>");
MODULE_DESCRIPTION("SOCFPGA System Manager driver");
| linux-master | drivers/mfd/altera-sysmgr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Core functions for TI TPS6594/TPS6593/LP8764 PMICs
*
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
*/
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps6594.h>
#define TPS6594_CRC_SYNC_TIMEOUT_MS 150
/* Completion to synchronize CRC feature enabling on all PMICs */
static DECLARE_COMPLETION(tps6594_crc_comp);
static const struct resource tps6594_regulator_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_OV, TPS6594_IRQ_NAME_BUCK1_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_UV, TPS6594_IRQ_NAME_BUCK1_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_SC, TPS6594_IRQ_NAME_BUCK1_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_ILIM, TPS6594_IRQ_NAME_BUCK1_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_OV, TPS6594_IRQ_NAME_BUCK2_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_UV, TPS6594_IRQ_NAME_BUCK2_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_SC, TPS6594_IRQ_NAME_BUCK2_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_ILIM, TPS6594_IRQ_NAME_BUCK2_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_OV, TPS6594_IRQ_NAME_BUCK3_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_UV, TPS6594_IRQ_NAME_BUCK3_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_SC, TPS6594_IRQ_NAME_BUCK3_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_ILIM, TPS6594_IRQ_NAME_BUCK3_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_OV, TPS6594_IRQ_NAME_BUCK4_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_UV, TPS6594_IRQ_NAME_BUCK4_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_SC, TPS6594_IRQ_NAME_BUCK4_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_ILIM, TPS6594_IRQ_NAME_BUCK4_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_OV, TPS6594_IRQ_NAME_BUCK5_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_UV, TPS6594_IRQ_NAME_BUCK5_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_SC, TPS6594_IRQ_NAME_BUCK5_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_ILIM, TPS6594_IRQ_NAME_BUCK5_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_OV, TPS6594_IRQ_NAME_LDO1_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_UV, TPS6594_IRQ_NAME_LDO1_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_SC, TPS6594_IRQ_NAME_LDO1_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_ILIM, TPS6594_IRQ_NAME_LDO1_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_OV, TPS6594_IRQ_NAME_LDO2_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_UV, TPS6594_IRQ_NAME_LDO2_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_SC, TPS6594_IRQ_NAME_LDO2_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_ILIM, TPS6594_IRQ_NAME_LDO2_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_OV, TPS6594_IRQ_NAME_LDO3_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_UV, TPS6594_IRQ_NAME_LDO3_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_SC, TPS6594_IRQ_NAME_LDO3_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_ILIM, TPS6594_IRQ_NAME_LDO3_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_OV, TPS6594_IRQ_NAME_LDO4_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_UV, TPS6594_IRQ_NAME_LDO4_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_SC, TPS6594_IRQ_NAME_LDO4_SC),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_ILIM, TPS6594_IRQ_NAME_LDO4_ILIM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OV, TPS6594_IRQ_NAME_VCCA_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_UV, TPS6594_IRQ_NAME_VCCA_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_OV, TPS6594_IRQ_NAME_VMON1_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_UV, TPS6594_IRQ_NAME_VMON1_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_RV, TPS6594_IRQ_NAME_VMON1_RV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_OV, TPS6594_IRQ_NAME_VMON2_OV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_UV, TPS6594_IRQ_NAME_VMON2_UV),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_RV, TPS6594_IRQ_NAME_VMON2_RV),
};
static const struct resource tps6594_pinctrl_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO9, TPS6594_IRQ_NAME_GPIO9),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO10, TPS6594_IRQ_NAME_GPIO10),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO11, TPS6594_IRQ_NAME_GPIO11),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO1, TPS6594_IRQ_NAME_GPIO1),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO2, TPS6594_IRQ_NAME_GPIO2),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO3, TPS6594_IRQ_NAME_GPIO3),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO4, TPS6594_IRQ_NAME_GPIO4),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO5, TPS6594_IRQ_NAME_GPIO5),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO6, TPS6594_IRQ_NAME_GPIO6),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO7, TPS6594_IRQ_NAME_GPIO7),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO8, TPS6594_IRQ_NAME_GPIO8),
};
static const struct resource tps6594_pfsm_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_START, TPS6594_IRQ_NAME_NPWRON_START),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ENABLE, TPS6594_IRQ_NAME_ENABLE),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_FSD, TPS6594_IRQ_NAME_FSD),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOFT_REBOOT, TPS6594_IRQ_NAME_SOFT_REBOOT),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_PASS, TPS6594_IRQ_NAME_BIST_PASS),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EXT_CLK, TPS6594_IRQ_NAME_EXT_CLK),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TWARN, TPS6594_IRQ_NAME_TWARN),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_ORD, TPS6594_IRQ_NAME_TSD_ORD),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_FAIL, TPS6594_IRQ_NAME_BIST_FAIL),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_REG_CRC_ERR, TPS6594_IRQ_NAME_REG_CRC_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_RECOV_CNT, TPS6594_IRQ_NAME_RECOV_CNT),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SPMI_ERR, TPS6594_IRQ_NAME_SPMI_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_LONG, TPS6594_IRQ_NAME_NPWRON_LONG),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NINT_READBACK, TPS6594_IRQ_NAME_NINT_READBACK),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_READBACK, TPS6594_IRQ_NAME_NRSTOUT_READBACK),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_IMM, TPS6594_IRQ_NAME_TSD_IMM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OVP, TPS6594_IRQ_NAME_VCCA_OVP),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_PFSM_ERR, TPS6594_IRQ_NAME_PFSM_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_IMM_SHUTDOWN, TPS6594_IRQ_NAME_IMM_SHUTDOWN),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ORD_SHUTDOWN, TPS6594_IRQ_NAME_ORD_SHUTDOWN),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_MCU_PWR_ERR, TPS6594_IRQ_NAME_MCU_PWR_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOC_PWR_ERR, TPS6594_IRQ_NAME_SOC_PWR_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_FRM_ERR, TPS6594_IRQ_NAME_COMM_FRM_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_CRC_ERR, TPS6594_IRQ_NAME_COMM_CRC_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_ADR_ERR, TPS6594_IRQ_NAME_COMM_ADR_ERR),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EN_DRV_READBACK, TPS6594_IRQ_NAME_EN_DRV_READBACK),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_SOC_READBACK,
TPS6594_IRQ_NAME_NRSTOUT_SOC_READBACK),
};
static const struct resource tps6594_esm_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_PIN, TPS6594_IRQ_NAME_ESM_SOC_PIN),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_FAIL, TPS6594_IRQ_NAME_ESM_SOC_FAIL),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_RST, TPS6594_IRQ_NAME_ESM_SOC_RST),
};
static const struct resource tps6594_rtc_resources[] = {
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TIMER, TPS6594_IRQ_NAME_TIMER),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ALARM, TPS6594_IRQ_NAME_ALARM),
DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_POWER_UP, TPS6594_IRQ_NAME_POWERUP),
};
static const struct mfd_cell tps6594_common_cells[] = {
MFD_CELL_RES("tps6594-regulator", tps6594_regulator_resources),
MFD_CELL_RES("tps6594-pinctrl", tps6594_pinctrl_resources),
MFD_CELL_RES("tps6594-pfsm", tps6594_pfsm_resources),
MFD_CELL_RES("tps6594-esm", tps6594_esm_resources),
};
static const struct mfd_cell tps6594_rtc_cells[] = {
MFD_CELL_RES("tps6594-rtc", tps6594_rtc_resources),
};
static const struct regmap_irq tps6594_irqs[] = {
/* INT_BUCK1_2 register */
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_OV, 0, TPS6594_BIT_BUCKX_OV_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_UV, 0, TPS6594_BIT_BUCKX_UV_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_SC, 0, TPS6594_BIT_BUCKX_SC_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_OV, 0, TPS6594_BIT_BUCKX_OV_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_UV, 0, TPS6594_BIT_BUCKX_UV_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_SC, 0, TPS6594_BIT_BUCKX_SC_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(1)),
/* INT_BUCK3_4 register */
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_OV, 1, TPS6594_BIT_BUCKX_OV_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_UV, 1, TPS6594_BIT_BUCKX_UV_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_SC, 1, TPS6594_BIT_BUCKX_SC_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_OV, 1, TPS6594_BIT_BUCKX_OV_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_UV, 1, TPS6594_BIT_BUCKX_UV_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_SC, 1, TPS6594_BIT_BUCKX_SC_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(3)),
/* INT_BUCK5 register */
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_OV, 2, TPS6594_BIT_BUCKX_OV_INT(4)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_UV, 2, TPS6594_BIT_BUCKX_UV_INT(4)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_SC, 2, TPS6594_BIT_BUCKX_SC_INT(4)),
REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_ILIM, 2, TPS6594_BIT_BUCKX_ILIM_INT(4)),
/* INT_LDO1_2 register */
REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_OV, 3, TPS6594_BIT_LDOX_OV_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_UV, 3, TPS6594_BIT_LDOX_UV_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_SC, 3, TPS6594_BIT_LDOX_SC_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_OV, 3, TPS6594_BIT_LDOX_OV_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_UV, 3, TPS6594_BIT_LDOX_UV_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_SC, 3, TPS6594_BIT_LDOX_SC_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(1)),
/* INT_LDO3_4 register */
REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_OV, 4, TPS6594_BIT_LDOX_OV_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_UV, 4, TPS6594_BIT_LDOX_UV_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_SC, 4, TPS6594_BIT_LDOX_SC_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_OV, 4, TPS6594_BIT_LDOX_OV_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_UV, 4, TPS6594_BIT_LDOX_UV_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_SC, 4, TPS6594_BIT_LDOX_SC_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(3)),
/* INT_VMON register */
REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OV, 5, TPS6594_BIT_VCCA_OV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_UV, 5, TPS6594_BIT_VCCA_UV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_OV, 5, TPS6594_BIT_VMON1_OV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_UV, 5, TPS6594_BIT_VMON1_UV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_RV, 5, TPS6594_BIT_VMON1_RV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_OV, 5, TPS6594_BIT_VMON2_OV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_UV, 5, TPS6594_BIT_VMON2_UV_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_RV, 5, TPS6594_BIT_VMON2_RV_INT),
/* INT_GPIO register */
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO9, 6, TPS6594_BIT_GPIO9_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO10, 6, TPS6594_BIT_GPIO10_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO11, 6, TPS6594_BIT_GPIO11_INT),
/* INT_GPIO1_8 register */
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO1, 7, TPS6594_BIT_GPIOX_INT(0)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO2, 7, TPS6594_BIT_GPIOX_INT(1)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO3, 7, TPS6594_BIT_GPIOX_INT(2)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO4, 7, TPS6594_BIT_GPIOX_INT(3)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO5, 7, TPS6594_BIT_GPIOX_INT(4)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO6, 7, TPS6594_BIT_GPIOX_INT(5)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO7, 7, TPS6594_BIT_GPIOX_INT(6)),
REGMAP_IRQ_REG(TPS6594_IRQ_GPIO8, 7, TPS6594_BIT_GPIOX_INT(7)),
/* INT_STARTUP register */
REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_START, 8, TPS6594_BIT_NPWRON_START_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_ENABLE, 8, TPS6594_BIT_ENABLE_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_FSD, 8, TPS6594_BIT_FSD_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_SOFT_REBOOT, 8, TPS6594_BIT_SOFT_REBOOT_INT),
/* INT_MISC register */
REGMAP_IRQ_REG(TPS6594_IRQ_BIST_PASS, 9, TPS6594_BIT_BIST_PASS_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_EXT_CLK, 9, TPS6594_BIT_EXT_CLK_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_TWARN, 9, TPS6594_BIT_TWARN_INT),
/* INT_MODERATE_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_TSD_ORD, 10, TPS6594_BIT_TSD_ORD_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_BIST_FAIL, 10, TPS6594_BIT_BIST_FAIL_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_REG_CRC_ERR, 10, TPS6594_BIT_REG_CRC_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_RECOV_CNT, 10, TPS6594_BIT_RECOV_CNT_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_SPMI_ERR, 10, TPS6594_BIT_SPMI_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_LONG, 10, TPS6594_BIT_NPWRON_LONG_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_NINT_READBACK, 10, TPS6594_BIT_NINT_READBACK_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_READBACK, 10, TPS6594_BIT_NRSTOUT_READBACK_INT),
/* INT_SEVERE_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_TSD_IMM, 11, TPS6594_BIT_TSD_IMM_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OVP, 11, TPS6594_BIT_VCCA_OVP_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_PFSM_ERR, 11, TPS6594_BIT_PFSM_ERR_INT),
/* INT_FSM_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_IMM_SHUTDOWN, 12, TPS6594_BIT_IMM_SHUTDOWN_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_ORD_SHUTDOWN, 12, TPS6594_BIT_ORD_SHUTDOWN_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_MCU_PWR_ERR, 12, TPS6594_BIT_MCU_PWR_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_SOC_PWR_ERR, 12, TPS6594_BIT_SOC_PWR_ERR_INT),
/* INT_COMM_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_COMM_FRM_ERR, 13, TPS6594_BIT_COMM_FRM_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_COMM_CRC_ERR, 13, TPS6594_BIT_COMM_CRC_ERR_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_COMM_ADR_ERR, 13, TPS6594_BIT_COMM_ADR_ERR_INT),
/* INT_READBACK_ERR register */
REGMAP_IRQ_REG(TPS6594_IRQ_EN_DRV_READBACK, 14, TPS6594_BIT_EN_DRV_READBACK_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_SOC_READBACK, 14, TPS6594_BIT_NRSTOUT_SOC_READBACK_INT),
/* INT_ESM register */
REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_PIN, 15, TPS6594_BIT_ESM_SOC_PIN_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_FAIL, 15, TPS6594_BIT_ESM_SOC_FAIL_INT),
REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_RST, 15, TPS6594_BIT_ESM_SOC_RST_INT),
/* RTC_STATUS register */
REGMAP_IRQ_REG(TPS6594_IRQ_TIMER, 16, TPS6594_BIT_TIMER),
REGMAP_IRQ_REG(TPS6594_IRQ_ALARM, 16, TPS6594_BIT_ALARM),
REGMAP_IRQ_REG(TPS6594_IRQ_POWER_UP, 16, TPS6594_BIT_POWER_UP),
};
static const unsigned int tps6594_irq_reg[] = {
TPS6594_REG_INT_BUCK1_2,
TPS6594_REG_INT_BUCK3_4,
TPS6594_REG_INT_BUCK5,
TPS6594_REG_INT_LDO1_2,
TPS6594_REG_INT_LDO3_4,
TPS6594_REG_INT_VMON,
TPS6594_REG_INT_GPIO,
TPS6594_REG_INT_GPIO1_8,
TPS6594_REG_INT_STARTUP,
TPS6594_REG_INT_MISC,
TPS6594_REG_INT_MODERATE_ERR,
TPS6594_REG_INT_SEVERE_ERR,
TPS6594_REG_INT_FSM_ERR,
TPS6594_REG_INT_COMM_ERR,
TPS6594_REG_INT_READBACK_ERR,
TPS6594_REG_INT_ESM,
TPS6594_REG_RTC_STATUS,
};
static inline unsigned int tps6594_get_irq_reg(struct regmap_irq_chip_data *data,
unsigned int base, int index)
{
return tps6594_irq_reg[index];
};
static int tps6594_handle_post_irq(void *irq_drv_data)
{
struct tps6594 *tps = irq_drv_data;
int ret = 0;
/*
* When CRC is enabled, writing to a read-only bit triggers an error,
* and COMM_ADR_ERR_INT bit is set. Besides, bits indicating interrupts
* (that must be cleared) and read-only bits are sometimes grouped in
* the same register.
* Since regmap clears interrupts by doing a write per register, clearing
* an interrupt bit in a register containing also a read-only bit makes
* COMM_ADR_ERR_INT bit set. Clear immediately this bit to avoid raising
* a new interrupt.
*/
if (tps->use_crc)
ret = regmap_write_bits(tps->regmap, TPS6594_REG_INT_COMM_ERR,
TPS6594_BIT_COMM_ADR_ERR_INT,
TPS6594_BIT_COMM_ADR_ERR_INT);
return ret;
};
static struct regmap_irq_chip tps6594_irq_chip = {
.ack_base = TPS6594_REG_INT_BUCK1_2,
.ack_invert = 1,
.clear_ack = 1,
.init_ack_masked = 1,
.num_regs = ARRAY_SIZE(tps6594_irq_reg),
.irqs = tps6594_irqs,
.num_irqs = ARRAY_SIZE(tps6594_irqs),
.get_irq_reg = tps6594_get_irq_reg,
.handle_post_irq = tps6594_handle_post_irq,
};
bool tps6594_is_volatile_reg(struct device *dev, unsigned int reg)
{
return (reg >= TPS6594_REG_INT_TOP && reg <= TPS6594_REG_STAT_READBACK_ERR) ||
reg == TPS6594_REG_RTC_STATUS;
}
EXPORT_SYMBOL_GPL(tps6594_is_volatile_reg);
static int tps6594_check_crc_mode(struct tps6594 *tps, bool primary_pmic)
{
int ret;
/*
* Check if CRC is enabled.
* Once CRC is enabled, it can't be disabled until next power cycle.
*/
tps->use_crc = true;
ret = regmap_test_bits(tps->regmap, TPS6594_REG_SERIAL_IF_CONFIG,
TPS6594_BIT_I2C1_SPI_CRC_EN);
if (ret == 0) {
ret = -EIO;
} else if (ret > 0) {
dev_info(tps->dev, "CRC feature enabled on %s PMIC",
primary_pmic ? "primary" : "secondary");
ret = 0;
}
return ret;
}
static int tps6594_set_crc_feature(struct tps6594 *tps)
{
int ret;
ret = tps6594_check_crc_mode(tps, true);
if (ret) {
/*
* If CRC is not already enabled, force PFSM I2C_2 trigger to enable it
* on primary PMIC.
*/
tps->use_crc = false;
ret = regmap_write_bits(tps->regmap, TPS6594_REG_FSM_I2C_TRIGGERS,
TPS6594_BIT_TRIGGER_I2C(2), TPS6594_BIT_TRIGGER_I2C(2));
if (ret)
return ret;
/*
* Wait for PFSM to process trigger.
* The datasheet indicates 2 ms, and clock specification is +/-5%.
* 4 ms should provide sufficient margin.
*/
usleep_range(4000, 5000);
ret = tps6594_check_crc_mode(tps, true);
}
return ret;
}
static int tps6594_enable_crc(struct tps6594 *tps)
{
struct device *dev = tps->dev;
unsigned int is_primary;
unsigned long timeout = msecs_to_jiffies(TPS6594_CRC_SYNC_TIMEOUT_MS);
int ret;
/*
* CRC mode can be used with I2C or SPI protocols.
* If this mode is specified for primary PMIC, it will also be applied to secondary PMICs
* through SPMI serial interface.
* In this multi-PMIC synchronization scheme, the primary PMIC is the controller device
* on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus.
*/
is_primary = of_property_read_bool(dev->of_node, "ti,primary-pmic");
if (is_primary) {
/* Enable CRC feature on primary PMIC */
ret = tps6594_set_crc_feature(tps);
if (ret)
return ret;
/* Notify secondary PMICs that CRC feature is enabled */
complete_all(&tps6594_crc_comp);
} else {
/* Wait for CRC feature enabling event from primary PMIC */
ret = wait_for_completion_interruptible_timeout(&tps6594_crc_comp, timeout);
if (ret == 0)
ret = -ETIMEDOUT;
else if (ret > 0)
ret = tps6594_check_crc_mode(tps, false);
}
return ret;
}
int tps6594_device_init(struct tps6594 *tps, bool enable_crc)
{
struct device *dev = tps->dev;
int ret;
if (enable_crc) {
ret = tps6594_enable_crc(tps);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable CRC\n");
}
/* Keep PMIC in ACTIVE state */
ret = regmap_set_bits(tps->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,
TPS6594_BIT_NSLEEP1B | TPS6594_BIT_NSLEEP2B);
if (ret)
return dev_err_probe(dev, ret, "Failed to set PMIC state\n");
tps6594_irq_chip.irq_drv_data = tps;
tps6594_irq_chip.name = devm_kasprintf(dev, GFP_KERNEL, "%s-%ld-0x%02x",
dev->driver->name, tps->chip_id, tps->reg);
ret = devm_regmap_add_irq_chip(dev, tps->regmap, tps->irq, IRQF_SHARED | IRQF_ONESHOT,
0, &tps6594_irq_chip, &tps->irq_data);
if (ret)
return dev_err_probe(dev, ret, "Failed to add regmap IRQ\n");
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_common_cells,
ARRAY_SIZE(tps6594_common_cells), NULL, 0,
regmap_irq_get_domain(tps->irq_data));
if (ret)
return dev_err_probe(dev, ret, "Failed to add common child devices\n");
/* No RTC for LP8764 */
if (tps->chip_id != LP8764) {
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_rtc_cells,
ARRAY_SIZE(tps6594_rtc_cells), NULL, 0,
regmap_irq_get_domain(tps->irq_data));
if (ret)
return dev_err_probe(dev, ret, "Failed to add RTC child device\n");
}
return 0;
}
EXPORT_SYMBOL_GPL(tps6594_device_init);
MODULE_AUTHOR("Julien Panis <[email protected]>");
MODULE_DESCRIPTION("TPS6594 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/tps6594-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/* NXP PCF50633 ADC Driver
*
* (C) 2006-2008 by Openmoko, Inc.
* Author: Balaji Rao <[email protected]>
* All rights reserved.
*
* Broken down from monstrous PCF50633 driver mainly by
* Harald Welte, Andy Green and Werner Almesberger
*
* NOTE: This driver does not yet support subtractive ADC mode, which means
* you can do only one measurement per read request.
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/completion.h>
#include <linux/mfd/pcf50633/core.h>
#include <linux/mfd/pcf50633/adc.h>
struct pcf50633_adc_request {
int mux;
int avg;
void (*callback)(struct pcf50633 *, void *, int);
void *callback_param;
};
struct pcf50633_adc_sync_request {
int result;
struct completion completion;
};
#define PCF50633_MAX_ADC_FIFO_DEPTH 8
struct pcf50633_adc {
struct pcf50633 *pcf;
/* Private stuff */
struct pcf50633_adc_request *queue[PCF50633_MAX_ADC_FIFO_DEPTH];
int queue_head;
int queue_tail;
struct mutex queue_mutex;
};
static inline struct pcf50633_adc *__to_adc(struct pcf50633 *pcf)
{
return platform_get_drvdata(pcf->adc_pdev);
}
static void adc_setup(struct pcf50633 *pcf, int channel, int avg)
{
channel &= PCF50633_ADCC1_ADCMUX_MASK;
/* kill ratiometric, but enable ACCSW biasing */
pcf50633_reg_write(pcf, PCF50633_REG_ADCC2, 0x00);
pcf50633_reg_write(pcf, PCF50633_REG_ADCC3, 0x01);
/* start ADC conversion on selected channel */
pcf50633_reg_write(pcf, PCF50633_REG_ADCC1, channel | avg |
PCF50633_ADCC1_ADCSTART | PCF50633_ADCC1_RES_10BIT);
}
static void trigger_next_adc_job_if_any(struct pcf50633 *pcf)
{
struct pcf50633_adc *adc = __to_adc(pcf);
int head;
head = adc->queue_head;
if (!adc->queue[head])
return;
adc_setup(pcf, adc->queue[head]->mux, adc->queue[head]->avg);
}
static int
adc_enqueue_request(struct pcf50633 *pcf, struct pcf50633_adc_request *req)
{
struct pcf50633_adc *adc = __to_adc(pcf);
int head, tail;
mutex_lock(&adc->queue_mutex);
head = adc->queue_head;
tail = adc->queue_tail;
if (adc->queue[tail]) {
mutex_unlock(&adc->queue_mutex);
dev_err(pcf->dev, "ADC queue is full, dropping request\n");
return -EBUSY;
}
adc->queue[tail] = req;
if (head == tail)
trigger_next_adc_job_if_any(pcf);
adc->queue_tail = (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
mutex_unlock(&adc->queue_mutex);
return 0;
}
static void pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param,
int result)
{
struct pcf50633_adc_sync_request *req = param;
req->result = result;
complete(&req->completion);
}
int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg)
{
struct pcf50633_adc_sync_request req;
int ret;
init_completion(&req.completion);
ret = pcf50633_adc_async_read(pcf, mux, avg,
pcf50633_adc_sync_read_callback, &req);
if (ret)
return ret;
wait_for_completion(&req.completion);
return req.result;
}
EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read);
int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
void (*callback)(struct pcf50633 *, void *, int),
void *callback_param)
{
struct pcf50633_adc_request *req;
int ret;
/* req is freed when the result is ready, in interrupt handler */
req = kmalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
req->mux = mux;
req->avg = avg;
req->callback = callback;
req->callback_param = callback_param;
ret = adc_enqueue_request(pcf, req);
if (ret)
kfree(req);
return ret;
}
EXPORT_SYMBOL_GPL(pcf50633_adc_async_read);
static int adc_result(struct pcf50633 *pcf)
{
u8 adcs1, adcs3;
u16 result;
adcs1 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS1);
adcs3 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS3);
result = (adcs1 << 2) | (adcs3 & PCF50633_ADCS3_ADCDAT1L_MASK);
dev_dbg(pcf->dev, "adc result = %d\n", result);
return result;
}
static void pcf50633_adc_irq(int irq, void *data)
{
struct pcf50633_adc *adc = data;
struct pcf50633 *pcf = adc->pcf;
struct pcf50633_adc_request *req;
int head, res;
mutex_lock(&adc->queue_mutex);
head = adc->queue_head;
req = adc->queue[head];
if (WARN_ON(!req)) {
dev_err(pcf->dev, "pcf50633-adc irq: ADC queue empty!\n");
mutex_unlock(&adc->queue_mutex);
return;
}
adc->queue[head] = NULL;
adc->queue_head = (head + 1) &
(PCF50633_MAX_ADC_FIFO_DEPTH - 1);
res = adc_result(pcf);
trigger_next_adc_job_if_any(pcf);
mutex_unlock(&adc->queue_mutex);
req->callback(pcf, req->callback_param, res);
kfree(req);
}
static int pcf50633_adc_probe(struct platform_device *pdev)
{
struct pcf50633_adc *adc;
adc = devm_kzalloc(&pdev->dev, sizeof(*adc), GFP_KERNEL);
if (!adc)
return -ENOMEM;
adc->pcf = dev_to_pcf50633(pdev->dev.parent);
platform_set_drvdata(pdev, adc);
pcf50633_register_irq(adc->pcf, PCF50633_IRQ_ADCRDY,
pcf50633_adc_irq, adc);
mutex_init(&adc->queue_mutex);
return 0;
}
static int pcf50633_adc_remove(struct platform_device *pdev)
{
struct pcf50633_adc *adc = platform_get_drvdata(pdev);
int i, head;
pcf50633_free_irq(adc->pcf, PCF50633_IRQ_ADCRDY);
mutex_lock(&adc->queue_mutex);
head = adc->queue_head;
if (WARN_ON(adc->queue[head]))
dev_err(adc->pcf->dev,
"adc driver removed with request pending\n");
for (i = 0; i < PCF50633_MAX_ADC_FIFO_DEPTH; i++)
kfree(adc->queue[i]);
mutex_unlock(&adc->queue_mutex);
return 0;
}
static struct platform_driver pcf50633_adc_driver = {
.driver = {
.name = "pcf50633-adc",
},
.probe = pcf50633_adc_probe,
.remove = pcf50633_adc_remove,
};
module_platform_driver(pcf50633_adc_driver);
MODULE_AUTHOR("Balaji Rao <[email protected]>");
MODULE_DESCRIPTION("PCF50633 adc driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pcf50633-adc");
| linux-master | drivers/mfd/pcf50633-adc.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* I2C bus interface for ATC260x PMICs
*
* Copyright (C) 2019 Manivannan Sadhasivam <[email protected]>
* Copyright (C) 2020 Cristian Ciocaltea <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/mfd/atc260x/core.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
static int atc260x_i2c_probe(struct i2c_client *client)
{
struct atc260x *atc260x;
struct regmap_config regmap_cfg;
int ret;
atc260x = devm_kzalloc(&client->dev, sizeof(*atc260x), GFP_KERNEL);
if (!atc260x)
return -ENOMEM;
atc260x->dev = &client->dev;
atc260x->irq = client->irq;
ret = atc260x_match_device(atc260x, ®map_cfg);
if (ret)
return ret;
i2c_set_clientdata(client, atc260x);
atc260x->regmap = devm_regmap_init_i2c(client, ®map_cfg);
if (IS_ERR(atc260x->regmap)) {
ret = PTR_ERR(atc260x->regmap);
dev_err(&client->dev, "failed to init regmap: %d\n", ret);
return ret;
}
return atc260x_device_probe(atc260x);
}
static const struct of_device_id atc260x_i2c_of_match[] = {
{ .compatible = "actions,atc2603c", .data = (void *)ATC2603C },
{ .compatible = "actions,atc2609a", .data = (void *)ATC2609A },
{ }
};
MODULE_DEVICE_TABLE(of, atc260x_i2c_of_match);
static struct i2c_driver atc260x_i2c_driver = {
.driver = {
.name = "atc260x",
.of_match_table = atc260x_i2c_of_match,
},
.probe = atc260x_i2c_probe,
};
module_i2c_driver(atc260x_i2c_driver);
MODULE_DESCRIPTION("ATC260x PMICs I2C bus interface");
MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>");
MODULE_AUTHOR("Cristian Ciocaltea <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/atc260x-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the Diolan DLN-2 USB adapter
*
* Copyright (c) 2014 Intel Corporation
*
* Derived from:
* i2c-diolan-u2c.c
* Copyright (c) 2010-2011 Ericsson AB
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/usb.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/dln2.h>
#include <linux/rculist.h>
struct dln2_header {
__le16 size;
__le16 id;
__le16 echo;
__le16 handle;
};
struct dln2_response {
struct dln2_header hdr;
__le16 result;
};
#define DLN2_GENERIC_MODULE_ID 0x00
#define DLN2_GENERIC_CMD(cmd) DLN2_CMD(cmd, DLN2_GENERIC_MODULE_ID)
#define CMD_GET_DEVICE_VER DLN2_GENERIC_CMD(0x30)
#define CMD_GET_DEVICE_SN DLN2_GENERIC_CMD(0x31)
#define DLN2_HW_ID 0x200
#define DLN2_USB_TIMEOUT 200 /* in ms */
#define DLN2_MAX_RX_SLOTS 16
#define DLN2_MAX_URBS 16
#define DLN2_RX_BUF_SIZE 512
enum dln2_handle {
DLN2_HANDLE_EVENT = 0, /* don't change, hardware defined */
DLN2_HANDLE_CTRL,
DLN2_HANDLE_GPIO,
DLN2_HANDLE_I2C,
DLN2_HANDLE_SPI,
DLN2_HANDLE_ADC,
DLN2_HANDLES
};
/*
* Receive context used between the receive demultiplexer and the transfer
* routine. While sending a request the transfer routine will look for a free
* receive context and use it to wait for a response and to receive the URB and
* thus the response data.
*/
struct dln2_rx_context {
/* completion used to wait for a response */
struct completion done;
/* if non-NULL the URB contains the response */
struct urb *urb;
/* if true then this context is used to wait for a response */
bool in_use;
};
/*
* Receive contexts for a particular DLN2 module (i2c, gpio, etc.). We use the
* handle header field to identify the module in dln2_dev.mod_rx_slots and then
* the echo header field to index the slots field and find the receive context
* for a particular request.
*/
struct dln2_mod_rx_slots {
/* RX slots bitmap */
DECLARE_BITMAP(bmap, DLN2_MAX_RX_SLOTS);
/* used to wait for a free RX slot */
wait_queue_head_t wq;
/* used to wait for an RX operation to complete */
struct dln2_rx_context slots[DLN2_MAX_RX_SLOTS];
/* avoid races between alloc/free_rx_slot and dln2_rx_transfer */
spinlock_t lock;
};
struct dln2_dev {
struct usb_device *usb_dev;
struct usb_interface *interface;
u8 ep_in;
u8 ep_out;
struct urb *rx_urb[DLN2_MAX_URBS];
void *rx_buf[DLN2_MAX_URBS];
struct dln2_mod_rx_slots mod_rx_slots[DLN2_HANDLES];
struct list_head event_cb_list;
spinlock_t event_cb_lock;
bool disconnect;
int active_transfers;
wait_queue_head_t disconnect_wq;
spinlock_t disconnect_lock;
};
struct dln2_event_cb_entry {
struct list_head list;
u16 id;
struct platform_device *pdev;
dln2_event_cb_t callback;
};
int dln2_register_event_cb(struct platform_device *pdev, u16 id,
dln2_event_cb_t event_cb)
{
struct dln2_dev *dln2 = dev_get_drvdata(pdev->dev.parent);
struct dln2_event_cb_entry *i, *entry;
unsigned long flags;
int ret = 0;
entry = kzalloc(sizeof(*entry), GFP_KERNEL);
if (!entry)
return -ENOMEM;
entry->id = id;
entry->callback = event_cb;
entry->pdev = pdev;
spin_lock_irqsave(&dln2->event_cb_lock, flags);
list_for_each_entry(i, &dln2->event_cb_list, list) {
if (i->id == id) {
ret = -EBUSY;
break;
}
}
if (!ret)
list_add_rcu(&entry->list, &dln2->event_cb_list);
spin_unlock_irqrestore(&dln2->event_cb_lock, flags);
if (ret)
kfree(entry);
return ret;
}
EXPORT_SYMBOL(dln2_register_event_cb);
void dln2_unregister_event_cb(struct platform_device *pdev, u16 id)
{
struct dln2_dev *dln2 = dev_get_drvdata(pdev->dev.parent);
struct dln2_event_cb_entry *i;
unsigned long flags;
bool found = false;
spin_lock_irqsave(&dln2->event_cb_lock, flags);
list_for_each_entry(i, &dln2->event_cb_list, list) {
if (i->id == id) {
list_del_rcu(&i->list);
found = true;
break;
}
}
spin_unlock_irqrestore(&dln2->event_cb_lock, flags);
if (found) {
synchronize_rcu();
kfree(i);
}
}
EXPORT_SYMBOL(dln2_unregister_event_cb);
/*
* Returns true if a valid transfer slot is found. In this case the URB must not
* be resubmitted immediately in dln2_rx as we need the data when dln2_transfer
* is woke up. It will be resubmitted there.
*/
static bool dln2_transfer_complete(struct dln2_dev *dln2, struct urb *urb,
u16 handle, u16 rx_slot)
{
struct device *dev = &dln2->interface->dev;
struct dln2_mod_rx_slots *rxs = &dln2->mod_rx_slots[handle];
struct dln2_rx_context *rxc;
unsigned long flags;
bool valid_slot = false;
if (rx_slot >= DLN2_MAX_RX_SLOTS)
goto out;
rxc = &rxs->slots[rx_slot];
spin_lock_irqsave(&rxs->lock, flags);
if (rxc->in_use && !rxc->urb) {
rxc->urb = urb;
complete(&rxc->done);
valid_slot = true;
}
spin_unlock_irqrestore(&rxs->lock, flags);
out:
if (!valid_slot)
dev_warn(dev, "bad/late response %d/%d\n", handle, rx_slot);
return valid_slot;
}
static void dln2_run_event_callbacks(struct dln2_dev *dln2, u16 id, u16 echo,
void *data, int len)
{
struct dln2_event_cb_entry *i;
rcu_read_lock();
list_for_each_entry_rcu(i, &dln2->event_cb_list, list) {
if (i->id == id) {
i->callback(i->pdev, echo, data, len);
break;
}
}
rcu_read_unlock();
}
static void dln2_rx(struct urb *urb)
{
struct dln2_dev *dln2 = urb->context;
struct dln2_header *hdr = urb->transfer_buffer;
struct device *dev = &dln2->interface->dev;
u16 id, echo, handle, size;
u8 *data;
int len;
int err;
switch (urb->status) {
case 0:
/* success */
break;
case -ECONNRESET:
case -ENOENT:
case -ESHUTDOWN:
case -EPIPE:
/* this urb is terminated, clean up */
dev_dbg(dev, "urb shutting down with status %d\n", urb->status);
return;
default:
dev_dbg(dev, "nonzero urb status received %d\n", urb->status);
goto out;
}
if (urb->actual_length < sizeof(struct dln2_header)) {
dev_err(dev, "short response: %d\n", urb->actual_length);
goto out;
}
handle = le16_to_cpu(hdr->handle);
id = le16_to_cpu(hdr->id);
echo = le16_to_cpu(hdr->echo);
size = le16_to_cpu(hdr->size);
if (size != urb->actual_length) {
dev_err(dev, "size mismatch: handle %x cmd %x echo %x size %d actual %d\n",
handle, id, echo, size, urb->actual_length);
goto out;
}
if (handle >= DLN2_HANDLES) {
dev_warn(dev, "invalid handle %d\n", handle);
goto out;
}
data = urb->transfer_buffer + sizeof(struct dln2_header);
len = urb->actual_length - sizeof(struct dln2_header);
if (handle == DLN2_HANDLE_EVENT) {
unsigned long flags;
spin_lock_irqsave(&dln2->event_cb_lock, flags);
dln2_run_event_callbacks(dln2, id, echo, data, len);
spin_unlock_irqrestore(&dln2->event_cb_lock, flags);
} else {
/* URB will be re-submitted in _dln2_transfer (free_rx_slot) */
if (dln2_transfer_complete(dln2, urb, handle, echo))
return;
}
out:
err = usb_submit_urb(urb, GFP_ATOMIC);
if (err < 0)
dev_err(dev, "failed to resubmit RX URB: %d\n", err);
}
static void *dln2_prep_buf(u16 handle, u16 cmd, u16 echo, const void *obuf,
int *obuf_len, gfp_t gfp)
{
int len;
void *buf;
struct dln2_header *hdr;
len = *obuf_len + sizeof(*hdr);
buf = kmalloc(len, gfp);
if (!buf)
return NULL;
hdr = (struct dln2_header *)buf;
hdr->id = cpu_to_le16(cmd);
hdr->size = cpu_to_le16(len);
hdr->echo = cpu_to_le16(echo);
hdr->handle = cpu_to_le16(handle);
memcpy(buf + sizeof(*hdr), obuf, *obuf_len);
*obuf_len = len;
return buf;
}
static int dln2_send_wait(struct dln2_dev *dln2, u16 handle, u16 cmd, u16 echo,
const void *obuf, int obuf_len)
{
int ret = 0;
int len = obuf_len;
void *buf;
int actual;
buf = dln2_prep_buf(handle, cmd, echo, obuf, &len, GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = usb_bulk_msg(dln2->usb_dev,
usb_sndbulkpipe(dln2->usb_dev, dln2->ep_out),
buf, len, &actual, DLN2_USB_TIMEOUT);
kfree(buf);
return ret;
}
static bool find_free_slot(struct dln2_dev *dln2, u16 handle, int *slot)
{
struct dln2_mod_rx_slots *rxs;
unsigned long flags;
if (dln2->disconnect) {
*slot = -ENODEV;
return true;
}
rxs = &dln2->mod_rx_slots[handle];
spin_lock_irqsave(&rxs->lock, flags);
*slot = find_first_zero_bit(rxs->bmap, DLN2_MAX_RX_SLOTS);
if (*slot < DLN2_MAX_RX_SLOTS) {
struct dln2_rx_context *rxc = &rxs->slots[*slot];
set_bit(*slot, rxs->bmap);
rxc->in_use = true;
}
spin_unlock_irqrestore(&rxs->lock, flags);
return *slot < DLN2_MAX_RX_SLOTS;
}
static int alloc_rx_slot(struct dln2_dev *dln2, u16 handle)
{
int ret;
int slot;
/*
* No need to timeout here, the wait is bounded by the timeout in
* _dln2_transfer.
*/
ret = wait_event_interruptible(dln2->mod_rx_slots[handle].wq,
find_free_slot(dln2, handle, &slot));
if (ret < 0)
return ret;
return slot;
}
static void free_rx_slot(struct dln2_dev *dln2, u16 handle, int slot)
{
struct dln2_mod_rx_slots *rxs;
struct urb *urb = NULL;
unsigned long flags;
struct dln2_rx_context *rxc;
rxs = &dln2->mod_rx_slots[handle];
spin_lock_irqsave(&rxs->lock, flags);
clear_bit(slot, rxs->bmap);
rxc = &rxs->slots[slot];
rxc->in_use = false;
urb = rxc->urb;
rxc->urb = NULL;
reinit_completion(&rxc->done);
spin_unlock_irqrestore(&rxs->lock, flags);
if (urb) {
int err;
struct device *dev = &dln2->interface->dev;
err = usb_submit_urb(urb, GFP_KERNEL);
if (err < 0)
dev_err(dev, "failed to resubmit RX URB: %d\n", err);
}
wake_up_interruptible(&rxs->wq);
}
static int _dln2_transfer(struct dln2_dev *dln2, u16 handle, u16 cmd,
const void *obuf, unsigned obuf_len,
void *ibuf, unsigned *ibuf_len)
{
int ret = 0;
int rx_slot;
struct dln2_response *rsp;
struct dln2_rx_context *rxc;
struct device *dev = &dln2->interface->dev;
const unsigned long timeout = msecs_to_jiffies(DLN2_USB_TIMEOUT);
struct dln2_mod_rx_slots *rxs = &dln2->mod_rx_slots[handle];
int size;
spin_lock(&dln2->disconnect_lock);
if (!dln2->disconnect)
dln2->active_transfers++;
else
ret = -ENODEV;
spin_unlock(&dln2->disconnect_lock);
if (ret)
return ret;
rx_slot = alloc_rx_slot(dln2, handle);
if (rx_slot < 0) {
ret = rx_slot;
goto out_decr;
}
ret = dln2_send_wait(dln2, handle, cmd, rx_slot, obuf, obuf_len);
if (ret < 0) {
dev_err(dev, "USB write failed: %d\n", ret);
goto out_free_rx_slot;
}
rxc = &rxs->slots[rx_slot];
ret = wait_for_completion_interruptible_timeout(&rxc->done, timeout);
if (ret <= 0) {
if (!ret)
ret = -ETIMEDOUT;
goto out_free_rx_slot;
} else {
ret = 0;
}
if (dln2->disconnect) {
ret = -ENODEV;
goto out_free_rx_slot;
}
/* if we got here we know that the response header has been checked */
rsp = rxc->urb->transfer_buffer;
size = le16_to_cpu(rsp->hdr.size);
if (size < sizeof(*rsp)) {
ret = -EPROTO;
goto out_free_rx_slot;
}
if (le16_to_cpu(rsp->result) > 0x80) {
dev_dbg(dev, "%d received response with error %d\n",
handle, le16_to_cpu(rsp->result));
ret = -EREMOTEIO;
goto out_free_rx_slot;
}
if (!ibuf)
goto out_free_rx_slot;
if (*ibuf_len > size - sizeof(*rsp))
*ibuf_len = size - sizeof(*rsp);
memcpy(ibuf, rsp + 1, *ibuf_len);
out_free_rx_slot:
free_rx_slot(dln2, handle, rx_slot);
out_decr:
spin_lock(&dln2->disconnect_lock);
dln2->active_transfers--;
spin_unlock(&dln2->disconnect_lock);
if (dln2->disconnect)
wake_up(&dln2->disconnect_wq);
return ret;
}
int dln2_transfer(struct platform_device *pdev, u16 cmd,
const void *obuf, unsigned obuf_len,
void *ibuf, unsigned *ibuf_len)
{
struct dln2_platform_data *dln2_pdata;
struct dln2_dev *dln2;
u16 handle;
dln2 = dev_get_drvdata(pdev->dev.parent);
dln2_pdata = dev_get_platdata(&pdev->dev);
handle = dln2_pdata->handle;
return _dln2_transfer(dln2, handle, cmd, obuf, obuf_len, ibuf,
ibuf_len);
}
EXPORT_SYMBOL(dln2_transfer);
static int dln2_check_hw(struct dln2_dev *dln2)
{
int ret;
__le32 hw_type;
int len = sizeof(hw_type);
ret = _dln2_transfer(dln2, DLN2_HANDLE_CTRL, CMD_GET_DEVICE_VER,
NULL, 0, &hw_type, &len);
if (ret < 0)
return ret;
if (len < sizeof(hw_type))
return -EREMOTEIO;
if (le32_to_cpu(hw_type) != DLN2_HW_ID) {
dev_err(&dln2->interface->dev, "Device ID 0x%x not supported\n",
le32_to_cpu(hw_type));
return -ENODEV;
}
return 0;
}
static int dln2_print_serialno(struct dln2_dev *dln2)
{
int ret;
__le32 serial_no;
int len = sizeof(serial_no);
struct device *dev = &dln2->interface->dev;
ret = _dln2_transfer(dln2, DLN2_HANDLE_CTRL, CMD_GET_DEVICE_SN, NULL, 0,
&serial_no, &len);
if (ret < 0)
return ret;
if (len < sizeof(serial_no))
return -EREMOTEIO;
dev_info(dev, "Diolan DLN2 serial %u\n", le32_to_cpu(serial_no));
return 0;
}
static int dln2_hw_init(struct dln2_dev *dln2)
{
int ret;
ret = dln2_check_hw(dln2);
if (ret < 0)
return ret;
return dln2_print_serialno(dln2);
}
static void dln2_free_rx_urbs(struct dln2_dev *dln2)
{
int i;
for (i = 0; i < DLN2_MAX_URBS; i++) {
usb_free_urb(dln2->rx_urb[i]);
kfree(dln2->rx_buf[i]);
}
}
static void dln2_stop_rx_urbs(struct dln2_dev *dln2)
{
int i;
for (i = 0; i < DLN2_MAX_URBS; i++)
usb_kill_urb(dln2->rx_urb[i]);
}
static void dln2_free(struct dln2_dev *dln2)
{
dln2_free_rx_urbs(dln2);
usb_put_dev(dln2->usb_dev);
kfree(dln2);
}
static int dln2_setup_rx_urbs(struct dln2_dev *dln2,
struct usb_host_interface *hostif)
{
int i;
const int rx_max_size = DLN2_RX_BUF_SIZE;
for (i = 0; i < DLN2_MAX_URBS; i++) {
dln2->rx_buf[i] = kmalloc(rx_max_size, GFP_KERNEL);
if (!dln2->rx_buf[i])
return -ENOMEM;
dln2->rx_urb[i] = usb_alloc_urb(0, GFP_KERNEL);
if (!dln2->rx_urb[i])
return -ENOMEM;
usb_fill_bulk_urb(dln2->rx_urb[i], dln2->usb_dev,
usb_rcvbulkpipe(dln2->usb_dev, dln2->ep_in),
dln2->rx_buf[i], rx_max_size, dln2_rx, dln2);
}
return 0;
}
static int dln2_start_rx_urbs(struct dln2_dev *dln2, gfp_t gfp)
{
struct device *dev = &dln2->interface->dev;
int ret;
int i;
for (i = 0; i < DLN2_MAX_URBS; i++) {
ret = usb_submit_urb(dln2->rx_urb[i], gfp);
if (ret < 0) {
dev_err(dev, "failed to submit RX URB: %d\n", ret);
return ret;
}
}
return 0;
}
enum {
DLN2_ACPI_MATCH_GPIO = 0,
DLN2_ACPI_MATCH_I2C = 1,
DLN2_ACPI_MATCH_SPI = 2,
DLN2_ACPI_MATCH_ADC = 3,
};
static struct dln2_platform_data dln2_pdata_gpio = {
.handle = DLN2_HANDLE_GPIO,
};
static struct mfd_cell_acpi_match dln2_acpi_match_gpio = {
.adr = DLN2_ACPI_MATCH_GPIO,
};
/* Only one I2C port seems to be supported on current hardware */
static struct dln2_platform_data dln2_pdata_i2c = {
.handle = DLN2_HANDLE_I2C,
.port = 0,
};
static struct mfd_cell_acpi_match dln2_acpi_match_i2c = {
.adr = DLN2_ACPI_MATCH_I2C,
};
/* Only one SPI port supported */
static struct dln2_platform_data dln2_pdata_spi = {
.handle = DLN2_HANDLE_SPI,
.port = 0,
};
static struct mfd_cell_acpi_match dln2_acpi_match_spi = {
.adr = DLN2_ACPI_MATCH_SPI,
};
/* Only one ADC port supported */
static struct dln2_platform_data dln2_pdata_adc = {
.handle = DLN2_HANDLE_ADC,
.port = 0,
};
static struct mfd_cell_acpi_match dln2_acpi_match_adc = {
.adr = DLN2_ACPI_MATCH_ADC,
};
static const struct mfd_cell dln2_devs[] = {
{
.name = "dln2-gpio",
.acpi_match = &dln2_acpi_match_gpio,
.platform_data = &dln2_pdata_gpio,
.pdata_size = sizeof(struct dln2_platform_data),
},
{
.name = "dln2-i2c",
.acpi_match = &dln2_acpi_match_i2c,
.platform_data = &dln2_pdata_i2c,
.pdata_size = sizeof(struct dln2_platform_data),
},
{
.name = "dln2-spi",
.acpi_match = &dln2_acpi_match_spi,
.platform_data = &dln2_pdata_spi,
.pdata_size = sizeof(struct dln2_platform_data),
},
{
.name = "dln2-adc",
.acpi_match = &dln2_acpi_match_adc,
.platform_data = &dln2_pdata_adc,
.pdata_size = sizeof(struct dln2_platform_data),
},
};
static void dln2_stop(struct dln2_dev *dln2)
{
int i, j;
/* don't allow starting new transfers */
spin_lock(&dln2->disconnect_lock);
dln2->disconnect = true;
spin_unlock(&dln2->disconnect_lock);
/* cancel in progress transfers */
for (i = 0; i < DLN2_HANDLES; i++) {
struct dln2_mod_rx_slots *rxs = &dln2->mod_rx_slots[i];
unsigned long flags;
spin_lock_irqsave(&rxs->lock, flags);
/* cancel all response waiters */
for (j = 0; j < DLN2_MAX_RX_SLOTS; j++) {
struct dln2_rx_context *rxc = &rxs->slots[j];
if (rxc->in_use)
complete(&rxc->done);
}
spin_unlock_irqrestore(&rxs->lock, flags);
}
/* wait for transfers to end */
wait_event(dln2->disconnect_wq, !dln2->active_transfers);
dln2_stop_rx_urbs(dln2);
}
static void dln2_disconnect(struct usb_interface *interface)
{
struct dln2_dev *dln2 = usb_get_intfdata(interface);
dln2_stop(dln2);
mfd_remove_devices(&interface->dev);
dln2_free(dln2);
}
static int dln2_probe(struct usb_interface *interface,
const struct usb_device_id *usb_id)
{
struct usb_host_interface *hostif = interface->cur_altsetting;
struct usb_endpoint_descriptor *epin;
struct usb_endpoint_descriptor *epout;
struct device *dev = &interface->dev;
struct dln2_dev *dln2;
int ret;
int i, j;
if (hostif->desc.bInterfaceNumber != 0)
return -ENODEV;
ret = usb_find_common_endpoints(hostif, &epin, &epout, NULL, NULL);
if (ret)
return ret;
dln2 = kzalloc(sizeof(*dln2), GFP_KERNEL);
if (!dln2)
return -ENOMEM;
dln2->ep_out = epout->bEndpointAddress;
dln2->ep_in = epin->bEndpointAddress;
dln2->usb_dev = usb_get_dev(interface_to_usbdev(interface));
dln2->interface = interface;
usb_set_intfdata(interface, dln2);
init_waitqueue_head(&dln2->disconnect_wq);
for (i = 0; i < DLN2_HANDLES; i++) {
init_waitqueue_head(&dln2->mod_rx_slots[i].wq);
spin_lock_init(&dln2->mod_rx_slots[i].lock);
for (j = 0; j < DLN2_MAX_RX_SLOTS; j++)
init_completion(&dln2->mod_rx_slots[i].slots[j].done);
}
spin_lock_init(&dln2->event_cb_lock);
spin_lock_init(&dln2->disconnect_lock);
INIT_LIST_HEAD(&dln2->event_cb_list);
ret = dln2_setup_rx_urbs(dln2, hostif);
if (ret)
goto out_free;
ret = dln2_start_rx_urbs(dln2, GFP_KERNEL);
if (ret)
goto out_stop_rx;
ret = dln2_hw_init(dln2);
if (ret < 0) {
dev_err(dev, "failed to initialize hardware\n");
goto out_stop_rx;
}
ret = mfd_add_hotplug_devices(dev, dln2_devs, ARRAY_SIZE(dln2_devs));
if (ret != 0) {
dev_err(dev, "failed to add mfd devices to core\n");
goto out_stop_rx;
}
return 0;
out_stop_rx:
dln2_stop_rx_urbs(dln2);
out_free:
usb_put_dev(dln2->usb_dev);
dln2_free(dln2);
return ret;
}
static int dln2_suspend(struct usb_interface *iface, pm_message_t message)
{
struct dln2_dev *dln2 = usb_get_intfdata(iface);
dln2_stop(dln2);
return 0;
}
static int dln2_resume(struct usb_interface *iface)
{
struct dln2_dev *dln2 = usb_get_intfdata(iface);
dln2->disconnect = false;
return dln2_start_rx_urbs(dln2, GFP_NOIO);
}
static const struct usb_device_id dln2_table[] = {
{ USB_DEVICE(0xa257, 0x2013) },
{ }
};
MODULE_DEVICE_TABLE(usb, dln2_table);
static struct usb_driver dln2_driver = {
.name = "dln2",
.probe = dln2_probe,
.disconnect = dln2_disconnect,
.id_table = dln2_table,
.suspend = dln2_suspend,
.resume = dln2_resume,
};
module_usb_driver(dln2_driver);
MODULE_AUTHOR("Octavian Purdila <[email protected]>");
MODULE_DESCRIPTION("Core driver for the Diolan DLN2 interface adapter");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/dln2.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Device access for Dialog DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <[email protected]>
*/
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/mfd/da9052/da9052.h>
#include <linux/mfd/da9052/pdata.h>
#include <linux/mfd/da9052/reg.h>
static bool da9052_reg_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA9052_PAGE0_CON_REG:
case DA9052_STATUS_A_REG:
case DA9052_STATUS_B_REG:
case DA9052_STATUS_C_REG:
case DA9052_STATUS_D_REG:
case DA9052_EVENT_A_REG:
case DA9052_EVENT_B_REG:
case DA9052_EVENT_C_REG:
case DA9052_EVENT_D_REG:
case DA9052_FAULTLOG_REG:
case DA9052_IRQ_MASK_A_REG:
case DA9052_IRQ_MASK_B_REG:
case DA9052_IRQ_MASK_C_REG:
case DA9052_IRQ_MASK_D_REG:
case DA9052_CONTROL_A_REG:
case DA9052_CONTROL_B_REG:
case DA9052_CONTROL_C_REG:
case DA9052_CONTROL_D_REG:
case DA9052_PDDIS_REG:
case DA9052_INTERFACE_REG:
case DA9052_RESET_REG:
case DA9052_GPIO_0_1_REG:
case DA9052_GPIO_2_3_REG:
case DA9052_GPIO_4_5_REG:
case DA9052_GPIO_6_7_REG:
case DA9052_GPIO_8_9_REG:
case DA9052_GPIO_10_11_REG:
case DA9052_GPIO_12_13_REG:
case DA9052_GPIO_14_15_REG:
case DA9052_ID_0_1_REG:
case DA9052_ID_2_3_REG:
case DA9052_ID_4_5_REG:
case DA9052_ID_6_7_REG:
case DA9052_ID_8_9_REG:
case DA9052_ID_10_11_REG:
case DA9052_ID_12_13_REG:
case DA9052_ID_14_15_REG:
case DA9052_ID_16_17_REG:
case DA9052_ID_18_19_REG:
case DA9052_ID_20_21_REG:
case DA9052_SEQ_STATUS_REG:
case DA9052_SEQ_A_REG:
case DA9052_SEQ_B_REG:
case DA9052_SEQ_TIMER_REG:
case DA9052_BUCKA_REG:
case DA9052_BUCKB_REG:
case DA9052_BUCKCORE_REG:
case DA9052_BUCKPRO_REG:
case DA9052_BUCKMEM_REG:
case DA9052_BUCKPERI_REG:
case DA9052_LDO1_REG:
case DA9052_LDO2_REG:
case DA9052_LDO3_REG:
case DA9052_LDO4_REG:
case DA9052_LDO5_REG:
case DA9052_LDO6_REG:
case DA9052_LDO7_REG:
case DA9052_LDO8_REG:
case DA9052_LDO9_REG:
case DA9052_LDO10_REG:
case DA9052_SUPPLY_REG:
case DA9052_PULLDOWN_REG:
case DA9052_CHGBUCK_REG:
case DA9052_WAITCONT_REG:
case DA9052_ISET_REG:
case DA9052_BATCHG_REG:
case DA9052_CHG_CONT_REG:
case DA9052_INPUT_CONT_REG:
case DA9052_CHG_TIME_REG:
case DA9052_BBAT_CONT_REG:
case DA9052_BOOST_REG:
case DA9052_LED_CONT_REG:
case DA9052_LEDMIN123_REG:
case DA9052_LED1_CONF_REG:
case DA9052_LED2_CONF_REG:
case DA9052_LED3_CONF_REG:
case DA9052_LED1CONT_REG:
case DA9052_LED2CONT_REG:
case DA9052_LED3CONT_REG:
case DA9052_LED_CONT_4_REG:
case DA9052_LED_CONT_5_REG:
case DA9052_ADC_MAN_REG:
case DA9052_ADC_CONT_REG:
case DA9052_ADC_RES_L_REG:
case DA9052_ADC_RES_H_REG:
case DA9052_VDD_RES_REG:
case DA9052_VDD_MON_REG:
case DA9052_ICHG_AV_REG:
case DA9052_ICHG_THD_REG:
case DA9052_ICHG_END_REG:
case DA9052_TBAT_RES_REG:
case DA9052_TBAT_HIGHP_REG:
case DA9052_TBAT_HIGHN_REG:
case DA9052_TBAT_LOW_REG:
case DA9052_T_OFFSET_REG:
case DA9052_ADCIN4_RES_REG:
case DA9052_AUTO4_HIGH_REG:
case DA9052_AUTO4_LOW_REG:
case DA9052_ADCIN5_RES_REG:
case DA9052_AUTO5_HIGH_REG:
case DA9052_AUTO5_LOW_REG:
case DA9052_ADCIN6_RES_REG:
case DA9052_AUTO6_HIGH_REG:
case DA9052_AUTO6_LOW_REG:
case DA9052_TJUNC_RES_REG:
case DA9052_TSI_CONT_A_REG:
case DA9052_TSI_CONT_B_REG:
case DA9052_TSI_X_MSB_REG:
case DA9052_TSI_Y_MSB_REG:
case DA9052_TSI_LSB_REG:
case DA9052_TSI_Z_MSB_REG:
case DA9052_COUNT_S_REG:
case DA9052_COUNT_MI_REG:
case DA9052_COUNT_H_REG:
case DA9052_COUNT_D_REG:
case DA9052_COUNT_MO_REG:
case DA9052_COUNT_Y_REG:
case DA9052_ALARM_MI_REG:
case DA9052_ALARM_H_REG:
case DA9052_ALARM_D_REG:
case DA9052_ALARM_MO_REG:
case DA9052_ALARM_Y_REG:
case DA9052_SECOND_A_REG:
case DA9052_SECOND_B_REG:
case DA9052_SECOND_C_REG:
case DA9052_SECOND_D_REG:
case DA9052_PAGE1_CON_REG:
return true;
default:
return false;
}
}
static bool da9052_reg_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA9052_PAGE0_CON_REG:
case DA9052_EVENT_A_REG:
case DA9052_EVENT_B_REG:
case DA9052_EVENT_C_REG:
case DA9052_EVENT_D_REG:
case DA9052_FAULTLOG_REG:
case DA9052_IRQ_MASK_A_REG:
case DA9052_IRQ_MASK_B_REG:
case DA9052_IRQ_MASK_C_REG:
case DA9052_IRQ_MASK_D_REG:
case DA9052_CONTROL_A_REG:
case DA9052_CONTROL_B_REG:
case DA9052_CONTROL_C_REG:
case DA9052_CONTROL_D_REG:
case DA9052_PDDIS_REG:
case DA9052_RESET_REG:
case DA9052_GPIO_0_1_REG:
case DA9052_GPIO_2_3_REG:
case DA9052_GPIO_4_5_REG:
case DA9052_GPIO_6_7_REG:
case DA9052_GPIO_8_9_REG:
case DA9052_GPIO_10_11_REG:
case DA9052_GPIO_12_13_REG:
case DA9052_GPIO_14_15_REG:
case DA9052_ID_0_1_REG:
case DA9052_ID_2_3_REG:
case DA9052_ID_4_5_REG:
case DA9052_ID_6_7_REG:
case DA9052_ID_8_9_REG:
case DA9052_ID_10_11_REG:
case DA9052_ID_12_13_REG:
case DA9052_ID_14_15_REG:
case DA9052_ID_16_17_REG:
case DA9052_ID_18_19_REG:
case DA9052_ID_20_21_REG:
case DA9052_SEQ_STATUS_REG:
case DA9052_SEQ_A_REG:
case DA9052_SEQ_B_REG:
case DA9052_SEQ_TIMER_REG:
case DA9052_BUCKA_REG:
case DA9052_BUCKB_REG:
case DA9052_BUCKCORE_REG:
case DA9052_BUCKPRO_REG:
case DA9052_BUCKMEM_REG:
case DA9052_BUCKPERI_REG:
case DA9052_LDO1_REG:
case DA9052_LDO2_REG:
case DA9052_LDO3_REG:
case DA9052_LDO4_REG:
case DA9052_LDO5_REG:
case DA9052_LDO6_REG:
case DA9052_LDO7_REG:
case DA9052_LDO8_REG:
case DA9052_LDO9_REG:
case DA9052_LDO10_REG:
case DA9052_SUPPLY_REG:
case DA9052_PULLDOWN_REG:
case DA9052_CHGBUCK_REG:
case DA9052_WAITCONT_REG:
case DA9052_ISET_REG:
case DA9052_BATCHG_REG:
case DA9052_CHG_CONT_REG:
case DA9052_INPUT_CONT_REG:
case DA9052_BBAT_CONT_REG:
case DA9052_BOOST_REG:
case DA9052_LED_CONT_REG:
case DA9052_LEDMIN123_REG:
case DA9052_LED1_CONF_REG:
case DA9052_LED2_CONF_REG:
case DA9052_LED3_CONF_REG:
case DA9052_LED1CONT_REG:
case DA9052_LED2CONT_REG:
case DA9052_LED3CONT_REG:
case DA9052_LED_CONT_4_REG:
case DA9052_LED_CONT_5_REG:
case DA9052_ADC_MAN_REG:
case DA9052_ADC_CONT_REG:
case DA9052_ADC_RES_L_REG:
case DA9052_ADC_RES_H_REG:
case DA9052_VDD_RES_REG:
case DA9052_VDD_MON_REG:
case DA9052_ICHG_THD_REG:
case DA9052_ICHG_END_REG:
case DA9052_TBAT_HIGHP_REG:
case DA9052_TBAT_HIGHN_REG:
case DA9052_TBAT_LOW_REG:
case DA9052_T_OFFSET_REG:
case DA9052_AUTO4_HIGH_REG:
case DA9052_AUTO4_LOW_REG:
case DA9052_AUTO5_HIGH_REG:
case DA9052_AUTO5_LOW_REG:
case DA9052_AUTO6_HIGH_REG:
case DA9052_AUTO6_LOW_REG:
case DA9052_TSI_CONT_A_REG:
case DA9052_TSI_CONT_B_REG:
case DA9052_COUNT_S_REG:
case DA9052_COUNT_MI_REG:
case DA9052_COUNT_H_REG:
case DA9052_COUNT_D_REG:
case DA9052_COUNT_MO_REG:
case DA9052_COUNT_Y_REG:
case DA9052_ALARM_MI_REG:
case DA9052_ALARM_H_REG:
case DA9052_ALARM_D_REG:
case DA9052_ALARM_MO_REG:
case DA9052_ALARM_Y_REG:
case DA9052_PAGE1_CON_REG:
return true;
default:
return false;
}
}
static bool da9052_reg_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA9052_STATUS_A_REG:
case DA9052_STATUS_B_REG:
case DA9052_STATUS_C_REG:
case DA9052_STATUS_D_REG:
case DA9052_EVENT_A_REG:
case DA9052_EVENT_B_REG:
case DA9052_EVENT_C_REG:
case DA9052_EVENT_D_REG:
case DA9052_CONTROL_B_REG:
case DA9052_CONTROL_D_REG:
case DA9052_SUPPLY_REG:
case DA9052_FAULTLOG_REG:
case DA9052_CHG_TIME_REG:
case DA9052_ADC_RES_L_REG:
case DA9052_ADC_RES_H_REG:
case DA9052_VDD_RES_REG:
case DA9052_ICHG_AV_REG:
case DA9052_TBAT_RES_REG:
case DA9052_ADCIN4_RES_REG:
case DA9052_ADCIN5_RES_REG:
case DA9052_ADCIN6_RES_REG:
case DA9052_TJUNC_RES_REG:
case DA9052_TSI_X_MSB_REG:
case DA9052_TSI_Y_MSB_REG:
case DA9052_TSI_LSB_REG:
case DA9052_TSI_Z_MSB_REG:
case DA9052_COUNT_S_REG:
case DA9052_COUNT_MI_REG:
case DA9052_COUNT_H_REG:
case DA9052_COUNT_D_REG:
case DA9052_COUNT_MO_REG:
case DA9052_COUNT_Y_REG:
case DA9052_ALARM_MI_REG:
return true;
default:
return false;
}
}
/*
* TBAT look-up table is computed from the R90 reg (8 bit register)
* reading as below. The battery temperature is in milliCentigrade
* TBAT = (1/(t1+1/298) - 273) * 1000 mC
* where t1 = (1/B)* ln(( ADCval * 2.5)/(R25*ITBAT*255))
* Default values are R25 = 10e3, B = 3380, ITBAT = 50e-6
* Example:
* R25=10E3, B=3380, ITBAT=50e-6, ADCVAL=62d calculates
* TBAT = 20015 mili degrees Centrigrade
*
*/
static const int32_t tbat_lookup[255] = {
183258, 144221, 124334, 111336, 101826, 94397, 88343, 83257,
78889, 75071, 71688, 68656, 65914, 63414, 61120, 59001,
570366, 55204, 53490, 51881, 50364, 48931, 47574, 46285,
45059, 43889, 42772, 41703, 40678, 39694, 38748, 37838,
36961, 36115, 35297, 34507, 33743, 33002, 32284, 31588,
30911, 30254, 29615, 28994, 28389, 27799, 27225, 26664,
26117, 25584, 25062, 24553, 24054, 23567, 23091, 22624,
22167, 21719, 21281, 20851, 20429, 20015, 19610, 19211,
18820, 18436, 18058, 17688, 17323, 16965, 16612, 16266,
15925, 15589, 15259, 14933, 14613, 14298, 13987, 13681,
13379, 13082, 12788, 12499, 12214, 11933, 11655, 11382,
11112, 10845, 10582, 10322, 10066, 9812, 9562, 9315,
9071, 8830, 8591, 8356, 8123, 7893, 7665, 7440,
7218, 6998, 6780, 6565, 6352, 6141, 5933, 5726,
5522, 5320, 5120, 4922, 4726, 4532, 4340, 4149,
3961, 3774, 3589, 3406, 3225, 3045, 2867, 2690,
2516, 2342, 2170, 2000, 1831, 1664, 1498, 1334,
1171, 1009, 849, 690, 532, 376, 221, 67,
-84, -236, -386, -535, -683, -830, -975, -1119,
-1263, -1405, -1546, -1686, -1825, -1964, -2101, -2237,
-2372, -2506, -2639, -2771, -2902, -3033, -3162, -3291,
-3418, -3545, -3671, -3796, -3920, -4044, -4166, -4288,
-4409, -4529, -4649, -4767, -4885, -5002, -5119, -5235,
-5349, -5464, -5577, -5690, -5802, -5913, -6024, -6134,
-6244, -6352, -6461, -6568, -6675, -6781, -6887, -6992,
-7096, -7200, -7303, -7406, -7508, -7609, -7710, -7810,
-7910, -8009, -8108, -8206, -8304, -8401, -8497, -8593,
-8689, -8784, -8878, -8972, -9066, -9159, -9251, -9343,
-9435, -9526, -9617, -9707, -9796, -9886, -9975, -10063,
-10151, -10238, -10325, -10412, -10839, -10923, -11007, -11090,
-11173, -11256, -11338, -11420, -11501, -11583, -11663, -11744,
-11823, -11903, -11982
};
static const u8 chan_mux[DA9052_ADC_VBBAT + 1] = {
[DA9052_ADC_VDDOUT] = DA9052_ADC_MAN_MUXSEL_VDDOUT,
[DA9052_ADC_ICH] = DA9052_ADC_MAN_MUXSEL_ICH,
[DA9052_ADC_TBAT] = DA9052_ADC_MAN_MUXSEL_TBAT,
[DA9052_ADC_VBAT] = DA9052_ADC_MAN_MUXSEL_VBAT,
[DA9052_ADC_IN4] = DA9052_ADC_MAN_MUXSEL_AD4,
[DA9052_ADC_IN5] = DA9052_ADC_MAN_MUXSEL_AD5,
[DA9052_ADC_IN6] = DA9052_ADC_MAN_MUXSEL_AD6,
[DA9052_ADC_VBBAT] = DA9052_ADC_MAN_MUXSEL_VBBAT
};
int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel)
{
int ret;
unsigned short calc_data;
unsigned short data;
unsigned char mux_sel;
if (channel > DA9052_ADC_VBBAT)
return -EINVAL;
mutex_lock(&da9052->auxadc_lock);
reinit_completion(&da9052->done);
/* Channel gets activated on enabling the Conversion bit */
mux_sel = chan_mux[channel] | DA9052_ADC_MAN_MAN_CONV;
ret = da9052_reg_write(da9052, DA9052_ADC_MAN_REG, mux_sel);
if (ret < 0)
goto err;
/* Wait for an interrupt */
if (!wait_for_completion_timeout(&da9052->done,
msecs_to_jiffies(500))) {
dev_err(da9052->dev,
"timeout waiting for ADC conversion interrupt\n");
ret = -ETIMEDOUT;
goto err;
}
ret = da9052_reg_read(da9052, DA9052_ADC_RES_H_REG);
if (ret < 0)
goto err;
calc_data = (unsigned short)ret;
data = calc_data << 2;
ret = da9052_reg_read(da9052, DA9052_ADC_RES_L_REG);
if (ret < 0)
goto err;
calc_data = (unsigned short)(ret & DA9052_ADC_RES_LSB);
data |= calc_data;
ret = data;
err:
mutex_unlock(&da9052->auxadc_lock);
return ret;
}
EXPORT_SYMBOL_GPL(da9052_adc_manual_read);
int da9052_adc_read_temp(struct da9052 *da9052)
{
int tbat;
tbat = da9052_reg_read(da9052, DA9052_TBAT_RES_REG);
if (tbat <= 0)
return tbat;
/* ARRAY_SIZE check is not needed since TBAT is a 8-bit register */
return tbat_lookup[tbat - 1];
}
EXPORT_SYMBOL_GPL(da9052_adc_read_temp);
static const struct mfd_cell da9052_subdev_info[] = {
{
.name = "da9052-regulator",
.id = 0,
},
{
.name = "da9052-regulator",
.id = 1,
},
{
.name = "da9052-regulator",
.id = 2,
},
{
.name = "da9052-regulator",
.id = 3,
},
{
.name = "da9052-regulator",
.id = 4,
},
{
.name = "da9052-regulator",
.id = 5,
},
{
.name = "da9052-regulator",
.id = 6,
},
{
.name = "da9052-regulator",
.id = 7,
},
{
.name = "da9052-regulator",
.id = 8,
},
{
.name = "da9052-regulator",
.id = 9,
},
{
.name = "da9052-regulator",
.id = 10,
},
{
.name = "da9052-regulator",
.id = 11,
},
{
.name = "da9052-regulator",
.id = 12,
},
{
.name = "da9052-regulator",
.id = 13,
},
{
.name = "da9052-onkey",
},
{
.name = "da9052-rtc",
},
{
.name = "da9052-gpio",
},
{
.name = "da9052-hwmon",
},
{
.name = "da9052-leds",
},
{
.name = "da9052-wled1",
},
{
.name = "da9052-wled2",
},
{
.name = "da9052-wled3",
},
{
.name = "da9052-bat",
},
{
.name = "da9052-watchdog",
},
};
static const struct mfd_cell da9052_tsi_subdev_info[] = {
{ .name = "da9052-tsi" },
};
const struct regmap_config da9052_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.max_register = DA9052_PAGE1_CON_REG,
.readable_reg = da9052_reg_readable,
.writeable_reg = da9052_reg_writeable,
.volatile_reg = da9052_reg_volatile,
};
EXPORT_SYMBOL_GPL(da9052_regmap_config);
static int da9052_clear_fault_log(struct da9052 *da9052)
{
int ret = 0;
int fault_log = 0;
fault_log = da9052_reg_read(da9052, DA9052_FAULTLOG_REG);
if (fault_log < 0) {
dev_err(da9052->dev,
"Cannot read FAULT_LOG %d\n", fault_log);
return fault_log;
}
if (fault_log) {
if (fault_log & DA9052_FAULTLOG_TWDERROR)
dev_dbg(da9052->dev,
"Fault log entry detected: TWD_ERROR\n");
if (fault_log & DA9052_FAULTLOG_VDDFAULT)
dev_dbg(da9052->dev,
"Fault log entry detected: VDD_FAULT\n");
if (fault_log & DA9052_FAULTLOG_VDDSTART)
dev_dbg(da9052->dev,
"Fault log entry detected: VDD_START\n");
if (fault_log & DA9052_FAULTLOG_TEMPOVER)
dev_dbg(da9052->dev,
"Fault log entry detected: TEMP_OVER\n");
if (fault_log & DA9052_FAULTLOG_KEYSHUT)
dev_dbg(da9052->dev,
"Fault log entry detected: KEY_SHUT\n");
if (fault_log & DA9052_FAULTLOG_NSDSET)
dev_dbg(da9052->dev,
"Fault log entry detected: nSD_SHUT\n");
if (fault_log & DA9052_FAULTLOG_WAITSET)
dev_dbg(da9052->dev,
"Fault log entry detected: WAIT_SHUT\n");
ret = da9052_reg_write(da9052,
DA9052_FAULTLOG_REG,
0xFF);
if (ret < 0)
dev_err(da9052->dev,
"Cannot reset FAULT_LOG values %d\n", ret);
}
return ret;
}
int da9052_device_init(struct da9052 *da9052, u8 chip_id)
{
struct da9052_pdata *pdata = dev_get_platdata(da9052->dev);
int ret;
mutex_init(&da9052->auxadc_lock);
init_completion(&da9052->done);
ret = da9052_clear_fault_log(da9052);
if (ret < 0)
dev_warn(da9052->dev, "Cannot clear FAULT_LOG\n");
if (pdata && pdata->init != NULL)
pdata->init(da9052);
da9052->chip_id = chip_id;
ret = da9052_irq_init(da9052);
if (ret != 0) {
dev_err(da9052->dev, "da9052_irq_init failed: %d\n", ret);
return ret;
}
ret = mfd_add_devices(da9052->dev, PLATFORM_DEVID_AUTO,
da9052_subdev_info,
ARRAY_SIZE(da9052_subdev_info), NULL, 0, NULL);
if (ret) {
dev_err(da9052->dev, "mfd_add_devices failed: %d\n", ret);
goto err;
}
/*
* Check if touchscreen pins are used are analogue input instead
* of having a touchscreen connected to them. The analogue input
* functionality will be provided by hwmon driver (if enabled).
*/
if (!device_property_read_bool(da9052->dev, "dlg,tsi-as-adc")) {
ret = mfd_add_devices(da9052->dev, PLATFORM_DEVID_AUTO,
da9052_tsi_subdev_info,
ARRAY_SIZE(da9052_tsi_subdev_info),
NULL, 0, NULL);
if (ret) {
dev_err(da9052->dev, "failed to add TSI subdev: %d\n",
ret);
goto err;
}
}
return 0;
err:
mfd_remove_devices(da9052->dev);
da9052_irq_exit(da9052);
return ret;
}
void da9052_device_exit(struct da9052 *da9052)
{
mfd_remove_devices(da9052->dev);
da9052_irq_exit(da9052);
}
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
MODULE_DESCRIPTION("DA9052 MFD Core");
| linux-master | drivers/mfd/da9052-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* omap-usb-tll.c - The USB TLL driver for OMAP EHCI & OHCI
*
* Copyright (C) 2012-2013 Texas Instruments Incorporated - https://www.ti.com
* Author: Keshava Munegowda <[email protected]>
* Author: Roger Quadros <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/usb-omap.h>
#include <linux/of.h>
#include "omap-usb.h"
#define USBTLL_DRIVER_NAME "usbhs_tll"
/* TLL Register Set */
#define OMAP_USBTLL_REVISION (0x00)
#define OMAP_USBTLL_SYSCONFIG (0x10)
#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
#define OMAP_USBTLL_SYSSTATUS (0x14)
#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
#define OMAP_USBTLL_IRQSTATUS (0x18)
#define OMAP_USBTLL_IRQENABLE (0x1C)
#define OMAP_TLL_SHARED_CONF (0x30)
#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
#define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16)
#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15)
#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
#define OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI (2 << 1)
#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
#define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
#define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
#define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
#define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
#define OMAP_REV2_TLL_CHANNEL_COUNT 2
#define OMAP_TLL_CHANNEL_COUNT 3
#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
/* Values of USBTLL_REVISION - Note: these are not given in the TRM */
#define OMAP_USBTLL_REV1 0x00000015 /* OMAP3 */
#define OMAP_USBTLL_REV2 0x00000018 /* OMAP 3630 */
#define OMAP_USBTLL_REV3 0x00000004 /* OMAP4 */
#define OMAP_USBTLL_REV4 0x00000006 /* OMAP5 */
#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
/* only PHY and UNUSED modes don't need TLL */
#define omap_usb_mode_needs_tll(x) ((x) != OMAP_USBHS_PORT_MODE_UNUSED &&\
(x) != OMAP_EHCI_PORT_MODE_PHY)
struct usbtll_omap {
void __iomem *base;
int nch; /* num. of channels */
struct clk *ch_clk[]; /* must be the last member */
};
/*-------------------------------------------------------------------------*/
static const char usbtll_driver_name[] = USBTLL_DRIVER_NAME;
static struct device *tll_dev;
static DEFINE_SPINLOCK(tll_lock); /* serialize access to tll_dev */
/*-------------------------------------------------------------------------*/
static inline void usbtll_write(void __iomem *base, u32 reg, u32 val)
{
writel_relaxed(val, base + reg);
}
static inline u32 usbtll_read(void __iomem *base, u32 reg)
{
return readl_relaxed(base + reg);
}
static inline void usbtll_writeb(void __iomem *base, u32 reg, u8 val)
{
writeb_relaxed(val, base + reg);
}
/*-------------------------------------------------------------------------*/
static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
{
switch (pmode) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
return true;
default:
return false;
}
}
/*
* convert the port-mode enum to a value we can use in the FSLSMODE
* field of USBTLL_CHANNEL_CONF
*/
static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
{
switch (mode) {
case OMAP_USBHS_PORT_MODE_UNUSED:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
return OMAP_TLL_FSLSMODE_3PIN_PHY;
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
return OMAP_TLL_FSLSMODE_4PIN_PHY;
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
return OMAP_TLL_FSLSMODE_3PIN_TLL;
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
return OMAP_TLL_FSLSMODE_4PIN_TLL;
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
default:
pr_warn("Invalid port mode, using default\n");
return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
}
}
/**
* usbtll_omap_probe - initialize TI-based HCDs
*
* Allocates basic resources for this USB host controller.
*
* @pdev: Pointer to this device's platform device structure
*/
static int usbtll_omap_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct usbtll_omap *tll;
void __iomem *base;
int i, nch, ver;
dev_dbg(dev, "starting TI HSUSB TLL Controller\n");
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
ver = usbtll_read(base, OMAP_USBTLL_REVISION);
switch (ver) {
case OMAP_USBTLL_REV1:
case OMAP_USBTLL_REV4:
nch = OMAP_TLL_CHANNEL_COUNT;
break;
case OMAP_USBTLL_REV2:
case OMAP_USBTLL_REV3:
nch = OMAP_REV2_TLL_CHANNEL_COUNT;
break;
default:
nch = OMAP_TLL_CHANNEL_COUNT;
dev_dbg(dev, "rev 0x%x not recognized, assuming %d channels\n",
ver, nch);
break;
}
tll = devm_kzalloc(dev, sizeof(*tll) + sizeof(tll->ch_clk[nch]),
GFP_KERNEL);
if (!tll) {
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
return -ENOMEM;
}
tll->base = base;
tll->nch = nch;
platform_set_drvdata(pdev, tll);
for (i = 0; i < nch; i++) {
char clkname[] = "usb_tll_hs_usb_chx_clk";
snprintf(clkname, sizeof(clkname),
"usb_tll_hs_usb_ch%d_clk", i);
tll->ch_clk[i] = clk_get(dev, clkname);
if (IS_ERR(tll->ch_clk[i]))
dev_dbg(dev, "can't get clock : %s\n", clkname);
else
clk_prepare(tll->ch_clk[i]);
}
pm_runtime_put_sync(dev);
/* only after this can omap_tll_enable/disable work */
spin_lock(&tll_lock);
tll_dev = dev;
spin_unlock(&tll_lock);
return 0;
}
/**
* usbtll_omap_remove - shutdown processing for UHH & TLL HCDs
* @pdev: USB Host Controller being removed
*
* Reverses the effect of usbtll_omap_probe().
*/
static int usbtll_omap_remove(struct platform_device *pdev)
{
struct usbtll_omap *tll = platform_get_drvdata(pdev);
int i;
spin_lock(&tll_lock);
tll_dev = NULL;
spin_unlock(&tll_lock);
for (i = 0; i < tll->nch; i++) {
if (!IS_ERR(tll->ch_clk[i])) {
clk_unprepare(tll->ch_clk[i]);
clk_put(tll->ch_clk[i]);
}
}
pm_runtime_disable(&pdev->dev);
return 0;
}
static const struct of_device_id usbtll_omap_dt_ids[] = {
{ .compatible = "ti,usbhs-tll" },
{ }
};
MODULE_DEVICE_TABLE(of, usbtll_omap_dt_ids);
static struct platform_driver usbtll_omap_driver = {
.driver = {
.name = usbtll_driver_name,
.of_match_table = usbtll_omap_dt_ids,
},
.probe = usbtll_omap_probe,
.remove = usbtll_omap_remove,
};
int omap_tll_init(struct usbhs_omap_platform_data *pdata)
{
int i;
bool needs_tll;
unsigned reg;
struct usbtll_omap *tll;
if (!tll_dev)
return -ENODEV;
pm_runtime_get_sync(tll_dev);
spin_lock(&tll_lock);
tll = dev_get_drvdata(tll_dev);
needs_tll = false;
for (i = 0; i < tll->nch; i++)
needs_tll |= omap_usb_mode_needs_tll(pdata->port_mode[i]);
if (needs_tll) {
void __iomem *base = tll->base;
/* Program Common TLL register */
reg = usbtll_read(base, OMAP_TLL_SHARED_CONF);
reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
| OMAP_TLL_SHARED_CONF_USB_DIVRATION);
reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
usbtll_write(base, OMAP_TLL_SHARED_CONF, reg);
/* Enable channels now */
for (i = 0; i < tll->nch; i++) {
reg = usbtll_read(base, OMAP_TLL_CHANNEL_CONF(i));
if (is_ohci_port(pdata->port_mode[i])) {
reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
<< OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
} else if (pdata->port_mode[i] ==
OMAP_EHCI_PORT_MODE_TLL) {
/*
* Disable UTMI AutoIdle, BitStuffing
* and use SDR Mode. Enable ULPI AutoIdle.
*/
reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
| OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
reg |= OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
reg |= OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE;
} else if (pdata->port_mode[i] ==
OMAP_EHCI_PORT_MODE_HSIC) {
/*
* HSIC Mode requires UTMI port configurations
*/
reg |= OMAP_TLL_CHANNEL_CONF_DRVVBUS
| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
| OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI
| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
} else {
continue;
}
reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
usbtll_write(base, OMAP_TLL_CHANNEL_CONF(i), reg);
usbtll_writeb(base,
OMAP_TLL_ULPI_SCRATCH_REGISTER(i),
0xbe);
}
}
spin_unlock(&tll_lock);
pm_runtime_put_sync(tll_dev);
return 0;
}
EXPORT_SYMBOL_GPL(omap_tll_init);
int omap_tll_enable(struct usbhs_omap_platform_data *pdata)
{
int i;
struct usbtll_omap *tll;
if (!tll_dev)
return -ENODEV;
pm_runtime_get_sync(tll_dev);
spin_lock(&tll_lock);
tll = dev_get_drvdata(tll_dev);
for (i = 0; i < tll->nch; i++) {
if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
int r;
if (IS_ERR(tll->ch_clk[i]))
continue;
r = clk_enable(tll->ch_clk[i]);
if (r) {
dev_err(tll_dev,
"Error enabling ch %d clock: %d\n", i, r);
}
}
}
spin_unlock(&tll_lock);
return 0;
}
EXPORT_SYMBOL_GPL(omap_tll_enable);
int omap_tll_disable(struct usbhs_omap_platform_data *pdata)
{
int i;
struct usbtll_omap *tll;
if (!tll_dev)
return -ENODEV;
spin_lock(&tll_lock);
tll = dev_get_drvdata(tll_dev);
for (i = 0; i < tll->nch; i++) {
if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
if (!IS_ERR(tll->ch_clk[i]))
clk_disable(tll->ch_clk[i]);
}
}
spin_unlock(&tll_lock);
pm_runtime_put_sync(tll_dev);
return 0;
}
EXPORT_SYMBOL_GPL(omap_tll_disable);
MODULE_AUTHOR("Keshava Munegowda <[email protected]>");
MODULE_AUTHOR("Roger Quadros <[email protected]>");
MODULE_DESCRIPTION("usb tll driver for TI OMAP EHCI and OHCI controllers");
static int __init omap_usbtll_drvinit(void)
{
return platform_driver_register(&usbtll_omap_driver);
}
/*
* init before usbhs core driver;
* The usbtll driver should be initialized before
* the usbhs core driver probe function is called.
*/
fs_initcall(omap_usbtll_drvinit);
static void __exit omap_usbtll_drvexit(void)
{
platform_driver_unregister(&usbtll_omap_driver);
}
module_exit(omap_usbtll_drvexit);
| linux-master | drivers/mfd/omap-usb-tll.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Broadcom BCM590xx PMU
*
* Copyright 2014 Linaro Limited
* Author: Matt Porter <[email protected]>
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/mfd/bcm590xx.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
static const struct mfd_cell bcm590xx_devs[] = {
{
.name = "bcm590xx-vregs",
},
};
static const struct regmap_config bcm590xx_regmap_config_pri = {
.reg_bits = 8,
.val_bits = 8,
.max_register = BCM590XX_MAX_REGISTER_PRI,
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_config bcm590xx_regmap_config_sec = {
.reg_bits = 8,
.val_bits = 8,
.max_register = BCM590XX_MAX_REGISTER_SEC,
.cache_type = REGCACHE_RBTREE,
};
static int bcm590xx_i2c_probe(struct i2c_client *i2c_pri)
{
struct bcm590xx *bcm590xx;
int ret;
bcm590xx = devm_kzalloc(&i2c_pri->dev, sizeof(*bcm590xx), GFP_KERNEL);
if (!bcm590xx)
return -ENOMEM;
i2c_set_clientdata(i2c_pri, bcm590xx);
bcm590xx->dev = &i2c_pri->dev;
bcm590xx->i2c_pri = i2c_pri;
bcm590xx->regmap_pri = devm_regmap_init_i2c(i2c_pri,
&bcm590xx_regmap_config_pri);
if (IS_ERR(bcm590xx->regmap_pri)) {
ret = PTR_ERR(bcm590xx->regmap_pri);
dev_err(&i2c_pri->dev, "primary regmap init failed: %d\n", ret);
return ret;
}
/* Secondary I2C slave address is the base address with A(2) asserted */
bcm590xx->i2c_sec = i2c_new_dummy_device(i2c_pri->adapter,
i2c_pri->addr | BIT(2));
if (IS_ERR(bcm590xx->i2c_sec)) {
dev_err(&i2c_pri->dev, "failed to add secondary I2C device\n");
return PTR_ERR(bcm590xx->i2c_sec);
}
i2c_set_clientdata(bcm590xx->i2c_sec, bcm590xx);
bcm590xx->regmap_sec = devm_regmap_init_i2c(bcm590xx->i2c_sec,
&bcm590xx_regmap_config_sec);
if (IS_ERR(bcm590xx->regmap_sec)) {
ret = PTR_ERR(bcm590xx->regmap_sec);
dev_err(&bcm590xx->i2c_sec->dev,
"secondary regmap init failed: %d\n", ret);
goto err;
}
ret = devm_mfd_add_devices(&i2c_pri->dev, -1, bcm590xx_devs,
ARRAY_SIZE(bcm590xx_devs), NULL, 0, NULL);
if (ret < 0) {
dev_err(&i2c_pri->dev, "failed to add sub-devices: %d\n", ret);
goto err;
}
return 0;
err:
i2c_unregister_device(bcm590xx->i2c_sec);
return ret;
}
static const struct of_device_id bcm590xx_of_match[] = {
{ .compatible = "brcm,bcm59056" },
{ }
};
MODULE_DEVICE_TABLE(of, bcm590xx_of_match);
static const struct i2c_device_id bcm590xx_i2c_id[] = {
{ "bcm59056" },
{ }
};
MODULE_DEVICE_TABLE(i2c, bcm590xx_i2c_id);
static struct i2c_driver bcm590xx_i2c_driver = {
.driver = {
.name = "bcm590xx",
.of_match_table = bcm590xx_of_match,
},
.probe = bcm590xx_i2c_probe,
.id_table = bcm590xx_i2c_id,
};
module_i2c_driver(bcm590xx_i2c_driver);
MODULE_AUTHOR("Matt Porter <[email protected]>");
MODULE_DESCRIPTION("BCM590xx multi-function driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/bcm590xx.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm831x-i2c.c -- I2C access for Wolfson WM831x PMICs
*
* Copyright 2009,2010 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/mfd/core.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/pdata.h>
static int wm831x_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct wm831x_pdata *pdata = dev_get_platdata(&i2c->dev);
const struct of_device_id *of_id;
struct wm831x *wm831x;
enum wm831x_parent type;
int ret;
if (i2c->dev.of_node) {
of_id = of_match_device(wm831x_of_match, &i2c->dev);
if (!of_id) {
dev_err(&i2c->dev, "Failed to match device\n");
return -ENODEV;
}
type = (uintptr_t)of_id->data;
} else {
type = (enum wm831x_parent)id->driver_data;
}
wm831x = devm_kzalloc(&i2c->dev, sizeof(struct wm831x), GFP_KERNEL);
if (wm831x == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, wm831x);
wm831x->dev = &i2c->dev;
wm831x->type = type;
wm831x->regmap = devm_regmap_init_i2c(i2c, &wm831x_regmap_config);
if (IS_ERR(wm831x->regmap)) {
ret = PTR_ERR(wm831x->regmap);
dev_err(wm831x->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
if (pdata)
memcpy(&wm831x->pdata, pdata, sizeof(*pdata));
return wm831x_device_init(wm831x, i2c->irq);
}
static int wm831x_i2c_suspend(struct device *dev)
{
struct wm831x *wm831x = dev_get_drvdata(dev);
return wm831x_device_suspend(wm831x);
}
static int wm831x_i2c_poweroff(struct device *dev)
{
struct wm831x *wm831x = dev_get_drvdata(dev);
wm831x_device_shutdown(wm831x);
return 0;
}
static const struct i2c_device_id wm831x_i2c_id[] = {
{ "wm8310", WM8310 },
{ "wm8311", WM8311 },
{ "wm8312", WM8312 },
{ "wm8320", WM8320 },
{ "wm8321", WM8321 },
{ "wm8325", WM8325 },
{ "wm8326", WM8326 },
{ }
};
static const struct dev_pm_ops wm831x_pm_ops = {
.suspend = wm831x_i2c_suspend,
.poweroff = wm831x_i2c_poweroff,
};
static struct i2c_driver wm831x_i2c_driver = {
.driver = {
.name = "wm831x",
.pm = &wm831x_pm_ops,
.of_match_table = of_match_ptr(wm831x_of_match),
.suppress_bind_attrs = true,
},
.probe = wm831x_i2c_probe,
.id_table = wm831x_i2c_id,
};
static int __init wm831x_i2c_init(void)
{
int ret;
ret = i2c_add_driver(&wm831x_i2c_driver);
if (ret != 0)
pr_err("Failed to register wm831x I2C driver: %d\n", ret);
return ret;
}
subsys_initcall(wm831x_i2c_init);
| linux-master | drivers/mfd/wm831x-i2c.c |
/*
* Base driver for Marvell 88PM800
*
* Copyright (C) 2012 Marvell International Ltd.
* Haojian Zhuang <[email protected]>
* Joseph(Yossi) Hanin <[email protected]>
* Qiao Zhou <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
* archive for more details.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/88pm80x.h>
#include <linux/slab.h>
/* Interrupt Registers */
#define PM800_INT_STATUS1 (0x05)
#define PM800_ONKEY_INT_STS1 (1 << 0)
#define PM800_EXTON_INT_STS1 (1 << 1)
#define PM800_CHG_INT_STS1 (1 << 2)
#define PM800_BAT_INT_STS1 (1 << 3)
#define PM800_RTC_INT_STS1 (1 << 4)
#define PM800_CLASSD_OC_INT_STS1 (1 << 5)
#define PM800_INT_STATUS2 (0x06)
#define PM800_VBAT_INT_STS2 (1 << 0)
#define PM800_VSYS_INT_STS2 (1 << 1)
#define PM800_VCHG_INT_STS2 (1 << 2)
#define PM800_TINT_INT_STS2 (1 << 3)
#define PM800_GPADC0_INT_STS2 (1 << 4)
#define PM800_TBAT_INT_STS2 (1 << 5)
#define PM800_GPADC2_INT_STS2 (1 << 6)
#define PM800_GPADC3_INT_STS2 (1 << 7)
#define PM800_INT_STATUS3 (0x07)
#define PM800_INT_STATUS4 (0x08)
#define PM800_GPIO0_INT_STS4 (1 << 0)
#define PM800_GPIO1_INT_STS4 (1 << 1)
#define PM800_GPIO2_INT_STS4 (1 << 2)
#define PM800_GPIO3_INT_STS4 (1 << 3)
#define PM800_GPIO4_INT_STS4 (1 << 4)
#define PM800_INT_ENA_1 (0x09)
#define PM800_ONKEY_INT_ENA1 (1 << 0)
#define PM800_EXTON_INT_ENA1 (1 << 1)
#define PM800_CHG_INT_ENA1 (1 << 2)
#define PM800_BAT_INT_ENA1 (1 << 3)
#define PM800_RTC_INT_ENA1 (1 << 4)
#define PM800_CLASSD_OC_INT_ENA1 (1 << 5)
#define PM800_INT_ENA_2 (0x0A)
#define PM800_VBAT_INT_ENA2 (1 << 0)
#define PM800_VSYS_INT_ENA2 (1 << 1)
#define PM800_VCHG_INT_ENA2 (1 << 2)
#define PM800_TINT_INT_ENA2 (1 << 3)
#define PM800_INT_ENA_3 (0x0B)
#define PM800_GPADC0_INT_ENA3 (1 << 0)
#define PM800_GPADC1_INT_ENA3 (1 << 1)
#define PM800_GPADC2_INT_ENA3 (1 << 2)
#define PM800_GPADC3_INT_ENA3 (1 << 3)
#define PM800_GPADC4_INT_ENA3 (1 << 4)
#define PM800_INT_ENA_4 (0x0C)
#define PM800_GPIO0_INT_ENA4 (1 << 0)
#define PM800_GPIO1_INT_ENA4 (1 << 1)
#define PM800_GPIO2_INT_ENA4 (1 << 2)
#define PM800_GPIO3_INT_ENA4 (1 << 3)
#define PM800_GPIO4_INT_ENA4 (1 << 4)
/* number of INT_ENA & INT_STATUS regs */
#define PM800_INT_REG_NUM (4)
/* Interrupt Number in 88PM800 */
enum {
PM800_IRQ_ONKEY, /*EN1b0 *//*0 */
PM800_IRQ_EXTON, /*EN1b1 */
PM800_IRQ_CHG, /*EN1b2 */
PM800_IRQ_BAT, /*EN1b3 */
PM800_IRQ_RTC, /*EN1b4 */
PM800_IRQ_CLASSD, /*EN1b5 *//*5 */
PM800_IRQ_VBAT, /*EN2b0 */
PM800_IRQ_VSYS, /*EN2b1 */
PM800_IRQ_VCHG, /*EN2b2 */
PM800_IRQ_TINT, /*EN2b3 */
PM800_IRQ_GPADC0, /*EN3b0 *//*10 */
PM800_IRQ_GPADC1, /*EN3b1 */
PM800_IRQ_GPADC2, /*EN3b2 */
PM800_IRQ_GPADC3, /*EN3b3 */
PM800_IRQ_GPADC4, /*EN3b4 */
PM800_IRQ_GPIO0, /*EN4b0 *//*15 */
PM800_IRQ_GPIO1, /*EN4b1 */
PM800_IRQ_GPIO2, /*EN4b2 */
PM800_IRQ_GPIO3, /*EN4b3 */
PM800_IRQ_GPIO4, /*EN4b4 *//*19 */
PM800_MAX_IRQ,
};
/* PM800: generation identification number */
#define PM800_CHIP_GEN_ID_NUM 0x3
static const struct i2c_device_id pm80x_id_table[] = {
{"88PM800", 0},
{} /* NULL terminated */
};
MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
static const struct resource rtc_resources[] = {
DEFINE_RES_IRQ_NAMED(PM800_IRQ_RTC, "88pm80x-rtc"),
};
static struct mfd_cell rtc_devs[] = {
{
.name = "88pm80x-rtc",
.num_resources = ARRAY_SIZE(rtc_resources),
.resources = &rtc_resources[0],
.id = -1,
},
};
static struct resource onkey_resources[] = {
DEFINE_RES_IRQ_NAMED(PM800_IRQ_ONKEY, "88pm80x-onkey"),
};
static const struct mfd_cell onkey_devs[] = {
{
.name = "88pm80x-onkey",
.num_resources = 1,
.resources = &onkey_resources[0],
.id = -1,
},
};
static const struct mfd_cell regulator_devs[] = {
{
.name = "88pm80x-regulator",
.id = -1,
},
};
static const struct regmap_irq pm800_irqs[] = {
/* INT0 */
[PM800_IRQ_ONKEY] = {
.mask = PM800_ONKEY_INT_ENA1,
},
[PM800_IRQ_EXTON] = {
.mask = PM800_EXTON_INT_ENA1,
},
[PM800_IRQ_CHG] = {
.mask = PM800_CHG_INT_ENA1,
},
[PM800_IRQ_BAT] = {
.mask = PM800_BAT_INT_ENA1,
},
[PM800_IRQ_RTC] = {
.mask = PM800_RTC_INT_ENA1,
},
[PM800_IRQ_CLASSD] = {
.mask = PM800_CLASSD_OC_INT_ENA1,
},
/* INT1 */
[PM800_IRQ_VBAT] = {
.reg_offset = 1,
.mask = PM800_VBAT_INT_ENA2,
},
[PM800_IRQ_VSYS] = {
.reg_offset = 1,
.mask = PM800_VSYS_INT_ENA2,
},
[PM800_IRQ_VCHG] = {
.reg_offset = 1,
.mask = PM800_VCHG_INT_ENA2,
},
[PM800_IRQ_TINT] = {
.reg_offset = 1,
.mask = PM800_TINT_INT_ENA2,
},
/* INT2 */
[PM800_IRQ_GPADC0] = {
.reg_offset = 2,
.mask = PM800_GPADC0_INT_ENA3,
},
[PM800_IRQ_GPADC1] = {
.reg_offset = 2,
.mask = PM800_GPADC1_INT_ENA3,
},
[PM800_IRQ_GPADC2] = {
.reg_offset = 2,
.mask = PM800_GPADC2_INT_ENA3,
},
[PM800_IRQ_GPADC3] = {
.reg_offset = 2,
.mask = PM800_GPADC3_INT_ENA3,
},
[PM800_IRQ_GPADC4] = {
.reg_offset = 2,
.mask = PM800_GPADC4_INT_ENA3,
},
/* INT3 */
[PM800_IRQ_GPIO0] = {
.reg_offset = 3,
.mask = PM800_GPIO0_INT_ENA4,
},
[PM800_IRQ_GPIO1] = {
.reg_offset = 3,
.mask = PM800_GPIO1_INT_ENA4,
},
[PM800_IRQ_GPIO2] = {
.reg_offset = 3,
.mask = PM800_GPIO2_INT_ENA4,
},
[PM800_IRQ_GPIO3] = {
.reg_offset = 3,
.mask = PM800_GPIO3_INT_ENA4,
},
[PM800_IRQ_GPIO4] = {
.reg_offset = 3,
.mask = PM800_GPIO4_INT_ENA4,
},
};
static int device_gpadc_init(struct pm80x_chip *chip,
struct pm80x_platform_data *pdata)
{
struct pm80x_subchip *subchip = chip->subchip;
struct regmap *map = subchip->regmap_gpadc;
int data = 0, mask = 0, ret = 0;
if (!map) {
dev_warn(chip->dev,
"Warning: gpadc regmap is not available!\n");
return -EINVAL;
}
/*
* initialize GPADC without activating it turn on GPADC
* measurments
*/
ret = regmap_update_bits(map,
PM800_GPADC_MISC_CONFIG2,
PM800_GPADC_MISC_GPFSM_EN,
PM800_GPADC_MISC_GPFSM_EN);
if (ret < 0)
goto out;
/*
* This function configures the ADC as requires for
* CP implementation.CP does not "own" the ADC configuration
* registers and relies on AP.
* Reason: enable automatic ADC measurements needed
* for CP to get VBAT and RF temperature readings.
*/
ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
if (ret < 0)
goto out;
ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
(PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
(PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
if (ret < 0)
goto out;
/*
* the defult of PM800 is GPADC operates at 100Ks/s rate
* and Number of GPADC slots with active current bias prior
* to GPADC sampling = 1 slot for all GPADCs set for
* Temprature mesurmants
*/
mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
if (pdata && (pdata->batt_det == 0))
data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
else
data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
PM800_GPADC_GP_BIAS_EN3);
ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
if (ret < 0)
goto out;
dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
return 0;
out:
dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
return ret;
}
static int device_onkey_init(struct pm80x_chip *chip,
struct pm80x_platform_data *pdata)
{
int ret;
ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0,
NULL);
if (ret) {
dev_err(chip->dev, "Failed to add onkey subdev\n");
return ret;
}
return 0;
}
static int device_rtc_init(struct pm80x_chip *chip,
struct pm80x_platform_data *pdata)
{
int ret;
if (pdata) {
rtc_devs[0].platform_data = pdata->rtc;
rtc_devs[0].pdata_size =
pdata->rtc ? sizeof(struct pm80x_rtc_pdata) : 0;
}
ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
if (ret) {
dev_err(chip->dev, "Failed to add rtc subdev\n");
return ret;
}
return 0;
}
static int device_regulator_init(struct pm80x_chip *chip,
struct pm80x_platform_data *pdata)
{
int ret;
ret = mfd_add_devices(chip->dev, 0, ®ulator_devs[0],
ARRAY_SIZE(regulator_devs), NULL, 0, NULL);
if (ret) {
dev_err(chip->dev, "Failed to add regulator subdev\n");
return ret;
}
return 0;
}
static int device_irq_init_800(struct pm80x_chip *chip)
{
struct regmap *map = chip->regmap;
unsigned long flags = IRQF_ONESHOT;
int data, mask, ret = -EINVAL;
if (!map || !chip->irq) {
dev_err(chip->dev, "incorrect parameters\n");
return -EINVAL;
}
/*
* irq_mode defines the way of clearing interrupt. it's read-clear by
* default.
*/
mask =
PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR |
PM800_WAKEUP2_INT_MASK;
data = PM800_WAKEUP2_INT_CLEAR;
ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);
if (ret < 0)
goto out;
ret =
regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
chip->regmap_irq_chip, &chip->irq_data);
out:
return ret;
}
static void device_irq_exit_800(struct pm80x_chip *chip)
{
regmap_del_irq_chip(chip->irq, chip->irq_data);
}
static struct regmap_irq_chip pm800_irq_chip = {
.name = "88pm800",
.irqs = pm800_irqs,
.num_irqs = ARRAY_SIZE(pm800_irqs),
.num_regs = 4,
.status_base = PM800_INT_STATUS1,
.unmask_base = PM800_INT_ENA_1,
.ack_base = PM800_INT_STATUS1,
};
static int pm800_pages_init(struct pm80x_chip *chip)
{
struct pm80x_subchip *subchip;
struct i2c_client *client = chip->client;
int ret = 0;
subchip = chip->subchip;
if (!subchip || !subchip->power_page_addr || !subchip->gpadc_page_addr)
return -ENODEV;
/* PM800 block power page */
subchip->power_page = i2c_new_dummy_device(client->adapter,
subchip->power_page_addr);
if (IS_ERR(subchip->power_page)) {
ret = PTR_ERR(subchip->power_page);
goto out;
}
subchip->regmap_power = devm_regmap_init_i2c(subchip->power_page,
&pm80x_regmap_config);
if (IS_ERR(subchip->regmap_power)) {
ret = PTR_ERR(subchip->regmap_power);
dev_err(chip->dev,
"Failed to allocate regmap_power: %d\n", ret);
goto out;
}
i2c_set_clientdata(subchip->power_page, chip);
/* PM800 block GPADC */
subchip->gpadc_page = i2c_new_dummy_device(client->adapter,
subchip->gpadc_page_addr);
if (IS_ERR(subchip->gpadc_page)) {
ret = PTR_ERR(subchip->gpadc_page);
goto out;
}
subchip->regmap_gpadc = devm_regmap_init_i2c(subchip->gpadc_page,
&pm80x_regmap_config);
if (IS_ERR(subchip->regmap_gpadc)) {
ret = PTR_ERR(subchip->regmap_gpadc);
dev_err(chip->dev,
"Failed to allocate regmap_gpadc: %d\n", ret);
goto out;
}
i2c_set_clientdata(subchip->gpadc_page, chip);
out:
return ret;
}
static void pm800_pages_exit(struct pm80x_chip *chip)
{
struct pm80x_subchip *subchip;
subchip = chip->subchip;
if (subchip && subchip->power_page)
i2c_unregister_device(subchip->power_page);
if (subchip && subchip->gpadc_page)
i2c_unregister_device(subchip->gpadc_page);
}
static int device_800_init(struct pm80x_chip *chip,
struct pm80x_platform_data *pdata)
{
int ret;
unsigned int val;
/*
* alarm wake up bit will be clear in device_irq_init(),
* read before that
*/
ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
if (ret < 0) {
dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
goto out;
}
if (val & PM800_ALARM_WAKEUP) {
if (pdata && pdata->rtc)
pdata->rtc->rtc_wakeup = 1;
}
ret = device_gpadc_init(chip, pdata);
if (ret < 0) {
dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
goto out;
}
chip->regmap_irq_chip = &pm800_irq_chip;
ret = device_irq_init_800(chip);
if (ret < 0) {
dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
goto out;
}
ret = device_onkey_init(chip, pdata);
if (ret) {
dev_err(chip->dev, "Failed to add onkey subdev\n");
goto out_dev;
}
ret = device_rtc_init(chip, pdata);
if (ret) {
dev_err(chip->dev, "Failed to add rtc subdev\n");
goto out;
}
ret = device_regulator_init(chip, pdata);
if (ret) {
dev_err(chip->dev, "Failed to add regulators subdev\n");
goto out;
}
return 0;
out_dev:
mfd_remove_devices(chip->dev);
device_irq_exit_800(chip);
out:
return ret;
}
static int pm800_probe(struct i2c_client *client)
{
int ret = 0;
struct pm80x_chip *chip;
struct pm80x_platform_data *pdata = dev_get_platdata(&client->dev);
struct pm80x_subchip *subchip;
ret = pm80x_init(client);
if (ret) {
dev_err(&client->dev, "pm800_init fail\n");
goto out_init;
}
chip = i2c_get_clientdata(client);
/* init subchip for PM800 */
subchip =
devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
GFP_KERNEL);
if (!subchip) {
ret = -ENOMEM;
goto err_subchip_alloc;
}
/* pm800 has 2 addtional pages to support power and gpadc. */
subchip->power_page_addr = client->addr + 1;
subchip->gpadc_page_addr = client->addr + 2;
chip->subchip = subchip;
ret = pm800_pages_init(chip);
if (ret) {
dev_err(&client->dev, "pm800_pages_init failed!\n");
goto err_device_init;
}
ret = device_800_init(chip, pdata);
if (ret) {
dev_err(chip->dev, "Failed to initialize 88pm800 devices\n");
goto err_device_init;
}
if (pdata && pdata->plat_config)
pdata->plat_config(chip, pdata);
return 0;
err_device_init:
pm800_pages_exit(chip);
err_subchip_alloc:
pm80x_deinit();
out_init:
return ret;
}
static void pm800_remove(struct i2c_client *client)
{
struct pm80x_chip *chip = i2c_get_clientdata(client);
mfd_remove_devices(chip->dev);
device_irq_exit_800(chip);
pm800_pages_exit(chip);
pm80x_deinit();
}
static struct i2c_driver pm800_driver = {
.driver = {
.name = "88PM800",
.pm = pm_sleep_ptr(&pm80x_pm_ops),
},
.probe = pm800_probe,
.remove = pm800_remove,
.id_table = pm80x_id_table,
};
static int __init pm800_i2c_init(void)
{
return i2c_add_driver(&pm800_driver);
}
subsys_initcall(pm800_i2c_init);
static void __exit pm800_i2c_exit(void)
{
i2c_del_driver(&pm800_driver);
}
module_exit(pm800_i2c_exit);
MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
MODULE_AUTHOR("Qiao Zhou <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/88pm800.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Base driver for Marvell 88PM8607
*
* Copyright (C) 2009 Marvell International Ltd.
*
* Author: Haojian Zhuang <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/mfd/core.h>
#include <linux/mfd/88pm860x.h>
#include <linux/regulator/machine.h>
#include <linux/power/charger-manager.h>
#define INT_STATUS_NUM 3
static const struct resource bk0_resources[] = {
{2, 2, "duty cycle", IORESOURCE_REG, },
{3, 3, "always on", IORESOURCE_REG, },
{3, 3, "current", IORESOURCE_REG, },
};
static const struct resource bk1_resources[] = {
{4, 4, "duty cycle", IORESOURCE_REG, },
{5, 5, "always on", IORESOURCE_REG, },
{5, 5, "current", IORESOURCE_REG, },
};
static const struct resource bk2_resources[] = {
{6, 6, "duty cycle", IORESOURCE_REG, },
{7, 7, "always on", IORESOURCE_REG, },
{5, 5, "current", IORESOURCE_REG, },
};
static const struct resource led0_resources[] = {
/* RGB1 Red LED */
{0xd, 0xd, "control", IORESOURCE_REG, },
{0xc, 0xc, "blink", IORESOURCE_REG, },
};
static const struct resource led1_resources[] = {
/* RGB1 Green LED */
{0xe, 0xe, "control", IORESOURCE_REG, },
{0xc, 0xc, "blink", IORESOURCE_REG, },
};
static const struct resource led2_resources[] = {
/* RGB1 Blue LED */
{0xf, 0xf, "control", IORESOURCE_REG, },
{0xc, 0xc, "blink", IORESOURCE_REG, },
};
static const struct resource led3_resources[] = {
/* RGB2 Red LED */
{0x9, 0x9, "control", IORESOURCE_REG, },
{0x8, 0x8, "blink", IORESOURCE_REG, },
};
static const struct resource led4_resources[] = {
/* RGB2 Green LED */
{0xa, 0xa, "control", IORESOURCE_REG, },
{0x8, 0x8, "blink", IORESOURCE_REG, },
};
static const struct resource led5_resources[] = {
/* RGB2 Blue LED */
{0xb, 0xb, "control", IORESOURCE_REG, },
{0x8, 0x8, "blink", IORESOURCE_REG, },
};
static const struct resource buck1_resources[] = {
{0x24, 0x24, "buck set", IORESOURCE_REG, },
};
static const struct resource buck2_resources[] = {
{0x25, 0x25, "buck set", IORESOURCE_REG, },
};
static const struct resource buck3_resources[] = {
{0x26, 0x26, "buck set", IORESOURCE_REG, },
};
static const struct resource ldo1_resources[] = {
{0x10, 0x10, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo2_resources[] = {
{0x11, 0x11, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo3_resources[] = {
{0x12, 0x12, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo4_resources[] = {
{0x13, 0x13, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo5_resources[] = {
{0x14, 0x14, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo6_resources[] = {
{0x15, 0x15, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo7_resources[] = {
{0x16, 0x16, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo8_resources[] = {
{0x17, 0x17, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo9_resources[] = {
{0x18, 0x18, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo10_resources[] = {
{0x19, 0x19, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo12_resources[] = {
{0x1a, 0x1a, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo_vibrator_resources[] = {
{0x28, 0x28, "ldo set", IORESOURCE_REG, },
};
static const struct resource ldo14_resources[] = {
{0x1b, 0x1b, "ldo set", IORESOURCE_REG, },
};
static struct resource touch_resources[] = {
{PM8607_IRQ_PEN, PM8607_IRQ_PEN, "touch", IORESOURCE_IRQ,},
};
static struct resource onkey_resources[] = {
{PM8607_IRQ_ONKEY, PM8607_IRQ_ONKEY, "onkey", IORESOURCE_IRQ,},
};
static struct resource codec_resources[] = {
/* Headset microphone insertion or removal */
{PM8607_IRQ_MICIN, PM8607_IRQ_MICIN, "micin", IORESOURCE_IRQ,},
/* Hook-switch press or release */
{PM8607_IRQ_HOOK, PM8607_IRQ_HOOK, "hook", IORESOURCE_IRQ,},
/* Headset insertion or removal */
{PM8607_IRQ_HEADSET, PM8607_IRQ_HEADSET, "headset", IORESOURCE_IRQ,},
/* Audio short */
{PM8607_IRQ_AUDIO_SHORT, PM8607_IRQ_AUDIO_SHORT, "audio-short",
IORESOURCE_IRQ,},
};
static struct resource battery_resources[] = {
{PM8607_IRQ_CC, PM8607_IRQ_CC, "columb counter", IORESOURCE_IRQ,},
{PM8607_IRQ_BAT, PM8607_IRQ_BAT, "battery", IORESOURCE_IRQ,},
};
static struct resource charger_resources[] = {
{PM8607_IRQ_CHG, PM8607_IRQ_CHG, "charger detect", IORESOURCE_IRQ,},
{PM8607_IRQ_CHG_DONE, PM8607_IRQ_CHG_DONE, "charging done",
IORESOURCE_IRQ,},
{PM8607_IRQ_CHG_FAIL, PM8607_IRQ_CHG_FAIL, "charging timeout",
IORESOURCE_IRQ,},
{PM8607_IRQ_CHG_FAULT, PM8607_IRQ_CHG_FAULT, "charging fault",
IORESOURCE_IRQ,},
{PM8607_IRQ_GPADC1, PM8607_IRQ_GPADC1, "battery temperature",
IORESOURCE_IRQ,},
{PM8607_IRQ_VBAT, PM8607_IRQ_VBAT, "battery voltage", IORESOURCE_IRQ,},
{PM8607_IRQ_VCHG, PM8607_IRQ_VCHG, "vchg voltage", IORESOURCE_IRQ,},
};
static struct resource rtc_resources[] = {
{PM8607_IRQ_RTC, PM8607_IRQ_RTC, "rtc", IORESOURCE_IRQ,},
};
static struct mfd_cell bk_devs[] = {
{
.name = "88pm860x-backlight",
.id = 0,
.num_resources = ARRAY_SIZE(bk0_resources),
.resources = bk0_resources,
}, {
.name = "88pm860x-backlight",
.id = 1,
.num_resources = ARRAY_SIZE(bk1_resources),
.resources = bk1_resources,
}, {
.name = "88pm860x-backlight",
.id = 2,
.num_resources = ARRAY_SIZE(bk2_resources),
.resources = bk2_resources,
},
};
static struct mfd_cell led_devs[] = {
{
.name = "88pm860x-led",
.id = 0,
.num_resources = ARRAY_SIZE(led0_resources),
.resources = led0_resources,
}, {
.name = "88pm860x-led",
.id = 1,
.num_resources = ARRAY_SIZE(led1_resources),
.resources = led1_resources,
}, {
.name = "88pm860x-led",
.id = 2,
.num_resources = ARRAY_SIZE(led2_resources),
.resources = led2_resources,
}, {
.name = "88pm860x-led",
.id = 3,
.num_resources = ARRAY_SIZE(led3_resources),
.resources = led3_resources,
}, {
.name = "88pm860x-led",
.id = 4,
.num_resources = ARRAY_SIZE(led4_resources),
.resources = led4_resources,
}, {
.name = "88pm860x-led",
.id = 5,
.num_resources = ARRAY_SIZE(led5_resources),
.resources = led5_resources,
},
};
static struct mfd_cell reg_devs[] = {
{
.name = "88pm860x-regulator",
.id = 0,
.num_resources = ARRAY_SIZE(buck1_resources),
.resources = buck1_resources,
}, {
.name = "88pm860x-regulator",
.id = 1,
.num_resources = ARRAY_SIZE(buck2_resources),
.resources = buck2_resources,
}, {
.name = "88pm860x-regulator",
.id = 2,
.num_resources = ARRAY_SIZE(buck3_resources),
.resources = buck3_resources,
}, {
.name = "88pm860x-regulator",
.id = 3,
.num_resources = ARRAY_SIZE(ldo1_resources),
.resources = ldo1_resources,
}, {
.name = "88pm860x-regulator",
.id = 4,
.num_resources = ARRAY_SIZE(ldo2_resources),
.resources = ldo2_resources,
}, {
.name = "88pm860x-regulator",
.id = 5,
.num_resources = ARRAY_SIZE(ldo3_resources),
.resources = ldo3_resources,
}, {
.name = "88pm860x-regulator",
.id = 6,
.num_resources = ARRAY_SIZE(ldo4_resources),
.resources = ldo4_resources,
}, {
.name = "88pm860x-regulator",
.id = 7,
.num_resources = ARRAY_SIZE(ldo5_resources),
.resources = ldo5_resources,
}, {
.name = "88pm860x-regulator",
.id = 8,
.num_resources = ARRAY_SIZE(ldo6_resources),
.resources = ldo6_resources,
}, {
.name = "88pm860x-regulator",
.id = 9,
.num_resources = ARRAY_SIZE(ldo7_resources),
.resources = ldo7_resources,
}, {
.name = "88pm860x-regulator",
.id = 10,
.num_resources = ARRAY_SIZE(ldo8_resources),
.resources = ldo8_resources,
}, {
.name = "88pm860x-regulator",
.id = 11,
.num_resources = ARRAY_SIZE(ldo9_resources),
.resources = ldo9_resources,
}, {
.name = "88pm860x-regulator",
.id = 12,
.num_resources = ARRAY_SIZE(ldo10_resources),
.resources = ldo10_resources,
}, {
.name = "88pm860x-regulator",
.id = 13,
.num_resources = ARRAY_SIZE(ldo12_resources),
.resources = ldo12_resources,
}, {
.name = "88pm860x-regulator",
.id = 14,
.num_resources = ARRAY_SIZE(ldo_vibrator_resources),
.resources = ldo_vibrator_resources,
}, {
.name = "88pm860x-regulator",
.id = 15,
.num_resources = ARRAY_SIZE(ldo14_resources),
.resources = ldo14_resources,
},
};
static struct mfd_cell touch_devs[] = {
{"88pm860x-touch", -1,},
};
static struct mfd_cell onkey_devs[] = {
{"88pm860x-onkey", -1,},
};
static struct mfd_cell codec_devs[] = {
{"88pm860x-codec", -1,},
};
static struct regulator_consumer_supply preg_supply[] = {
REGULATOR_SUPPLY("preg", "charger-manager"),
};
static struct regulator_init_data preg_init_data = {
.num_consumer_supplies = ARRAY_SIZE(preg_supply),
.consumer_supplies = &preg_supply[0],
};
static struct charger_regulator chg_desc_regulator_data[] = {
{ .regulator_name = "preg", },
};
static struct mfd_cell power_devs[] = {
{"88pm860x-battery", -1,},
{"88pm860x-charger", -1,},
{"88pm860x-preg", -1,},
{"charger-manager", -1,},
};
static struct mfd_cell rtc_devs[] = {
{"88pm860x-rtc", -1,},
};
struct pm860x_irq_data {
int reg;
int mask_reg;
int enable; /* enable or not */
int offs; /* bit offset in mask register */
};
static struct pm860x_irq_data pm860x_irqs[] = {
[PM8607_IRQ_ONKEY] = {
.reg = PM8607_INT_STATUS1,
.mask_reg = PM8607_INT_MASK_1,
.offs = 1 << 0,
},
[PM8607_IRQ_EXTON] = {
.reg = PM8607_INT_STATUS1,
.mask_reg = PM8607_INT_MASK_1,
.offs = 1 << 1,
},
[PM8607_IRQ_CHG] = {
.reg = PM8607_INT_STATUS1,
.mask_reg = PM8607_INT_MASK_1,
.offs = 1 << 2,
},
[PM8607_IRQ_BAT] = {
.reg = PM8607_INT_STATUS1,
.mask_reg = PM8607_INT_MASK_1,
.offs = 1 << 3,
},
[PM8607_IRQ_RTC] = {
.reg = PM8607_INT_STATUS1,
.mask_reg = PM8607_INT_MASK_1,
.offs = 1 << 4,
},
[PM8607_IRQ_CC] = {
.reg = PM8607_INT_STATUS1,
.mask_reg = PM8607_INT_MASK_1,
.offs = 1 << 5,
},
[PM8607_IRQ_VBAT] = {
.reg = PM8607_INT_STATUS2,
.mask_reg = PM8607_INT_MASK_2,
.offs = 1 << 0,
},
[PM8607_IRQ_VCHG] = {
.reg = PM8607_INT_STATUS2,
.mask_reg = PM8607_INT_MASK_2,
.offs = 1 << 1,
},
[PM8607_IRQ_VSYS] = {
.reg = PM8607_INT_STATUS2,
.mask_reg = PM8607_INT_MASK_2,
.offs = 1 << 2,
},
[PM8607_IRQ_TINT] = {
.reg = PM8607_INT_STATUS2,
.mask_reg = PM8607_INT_MASK_2,
.offs = 1 << 3,
},
[PM8607_IRQ_GPADC0] = {
.reg = PM8607_INT_STATUS2,
.mask_reg = PM8607_INT_MASK_2,
.offs = 1 << 4,
},
[PM8607_IRQ_GPADC1] = {
.reg = PM8607_INT_STATUS2,
.mask_reg = PM8607_INT_MASK_2,
.offs = 1 << 5,
},
[PM8607_IRQ_GPADC2] = {
.reg = PM8607_INT_STATUS2,
.mask_reg = PM8607_INT_MASK_2,
.offs = 1 << 6,
},
[PM8607_IRQ_GPADC3] = {
.reg = PM8607_INT_STATUS2,
.mask_reg = PM8607_INT_MASK_2,
.offs = 1 << 7,
},
[PM8607_IRQ_AUDIO_SHORT] = {
.reg = PM8607_INT_STATUS3,
.mask_reg = PM8607_INT_MASK_3,
.offs = 1 << 0,
},
[PM8607_IRQ_PEN] = {
.reg = PM8607_INT_STATUS3,
.mask_reg = PM8607_INT_MASK_3,
.offs = 1 << 1,
},
[PM8607_IRQ_HEADSET] = {
.reg = PM8607_INT_STATUS3,
.mask_reg = PM8607_INT_MASK_3,
.offs = 1 << 2,
},
[PM8607_IRQ_HOOK] = {
.reg = PM8607_INT_STATUS3,
.mask_reg = PM8607_INT_MASK_3,
.offs = 1 << 3,
},
[PM8607_IRQ_MICIN] = {
.reg = PM8607_INT_STATUS3,
.mask_reg = PM8607_INT_MASK_3,
.offs = 1 << 4,
},
[PM8607_IRQ_CHG_FAIL] = {
.reg = PM8607_INT_STATUS3,
.mask_reg = PM8607_INT_MASK_3,
.offs = 1 << 5,
},
[PM8607_IRQ_CHG_DONE] = {
.reg = PM8607_INT_STATUS3,
.mask_reg = PM8607_INT_MASK_3,
.offs = 1 << 6,
},
[PM8607_IRQ_CHG_FAULT] = {
.reg = PM8607_INT_STATUS3,
.mask_reg = PM8607_INT_MASK_3,
.offs = 1 << 7,
},
};
static irqreturn_t pm860x_irq(int irq, void *data)
{
struct pm860x_chip *chip = data;
struct pm860x_irq_data *irq_data;
struct i2c_client *i2c;
int read_reg = -1, value = 0;
int i;
i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion;
for (i = 0; i < ARRAY_SIZE(pm860x_irqs); i++) {
irq_data = &pm860x_irqs[i];
if (read_reg != irq_data->reg) {
read_reg = irq_data->reg;
value = pm860x_reg_read(i2c, irq_data->reg);
}
if (value & irq_data->enable)
handle_nested_irq(chip->irq_base + i);
}
return IRQ_HANDLED;
}
static void pm860x_irq_lock(struct irq_data *data)
{
struct pm860x_chip *chip = irq_data_get_irq_chip_data(data);
mutex_lock(&chip->irq_lock);
}
static void pm860x_irq_sync_unlock(struct irq_data *data)
{
struct pm860x_chip *chip = irq_data_get_irq_chip_data(data);
struct pm860x_irq_data *irq_data;
struct i2c_client *i2c;
static unsigned char cached[3] = {0x0, 0x0, 0x0};
unsigned char mask[3];
int i;
i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion;
/* Load cached value. In initial, all IRQs are masked */
for (i = 0; i < 3; i++)
mask[i] = cached[i];
for (i = 0; i < ARRAY_SIZE(pm860x_irqs); i++) {
irq_data = &pm860x_irqs[i];
switch (irq_data->mask_reg) {
case PM8607_INT_MASK_1:
mask[0] &= ~irq_data->offs;
mask[0] |= irq_data->enable;
break;
case PM8607_INT_MASK_2:
mask[1] &= ~irq_data->offs;
mask[1] |= irq_data->enable;
break;
case PM8607_INT_MASK_3:
mask[2] &= ~irq_data->offs;
mask[2] |= irq_data->enable;
break;
default:
dev_err(chip->dev, "wrong IRQ\n");
break;
}
}
/* update mask into registers */
for (i = 0; i < 3; i++) {
if (mask[i] != cached[i]) {
cached[i] = mask[i];
pm860x_reg_write(i2c, PM8607_INT_MASK_1 + i, mask[i]);
}
}
mutex_unlock(&chip->irq_lock);
}
static void pm860x_irq_enable(struct irq_data *data)
{
pm860x_irqs[data->hwirq].enable = pm860x_irqs[data->hwirq].offs;
}
static void pm860x_irq_disable(struct irq_data *data)
{
pm860x_irqs[data->hwirq].enable = 0;
}
static struct irq_chip pm860x_irq_chip = {
.name = "88pm860x",
.irq_bus_lock = pm860x_irq_lock,
.irq_bus_sync_unlock = pm860x_irq_sync_unlock,
.irq_enable = pm860x_irq_enable,
.irq_disable = pm860x_irq_disable,
};
static int pm860x_irq_domain_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw)
{
irq_set_chip_data(virq, d->host_data);
irq_set_chip_and_handler(virq, &pm860x_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops pm860x_irq_domain_ops = {
.map = pm860x_irq_domain_map,
.xlate = irq_domain_xlate_onetwocell,
};
static int device_irq_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
struct i2c_client *i2c = (chip->id == CHIP_PM8607) ?
chip->client : chip->companion;
unsigned char status_buf[INT_STATUS_NUM];
unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
int data, mask, ret = -EINVAL;
int nr_irqs, irq_base = -1;
struct device_node *node = i2c->dev.of_node;
mask = PM8607_B0_MISC1_INV_INT | PM8607_B0_MISC1_INT_CLEAR
| PM8607_B0_MISC1_INT_MASK;
data = 0;
chip->irq_mode = 0;
if (pdata && pdata->irq_mode) {
/*
* irq_mode defines the way of clearing interrupt. If it's 1,
* clear IRQ by write. Otherwise, clear it by read.
* This control bit is valid from 88PM8607 B0 steping.
*/
data |= PM8607_B0_MISC1_INT_CLEAR;
chip->irq_mode = 1;
}
ret = pm860x_set_bits(i2c, PM8607_B0_MISC1, mask, data);
if (ret < 0)
goto out;
/* mask all IRQs */
memset(status_buf, 0, INT_STATUS_NUM);
ret = pm860x_bulk_write(i2c, PM8607_INT_MASK_1,
INT_STATUS_NUM, status_buf);
if (ret < 0)
goto out;
if (chip->irq_mode) {
/* clear interrupt status by write */
memset(status_buf, 0xFF, INT_STATUS_NUM);
ret = pm860x_bulk_write(i2c, PM8607_INT_STATUS1,
INT_STATUS_NUM, status_buf);
} else {
/* clear interrupt status by read */
ret = pm860x_bulk_read(i2c, PM8607_INT_STATUS1,
INT_STATUS_NUM, status_buf);
}
if (ret < 0)
goto out;
mutex_init(&chip->irq_lock);
if (pdata && pdata->irq_base)
irq_base = pdata->irq_base;
nr_irqs = ARRAY_SIZE(pm860x_irqs);
chip->irq_base = irq_alloc_descs(irq_base, 0, nr_irqs, 0);
if (chip->irq_base < 0) {
dev_err(&i2c->dev, "Failed to allocate interrupts, ret:%d\n",
chip->irq_base);
ret = -EBUSY;
goto out;
}
irq_domain_add_legacy(node, nr_irqs, chip->irq_base, 0,
&pm860x_irq_domain_ops, chip);
chip->core_irq = i2c->irq;
if (!chip->core_irq)
goto out;
ret = request_threaded_irq(chip->core_irq, NULL, pm860x_irq,
flags | IRQF_ONESHOT, "88pm860x", chip);
if (ret) {
dev_err(chip->dev, "Failed to request IRQ: %d\n", ret);
chip->core_irq = 0;
}
return 0;
out:
chip->core_irq = 0;
return ret;
}
static void device_irq_exit(struct pm860x_chip *chip)
{
if (chip->core_irq)
free_irq(chip->core_irq, chip);
}
int pm8606_osc_enable(struct pm860x_chip *chip, unsigned short client)
{
int ret = -EIO;
struct i2c_client *i2c = (chip->id == CHIP_PM8606) ?
chip->client : chip->companion;
dev_dbg(chip->dev, "%s(B): client=0x%x\n", __func__, client);
dev_dbg(chip->dev, "%s(B): vote=0x%x status=%d\n",
__func__, chip->osc_vote,
chip->osc_status);
mutex_lock(&chip->osc_lock);
/* Update voting status */
chip->osc_vote |= client;
/* If reference group is off - turn on*/
if (chip->osc_status != PM8606_REF_GP_OSC_ON) {
chip->osc_status = PM8606_REF_GP_OSC_UNKNOWN;
/* Enable Reference group Vsys */
if (pm860x_set_bits(i2c, PM8606_VSYS,
PM8606_VSYS_EN, PM8606_VSYS_EN))
goto out;
/*Enable Internal Oscillator */
if (pm860x_set_bits(i2c, PM8606_MISC,
PM8606_MISC_OSC_EN, PM8606_MISC_OSC_EN))
goto out;
/* Update status (only if writes succeed) */
chip->osc_status = PM8606_REF_GP_OSC_ON;
}
mutex_unlock(&chip->osc_lock);
dev_dbg(chip->dev, "%s(A): vote=0x%x status=%d ret=%d\n",
__func__, chip->osc_vote,
chip->osc_status, ret);
return 0;
out:
mutex_unlock(&chip->osc_lock);
return ret;
}
EXPORT_SYMBOL(pm8606_osc_enable);
int pm8606_osc_disable(struct pm860x_chip *chip, unsigned short client)
{
int ret = -EIO;
struct i2c_client *i2c = (chip->id == CHIP_PM8606) ?
chip->client : chip->companion;
dev_dbg(chip->dev, "%s(B): client=0x%x\n", __func__, client);
dev_dbg(chip->dev, "%s(B): vote=0x%x status=%d\n",
__func__, chip->osc_vote,
chip->osc_status);
mutex_lock(&chip->osc_lock);
/* Update voting status */
chip->osc_vote &= ~(client);
/*
* If reference group is off and this is the last client to release
* - turn off
*/
if ((chip->osc_status != PM8606_REF_GP_OSC_OFF) &&
(chip->osc_vote == REF_GP_NO_CLIENTS)) {
chip->osc_status = PM8606_REF_GP_OSC_UNKNOWN;
/* Disable Reference group Vsys */
if (pm860x_set_bits(i2c, PM8606_VSYS, PM8606_VSYS_EN, 0))
goto out;
/* Disable Internal Oscillator */
if (pm860x_set_bits(i2c, PM8606_MISC, PM8606_MISC_OSC_EN, 0))
goto out;
chip->osc_status = PM8606_REF_GP_OSC_OFF;
}
mutex_unlock(&chip->osc_lock);
dev_dbg(chip->dev, "%s(A): vote=0x%x status=%d ret=%d\n",
__func__, chip->osc_vote,
chip->osc_status, ret);
return 0;
out:
mutex_unlock(&chip->osc_lock);
return ret;
}
EXPORT_SYMBOL(pm8606_osc_disable);
static void device_osc_init(struct i2c_client *i2c)
{
struct pm860x_chip *chip = i2c_get_clientdata(i2c);
mutex_init(&chip->osc_lock);
/* init portofino reference group voting and status */
/* Disable Reference group Vsys */
pm860x_set_bits(i2c, PM8606_VSYS, PM8606_VSYS_EN, 0);
/* Disable Internal Oscillator */
pm860x_set_bits(i2c, PM8606_MISC, PM8606_MISC_OSC_EN, 0);
chip->osc_vote = REF_GP_NO_CLIENTS;
chip->osc_status = PM8606_REF_GP_OSC_OFF;
}
static void device_bk_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
int ret, i;
if (pdata && pdata->backlight) {
if (pdata->num_backlights > ARRAY_SIZE(bk_devs))
pdata->num_backlights = ARRAY_SIZE(bk_devs);
for (i = 0; i < pdata->num_backlights; i++) {
bk_devs[i].platform_data = &pdata->backlight[i];
bk_devs[i].pdata_size =
sizeof(struct pm860x_backlight_pdata);
}
}
ret = mfd_add_devices(chip->dev, 0, bk_devs,
ARRAY_SIZE(bk_devs), NULL, 0, NULL);
if (ret < 0)
dev_err(chip->dev, "Failed to add backlight subdev\n");
}
static void device_led_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
int ret, i;
if (pdata && pdata->led) {
if (pdata->num_leds > ARRAY_SIZE(led_devs))
pdata->num_leds = ARRAY_SIZE(led_devs);
for (i = 0; i < pdata->num_leds; i++) {
led_devs[i].platform_data = &pdata->led[i];
led_devs[i].pdata_size =
sizeof(struct pm860x_led_pdata);
}
}
ret = mfd_add_devices(chip->dev, 0, led_devs,
ARRAY_SIZE(led_devs), NULL, 0, NULL);
if (ret < 0) {
dev_err(chip->dev, "Failed to add led subdev\n");
return;
}
}
static void device_regulator_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
int ret;
if (pdata == NULL)
return;
if (pdata->buck1) {
reg_devs[0].platform_data = pdata->buck1;
reg_devs[0].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->buck2) {
reg_devs[1].platform_data = pdata->buck2;
reg_devs[1].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->buck3) {
reg_devs[2].platform_data = pdata->buck3;
reg_devs[2].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo1) {
reg_devs[3].platform_data = pdata->ldo1;
reg_devs[3].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo2) {
reg_devs[4].platform_data = pdata->ldo2;
reg_devs[4].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo3) {
reg_devs[5].platform_data = pdata->ldo3;
reg_devs[5].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo4) {
reg_devs[6].platform_data = pdata->ldo4;
reg_devs[6].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo5) {
reg_devs[7].platform_data = pdata->ldo5;
reg_devs[7].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo6) {
reg_devs[8].platform_data = pdata->ldo6;
reg_devs[8].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo7) {
reg_devs[9].platform_data = pdata->ldo7;
reg_devs[9].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo8) {
reg_devs[10].platform_data = pdata->ldo8;
reg_devs[10].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo9) {
reg_devs[11].platform_data = pdata->ldo9;
reg_devs[11].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo10) {
reg_devs[12].platform_data = pdata->ldo10;
reg_devs[12].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo12) {
reg_devs[13].platform_data = pdata->ldo12;
reg_devs[13].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo_vibrator) {
reg_devs[14].platform_data = pdata->ldo_vibrator;
reg_devs[14].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo14) {
reg_devs[15].platform_data = pdata->ldo14;
reg_devs[15].pdata_size = sizeof(struct regulator_init_data);
}
ret = mfd_add_devices(chip->dev, 0, reg_devs,
ARRAY_SIZE(reg_devs), NULL, 0, NULL);
if (ret < 0) {
dev_err(chip->dev, "Failed to add regulator subdev\n");
return;
}
}
static void device_rtc_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
int ret;
if (!pdata)
return;
rtc_devs[0].platform_data = pdata->rtc;
rtc_devs[0].pdata_size = sizeof(struct pm860x_rtc_pdata);
rtc_devs[0].num_resources = ARRAY_SIZE(rtc_resources);
rtc_devs[0].resources = &rtc_resources[0];
ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
ARRAY_SIZE(rtc_devs), &rtc_resources[0],
chip->irq_base, NULL);
if (ret < 0)
dev_err(chip->dev, "Failed to add rtc subdev\n");
}
static void device_touch_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
int ret;
if (pdata == NULL)
return;
touch_devs[0].platform_data = pdata->touch;
touch_devs[0].pdata_size = sizeof(struct pm860x_touch_pdata);
touch_devs[0].num_resources = ARRAY_SIZE(touch_resources);
touch_devs[0].resources = &touch_resources[0];
ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
ARRAY_SIZE(touch_devs), &touch_resources[0],
chip->irq_base, NULL);
if (ret < 0)
dev_err(chip->dev, "Failed to add touch subdev\n");
}
static void device_power_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
int ret;
if (pdata == NULL)
return;
power_devs[0].platform_data = pdata->power;
power_devs[0].pdata_size = sizeof(struct pm860x_power_pdata);
power_devs[0].num_resources = ARRAY_SIZE(battery_resources);
power_devs[0].resources = &battery_resources[0],
ret = mfd_add_devices(chip->dev, 0, &power_devs[0], 1,
&battery_resources[0], chip->irq_base, NULL);
if (ret < 0)
dev_err(chip->dev, "Failed to add battery subdev\n");
power_devs[1].platform_data = pdata->power;
power_devs[1].pdata_size = sizeof(struct pm860x_power_pdata);
power_devs[1].num_resources = ARRAY_SIZE(charger_resources);
power_devs[1].resources = &charger_resources[0],
ret = mfd_add_devices(chip->dev, 0, &power_devs[1], 1,
&charger_resources[0], chip->irq_base, NULL);
if (ret < 0)
dev_err(chip->dev, "Failed to add charger subdev\n");
power_devs[2].platform_data = &preg_init_data;
power_devs[2].pdata_size = sizeof(struct regulator_init_data);
ret = mfd_add_devices(chip->dev, 0, &power_devs[2], 1,
NULL, chip->irq_base, NULL);
if (ret < 0)
dev_err(chip->dev, "Failed to add preg subdev\n");
if (pdata->chg_desc) {
pdata->chg_desc->charger_regulators =
&chg_desc_regulator_data[0];
pdata->chg_desc->num_charger_regulators =
ARRAY_SIZE(chg_desc_regulator_data),
power_devs[3].platform_data = pdata->chg_desc;
power_devs[3].pdata_size = sizeof(*pdata->chg_desc);
ret = mfd_add_devices(chip->dev, 0, &power_devs[3], 1,
NULL, chip->irq_base, NULL);
if (ret < 0)
dev_err(chip->dev, "Failed to add chg-manager subdev\n");
}
}
static void device_onkey_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
int ret;
onkey_devs[0].num_resources = ARRAY_SIZE(onkey_resources);
onkey_devs[0].resources = &onkey_resources[0],
ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
ARRAY_SIZE(onkey_devs), &onkey_resources[0],
chip->irq_base, NULL);
if (ret < 0)
dev_err(chip->dev, "Failed to add onkey subdev\n");
}
static void device_codec_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
int ret;
codec_devs[0].num_resources = ARRAY_SIZE(codec_resources);
codec_devs[0].resources = &codec_resources[0],
ret = mfd_add_devices(chip->dev, 0, &codec_devs[0],
ARRAY_SIZE(codec_devs), &codec_resources[0], 0,
NULL);
if (ret < 0)
dev_err(chip->dev, "Failed to add codec subdev\n");
}
static void device_8607_init(struct pm860x_chip *chip,
struct i2c_client *i2c,
struct pm860x_platform_data *pdata)
{
int data, ret;
ret = pm860x_reg_read(i2c, PM8607_CHIP_ID);
if (ret < 0) {
dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret);
goto out;
}
switch (ret & PM8607_VERSION_MASK) {
case 0x40:
case 0x50:
dev_info(chip->dev, "Marvell 88PM8607 (ID: %02x) detected\n",
ret);
break;
default:
dev_err(chip->dev,
"Failed to detect Marvell 88PM8607. Chip ID: %02x\n",
ret);
goto out;
}
ret = pm860x_reg_read(i2c, PM8607_BUCK3);
if (ret < 0) {
dev_err(chip->dev, "Failed to read BUCK3 register: %d\n", ret);
goto out;
}
if (ret & PM8607_BUCK3_DOUBLE)
chip->buck3_double = 1;
ret = pm860x_reg_read(i2c, PM8607_B0_MISC1);
if (ret < 0) {
dev_err(chip->dev, "Failed to read MISC1 register: %d\n", ret);
goto out;
}
if (pdata && (pdata->i2c_port == PI2C_PORT))
data = PM8607_B0_MISC1_PI2C;
else
data = 0;
ret = pm860x_set_bits(i2c, PM8607_B0_MISC1, PM8607_B0_MISC1_PI2C, data);
if (ret < 0) {
dev_err(chip->dev, "Failed to access MISC1:%d\n", ret);
goto out;
}
ret = device_irq_init(chip, pdata);
if (ret < 0)
goto out;
device_regulator_init(chip, pdata);
device_rtc_init(chip, pdata);
device_onkey_init(chip, pdata);
device_touch_init(chip, pdata);
device_power_init(chip, pdata);
device_codec_init(chip, pdata);
out:
return;
}
static void device_8606_init(struct pm860x_chip *chip,
struct i2c_client *i2c,
struct pm860x_platform_data *pdata)
{
device_osc_init(i2c);
device_bk_init(chip, pdata);
device_led_init(chip, pdata);
}
static int pm860x_device_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata)
{
chip->core_irq = 0;
switch (chip->id) {
case CHIP_PM8606:
device_8606_init(chip, chip->client, pdata);
break;
case CHIP_PM8607:
device_8607_init(chip, chip->client, pdata);
break;
}
if (chip->companion) {
switch (chip->id) {
case CHIP_PM8607:
device_8606_init(chip, chip->companion, pdata);
break;
case CHIP_PM8606:
device_8607_init(chip, chip->companion, pdata);
break;
}
}
return 0;
}
static void pm860x_device_exit(struct pm860x_chip *chip)
{
device_irq_exit(chip);
mfd_remove_devices(chip->dev);
}
static int verify_addr(struct i2c_client *i2c)
{
unsigned short addr_8607[] = {0x30, 0x34};
unsigned short addr_8606[] = {0x10, 0x11};
int size, i;
if (i2c == NULL)
return 0;
size = ARRAY_SIZE(addr_8606);
for (i = 0; i < size; i++) {
if (i2c->addr == *(addr_8606 + i))
return CHIP_PM8606;
}
size = ARRAY_SIZE(addr_8607);
for (i = 0; i < size; i++) {
if (i2c->addr == *(addr_8607 + i))
return CHIP_PM8607;
}
return 0;
}
static const struct regmap_config pm860x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int pm860x_dt_init(struct device_node *np,
struct device *dev,
struct pm860x_platform_data *pdata)
{
int ret;
pdata->irq_mode = of_property_read_bool(np, "marvell,88pm860x-irq-read-clr");
ret = of_property_read_u32(np, "marvell,88pm860x-slave-addr",
&pdata->companion_addr);
if (ret) {
dev_err(dev,
"Not found \"marvell,88pm860x-slave-addr\" property\n");
pdata->companion_addr = 0;
}
return 0;
}
static int pm860x_probe(struct i2c_client *client)
{
struct pm860x_platform_data *pdata = dev_get_platdata(&client->dev);
struct device_node *node = client->dev.of_node;
struct pm860x_chip *chip;
int ret;
if (node && !pdata) {
/* parse DT to get platform data */
pdata = devm_kzalloc(&client->dev,
sizeof(struct pm860x_platform_data),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
ret = pm860x_dt_init(node, &client->dev, pdata);
if (ret)
return ret;
} else if (!pdata) {
pr_info("No platform data in %s!\n", __func__);
return -EINVAL;
}
chip = devm_kzalloc(&client->dev,
sizeof(struct pm860x_chip), GFP_KERNEL);
if (chip == NULL)
return -ENOMEM;
chip->id = verify_addr(client);
chip->regmap = devm_regmap_init_i2c(client, &pm860x_regmap_config);
if (IS_ERR(chip->regmap)) {
ret = PTR_ERR(chip->regmap);
dev_err(&client->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
chip->client = client;
i2c_set_clientdata(client, chip);
chip->dev = &client->dev;
/*
* Both client and companion client shares same platform driver.
* Driver distinguishes them by pdata->companion_addr.
* pdata->companion_addr is only assigned if companion chip exists.
* At the same time, the companion_addr shouldn't equal to client
* address.
*/
if (pdata->companion_addr && (pdata->companion_addr != client->addr)) {
chip->companion_addr = pdata->companion_addr;
chip->companion = i2c_new_dummy_device(chip->client->adapter,
chip->companion_addr);
if (IS_ERR(chip->companion)) {
dev_err(&client->dev,
"Failed to allocate I2C companion device\n");
return PTR_ERR(chip->companion);
}
chip->regmap_companion = regmap_init_i2c(chip->companion,
&pm860x_regmap_config);
if (IS_ERR(chip->regmap_companion)) {
ret = PTR_ERR(chip->regmap_companion);
dev_err(&chip->companion->dev,
"Failed to allocate register map: %d\n", ret);
i2c_unregister_device(chip->companion);
return ret;
}
i2c_set_clientdata(chip->companion, chip);
}
pm860x_device_init(chip, pdata);
return 0;
}
static void pm860x_remove(struct i2c_client *client)
{
struct pm860x_chip *chip = i2c_get_clientdata(client);
pm860x_device_exit(chip);
if (chip->companion) {
regmap_exit(chip->regmap_companion);
i2c_unregister_device(chip->companion);
}
}
static int pm860x_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct pm860x_chip *chip = i2c_get_clientdata(client);
if (device_may_wakeup(dev) && chip->wakeup_flag)
enable_irq_wake(chip->core_irq);
return 0;
}
static int pm860x_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct pm860x_chip *chip = i2c_get_clientdata(client);
if (device_may_wakeup(dev) && chip->wakeup_flag)
disable_irq_wake(chip->core_irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(pm860x_pm_ops, pm860x_suspend, pm860x_resume);
static const struct i2c_device_id pm860x_id_table[] = {
{ "88PM860x", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, pm860x_id_table);
static const struct of_device_id pm860x_dt_ids[] = {
{ .compatible = "marvell,88pm860x", },
{},
};
MODULE_DEVICE_TABLE(of, pm860x_dt_ids);
static struct i2c_driver pm860x_driver = {
.driver = {
.name = "88PM860x",
.pm = pm_sleep_ptr(&pm860x_pm_ops),
.of_match_table = pm860x_dt_ids,
},
.probe = pm860x_probe,
.remove = pm860x_remove,
.id_table = pm860x_id_table,
};
static int __init pm860x_i2c_init(void)
{
int ret;
ret = i2c_add_driver(&pm860x_driver);
if (ret != 0)
pr_err("Failed to register 88PM860x I2C driver: %d\n", ret);
return ret;
}
subsys_initcall(pm860x_i2c_init);
static void __exit pm860x_i2c_exit(void)
{
i2c_del_driver(&pm860x_driver);
}
module_exit(pm860x_i2c_exit);
MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM860x");
MODULE_AUTHOR("Haojian Zhuang <[email protected]>");
| linux-master | drivers/mfd/88pm860x-core.c |
/*
*
* Handle TWL4030 Power initialization
*
* Copyright (C) 2008 Nokia Corporation
* Copyright (C) 2006 Texas Instruments, Inc
*
* Written by Kalle Jokiniemi
* Peter De Schrijver <[email protected]>
* Several fixes by Amit Kucheria <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
* archive for more details.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/mfd/twl.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <asm/mach-types.h>
static u8 twl4030_start_script_address = 0x2b;
/* Register bits for P1, P2 and P3_SW_EVENTS */
#define PWR_STOPON_PRWON BIT(6)
#define PWR_STOPON_SYSEN BIT(5)
#define PWR_ENABLE_WARMRESET BIT(4)
#define PWR_LVL_WAKEUP BIT(3)
#define PWR_DEVACT BIT(2)
#define PWR_DEVSLP BIT(1)
#define PWR_DEVOFF BIT(0)
/* Register bits for CFG_P1_TRANSITION (also for P2 and P3) */
#define STARTON_SWBUG BIT(7) /* Start on watchdog */
#define STARTON_VBUS BIT(5) /* Start on VBUS */
#define STARTON_VBAT BIT(4) /* Start on battery insert */
#define STARTON_RTC BIT(3) /* Start on RTC */
#define STARTON_USB BIT(2) /* Start on USB host */
#define STARTON_CHG BIT(1) /* Start on charger */
#define STARTON_PWON BIT(0) /* Start on PWRON button */
#define SEQ_OFFSYNC (1 << 0)
#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
/* resource - hfclk */
#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
/* PM events */
#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
#define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
#define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
#define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
#define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
#define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
#define END_OF_SCRIPT 0x3f
#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
#define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
#define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
#define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
/* resource configuration registers
<RESOURCE>_DEV_GRP at address 'n+0'
<RESOURCE>_TYPE at address 'n+1'
<RESOURCE>_REMAP at address 'n+2'
<RESOURCE>_DEDICATED at address 'n+3'
*/
#define DEV_GRP_OFFSET 0
#define TYPE_OFFSET 1
#define REMAP_OFFSET 2
#define DEDICATED_OFFSET 3
/* Bit positions in the registers */
/* <RESOURCE>_DEV_GRP */
#define DEV_GRP_SHIFT 5
#define DEV_GRP_MASK (7 << DEV_GRP_SHIFT)
/* <RESOURCE>_TYPE */
#define TYPE_SHIFT 0
#define TYPE_MASK (7 << TYPE_SHIFT)
#define TYPE2_SHIFT 3
#define TYPE2_MASK (3 << TYPE2_SHIFT)
/* <RESOURCE>_REMAP */
#define SLEEP_STATE_SHIFT 0
#define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT)
#define OFF_STATE_SHIFT 4
#define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT)
static u8 res_config_addrs[] = {
[RES_VAUX1] = 0x17,
[RES_VAUX2] = 0x1b,
[RES_VAUX3] = 0x1f,
[RES_VAUX4] = 0x23,
[RES_VMMC1] = 0x27,
[RES_VMMC2] = 0x2b,
[RES_VPLL1] = 0x2f,
[RES_VPLL2] = 0x33,
[RES_VSIM] = 0x37,
[RES_VDAC] = 0x3b,
[RES_VINTANA1] = 0x3f,
[RES_VINTANA2] = 0x43,
[RES_VINTDIG] = 0x47,
[RES_VIO] = 0x4b,
[RES_VDD1] = 0x55,
[RES_VDD2] = 0x63,
[RES_VUSB_1V5] = 0x71,
[RES_VUSB_1V8] = 0x74,
[RES_VUSB_3V1] = 0x77,
[RES_VUSBCP] = 0x7a,
[RES_REGEN] = 0x7f,
[RES_NRES_PWRON] = 0x82,
[RES_CLKEN] = 0x85,
[RES_SYSEN] = 0x88,
[RES_HFCLKOUT] = 0x8b,
[RES_32KCLKOUT] = 0x8e,
[RES_RESET] = 0x91,
[RES_MAIN_REF] = 0x94,
};
/*
* Usable values for .remap_sleep and .remap_off
* Based on table "5.3.3 Resource Operating modes"
*/
enum {
TWL_REMAP_OFF = 0,
TWL_REMAP_SLEEP = 8,
TWL_REMAP_ACTIVE = 9,
};
/*
* Macros to configure the PM register states for various resources.
* Note that we can make MSG_SINGULAR etc private to this driver once
* omap3 has been made DT only.
*/
#define TWL_DFLT_DELAY 2 /* typically 2 32 KiHz cycles */
#define TWL_DEV_GRP_P123 (DEV_GRP_P1 | DEV_GRP_P2 | DEV_GRP_P3)
#define TWL_RESOURCE_SET(res, state) \
{ MSG_SINGULAR(DEV_GRP_NULL, (res), (state)), TWL_DFLT_DELAY }
#define TWL_RESOURCE_ON(res) TWL_RESOURCE_SET(res, RES_STATE_ACTIVE)
#define TWL_RESOURCE_OFF(res) TWL_RESOURCE_SET(res, RES_STATE_OFF)
#define TWL_RESOURCE_RESET(res) TWL_RESOURCE_SET(res, RES_STATE_WRST)
/*
* It seems that type1 and type2 is just the resource init order
* number for the type1 and type2 group.
*/
#define TWL_RESOURCE_SET_ACTIVE(res, state) \
{ MSG_SINGULAR(DEV_GRP_NULL, (res), RES_STATE_ACTIVE), (state) }
#define TWL_RESOURCE_GROUP_RESET(group, type1, type2) \
{ MSG_BROADCAST(DEV_GRP_NULL, (group), (type1), (type2), \
RES_STATE_WRST), TWL_DFLT_DELAY }
#define TWL_RESOURCE_GROUP_SLEEP(group, type, type2) \
{ MSG_BROADCAST(DEV_GRP_NULL, (group), (type), (type2), \
RES_STATE_SLEEP), TWL_DFLT_DELAY }
#define TWL_RESOURCE_GROUP_ACTIVE(group, type, type2) \
{ MSG_BROADCAST(DEV_GRP_NULL, (group), (type), (type2), \
RES_STATE_ACTIVE), TWL_DFLT_DELAY }
#define TWL_REMAP_SLEEP(res, devgrp, typ, typ2) \
{ .resource = (res), .devgroup = (devgrp), \
.type = (typ), .type2 = (typ2), \
.remap_off = TWL_REMAP_OFF, \
.remap_sleep = TWL_REMAP_SLEEP, }
#define TWL_REMAP_OFF(res, devgrp, typ, typ2) \
{ .resource = (res), .devgroup = (devgrp), \
.type = (typ), .type2 = (typ2), \
.remap_off = TWL_REMAP_OFF, .remap_sleep = TWL_REMAP_OFF, }
static int twl4030_write_script_byte(u8 address, u8 byte)
{
int err;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_MEMORY_ADDRESS);
if (err)
goto out;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, byte, R_MEMORY_DATA);
out:
return err;
}
static int twl4030_write_script_ins(u8 address, u16 pmb_message,
u8 delay, u8 next)
{
int err;
address *= 4;
err = twl4030_write_script_byte(address++, pmb_message >> 8);
if (err)
goto out;
err = twl4030_write_script_byte(address++, pmb_message & 0xff);
if (err)
goto out;
err = twl4030_write_script_byte(address++, delay);
if (err)
goto out;
err = twl4030_write_script_byte(address++, next);
out:
return err;
}
static int twl4030_write_script(u8 address, struct twl4030_ins *script,
int len)
{
int err = -EINVAL;
for (; len; len--, address++, script++) {
if (len == 1) {
err = twl4030_write_script_ins(address,
script->pmb_message,
script->delay,
END_OF_SCRIPT);
if (err)
break;
} else {
err = twl4030_write_script_ins(address,
script->pmb_message,
script->delay,
address + 1);
if (err)
break;
}
}
return err;
}
static int twl4030_config_wakeup3_sequence(u8 address)
{
int err;
u8 data;
/* Set SLEEP to ACTIVE SEQ address for P3 */
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A3);
if (err)
goto out;
/* P3 LVL_WAKEUP should be on LEVEL */
err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P3_SW_EVENTS);
if (err)
goto out;
data |= PWR_LVL_WAKEUP;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P3_SW_EVENTS);
out:
if (err)
pr_err("TWL4030 wakeup sequence for P3 config error\n");
return err;
}
static int
twl4030_config_wakeup12_sequence(const struct twl4030_power_data *pdata,
u8 address)
{
int err = 0;
u8 data;
/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A12);
if (err)
goto out;
/* P1/P2 LVL_WAKEUP should be on LEVEL */
err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P1_SW_EVENTS);
if (err)
goto out;
data |= PWR_LVL_WAKEUP;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P1_SW_EVENTS);
if (err)
goto out;
err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P2_SW_EVENTS);
if (err)
goto out;
data |= PWR_LVL_WAKEUP;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P2_SW_EVENTS);
if (err)
goto out;
if (pdata->ac_charger_quirk || machine_is_omap_3430sdp() ||
machine_is_omap_ldp()) {
/* Disabling AC charger effect on sleep-active transitions */
err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data,
R_CFG_P1_TRANSITION);
if (err)
goto out;
data &= ~STARTON_CHG;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data,
R_CFG_P1_TRANSITION);
if (err)
goto out;
}
out:
if (err)
pr_err("TWL4030 wakeup sequence for P1 and P2" \
"config error\n");
return err;
}
static int twl4030_config_sleep_sequence(u8 address)
{
int err;
/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_A2S);
if (err)
pr_err("TWL4030 sleep sequence config error\n");
return err;
}
static int twl4030_config_warmreset_sequence(u8 address)
{
int err;
u8 rd_data;
/* Set WARM RESET SEQ address for P1 */
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_WARM);
if (err)
goto out;
/* P1/P2/P3 enable WARMRESET */
err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P1_SW_EVENTS);
if (err)
goto out;
rd_data |= PWR_ENABLE_WARMRESET;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P1_SW_EVENTS);
if (err)
goto out;
err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P2_SW_EVENTS);
if (err)
goto out;
rd_data |= PWR_ENABLE_WARMRESET;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P2_SW_EVENTS);
if (err)
goto out;
err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P3_SW_EVENTS);
if (err)
goto out;
rd_data |= PWR_ENABLE_WARMRESET;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P3_SW_EVENTS);
out:
if (err)
pr_err("TWL4030 warmreset seq config error\n");
return err;
}
static int twl4030_configure_resource(struct twl4030_resconfig *rconfig)
{
int rconfig_addr;
int err;
u8 type;
u8 grp;
u8 remap;
if (rconfig->resource > TOTAL_RESOURCES) {
pr_err("TWL4030 Resource %d does not exist\n",
rconfig->resource);
return -EINVAL;
}
rconfig_addr = res_config_addrs[rconfig->resource];
/* Set resource group */
err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &grp,
rconfig_addr + DEV_GRP_OFFSET);
if (err) {
pr_err("TWL4030 Resource %d group could not be read\n",
rconfig->resource);
return err;
}
if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
grp &= ~DEV_GRP_MASK;
grp |= rconfig->devgroup << DEV_GRP_SHIFT;
err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
grp, rconfig_addr + DEV_GRP_OFFSET);
if (err < 0) {
pr_err("TWL4030 failed to program devgroup\n");
return err;
}
}
/* Set resource types */
err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &type,
rconfig_addr + TYPE_OFFSET);
if (err < 0) {
pr_err("TWL4030 Resource %d type could not be read\n",
rconfig->resource);
return err;
}
if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
type &= ~TYPE_MASK;
type |= rconfig->type << TYPE_SHIFT;
}
if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
type &= ~TYPE2_MASK;
type |= rconfig->type2 << TYPE2_SHIFT;
}
err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
type, rconfig_addr + TYPE_OFFSET);
if (err < 0) {
pr_err("TWL4030 failed to program resource type\n");
return err;
}
/* Set remap states */
err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &remap,
rconfig_addr + REMAP_OFFSET);
if (err < 0) {
pr_err("TWL4030 Resource %d remap could not be read\n",
rconfig->resource);
return err;
}
if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
remap &= ~OFF_STATE_MASK;
remap |= rconfig->remap_off << OFF_STATE_SHIFT;
}
if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
remap &= ~SLEEP_STATE_MASK;
remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
}
err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
remap,
rconfig_addr + REMAP_OFFSET);
if (err < 0) {
pr_err("TWL4030 failed to program remap\n");
return err;
}
return 0;
}
static int load_twl4030_script(const struct twl4030_power_data *pdata,
struct twl4030_script *tscript,
u8 address)
{
int err;
static int order;
/* Make sure the script isn't going beyond last valid address (0x3f) */
if ((address + tscript->size) > END_OF_SCRIPT) {
pr_err("TWL4030 scripts too big error\n");
return -EINVAL;
}
err = twl4030_write_script(address, tscript->script, tscript->size);
if (err)
goto out;
if (tscript->flags & TWL4030_WRST_SCRIPT) {
err = twl4030_config_warmreset_sequence(address);
if (err)
goto out;
}
if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
/* Reset any existing sleep script to avoid hangs on reboot */
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
R_SEQ_ADD_A2S);
if (err)
goto out;
err = twl4030_config_wakeup12_sequence(pdata, address);
if (err)
goto out;
order = 1;
}
if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
err = twl4030_config_wakeup3_sequence(address);
if (err)
goto out;
}
if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
if (!order)
pr_warn("TWL4030: Bad order of scripts (sleep script before wakeup) Leads to boot failure on some boards\n");
err = twl4030_config_sleep_sequence(address);
}
out:
return err;
}
int twl4030_remove_script(u8 flags)
{
int err = 0;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
TWL4030_PM_MASTER_PROTECT_KEY);
if (err) {
pr_err("twl4030: unable to unlock PROTECT_KEY\n");
return err;
}
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
TWL4030_PM_MASTER_PROTECT_KEY);
if (err) {
pr_err("twl4030: unable to unlock PROTECT_KEY\n");
return err;
}
if (flags & TWL4030_WRST_SCRIPT) {
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
R_SEQ_ADD_WARM);
if (err)
return err;
}
if (flags & TWL4030_WAKEUP12_SCRIPT) {
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
R_SEQ_ADD_S2A12);
if (err)
return err;
}
if (flags & TWL4030_WAKEUP3_SCRIPT) {
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
R_SEQ_ADD_S2A3);
if (err)
return err;
}
if (flags & TWL4030_SLEEP_SCRIPT) {
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
R_SEQ_ADD_A2S);
if (err)
return err;
}
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
TWL4030_PM_MASTER_PROTECT_KEY);
if (err)
pr_err("TWL4030 Unable to relock registers\n");
return err;
}
static int
twl4030_power_configure_scripts(const struct twl4030_power_data *pdata)
{
int err;
int i;
u8 address = twl4030_start_script_address;
for (i = 0; i < pdata->num; i++) {
err = load_twl4030_script(pdata, pdata->scripts[i], address);
if (err)
return err;
address += pdata->scripts[i]->size;
}
return 0;
}
static void twl4030_patch_rconfig(struct twl4030_resconfig *common,
struct twl4030_resconfig *board)
{
while (common->resource) {
struct twl4030_resconfig *b = board;
while (b->resource) {
if (b->resource == common->resource) {
*common = *b;
break;
}
b++;
}
common++;
}
}
static int
twl4030_power_configure_resources(const struct twl4030_power_data *pdata)
{
struct twl4030_resconfig *resconfig = pdata->resource_config;
struct twl4030_resconfig *boardconf = pdata->board_config;
int err;
if (resconfig) {
if (boardconf)
twl4030_patch_rconfig(resconfig, boardconf);
while (resconfig->resource) {
err = twl4030_configure_resource(resconfig);
if (err)
return err;
resconfig++;
}
}
return 0;
}
static int twl4030_starton_mask_and_set(u8 bitmask, u8 bitvalues)
{
u8 regs[3] = { TWL4030_PM_MASTER_CFG_P1_TRANSITION,
TWL4030_PM_MASTER_CFG_P2_TRANSITION,
TWL4030_PM_MASTER_CFG_P3_TRANSITION, };
u8 val;
int i, err;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
TWL4030_PM_MASTER_PROTECT_KEY);
if (err)
goto relock;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
TWL4030_PM_MASTER_KEY_CFG2,
TWL4030_PM_MASTER_PROTECT_KEY);
if (err)
goto relock;
for (i = 0; i < sizeof(regs); i++) {
err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER,
&val, regs[i]);
if (err)
break;
val = (~bitmask & val) | (bitmask & bitvalues);
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
val, regs[i]);
if (err)
break;
}
if (err)
pr_err("TWL4030 Register access failed: %i\n", err);
relock:
return twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
TWL4030_PM_MASTER_PROTECT_KEY);
}
/*
* In master mode, start the power off sequence.
* After a successful execution, TWL shuts down the power to the SoC
* and all peripherals connected to it.
*/
void twl4030_power_off(void)
{
int err;
/* Disable start on charger or VBUS as it can break poweroff */
err = twl4030_starton_mask_and_set(STARTON_VBUS | STARTON_CHG, 0);
if (err)
pr_err("TWL4030 Unable to configure start-up\n");
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, PWR_DEVOFF,
TWL4030_PM_MASTER_P1_SW_EVENTS);
if (err)
pr_err("TWL4030 Unable to power off\n");
}
static bool twl4030_power_use_poweroff(const struct twl4030_power_data *pdata,
struct device_node *node)
{
if (pdata && pdata->use_poweroff)
return true;
if (of_property_read_bool(node, "ti,system-power-controller"))
return true;
if (of_property_read_bool(node, "ti,use_poweroff"))
return true;
return false;
}
#ifdef CONFIG_OF
/* Generic warm reset configuration for omap3 */
static struct twl4030_ins omap3_wrst_seq[] = {
TWL_RESOURCE_OFF(RES_NRES_PWRON),
TWL_RESOURCE_OFF(RES_RESET),
TWL_RESOURCE_RESET(RES_MAIN_REF),
TWL_RESOURCE_GROUP_RESET(RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2),
TWL_RESOURCE_RESET(RES_VUSB_3V1),
TWL_RESOURCE_RESET(RES_VMMC1),
TWL_RESOURCE_GROUP_RESET(RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1),
TWL_RESOURCE_GROUP_RESET(RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0),
TWL_RESOURCE_ON(RES_RESET),
TWL_RESOURCE_ON(RES_NRES_PWRON),
};
static struct twl4030_script omap3_wrst_script = {
.script = omap3_wrst_seq,
.size = ARRAY_SIZE(omap3_wrst_seq),
.flags = TWL4030_WRST_SCRIPT,
};
static struct twl4030_script *omap3_reset_scripts[] = {
&omap3_wrst_script,
};
static struct twl4030_resconfig omap3_rconfig[] = {
TWL_REMAP_SLEEP(RES_HFCLKOUT, DEV_GRP_P3, -1, -1),
TWL_REMAP_SLEEP(RES_VDD1, DEV_GRP_P1, -1, -1),
TWL_REMAP_SLEEP(RES_VDD2, DEV_GRP_P1, -1, -1),
{ 0, 0 },
};
static struct twl4030_power_data omap3_reset = {
.scripts = omap3_reset_scripts,
.num = ARRAY_SIZE(omap3_reset_scripts),
.resource_config = omap3_rconfig,
};
/* Recommended generic default idle configuration for off-idle */
/* Broadcast message to put res to sleep */
static struct twl4030_ins omap3_idle_sleep_on_seq[] = {
TWL_RESOURCE_GROUP_SLEEP(RES_GRP_ALL, RES_TYPE_ALL, 0),
};
static struct twl4030_script omap3_idle_sleep_on_script = {
.script = omap3_idle_sleep_on_seq,
.size = ARRAY_SIZE(omap3_idle_sleep_on_seq),
.flags = TWL4030_SLEEP_SCRIPT,
};
/* Broadcast message to put res to active */
static struct twl4030_ins omap3_idle_wakeup_p12_seq[] = {
TWL_RESOURCE_GROUP_ACTIVE(RES_GRP_ALL, RES_TYPE_ALL, 0),
};
static struct twl4030_script omap3_idle_wakeup_p12_script = {
.script = omap3_idle_wakeup_p12_seq,
.size = ARRAY_SIZE(omap3_idle_wakeup_p12_seq),
.flags = TWL4030_WAKEUP12_SCRIPT,
};
/* Broadcast message to put res to active */
static struct twl4030_ins omap3_idle_wakeup_p3_seq[] = {
TWL_RESOURCE_SET_ACTIVE(RES_CLKEN, 0x37),
TWL_RESOURCE_GROUP_ACTIVE(RES_GRP_ALL, RES_TYPE_ALL, 0),
};
static struct twl4030_script omap3_idle_wakeup_p3_script = {
.script = omap3_idle_wakeup_p3_seq,
.size = ARRAY_SIZE(omap3_idle_wakeup_p3_seq),
.flags = TWL4030_WAKEUP3_SCRIPT,
};
static struct twl4030_script *omap3_idle_scripts[] = {
&omap3_idle_wakeup_p12_script,
&omap3_idle_wakeup_p3_script,
&omap3_wrst_script,
&omap3_idle_sleep_on_script,
};
/*
* Recommended configuration based on "Recommended Sleep
* Sequences for the Zoom Platform":
* http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf
* Note that the type1 and type2 seem to be just the init order number
* for type1 and type2 groups as specified in the document mentioned
* above.
*/
static struct twl4030_resconfig omap3_idle_rconfig[] = {
TWL_REMAP_SLEEP(RES_VAUX1, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_SLEEP(RES_VAUX2, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_SLEEP(RES_VAUX3, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_SLEEP(RES_VAUX4, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_SLEEP(RES_VMMC1, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_SLEEP(RES_VMMC2, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_OFF(RES_VPLL1, DEV_GRP_P1, 3, 1),
TWL_REMAP_SLEEP(RES_VPLL2, DEV_GRP_P1, 0, 0),
TWL_REMAP_SLEEP(RES_VSIM, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_SLEEP(RES_VDAC, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_SLEEP(RES_VINTANA1, TWL_DEV_GRP_P123, 1, 2),
TWL_REMAP_SLEEP(RES_VINTANA2, TWL_DEV_GRP_P123, 0, 2),
TWL_REMAP_SLEEP(RES_VINTDIG, TWL_DEV_GRP_P123, 1, 2),
TWL_REMAP_SLEEP(RES_VIO, TWL_DEV_GRP_P123, 2, 2),
TWL_REMAP_OFF(RES_VDD1, DEV_GRP_P1, 4, 1),
TWL_REMAP_OFF(RES_VDD2, DEV_GRP_P1, 3, 1),
TWL_REMAP_SLEEP(RES_VUSB_1V5, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_SLEEP(RES_VUSB_1V8, TWL4030_RESCONFIG_UNDEF, 0, 0),
TWL_REMAP_SLEEP(RES_VUSB_3V1, TWL_DEV_GRP_P123, 0, 0),
/* Resource #20 USB charge pump skipped */
TWL_REMAP_SLEEP(RES_REGEN, TWL_DEV_GRP_P123, 2, 1),
TWL_REMAP_SLEEP(RES_NRES_PWRON, TWL_DEV_GRP_P123, 0, 1),
TWL_REMAP_SLEEP(RES_CLKEN, TWL_DEV_GRP_P123, 3, 2),
TWL_REMAP_SLEEP(RES_SYSEN, TWL_DEV_GRP_P123, 6, 1),
TWL_REMAP_SLEEP(RES_HFCLKOUT, DEV_GRP_P3, 0, 2),
TWL_REMAP_SLEEP(RES_32KCLKOUT, TWL_DEV_GRP_P123, 0, 0),
TWL_REMAP_SLEEP(RES_RESET, TWL_DEV_GRP_P123, 6, 0),
TWL_REMAP_SLEEP(RES_MAIN_REF, TWL_DEV_GRP_P123, 0, 0),
{ /* Terminator */ },
};
static struct twl4030_power_data omap3_idle = {
.scripts = omap3_idle_scripts,
.num = ARRAY_SIZE(omap3_idle_scripts),
.resource_config = omap3_idle_rconfig,
};
/* Disable 32 KiHz oscillator during idle */
static struct twl4030_resconfig osc_off_rconfig[] = {
TWL_REMAP_OFF(RES_CLKEN, DEV_GRP_P1 | DEV_GRP_P3, 3, 2),
{ /* Terminator */ },
};
static struct twl4030_power_data osc_off_idle = {
.scripts = omap3_idle_scripts,
.num = ARRAY_SIZE(omap3_idle_scripts),
.resource_config = omap3_idle_rconfig,
.board_config = osc_off_rconfig,
};
static struct twl4030_power_data omap3_idle_ac_quirk = {
.scripts = omap3_idle_scripts,
.num = ARRAY_SIZE(omap3_idle_scripts),
.resource_config = omap3_idle_rconfig,
.ac_charger_quirk = true,
};
static struct twl4030_power_data omap3_idle_ac_quirk_osc_off = {
.scripts = omap3_idle_scripts,
.num = ARRAY_SIZE(omap3_idle_scripts),
.resource_config = omap3_idle_rconfig,
.board_config = osc_off_rconfig,
.ac_charger_quirk = true,
};
static const struct of_device_id twl4030_power_of_match[] = {
{
.compatible = "ti,twl4030-power",
},
{
.compatible = "ti,twl4030-power-reset",
.data = &omap3_reset,
},
{
.compatible = "ti,twl4030-power-idle",
.data = &omap3_idle,
},
{
.compatible = "ti,twl4030-power-idle-osc-off",
.data = &osc_off_idle,
},
{
.compatible = "ti,twl4030-power-omap3-sdp",
.data = &omap3_idle_ac_quirk,
},
{
.compatible = "ti,twl4030-power-omap3-ldp",
.data = &omap3_idle_ac_quirk_osc_off,
},
{
.compatible = "ti,twl4030-power-omap3-evm",
.data = &omap3_idle_ac_quirk,
},
{ },
};
MODULE_DEVICE_TABLE(of, twl4030_power_of_match);
#endif /* CONFIG_OF */
static int twl4030_power_probe(struct platform_device *pdev)
{
const struct twl4030_power_data *pdata = dev_get_platdata(&pdev->dev);
struct device_node *node = pdev->dev.of_node;
const struct of_device_id *match;
int err = 0;
int err2 = 0;
u8 val;
if (!pdata && !node) {
dev_err(&pdev->dev, "Platform data is missing\n");
return -EINVAL;
}
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
TWL4030_PM_MASTER_PROTECT_KEY);
err |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
TWL4030_PM_MASTER_KEY_CFG2,
TWL4030_PM_MASTER_PROTECT_KEY);
if (err) {
pr_err("TWL4030 Unable to unlock registers\n");
return err;
}
match = of_match_device(of_match_ptr(twl4030_power_of_match),
&pdev->dev);
if (match && match->data)
pdata = match->data;
if (pdata) {
err = twl4030_power_configure_scripts(pdata);
if (err) {
pr_err("TWL4030 failed to load scripts\n");
goto relock;
}
err = twl4030_power_configure_resources(pdata);
if (err) {
pr_err("TWL4030 failed to configure resource\n");
goto relock;
}
}
/* Board has to be wired properly to use this feature */
if (twl4030_power_use_poweroff(pdata, node) && !pm_power_off) {
/* Default for SEQ_OFFSYNC is set, lets ensure this */
err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
TWL4030_PM_MASTER_CFG_P123_TRANSITION);
if (err) {
pr_warn("TWL4030 Unable to read registers\n");
} else if (!(val & SEQ_OFFSYNC)) {
val |= SEQ_OFFSYNC;
err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
TWL4030_PM_MASTER_CFG_P123_TRANSITION);
if (err) {
pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
goto relock;
}
}
pm_power_off = twl4030_power_off;
}
relock:
err2 = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
TWL4030_PM_MASTER_PROTECT_KEY);
if (err2) {
pr_err("TWL4030 Unable to relock registers\n");
return err2;
}
return err;
}
static struct platform_driver twl4030_power_driver = {
.driver = {
.name = "twl4030_power",
.of_match_table = of_match_ptr(twl4030_power_of_match),
},
.probe = twl4030_power_probe,
};
module_platform_driver(twl4030_power_driver);
MODULE_AUTHOR("Nokia Corporation");
MODULE_AUTHOR("Texas Instruments, Inc.");
MODULE_DESCRIPTION("Power management for TWL4030");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:twl4030_power");
| linux-master | drivers/mfd/twl4030-power.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Interrupt controller support for MAX8998
//
// Copyright (C) 2010 Samsung Electronics Co.Ltd
// Author: Joonyoung Shim <[email protected]>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/mfd/max8998-private.h>
struct max8998_irq_data {
int reg;
int mask;
};
static struct max8998_irq_data max8998_irqs[] = {
[MAX8998_IRQ_DCINF] = {
.reg = 1,
.mask = MAX8998_IRQ_DCINF_MASK,
},
[MAX8998_IRQ_DCINR] = {
.reg = 1,
.mask = MAX8998_IRQ_DCINR_MASK,
},
[MAX8998_IRQ_JIGF] = {
.reg = 1,
.mask = MAX8998_IRQ_JIGF_MASK,
},
[MAX8998_IRQ_JIGR] = {
.reg = 1,
.mask = MAX8998_IRQ_JIGR_MASK,
},
[MAX8998_IRQ_PWRONF] = {
.reg = 1,
.mask = MAX8998_IRQ_PWRONF_MASK,
},
[MAX8998_IRQ_PWRONR] = {
.reg = 1,
.mask = MAX8998_IRQ_PWRONR_MASK,
},
[MAX8998_IRQ_WTSREVNT] = {
.reg = 2,
.mask = MAX8998_IRQ_WTSREVNT_MASK,
},
[MAX8998_IRQ_SMPLEVNT] = {
.reg = 2,
.mask = MAX8998_IRQ_SMPLEVNT_MASK,
},
[MAX8998_IRQ_ALARM1] = {
.reg = 2,
.mask = MAX8998_IRQ_ALARM1_MASK,
},
[MAX8998_IRQ_ALARM0] = {
.reg = 2,
.mask = MAX8998_IRQ_ALARM0_MASK,
},
[MAX8998_IRQ_ONKEY1S] = {
.reg = 3,
.mask = MAX8998_IRQ_ONKEY1S_MASK,
},
[MAX8998_IRQ_TOPOFFR] = {
.reg = 3,
.mask = MAX8998_IRQ_TOPOFFR_MASK,
},
[MAX8998_IRQ_DCINOVPR] = {
.reg = 3,
.mask = MAX8998_IRQ_DCINOVPR_MASK,
},
[MAX8998_IRQ_CHGRSTF] = {
.reg = 3,
.mask = MAX8998_IRQ_CHGRSTF_MASK,
},
[MAX8998_IRQ_DONER] = {
.reg = 3,
.mask = MAX8998_IRQ_DONER_MASK,
},
[MAX8998_IRQ_CHGFAULT] = {
.reg = 3,
.mask = MAX8998_IRQ_CHGFAULT_MASK,
},
[MAX8998_IRQ_LOBAT1] = {
.reg = 4,
.mask = MAX8998_IRQ_LOBAT1_MASK,
},
[MAX8998_IRQ_LOBAT2] = {
.reg = 4,
.mask = MAX8998_IRQ_LOBAT2_MASK,
},
};
static inline struct max8998_irq_data *
irq_to_max8998_irq(struct max8998_dev *max8998, struct irq_data *data)
{
return &max8998_irqs[data->hwirq];
}
static void max8998_irq_lock(struct irq_data *data)
{
struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
mutex_lock(&max8998->irqlock);
}
static void max8998_irq_sync_unlock(struct irq_data *data)
{
struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
int i;
for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
/*
* If there's been a change in the mask write it back
* to the hardware.
*/
if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
max8998->irq_masks_cur[i]);
}
}
mutex_unlock(&max8998->irqlock);
}
static void max8998_irq_unmask(struct irq_data *data)
{
struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
}
static void max8998_irq_mask(struct irq_data *data)
{
struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
}
static struct irq_chip max8998_irq_chip = {
.name = "max8998",
.irq_bus_lock = max8998_irq_lock,
.irq_bus_sync_unlock = max8998_irq_sync_unlock,
.irq_mask = max8998_irq_mask,
.irq_unmask = max8998_irq_unmask,
};
static irqreturn_t max8998_irq_thread(int irq, void *data)
{
struct max8998_dev *max8998 = data;
u8 irq_reg[MAX8998_NUM_IRQ_REGS];
int ret;
int i;
ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
MAX8998_NUM_IRQ_REGS, irq_reg);
if (ret < 0) {
dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
ret);
return IRQ_NONE;
}
/* Apply masking */
for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
irq_reg[i] &= ~max8998->irq_masks_cur[i];
/* Report */
for (i = 0; i < MAX8998_IRQ_NR; i++) {
if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) {
irq = irq_find_mapping(max8998->irq_domain, i);
if (WARN_ON(!irq)) {
disable_irq_nosync(max8998->irq);
return IRQ_NONE;
}
handle_nested_irq(irq);
}
}
return IRQ_HANDLED;
}
int max8998_irq_resume(struct max8998_dev *max8998)
{
if (max8998->irq && max8998->irq_domain)
max8998_irq_thread(max8998->irq, max8998);
return 0;
}
static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
struct max8997_dev *max8998 = d->host_data;
irq_set_chip_data(irq, max8998);
irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
irq_set_nested_thread(irq, 1);
irq_set_noprobe(irq);
return 0;
}
static const struct irq_domain_ops max8998_irq_domain_ops = {
.map = max8998_irq_domain_map,
};
int max8998_irq_init(struct max8998_dev *max8998)
{
int i;
int ret;
struct irq_domain *domain;
if (!max8998->irq) {
dev_warn(max8998->dev,
"No interrupt specified, no interrupts\n");
return 0;
}
mutex_init(&max8998->irqlock);
/* Mask the individual interrupt sources */
for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
max8998->irq_masks_cur[i] = 0xff;
max8998->irq_masks_cache[i] = 0xff;
max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
}
max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
domain = irq_domain_add_simple(NULL, MAX8998_IRQ_NR,
max8998->irq_base, &max8998_irq_domain_ops, max8998);
if (!domain) {
dev_err(max8998->dev, "could not create irq domain\n");
return -ENODEV;
}
max8998->irq_domain = domain;
ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"max8998-irq", max8998);
if (ret) {
dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
max8998->irq, ret);
return ret;
}
if (!max8998->ono)
return 0;
ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
IRQF_ONESHOT, "max8998-ono", max8998);
if (ret)
dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
max8998->ono, ret);
return 0;
}
void max8998_irq_exit(struct max8998_dev *max8998)
{
if (max8998->ono)
free_irq(max8998->ono, max8998);
if (max8998->irq)
free_irq(max8998->irq, max8998);
}
| linux-master | drivers/mfd/max8998-irq.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 MediaTek Inc.
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/mfd/mt6357/core.h>
#include <linux/mfd/mt6357/registers.h>
#include <linux/mfd/mt6358/core.h>
#include <linux/mfd/mt6358/registers.h>
#include <linux/mfd/mt6359/core.h>
#include <linux/mfd/mt6359/registers.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define MTK_PMIC_REG_WIDTH 16
static const struct irq_top_t mt6357_ints[] = {
MT6357_TOP_GEN(BUCK),
MT6357_TOP_GEN(LDO),
MT6357_TOP_GEN(PSC),
MT6357_TOP_GEN(SCK),
MT6357_TOP_GEN(BM),
MT6357_TOP_GEN(HK),
MT6357_TOP_GEN(AUD),
MT6357_TOP_GEN(MISC),
};
static const struct irq_top_t mt6358_ints[] = {
MT6358_TOP_GEN(BUCK),
MT6358_TOP_GEN(LDO),
MT6358_TOP_GEN(PSC),
MT6358_TOP_GEN(SCK),
MT6358_TOP_GEN(BM),
MT6358_TOP_GEN(HK),
MT6358_TOP_GEN(AUD),
MT6358_TOP_GEN(MISC),
};
static const struct irq_top_t mt6359_ints[] = {
MT6359_TOP_GEN(BUCK),
MT6359_TOP_GEN(LDO),
MT6359_TOP_GEN(PSC),
MT6359_TOP_GEN(SCK),
MT6359_TOP_GEN(BM),
MT6359_TOP_GEN(HK),
MT6359_TOP_GEN(AUD),
MT6359_TOP_GEN(MISC),
};
static struct pmic_irq_data mt6357_irqd = {
.num_top = ARRAY_SIZE(mt6357_ints),
.num_pmic_irqs = MT6357_IRQ_NR,
.top_int_status_reg = MT6357_TOP_INT_STATUS0,
.pmic_ints = mt6357_ints,
};
static struct pmic_irq_data mt6358_irqd = {
.num_top = ARRAY_SIZE(mt6358_ints),
.num_pmic_irqs = MT6358_IRQ_NR,
.top_int_status_reg = MT6358_TOP_INT_STATUS0,
.pmic_ints = mt6358_ints,
};
static struct pmic_irq_data mt6359_irqd = {
.num_top = ARRAY_SIZE(mt6359_ints),
.num_pmic_irqs = MT6359_IRQ_NR,
.top_int_status_reg = MT6359_TOP_INT_STATUS0,
.pmic_ints = mt6359_ints,
};
static void pmic_irq_enable(struct irq_data *data)
{
unsigned int hwirq = irqd_to_hwirq(data);
struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
struct pmic_irq_data *irqd = chip->irq_data;
irqd->enable_hwirq[hwirq] = true;
}
static void pmic_irq_disable(struct irq_data *data)
{
unsigned int hwirq = irqd_to_hwirq(data);
struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
struct pmic_irq_data *irqd = chip->irq_data;
irqd->enable_hwirq[hwirq] = false;
}
static void pmic_irq_lock(struct irq_data *data)
{
struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
mutex_lock(&chip->irqlock);
}
static void pmic_irq_sync_unlock(struct irq_data *data)
{
unsigned int i, top_gp, gp_offset, en_reg, int_regs, shift;
struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
struct pmic_irq_data *irqd = chip->irq_data;
for (i = 0; i < irqd->num_pmic_irqs; i++) {
if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i])
continue;
/* Find out the IRQ group */
top_gp = 0;
while ((top_gp + 1) < irqd->num_top &&
i >= irqd->pmic_ints[top_gp + 1].hwirq_base)
top_gp++;
/* Find the IRQ registers */
gp_offset = i - irqd->pmic_ints[top_gp].hwirq_base;
int_regs = gp_offset / MTK_PMIC_REG_WIDTH;
shift = gp_offset % MTK_PMIC_REG_WIDTH;
en_reg = irqd->pmic_ints[top_gp].en_reg +
(irqd->pmic_ints[top_gp].en_reg_shift * int_regs);
regmap_update_bits(chip->regmap, en_reg, BIT(shift),
irqd->enable_hwirq[i] << shift);
irqd->cache_hwirq[i] = irqd->enable_hwirq[i];
}
mutex_unlock(&chip->irqlock);
}
static struct irq_chip mt6358_irq_chip = {
.name = "mt6358-irq",
.flags = IRQCHIP_SKIP_SET_WAKE,
.irq_enable = pmic_irq_enable,
.irq_disable = pmic_irq_disable,
.irq_bus_lock = pmic_irq_lock,
.irq_bus_sync_unlock = pmic_irq_sync_unlock,
};
static void mt6358_irq_sp_handler(struct mt6397_chip *chip,
unsigned int top_gp)
{
unsigned int irq_status, sta_reg, status;
unsigned int hwirq, virq;
int i, j, ret;
struct pmic_irq_data *irqd = chip->irq_data;
for (i = 0; i < irqd->pmic_ints[top_gp].num_int_regs; i++) {
sta_reg = irqd->pmic_ints[top_gp].sta_reg +
irqd->pmic_ints[top_gp].sta_reg_shift * i;
ret = regmap_read(chip->regmap, sta_reg, &irq_status);
if (ret) {
dev_err(chip->dev,
"Failed to read IRQ status, ret=%d\n", ret);
return;
}
if (!irq_status)
continue;
status = irq_status;
do {
j = __ffs(status);
hwirq = irqd->pmic_ints[top_gp].hwirq_base +
MTK_PMIC_REG_WIDTH * i + j;
virq = irq_find_mapping(chip->irq_domain, hwirq);
if (virq)
handle_nested_irq(virq);
status &= ~BIT(j);
} while (status);
regmap_write(chip->regmap, sta_reg, irq_status);
}
}
static irqreturn_t mt6358_irq_handler(int irq, void *data)
{
struct mt6397_chip *chip = data;
struct pmic_irq_data *irqd = chip->irq_data;
unsigned int bit, i, top_irq_status = 0;
int ret;
ret = regmap_read(chip->regmap,
irqd->top_int_status_reg,
&top_irq_status);
if (ret) {
dev_err(chip->dev,
"Failed to read status from the device, ret=%d\n", ret);
return IRQ_NONE;
}
for (i = 0; i < irqd->num_top; i++) {
bit = BIT(irqd->pmic_ints[i].top_offset);
if (top_irq_status & bit) {
mt6358_irq_sp_handler(chip, i);
top_irq_status &= ~bit;
if (!top_irq_status)
break;
}
}
return IRQ_HANDLED;
}
static int pmic_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
struct mt6397_chip *mt6397 = d->host_data;
irq_set_chip_data(irq, mt6397);
irq_set_chip_and_handler(irq, &mt6358_irq_chip, handle_level_irq);
irq_set_nested_thread(irq, 1);
irq_set_noprobe(irq);
return 0;
}
static const struct irq_domain_ops mt6358_irq_domain_ops = {
.map = pmic_irq_domain_map,
.xlate = irq_domain_xlate_twocell,
};
int mt6358_irq_init(struct mt6397_chip *chip)
{
int i, j, ret;
struct pmic_irq_data *irqd;
switch (chip->chip_id) {
case MT6357_CHIP_ID:
chip->irq_data = &mt6357_irqd;
break;
case MT6358_CHIP_ID:
case MT6366_CHIP_ID:
chip->irq_data = &mt6358_irqd;
break;
case MT6359_CHIP_ID:
chip->irq_data = &mt6359_irqd;
break;
default:
dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
return -ENODEV;
}
mutex_init(&chip->irqlock);
irqd = chip->irq_data;
irqd->enable_hwirq = devm_kcalloc(chip->dev,
irqd->num_pmic_irqs,
sizeof(*irqd->enable_hwirq),
GFP_KERNEL);
if (!irqd->enable_hwirq)
return -ENOMEM;
irqd->cache_hwirq = devm_kcalloc(chip->dev,
irqd->num_pmic_irqs,
sizeof(*irqd->cache_hwirq),
GFP_KERNEL);
if (!irqd->cache_hwirq)
return -ENOMEM;
/* Disable all interrupts for initializing */
for (i = 0; i < irqd->num_top; i++) {
for (j = 0; j < irqd->pmic_ints[i].num_int_regs; j++)
regmap_write(chip->regmap,
irqd->pmic_ints[i].en_reg +
irqd->pmic_ints[i].en_reg_shift * j, 0);
}
chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
irqd->num_pmic_irqs,
&mt6358_irq_domain_ops, chip);
if (!chip->irq_domain) {
dev_err(chip->dev, "Could not create IRQ domain\n");
return -ENODEV;
}
ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
mt6358_irq_handler, IRQF_ONESHOT,
mt6358_irq_chip.name, chip);
if (ret) {
dev_err(chip->dev, "Failed to register IRQ=%d, ret=%d\n",
chip->irq, ret);
return ret;
}
enable_irq_wake(chip->irq);
return ret;
}
| linux-master | drivers/mfd/mt6358-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* I2C access driver for TI TPS65912x PMICs
*
* Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <[email protected]>
*
* Based on the TPS65218 driver and the previous TPS65912 driver by
* Margarita Olaya Cabrera <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/mfd/tps65912.h>
static const struct of_device_id tps65912_i2c_of_match_table[] = {
{ .compatible = "ti,tps65912", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tps65912_i2c_of_match_table);
static int tps65912_i2c_probe(struct i2c_client *client)
{
struct tps65912 *tps;
tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
i2c_set_clientdata(client, tps);
tps->dev = &client->dev;
tps->irq = client->irq;
tps->regmap = devm_regmap_init_i2c(client, &tps65912_regmap_config);
if (IS_ERR(tps->regmap)) {
dev_err(tps->dev, "Failed to initialize register map\n");
return PTR_ERR(tps->regmap);
}
return tps65912_device_init(tps);
}
static void tps65912_i2c_remove(struct i2c_client *client)
{
struct tps65912 *tps = i2c_get_clientdata(client);
tps65912_device_exit(tps);
}
static const struct i2c_device_id tps65912_i2c_id_table[] = {
{ "tps65912", 0 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, tps65912_i2c_id_table);
static struct i2c_driver tps65912_i2c_driver = {
.driver = {
.name = "tps65912",
.of_match_table = tps65912_i2c_of_match_table,
},
.probe = tps65912_i2c_probe,
.remove = tps65912_i2c_remove,
.id_table = tps65912_i2c_id_table,
};
module_i2c_driver(tps65912_i2c_driver);
MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
MODULE_DESCRIPTION("TPS65912x I2C Interface Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/tps65912-i2c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* CS42L43 I2C driver
*
* Copyright (C) 2022-2023 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*/
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/mfd/cs42l43-regs.h>
#include <linux/module.h>
#include "cs42l43.h"
static const struct regmap_config cs42l43_i2c_regmap = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS42L43_MCU_RAM_MAX,
.readable_reg = cs42l43_readable_register,
.volatile_reg = cs42l43_volatile_register,
.precious_reg = cs42l43_precious_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs42l43_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs42l43_reg_default),
};
static int cs42l43_i2c_probe(struct i2c_client *i2c)
{
struct cs42l43 *cs42l43;
int ret;
cs42l43 = devm_kzalloc(&i2c->dev, sizeof(*cs42l43), GFP_KERNEL);
if (!cs42l43)
return -ENOMEM;
cs42l43->dev = &i2c->dev;
cs42l43->irq = i2c->irq;
/* A device on an I2C is always attached by definition. */
cs42l43->attached = true;
cs42l43->regmap = devm_regmap_init_i2c(i2c, &cs42l43_i2c_regmap);
if (IS_ERR(cs42l43->regmap)) {
ret = PTR_ERR(cs42l43->regmap);
dev_err(cs42l43->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
return cs42l43_dev_probe(cs42l43);
}
static void cs42l43_i2c_remove(struct i2c_client *i2c)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(&i2c->dev);
cs42l43_dev_remove(cs42l43);
}
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id cs42l43_of_match[] = {
{ .compatible = "cirrus,cs42l43", },
{}
};
MODULE_DEVICE_TABLE(of, cs42l43_of_match);
#endif
#if IS_ENABLED(CONFIG_ACPI)
static const struct acpi_device_id cs42l43_acpi_match[] = {
{ "CSC4243", 0 },
{}
};
MODULE_DEVICE_TABLE(acpi, cs42l43_acpi_match);
#endif
static struct i2c_driver cs42l43_i2c_driver = {
.driver = {
.name = "cs42l43",
.pm = pm_ptr(&cs42l43_pm_ops),
.of_match_table = of_match_ptr(cs42l43_of_match),
.acpi_match_table = ACPI_PTR(cs42l43_acpi_match),
},
.probe = cs42l43_i2c_probe,
.remove = cs42l43_i2c_remove,
};
module_i2c_driver(cs42l43_i2c_driver);
MODULE_IMPORT_NS(MFD_CS42L43);
MODULE_DESCRIPTION("CS42L43 I2C Driver");
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/cs42l43-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ST Microelectronics MFD: stmpe's spi client specific driver
*
* Copyright (C) ST Microelectronics SA 2011
*
* Author: Viresh Kumar <[email protected]> for ST Microelectronics
*/
#include <linux/spi/spi.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/types.h>
#include "stmpe.h"
#define READ_CMD (1 << 7)
static int spi_reg_read(struct stmpe *stmpe, u8 reg)
{
struct spi_device *spi = stmpe->client;
int status = spi_w8r16(spi, reg | READ_CMD);
return (status < 0) ? status : status >> 8;
}
static int spi_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
{
struct spi_device *spi = stmpe->client;
u16 cmd = (val << 8) | reg;
return spi_write(spi, (const u8 *)&cmd, 2);
}
static int spi_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
{
int ret, i;
for (i = 0; i < length; i++) {
ret = spi_reg_read(stmpe, reg + i);
if (ret < 0)
return ret;
*(values + i) = ret;
}
return 0;
}
static int spi_block_write(struct stmpe *stmpe, u8 reg, u8 length,
const u8 *values)
{
int ret = 0, i;
for (i = length; i > 0; i--, reg++) {
ret = spi_reg_write(stmpe, reg, *(values + i - 1));
if (ret < 0)
return ret;
}
return ret;
}
static void spi_init(struct stmpe *stmpe)
{
struct spi_device *spi = stmpe->client;
spi->bits_per_word = 8;
/* This register is only present for stmpe811 */
if (stmpe->variant->id_val == 0x0811)
spi_reg_write(stmpe, STMPE811_REG_SPI_CFG, spi->mode);
if (spi_setup(spi) < 0)
dev_dbg(&spi->dev, "spi_setup failed\n");
}
static struct stmpe_client_info spi_ci = {
.read_byte = spi_reg_read,
.write_byte = spi_reg_write,
.read_block = spi_block_read,
.write_block = spi_block_write,
.init = spi_init,
};
static int
stmpe_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
/* don't exceed max specified rate - 1MHz - Limitation of STMPE */
if (spi->max_speed_hz > 1000000) {
dev_dbg(&spi->dev, "f(sample) %d KHz?\n",
(spi->max_speed_hz/1000));
return -EINVAL;
}
spi_ci.irq = spi->irq;
spi_ci.client = spi;
spi_ci.dev = &spi->dev;
return stmpe_probe(&spi_ci, id->driver_data);
}
static void stmpe_spi_remove(struct spi_device *spi)
{
struct stmpe *stmpe = spi_get_drvdata(spi);
stmpe_remove(stmpe);
}
static const struct of_device_id stmpe_spi_of_match[] = {
{ .compatible = "st,stmpe610", },
{ .compatible = "st,stmpe801", },
{ .compatible = "st,stmpe811", },
{ .compatible = "st,stmpe1601", },
{ .compatible = "st,stmpe2401", },
{ .compatible = "st,stmpe2403", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, stmpe_spi_of_match);
static const struct spi_device_id stmpe_spi_id[] = {
{ "stmpe610", STMPE610 },
{ "stmpe801", STMPE801 },
{ "stmpe811", STMPE811 },
{ "stmpe1601", STMPE1601 },
{ "stmpe2401", STMPE2401 },
{ "stmpe2403", STMPE2403 },
{ }
};
MODULE_DEVICE_TABLE(spi, stmpe_id);
static struct spi_driver stmpe_spi_driver = {
.driver = {
.name = "stmpe-spi",
.of_match_table = of_match_ptr(stmpe_spi_of_match),
.pm = pm_sleep_ptr(&stmpe_dev_pm_ops),
},
.probe = stmpe_spi_probe,
.remove = stmpe_spi_remove,
.id_table = stmpe_spi_id,
};
static int __init stmpe_init(void)
{
return spi_register_driver(&stmpe_spi_driver);
}
subsys_initcall(stmpe_init);
static void __exit stmpe_exit(void)
{
spi_unregister_driver(&stmpe_spi_driver);
}
module_exit(stmpe_exit);
MODULE_DESCRIPTION("STMPE MFD SPI Interface Driver");
MODULE_AUTHOR("Viresh Kumar <[email protected]>");
| linux-master | drivers/mfd/stmpe-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/mfd/ucb1x00-core.c
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
*
* The UCB1x00 core driver provides basic services for handling IO,
* the ADC, interrupts, and accessing registers. It is designed
* such that everything goes through this layer, thereby providing
* a consistent locking methodology, as well as allowing the drivers
* to be used on other non-MCP-enabled hardware platforms.
*
* Note that all locks are private to this file. Nothing else may
* touch them.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/mfd/ucb1x00.h>
#include <linux/pm.h>
#include <linux/gpio/driver.h>
static DEFINE_MUTEX(ucb1x00_mutex);
static LIST_HEAD(ucb1x00_drivers);
static LIST_HEAD(ucb1x00_devices);
/**
* ucb1x00_io_set_dir - set IO direction
* @ucb: UCB1x00 structure describing chip
* @in: bitfield of IO pins to be set as inputs
* @out: bitfield of IO pins to be set as outputs
*
* Set the IO direction of the ten general purpose IO pins on
* the UCB1x00 chip. The @in bitfield has priority over the
* @out bitfield, in that if you specify a pin as both input
* and output, it will end up as an input.
*
* ucb1x00_enable must have been called to enable the comms
* before using this function.
*
* This function takes a spinlock, disabling interrupts.
*/
void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
{
unsigned long flags;
spin_lock_irqsave(&ucb->io_lock, flags);
ucb->io_dir |= out;
ucb->io_dir &= ~in;
ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
spin_unlock_irqrestore(&ucb->io_lock, flags);
}
/**
* ucb1x00_io_write - set or clear IO outputs
* @ucb: UCB1x00 structure describing chip
* @set: bitfield of IO pins to set to logic '1'
* @clear: bitfield of IO pins to set to logic '0'
*
* Set the IO output state of the specified IO pins. The value
* is retained if the pins are subsequently configured as inputs.
* The @clear bitfield has priority over the @set bitfield -
* outputs will be cleared.
*
* ucb1x00_enable must have been called to enable the comms
* before using this function.
*
* This function takes a spinlock, disabling interrupts.
*/
void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
{
unsigned long flags;
spin_lock_irqsave(&ucb->io_lock, flags);
ucb->io_out |= set;
ucb->io_out &= ~clear;
ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
spin_unlock_irqrestore(&ucb->io_lock, flags);
}
/**
* ucb1x00_io_read - read the current state of the IO pins
* @ucb: UCB1x00 structure describing chip
*
* Return a bitfield describing the logic state of the ten
* general purpose IO pins.
*
* ucb1x00_enable must have been called to enable the comms
* before using this function.
*
* This function does not take any mutexes or spinlocks.
*/
unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
{
return ucb1x00_reg_read(ucb, UCB_IO_DATA);
}
static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct ucb1x00 *ucb = gpiochip_get_data(chip);
unsigned long flags;
spin_lock_irqsave(&ucb->io_lock, flags);
if (value)
ucb->io_out |= 1 << offset;
else
ucb->io_out &= ~(1 << offset);
ucb1x00_enable(ucb);
ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
ucb1x00_disable(ucb);
spin_unlock_irqrestore(&ucb->io_lock, flags);
}
static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct ucb1x00 *ucb = gpiochip_get_data(chip);
unsigned val;
ucb1x00_enable(ucb);
val = ucb1x00_reg_read(ucb, UCB_IO_DATA);
ucb1x00_disable(ucb);
return !!(val & (1 << offset));
}
static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct ucb1x00 *ucb = gpiochip_get_data(chip);
unsigned long flags;
spin_lock_irqsave(&ucb->io_lock, flags);
ucb->io_dir &= ~(1 << offset);
ucb1x00_enable(ucb);
ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
ucb1x00_disable(ucb);
spin_unlock_irqrestore(&ucb->io_lock, flags);
return 0;
}
static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset
, int value)
{
struct ucb1x00 *ucb = gpiochip_get_data(chip);
unsigned long flags;
unsigned old, mask = 1 << offset;
spin_lock_irqsave(&ucb->io_lock, flags);
old = ucb->io_out;
if (value)
ucb->io_out |= mask;
else
ucb->io_out &= ~mask;
ucb1x00_enable(ucb);
if (old != ucb->io_out)
ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
if (!(ucb->io_dir & mask)) {
ucb->io_dir |= mask;
ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
}
ucb1x00_disable(ucb);
spin_unlock_irqrestore(&ucb->io_lock, flags);
return 0;
}
static int ucb1x00_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct ucb1x00 *ucb = gpiochip_get_data(chip);
return ucb->irq_base > 0 ? ucb->irq_base + offset : -ENXIO;
}
/*
* UCB1300 data sheet says we must:
* 1. enable ADC => 5us (including reference startup time)
* 2. select input => 51*tsibclk => 4.3us
* 3. start conversion => 102*tsibclk => 8.5us
* (tsibclk = 1/11981000)
* Period between SIB 128-bit frames = 10.7us
*/
/**
* ucb1x00_adc_enable - enable the ADC converter
* @ucb: UCB1x00 structure describing chip
*
* Enable the ucb1x00 and ADC converter on the UCB1x00 for use.
* Any code wishing to use the ADC converter must call this
* function prior to using it.
*
* This function takes the ADC mutex to prevent two or more
* concurrent uses, and therefore may sleep. As a result, it
* can only be called from process context, not interrupt
* context.
*
* You should release the ADC as soon as possible using
* ucb1x00_adc_disable.
*/
void ucb1x00_adc_enable(struct ucb1x00 *ucb)
{
mutex_lock(&ucb->adc_mutex);
ucb->adc_cr |= UCB_ADC_ENA;
ucb1x00_enable(ucb);
ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
}
/**
* ucb1x00_adc_read - read the specified ADC channel
* @ucb: UCB1x00 structure describing chip
* @adc_channel: ADC channel mask
* @sync: wait for syncronisation pulse.
*
* Start an ADC conversion and wait for the result. Note that
* synchronised ADC conversions (via the ADCSYNC pin) must wait
* until the trigger is asserted and the conversion is finished.
*
* This function currently spins waiting for the conversion to
* complete (2 frames max without sync).
*
* If called for a synchronised ADC conversion, it may sleep
* with the ADC mutex held.
*/
unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
{
unsigned int val;
if (sync)
adc_channel |= UCB_ADC_SYNC_ENA;
ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
for (;;) {
val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
if (val & UCB_ADC_DAT_VAL)
break;
/* yield to other processes */
set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(1);
}
return UCB_ADC_DAT(val);
}
/**
* ucb1x00_adc_disable - disable the ADC converter
* @ucb: UCB1x00 structure describing chip
*
* Disable the ADC converter and release the ADC mutex.
*/
void ucb1x00_adc_disable(struct ucb1x00 *ucb)
{
ucb->adc_cr &= ~UCB_ADC_ENA;
ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
ucb1x00_disable(ucb);
mutex_unlock(&ucb->adc_mutex);
}
/*
* UCB1x00 Interrupt handling.
*
* The UCB1x00 can generate interrupts when the SIBCLK is stopped.
* Since we need to read an internal register, we must re-enable
* SIBCLK to talk to the chip. We leave the clock running until
* we have finished processing all interrupts from the chip.
*/
static void ucb1x00_irq(struct irq_desc *desc)
{
struct ucb1x00 *ucb = irq_desc_get_handler_data(desc);
unsigned int isr, i;
ucb1x00_enable(ucb);
isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
for (i = 0; i < 16 && isr; i++, isr >>= 1)
if (isr & 1)
generic_handle_irq(ucb->irq_base + i);
ucb1x00_disable(ucb);
}
static void ucb1x00_irq_update(struct ucb1x00 *ucb, unsigned mask)
{
ucb1x00_enable(ucb);
if (ucb->irq_ris_enbl & mask)
ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
ucb->irq_mask);
if (ucb->irq_fal_enbl & mask)
ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
ucb->irq_mask);
ucb1x00_disable(ucb);
}
static void ucb1x00_irq_noop(struct irq_data *data)
{
}
static void ucb1x00_irq_mask(struct irq_data *data)
{
struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
unsigned mask = 1 << (data->irq - ucb->irq_base);
raw_spin_lock(&ucb->irq_lock);
ucb->irq_mask &= ~mask;
ucb1x00_irq_update(ucb, mask);
raw_spin_unlock(&ucb->irq_lock);
}
static void ucb1x00_irq_unmask(struct irq_data *data)
{
struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
unsigned mask = 1 << (data->irq - ucb->irq_base);
raw_spin_lock(&ucb->irq_lock);
ucb->irq_mask |= mask;
ucb1x00_irq_update(ucb, mask);
raw_spin_unlock(&ucb->irq_lock);
}
static int ucb1x00_irq_set_type(struct irq_data *data, unsigned int type)
{
struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
unsigned mask = 1 << (data->irq - ucb->irq_base);
raw_spin_lock(&ucb->irq_lock);
if (type & IRQ_TYPE_EDGE_RISING)
ucb->irq_ris_enbl |= mask;
else
ucb->irq_ris_enbl &= ~mask;
if (type & IRQ_TYPE_EDGE_FALLING)
ucb->irq_fal_enbl |= mask;
else
ucb->irq_fal_enbl &= ~mask;
if (ucb->irq_mask & mask) {
ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
ucb->irq_mask);
ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
ucb->irq_mask);
}
raw_spin_unlock(&ucb->irq_lock);
return 0;
}
static int ucb1x00_irq_set_wake(struct irq_data *data, unsigned int on)
{
struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
struct ucb1x00_plat_data *pdata = ucb->mcp->attached_device.platform_data;
unsigned mask = 1 << (data->irq - ucb->irq_base);
if (!pdata || !pdata->can_wakeup)
return -EINVAL;
raw_spin_lock(&ucb->irq_lock);
if (on)
ucb->irq_wake |= mask;
else
ucb->irq_wake &= ~mask;
raw_spin_unlock(&ucb->irq_lock);
return 0;
}
static struct irq_chip ucb1x00_irqchip = {
.name = "ucb1x00",
.irq_ack = ucb1x00_irq_noop,
.irq_mask = ucb1x00_irq_mask,
.irq_unmask = ucb1x00_irq_unmask,
.irq_set_type = ucb1x00_irq_set_type,
.irq_set_wake = ucb1x00_irq_set_wake,
};
static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
{
struct ucb1x00_dev *dev;
int ret;
dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dev->ucb = ucb;
dev->drv = drv;
ret = drv->add(dev);
if (ret) {
kfree(dev);
return ret;
}
list_add_tail(&dev->dev_node, &ucb->devs);
list_add_tail(&dev->drv_node, &drv->devs);
return ret;
}
static void ucb1x00_remove_dev(struct ucb1x00_dev *dev)
{
dev->drv->remove(dev);
list_del(&dev->dev_node);
list_del(&dev->drv_node);
kfree(dev);
}
/*
* Try to probe our interrupt, rather than relying on lots of
* hard-coded machine dependencies. For reference, the expected
* IRQ mappings are:
*
* Machine Default IRQ
* adsbitsy IRQ_GPCIN4
* cerf IRQ_GPIO_UCB1200_IRQ
* flexanet IRQ_GPIO_GUI
* freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ
* graphicsclient ADS_EXT_IRQ(8)
* graphicsmaster ADS_EXT_IRQ(8)
* lart LART_IRQ_UCB1200
* omnimeter IRQ_GPIO23
* pfs168 IRQ_GPIO_UCB1300_IRQ
* simpad IRQ_GPIO_UCB1300_IRQ
* shannon SHANNON_IRQ_GPIO_IRQ_CODEC
* yopy IRQ_GPIO_UCB1200_IRQ
*/
static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
{
unsigned long mask;
mask = probe_irq_on();
/*
* Enable the ADC interrupt.
*/
ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
/*
* Cause an ADC interrupt.
*/
ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
/*
* Wait for the conversion to complete.
*/
while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
/*
* Disable and clear interrupt.
*/
ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
/*
* Read triggered interrupt.
*/
return probe_irq_off(mask);
}
static void ucb1x00_release(struct device *dev)
{
struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
kfree(ucb);
}
static struct class ucb1x00_class = {
.name = "ucb1x00",
.dev_release = ucb1x00_release,
};
static int ucb1x00_probe(struct mcp *mcp)
{
struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data;
struct ucb1x00_driver *drv;
struct ucb1x00 *ucb;
unsigned id, i, irq_base;
int ret = -ENODEV;
/* Tell the platform to deassert the UCB1x00 reset */
if (pdata && pdata->reset)
pdata->reset(UCB_RST_PROBE);
mcp_enable(mcp);
id = mcp_reg_read(mcp, UCB_ID);
mcp_disable(mcp);
if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) {
printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id);
goto out;
}
ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL);
ret = -ENOMEM;
if (!ucb)
goto out;
device_initialize(&ucb->dev);
ucb->dev.class = &ucb1x00_class;
ucb->dev.parent = &mcp->attached_device;
dev_set_name(&ucb->dev, "ucb1x00");
raw_spin_lock_init(&ucb->irq_lock);
spin_lock_init(&ucb->io_lock);
mutex_init(&ucb->adc_mutex);
ucb->id = id;
ucb->mcp = mcp;
ret = device_add(&ucb->dev);
if (ret)
goto err_dev_add;
ucb1x00_enable(ucb);
ucb->irq = ucb1x00_detect_irq(ucb);
ucb1x00_disable(ucb);
if (!ucb->irq) {
dev_err(&ucb->dev, "IRQ probe failed\n");
ret = -ENODEV;
goto err_no_irq;
}
ucb->gpio.base = -1;
irq_base = pdata ? pdata->irq_base : 0;
ucb->irq_base = irq_alloc_descs(-1, irq_base, 16, -1);
if (ucb->irq_base < 0) {
dev_err(&ucb->dev, "unable to allocate 16 irqs: %d\n",
ucb->irq_base);
ret = ucb->irq_base;
goto err_irq_alloc;
}
for (i = 0; i < 16; i++) {
unsigned irq = ucb->irq_base + i;
irq_set_chip_and_handler(irq, &ucb1x00_irqchip, handle_edge_irq);
irq_set_chip_data(irq, ucb);
irq_clear_status_flags(irq, IRQ_NOREQUEST);
}
irq_set_irq_type(ucb->irq, IRQ_TYPE_EDGE_RISING);
irq_set_chained_handler_and_data(ucb->irq, ucb1x00_irq, ucb);
if (pdata && pdata->gpio_base) {
ucb->gpio.label = dev_name(&ucb->dev);
ucb->gpio.parent = &ucb->dev;
ucb->gpio.owner = THIS_MODULE;
ucb->gpio.base = pdata->gpio_base;
ucb->gpio.ngpio = 10;
ucb->gpio.set = ucb1x00_gpio_set;
ucb->gpio.get = ucb1x00_gpio_get;
ucb->gpio.direction_input = ucb1x00_gpio_direction_input;
ucb->gpio.direction_output = ucb1x00_gpio_direction_output;
ucb->gpio.to_irq = ucb1x00_to_irq;
ret = gpiochip_add_data(&ucb->gpio, ucb);
if (ret)
goto err_gpio_add;
} else
dev_info(&ucb->dev, "gpio_base not set so no gpiolib support");
mcp_set_drvdata(mcp, ucb);
if (pdata)
device_set_wakeup_capable(&ucb->dev, pdata->can_wakeup);
INIT_LIST_HEAD(&ucb->devs);
mutex_lock(&ucb1x00_mutex);
list_add_tail(&ucb->node, &ucb1x00_devices);
list_for_each_entry(drv, &ucb1x00_drivers, node) {
ucb1x00_add_dev(ucb, drv);
}
mutex_unlock(&ucb1x00_mutex);
return ret;
err_gpio_add:
irq_set_chained_handler(ucb->irq, NULL);
err_irq_alloc:
if (ucb->irq_base > 0)
irq_free_descs(ucb->irq_base, 16);
err_no_irq:
device_del(&ucb->dev);
err_dev_add:
put_device(&ucb->dev);
out:
if (pdata && pdata->reset)
pdata->reset(UCB_RST_PROBE_FAIL);
return ret;
}
static void ucb1x00_remove(struct mcp *mcp)
{
struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data;
struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
struct list_head *l, *n;
mutex_lock(&ucb1x00_mutex);
list_del(&ucb->node);
list_for_each_safe(l, n, &ucb->devs) {
struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node);
ucb1x00_remove_dev(dev);
}
mutex_unlock(&ucb1x00_mutex);
if (ucb->gpio.base != -1)
gpiochip_remove(&ucb->gpio);
irq_set_chained_handler(ucb->irq, NULL);
irq_free_descs(ucb->irq_base, 16);
device_unregister(&ucb->dev);
if (pdata && pdata->reset)
pdata->reset(UCB_RST_REMOVE);
}
int ucb1x00_register_driver(struct ucb1x00_driver *drv)
{
struct ucb1x00 *ucb;
INIT_LIST_HEAD(&drv->devs);
mutex_lock(&ucb1x00_mutex);
list_add_tail(&drv->node, &ucb1x00_drivers);
list_for_each_entry(ucb, &ucb1x00_devices, node) {
ucb1x00_add_dev(ucb, drv);
}
mutex_unlock(&ucb1x00_mutex);
return 0;
}
void ucb1x00_unregister_driver(struct ucb1x00_driver *drv)
{
struct list_head *n, *l;
mutex_lock(&ucb1x00_mutex);
list_del(&drv->node);
list_for_each_safe(l, n, &drv->devs) {
struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node);
ucb1x00_remove_dev(dev);
}
mutex_unlock(&ucb1x00_mutex);
}
static int ucb1x00_suspend(struct device *dev)
{
struct ucb1x00_plat_data *pdata = dev_get_platdata(dev);
struct ucb1x00 *ucb = dev_get_drvdata(dev);
struct ucb1x00_dev *udev;
mutex_lock(&ucb1x00_mutex);
list_for_each_entry(udev, &ucb->devs, dev_node) {
if (udev->drv->suspend)
udev->drv->suspend(udev);
}
mutex_unlock(&ucb1x00_mutex);
if (ucb->irq_wake) {
unsigned long flags;
raw_spin_lock_irqsave(&ucb->irq_lock, flags);
ucb1x00_enable(ucb);
ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
ucb->irq_wake);
ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
ucb->irq_wake);
ucb1x00_disable(ucb);
raw_spin_unlock_irqrestore(&ucb->irq_lock, flags);
enable_irq_wake(ucb->irq);
} else if (pdata && pdata->reset)
pdata->reset(UCB_RST_SUSPEND);
return 0;
}
static int ucb1x00_resume(struct device *dev)
{
struct ucb1x00_plat_data *pdata = dev_get_platdata(dev);
struct ucb1x00 *ucb = dev_get_drvdata(dev);
struct ucb1x00_dev *udev;
if (!ucb->irq_wake && pdata && pdata->reset)
pdata->reset(UCB_RST_RESUME);
ucb1x00_enable(ucb);
ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
if (ucb->irq_wake) {
unsigned long flags;
raw_spin_lock_irqsave(&ucb->irq_lock, flags);
ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
ucb->irq_mask);
ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
ucb->irq_mask);
raw_spin_unlock_irqrestore(&ucb->irq_lock, flags);
disable_irq_wake(ucb->irq);
}
ucb1x00_disable(ucb);
mutex_lock(&ucb1x00_mutex);
list_for_each_entry(udev, &ucb->devs, dev_node) {
if (udev->drv->resume)
udev->drv->resume(udev);
}
mutex_unlock(&ucb1x00_mutex);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(ucb1x00_pm_ops,
ucb1x00_suspend, ucb1x00_resume);
static struct mcp_driver ucb1x00_driver = {
.drv = {
.name = "ucb1x00",
.owner = THIS_MODULE,
.pm = pm_sleep_ptr(&ucb1x00_pm_ops),
},
.probe = ucb1x00_probe,
.remove = ucb1x00_remove,
};
static int __init ucb1x00_init(void)
{
int ret = class_register(&ucb1x00_class);
if (ret == 0) {
ret = mcp_driver_register(&ucb1x00_driver);
if (ret)
class_unregister(&ucb1x00_class);
}
return ret;
}
static void __exit ucb1x00_exit(void)
{
mcp_driver_unregister(&ucb1x00_driver);
class_unregister(&ucb1x00_class);
}
module_init(ucb1x00_init);
module_exit(ucb1x00_exit);
EXPORT_SYMBOL(ucb1x00_io_set_dir);
EXPORT_SYMBOL(ucb1x00_io_write);
EXPORT_SYMBOL(ucb1x00_io_read);
EXPORT_SYMBOL(ucb1x00_adc_enable);
EXPORT_SYMBOL(ucb1x00_adc_read);
EXPORT_SYMBOL(ucb1x00_adc_disable);
EXPORT_SYMBOL(ucb1x00_register_driver);
EXPORT_SYMBOL(ucb1x00_unregister_driver);
MODULE_ALIAS("mcp:ucb1x00");
MODULE_AUTHOR("Russell King <[email protected]>");
MODULE_DESCRIPTION("UCB1x00 core driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/ucb1x00-core.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Core driver for Renesas Synchronization Management Unit (SMU) devices.
*
* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rsmu.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "rsmu.h"
enum {
RSMU_PHC = 0,
RSMU_CDEV = 1,
RSMU_N_DEVS = 2,
};
static struct mfd_cell rsmu_cm_devs[] = {
[RSMU_PHC] = {
.name = "8a3400x-phc",
},
[RSMU_CDEV] = {
.name = "8a3400x-cdev",
},
};
static struct mfd_cell rsmu_sabre_devs[] = {
[RSMU_PHC] = {
.name = "82p33x1x-phc",
},
[RSMU_CDEV] = {
.name = "82p33x1x-cdev",
},
};
static struct mfd_cell rsmu_sl_devs[] = {
[RSMU_PHC] = {
.name = "8v19n85x-phc",
},
[RSMU_CDEV] = {
.name = "8v19n85x-cdev",
},
};
int rsmu_core_init(struct rsmu_ddata *rsmu)
{
struct mfd_cell *cells;
int ret;
switch (rsmu->type) {
case RSMU_CM:
cells = rsmu_cm_devs;
break;
case RSMU_SABRE:
cells = rsmu_sabre_devs;
break;
case RSMU_SL:
cells = rsmu_sl_devs;
break;
default:
dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
return -ENODEV;
}
mutex_init(&rsmu->lock);
ret = devm_mfd_add_devices(rsmu->dev, PLATFORM_DEVID_AUTO, cells,
RSMU_N_DEVS, NULL, 0, NULL);
if (ret < 0)
dev_err(rsmu->dev, "Failed to register sub-devices: %d\n", ret);
return ret;
}
void rsmu_core_exit(struct rsmu_ddata *rsmu)
{
mutex_destroy(&rsmu->lock);
}
MODULE_DESCRIPTION("Renesas SMU core driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/rsmu_core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* I2C driver for Marvell 88PM80x
*
* Copyright (C) 2012 Marvell International Ltd.
* Haojian Zhuang <[email protected]>
* Joseph(Yossi) Hanin <[email protected]>
* Qiao Zhou <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/mfd/88pm80x.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/err.h>
/* 88pm80x chips have same definition for chip id register. */
#define PM80X_CHIP_ID (0x00)
#define PM80X_CHIP_ID_NUM(x) (((x) >> 5) & 0x7)
#define PM80X_CHIP_ID_REVISION(x) ((x) & 0x1F)
struct pm80x_chip_mapping {
unsigned int id;
int type;
};
static struct pm80x_chip_mapping chip_mapping[] = {
/* 88PM800 chip id number */
{0x3, CHIP_PM800},
/* 88PM805 chip id number */
{0x0, CHIP_PM805},
/* 88PM860 chip id number */
{0x4, CHIP_PM860},
};
/*
* workaround: some registers needed by pm805 are defined in pm800, so
* need to use this global variable to maintain the relation between
* pm800 and pm805. would remove it after HW chip fixes the issue.
*/
static struct pm80x_chip *g_pm80x_chip;
const struct regmap_config pm80x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
EXPORT_SYMBOL_GPL(pm80x_regmap_config);
int pm80x_init(struct i2c_client *client)
{
struct pm80x_chip *chip;
struct regmap *map;
unsigned int val;
int i, ret = 0;
chip =
devm_kzalloc(&client->dev, sizeof(struct pm80x_chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
map = devm_regmap_init_i2c(client, &pm80x_regmap_config);
if (IS_ERR(map)) {
ret = PTR_ERR(map);
dev_err(&client->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
chip->client = client;
chip->regmap = map;
chip->irq = client->irq;
chip->dev = &client->dev;
i2c_set_clientdata(chip->client, chip);
ret = regmap_read(chip->regmap, PM80X_CHIP_ID, &val);
if (ret < 0) {
dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(chip_mapping); i++) {
if (chip_mapping[i].id == PM80X_CHIP_ID_NUM(val)) {
chip->type = chip_mapping[i].type;
break;
}
}
if (i == ARRAY_SIZE(chip_mapping)) {
dev_err(chip->dev,
"Failed to detect Marvell 88PM800:ChipID[0x%x]\n", val);
return -EINVAL;
}
device_init_wakeup(&client->dev, 1);
/*
* workaround: set g_pm80x_chip to the first probed chip. if the
* second chip is probed, just point to the companion to each
* other so that pm805 can access those specific register. would
* remove it after HW chip fixes the issue.
*/
if (!g_pm80x_chip)
g_pm80x_chip = chip;
else {
chip->companion = g_pm80x_chip->client;
g_pm80x_chip->companion = chip->client;
}
return 0;
}
EXPORT_SYMBOL_GPL(pm80x_init);
int pm80x_deinit(void)
{
/*
* workaround: clear the dependency between pm800 and pm805.
* would remove it after HW chip fixes the issue.
*/
if (g_pm80x_chip->companion)
g_pm80x_chip->companion = NULL;
else
g_pm80x_chip = NULL;
return 0;
}
EXPORT_SYMBOL_GPL(pm80x_deinit);
static int pm80x_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct pm80x_chip *chip = i2c_get_clientdata(client);
if (chip && chip->wu_flag)
if (device_may_wakeup(chip->dev))
enable_irq_wake(chip->irq);
return 0;
}
static int pm80x_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct pm80x_chip *chip = i2c_get_clientdata(client);
if (chip && chip->wu_flag)
if (device_may_wakeup(chip->dev))
disable_irq_wake(chip->irq);
return 0;
}
EXPORT_GPL_SIMPLE_DEV_PM_OPS(pm80x_pm_ops, pm80x_suspend, pm80x_resume);
MODULE_DESCRIPTION("I2C Driver for Marvell 88PM80x");
MODULE_AUTHOR("Qiao Zhou <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/88pm80x.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2018 BayLibre SAS
// Author: Bartosz Golaszewski <[email protected]>
//
// Core MFD driver for MAXIM 77650/77651 charger/power-supply.
// Programming manual: https://pdfserv.maximintegrated.com/en/an/AN6428.pdf
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max77650.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#define MAX77650_INT_GPI_F_MSK BIT(0)
#define MAX77650_INT_GPI_R_MSK BIT(1)
#define MAX77650_INT_GPI_MSK \
(MAX77650_INT_GPI_F_MSK | MAX77650_INT_GPI_R_MSK)
#define MAX77650_INT_nEN_F_MSK BIT(2)
#define MAX77650_INT_nEN_R_MSK BIT(3)
#define MAX77650_INT_TJAL1_R_MSK BIT(4)
#define MAX77650_INT_TJAL2_R_MSK BIT(5)
#define MAX77650_INT_DOD_R_MSK BIT(6)
#define MAX77650_INT_THM_MSK BIT(0)
#define MAX77650_INT_CHG_MSK BIT(1)
#define MAX77650_INT_CHGIN_MSK BIT(2)
#define MAX77650_INT_TJ_REG_MSK BIT(3)
#define MAX77650_INT_CHGIN_CTRL_MSK BIT(4)
#define MAX77650_INT_SYS_CTRL_MSK BIT(5)
#define MAX77650_INT_SYS_CNFG_MSK BIT(6)
#define MAX77650_INT_GLBL_OFFSET 0
#define MAX77650_INT_CHG_OFFSET 1
#define MAX77650_SBIA_LPM_MASK BIT(5)
#define MAX77650_SBIA_LPM_DISABLED 0x00
enum {
MAX77650_INT_GPI,
MAX77650_INT_nEN_F,
MAX77650_INT_nEN_R,
MAX77650_INT_TJAL1_R,
MAX77650_INT_TJAL2_R,
MAX77650_INT_DOD_R,
MAX77650_INT_THM,
MAX77650_INT_CHG,
MAX77650_INT_CHGIN,
MAX77650_INT_TJ_REG,
MAX77650_INT_CHGIN_CTRL,
MAX77650_INT_SYS_CTRL,
MAX77650_INT_SYS_CNFG,
};
static const struct resource max77650_charger_resources[] = {
DEFINE_RES_IRQ_NAMED(MAX77650_INT_CHG, "CHG"),
DEFINE_RES_IRQ_NAMED(MAX77650_INT_CHGIN, "CHGIN"),
};
static const struct resource max77650_gpio_resources[] = {
DEFINE_RES_IRQ_NAMED(MAX77650_INT_GPI, "GPI"),
};
static const struct resource max77650_onkey_resources[] = {
DEFINE_RES_IRQ_NAMED(MAX77650_INT_nEN_F, "nEN_F"),
DEFINE_RES_IRQ_NAMED(MAX77650_INT_nEN_R, "nEN_R"),
};
static const struct mfd_cell max77650_cells[] = {
{
.name = "max77650-regulator",
.of_compatible = "maxim,max77650-regulator",
}, {
.name = "max77650-charger",
.of_compatible = "maxim,max77650-charger",
.resources = max77650_charger_resources,
.num_resources = ARRAY_SIZE(max77650_charger_resources),
}, {
.name = "max77650-gpio",
.of_compatible = "maxim,max77650-gpio",
.resources = max77650_gpio_resources,
.num_resources = ARRAY_SIZE(max77650_gpio_resources),
}, {
.name = "max77650-led",
.of_compatible = "maxim,max77650-led",
}, {
.name = "max77650-onkey",
.of_compatible = "maxim,max77650-onkey",
.resources = max77650_onkey_resources,
.num_resources = ARRAY_SIZE(max77650_onkey_resources),
},
};
static const struct regmap_irq max77650_irqs[] = {
[MAX77650_INT_GPI] = {
.reg_offset = MAX77650_INT_GLBL_OFFSET,
.mask = MAX77650_INT_GPI_MSK,
.type = {
.type_falling_val = MAX77650_INT_GPI_F_MSK,
.type_rising_val = MAX77650_INT_GPI_R_MSK,
.types_supported = IRQ_TYPE_EDGE_BOTH,
},
},
REGMAP_IRQ_REG(MAX77650_INT_nEN_F,
MAX77650_INT_GLBL_OFFSET, MAX77650_INT_nEN_F_MSK),
REGMAP_IRQ_REG(MAX77650_INT_nEN_R,
MAX77650_INT_GLBL_OFFSET, MAX77650_INT_nEN_R_MSK),
REGMAP_IRQ_REG(MAX77650_INT_TJAL1_R,
MAX77650_INT_GLBL_OFFSET, MAX77650_INT_TJAL1_R_MSK),
REGMAP_IRQ_REG(MAX77650_INT_TJAL2_R,
MAX77650_INT_GLBL_OFFSET, MAX77650_INT_TJAL2_R_MSK),
REGMAP_IRQ_REG(MAX77650_INT_DOD_R,
MAX77650_INT_GLBL_OFFSET, MAX77650_INT_DOD_R_MSK),
REGMAP_IRQ_REG(MAX77650_INT_THM,
MAX77650_INT_CHG_OFFSET, MAX77650_INT_THM_MSK),
REGMAP_IRQ_REG(MAX77650_INT_CHG,
MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHG_MSK),
REGMAP_IRQ_REG(MAX77650_INT_CHGIN,
MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHGIN_MSK),
REGMAP_IRQ_REG(MAX77650_INT_TJ_REG,
MAX77650_INT_CHG_OFFSET, MAX77650_INT_TJ_REG_MSK),
REGMAP_IRQ_REG(MAX77650_INT_CHGIN_CTRL,
MAX77650_INT_CHG_OFFSET, MAX77650_INT_CHGIN_CTRL_MSK),
REGMAP_IRQ_REG(MAX77650_INT_SYS_CTRL,
MAX77650_INT_CHG_OFFSET, MAX77650_INT_SYS_CTRL_MSK),
REGMAP_IRQ_REG(MAX77650_INT_SYS_CNFG,
MAX77650_INT_CHG_OFFSET, MAX77650_INT_SYS_CNFG_MSK),
};
static const struct regmap_irq_chip max77650_irq_chip = {
.name = "max77650-irq",
.irqs = max77650_irqs,
.num_irqs = ARRAY_SIZE(max77650_irqs),
.num_regs = 2,
.status_base = MAX77650_REG_INT_GLBL,
.mask_base = MAX77650_REG_INTM_GLBL,
.type_in_mask = true,
.init_ack_masked = true,
.clear_on_unmask = true,
};
static const struct regmap_config max77650_regmap_config = {
.name = "max77650",
.reg_bits = 8,
.val_bits = 8,
};
static int max77650_i2c_probe(struct i2c_client *i2c)
{
struct regmap_irq_chip_data *irq_data;
struct device *dev = &i2c->dev;
struct irq_domain *domain;
struct regmap *map;
unsigned int val;
int rv, id;
map = devm_regmap_init_i2c(i2c, &max77650_regmap_config);
if (IS_ERR(map)) {
dev_err(dev, "Unable to initialise I2C Regmap\n");
return PTR_ERR(map);
}
rv = regmap_read(map, MAX77650_REG_CID, &val);
if (rv) {
dev_err(dev, "Unable to read Chip ID\n");
return rv;
}
id = MAX77650_CID_BITS(val);
switch (id) {
case MAX77650_CID_77650A:
case MAX77650_CID_77650C:
case MAX77650_CID_77651A:
case MAX77650_CID_77651B:
break;
default:
dev_err(dev, "Chip not supported - ID: 0x%02x\n", id);
return -ENODEV;
}
/*
* This IC has a low-power mode which reduces the quiescent current
* consumption to ~5.6uA but is only suitable for systems consuming
* less than ~2mA. Since this is not likely the case even on
* linux-based wearables - keep the chip in normal power mode.
*/
rv = regmap_update_bits(map,
MAX77650_REG_CNFG_GLBL,
MAX77650_SBIA_LPM_MASK,
MAX77650_SBIA_LPM_DISABLED);
if (rv) {
dev_err(dev, "Unable to change the power mode\n");
return rv;
}
rv = devm_regmap_add_irq_chip(dev, map, i2c->irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77650_irq_chip, &irq_data);
if (rv) {
dev_err(dev, "Unable to add Regmap IRQ chip\n");
return rv;
}
domain = regmap_irq_get_domain(irq_data);
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
max77650_cells, ARRAY_SIZE(max77650_cells),
NULL, 0, domain);
}
static const struct of_device_id max77650_of_match[] = {
{ .compatible = "maxim,max77650" },
{ }
};
MODULE_DEVICE_TABLE(of, max77650_of_match);
static struct i2c_driver max77650_i2c_driver = {
.driver = {
.name = "max77650",
.of_match_table = max77650_of_match,
},
.probe = max77650_i2c_probe,
};
module_i2c_driver(max77650_i2c_driver);
MODULE_DESCRIPTION("MAXIM 77650/77651 multi-function core driver");
MODULE_AUTHOR("Bartosz Golaszewski <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/max77650.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Maxim MAX77714 Core Driver
*
* Copyright (C) 2022 Luca Ceresoli
* Author: Luca Ceresoli <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max77714.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
static const struct mfd_cell max77714_cells[] = {
{ .name = "max77714-watchdog" },
{ .name = "max77714-rtc" },
};
static const struct regmap_range max77714_readable_ranges[] = {
regmap_reg_range(MAX77714_INT_TOP, MAX77714_INT_TOP),
regmap_reg_range(MAX77714_INT_TOPM, MAX77714_INT_TOPM),
regmap_reg_range(MAX77714_32K_STATUS, MAX77714_32K_CONFIG),
regmap_reg_range(MAX77714_CNFG_GLBL2, MAX77714_CNFG2_ONOFF),
};
static const struct regmap_range max77714_writable_ranges[] = {
regmap_reg_range(MAX77714_INT_TOPM, MAX77714_INT_TOPM),
regmap_reg_range(MAX77714_32K_CONFIG, MAX77714_32K_CONFIG),
regmap_reg_range(MAX77714_CNFG_GLBL2, MAX77714_CNFG2_ONOFF),
};
static const struct regmap_access_table max77714_readable_table = {
.yes_ranges = max77714_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(max77714_readable_ranges),
};
static const struct regmap_access_table max77714_writable_table = {
.yes_ranges = max77714_writable_ranges,
.n_yes_ranges = ARRAY_SIZE(max77714_writable_ranges),
};
static const struct regmap_config max77714_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX77714_CNFG2_ONOFF,
.rd_table = &max77714_readable_table,
.wr_table = &max77714_writable_table,
};
static const struct regmap_irq max77714_top_irqs[] = {
REGMAP_IRQ_REG(MAX77714_IRQ_TOP_ONOFF, 0, MAX77714_INT_TOP_ONOFF),
REGMAP_IRQ_REG(MAX77714_IRQ_TOP_RTC, 0, MAX77714_INT_TOP_RTC),
REGMAP_IRQ_REG(MAX77714_IRQ_TOP_GPIO, 0, MAX77714_INT_TOP_GPIO),
REGMAP_IRQ_REG(MAX77714_IRQ_TOP_LDO, 0, MAX77714_INT_TOP_LDO),
REGMAP_IRQ_REG(MAX77714_IRQ_TOP_SD, 0, MAX77714_INT_TOP_SD),
REGMAP_IRQ_REG(MAX77714_IRQ_TOP_GLBL, 0, MAX77714_INT_TOP_GLBL),
};
static const struct regmap_irq_chip max77714_irq_chip = {
.name = "max77714-pmic",
.status_base = MAX77714_INT_TOP,
.mask_base = MAX77714_INT_TOPM,
.num_regs = 1,
.irqs = max77714_top_irqs,
.num_irqs = ARRAY_SIZE(max77714_top_irqs),
};
/*
* MAX77714 initially uses the internal, low precision oscillator. Enable
* the external oscillator by setting the XOSC_RETRY bit. If the external
* oscillator is not OK (probably not installed) this has no effect.
*/
static int max77714_setup_xosc(struct device *dev, struct regmap *regmap)
{
/* Internal Crystal Load Capacitance, indexed by value of 32KLOAD bits */
static const unsigned int load_cap[4] = {0, 10, 12, 22}; /* pF */
unsigned int load_cap_idx;
unsigned int status;
int err;
err = regmap_update_bits(regmap, MAX77714_32K_CONFIG,
MAX77714_32K_CONFIG_XOSC_RETRY,
MAX77714_32K_CONFIG_XOSC_RETRY);
if (err)
return dev_err_probe(dev, err, "Failed to configure the external oscillator\n");
err = regmap_read(regmap, MAX77714_32K_STATUS, &status);
if (err)
return dev_err_probe(dev, err, "Failed to read external oscillator status\n");
load_cap_idx = (status >> MAX77714_32K_STATUS_32KLOAD_SHF)
& MAX77714_32K_STATUS_32KLOAD_MSK;
dev_info(dev, "Using %s oscillator, %d pF load cap\n",
status & MAX77714_32K_STATUS_32KSOURCE ? "internal" : "external",
load_cap[load_cap_idx]);
return 0;
}
static int max77714_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
int err;
regmap = devm_regmap_init_i2c(client, &max77714_regmap_config);
if (IS_ERR(regmap))
return dev_err_probe(dev, PTR_ERR(regmap),
"Failed to initialise regmap\n");
err = max77714_setup_xosc(dev, regmap);
if (err)
return err;
err = devm_regmap_add_irq_chip(dev, regmap, client->irq,
IRQF_ONESHOT | IRQF_SHARED, 0,
&max77714_irq_chip, &irq_data);
if (err)
return dev_err_probe(dev, err, "Failed to add PMIC IRQ chip\n");
err = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
max77714_cells, ARRAY_SIZE(max77714_cells),
NULL, 0, NULL);
if (err)
return dev_err_probe(dev, err, "Failed to register child devices\n");
return 0;
}
static const struct of_device_id max77714_dt_match[] = {
{ .compatible = "maxim,max77714" },
{},
};
MODULE_DEVICE_TABLE(of, max77714_dt_match);
static struct i2c_driver max77714_driver = {
.driver = {
.name = "max77714",
.of_match_table = max77714_dt_match,
},
.probe = max77714_probe,
};
module_i2c_driver(max77714_driver);
MODULE_DESCRIPTION("Maxim MAX77714 MFD core driver");
MODULE_AUTHOR("Luca Ceresoli <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/max77714.c |
// SPDX-License-Identifier: GPL-2.0+
//
// max8998.c - mfd core driver for the Maxim 8998
//
// Copyright (C) 2009-2010 Samsung Electronics
// Kyungmin Park <[email protected]>
// Marek Szyprowski <[email protected]>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pm_runtime.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max8998.h>
#include <linux/mfd/max8998-private.h>
#define RTC_I2C_ADDR (0x0c >> 1)
static const struct mfd_cell max8998_devs[] = {
{
.name = "max8998-pmic",
}, {
.name = "max8998-rtc",
}, {
.name = "max8998-battery",
},
};
static const struct mfd_cell lp3974_devs[] = {
{
.name = "lp3974-pmic",
}, {
.name = "lp3974-rtc",
},
};
int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest)
{
struct max8998_dev *max8998 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8998->iolock);
ret = i2c_smbus_read_byte_data(i2c, reg);
mutex_unlock(&max8998->iolock);
if (ret < 0)
return ret;
ret &= 0xff;
*dest = ret;
return 0;
}
EXPORT_SYMBOL(max8998_read_reg);
int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf)
{
struct max8998_dev *max8998 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8998->iolock);
ret = i2c_smbus_read_i2c_block_data(i2c, reg, count, buf);
mutex_unlock(&max8998->iolock);
if (ret < 0)
return ret;
return 0;
}
EXPORT_SYMBOL(max8998_bulk_read);
int max8998_write_reg(struct i2c_client *i2c, u8 reg, u8 value)
{
struct max8998_dev *max8998 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8998->iolock);
ret = i2c_smbus_write_byte_data(i2c, reg, value);
mutex_unlock(&max8998->iolock);
return ret;
}
EXPORT_SYMBOL(max8998_write_reg);
int max8998_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf)
{
struct max8998_dev *max8998 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8998->iolock);
ret = i2c_smbus_write_i2c_block_data(i2c, reg, count, buf);
mutex_unlock(&max8998->iolock);
if (ret < 0)
return ret;
return 0;
}
EXPORT_SYMBOL(max8998_bulk_write);
int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask)
{
struct max8998_dev *max8998 = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&max8998->iolock);
ret = i2c_smbus_read_byte_data(i2c, reg);
if (ret >= 0) {
u8 old_val = ret & 0xff;
u8 new_val = (val & mask) | (old_val & (~mask));
ret = i2c_smbus_write_byte_data(i2c, reg, new_val);
}
mutex_unlock(&max8998->iolock);
return ret;
}
EXPORT_SYMBOL(max8998_update_reg);
#ifdef CONFIG_OF
static const struct of_device_id max8998_dt_match[] = {
{ .compatible = "maxim,max8998", .data = (void *)TYPE_MAX8998 },
{ .compatible = "national,lp3974", .data = (void *)TYPE_LP3974 },
{ .compatible = "ti,lp3974", .data = (void *)TYPE_LP3974 },
{},
};
#endif
/*
* Only the common platform data elements for max8998 are parsed here from the
* device tree. Other sub-modules of max8998 such as pmic, rtc and others have
* to parse their own platform data elements from device tree.
*
* The max8998 platform data structure is instantiated here and the drivers for
* the sub-modules need not instantiate another instance while parsing their
* platform data.
*/
static struct max8998_platform_data *max8998_i2c_parse_dt_pdata(
struct device *dev)
{
struct max8998_platform_data *pd;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return ERR_PTR(-ENOMEM);
pd->ono = irq_of_parse_and_map(dev->of_node, 1);
/*
* ToDo: the 'wakeup' member in the platform data is more of a linux
* specfic information. Hence, there is no binding for that yet and
* not parsed here.
*/
return pd;
}
static inline unsigned long max8998_i2c_get_driver_data(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
if (i2c->dev.of_node)
return (unsigned long)of_device_get_match_data(&i2c->dev);
return id->driver_data;
}
static int max8998_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct max8998_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct max8998_dev *max8998;
int ret = 0;
max8998 = devm_kzalloc(&i2c->dev, sizeof(struct max8998_dev),
GFP_KERNEL);
if (max8998 == NULL)
return -ENOMEM;
if (IS_ENABLED(CONFIG_OF) && i2c->dev.of_node) {
pdata = max8998_i2c_parse_dt_pdata(&i2c->dev);
if (IS_ERR(pdata))
return PTR_ERR(pdata);
}
i2c_set_clientdata(i2c, max8998);
max8998->dev = &i2c->dev;
max8998->i2c = i2c;
max8998->irq = i2c->irq;
max8998->type = max8998_i2c_get_driver_data(i2c, id);
max8998->pdata = pdata;
if (pdata) {
max8998->ono = pdata->ono;
max8998->irq_base = pdata->irq_base;
max8998->wakeup = pdata->wakeup;
}
mutex_init(&max8998->iolock);
max8998->rtc = i2c_new_dummy_device(i2c->adapter, RTC_I2C_ADDR);
if (IS_ERR(max8998->rtc)) {
dev_err(&i2c->dev, "Failed to allocate I2C device for RTC\n");
return PTR_ERR(max8998->rtc);
}
i2c_set_clientdata(max8998->rtc, max8998);
max8998_irq_init(max8998);
pm_runtime_set_active(max8998->dev);
switch (max8998->type) {
case TYPE_LP3974:
ret = mfd_add_devices(max8998->dev, -1,
lp3974_devs, ARRAY_SIZE(lp3974_devs),
NULL, 0, NULL);
break;
case TYPE_MAX8998:
ret = mfd_add_devices(max8998->dev, -1,
max8998_devs, ARRAY_SIZE(max8998_devs),
NULL, 0, NULL);
break;
default:
ret = -EINVAL;
}
if (ret < 0)
goto err;
device_init_wakeup(max8998->dev, max8998->wakeup);
return ret;
err:
mfd_remove_devices(max8998->dev);
max8998_irq_exit(max8998);
i2c_unregister_device(max8998->rtc);
return ret;
}
static const struct i2c_device_id max8998_i2c_id[] = {
{ "max8998", TYPE_MAX8998 },
{ "lp3974", TYPE_LP3974},
{ }
};
static int max8998_suspend(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max8998_dev *max8998 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
irq_set_irq_wake(max8998->irq, 1);
return 0;
}
static int max8998_resume(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max8998_dev *max8998 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
irq_set_irq_wake(max8998->irq, 0);
/*
* In LP3974, if IRQ registers are not "read & clear"
* when it's set during sleep, the interrupt becomes
* disabled.
*/
return max8998_irq_resume(i2c_get_clientdata(i2c));
}
struct max8998_reg_dump {
u8 addr;
u8 val;
};
#define SAVE_ITEM(x) { .addr = (x), .val = 0x0, }
static struct max8998_reg_dump max8998_dump[] = {
SAVE_ITEM(MAX8998_REG_IRQM1),
SAVE_ITEM(MAX8998_REG_IRQM2),
SAVE_ITEM(MAX8998_REG_IRQM3),
SAVE_ITEM(MAX8998_REG_IRQM4),
SAVE_ITEM(MAX8998_REG_STATUSM1),
SAVE_ITEM(MAX8998_REG_STATUSM2),
SAVE_ITEM(MAX8998_REG_CHGR1),
SAVE_ITEM(MAX8998_REG_CHGR2),
SAVE_ITEM(MAX8998_REG_LDO_ACTIVE_DISCHARGE1),
SAVE_ITEM(MAX8998_REG_LDO_ACTIVE_DISCHARGE1),
SAVE_ITEM(MAX8998_REG_BUCK_ACTIVE_DISCHARGE3),
SAVE_ITEM(MAX8998_REG_ONOFF1),
SAVE_ITEM(MAX8998_REG_ONOFF2),
SAVE_ITEM(MAX8998_REG_ONOFF3),
SAVE_ITEM(MAX8998_REG_ONOFF4),
SAVE_ITEM(MAX8998_REG_BUCK1_VOLTAGE1),
SAVE_ITEM(MAX8998_REG_BUCK1_VOLTAGE2),
SAVE_ITEM(MAX8998_REG_BUCK1_VOLTAGE3),
SAVE_ITEM(MAX8998_REG_BUCK1_VOLTAGE4),
SAVE_ITEM(MAX8998_REG_BUCK2_VOLTAGE1),
SAVE_ITEM(MAX8998_REG_BUCK2_VOLTAGE2),
SAVE_ITEM(MAX8998_REG_LDO2_LDO3),
SAVE_ITEM(MAX8998_REG_LDO4),
SAVE_ITEM(MAX8998_REG_LDO5),
SAVE_ITEM(MAX8998_REG_LDO6),
SAVE_ITEM(MAX8998_REG_LDO7),
SAVE_ITEM(MAX8998_REG_LDO8_LDO9),
SAVE_ITEM(MAX8998_REG_LDO10_LDO11),
SAVE_ITEM(MAX8998_REG_LDO12),
SAVE_ITEM(MAX8998_REG_LDO13),
SAVE_ITEM(MAX8998_REG_LDO14),
SAVE_ITEM(MAX8998_REG_LDO15),
SAVE_ITEM(MAX8998_REG_LDO16),
SAVE_ITEM(MAX8998_REG_LDO17),
SAVE_ITEM(MAX8998_REG_BKCHR),
SAVE_ITEM(MAX8998_REG_LBCNFG1),
SAVE_ITEM(MAX8998_REG_LBCNFG2),
};
/* Save registers before hibernation */
static int max8998_freeze(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
int i;
for (i = 0; i < ARRAY_SIZE(max8998_dump); i++)
max8998_read_reg(i2c, max8998_dump[i].addr,
&max8998_dump[i].val);
return 0;
}
/* Restore registers after hibernation */
static int max8998_restore(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
int i;
for (i = 0; i < ARRAY_SIZE(max8998_dump); i++)
max8998_write_reg(i2c, max8998_dump[i].addr,
max8998_dump[i].val);
return 0;
}
static const struct dev_pm_ops max8998_pm = {
.suspend = max8998_suspend,
.resume = max8998_resume,
.freeze = max8998_freeze,
.restore = max8998_restore,
};
static struct i2c_driver max8998_i2c_driver = {
.driver = {
.name = "max8998",
.pm = &max8998_pm,
.suppress_bind_attrs = true,
.of_match_table = of_match_ptr(max8998_dt_match),
},
.probe = max8998_i2c_probe,
.id_table = max8998_i2c_id,
};
static int __init max8998_i2c_init(void)
{
return i2c_add_driver(&max8998_i2c_driver);
}
/* init early so consumer devices can complete system boot */
subsys_initcall(max8998_i2c_init);
| linux-master | drivers/mfd/max8998.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Regmap tables for CS47L85 codec
*
* Copyright (C) 2015-2017 Cirrus Logic
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
static const struct reg_sequence cs47l85_reva_16_patch[] = {
{ 0x80, 0x0003 },
{ 0x213, 0x03E4 },
{ 0x177, 0x0281 },
{ 0x197, 0x0281 },
{ 0x1B7, 0x0281 },
{ 0x4B1, 0x010A },
{ 0x4CF, 0x0933 },
{ 0x36C, 0x011B },
{ 0x4B8, 0x1120 },
{ 0x4A0, 0x3280 },
{ 0x4A1, 0x3200 },
{ 0x4A2, 0x3200 },
{ 0x441, 0xC050 },
{ 0x4A4, 0x000B },
{ 0x4A5, 0x000B },
{ 0x4A6, 0x000B },
{ 0x4E2, 0x1E1D },
{ 0x4E3, 0x1E1D },
{ 0x4E4, 0x1E1D },
{ 0x293, 0x0080 },
{ 0x17D, 0x0303 },
{ 0x19D, 0x0303 },
{ 0x27E, 0x0000 },
{ 0x80, 0x0000 },
{ 0x80, 0x0000 },
{ 0x448, 0x003f },
};
static const struct reg_sequence cs47l85_revc_16_patch[] = {
{ 0x27E, 0x0000 },
{ 0x2C2, 0x0005 },
{ 0x448, 0x003f },
};
static const struct reg_sequence cs47l85_reva_32_patch[] = {
{ 0x3000, 0xC2253632 },
{ 0x3002, 0xC2300001 },
{ 0x3004, 0x8225100E },
{ 0x3006, 0x22251803 },
{ 0x3008, 0x82310B00 },
{ 0x300A, 0xE231023B },
{ 0x300C, 0x02313B01 },
{ 0x300E, 0x62300000 },
{ 0x3010, 0xE2314288 },
{ 0x3012, 0x02310B00 },
{ 0x3014, 0x02310B00 },
{ 0x3016, 0x04050100 },
{ 0x3018, 0x42310C02 },
{ 0x301A, 0xE2310227 },
{ 0x301C, 0x02313B01 },
{ 0x301E, 0xE2314266 },
{ 0x3020, 0xE2315294 },
{ 0x3022, 0x02310B00 },
{ 0x3024, 0x02310B00 },
{ 0x3026, 0x02251100 },
{ 0x3028, 0x02251401 },
{ 0x302A, 0x02250200 },
{ 0x302C, 0x02251001 },
{ 0x302E, 0x02250200 },
{ 0x3030, 0xE2310266 },
{ 0x3032, 0x82314B15 },
{ 0x3034, 0x82310B15 },
{ 0x3036, 0xE2315294 },
{ 0x3038, 0x02310B00 },
{ 0x303A, 0x8225160D },
{ 0x303C, 0x0225F501 },
{ 0x303E, 0x8225061C },
{ 0x3040, 0x02251000 },
{ 0x3042, 0x04051101 },
{ 0x3044, 0x02251800 },
{ 0x3046, 0x42251203 },
{ 0x3048, 0x02251101 },
{ 0x304A, 0xC2251300 },
{ 0x304C, 0x2225FB02 },
{ 0x3050, 0xC2263632 },
{ 0x3052, 0xC2300001 },
{ 0x3054, 0x8226100E },
{ 0x3056, 0x22261803 },
{ 0x3058, 0x82310B02 },
{ 0x305A, 0xE231023B },
{ 0x305C, 0x02313B01 },
{ 0x305E, 0x62300000 },
{ 0x3060, 0xE2314288 },
{ 0x3062, 0x02310B00 },
{ 0x3064, 0x02310B00 },
{ 0x3066, 0x04050000 },
{ 0x3068, 0x42310C03 },
{ 0x306A, 0xE2310227 },
{ 0x306C, 0x02313B01 },
{ 0x306E, 0xE2314266 },
{ 0x3070, 0xE2315294 },
{ 0x3072, 0x02310B00 },
{ 0x3074, 0x02310B00 },
{ 0x3076, 0x02261100 },
{ 0x3078, 0x02261401 },
{ 0x307A, 0x02260200 },
{ 0x307C, 0x02261001 },
{ 0x307E, 0x02260200 },
{ 0x3080, 0xE2310266 },
{ 0x3082, 0x82314B17 },
{ 0x3084, 0x82310B17 },
{ 0x3086, 0xE2315294 },
{ 0x3088, 0x02310B00 },
{ 0x308A, 0x8226160D },
{ 0x308C, 0x0226F501 },
{ 0x308E, 0x8226061C },
{ 0x3090, 0x02261000 },
{ 0x3092, 0x04051101 },
{ 0x3094, 0x02261800 },
{ 0x3096, 0x42261203 },
{ 0x3098, 0x02261101 },
{ 0x309A, 0xC2261300 },
{ 0x309C, 0x2226FB02 },
{ 0x309E, 0x0000F000 },
{ 0x30A0, 0xC2273632 },
{ 0x30A2, 0xC2400001 },
{ 0x30A4, 0x8227100E },
{ 0x30A6, 0x22271803 },
{ 0x30A8, 0x82410B00 },
{ 0x30AA, 0xE241023B },
{ 0x30AC, 0x02413B01 },
{ 0x30AE, 0x62400000 },
{ 0x30B0, 0xE2414288 },
{ 0x30B2, 0x02410B00 },
{ 0x30B4, 0x02410B00 },
{ 0x30B6, 0x04050300 },
{ 0x30B8, 0x42410C02 },
{ 0x30BA, 0xE2410227 },
{ 0x30BC, 0x02413B01 },
{ 0x30BE, 0xE2414266 },
{ 0x30C0, 0xE2415294 },
{ 0x30C2, 0x02410B00 },
{ 0x30C4, 0x02410B00 },
{ 0x30C6, 0x02271100 },
{ 0x30C8, 0x02271401 },
{ 0x30CA, 0x02270200 },
{ 0x30CC, 0x02271001 },
{ 0x30CE, 0x02270200 },
{ 0x30D0, 0xE2410266 },
{ 0x30D2, 0x82414B15 },
{ 0x30D4, 0x82410B15 },
{ 0x30D6, 0xE2415294 },
{ 0x30D8, 0x02410B00 },
{ 0x30DA, 0x8227160D },
{ 0x30DC, 0x0227F501 },
{ 0x30DE, 0x8227061C },
{ 0x30E0, 0x02271000 },
{ 0x30E2, 0x04051101 },
{ 0x30E4, 0x02271800 },
{ 0x30E6, 0x42271203 },
{ 0x30E8, 0x02271101 },
{ 0x30EA, 0xC2271300 },
{ 0x30EC, 0x2227FB02 },
{ 0x30F0, 0xC2283632 },
{ 0x30F2, 0xC2400001 },
{ 0x30F4, 0x8228100E },
{ 0x30F6, 0x22281803 },
{ 0x30F8, 0x82410B02 },
{ 0x30FA, 0xE241023B },
{ 0x30FC, 0x02413B01 },
{ 0x30FE, 0x62400000 },
{ 0x3100, 0xE2414288 },
{ 0x3102, 0x02410B00 },
{ 0x3104, 0x02410B00 },
{ 0x3106, 0x04050200 },
{ 0x3108, 0x42410C03 },
{ 0x310A, 0xE2410227 },
{ 0x310C, 0x02413B01 },
{ 0x310E, 0xE2414266 },
{ 0x3110, 0xE2415294 },
{ 0x3112, 0x02410B00 },
{ 0x3114, 0x02410B00 },
{ 0x3116, 0x02281100 },
{ 0x3118, 0x02281401 },
{ 0x311A, 0x02280200 },
{ 0x311C, 0x02281001 },
{ 0x311E, 0x02280200 },
{ 0x3120, 0xE2410266 },
{ 0x3122, 0x82414B17 },
{ 0x3124, 0x82410B17 },
{ 0x3126, 0xE2415294 },
{ 0x3128, 0x02410B00 },
{ 0x312A, 0x8228160D },
{ 0x312C, 0x0228F501 },
{ 0x312E, 0x8228061C },
{ 0x3130, 0x02281000 },
{ 0x3132, 0x04051101 },
{ 0x3134, 0x02281800 },
{ 0x3136, 0x42281203 },
{ 0x3138, 0x02281101 },
{ 0x313A, 0xC2281300 },
{ 0x313C, 0x2228FB02 },
{ 0x3140, 0xC2293632 },
{ 0x3142, 0xC2500001 },
{ 0x3144, 0x8229100E },
{ 0x3146, 0x22291803 },
{ 0x3148, 0x82510B00 },
{ 0x314A, 0xE251023B },
{ 0x314C, 0x02513B01 },
{ 0x314E, 0x62500000 },
{ 0x3150, 0xE2514288 },
{ 0x3152, 0x02510B00 },
{ 0x3154, 0x02510B00 },
{ 0x3156, 0x04050500 },
{ 0x3158, 0x42510C02 },
{ 0x315A, 0xE2510227 },
{ 0x315C, 0x02513B01 },
{ 0x315E, 0xE2514266 },
{ 0x3160, 0xE2515294 },
{ 0x3162, 0x02510B00 },
{ 0x3164, 0x02510B00 },
{ 0x3166, 0x02291100 },
{ 0x3168, 0x02291401 },
{ 0x316A, 0x02290200 },
{ 0x316C, 0x02291001 },
{ 0x316E, 0x02290200 },
{ 0x3170, 0xE2510266 },
{ 0x3172, 0x82514B15 },
{ 0x3174, 0x82510B15 },
{ 0x3176, 0xE2515294 },
{ 0x3178, 0x02510B00 },
{ 0x317A, 0x8229160D },
{ 0x317C, 0x0229F501 },
{ 0x317E, 0x8229061C },
{ 0x3180, 0x02291000 },
{ 0x3182, 0x04051101 },
{ 0x3184, 0x02291800 },
{ 0x3186, 0x42291203 },
{ 0x3188, 0x02291101 },
{ 0x318A, 0xC2291300 },
{ 0x318C, 0x2229FB02 },
{ 0x3190, 0xC22A3632 },
{ 0x3192, 0xC2500001 },
{ 0x3194, 0x822A100E },
{ 0x3196, 0x222A1803 },
{ 0x3198, 0x82510B02 },
{ 0x319A, 0xE251023B },
{ 0x319C, 0x02513B01 },
{ 0x319E, 0x62500000 },
{ 0x31A0, 0xE2514288 },
{ 0x31A2, 0x02510B00 },
{ 0x31A4, 0x02510B00 },
{ 0x31A6, 0x04050400 },
{ 0x31A8, 0x42510C03 },
{ 0x31AA, 0xE2510227 },
{ 0x31AC, 0x02513B01 },
{ 0x31AE, 0xE2514266 },
{ 0x31B0, 0xE2515294 },
{ 0x31B2, 0x02510B00 },
{ 0x31B4, 0x02510B00 },
{ 0x31B6, 0x022A1100 },
{ 0x31B8, 0x022A1401 },
{ 0x31BA, 0x022A0200 },
{ 0x31BC, 0x022A1001 },
{ 0x31BE, 0x022A0200 },
{ 0x31C0, 0xE2510266 },
{ 0x31C2, 0x82514B17 },
{ 0x31C4, 0x82510B17 },
{ 0x31C6, 0xE2515294 },
{ 0x31C8, 0x02510B00 },
{ 0x31CA, 0x822A160D },
{ 0x31CC, 0x022AF501 },
{ 0x31CE, 0x822A061C },
{ 0x31D0, 0x022A1000 },
{ 0x31D2, 0x04051101 },
{ 0x31D4, 0x022A1800 },
{ 0x31D6, 0x422A1203 },
{ 0x31D8, 0x022A1101 },
{ 0x31DA, 0xC22A1300 },
{ 0x31DC, 0x222AFB02 },
};
static const struct reg_sequence cs47l85_revc_32_patch[] = {
{ 0x3380, 0xE4103066 },
{ 0x3382, 0xE4103070 },
{ 0x3384, 0xE4103078 },
{ 0x3386, 0xE4103080 },
{ 0x3388, 0xE410F080 },
{ 0x338A, 0xE4143066 },
{ 0x338C, 0xE4143070 },
{ 0x338E, 0xE4143078 },
{ 0x3390, 0xE4143080 },
{ 0x3392, 0xE414F080 },
{ 0x3394, 0xE4103078 },
{ 0x3396, 0xE4103070 },
{ 0x3398, 0xE4103066 },
{ 0x339A, 0xE410F056 },
{ 0x339C, 0xE4143078 },
{ 0x339E, 0xE4143070 },
{ 0x33A0, 0xE4143066 },
{ 0x33A2, 0xE414F056 },
};
int cs47l85_patch(struct madera *madera)
{
int ret = 0;
const struct reg_sequence *patch16;
const struct reg_sequence *patch32;
unsigned int num16, num32;
switch (madera->rev) {
case 0:
case 1:
patch16 = cs47l85_reva_16_patch;
num16 = ARRAY_SIZE(cs47l85_reva_16_patch);
patch32 = cs47l85_reva_32_patch;
num32 = ARRAY_SIZE(cs47l85_reva_32_patch);
break;
default:
patch16 = cs47l85_revc_16_patch;
num16 = ARRAY_SIZE(cs47l85_revc_16_patch);
patch32 = cs47l85_revc_32_patch;
num32 = ARRAY_SIZE(cs47l85_revc_32_patch);
break;
}
ret = regmap_register_patch(madera->regmap, patch16, num16);
if (ret < 0) {
dev_err(madera->dev,
"Error in applying 16-bit patch: %d\n", ret);
return ret;
}
ret = regmap_register_patch(madera->regmap_32bit, patch32, num32);
if (ret < 0) {
dev_err(madera->dev,
"Error in applying 32-bit patch: %d\n", ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(cs47l85_patch);
static const struct reg_default cs47l85_reg_default[] = {
{ 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */
{ 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4 */
{ 0x00000066, 0x01ff }, /* R102 (0x66) - Always On Triggers Sequence Select 1*/
{ 0x00000067, 0x01ff }, /* R103 (0x67) - Always On Triggers Sequence Select 2*/
{ 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */
{ 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics phase 1 intensity */
{ 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics phase 1 duration */
{ 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics phase 2 intensity */
{ 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics phase 2 duration */
{ 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics phase 3 intensity */
{ 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics phase 3 duration */
{ 0x000000a0, 0x0000 }, /* R160 (0xa0) - Comfort Noise Generator */
{ 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32k 1 */
{ 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 (0x102) - Sample rate 1 */
{ 0x00000103, 0x0011 }, /* R259 (0x103) - Sample rate 2 */
{ 0x00000104, 0x0011 }, /* R260 (0x104) - Sample rate 3 */
{ 0x00000112, 0x0305 }, /* R274 (0x112) - Async clock 1 */
{ 0x00000113, 0x0011 }, /* R275 (0x113) - Async sample rate 1 */
{ 0x00000114, 0x0011 }, /* R276 (0x114) - Async sample rate 2 */
{ 0x00000120, 0x0305 }, /* R288 (0x120) - DSP Clock 1 */
{ 0x00000122, 0x0000 }, /* R290 (0x122) - DSP Clock 2 */
{ 0x00000149, 0x0000 }, /* R329 (0x149) - Output system clock */
{ 0x0000014a, 0x0000 }, /* R330 (0x14a) - Output async clock */
{ 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */
{ 0x00000171, 0x0002 }, /* R369 (0x171) - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 (0x172) - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 (0x173) - FLL1 Control 3 */
{ 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */
{ 0x00000175, 0x0000 }, /* R373 (0x175) - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */
{ 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */
{ 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0000 }, /* R386 (0x182) - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0000 }, /* R389 (0x185) - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 (0x186) - FLL1 Synchroniser 6 */
{ 0x00000187, 0x0001 }, /* R391 (0x187) - FLL1 Synchroniser 7 */
{ 0x00000189, 0x0000 }, /* R393 (0x189) - FLL1 Spread Spectrum */
{ 0x0000018a, 0x000c }, /* R394 (0x18a) - FLL1 GPIO Clock */
{ 0x00000191, 0x0002 }, /* R401 (0x191) - FLL2 Control 1 */
{ 0x00000192, 0x0008 }, /* R402 (0x192) - FLL2 Control 2 */
{ 0x00000193, 0x0018 }, /* R403 (0x193) - FLL2 Control 3 */
{ 0x00000194, 0x007d }, /* R404 (0x194) - FLL2 Control 4 */
{ 0x00000195, 0x0000 }, /* R405 (0x195) - FLL2 Control 5 */
{ 0x00000196, 0x0000 }, /* R406 (0x196) - FLL2 Control 6 */
{ 0x00000199, 0x0000 }, /* R409 (0x199) - FLL2 Control 7 */
{ 0x000001a1, 0x0000 }, /* R417 (0x1a1) - FLL2 Synchroniser 1 */
{ 0x000001a2, 0x0000 }, /* R418 (0x1a2) - FLL2 Synchroniser 2 */
{ 0x000001a3, 0x0000 }, /* R419 (0x1a3) - FLL2 Synchroniser 3 */
{ 0x000001a4, 0x0000 }, /* R420 (0x1a4) - FLL2 Synchroniser 4 */
{ 0x000001a5, 0x0000 }, /* R421 (0x1a5) - FLL2 Synchroniser 5 */
{ 0x000001a6, 0x0000 }, /* R422 (0x1a6) - FLL2 Synchroniser 6 */
{ 0x000001a7, 0x0001 }, /* R423 (0x1a7) - FLL2 Synchroniser 7 */
{ 0x000001a9, 0x0000 }, /* R425 (0x1a9) - FLL2 Spread Spectrum */
{ 0x000001aa, 0x000c }, /* R426 (0x1aa) - FLL2 GPIO Clock */
{ 0x000001b1, 0x0002 }, /* R433 (0x1b1) - FLL3 Control 1 */
{ 0x000001b2, 0x0008 }, /* R434 (0x1b2) - FLL3 Control 2 */
{ 0x000001b3, 0x0018 }, /* R435 (0x1b3) - FLL3 Control 3 */
{ 0x000001b4, 0x007d }, /* R436 (0x1b4) - FLL3 Control 4 */
{ 0x000001b5, 0x0000 }, /* R437 (0x1b5) - FLL3 Control 5 */
{ 0x000001b6, 0x0000 }, /* R438 (0x1b6) - FLL3 Control 6 */
{ 0x000001b9, 0x0000 }, /* R441 (0x1b9) - FLL3 Control 7 */
{ 0x000001c1, 0x0000 }, /* R449 (0x1c1) - FLL3 Synchroniser 1 */
{ 0x000001c2, 0x0000 }, /* R450 (0x1c2) - FLL3 Synchroniser 2 */
{ 0x000001c3, 0x0000 }, /* R451 (0x1c3) - FLL3 Synchroniser 3 */
{ 0x000001c4, 0x0000 }, /* R452 (0x1c4) - FLL3 Synchroniser 4 */
{ 0x000001c5, 0x0000 }, /* R453 (0x1c5) - FLL3 Synchroniser 5 */
{ 0x000001c6, 0x0000 }, /* R454 (0x1c6) - FLL3 Synchroniser 6 */
{ 0x000001c7, 0x0001 }, /* R455 (0x1c7) - FLL3 Synchroniser 7 */
{ 0x000001c9, 0x0000 }, /* R457 (0x1c9) - FLL3 Spread Spectrum */
{ 0x000001ca, 0x000C }, /* R458 (0x1ca) - FLL3 GPIO Clock */
{ 0x00000200, 0x0006 }, /* R512 (0x200) - Mic Charge Pump 1 */
{ 0x0000020b, 0x0400 }, /* R523 (0x20B) - HP Charge Pump 8 */
{ 0x00000210, 0x0184 }, /* R528 (0x210) - LDO1 Control 1 */
{ 0x00000213, 0x03e4 }, /* R531 (0x213) - LDO2 Control 1 */
{ 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */
{ 0x00000219, 0x00e6 }, /* R537 (0x219) - Mic Bias Ctrl 2 */
{ 0x0000021a, 0x00e6 }, /* R538 (0x21a) - Mic Bias Ctrl 3 */
{ 0x0000021b, 0x00e6 }, /* R539 (0x21b) - Mic Bias Ctrl 4 */
{ 0x0000027e, 0x0000 }, /* R638 (0x27e) - EDRE HP stereo control */
{ 0x00000293, 0x0000 }, /* R659 (0x293) - Accessory Detect Mode 1 */
{ 0x0000029b, 0x0000 }, /* R667 (0x29b) - Headphone Detect 1 */
{ 0x000002a3, 0x1102 }, /* R675 (0x2a3) - Mic Detect Control 1 */
{ 0x000002a4, 0x009f }, /* R676 (0x2a4) - Mic Detect Control 2 */
{ 0x000002a6, 0x3737 }, /* R678 (0x2a6) - Mic Detect Level 1 */
{ 0x000002a7, 0x2c37 }, /* R679 (0x2a7) - Mic Detect Level 2 */
{ 0x000002a8, 0x1422 }, /* R680 (0x2a8) - Mic Detect Level 3 */
{ 0x000002a9, 0x030a }, /* R681 (0x2a9) - Mic Detect Level 4 */
{ 0x000002c6, 0x0010 }, /* R710 (0x2c6) - Mic Clamp control */
{ 0x000002c8, 0x0000 }, /* R712 (0x2c8) - GP switch 1 */
{ 0x000002d3, 0x0000 }, /* R723 (0x2d3) - Jack detect analogue */
{ 0x00000300, 0x0000 }, /* R768 (0x300) - Input Enables */
{ 0x00000308, 0x0000 }, /* R776 (0x308) - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */
{ 0x0000030c, 0x0002 }, /* R780 (0x30c) - HPF Control */
{ 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */
{ 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */
{ 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */
{ 0x00000318, 0x0080 }, /* R792 (0x318) - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */
{ 0x0000031a, 0x0500 }, /* R794 (0x31a) - DMIC2L Control */
{ 0x0000031c, 0x0080 }, /* R796 (0x31c) - IN2R Control */
{ 0x0000031d, 0x0180 }, /* R797 (0x31d) - ADC Digital Volume 2R */
{ 0x0000031e, 0x0000 }, /* R798 (0x31e) - DMIC2R Control */
{ 0x00000320, 0x0080 }, /* R800 (0x320) - IN3L Control */
{ 0x00000321, 0x0180 }, /* R801 (0x321) - ADC Digital Volume 3L */
{ 0x00000322, 0x0500 }, /* R802 (0x322) - DMIC3L Control */
{ 0x00000324, 0x0080 }, /* R804 (0x324) - IN3R Control */
{ 0x00000325, 0x0180 }, /* R805 (0x325) - ADC Digital Volume 3R */
{ 0x00000326, 0x0000 }, /* R806 (0x326) - DMIC3R Control */
{ 0x00000328, 0x0000 }, /* R808 (0x328) - IN4 Control */
{ 0x00000329, 0x0180 }, /* R809 (0x329) - ADC Digital Volume 4L */
{ 0x0000032a, 0x0500 }, /* R810 (0x32a) - DMIC4L Control */
{ 0x0000032c, 0x0000 }, /* R812 (0x32c) - IN4R Control */
{ 0x0000032d, 0x0180 }, /* R813 (0x32d) - ADC Digital Volume 4R */
{ 0x0000032e, 0x0000 }, /* R814 (0x32e) - DMIC4R Control */
{ 0x00000330, 0x0000 }, /* R816 (0x330) - IN5L Control */
{ 0x00000331, 0x0180 }, /* R817 (0x331) - ADC Digital Volume 5L */
{ 0x00000332, 0x0500 }, /* R818 (0x332) - DMIC5L Control */
{ 0x00000334, 0x0000 }, /* R820 (0x334) - IN5R Control */
{ 0x00000335, 0x0180 }, /* R821 (0x335) - ADC Digital Volume 5R */
{ 0x00000336, 0x0000 }, /* R822 (0x336) - DMIC5R Control */
{ 0x00000338, 0x0000 }, /* R824 (0x338) - IN6L Control */
{ 0x00000339, 0x0180 }, /* R825 (0x339) - ADC Digital Volume 6L */
{ 0x0000033a, 0x0500 }, /* R826 (0x33a) - DMIC6L Control */
{ 0x0000033c, 0x0000 }, /* R828 (0x33c) - IN6R Control */
{ 0x0000033d, 0x0180 }, /* R829 (0x33d) - ADC Digital Volume 6R */
{ 0x0000033e, 0x0000 }, /* R830 (0x33e) - DMIC6R Control */
{ 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 (0x408) - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */
{ 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */
{ 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */
{ 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */
{ 0x00000418, 0x0080 }, /* R1048 (0x418) - Output Path Config 2L */
{ 0x00000419, 0x0180 }, /* R1049 (0x419) - DAC Digital Volume 2L */
{ 0x0000041b, 0x0004 }, /* R1051 (0x41b) - Noise Gate Select 2L */
{ 0x0000041c, 0x0080 }, /* R1052 (0x41c) - Output Path Config 2R */
{ 0x0000041d, 0x0180 }, /* R1053 (0x41d) - DAC Digital Volume 2R */
{ 0x0000041f, 0x0008 }, /* R1055 (0x41f) - Noise Gate Select 2R */
{ 0x00000420, 0x0080 }, /* R1056 (0x420) - Output Path Config 3L */
{ 0x00000421, 0x0180 }, /* R1057 (0x421) - DAC Digital Volume 3L */
{ 0x00000423, 0x0010 }, /* R1059 (0x423) - Noise Gate Select 3L */
{ 0x00000424, 0x0080 }, /* R1060 (0x424) - Output Path Config 3R */
{ 0x00000425, 0x0180 }, /* R1061 (0x425) - DAC Digital Volume 3R */
{ 0x00000427, 0x0020 }, /* R1063 (0x427) - Noise Gate Select 3R */
{ 0x00000428, 0x0000 }, /* R1064 (0x428) - Output Path Config 4L */
{ 0x00000429, 0x0180 }, /* R1065 (0x429) - DAC Digital Volume 4L */
{ 0x0000042b, 0x0040 }, /* R1067 (0x42b) - Noise Gate Select 4L */
{ 0x0000042c, 0x0000 }, /* R1068 (0x42c) - Output Path Config 4R */
{ 0x0000042d, 0x0180 }, /* R1069 (0x42d) - DAC Digital Volume 4R */
{ 0x0000042f, 0x0080 }, /* R1071 (0x42f) - Noise Gate Select 4R */
{ 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */
{ 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */
{ 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */
{ 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */
{ 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */
{ 0x00000438, 0x0000 }, /* R1080 (0x438) - Output Path Config 6L */
{ 0x00000439, 0x0180 }, /* R1081 (0x439) - DAC Digital Volume 6L */
{ 0x0000043b, 0x0400 }, /* R1083 (0x43b) - Noise Gate Select 6L */
{ 0x0000043c, 0x0000 }, /* R1084 (0x43c) - Output Path Config 6R */
{ 0x0000043d, 0x0180 }, /* R1085 (0x43d) - DAC Digital Volume 6R */
{ 0x0000043f, 0x0800 }, /* R1087 (0x43f) - Noise Gate Select 6R */
{ 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */
{ 0x00000451, 0x0000 }, /* R1105 (0x451) - DAC AEC Control 2 */
{ 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 CTRL 1 */
{ 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 CTRL 2 */
{ 0x00000492, 0x0069 }, /* R1170 (0x492) - PDM SPK2 CTRL 1 */
{ 0x00000493, 0x0000 }, /* R1171 (0x493) - PDM SPK2 CTRL 2 */
{ 0x000004a0, 0x3280 }, /* R1184 (0x4a0) - HP1 Short Circuit Ctrl */
{ 0x000004a1, 0x3200 }, /* R1185 (0x4a1) - HP2 Short Circuit Ctrl */
{ 0x000004a2, 0x3200 }, /* R1186 (0x4a2) - HP3 Short Circuit Ctrl */
{ 0x000004a8, 0x7020 }, /* R1192 (0x4a8) - HP Test Ctrl 5 */
{ 0x000004a9, 0x7020 }, /* R1193 (0x4a9) - HP Test Ctrl 6 */
{ 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */
{ 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */
{ 0x0000050a, 0x0001 }, /* R1290 (0x50a) - AIF1 Frame Ctrl 4 */
{ 0x0000050b, 0x0002 }, /* R1291 (0x50b) - AIF1 Frame Ctrl 5 */
{ 0x0000050c, 0x0003 }, /* R1292 (0x50c) - AIF1 Frame Ctrl 6 */
{ 0x0000050d, 0x0004 }, /* R1293 (0x50d) - AIF1 Frame Ctrl 7 */
{ 0x0000050e, 0x0005 }, /* R1294 (0x50e) - AIF1 Frame Ctrl 8 */
{ 0x0000050f, 0x0006 }, /* R1295 (0x50f) - AIF1 Frame Ctrl 9 */
{ 0x00000510, 0x0007 }, /* R1296 (0x510) - AIF1 Frame Ctrl 10 */
{ 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */
{ 0x00000517, 0x0006 }, /* R1303 (0x517) - AIF1 Frame Ctrl 17 */
{ 0x00000518, 0x0007 }, /* R1304 (0x518) - AIF1 Frame Ctrl 18 */
{ 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */
{ 0x0000051a, 0x0000 }, /* R1306 (0x51a) - AIF1 Rx Enables */
{ 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */
{ 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */
{ 0x0000054a, 0x0001 }, /* R1354 (0x54a) - AIF2 Frame Ctrl 4 */
{ 0x0000054b, 0x0002 }, /* R1355 (0x54b) - AIF2 Frame Ctrl 5 */
{ 0x0000054c, 0x0003 }, /* R1356 (0x54c) - AIF2 Frame Ctrl 6 */
{ 0x0000054d, 0x0004 }, /* R1357 (0x54d) - AIF2 Frame Ctrl 7 */
{ 0x0000054e, 0x0005 }, /* R1358 (0x54e) - AIF2 Frame Ctrl 8 */
{ 0x0000054f, 0x0006 }, /* R1359 (0x54f) - AIF2 Frame Ctrl 9 */
{ 0x00000550, 0x0007 }, /* R1360 (0x550) - AIF2 Frame Ctrl 10 */
{ 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */
{ 0x00000553, 0x0002 }, /* R1363 (0x553) - AIF2 Frame Ctrl 13 */
{ 0x00000554, 0x0003 }, /* R1364 (0x554) - AIF2 Frame Ctrl 14 */
{ 0x00000555, 0x0004 }, /* R1365 (0x555) - AIF2 Frame Ctrl 15 */
{ 0x00000556, 0x0005 }, /* R1366 (0x556) - AIF2 Frame Ctrl 16 */
{ 0x00000557, 0x0006 }, /* R1367 (0x557) - AIF2 Frame Ctrl 17 */
{ 0x00000558, 0x0007 }, /* R1368 (0x558) - AIF2 Frame Ctrl 18 */
{ 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */
{ 0x0000055a, 0x0000 }, /* R1370 (0x55a) - AIF2 Rx Enables */
{ 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */
{ 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */
{ 0x0000058a, 0x0001 }, /* R1418 (0x58a) - AIF3 Frame Ctrl 4 */
{ 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */
{ 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */
{ 0x0000059a, 0x0000 }, /* R1434 (0x59a) - AIF3 Rx Enables */
{ 0x000005a0, 0x000c }, /* R1440 (0x5a0) - AIF4 BCLK Ctrl */
{ 0x000005a1, 0x0000 }, /* R1441 (0x5a1) - AIF4 Tx Pin Ctrl */
{ 0x000005a2, 0x0000 }, /* R1442 (0x5a2) - AIF4 Rx Pin Ctrl */
{ 0x000005a3, 0x0000 }, /* R1443 (0x5a3) - AIF4 Rate Ctrl */
{ 0x000005a4, 0x0000 }, /* R1444 (0x5a4) - AIF4 Format */
{ 0x000005a6, 0x0040 }, /* R1446 (0x5a6) - AIF4 Rx BCLK Rate */
{ 0x000005a7, 0x1818 }, /* R1447 (0x5a7) - AIF4 Frame Ctrl 1 */
{ 0x000005a8, 0x1818 }, /* R1448 (0x5a8) - AIF4 Frame Ctrl 2 */
{ 0x000005a9, 0x0000 }, /* R1449 (0x5a9) - AIF4 Frame Ctrl 3 */
{ 0x000005aa, 0x0001 }, /* R1450 (0x5aa) - AIF4 Frame Ctrl 4 */
{ 0x000005b1, 0x0000 }, /* R1457 (0x5b1) - AIF4 Frame Ctrl 11 */
{ 0x000005b2, 0x0001 }, /* R1458 (0x5b2) - AIF4 Frame Ctrl 12 */
{ 0x000005b9, 0x0000 }, /* R1465 (0x5b9) - AIF4 Tx Enables */
{ 0x000005ba, 0x0000 }, /* R1466 (0x5ba) - AIF4 Rx Enables */
{ 0x000005c2, 0x0000 }, /* R1474 (0x5c2) - SPD1 TX Control */
{ 0x000005e3, 0x0000 }, /* R1507 (0x5e3) - SLIMbus Framer Ref Gear */
{ 0x000005e5, 0x0000 }, /* R1509 (0x5e5) - SLIMbus Rates 1 */
{ 0x000005e6, 0x0000 }, /* R1510 (0x5e6) - SLIMbus Rates 2 */
{ 0x000005e7, 0x0000 }, /* R1511 (0x5e7) - SLIMbus Rates 3 */
{ 0x000005e8, 0x0000 }, /* R1512 (0x5e8) - SLIMbus Rates 4 */
{ 0x000005e9, 0x0000 }, /* R1513 (0x5e9) - SLIMbus Rates 5 */
{ 0x000005ea, 0x0000 }, /* R1514 (0x5ea) - SLIMbus Rates 6 */
{ 0x000005eb, 0x0000 }, /* R1515 (0x5eb) - SLIMbus Rates 7 */
{ 0x000005ec, 0x0000 }, /* R1516 (0x5ec) - SLIMbus Rates 8 */
{ 0x000005f5, 0x0000 }, /* R1525 (0x5f5) - SLIMbus RX Channel Enable */
{ 0x000005f6, 0x0000 }, /* R1526 (0x5F6) - SLIMbus TX Channel Enable */
{ 0x00000640, 0x0000 }, /* R1600 (0x640) - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 (0x641) - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 (0x642) - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 (0x643) - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 (0x644) - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 (0x645) - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 (0x646) - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 (0x647) - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 (0x648) - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 (0x649) - PWM2MIX Input 1 Volume */
{ 0x0000064a, 0x0000 }, /* R1610 (0x64a) - PWM2MIX Input 2 Source */
{ 0x0000064b, 0x0080 }, /* R1611 (0x64b) - PWM2MIX Input 2 Volume */
{ 0x0000064c, 0x0000 }, /* R1612 (0x64c) - PWM2MIX Input 3 Source */
{ 0x0000064d, 0x0080 }, /* R1613 (0x64d) - PWM2MIX Input 3 Volume */
{ 0x0000064e, 0x0000 }, /* R1614 (0x64e) - PWM2MIX Input 4 Source */
{ 0x0000064f, 0x0080 }, /* R1615 (0x64f) - PWM2MIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 (0x680) - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 (0x681) - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 (0x682) - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 (0x683) - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 (0x684) - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 (0x685) - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 (0x686) - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 (0x687) - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 (0x688) - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 (0x689) - OUT1RMIX Input 1 Volume */
{ 0x0000068a, 0x0000 }, /* R1674 (0x68a) - OUT1RMIX Input 2 Source */
{ 0x0000068b, 0x0080 }, /* R1675 (0x68b) - OUT1RMIX Input 2 Volume */
{ 0x0000068c, 0x0000 }, /* R1672 (0x68c) - OUT1RMIX Input 3 Source */
{ 0x0000068d, 0x0080 }, /* R1673 (0x68d) - OUT1RMIX Input 3 Volume */
{ 0x0000068e, 0x0000 }, /* R1674 (0x68e) - OUT1RMIX Input 4 Source */
{ 0x0000068f, 0x0080 }, /* R1675 (0x68f) - OUT1RMIX Input 4 Volume */
{ 0x00000690, 0x0000 }, /* R1680 (0x690) - OUT2LMIX Input 1 Source */
{ 0x00000691, 0x0080 }, /* R1681 (0x691) - OUT2LMIX Input 1 Volume */
{ 0x00000692, 0x0000 }, /* R1682 (0x692) - OUT2LMIX Input 2 Source */
{ 0x00000693, 0x0080 }, /* R1683 (0x693) - OUT2LMIX Input 2 Volume */
{ 0x00000694, 0x0000 }, /* R1684 (0x694) - OUT2LMIX Input 3 Source */
{ 0x00000695, 0x0080 }, /* R1685 (0x695) - OUT2LMIX Input 3 Volume */
{ 0x00000696, 0x0000 }, /* R1686 (0x696) - OUT2LMIX Input 4 Source */
{ 0x00000697, 0x0080 }, /* R1687 (0x697) - OUT2LMIX Input 4 Volume */
{ 0x00000698, 0x0000 }, /* R1688 (0x698) - OUT2RMIX Input 1 Source */
{ 0x00000699, 0x0080 }, /* R1689 (0x699) - OUT2RMIX Input 1 Volume */
{ 0x0000069a, 0x0000 }, /* R1690 (0x69a) - OUT2RMIX Input 2 Source */
{ 0x0000069b, 0x0080 }, /* R1691 (0x69b) - OUT2RMIX Input 2 Volume */
{ 0x0000069c, 0x0000 }, /* R1692 (0x69c) - OUT2RMIX Input 3 Source */
{ 0x0000069d, 0x0080 }, /* R1693 (0x69d) - OUT2RMIX Input 3 Volume */
{ 0x0000069e, 0x0000 }, /* R1694 (0x69e) - OUT2RMIX Input 4 Source */
{ 0x0000069f, 0x0080 }, /* R1695 (0x69f) - OUT2RMIX Input 4 Volume */
{ 0x000006a0, 0x0000 }, /* R1696 (0x6a0) - OUT3LMIX Input 1 Source */
{ 0x000006a1, 0x0080 }, /* R1697 (0x6a1) - OUT3LMIX Input 1 Volume */
{ 0x000006a2, 0x0000 }, /* R1698 (0x6a2) - OUT3LMIX Input 2 Source */
{ 0x000006a3, 0x0080 }, /* R1699 (0x6a3) - OUT3LMIX Input 2 Volume */
{ 0x000006a4, 0x0000 }, /* R1700 (0x6a4) - OUT3LMIX Input 3 Source */
{ 0x000006a5, 0x0080 }, /* R1701 (0x6a5) - OUT3LMIX Input 3 Volume */
{ 0x000006a6, 0x0000 }, /* R1702 (0x6a6) - OUT3LMIX Input 4 Source */
{ 0x000006a7, 0x0080 }, /* R1703 (0x6a7) - OUT3LMIX Input 4 Volume */
{ 0x000006a8, 0x0000 }, /* R1704 (0x6a8) - OUT3RMIX Input 1 Source */
{ 0x000006a9, 0x0080 }, /* R1705 (0x6a9) - OUT3RMIX Input 1 Volume */
{ 0x000006aa, 0x0000 }, /* R1706 (0x6aa) - OUT3RMIX Input 2 Source */
{ 0x000006ab, 0x0080 }, /* R1707 (0x6ab) - OUT3RMIX Input 2 Volume */
{ 0x000006ac, 0x0000 }, /* R1708 (0x6ac) - OUT3RMIX Input 3 Source */
{ 0x000006ad, 0x0080 }, /* R1709 (0x6ad) - OUT3RMIX Input 3 Volume */
{ 0x000006ae, 0x0000 }, /* R1710 (0x6ae) - OUT3RMIX Input 4 Source */
{ 0x000006af, 0x0080 }, /* R1711 (0x6af) - OUT3RMIX Input 4 Volume */
{ 0x000006b0, 0x0000 }, /* R1712 (0x6b0) - OUT4LMIX Input 1 Source */
{ 0x000006b1, 0x0080 }, /* R1713 (0x6b1) - OUT4LMIX Input 1 Volume */
{ 0x000006b2, 0x0000 }, /* R1714 (0x6b2) - OUT4LMIX Input 2 Source */
{ 0x000006b3, 0x0080 }, /* R1715 (0x6b3) - OUT4LMIX Input 2 Volume */
{ 0x000006b4, 0x0000 }, /* R1716 (0x6b4) - OUT4LMIX Input 3 Source */
{ 0x000006b5, 0x0080 }, /* R1717 (0x6b5) - OUT4LMIX Input 3 Volume */
{ 0x000006b6, 0x0000 }, /* R1718 (0x6b6) - OUT4LMIX Input 4 Source */
{ 0x000006b7, 0x0080 }, /* R1719 (0x6b7) - OUT4LMIX Input 4 Volume */
{ 0x000006b8, 0x0000 }, /* R1720 (0x6b8) - OUT4RMIX Input 1 Source */
{ 0x000006b9, 0x0080 }, /* R1721 (0x6b9) - OUT4RMIX Input 1 Volume */
{ 0x000006ba, 0x0000 }, /* R1722 (0x6ba) - OUT4RMIX Input 2 Source */
{ 0x000006bb, 0x0080 }, /* R1723 (0x6bb) - OUT4RMIX Input 2 Volume */
{ 0x000006bc, 0x0000 }, /* R1724 (0x6bc) - OUT4RMIX Input 3 Source */
{ 0x000006bd, 0x0080 }, /* R1725 (0x6bd) - OUT4RMIX Input 3 Volume */
{ 0x000006be, 0x0000 }, /* R1726 (0x6be) - OUT4RMIX Input 4 Source */
{ 0x000006bf, 0x0080 }, /* R1727 (0x6bf) - OUT4RMIX Input 4 Volume */
{ 0x000006c0, 0x0000 }, /* R1728 (0x6c0) - OUT5LMIX Input 1 Source */
{ 0x000006c1, 0x0080 }, /* R1729 (0x6c1) - OUT5LMIX Input 1 Volume */
{ 0x000006c2, 0x0000 }, /* R1730 (0x6c2) - OUT5LMIX Input 2 Source */
{ 0x000006c3, 0x0080 }, /* R1731 (0x6c3) - OUT5LMIX Input 2 Volume */
{ 0x000006c4, 0x0000 }, /* R1732 (0x6c4) - OUT5LMIX Input 3 Source */
{ 0x000006c5, 0x0080 }, /* R1733 (0x6c5) - OUT5LMIX Input 3 Volume */
{ 0x000006c6, 0x0000 }, /* R1734 (0x6c6) - OUT5LMIX Input 4 Source */
{ 0x000006c7, 0x0080 }, /* R1735 (0x6c7) - OUT5LMIX Input 4 Volume */
{ 0x000006c8, 0x0000 }, /* R1736 (0x6c8) - OUT5RMIX Input 1 Source */
{ 0x000006c9, 0x0080 }, /* R1737 (0x6c9) - OUT5RMIX Input 1 Volume */
{ 0x000006ca, 0x0000 }, /* R1738 (0x6ca) - OUT5RMIX Input 2 Source */
{ 0x000006cb, 0x0080 }, /* R1739 (0x6cb) - OUT5RMIX Input 2 Volume */
{ 0x000006cc, 0x0000 }, /* R1740 (0x6cc) - OUT5RMIX Input 3 Source */
{ 0x000006cd, 0x0080 }, /* R1741 (0x6cd) - OUT5RMIX Input 3 Volume */
{ 0x000006ce, 0x0000 }, /* R1742 (0x6ce) - OUT5RMIX Input 4 Source */
{ 0x000006cf, 0x0080 }, /* R1743 (0x6cf) - OUT5RMIX Input 4 Volume */
{ 0x000006d0, 0x0000 }, /* R1744 (0x6d0) - OUT6LMIX Input 1 Source */
{ 0x000006d1, 0x0080 }, /* R1745 (0x6d1) - OUT6LMIX Input 1 Volume */
{ 0x000006d2, 0x0000 }, /* R1746 (0x6d2) - OUT6LMIX Input 2 Source */
{ 0x000006d3, 0x0080 }, /* R1747 (0x6d3) - OUT6LMIX Input 2 Volume */
{ 0x000006d4, 0x0000 }, /* R1748 (0x6d4) - OUT6LMIX Input 3 Source */
{ 0x000006d5, 0x0080 }, /* R1749 (0x6d5) - OUT6LMIX Input 3 Volume */
{ 0x000006d6, 0x0000 }, /* R1750 (0x6d6) - OUT6LMIX Input 4 Source */
{ 0x000006d7, 0x0080 }, /* R1751 (0x6d7) - OUT6LMIX Input 4 Volume */
{ 0x000006d8, 0x0000 }, /* R1752 (0x6d8) - OUT6RMIX Input 1 Source */
{ 0x000006d9, 0x0080 }, /* R1753 (0x6d9) - OUT6RMIX Input 1 Volume */
{ 0x000006da, 0x0000 }, /* R1754 (0x6da) - OUT6RMIX Input 2 Source */
{ 0x000006db, 0x0080 }, /* R1755 (0x6db) - OUT6RMIX Input 2 Volume */
{ 0x000006dc, 0x0000 }, /* R1756 (0x6dc) - OUT6RMIX Input 3 Source */
{ 0x000006dd, 0x0080 }, /* R1757 (0x6dd) - OUT6RMIX Input 3 Volume */
{ 0x000006de, 0x0000 }, /* R1758 (0x6de) - OUT6RMIX Input 4 Source */
{ 0x000006df, 0x0080 }, /* R1759 (0x6df) - OUT6RMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 (0x700) - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 (0x701) - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 (0x702) - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 (0x703) - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 (0x704) - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 (0x705) - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 (0x706) - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 (0x707) - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 (0x708) - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 (0x709) - AIF1TX2MIX Input 1 Volume */
{ 0x0000070a, 0x0000 }, /* R1802 (0x70a) - AIF1TX2MIX Input 2 Source */
{ 0x0000070b, 0x0080 }, /* R1803 (0x70b) - AIF1TX2MIX Input 2 Volume */
{ 0x0000070c, 0x0000 }, /* R1804 (0x70c) - AIF1TX2MIX Input 3 Source */
{ 0x0000070d, 0x0080 }, /* R1805 (0x70d) - AIF1TX2MIX Input 3 Volume */
{ 0x0000070e, 0x0000 }, /* R1806 (0x70e) - AIF1TX2MIX Input 4 Source */
{ 0x0000070f, 0x0080 }, /* R1807 (0x70f) - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 (0x710) - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 (0x711) - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 (0x712) - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 (0x713) - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 (0x714) - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 (0x715) - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 (0x716) - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 (0x717) - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 (0x718) - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 (0x719) - AIF1TX4MIX Input 1 Volume */
{ 0x0000071a, 0x0000 }, /* R1818 (0x71a) - AIF1TX4MIX Input 2 Source */
{ 0x0000071b, 0x0080 }, /* R1819 (0x71b) - AIF1TX4MIX Input 2 Volume */
{ 0x0000071c, 0x0000 }, /* R1820 (0x71c) - AIF1TX4MIX Input 3 Source */
{ 0x0000071d, 0x0080 }, /* R1821 (0x71d) - AIF1TX4MIX Input 3 Volume */
{ 0x0000071e, 0x0000 }, /* R1822 (0x71e) - AIF1TX4MIX Input 4 Source */
{ 0x0000071f, 0x0080 }, /* R1823 (0x71f) - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 (0x720) - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 (0x721) - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 (0x722) - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 (0x723) - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 (0x724) - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 (0x725) - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 (0x726) - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 (0x727) - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 (0x728) - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 (0x729) - AIF1TX6MIX Input 1 Volume */
{ 0x0000072a, 0x0000 }, /* R1834 (0x72a) - AIF1TX6MIX Input 2 Source */
{ 0x0000072b, 0x0080 }, /* R1835 (0x72b) - AIF1TX6MIX Input 2 Volume */
{ 0x0000072c, 0x0000 }, /* R1836 (0x72c) - AIF1TX6MIX Input 3 Source */
{ 0x0000072d, 0x0080 }, /* R1837 (0x72d) - AIF1TX6MIX Input 3 Volume */
{ 0x0000072e, 0x0000 }, /* R1838 (0x72e) - AIF1TX6MIX Input 4 Source */
{ 0x0000072f, 0x0080 }, /* R1839 (0x72f) - AIF1TX6MIX Input 4 Volume */
{ 0x00000730, 0x0000 }, /* R1840 (0x730) - AIF1TX7MIX Input 1 Source */
{ 0x00000731, 0x0080 }, /* R1841 (0x731) - AIF1TX7MIX Input 1 Volume */
{ 0x00000732, 0x0000 }, /* R1842 (0x732) - AIF1TX7MIX Input 2 Source */
{ 0x00000733, 0x0080 }, /* R1843 (0x733) - AIF1TX7MIX Input 2 Volume */
{ 0x00000734, 0x0000 }, /* R1844 (0x734) - AIF1TX7MIX Input 3 Source */
{ 0x00000735, 0x0080 }, /* R1845 (0x735) - AIF1TX7MIX Input 3 Volume */
{ 0x00000736, 0x0000 }, /* R1846 (0x736) - AIF1TX7MIX Input 4 Source */
{ 0x00000737, 0x0080 }, /* R1847 (0x737) - AIF1TX7MIX Input 4 Volume */
{ 0x00000738, 0x0000 }, /* R1848 (0x738) - AIF1TX8MIX Input 1 Source */
{ 0x00000739, 0x0080 }, /* R1849 (0x739) - AIF1TX8MIX Input 1 Volume */
{ 0x0000073a, 0x0000 }, /* R1850 (0x73a) - AIF1TX8MIX Input 2 Source */
{ 0x0000073b, 0x0080 }, /* R1851 (0x73b) - AIF1TX8MIX Input 2 Volume */
{ 0x0000073c, 0x0000 }, /* R1852 (0x73c) - AIF1TX8MIX Input 3 Source */
{ 0x0000073d, 0x0080 }, /* R1853 (0x73d) - AIF1TX8MIX Input 3 Volume */
{ 0x0000073e, 0x0000 }, /* R1854 (0x73e) - AIF1TX8MIX Input 4 Source */
{ 0x0000073f, 0x0080 }, /* R1855 (0x73f) - AIF1TX8MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 (0x740) - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 (0x741) - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 (0x742) - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 (0x743) - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 (0x744) - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 (0x745) - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 (0x746) - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 (0x747) - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 (0x748) - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 (0x749) - AIF2TX2MIX Input 1 Volume */
{ 0x0000074a, 0x0000 }, /* R1866 (0x74a) - AIF2TX2MIX Input 2 Source */
{ 0x0000074b, 0x0080 }, /* R1867 (0x74b) - AIF2TX2MIX Input 2 Volume */
{ 0x0000074c, 0x0000 }, /* R1868 (0x74c) - AIF2TX2MIX Input 3 Source */
{ 0x0000074d, 0x0080 }, /* R1869 (0x74d) - AIF2TX2MIX Input 3 Volume */
{ 0x0000074e, 0x0000 }, /* R1870 (0x74e) - AIF2TX2MIX Input 4 Source */
{ 0x0000074f, 0x0080 }, /* R1871 (0x74f) - AIF2TX2MIX Input 4 Volume */
{ 0x00000750, 0x0000 }, /* R1872 (0x750) - AIF2TX3MIX Input 1 Source */
{ 0x00000751, 0x0080 }, /* R1873 (0x751) - AIF2TX3MIX Input 1 Volume */
{ 0x00000752, 0x0000 }, /* R1874 (0x752) - AIF2TX3MIX Input 2 Source */
{ 0x00000753, 0x0080 }, /* R1875 (0x753) - AIF2TX3MIX Input 2 Volume */
{ 0x00000754, 0x0000 }, /* R1876 (0x754) - AIF2TX3MIX Input 3 Source */
{ 0x00000755, 0x0080 }, /* R1877 (0x755) - AIF2TX3MIX Input 3 Volume */
{ 0x00000756, 0x0000 }, /* R1878 (0x756) - AIF2TX3MIX Input 4 Source */
{ 0x00000757, 0x0080 }, /* R1879 (0x757) - AIF2TX3MIX Input 4 Volume */
{ 0x00000758, 0x0000 }, /* R1880 (0x758) - AIF2TX4MIX Input 1 Source */
{ 0x00000759, 0x0080 }, /* R1881 (0x759) - AIF2TX4MIX Input 1 Volume */
{ 0x0000075a, 0x0000 }, /* R1882 (0x75a) - AIF2TX4MIX Input 2 Source */
{ 0x0000075b, 0x0080 }, /* R1883 (0x75b) - AIF2TX4MIX Input 2 Volume */
{ 0x0000075c, 0x0000 }, /* R1884 (0x75c) - AIF2TX4MIX Input 3 Source */
{ 0x0000075d, 0x0080 }, /* R1885 (0x75d) - AIF2TX4MIX Input 3 Volume */
{ 0x0000075e, 0x0000 }, /* R1886 (0x75e) - AIF2TX4MIX Input 4 Source */
{ 0x0000075f, 0x0080 }, /* R1887 (0x75f) - AIF2TX4MIX Input 4 Volume */
{ 0x00000760, 0x0000 }, /* R1888 (0x760) - AIF2TX5MIX Input 1 Source */
{ 0x00000761, 0x0080 }, /* R1889 (0x761) - AIF2TX5MIX Input 1 Volume */
{ 0x00000762, 0x0000 }, /* R1890 (0x762) - AIF2TX5MIX Input 2 Source */
{ 0x00000763, 0x0080 }, /* R1891 (0x763) - AIF2TX5MIX Input 2 Volume */
{ 0x00000764, 0x0000 }, /* R1892 (0x764) - AIF2TX5MIX Input 3 Source */
{ 0x00000765, 0x0080 }, /* R1893 (0x765) - AIF2TX5MIX Input 3 Volume */
{ 0x00000766, 0x0000 }, /* R1894 (0x766) - AIF2TX5MIX Input 4 Source */
{ 0x00000767, 0x0080 }, /* R1895 (0x767) - AIF2TX5MIX Input 4 Volume */
{ 0x00000768, 0x0000 }, /* R1896 (0x768) - AIF2TX6MIX Input 1 Source */
{ 0x00000769, 0x0080 }, /* R1897 (0x769) - AIF2TX6MIX Input 1 Volume */
{ 0x0000076a, 0x0000 }, /* R1898 (0x76a) - AIF2TX6MIX Input 2 Source */
{ 0x0000076b, 0x0080 }, /* R1899 (0x76b) - AIF2TX6MIX Input 2 Volume */
{ 0x0000076c, 0x0000 }, /* R1900 (0x76c) - AIF2TX6MIX Input 3 Source */
{ 0x0000076d, 0x0080 }, /* R1901 (0x76d) - AIF2TX6MIX Input 3 Volume */
{ 0x0000076e, 0x0000 }, /* R1902 (0x76e) - AIF2TX6MIX Input 4 Source */
{ 0x0000076f, 0x0080 }, /* R1903 (0x76f) - AIF2TX6MIX Input 4 Volume */
{ 0x00000770, 0x0000 }, /* R1904 (0x770) - AIF2TX7MIX Input 1 Source */
{ 0x00000771, 0x0080 }, /* R1905 (0x771) - AIF2TX7MIX Input 1 Volume */
{ 0x00000772, 0x0000 }, /* R1906 (0x772) - AIF2TX7MIX Input 2 Source */
{ 0x00000773, 0x0080 }, /* R1907 (0x773) - AIF2TX7MIX Input 2 Volume */
{ 0x00000774, 0x0000 }, /* R1908 (0x774) - AIF2TX7MIX Input 3 Source */
{ 0x00000775, 0x0080 }, /* R1909 (0x775) - AIF2TX7MIX Input 3 Volume */
{ 0x00000776, 0x0000 }, /* R1910 (0x776) - AIF2TX7MIX Input 4 Source */
{ 0x00000777, 0x0080 }, /* R1911 (0x777) - AIF2TX7MIX Input 4 Volume */
{ 0x00000778, 0x0000 }, /* R1912 (0x778) - AIF2TX8MIX Input 1 Source */
{ 0x00000779, 0x0080 }, /* R1913 (0x779) - AIF2TX8MIX Input 1 Volume */
{ 0x0000077a, 0x0000 }, /* R1914 (0x77a) - AIF2TX8MIX Input 2 Source */
{ 0x0000077b, 0x0080 }, /* R1915 (0x77b) - AIF2TX8MIX Input 2 Volume */
{ 0x0000077c, 0x0000 }, /* R1916 (0x77c) - AIF2TX8MIX Input 3 Source */
{ 0x0000077d, 0x0080 }, /* R1917 (0x77d) - AIF2TX8MIX Input 3 Volume */
{ 0x0000077e, 0x0000 }, /* R1918 (0x77e) - AIF2TX8MIX Input 4 Source */
{ 0x0000077f, 0x0080 }, /* R1919 (0x77f) - AIF2TX8MIX Input 4 Volume */
{ 0x00000780, 0x0000 }, /* R1920 (0x780) - AIF3TX1MIX Input 1 Source */
{ 0x00000781, 0x0080 }, /* R1921 (0x781) - AIF3TX1MIX Input 1 Volume */
{ 0x00000782, 0x0000 }, /* R1922 (0x782) - AIF3TX1MIX Input 2 Source */
{ 0x00000783, 0x0080 }, /* R1923 (0x783) - AIF3TX1MIX Input 2 Volume */
{ 0x00000784, 0x0000 }, /* R1924 (0x784) - AIF3TX1MIX Input 3 Source */
{ 0x00000785, 0x0080 }, /* R1925 (0x785) - AIF3TX1MIX Input 3 Volume */
{ 0x00000786, 0x0000 }, /* R1926 (0x786) - AIF3TX1MIX Input 4 Source */
{ 0x00000787, 0x0080 }, /* R1927 (0x787) - AIF3TX1MIX Input 4 Volume */
{ 0x00000788, 0x0000 }, /* R1928 (0x788) - AIF3TX2MIX Input 1 Source */
{ 0x00000789, 0x0080 }, /* R1929 (0x789) - AIF3TX2MIX Input 1 Volume */
{ 0x0000078a, 0x0000 }, /* R1930 (0x78a) - AIF3TX2MIX Input 2 Source */
{ 0x0000078b, 0x0080 }, /* R1931 (0x78b) - AIF3TX2MIX Input 2 Volume */
{ 0x0000078c, 0x0000 }, /* R1932 (0x78c) - AIF3TX2MIX Input 3 Source */
{ 0x0000078d, 0x0080 }, /* R1933 (0x78d) - AIF3TX2MIX Input 3 Volume */
{ 0x0000078e, 0x0000 }, /* R1934 (0x78e) - AIF3TX2MIX Input 4 Source */
{ 0x0000078f, 0x0080 }, /* R1935 (0x78f) - AIF3TX2MIX Input 4 Volume */
{ 0x000007a0, 0x0000 }, /* R1952 (0x7a0) - AIF4TX1MIX Input 1 Source */
{ 0x000007a1, 0x0080 }, /* R1953 (0x7a1) - AIF4TX1MIX Input 1 Volume */
{ 0x000007a2, 0x0000 }, /* R1954 (0x7a2) - AIF4TX1MIX Input 2 Source */
{ 0x000007a3, 0x0080 }, /* R1955 (0x7a3) - AIF4TX1MIX Input 2 Volume */
{ 0x000007a4, 0x0000 }, /* R1956 (0x7a4) - AIF4TX1MIX Input 3 Source */
{ 0x000007a5, 0x0080 }, /* R1957 (0x7a5) - AIF4TX1MIX Input 3 Volume */
{ 0x000007a6, 0x0000 }, /* R1958 (0x7a6) - AIF4TX1MIX Input 4 Source */
{ 0x000007a7, 0x0080 }, /* R1959 (0x7a7) - AIF4TX1MIX Input 4 Volume */
{ 0x000007a8, 0x0000 }, /* R1960 (0x7a8) - AIF4TX2MIX Input 1 Source */
{ 0x000007a9, 0x0080 }, /* R1961 (0x7a9) - AIF4TX2MIX Input 1 Volume */
{ 0x000007aa, 0x0000 }, /* R1962 (0x7aa) - AIF4TX2MIX Input 2 Source */
{ 0x000007ab, 0x0080 }, /* R1963 (0x7ab) - AIF4TX2MIX Input 2 Volume */
{ 0x000007ac, 0x0000 }, /* R1964 (0x7ac) - AIF4TX2MIX Input 3 Source */
{ 0x000007ad, 0x0080 }, /* R1965 (0x7ad) - AIF4TX2MIX Input 3 Volume */
{ 0x000007ae, 0x0000 }, /* R1966 (0x7ae) - AIF4TX2MIX Input 4 Source */
{ 0x000007af, 0x0080 }, /* R1967 (0x7af) - AIF4TX2MIX Input 4 Volume */
{ 0x000007c0, 0x0000 }, /* R1984 (0x7c0) - SLIMTX1MIX Input 1 Source */
{ 0x000007c1, 0x0080 }, /* R1985 (0x7c1) - SLIMTX1MIX Input 1 Volume */
{ 0x000007c2, 0x0000 }, /* R1986 (0x7c2) - SLIMTX1MIX Input 2 Source */
{ 0x000007c3, 0x0080 }, /* R1987 (0x7c3) - SLIMTX1MIX Input 2 Volume */
{ 0x000007c4, 0x0000 }, /* R1988 (0x7c4) - SLIMTX1MIX Input 3 Source */
{ 0x000007c5, 0x0080 }, /* R1989 (0x7c5) - SLIMTX1MIX Input 3 Volume */
{ 0x000007c6, 0x0000 }, /* R1990 (0x7c6) - SLIMTX1MIX Input 4 Source */
{ 0x000007c7, 0x0080 }, /* R1991 (0x7c7) - SLIMTX1MIX Input 4 Volume */
{ 0x000007c8, 0x0000 }, /* R1992 (0x7c8) - SLIMTX2MIX Input 1 Source */
{ 0x000007c9, 0x0080 }, /* R1993 (0x7c9) - SLIMTX2MIX Input 1 Volume */
{ 0x000007ca, 0x0000 }, /* R1994 (0x7ca) - SLIMTX2MIX Input 2 Source */
{ 0x000007cb, 0x0080 }, /* R1995 (0x7cb) - SLIMTX2MIX Input 2 Volume */
{ 0x000007cc, 0x0000 }, /* R1996 (0x7cc) - SLIMTX2MIX Input 3 Source */
{ 0x000007cd, 0x0080 }, /* R1997 (0x7cd) - SLIMTX2MIX Input 3 Volume */
{ 0x000007ce, 0x0000 }, /* R1998 (0x7ce) - SLIMTX2MIX Input 4 Source */
{ 0x000007cf, 0x0080 }, /* R1999 (0x7cf) - SLIMTX2MIX Input 4 Volume */
{ 0x000007d0, 0x0000 }, /* R2000 (0x7d0) - SLIMTX3MIX Input 1 Source */
{ 0x000007d1, 0x0080 }, /* R2001 (0x7d1) - SLIMTX3MIX Input 1 Volume */
{ 0x000007d2, 0x0000 }, /* R2002 (0x7d2) - SLIMTX3MIX Input 2 Source */
{ 0x000007d3, 0x0080 }, /* R2003 (0x7d3) - SLIMTX3MIX Input 2 Volume */
{ 0x000007d4, 0x0000 }, /* R2004 (0x7d4) - SLIMTX3MIX Input 3 Source */
{ 0x000007d5, 0x0080 }, /* R2005 (0x7d5) - SLIMTX3MIX Input 3 Volume */
{ 0x000007d6, 0x0000 }, /* R2006 (0x7d6) - SLIMTX3MIX Input 4 Source */
{ 0x000007d7, 0x0080 }, /* R2007 (0x7d7) - SLIMTX3MIX Input 4 Volume */
{ 0x000007d8, 0x0000 }, /* R2008 (0x7d8) - SLIMTX4MIX Input 1 Source */
{ 0x000007d9, 0x0080 }, /* R2009 (0x7d9) - SLIMTX4MIX Input 1 Volume */
{ 0x000007da, 0x0000 }, /* R2010 (0x7da) - SLIMTX4MIX Input 2 Source */
{ 0x000007db, 0x0080 }, /* R2011 (0x7db) - SLIMTX4MIX Input 2 Volume */
{ 0x000007dc, 0x0000 }, /* R2012 (0x7dc) - SLIMTX4MIX Input 3 Source */
{ 0x000007dd, 0x0080 }, /* R2013 (0x7dd) - SLIMTX4MIX Input 3 Volume */
{ 0x000007de, 0x0000 }, /* R2014 (0x7de) - SLIMTX4MIX Input 4 Source */
{ 0x000007df, 0x0080 }, /* R2015 (0x7df) - SLIMTX4MIX Input 4 Volume */
{ 0x000007e0, 0x0000 }, /* R2016 (0x7e0) - SLIMTX5MIX Input 1 Source */
{ 0x000007e1, 0x0080 }, /* R2017 (0x7e1) - SLIMTX5MIX Input 1 Volume */
{ 0x000007e2, 0x0000 }, /* R2018 (0x7e2) - SLIMTX5MIX Input 2 Source */
{ 0x000007e3, 0x0080 }, /* R2019 (0x7e3) - SLIMTX5MIX Input 2 Volume */
{ 0x000007e4, 0x0000 }, /* R2020 (0x7e4) - SLIMTX5MIX Input 3 Source */
{ 0x000007e5, 0x0080 }, /* R2021 (0x7e5) - SLIMTX5MIX Input 3 Volume */
{ 0x000007e6, 0x0000 }, /* R2022 (0x7e6) - SLIMTX5MIX Input 4 Source */
{ 0x000007e7, 0x0080 }, /* R2023 (0x7e7) - SLIMTX5MIX Input 4 Volume */
{ 0x000007e8, 0x0000 }, /* R2024 (0x7e8) - SLIMTX6MIX Input 1 Source */
{ 0x000007e9, 0x0080 }, /* R2025 (0x7e9) - SLIMTX6MIX Input 1 Volume */
{ 0x000007ea, 0x0000 }, /* R2026 (0x7ea) - SLIMTX6MIX Input 2 Source */
{ 0x000007eb, 0x0080 }, /* R2027 (0x7eb) - SLIMTX6MIX Input 2 Volume */
{ 0x000007ec, 0x0000 }, /* R2028 (0x7ec) - SLIMTX6MIX Input 3 Source */
{ 0x000007ed, 0x0080 }, /* R2029 (0x7ed) - SLIMTX6MIX Input 3 Volume */
{ 0x000007ee, 0x0000 }, /* R2030 (0x7ee) - SLIMTX6MIX Input 4 Source */
{ 0x000007ef, 0x0080 }, /* R2031 (0x7ef) - SLIMTX6MIX Input 4 Volume */
{ 0x000007f0, 0x0000 }, /* R2032 (0x7f0) - SLIMTX7MIX Input 1 Source */
{ 0x000007f1, 0x0080 }, /* R2033 (0x7f1) - SLIMTX7MIX Input 1 Volume */
{ 0x000007f2, 0x0000 }, /* R2034 (0x7f2) - SLIMTX7MIX Input 2 Source */
{ 0x000007f3, 0x0080 }, /* R2035 (0x7f3) - SLIMTX7MIX Input 2 Volume */
{ 0x000007f4, 0x0000 }, /* R2036 (0x7f4) - SLIMTX7MIX Input 3 Source */
{ 0x000007f5, 0x0080 }, /* R2037 (0x7f5) - SLIMTX7MIX Input 3 Volume */
{ 0x000007f6, 0x0000 }, /* R2038 (0x7f6) - SLIMTX7MIX Input 4 Source */
{ 0x000007f7, 0x0080 }, /* R2039 (0x7f7) - SLIMTX7MIX Input 4 Volume */
{ 0x000007f8, 0x0000 }, /* R2040 (0x7f8) - SLIMTX8MIX Input 1 Source */
{ 0x000007f9, 0x0080 }, /* R2041 (0x7f9) - SLIMTX8MIX Input 1 Volume */
{ 0x000007fa, 0x0000 }, /* R2042 (0x7fa) - SLIMTX8MIX Input 2 Source */
{ 0x000007fb, 0x0080 }, /* R2043 (0x7fb) - SLIMTX8MIX Input 2 Volume */
{ 0x000007fc, 0x0000 }, /* R2044 (0x7fc) - SLIMTX8MIX Input 3 Source */
{ 0x000007fd, 0x0080 }, /* R2045 (0x7fd) - SLIMTX8MIX Input 3 Volume */
{ 0x000007fe, 0x0000 }, /* R2046 (0x7fe) - SLIMTX8MIX Input 4 Source */
{ 0x000007ff, 0x0080 }, /* R2047 (0x7ff) - SLIMTX8MIX Input 4 Volume */
{ 0x00000800, 0x0000 }, /* R2048 (0x800) - SPDIF1TX1MIX Input 1 Source */
{ 0x00000801, 0x0080 }, /* R2049 (0x801) - SPDIF1TX1MIX Input 1 Volume */
{ 0x00000808, 0x0000 }, /* R2056 (0x808) - SPDIF1TX2MIX Input 1 Source */
{ 0x00000809, 0x0080 }, /* R2057 (0x809) - SPDIF1TX2MIX Input 1 Volume */
{ 0x00000880, 0x0000 }, /* R2176 (0x880) - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 (0x881) - EQ1MIX Input 1 Volume */
{ 0x00000882, 0x0000 }, /* R2178 (0x882) - EQ1MIX Input 2 Source */
{ 0x00000883, 0x0080 }, /* R2179 (0x883) - EQ1MIX Input 2 Volume */
{ 0x00000884, 0x0000 }, /* R2180 (0x884) - EQ1MIX Input 3 Source */
{ 0x00000885, 0x0080 }, /* R2181 (0x885) - EQ1MIX Input 3 Volume */
{ 0x00000886, 0x0000 }, /* R2182 (0x886) - EQ1MIX Input 4 Source */
{ 0x00000887, 0x0080 }, /* R2183 (0x887) - EQ1MIX Input 4 Volume */
{ 0x00000888, 0x0000 }, /* R2184 (0x888) - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 (0x889) - EQ2MIX Input 1 Volume */
{ 0x0000088a, 0x0000 }, /* R2186 (0x88a) - EQ2MIX Input 2 Source */
{ 0x0000088b, 0x0080 }, /* R2187 (0x88b) - EQ2MIX Input 2 Volume */
{ 0x0000088c, 0x0000 }, /* R2188 (0x88c) - EQ2MIX Input 3 Source */
{ 0x0000088d, 0x0080 }, /* R2189 (0x88d) - EQ2MIX Input 3 Volume */
{ 0x0000088e, 0x0000 }, /* R2190 (0x88e) - EQ2MIX Input 4 Source */
{ 0x0000088f, 0x0080 }, /* R2191 (0x88f) - EQ2MIX Input 4 Volume */
{ 0x00000890, 0x0000 }, /* R2192 (0x890) - EQ3MIX Input 1 Source */
{ 0x00000891, 0x0080 }, /* R2193 (0x891) - EQ3MIX Input 1 Volume */
{ 0x00000892, 0x0000 }, /* R2194 (0x892) - EQ3MIX Input 2 Source */
{ 0x00000893, 0x0080 }, /* R2195 (0x893) - EQ3MIX Input 2 Volume */
{ 0x00000894, 0x0000 }, /* R2196 (0x894) - EQ3MIX Input 3 Source */
{ 0x00000895, 0x0080 }, /* R2197 (0x895) - EQ3MIX Input 3 Volume */
{ 0x00000896, 0x0000 }, /* R2198 (0x896) - EQ3MIX Input 4 Source */
{ 0x00000897, 0x0080 }, /* R2199 (0x897) - EQ3MIX Input 4 Volume */
{ 0x00000898, 0x0000 }, /* R2200 (0x898) - EQ4MIX Input 1 Source */
{ 0x00000899, 0x0080 }, /* R2201 (0x899) - EQ4MIX Input 1 Volume */
{ 0x0000089a, 0x0000 }, /* R2202 (0x89a) - EQ4MIX Input 2 Source */
{ 0x0000089b, 0x0080 }, /* R2203 (0x89b) - EQ4MIX Input 2 Volume */
{ 0x0000089c, 0x0000 }, /* R2204 (0x89c) - EQ4MIX Input 3 Source */
{ 0x0000089d, 0x0080 }, /* R2205 (0x89d) - EQ4MIX Input 3 Volume */
{ 0x0000089e, 0x0000 }, /* R2206 (0x89e) - EQ4MIX Input 4 Source */
{ 0x0000089f, 0x0080 }, /* R2207 (0x89f) - EQ4MIX Input 4 Volume */
{ 0x000008c0, 0x0000 }, /* R2240 (0x8c0) - DRC1LMIX Input 1 Source */
{ 0x000008c1, 0x0080 }, /* R2241 (0x8c1) - DRC1LMIX Input 1 Volume */
{ 0x000008c2, 0x0000 }, /* R2242 (0x8c2) - DRC1LMIX Input 2 Source */
{ 0x000008c3, 0x0080 }, /* R2243 (0x8c3) - DRC1LMIX Input 2 Volume */
{ 0x000008c4, 0x0000 }, /* R2244 (0x8c4) - DRC1LMIX Input 3 Source */
{ 0x000008c5, 0x0080 }, /* R2245 (0x8c5) - DRC1LMIX Input 3 Volume */
{ 0x000008c6, 0x0000 }, /* R2246 (0x8c6) - DRC1LMIX Input 4 Source */
{ 0x000008c7, 0x0080 }, /* R2247 (0x8c7) - DRC1LMIX Input 4 Volume */
{ 0x000008c8, 0x0000 }, /* R2248 (0x8c8) - DRC1RMIX Input 1 Source */
{ 0x000008c9, 0x0080 }, /* R2249 (0x8c9) - DRC1RMIX Input 1 Volume */
{ 0x000008ca, 0x0000 }, /* R2250 (0x8ca) - DRC1RMIX Input 2 Source */
{ 0x000008cb, 0x0080 }, /* R2251 (0x8cb) - DRC1RMIX Input 2 Volume */
{ 0x000008cc, 0x0000 }, /* R2252 (0x8cc) - DRC1RMIX Input 3 Source */
{ 0x000008cd, 0x0080 }, /* R2253 (0x8cd) - DRC1RMIX Input 3 Volume */
{ 0x000008ce, 0x0000 }, /* R2254 (0x8ce) - DRC1RMIX Input 4 Source */
{ 0x000008cf, 0x0080 }, /* R2255 (0x8cf) - DRC1RMIX Input 4 Volume */
{ 0x000008d0, 0x0000 }, /* R2256 (0x8d0) - DRC2LMIX Input 1 Source */
{ 0x000008d1, 0x0080 }, /* R2257 (0x8d1) - DRC2LMIX Input 1 Volume */
{ 0x000008d2, 0x0000 }, /* R2258 (0x8d2) - DRC2LMIX Input 2 Source */
{ 0x000008d3, 0x0080 }, /* R2259 (0x8d3) - DRC2LMIX Input 2 Volume */
{ 0x000008d4, 0x0000 }, /* R2260 (0x8d4) - DRC2LMIX Input 3 Source */
{ 0x000008d5, 0x0080 }, /* R2261 (0x8d5) - DRC2LMIX Input 3 Volume */
{ 0x000008d6, 0x0000 }, /* R2262 (0x8d6) - DRC2LMIX Input 4 Source */
{ 0x000008d7, 0x0080 }, /* R2263 (0x8d7) - DRC2LMIX Input 4 Volume */
{ 0x000008d8, 0x0000 }, /* R2264 (0x8d8) - DRC2RMIX Input 1 Source */
{ 0x000008d9, 0x0080 }, /* R2265 (0x8d9) - DRC2RMIX Input 1 Volume */
{ 0x000008da, 0x0000 }, /* R2266 (0x8da) - DRC2RMIX Input 2 Source */
{ 0x000008db, 0x0080 }, /* R2267 (0x8db) - DRC2RMIX Input 2 Volume */
{ 0x000008dc, 0x0000 }, /* R2268 (0x8dc) - DRC2RMIX Input 3 Source */
{ 0x000008dd, 0x0080 }, /* R2269 (0x8dd) - DRC2RMIX Input 3 Volume */
{ 0x000008de, 0x0000 }, /* R2270 (0x8de) - DRC2RMIX Input 4 Source */
{ 0x000008df, 0x0080 }, /* R2271 (0x8df) - DRC2RMIX Input 4 Volume */
{ 0x00000900, 0x0000 }, /* R2304 (0x900) - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 (0x901) - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 (0x902) - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 (0x903) - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 (0x904) - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 (0x905) - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 (0x906) - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 (0x907) - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 (0x908) - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 (0x909) - HPLP2MIX Input 1 Volume */
{ 0x0000090a, 0x0000 }, /* R2314 (0x90a) - HPLP2MIX Input 2 Source */
{ 0x0000090b, 0x0080 }, /* R2315 (0x90b) - HPLP2MIX Input 2 Volume */
{ 0x0000090c, 0x0000 }, /* R2316 (0x90c) - HPLP2MIX Input 3 Source */
{ 0x0000090d, 0x0080 }, /* R2317 (0x90d) - HPLP2MIX Input 3 Volume */
{ 0x0000090e, 0x0000 }, /* R2318 (0x90e) - HPLP2MIX Input 4 Source */
{ 0x0000090f, 0x0080 }, /* R2319 (0x90f) - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 (0x910) - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 (0x911) - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 (0x912) - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 (0x913) - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 (0x914) - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 (0x915) - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 (0x916) - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 (0x917) - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 (0x918) - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 (0x919) - HPLP4MIX Input 1 Volume */
{ 0x0000091a, 0x0000 }, /* R2330 (0x91a) - HPLP4MIX Input 2 Source */
{ 0x0000091b, 0x0080 }, /* R2331 (0x91b) - HPLP4MIX Input 2 Volume */
{ 0x0000091c, 0x0000 }, /* R2332 (0x91c) - HPLP4MIX Input 3 Source */
{ 0x0000091d, 0x0080 }, /* R2333 (0x91d) - HPLP4MIX Input 3 Volume */
{ 0x0000091e, 0x0000 }, /* R2334 (0x91e) - HPLP4MIX Input 4 Source */
{ 0x0000091f, 0x0080 }, /* R2335 (0x91f) - HPLP4MIX Input 4 Volume */
{ 0x00000940, 0x0000 }, /* R2368 (0x940) - DSP1LMIX Input 1 Source */
{ 0x00000941, 0x0080 }, /* R2369 (0x941) - DSP1LMIX Input 1 Volume */
{ 0x00000942, 0x0000 }, /* R2370 (0x942) - DSP1LMIX Input 2 Source */
{ 0x00000943, 0x0080 }, /* R2371 (0x943) - DSP1LMIX Input 2 Volume */
{ 0x00000944, 0x0000 }, /* R2372 (0x944) - DSP1LMIX Input 3 Source */
{ 0x00000945, 0x0080 }, /* R2373 (0x945) - DSP1LMIX Input 3 Volume */
{ 0x00000946, 0x0000 }, /* R2374 (0x946) - DSP1LMIX Input 4 Source */
{ 0x00000947, 0x0080 }, /* R2375 (0x947) - DSP1LMIX Input 4 Volume */
{ 0x00000948, 0x0000 }, /* R2376 (0x948) - DSP1RMIX Input 1 Source */
{ 0x00000949, 0x0080 }, /* R2377 (0x949) - DSP1RMIX Input 1 Volume */
{ 0x0000094a, 0x0000 }, /* R2378 (0x94a) - DSP1RMIX Input 2 Source */
{ 0x0000094b, 0x0080 }, /* R2379 (0x94b) - DSP1RMIX Input 2 Volume */
{ 0x0000094c, 0x0000 }, /* R2380 (0x94c) - DSP1RMIX Input 3 Source */
{ 0x0000094d, 0x0080 }, /* R2381 (0x94d) - DSP1RMIX Input 3 Volume */
{ 0x0000094e, 0x0000 }, /* R2382 (0x94e) - DSP1RMIX Input 4 Source */
{ 0x0000094f, 0x0080 }, /* R2383 (0x94f) - DSP1RMIX Input 4 Volume */
{ 0x00000950, 0x0000 }, /* R2384 (0x950) - DSP1AUX1MIX Input 1 Source */
{ 0x00000958, 0x0000 }, /* R2392 (0x958) - DSP1AUX2MIX Input 1 Source */
{ 0x00000960, 0x0000 }, /* R2400 (0x960) - DSP1AUX3MIX Input 1 Source */
{ 0x00000968, 0x0000 }, /* R2408 (0x968) - DSP1AUX4MIX Input 1 Source */
{ 0x00000970, 0x0000 }, /* R2416 (0x970) - DSP1AUX5MIX Input 1 Source */
{ 0x00000978, 0x0000 }, /* R2424 (0x978) - DSP1AUX6MIX Input 1 Source */
{ 0x00000980, 0x0000 }, /* R2432 (0x980) - DSP2LMIX Input 1 Source */
{ 0x00000981, 0x0080 }, /* R2433 (0x981) - DSP2LMIX Input 1 Volume */
{ 0x00000982, 0x0000 }, /* R2434 (0x982) - DSP2LMIX Input 2 Source */
{ 0x00000983, 0x0080 }, /* R2435 (0x983) - DSP2LMIX Input 2 Volume */
{ 0x00000984, 0x0000 }, /* R2436 (0x984) - DSP2LMIX Input 3 Source */
{ 0x00000985, 0x0080 }, /* R2437 (0x985) - DSP2LMIX Input 3 Volume */
{ 0x00000986, 0x0000 }, /* R2438 (0x986) - DSP2LMIX Input 4 Source */
{ 0x00000987, 0x0080 }, /* R2439 (0x987) - DSP2LMIX Input 4 Volume */
{ 0x00000988, 0x0000 }, /* R2440 (0x988) - DSP2RMIX Input 1 Source */
{ 0x00000989, 0x0080 }, /* R2441 (0x989) - DSP2RMIX Input 1 Volume */
{ 0x0000098a, 0x0000 }, /* R2442 (0x98a) - DSP2RMIX Input 2 Source */
{ 0x0000098b, 0x0080 }, /* R2443 (0x98b) - DSP2RMIX Input 2 Volume */
{ 0x0000098c, 0x0000 }, /* R2444 (0x98c) - DSP2RMIX Input 3 Source */
{ 0x0000098d, 0x0080 }, /* R2445 (0x98d) - DSP2RMIX Input 3 Volume */
{ 0x0000098e, 0x0000 }, /* R2446 (0x98e) - DSP2RMIX Input 4 Source */
{ 0x0000098f, 0x0080 }, /* R2447 (0x98f) - DSP2RMIX Input 4 Volume */
{ 0x00000990, 0x0000 }, /* R2448 (0x990) - DSP2AUX1MIX Input 1 Source */
{ 0x00000998, 0x0000 }, /* R2456 (0x998) - DSP2AUX2MIX Input 1 Source */
{ 0x000009a0, 0x0000 }, /* R2464 (0x9a0) - DSP2AUX3MIX Input 1 Source */
{ 0x000009a8, 0x0000 }, /* R2472 (0x9a8) - DSP2AUX4MIX Input 1 Source */
{ 0x000009b0, 0x0000 }, /* R2480 (0x9b0) - DSP2AUX5MIX Input 1 Source */
{ 0x000009b8, 0x0000 }, /* R2488 (0x9b8) - DSP2AUX6MIX Input 1 Source */
{ 0x000009c0, 0x0000 }, /* R2496 (0x9c0) - DSP3LMIX Input 1 Source */
{ 0x000009c1, 0x0080 }, /* R2497 (0x9c1) - DSP3LMIX Input 1 Volume */
{ 0x000009c2, 0x0000 }, /* R2498 (0x9c2) - DSP3LMIX Input 2 Source */
{ 0x000009c3, 0x0080 }, /* R2499 (0x9c3) - DSP3LMIX Input 2 Volume */
{ 0x000009c4, 0x0000 }, /* R2500 (0x9c4) - DSP3LMIX Input 3 Source */
{ 0x000009c5, 0x0080 }, /* R2501 (0x9c5) - DSP3LMIX Input 3 Volume */
{ 0x000009c6, 0x0000 }, /* R2502 (0x9c6) - DSP3LMIX Input 4 Source */
{ 0x000009c7, 0x0080 }, /* R2503 (0x9c7) - DSP3LMIX Input 4 Volume */
{ 0x000009c8, 0x0000 }, /* R2504 (0x9c8) - DSP3RMIX Input 1 Source */
{ 0x000009c9, 0x0080 }, /* R2505 (0x9c9) - DSP3RMIX Input 1 Volume */
{ 0x000009ca, 0x0000 }, /* R2506 (0x9ca) - DSP3RMIX Input 2 Source */
{ 0x000009cb, 0x0080 }, /* R2507 (0x9cb) - DSP3RMIX Input 2 Volume */
{ 0x000009cc, 0x0000 }, /* R2508 (0x9cc) - DSP3RMIX Input 3 Source */
{ 0x000009cd, 0x0080 }, /* R2509 (0x9cd) - DSP3RMIX Input 3 Volume */
{ 0x000009ce, 0x0000 }, /* R2510 (0x9ce) - DSP3RMIX Input 4 Source */
{ 0x000009cf, 0x0080 }, /* R2511 (0x9cf) - DSP3RMIX Input 4 Volume */
{ 0x000009d0, 0x0000 }, /* R2512 (0x9d0) - DSP3AUX1MIX Input 1 Source */
{ 0x000009d8, 0x0000 }, /* R2520 (0x9d8) - DSP3AUX2MIX Input 1 Source */
{ 0x000009e0, 0x0000 }, /* R2528 (0x9e0) - DSP3AUX3MIX Input 1 Source */
{ 0x000009e8, 0x0000 }, /* R2536 (0x9e8) - DSP3AUX4MIX Input 1 Source */
{ 0x000009f0, 0x0000 }, /* R2544 (0x9f0) - DSP3AUX5MIX Input 1 Source */
{ 0x000009f8, 0x0000 }, /* R2552 (0x9f8) - DSP3AUX6MIX Input 1 Source */
{ 0x00000a00, 0x0000 }, /* R2560 (0xa00) - DSP4LMIX Input 1 Source */
{ 0x00000a01, 0x0080 }, /* R2561 (0xa01) - DSP4LMIX Input 1 Volume */
{ 0x00000a02, 0x0000 }, /* R2562 (0xa02) - DSP4LMIX Input 2 Source */
{ 0x00000a03, 0x0080 }, /* R2563 (0xa03) - DSP4LMIX Input 2 Volume */
{ 0x00000a04, 0x0000 }, /* R2564 (0xa04) - DSP4LMIX Input 3 Source */
{ 0x00000a05, 0x0080 }, /* R2565 (0xa05) - DSP4LMIX Input 3 Volume */
{ 0x00000a06, 0x0000 }, /* R2566 (0xa06) - DSP4LMIX Input 4 Source */
{ 0x00000a07, 0x0080 }, /* R2567 (0xa07) - DSP4LMIX Input 4 Volume */
{ 0x00000a08, 0x0000 }, /* R2568 (0xa08) - DSP4RMIX Input 1 Source */
{ 0x00000a09, 0x0080 }, /* R2569 (0xa09) - DSP4RMIX Input 1 Volume */
{ 0x00000a0a, 0x0000 }, /* R2570 (0xa0a) - DSP4RMIX Input 2 Source */
{ 0x00000a0b, 0x0080 }, /* R2571 (0xa0b) - DSP4RMIX Input 2 Volume */
{ 0x00000a0c, 0x0000 }, /* R2572 (0xa0c) - DSP4RMIX Input 3 Source */
{ 0x00000a0d, 0x0080 }, /* R2573 (0xa0d) - DSP4RMIX Input 3 Volume */
{ 0x00000a0e, 0x0000 }, /* R2574 (0xa0e) - DSP4RMIX Input 4 Source */
{ 0x00000a0f, 0x0080 }, /* R2575 (0xa0f) - DSP4RMIX Input 4 Volume */
{ 0x00000a10, 0x0000 }, /* R2576 (0xa10) - DSP4AUX1MIX Input 1 Source */
{ 0x00000a18, 0x0000 }, /* R2584 (0xa18) - DSP4AUX2MIX Input 1 Source */
{ 0x00000a20, 0x0000 }, /* R2592 (0xa20) - DSP4AUX3MIX Input 1 Source */
{ 0x00000a28, 0x0000 }, /* R2600 (0xa28) - DSP4AUX4MIX Input 1 Source */
{ 0x00000a30, 0x0000 }, /* R2608 (0xa30) - DSP4AUX5MIX Input 1 Source */
{ 0x00000a38, 0x0000 }, /* R2616 (0xa38) - DSP4AUX6MIX Input 1 Source */
{ 0x00000a40, 0x0000 }, /* R2624 (0xa40) - DSP5LMIX Input 1 Source */
{ 0x00000a41, 0x0080 }, /* R2625 (0xa41) - DSP5LMIX Input 1 Volume */
{ 0x00000a42, 0x0000 }, /* R2626 (0xa42) - DSP5LMIX Input 2 Source */
{ 0x00000a43, 0x0080 }, /* R2627 (0xa43) - DSP5LMIX Input 2 Volume */
{ 0x00000a44, 0x0000 }, /* R2628 (0xa44) - DSP5LMIX Input 3 Source */
{ 0x00000a45, 0x0080 }, /* R2629 (0xa45) - DSP5LMIX Input 3 Volume */
{ 0x00000a46, 0x0000 }, /* R2630 (0xa46) - DSP5LMIX Input 4 Source */
{ 0x00000a47, 0x0080 }, /* R2631 (0xa47) - DSP5LMIX Input 4 Volume */
{ 0x00000a48, 0x0000 }, /* R2632 (0xa48) - DSP5RMIX Input 1 Source */
{ 0x00000a49, 0x0080 }, /* R2633 (0xa49) - DSP5RMIX Input 1 Volume */
{ 0x00000a4a, 0x0000 }, /* R2634 (0xa4a) - DSP5RMIX Input 2 Source */
{ 0x00000a4b, 0x0080 }, /* R2635 (0xa4b) - DSP5RMIX Input 2 Volume */
{ 0x00000a4c, 0x0000 }, /* R2636 (0xa4c) - DSP5RMIX Input 3 Source */
{ 0x00000a4d, 0x0080 }, /* R2637 (0xa4d) - DSP5RMIX Input 3 Volume */
{ 0x00000a4e, 0x0000 }, /* R2638 (0xa4e) - DSP5RMIX Input 4 Source */
{ 0x00000a4f, 0x0080 }, /* R2639 (0xa4f) - DSP5RMIX Input 4 Volume */
{ 0x00000a50, 0x0000 }, /* R2640 (0xa50) - DSP5AUX1MIX Input 1 Source */
{ 0x00000a58, 0x0000 }, /* R2658 (0xa58) - DSP5AUX2MIX Input 1 Source */
{ 0x00000a60, 0x0000 }, /* R2656 (0xa60) - DSP5AUX3MIX Input 1 Source */
{ 0x00000a68, 0x0000 }, /* R2664 (0xa68) - DSP5AUX4MIX Input 1 Source */
{ 0x00000a70, 0x0000 }, /* R2672 (0xa70) - DSP5AUX5MIX Input 1 Source */
{ 0x00000a78, 0x0000 }, /* R2680 (0xa78) - DSP5AUX6MIX Input 1 Source */
{ 0x00000a80, 0x0000 }, /* R2688 (0xa80) - ASRC1_1LMIX Input 1 Source */
{ 0x00000a88, 0x0000 }, /* R2696 (0xa88) - ASRC1_1RMIX Input 1 Source */
{ 0x00000a90, 0x0000 }, /* R2704 (0xa90) - ASRC1_2LMIX Input 1 Source */
{ 0x00000a98, 0x0000 }, /* R2712 (0xa98) - ASRC1_2RMIX Input 1 Source */
{ 0x00000aa0, 0x0000 }, /* R2720 (0xaa0) - ASRC2_1LMIX Input 1 Source */
{ 0x00000aa8, 0x0000 }, /* R2728 (0xaa8) - ASRC2_1RMIX Input 1 Source */
{ 0x00000ab0, 0x0000 }, /* R2736 (0xab0) - ASRC2_2LMIX Input 1 Source */
{ 0x00000ab8, 0x0000 }, /* R2744 (0xab8) - ASRC2_2RMIX Input 1 Source */
{ 0x00000b00, 0x0000 }, /* R2816 (0xb00) - ISRC1DEC1MIX Input 1 Source*/
{ 0x00000b08, 0x0000 }, /* R2824 (0xb08) - ISRC1DEC2MIX Input 1 Source*/
{ 0x00000b10, 0x0000 }, /* R2832 (0xb10) - ISRC1DEC3MIX Input 1 Source*/
{ 0x00000b18, 0x0000 }, /* R2840 (0xb18) - ISRC1DEC4MIX Input 1 Source*/
{ 0x00000b20, 0x0000 }, /* R2848 (0xb20) - ISRC1INT1MIX Input 1 Source*/
{ 0x00000b28, 0x0000 }, /* R2856 (0xb28) - ISRC1INT2MIX Input 1 Source*/
{ 0x00000b30, 0x0000 }, /* R2864 (0xb30) - ISRC1INT3MIX Input 1 Source*/
{ 0x00000b38, 0x0000 }, /* R2872 (0xb38) - ISRC1INT4MIX Input 1 Source*/
{ 0x00000b40, 0x0000 }, /* R2880 (0xb40) - ISRC2DEC1MIX Input 1 Source*/
{ 0x00000b48, 0x0000 }, /* R2888 (0xb48) - ISRC2DEC2MIX Input 1 Source*/
{ 0x00000b50, 0x0000 }, /* R2896 (0xb50) - ISRC2DEC3MIX Input 1 Source*/
{ 0x00000b58, 0x0000 }, /* R2904 (0xb58) - ISRC2DEC4MIX Input 1 Source*/
{ 0x00000b60, 0x0000 }, /* R2912 (0xb60) - ISRC2INT1MIX Input 1 Source*/
{ 0x00000b68, 0x0000 }, /* R2920 (0xb68) - ISRC2INT2MIX Input 1 Source*/
{ 0x00000b70, 0x0000 }, /* R2928 (0xb70) - ISRC2INT3MIX Input 1 Source*/
{ 0x00000b78, 0x0000 }, /* R2936 (0xb78) - ISRC2INT4MIX Input 1 Source*/
{ 0x00000b80, 0x0000 }, /* R2944 (0xb80) - ISRC3DEC1MIX Input 1 Source*/
{ 0x00000b88, 0x0000 }, /* R2952 (0xb88) - ISRC3DEC2MIX Input 1 Source*/
{ 0x00000ba0, 0x0000 }, /* R2976 (0xb80) - ISRC3INT1MIX Input 1 Source*/
{ 0x00000ba8, 0x0000 }, /* R2984 (0xb88) - ISRC3INT2MIX Input 1 Source*/
{ 0x00000bc0, 0x0000 }, /* R3008 (0xbc0) - ISRC4DEC1MIX Input 1 Source */
{ 0x00000bc8, 0x0000 }, /* R3016 (0xbc8) - ISRC4DEC2MIX Input 1 Source */
{ 0x00000be0, 0x0000 }, /* R3040 (0xbe0) - ISRC4INT1MIX Input 1 Source */
{ 0x00000be8, 0x0000 }, /* R3048 (0xbe8) - ISRC4INT2MIX Input 1 Source */
{ 0x00000c00, 0x0000 }, /* R3072 (0xc00) - DSP6LMIX Input 1 Source */
{ 0x00000c01, 0x0080 }, /* R3073 (0xc01) - DSP6LMIX Input 1 Volume */
{ 0x00000c02, 0x0000 }, /* R3074 (0xc02) - DSP6LMIX Input 2 Source */
{ 0x00000c03, 0x0080 }, /* R3075 (0xc03) - DSP6LMIX Input 2 Volume */
{ 0x00000c04, 0x0000 }, /* R3076 (0xc04) - DSP6LMIX Input 3 Source */
{ 0x00000c05, 0x0080 }, /* R3077 (0xc05) - DSP6LMIX Input 3 Volume */
{ 0x00000c06, 0x0000 }, /* R3078 (0xc06) - DSP6LMIX Input 4 Source */
{ 0x00000c07, 0x0080 }, /* R3079 (0xc07) - DSP6LMIX Input 4 Volume */
{ 0x00000c08, 0x0000 }, /* R3080 (0xc08) - DSP6RMIX Input 1 Source */
{ 0x00000c09, 0x0080 }, /* R3081 (0xc09) - DSP6RMIX Input 1 Volume */
{ 0x00000c0a, 0x0000 }, /* R3082 (0xc0a) - DSP6RMIX Input 2 Source */
{ 0x00000c0b, 0x0080 }, /* R3083 (0xc0b) - DSP6RMIX Input 2 Volume */
{ 0x00000c0c, 0x0000 }, /* R3084 (0xc0c) - DSP6RMIX Input 3 Source */
{ 0x00000c0d, 0x0080 }, /* R3085 (0xc0d) - DSP6RMIX Input 3 Volume */
{ 0x00000c0e, 0x0000 }, /* R3086 (0xc0e) - DSP6RMIX Input 4 Source */
{ 0x00000c0f, 0x0080 }, /* R3087 (0xc0f) - DSP6RMIX Input 4 Volume */
{ 0x00000c10, 0x0000 }, /* R3088 (0xc10) - DSP6AUX1MIX Input 1 Source */
{ 0x00000c18, 0x0000 }, /* R3088 (0xc18) - DSP6AUX2MIX Input 1 Source */
{ 0x00000c20, 0x0000 }, /* R3088 (0xc20) - DSP6AUX3MIX Input 1 Source */
{ 0x00000c28, 0x0000 }, /* R3088 (0xc28) - DSP6AUX4MIX Input 1 Source */
{ 0x00000c30, 0x0000 }, /* R3088 (0xc30) - DSP6AUX5MIX Input 1 Source */
{ 0x00000c38, 0x0000 }, /* R3088 (0xc38) - DSP6AUX6MIX Input 1 Source */
{ 0x00000c40, 0x0000 }, /* R3136 (0xc40) - DSP7LMIX Input 1 Source */
{ 0x00000c41, 0x0080 }, /* R3137 (0xc41) - DSP7LMIX Input 1 Volume */
{ 0x00000c42, 0x0000 }, /* R3138 (0xc42) - DSP7LMIX Input 2 Source */
{ 0x00000c43, 0x0080 }, /* R3139 (0xc43) - DSP7LMIX Input 2 Volume */
{ 0x00000c44, 0x0000 }, /* R3140 (0xc44) - DSP7LMIX Input 3 Source */
{ 0x00000c45, 0x0080 }, /* R3141 (0xc45) - DSP7lMIX Input 3 Volume */
{ 0x00000c46, 0x0000 }, /* R3142 (0xc46) - DSP7lMIX Input 4 Source */
{ 0x00000c47, 0x0080 }, /* R3143 (0xc47) - DSP7LMIX Input 4 Volume */
{ 0x00000c48, 0x0000 }, /* R3144 (0xc48) - DSP7RMIX Input 1 Source */
{ 0x00000c49, 0x0080 }, /* R3145 (0xc49) - DSP7RMIX Input 1 Volume */
{ 0x00000c4a, 0x0000 }, /* R3146 (0xc4a) - DSP7RMIX Input 2 Source */
{ 0x00000c4b, 0x0080 }, /* R3147 (0xc4b) - DSP7RMIX Input 2 Volume */
{ 0x00000c4c, 0x0000 }, /* R3148 (0xc4c) - DSP7RMIX Input 3 Source */
{ 0x00000c4d, 0x0080 }, /* R3159 (0xc4d) - DSP7RMIX Input 3 Volume */
{ 0x00000c4e, 0x0000 }, /* R3150 (0xc4e) - DSP7RMIX Input 4 Source */
{ 0x00000c4f, 0x0080 }, /* R3151 (0xc4f) - DSP7RMIX Input 4 Volume */
{ 0x00000c50, 0x0000 }, /* R3152 (0xc50) - DSP7AUX1MIX Input 1 Source */
{ 0x00000c58, 0x0000 }, /* R3160 (0xc58) - DSP7AUX2MIX Input 1 Source */
{ 0x00000c60, 0x0000 }, /* R3168 (0xc60) - DSP7AUX3MIX Input 1 Source */
{ 0x00000c68, 0x0000 }, /* R3176 (0xc68) - DSP7AUX4MIX Input 1 Source */
{ 0x00000c70, 0x0000 }, /* R3184 (0xc70) - DSP7AUX5MIX Input 1 Source */
{ 0x00000c78, 0x0000 }, /* R3192 (0xc78) - DSP7AUX6MIX Input 1 Source */
{ 0x00000e00, 0x0000 }, /* R3584 (0xe00) - FX Ctrl1 */
{ 0x00000e10, 0x6318 }, /* R3600 (0xe10) - EQ1_1 */
{ 0x00000e11, 0x6300 }, /* R3601 (0xe11) - EQ1_2 */
{ 0x00000e12, 0x0fc8 }, /* R3602 (0xe12) - EQ1_3 */
{ 0x00000e13, 0x03fe }, /* R3603 (0xe13) - EQ1_4 */
{ 0x00000e14, 0x00e0 }, /* R3604 (0xe14) - EQ1_5 */
{ 0x00000e15, 0x1ec4 }, /* R3605 (0xe15) - EQ1_6 */
{ 0x00000e16, 0xf136 }, /* R3606 (0xe16) - EQ1_7 */
{ 0x00000e17, 0x0409 }, /* R3607 (0xe17) - EQ1_8 */
{ 0x00000e18, 0x04cc }, /* R3608 (0xe18) - EQ1_9 */
{ 0x00000e19, 0x1c9b }, /* R3609 (0xe19) - EQ1_10 */
{ 0x00000e1a, 0xf337 }, /* R3610 (0xe1a) - EQ1_11 */
{ 0x00000e1b, 0x040b }, /* R3611 (0xe1b) - EQ1_12 */
{ 0x00000e1c, 0x0cbb }, /* R3612 (0xe1c) - EQ1_13 */
{ 0x00000e1d, 0x16f8 }, /* R3613 (0xe1d) - EQ1_14 */
{ 0x00000e1e, 0xf7d9 }, /* R3614 (0xe1e) - EQ1_15 */
{ 0x00000e1f, 0x040a }, /* R3615 (0xe1f) - EQ1_16 */
{ 0x00000e20, 0x1f14 }, /* R3616 (0xe20) - EQ1_17 */
{ 0x00000e21, 0x058c }, /* R3617 (0xe21) - EQ1_18 */
{ 0x00000e22, 0x0563 }, /* R3618 (0xe22) - EQ1_19 */
{ 0x00000e23, 0x4000 }, /* R3619 (0xe23) - EQ1_20 */
{ 0x00000e24, 0x0b75 }, /* R3620 (0xe24) - EQ1_21 */
{ 0x00000e26, 0x6318 }, /* R3622 (0xe26) - EQ2_1 */
{ 0x00000e27, 0x6300 }, /* R3623 (0xe27) - EQ2_2 */
{ 0x00000e28, 0x0fc8 }, /* R3624 (0xe28) - EQ2_3 */
{ 0x00000e29, 0x03fe }, /* R3625 (0xe29) - EQ2_4 */
{ 0x00000e2a, 0x00e0 }, /* R3626 (0xe2a) - EQ2_5 */
{ 0x00000e2b, 0x1ec4 }, /* R3627 (0xe2b) - EQ2_6 */
{ 0x00000e2c, 0xf136 }, /* R3628 (0xe2c) - EQ2_7 */
{ 0x00000e2d, 0x0409 }, /* R3629 (0xe2d) - EQ2_8 */
{ 0x00000e2e, 0x04cc }, /* R3630 (0xe2e) - EQ2_9 */
{ 0x00000e2f, 0x1c9b }, /* R3631 (0xe2f) - EQ2_10 */
{ 0x00000e30, 0xf337 }, /* R3632 (0xe30) - EQ2_11 */
{ 0x00000e31, 0x040b }, /* R3633 (0xe31) - EQ2_12 */
{ 0x00000e32, 0x0cbb }, /* R3634 (0xe32) - EQ2_13 */
{ 0x00000e33, 0x16f8 }, /* R3635 (0xe33) - EQ2_14 */
{ 0x00000e34, 0xf7d9 }, /* R3636 (0xe34) - EQ2_15 */
{ 0x00000e35, 0x040a }, /* R3637 (0xe35) - EQ2_16 */
{ 0x00000e36, 0x1f14 }, /* R3638 (0xe36) - EQ2_17 */
{ 0x00000e37, 0x058c }, /* R3639 (0xe37) - EQ2_18 */
{ 0x00000e38, 0x0563 }, /* R3640 (0xe38) - EQ2_19 */
{ 0x00000e39, 0x4000 }, /* R3641 (0xe39) - EQ2_20 */
{ 0x00000e3a, 0x0b75 }, /* R3642 (0xe3a) - EQ2_21 */
{ 0x00000e3c, 0x6318 }, /* R3644 (0xe3c) - EQ3_1 */
{ 0x00000e3d, 0x6300 }, /* R3645 (0xe3d) - EQ3_2 */
{ 0x00000e3e, 0x0fc8 }, /* R3646 (0xe3e) - EQ3_3 */
{ 0x00000e3f, 0x03fe }, /* R3647 (0xe3f) - EQ3_4 */
{ 0x00000e40, 0x00e0 }, /* R3648 (0xe40) - EQ3_5 */
{ 0x00000e41, 0x1ec4 }, /* R3649 (0xe41) - EQ3_6 */
{ 0x00000e42, 0xf136 }, /* R3650 (0xe42) - EQ3_7 */
{ 0x00000e43, 0x0409 }, /* R3651 (0xe43) - EQ3_8 */
{ 0x00000e44, 0x04cc }, /* R3652 (0xe44) - EQ3_9 */
{ 0x00000e45, 0x1c9b }, /* R3653 (0xe45) - EQ3_10 */
{ 0x00000e46, 0xf337 }, /* R3654 (0xe46) - EQ3_11 */
{ 0x00000e47, 0x040b }, /* R3655 (0xe47) - EQ3_12 */
{ 0x00000e48, 0x0cbb }, /* R3656 (0xe48) - EQ3_13 */
{ 0x00000e49, 0x16f8 }, /* R3657 (0xe49) - EQ3_14 */
{ 0x00000e4a, 0xf7d9 }, /* R3658 (0xe4a) - EQ3_15 */
{ 0x00000e4b, 0x040a }, /* R3659 (0xe4b) - EQ3_16 */
{ 0x00000e4c, 0x1f14 }, /* R3660 (0xe4c) - EQ3_17 */
{ 0x00000e4d, 0x058c }, /* R3661 (0xe4d) - EQ3_18 */
{ 0x00000e4e, 0x0563 }, /* R3662 (0xe4e) - EQ3_19 */
{ 0x00000e4f, 0x4000 }, /* R3663 (0xe4f) - EQ3_20 */
{ 0x00000e50, 0x0b75 }, /* R3664 (0xe50) - EQ3_21 */
{ 0x00000e52, 0x6318 }, /* R3666 (0xe52) - EQ4_1 */
{ 0x00000e53, 0x6300 }, /* R3667 (0xe53) - EQ4_2 */
{ 0x00000e54, 0x0fc8 }, /* R3668 (0xe54) - EQ4_3 */
{ 0x00000e55, 0x03fe }, /* R3669 (0xe55) - EQ4_4 */
{ 0x00000e56, 0x00e0 }, /* R3670 (0xe56) - EQ4_5 */
{ 0x00000e57, 0x1ec4 }, /* R3671 (0xe57) - EQ4_6 */
{ 0x00000e58, 0xf136 }, /* R3672 (0xe58) - EQ4_7 */
{ 0x00000e59, 0x0409 }, /* R3673 (0xe59) - EQ4_8 */
{ 0x00000e5a, 0x04cc }, /* R3674 (0xe5a) - EQ4_9 */
{ 0x00000e5b, 0x1c9b }, /* R3675 (0xe5b) - EQ4_10 */
{ 0x00000e5c, 0xf337 }, /* R3676 (0xe5c) - EQ4_11 */
{ 0x00000e5d, 0x040b }, /* R3677 (0xe5d) - EQ4_12 */
{ 0x00000e5e, 0x0cbb }, /* R3678 (0xe5e) - EQ4_13 */
{ 0x00000e5f, 0x16f8 }, /* R3679 (0xe5f) - EQ4_14 */
{ 0x00000e60, 0xf7d9 }, /* R3680 (0xe60) - EQ4_15 */
{ 0x00000e61, 0x040a }, /* R3681 (0xe61) - EQ4_16 */
{ 0x00000e62, 0x1f14 }, /* R3682 (0xe62) - EQ4_17 */
{ 0x00000e63, 0x058c }, /* R3683 (0xe63) - EQ4_18 */
{ 0x00000e64, 0x0563 }, /* R3684 (0xe64) - EQ4_19 */
{ 0x00000e65, 0x4000 }, /* R3685 (0xe65) - EQ4_20 */
{ 0x00000e66, 0x0b75 }, /* R3686 (0xe66) - EQ4_21 */
{ 0x00000e80, 0x0018 }, /* R3712 (0xe80) - DRC1 ctrl1 */
{ 0x00000e81, 0x0933 }, /* R3713 (0xe81) - DRC1 ctrl2 */
{ 0x00000e82, 0x0018 }, /* R3714 (0xe82) - DRC1 ctrl3 */
{ 0x00000e83, 0x0000 }, /* R3715 (0xe83) - DRC1 ctrl4 */
{ 0x00000e84, 0x0000 }, /* R3716 (0xe84) - DRC1 ctrl5 */
{ 0x00000e88, 0x0018 }, /* R3720 (0xe88) - DRC2 ctrl1 */
{ 0x00000e89, 0x0933 }, /* R3721 (0xe89) - DRC2 ctrl2 */
{ 0x00000e8a, 0x0018 }, /* R3722 (0xe8a) - DRC2 ctrl3 */
{ 0x00000e8b, 0x0000 }, /* R3723 (0xe8b) - DRC2 ctrl4 */
{ 0x00000e8c, 0x0000 }, /* R3724 (0xe8c) - DRC2 ctrl5 */
{ 0x00000ec0, 0x0000 }, /* R3776 (0xec0) - HPLPF1_1 */
{ 0x00000ec1, 0x0000 }, /* R3777 (0xec1) - HPLPF1_2 */
{ 0x00000ec4, 0x0000 }, /* R3780 (0xec4) - HPLPF2_1 */
{ 0x00000ec5, 0x0000 }, /* R3781 (0xec5) - HPLPF2_2 */
{ 0x00000ec8, 0x0000 }, /* R3784 (0xec8) - HPLPF3_1 */
{ 0x00000ec9, 0x0000 }, /* R3785 (0xec9) - HPLPF3_2 */
{ 0x00000ecc, 0x0000 }, /* R3788 (0xecc) - HPLPF4_1 */
{ 0x00000ecd, 0x0000 }, /* R3789 (0xecd) - HPLPF4_2 */
{ 0x00000ed0, 0x0000 }, /* R3792 (0xed0) - ASRC2_ENABLE */
{ 0x00000ed2, 0x0000 }, /* R3794 (0xed2) - ASRC2_RATE1 */
{ 0x00000ed3, 0x4000 }, /* R3795 (0xed3) - ASRC2_RATE2 */
{ 0x00000ee0, 0x0000 }, /* R3808 (0xee0) - ASRC1_ENABLE */
{ 0x00000ee2, 0x0000 }, /* R3810 (0xee2) - ASRC1_RATE1 */
{ 0x00000ee3, 0x4000 }, /* R3811 (0xee3) - ASRC1_RATE2 */
{ 0x00000ef0, 0x0000 }, /* R3824 (0xef0) - ISRC 1 CTRL 1 */
{ 0x00000ef1, 0x0001 }, /* R3825 (0xef1) - ISRC 1 CTRL 2 */
{ 0x00000ef2, 0x0000 }, /* R3826 (0xef2) - ISRC 1 CTRL 3 */
{ 0x00000ef3, 0x0000 }, /* R3827 (0xef3) - ISRC 2 CTRL 1 */
{ 0x00000ef4, 0x0001 }, /* R3828 (0xef4) - ISRC 2 CTRL 2 */
{ 0x00000ef5, 0x0000 }, /* R3829 (0xef5) - ISRC 2 CTRL 3 */
{ 0x00000ef6, 0x0000 }, /* R3830 (0xef6) - ISRC 3 CTRL 1 */
{ 0x00000ef7, 0x0001 }, /* R3831 (0xef7) - ISRC 3 CTRL 2 */
{ 0x00000ef8, 0x0000 }, /* R3832 (0xef8) - ISRC 3 CTRL 3 */
{ 0x00000ef9, 0x0000 }, /* R3833 (0xef9) - ISRC 4 CTRL 1 */
{ 0x00000efa, 0x0001 }, /* R3834 (0xefa) - ISRC 4 CTRL 2 */
{ 0x00000efb, 0x0000 }, /* R3835 (0xefb) - ISRC 4 CTRL 3 */
{ 0x00000f01, 0x0000 }, /* R3841 (0xf01) - ANC_SRC */
{ 0x00000f02, 0x0000 }, /* R3842 (0xf02) - DSP Status */
{ 0x00000f08, 0x001c }, /* R3848 (0xf08) - ANC Coefficient */
{ 0x00000f09, 0x0000 }, /* R3849 (0xf09) - ANC Coefficient */
{ 0x00000f0a, 0x0000 }, /* R3850 (0xf0a) - ANC Coefficient */
{ 0x00000f0b, 0x0000 }, /* R3851 (0xf0b) - ANC Coefficient */
{ 0x00000f0c, 0x0000 }, /* R3852 (0xf0c) - ANC Coefficient */
{ 0x00000f0d, 0x0000 }, /* R3853 (0xf0d) - ANC Coefficient */
{ 0x00000f0e, 0x0000 }, /* R3854 (0xf0e) - ANC Coefficient */
{ 0x00000f0f, 0x0000 }, /* R3855 (0xf0f) - ANC Coefficient */
{ 0x00000f10, 0x0000 }, /* R3856 (0xf10) - ANC Coefficient */
{ 0x00000f11, 0x0000 }, /* R3857 (0xf11) - ANC Coefficient */
{ 0x00000f12, 0x0000 }, /* R3858 (0xf12) - ANC Coefficient */
{ 0x00000f15, 0x0000 }, /* R3861 (0xf15) - FCL Filter Control */
{ 0x00000f17, 0x0004 }, /* R3863 (0xf17) - FCL ADC Reformatter Control */
{ 0x00000f18, 0x0004 }, /* R3864 (0xf18) - ANC Coefficient */
{ 0x00000f19, 0x0002 }, /* R3865 (0xf19) - ANC Coefficient */
{ 0x00000f1a, 0x0000 }, /* R3866 (0xf1a) - ANC Coefficient */
{ 0x00000f1b, 0x0010 }, /* R3867 (0xf1b) - ANC Coefficient */
{ 0x00000f1c, 0x0000 }, /* R3868 (0xf1c) - ANC Coefficient */
{ 0x00000f1d, 0x0000 }, /* R3869 (0xf1d) - ANC Coefficient */
{ 0x00000f1e, 0x0000 }, /* R3870 (0xf1e) - ANC Coefficient */
{ 0x00000f1f, 0x0000 }, /* R3871 (0xf1f) - ANC Coefficient */
{ 0x00000f20, 0x0000 }, /* R3872 (0xf20) - ANC Coefficient */
{ 0x00000f21, 0x0000 }, /* R3873 (0xf21) - ANC Coefficient */
{ 0x00000f22, 0x0000 }, /* R3874 (0xf22) - ANC Coefficient */
{ 0x00000f23, 0x0000 }, /* R3875 (0xf23) - ANC Coefficient */
{ 0x00000f24, 0x0000 }, /* R3876 (0xf24) - ANC Coefficient */
{ 0x00000f25, 0x0000 }, /* R3877 (0xf25) - ANC Coefficient */
{ 0x00000f26, 0x0000 }, /* R3878 (0xf26) - ANC Coefficient */
{ 0x00000f27, 0x0000 }, /* R3879 (0xf27) - ANC Coefficient */
{ 0x00000f28, 0x0000 }, /* R3880 (0xf28) - ANC Coefficient */
{ 0x00000f29, 0x0000 }, /* R3881 (0xf29) - ANC Coefficient */
{ 0x00000f2a, 0x0000 }, /* R3882 (0xf2a) - ANC Coefficient */
{ 0x00000f2b, 0x0000 }, /* R3883 (0xf2b) - ANC Coefficient */
{ 0x00000f2c, 0x0000 }, /* R3884 (0xf2c) - ANC Coefficient */
{ 0x00000f2d, 0x0000 }, /* R3885 (0xf2d) - ANC Coefficient */
{ 0x00000f2e, 0x0000 }, /* R3886 (0xf2e) - ANC Coefficient */
{ 0x00000f2f, 0x0000 }, /* R3887 (0xf2f) - ANC Coefficient */
{ 0x00000f30, 0x0000 }, /* R3888 (0xf30) - ANC Coefficient */
{ 0x00000f31, 0x0000 }, /* R3889 (0xf31) - ANC Coefficient */
{ 0x00000f32, 0x0000 }, /* R3890 (0xf32) - ANC Coefficient */
{ 0x00000f33, 0x0000 }, /* R3891 (0xf33) - ANC Coefficient */
{ 0x00000f34, 0x0000 }, /* R3892 (0xf34) - ANC Coefficient */
{ 0x00000f35, 0x0000 }, /* R3893 (0xf35) - ANC Coefficient */
{ 0x00000f36, 0x0000 }, /* R3894 (0xf36) - ANC Coefficient */
{ 0x00000f37, 0x0000 }, /* R3895 (0xf37) - ANC Coefficient */
{ 0x00000f38, 0x0000 }, /* R3896 (0xf38) - ANC Coefficient */
{ 0x00000f39, 0x0000 }, /* R3897 (0xf39) - ANC Coefficient */
{ 0x00000f3a, 0x0000 }, /* R3898 (0xf3a) - ANC Coefficient */
{ 0x00000f3b, 0x0000 }, /* R3899 (0xf3b) - ANC Coefficient */
{ 0x00000f3c, 0x0000 }, /* R3900 (0xf3c) - ANC Coefficient */
{ 0x00000f3d, 0x0000 }, /* R3901 (0xf3d) - ANC Coefficient */
{ 0x00000f3e, 0x0000 }, /* R3902 (0xf3e) - ANC Coefficient */
{ 0x00000f3f, 0x0000 }, /* R3903 (0xf3f) - ANC Coefficient */
{ 0x00000f40, 0x0000 }, /* R3904 (0xf40) - ANC Coefficient */
{ 0x00000f41, 0x0000 }, /* R3905 (0xf41) - ANC Coefficient */
{ 0x00000f42, 0x0000 }, /* R3906 (0xf42) - ANC Coefficient */
{ 0x00000f43, 0x0000 }, /* R3907 (0xf43) - ANC Coefficient */
{ 0x00000f44, 0x0000 }, /* R3908 (0xf44) - ANC Coefficient */
{ 0x00000f45, 0x0000 }, /* R3909 (0xf45) - ANC Coefficient */
{ 0x00000f46, 0x0000 }, /* R3910 (0xf46) - ANC Coefficient */
{ 0x00000f47, 0x0000 }, /* R3911 (0xf47) - ANC Coefficient */
{ 0x00000f48, 0x0000 }, /* R3912 (0xf48) - ANC Coefficient */
{ 0x00000f49, 0x0000 }, /* R3913 (0xf49) - ANC Coefficient */
{ 0x00000f4a, 0x0000 }, /* R3914 (0xf4a) - ANC Coefficient */
{ 0x00000f4b, 0x0000 }, /* R3915 (0xf4b) - ANC Coefficient */
{ 0x00000f4c, 0x0000 }, /* R3916 (0xf4c) - ANC Coefficient */
{ 0x00000f4d, 0x0000 }, /* R3917 (0xf4d) - ANC Coefficient */
{ 0x00000f4e, 0x0000 }, /* R3918 (0xf4e) - ANC Coefficient */
{ 0x00000f4f, 0x0000 }, /* R3919 (0xf4f) - ANC Coefficient */
{ 0x00000f50, 0x0000 }, /* R3920 (0xf50) - ANC Coefficient */
{ 0x00000f51, 0x0000 }, /* R3921 (0xf51) - ANC Coefficient */
{ 0x00000f52, 0x0000 }, /* R3922 (0xf52) - ANC Coefficient */
{ 0x00000f53, 0x0000 }, /* R3923 (0xf53) - ANC Coefficient */
{ 0x00000f54, 0x0000 }, /* R3924 (0xf54) - ANC Coefficient */
{ 0x00000f55, 0x0000 }, /* R3925 (0xf55) - ANC Coefficient */
{ 0x00000f56, 0x0000 }, /* R3926 (0xf56) - ANC Coefficient */
{ 0x00000f57, 0x0000 }, /* R3927 (0xf57) - ANC Coefficient */
{ 0x00000f58, 0x0000 }, /* R3928 (0xf58) - ANC Coefficient */
{ 0x00000f59, 0x0000 }, /* R3929 (0xf59) - ANC Coefficient */
{ 0x00000f5a, 0x0000 }, /* R3930 (0xf5a) - ANC Coefficient */
{ 0x00000f5b, 0x0000 }, /* R3931 (0xf5b) - ANC Coefficient */
{ 0x00000f5c, 0x0000 }, /* R3932 (0xf5c) - ANC Coefficient */
{ 0x00000f5d, 0x0000 }, /* R3933 (0xf5d) - ANC Coefficient */
{ 0x00000f5e, 0x0000 }, /* R3934 (0xf5e) - ANC Coefficient */
{ 0x00000f5f, 0x0000 }, /* R3935 (0xf5f) - ANC Coefficient */
{ 0x00000f60, 0x0000 }, /* R3936 (0xf60) - ANC Coefficient */
{ 0x00000f61, 0x0000 }, /* R3937 (0xf61) - ANC Coefficient */
{ 0x00000f62, 0x0000 }, /* R3938 (0xf62) - ANC Coefficient */
{ 0x00000f63, 0x0000 }, /* R3939 (0xf63) - ANC Coefficient */
{ 0x00000f64, 0x0000 }, /* R3940 (0xf64) - ANC Coefficient */
{ 0x00000f65, 0x0000 }, /* R3941 (0xf65) - ANC Coefficient */
{ 0x00000f66, 0x0000 }, /* R3942 (0xf66) - ANC Coefficient */
{ 0x00000f67, 0x0000 }, /* R3943 (0xf67) - ANC Coefficient */
{ 0x00000f68, 0x0000 }, /* R3944 (0xf68) - ANC Coefficient */
{ 0x00000f69, 0x0000 }, /* R3945 (0xf69) - ANC Coefficient */
{ 0x00000f71, 0x0000 }, /* R3953 (0xf71) - FCR Filter Control */
{ 0x00000f73, 0x0004 }, /* R3955 (0xf73) - FCR ADC Reformatter Control */
{ 0x00000f74, 0x0004 }, /* R3956 (0xf74) - ANC Coefficient */
{ 0x00000f75, 0x0002 }, /* R3957 (0xf75) - ANC Coefficient */
{ 0x00000f76, 0x0000 }, /* R3958 (0xf76) - ANC Coefficient */
{ 0x00000f77, 0x0010 }, /* R3959 (0xf77) - ANC Coefficient */
{ 0x00000f78, 0x0000 }, /* R3960 (0xf78) - ANC Coefficient */
{ 0x00000f79, 0x0000 }, /* R3961 (0xf79) - ANC Coefficient */
{ 0x00000f7a, 0x0000 }, /* R3962 (0xf7a) - ANC Coefficient */
{ 0x00000f7b, 0x0000 }, /* R3963 (0xf7b) - ANC Coefficient */
{ 0x00000f7c, 0x0000 }, /* R3964 (0xf7c) - ANC Coefficient */
{ 0x00000f7d, 0x0000 }, /* R3965 (0xf7d) - ANC Coefficient */
{ 0x00000f7e, 0x0000 }, /* R3966 (0xf7e) - ANC Coefficient */
{ 0x00000f7f, 0x0000 }, /* R3967 (0xf7f) - ANC Coefficient */
{ 0x00000f80, 0x0000 }, /* R3968 (0xf80) - ANC Coefficient */
{ 0x00000f81, 0x0000 }, /* R3969 (0xf81) - ANC Coefficient */
{ 0x00000f82, 0x0000 }, /* R3970 (0xf82) - ANC Coefficient */
{ 0x00000f83, 0x0000 }, /* R3971 (0xf83) - ANC Coefficient */
{ 0x00000f84, 0x0000 }, /* R3972 (0xf84) - ANC Coefficient */
{ 0x00000f85, 0x0000 }, /* R3973 (0xf85) - ANC Coefficient */
{ 0x00000f86, 0x0000 }, /* R3974 (0xf86) - ANC Coefficient */
{ 0x00000f87, 0x0000 }, /* R3975 (0xf87) - ANC Coefficient */
{ 0x00000f88, 0x0000 }, /* R3976 (0xf88) - ANC Coefficient */
{ 0x00000f89, 0x0000 }, /* R3977 (0xf89) - ANC Coefficient */
{ 0x00000f8a, 0x0000 }, /* R3978 (0xf8a) - ANC Coefficient */
{ 0x00000f8b, 0x0000 }, /* R3979 (0xf8b) - ANC Coefficient */
{ 0x00000f8c, 0x0000 }, /* R3980 (0xf8c) - ANC Coefficient */
{ 0x00000f8d, 0x0000 }, /* R3981 (0xf8d) - ANC Coefficient */
{ 0x00000f8e, 0x0000 }, /* R3982 (0xf8e) - ANC Coefficient */
{ 0x00000f8f, 0x0000 }, /* R3983 (0xf8f) - ANC Coefficient */
{ 0x00000f90, 0x0000 }, /* R3984 (0xf90) - ANC Coefficient */
{ 0x00000f91, 0x0000 }, /* R3985 (0xf91) - ANC Coefficient */
{ 0x00000f92, 0x0000 }, /* R3986 (0xf92) - ANC Coefficient */
{ 0x00000f93, 0x0000 }, /* R3987 (0xf93) - ANC Coefficient */
{ 0x00000f94, 0x0000 }, /* R3988 (0xf94) - ANC Coefficient */
{ 0x00000f95, 0x0000 }, /* R3989 (0xf95) - ANC Coefficient */
{ 0x00000f96, 0x0000 }, /* R3990 (0xf96) - ANC Coefficient */
{ 0x00000f97, 0x0000 }, /* R3991 (0xf97) - ANC Coefficient */
{ 0x00000f98, 0x0000 }, /* R3992 (0xf98) - ANC Coefficient */
{ 0x00000f99, 0x0000 }, /* R3993 (0xf99) - ANC Coefficient */
{ 0x00000f9a, 0x0000 }, /* R3994 (0xf9a) - ANC Coefficient */
{ 0x00000f9b, 0x0000 }, /* R3995 (0xf9b) - ANC Coefficient */
{ 0x00000f9c, 0x0000 }, /* R3996 (0xf9c) - ANC Coefficient */
{ 0x00000f9d, 0x0000 }, /* R3997 (0xf9d) - ANC Coefficient */
{ 0x00000f9e, 0x0000 }, /* R3998 (0xf9e) - ANC Coefficient */
{ 0x00000f9f, 0x0000 }, /* R3999 (0xf9f) - ANC Coefficient */
{ 0x00000fa0, 0x0000 }, /* R4000 (0xfa0) - ANC Coefficient */
{ 0x00000fa1, 0x0000 }, /* R4001 (0xfa1) - ANC Coefficient */
{ 0x00000fa2, 0x0000 }, /* R4002 (0xfa2) - ANC Coefficient */
{ 0x00000fa3, 0x0000 }, /* R4003 (0xfa3) - ANC Coefficient */
{ 0x00000fa4, 0x0000 }, /* R4004 (0xfa4) - ANC Coefficient */
{ 0x00000fa5, 0x0000 }, /* R4005 (0xfa5) - ANC Coefficient */
{ 0x00000fa6, 0x0000 }, /* R4006 (0xfa6) - ANC Coefficient */
{ 0x00000fa7, 0x0000 }, /* R4007 (0xfa7) - ANC Coefficient */
{ 0x00000fa8, 0x0000 }, /* R4008 (0xfa8) - ANC Coefficient */
{ 0x00000fa9, 0x0000 }, /* R4009 (0xfa9) - ANC Coefficient */
{ 0x00000faa, 0x0000 }, /* R4010 (0xfaa) - ANC Coefficient */
{ 0x00000fab, 0x0000 }, /* R4011 (0xfab) - ANC Coefficient */
{ 0x00000fac, 0x0000 }, /* R4012 (0xfac) - ANC Coefficient */
{ 0x00000fad, 0x0000 }, /* R4013 (0xfad) - ANC Coefficient */
{ 0x00000fae, 0x0000 }, /* R4014 (0xfae) - ANC Coefficient */
{ 0x00000faf, 0x0000 }, /* R4015 (0xfaf) - ANC Coefficient */
{ 0x00000fb0, 0x0000 }, /* R4016 (0xfb0) - ANC Coefficient */
{ 0x00000fb1, 0x0000 }, /* R4017 (0xfb1) - ANC Coefficient */
{ 0x00000fb2, 0x0000 }, /* R4018 (0xfb2) - ANC Coefficient */
{ 0x00000fb3, 0x0000 }, /* R4019 (0xfb3) - ANC Coefficient */
{ 0x00000fb4, 0x0000 }, /* R4020 (0xfb4) - ANC Coefficient */
{ 0x00000fb5, 0x0000 }, /* R4021 (0xfb5) - ANC Coefficient */
{ 0x00000fb6, 0x0000 }, /* R4022 (0xfb6) - ANC Coefficient */
{ 0x00000fb7, 0x0000 }, /* R4023 (0xfb7) - ANC Coefficient */
{ 0x00000fb8, 0x0000 }, /* R4024 (0xfb8) - ANC Coefficient */
{ 0x00000fb9, 0x0000 }, /* R4025 (0xfb9) - ANC Coefficient */
{ 0x00000fba, 0x0000 }, /* R4026 (0xfba) - ANC Coefficient */
{ 0x00000fbb, 0x0000 }, /* R4027 (0xfbb) - ANC Coefficient */
{ 0x00000fbc, 0x0000 }, /* R4028 (0xfbc) - ANC Coefficient */
{ 0x00000fbd, 0x0000 }, /* R4029 (0xfbd) - ANC Coefficient */
{ 0x00000fbe, 0x0000 }, /* R4030 (0xfbe) - ANC Coefficient */
{ 0x00000fbf, 0x0000 }, /* R4031 (0xfbf) - ANC Coefficient */
{ 0x00000fc0, 0x0000 }, /* R4032 (0xfc0) - ANC Coefficient */
{ 0x00000fc1, 0x0000 }, /* R4033 (0xfc1) - ANC Coefficient */
{ 0x00000fc2, 0x0000 }, /* R4034 (0xfc2) - ANC Coefficient */
{ 0x00000fc3, 0x0000 }, /* R4035 (0xfc3) - ANC Coefficient */
{ 0x00000fc4, 0x0000 }, /* R4036 (0xfc4) - ANC Coefficient */
{ 0x00000fc5, 0x0000 }, /* R4037 (0xfc5) - ANC Coefficient */
{ 0x00001700, 0x2001 }, /* R5888 (0x1700) - GPIO1 Control 1 */
{ 0x00001701, 0xe000 }, /* R5889 (0x1701) - GPIO1 Control 2 */
{ 0x00001702, 0x2001 }, /* R5890 (0x1702) - GPIO2 Control 1 */
{ 0x00001703, 0xe000 }, /* R5891 (0x1703) - GPIO2 Control 2 */
{ 0x00001704, 0x2001 }, /* R5892 (0x1704) - GPIO3 Control 1 */
{ 0x00001705, 0xe000 }, /* R5893 (0x1705) - GPIO3 Control 2 */
{ 0x00001706, 0x2001 }, /* R5894 (0x1706) - GPIO4 Control 1 */
{ 0x00001707, 0xe000 }, /* R5895 (0x1707) - GPIO4 Control 2 */
{ 0x00001708, 0x2001 }, /* R5896 (0x1708) - GPIO5 Control 1 */
{ 0x00001709, 0xe000 }, /* R5897 (0x1709) - GPIO5 Control 2 */
{ 0x0000170a, 0x2001 }, /* R5898 (0x170a) - GPIO6 Control 1 */
{ 0x0000170b, 0xe000 }, /* R5899 (0x170b) - GPIO6 Control 2 */
{ 0x0000170c, 0x2001 }, /* R5900 (0x170c) - GPIO7 Control 1 */
{ 0x0000170d, 0xe000 }, /* R5901 (0x170d) - GPIO7 Control 2 */
{ 0x0000170e, 0x2001 }, /* R5902 (0x170e) - GPIO8 Control 1 */
{ 0x0000170f, 0xe000 }, /* R5903 (0x170f) - GPIO8 Control 2 */
{ 0x00001710, 0x2001 }, /* R5904 (0x1710) - GPIO9 Control 1 */
{ 0x00001711, 0xe000 }, /* R5905 (0x1711) - GPIO9 Control 2 */
{ 0x00001712, 0x2001 }, /* R5906 (0x1712) - GPIO10 Control 1 */
{ 0x00001713, 0xe000 }, /* R5907 (0x1713) - GPIO10 Control 2 */
{ 0x00001714, 0x2001 }, /* R5908 (0x1714) - GPIO11 Control 1 */
{ 0x00001715, 0xe000 }, /* R5909 (0x1715) - GPIO11 Control 2 */
{ 0x00001716, 0x2001 }, /* R5910 (0x1716) - GPIO12 Control 1 */
{ 0x00001717, 0xe000 }, /* R5911 (0x1717) - GPIO12 Control 2 */
{ 0x00001718, 0x2001 }, /* R5912 (0x1718) - GPIO13 Control 1 */
{ 0x00001719, 0xE000 }, /* R5913 (0x1719) - GPIO13 Control 2 */
{ 0x0000171a, 0x2001 }, /* R5914 (0x171a) - GPIO14 Control 1 */
{ 0x0000171b, 0xE000 }, /* R5915 (0x171b) - GPIO14 Control 2 */
{ 0x0000171c, 0x2001 }, /* R5916 (0x171c) - GPIO15 Control 1 */
{ 0x0000171d, 0xE000 }, /* R5917 (0x171d) - GPIO15 Control 2 */
{ 0x0000171e, 0x2001 }, /* R5918 (0x171e) - GPIO16 Control 1 */
{ 0x0000171f, 0xE000 }, /* R5919 (0x171f) - GPIO16 Control 2 */
{ 0x00001720, 0x2001 }, /* R5920 (0x1720) - GPIO17 Control 1 */
{ 0x00001721, 0xe000 }, /* R5921 (0x1721) - GPIO17 Control 2 */
{ 0x00001722, 0x2001 }, /* R5922 (0x1722) - GPIO18 Control 1 */
{ 0x00001723, 0xe000 }, /* R5923 (0x1723) - GPIO18 Control 2 */
{ 0x00001724, 0x2001 }, /* R5924 (0x1724) - GPIO19 Control 1 */
{ 0x00001725, 0xe000 }, /* R5925 (0x1725) - GPIO19 Control 2 */
{ 0x00001726, 0x2001 }, /* R5926 (0x1726) - GPIO20 Control 1 */
{ 0x00001727, 0xe000 }, /* R5927 (0x1727) - GPIO20 Control 2 */
{ 0x00001728, 0x2001 }, /* R5928 (0x1728) - GPIO21 Control 1 */
{ 0x00001729, 0xe000 }, /* R5929 (0x1729) - GPIO21 Control 2 */
{ 0x0000172a, 0x2001 }, /* R5930 (0x172a) - GPIO22 Control 1 */
{ 0x0000172b, 0xe000 }, /* R5931 (0x172b) - GPIO22 Control 2 */
{ 0x0000172c, 0x2001 }, /* R5932 (0x172c) - GPIO23 Control 1 */
{ 0x0000172d, 0xe000 }, /* R5933 (0x172d) - GPIO23 Control 2 */
{ 0x0000172e, 0x2001 }, /* R5934 (0x172e) - GPIO24 Control 1 */
{ 0x0000172f, 0xe000 }, /* R5935 (0x172f) - GPIO24 Control 2 */
{ 0x00001730, 0x2001 }, /* R5936 (0x1730) - GPIO25 Control 1 */
{ 0x00001731, 0xe000 }, /* R5937 (0x1731) - GPIO25 Control 2 */
{ 0x00001732, 0x2001 }, /* R5938 (0x1732) - GPIO26 Control 1 */
{ 0x00001733, 0xe000 }, /* R5939 (0x1733) - GPIO26 Control 2 */
{ 0x00001734, 0x2001 }, /* R5940 (0x1734) - GPIO27 Control 1 */
{ 0x00001735, 0xe000 }, /* R5941 (0x1735) - GPIO27 Control 2 */
{ 0x00001736, 0x2001 }, /* R5942 (0x1736) - GPIO28 Control 1 */
{ 0x00001737, 0xe000 }, /* R5943 (0x1737) - GPIO28 Control 2 */
{ 0x00001738, 0x2001 }, /* R5944 (0x1738) - GPIO29 Control 1 */
{ 0x00001739, 0xe000 }, /* R5945 (0x1739) - GPIO29 Control 2 */
{ 0x0000173a, 0x2001 }, /* R5946 (0x173a) - GPIO30 Control 1 */
{ 0x0000173b, 0xe000 }, /* R5947 (0x173b) - GPIO30 Control 2 */
{ 0x0000173c, 0x2001 }, /* R5948 (0x173c) - GPIO31 Control 1 */
{ 0x0000173d, 0xe000 }, /* R5949 (0x173d) - GPIO31 Control 2 */
{ 0x0000173e, 0x2001 }, /* R5950 (0x173e) - GPIO32 Control 1 */
{ 0x0000173f, 0xe000 }, /* R5951 (0x173f) - GPIO32 Control 2 */
{ 0x00001740, 0x2001 }, /* R5952 (0x1740) - GPIO33 Control 1 */
{ 0x00001741, 0xe000 }, /* R5953 (0x1741) - GPIO33 Control 2 */
{ 0x00001742, 0x2001 }, /* R5954 (0x1742) - GPIO34 Control 1 */
{ 0x00001743, 0xe000 }, /* R5955 (0x1743) - GPIO34 Control 2 */
{ 0x00001744, 0x2001 }, /* R5956 (0x1744) - GPIO35 Control 1 */
{ 0x00001745, 0xe000 }, /* R5957 (0x1745) - GPIO35 Control 2 */
{ 0x00001746, 0x2001 }, /* R5958 (0x1746) - GPIO36 Control 1 */
{ 0x00001747, 0xe000 }, /* R5959 (0x1747) - GPIO36 Control 2 */
{ 0x00001748, 0x2001 }, /* R5960 (0x1748) - GPIO37 Control 1 */
{ 0x00001749, 0xe000 }, /* R5961 (0x1749) - GPIO37 Control 2 */
{ 0x0000174a, 0x2001 }, /* R5962 (0x174a) - GPIO38 Control 1 */
{ 0x0000174b, 0xe000 }, /* R5963 (0x174b) - GPIO38 Control 2 */
{ 0x0000174c, 0x2001 }, /* R5964 (0x174c) - GPIO39 Control 1 */
{ 0x0000174d, 0xe000 }, /* R5965 (0x174d) - GPIO39 Control 2 */
{ 0x0000174e, 0x2001 }, /* R5966 (0x174e) - GPIO40 Control 1 */
{ 0x0000174f, 0xe000 }, /* R5967 (0x174f) - GPIO40 Control 2 */
{ 0x00001840, 0xffff }, /* R6208 (0x1840) - IRQ1 Mask 1 */
{ 0x00001841, 0xffff }, /* R6209 (0x1841) - IRQ1 Mask 2 */
{ 0x00001842, 0xffff }, /* R6210 (0x1842) - IRQ1 Mask 3 */
{ 0x00001843, 0xffff }, /* R6211 (0x1843) - IRQ1 Mask 4 */
{ 0x00001844, 0xffff }, /* R6212 (0x1844) - IRQ1 Mask 5 */
{ 0x00001845, 0xffff }, /* R6213 (0x1845) - IRQ1 Mask 6 */
{ 0x00001846, 0xffff }, /* R6214 (0x1846) - IRQ1 Mask 7 */
{ 0x00001847, 0xffff }, /* R6215 (0x1847) - IRQ1 Mask 8 */
{ 0x00001848, 0xffff }, /* R6216 (0x1848) - IRQ1 Mask 9 */
{ 0x00001849, 0xffff }, /* R6217 (0x1849) - IRQ1 Mask 10 */
{ 0x0000184a, 0xffff }, /* R6218 (0x184a) - IRQ1 Mask 11 */
{ 0x0000184b, 0xffff }, /* R6219 (0x184b) - IRQ1 Mask 12 */
{ 0x0000184c, 0xffff }, /* R6220 (0x184c) - IRQ1 Mask 13 */
{ 0x0000184d, 0xffff }, /* R6221 (0x184d) - IRQ1 Mask 14 */
{ 0x0000184e, 0xffff }, /* R6222 (0x184e) - IRQ1 Mask 15 */
{ 0x0000184f, 0xffff }, /* R6223 (0x184f) - IRQ1 Mask 16 */
{ 0x00001850, 0xffff }, /* R6224 (0x1850) - IRQ1 Mask 17 */
{ 0x00001851, 0xffff }, /* R6225 (0x1851) - IRQ1 Mask 18 */
{ 0x00001852, 0xffff }, /* R6226 (0x1852) - IRQ1 Mask 19 */
{ 0x00001853, 0xffff }, /* R6227 (0x1853) - IRQ1 Mask 20 */
{ 0x00001854, 0xffff }, /* R6228 (0x1854) - IRQ1 Mask 21 */
{ 0x00001855, 0xffff }, /* R6229 (0x1855) - IRQ1 Mask 22 */
{ 0x00001856, 0xffff }, /* R6230 (0x1856) - IRQ1 Mask 23 */
{ 0x00001857, 0xffff }, /* R6231 (0x1857) - IRQ1 Mask 24 */
{ 0x00001858, 0xffff }, /* R6232 (0x1858) - IRQ1 Mask 25 */
{ 0x00001859, 0xffff }, /* R6233 (0x1859) - IRQ1 Mask 26 */
{ 0x0000185a, 0xffff }, /* R6234 (0x185a) - IRQ1 Mask 27 */
{ 0x0000185b, 0xffff }, /* R6235 (0x185b) - IRQ1 Mask 28 */
{ 0x0000185c, 0xffff }, /* R6236 (0x185c) - IRQ1 Mask 29 */
{ 0x0000185d, 0xffff }, /* R6237 (0x185d) - IRQ1 Mask 30 */
{ 0x0000185e, 0xffff }, /* R6238 (0x185e) - IRQ1 Mask 31 */
{ 0x0000185f, 0xffff }, /* R6239 (0x185f) - IRQ1 Mask 32 */
{ 0x00001860, 0xffff }, /* R6240 (0x1860) - IRQ1 Mask 33 */
{ 0x00001a06, 0x0000 }, /* R6662 (0x1a06) - Interrupt Debounce 7 */
{ 0x00001a80, 0x4400 }, /* R6784 (0x1a80) - IRQ1 CTRL */
};
static bool cs47l85_is_adsp_memory(unsigned int reg)
{
switch (reg) {
case 0x080000 ... 0x085ffe:
case 0x0a0000 ... 0x0a7ffe:
case 0x0c0000 ... 0x0c1ffe:
case 0x0e0000 ... 0x0e1ffe:
case 0x100000 ... 0x10effe:
case 0x120000 ... 0x12bffe:
case 0x136000 ... 0x137ffe:
case 0x140000 ... 0x14bffe:
case 0x160000 ... 0x161ffe:
case 0x180000 ... 0x18effe:
case 0x1a0000 ... 0x1b1ffe:
case 0x1b6000 ... 0x1b7ffe:
case 0x1c0000 ... 0x1cbffe:
case 0x1e0000 ... 0x1e1ffe:
case 0x200000 ... 0x208ffe:
case 0x220000 ... 0x231ffe:
case 0x240000 ... 0x24bffe:
case 0x260000 ... 0x261ffe:
case 0x280000 ... 0x288ffe:
case 0x2a0000 ... 0x2a9ffe:
case 0x2c0000 ... 0x2c3ffe:
case 0x2e0000 ... 0x2e1ffe:
case 0x300000 ... 0x305ffe:
case 0x320000 ... 0x333ffe:
case 0x340000 ... 0x34bffe:
case 0x360000 ... 0x361ffe:
case 0x380000 ... 0x388ffe:
case 0x3a0000 ... 0x3a7ffe:
case 0x3c0000 ... 0x3c1ffe:
case 0x3e0000 ... 0x3e1ffe:
return true;
default:
return false;
}
}
static bool cs47l85_16bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0:
case MADERA_WRITE_SEQUENCER_CTRL_1:
case MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_TONE_GENERATOR_1:
case MADERA_TONE_GENERATOR_2:
case MADERA_TONE_GENERATOR_3:
case MADERA_TONE_GENERATOR_4:
case MADERA_TONE_GENERATOR_5:
case MADERA_PWM_DRIVE_1:
case MADERA_PWM_DRIVE_2:
case MADERA_PWM_DRIVE_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
case MADERA_HAPTICS_CONTROL_1:
case MADERA_HAPTICS_CONTROL_2:
case MADERA_HAPTICS_PHASE_1_INTENSITY:
case MADERA_HAPTICS_PHASE_1_DURATION:
case MADERA_HAPTICS_PHASE_2_INTENSITY:
case MADERA_HAPTICS_PHASE_2_DURATION:
case MADERA_HAPTICS_PHASE_3_INTENSITY:
case MADERA_HAPTICS_PHASE_3_DURATION:
case MADERA_HAPTICS_STATUS:
case MADERA_COMFORT_NOISE_GENERATOR:
case MADERA_CLOCK_32K_1:
case MADERA_SYSTEM_CLOCK_1:
case MADERA_SAMPLE_RATE_1:
case MADERA_SAMPLE_RATE_2:
case MADERA_SAMPLE_RATE_3:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_ASYNC_CLOCK_1:
case MADERA_ASYNC_SAMPLE_RATE_1:
case MADERA_ASYNC_SAMPLE_RATE_1_STATUS:
case MADERA_ASYNC_SAMPLE_RATE_2:
case MADERA_ASYNC_SAMPLE_RATE_2_STATUS:
case MADERA_DSP_CLOCK_1:
case MADERA_DSP_CLOCK_2:
case MADERA_OUTPUT_SYSTEM_CLOCK:
case MADERA_OUTPUT_ASYNC_CLOCK:
case MADERA_RATE_ESTIMATOR_1:
case MADERA_RATE_ESTIMATOR_2:
case MADERA_RATE_ESTIMATOR_3:
case MADERA_RATE_ESTIMATOR_4:
case MADERA_RATE_ESTIMATOR_5:
case MADERA_FLL1_CONTROL_1:
case MADERA_FLL1_CONTROL_2:
case MADERA_FLL1_CONTROL_3:
case MADERA_FLL1_CONTROL_4:
case MADERA_FLL1_CONTROL_5:
case MADERA_FLL1_CONTROL_6:
case MADERA_FLL1_CONTROL_7:
case MADERA_FLL1_SYNCHRONISER_1:
case MADERA_FLL1_SYNCHRONISER_2:
case MADERA_FLL1_SYNCHRONISER_3:
case MADERA_FLL1_SYNCHRONISER_4:
case MADERA_FLL1_SYNCHRONISER_5:
case MADERA_FLL1_SYNCHRONISER_6:
case MADERA_FLL1_SYNCHRONISER_7:
case MADERA_FLL1_SPREAD_SPECTRUM:
case MADERA_FLL1_GPIO_CLOCK:
case MADERA_FLL2_CONTROL_1:
case MADERA_FLL2_CONTROL_2:
case MADERA_FLL2_CONTROL_3:
case MADERA_FLL2_CONTROL_4:
case MADERA_FLL2_CONTROL_5:
case MADERA_FLL2_CONTROL_6:
case MADERA_FLL2_CONTROL_7:
case MADERA_FLL2_SYNCHRONISER_1:
case MADERA_FLL2_SYNCHRONISER_2:
case MADERA_FLL2_SYNCHRONISER_3:
case MADERA_FLL2_SYNCHRONISER_4:
case MADERA_FLL2_SYNCHRONISER_5:
case MADERA_FLL2_SYNCHRONISER_6:
case MADERA_FLL2_SYNCHRONISER_7:
case MADERA_FLL2_SPREAD_SPECTRUM:
case MADERA_FLL2_GPIO_CLOCK:
case MADERA_FLL3_CONTROL_1:
case MADERA_FLL3_CONTROL_2:
case MADERA_FLL3_CONTROL_3:
case MADERA_FLL3_CONTROL_4:
case MADERA_FLL3_CONTROL_5:
case MADERA_FLL3_CONTROL_6:
case MADERA_FLL3_CONTROL_7:
case MADERA_FLL3_SYNCHRONISER_1:
case MADERA_FLL3_SYNCHRONISER_2:
case MADERA_FLL3_SYNCHRONISER_3:
case MADERA_FLL3_SYNCHRONISER_4:
case MADERA_FLL3_SYNCHRONISER_5:
case MADERA_FLL3_SYNCHRONISER_6:
case MADERA_FLL3_SYNCHRONISER_7:
case MADERA_FLL3_SPREAD_SPECTRUM:
case MADERA_FLL3_GPIO_CLOCK:
case MADERA_MIC_CHARGE_PUMP_1:
case MADERA_HP_CHARGE_PUMP_8:
case MADERA_LDO1_CONTROL_1:
case MADERA_LDO2_CONTROL_1:
case MADERA_MIC_BIAS_CTRL_1:
case MADERA_MIC_BIAS_CTRL_2:
case MADERA_MIC_BIAS_CTRL_3:
case MADERA_MIC_BIAS_CTRL_4:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_HP_CTRL_2L:
case MADERA_HP_CTRL_2R:
case MADERA_HP_CTRL_3L:
case MADERA_HP_CTRL_3R:
case MADERA_DCS_HP1L_CONTROL:
case MADERA_DCS_HP1R_CONTROL:
case MADERA_EDRE_HP_STEREO_CONTROL:
case MADERA_ACCESSORY_DETECT_MODE_1:
case MADERA_HEADPHONE_DETECT_1:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_MICD_CLAMP_CONTROL:
case MADERA_MIC_DETECT_1_CONTROL_1:
case MADERA_MIC_DETECT_1_CONTROL_2:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_LEVEL_1:
case MADERA_MIC_DETECT_1_LEVEL_2:
case MADERA_MIC_DETECT_1_LEVEL_3:
case MADERA_MIC_DETECT_1_LEVEL_4:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_GP_SWITCH_1:
case MADERA_JACK_DETECT_ANALOGUE:
case MADERA_INPUT_ENABLES:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_INPUT_RATE:
case MADERA_INPUT_VOLUME_RAMP:
case MADERA_HPF_CONTROL:
case MADERA_IN1L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1L:
case MADERA_DMIC1L_CONTROL:
case MADERA_IN1R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1R:
case MADERA_DMIC1R_CONTROL:
case MADERA_IN2L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2L:
case MADERA_DMIC2L_CONTROL:
case MADERA_IN2R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2R:
case MADERA_DMIC2R_CONTROL:
case MADERA_IN3L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_3L:
case MADERA_DMIC3L_CONTROL:
case MADERA_IN3R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_3R:
case MADERA_DMIC3R_CONTROL:
case MADERA_IN4L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_4L:
case MADERA_DMIC4L_CONTROL:
case MADERA_IN4R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_4R:
case MADERA_DMIC4R_CONTROL:
case MADERA_IN5L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_5L:
case MADERA_DMIC5L_CONTROL:
case MADERA_IN5R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_5R:
case MADERA_DMIC5R_CONTROL:
case MADERA_IN6L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_6L:
case MADERA_DMIC6L_CONTROL:
case MADERA_IN6R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_6R:
case MADERA_DMIC6R_CONTROL:
case MADERA_OUTPUT_ENABLES_1:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_OUTPUT_RATE_1:
case MADERA_OUTPUT_VOLUME_RAMP:
case MADERA_OUTPUT_PATH_CONFIG_1L:
case MADERA_DAC_DIGITAL_VOLUME_1L:
case MADERA_NOISE_GATE_SELECT_1L:
case MADERA_OUTPUT_PATH_CONFIG_1R:
case MADERA_DAC_DIGITAL_VOLUME_1R:
case MADERA_NOISE_GATE_SELECT_1R:
case MADERA_OUTPUT_PATH_CONFIG_2L:
case MADERA_DAC_DIGITAL_VOLUME_2L:
case MADERA_NOISE_GATE_SELECT_2L:
case MADERA_OUTPUT_PATH_CONFIG_2R:
case MADERA_DAC_DIGITAL_VOLUME_2R:
case MADERA_NOISE_GATE_SELECT_2R:
case MADERA_OUTPUT_PATH_CONFIG_3L:
case MADERA_DAC_DIGITAL_VOLUME_3L:
case MADERA_NOISE_GATE_SELECT_3L:
case MADERA_OUTPUT_PATH_CONFIG_3R:
case MADERA_DAC_DIGITAL_VOLUME_3R:
case MADERA_NOISE_GATE_SELECT_3R:
case MADERA_OUTPUT_PATH_CONFIG_4L:
case MADERA_DAC_DIGITAL_VOLUME_4L:
case MADERA_NOISE_GATE_SELECT_4L:
case MADERA_OUTPUT_PATH_CONFIG_4R:
case MADERA_DAC_DIGITAL_VOLUME_4R:
case MADERA_NOISE_GATE_SELECT_4R:
case MADERA_OUTPUT_PATH_CONFIG_5L:
case MADERA_DAC_DIGITAL_VOLUME_5L:
case MADERA_NOISE_GATE_SELECT_5L:
case MADERA_OUTPUT_PATH_CONFIG_5R:
case MADERA_DAC_DIGITAL_VOLUME_5R:
case MADERA_NOISE_GATE_SELECT_5R:
case MADERA_OUTPUT_PATH_CONFIG_6L:
case MADERA_DAC_DIGITAL_VOLUME_6L:
case MADERA_NOISE_GATE_SELECT_6L:
case MADERA_OUTPUT_PATH_CONFIG_6R:
case MADERA_DAC_DIGITAL_VOLUME_6R:
case MADERA_NOISE_GATE_SELECT_6R:
case MADERA_DAC_AEC_CONTROL_1:
case MADERA_DAC_AEC_CONTROL_2:
case MADERA_NOISE_GATE_CONTROL:
case MADERA_PDM_SPK1_CTRL_1:
case MADERA_PDM_SPK1_CTRL_2:
case MADERA_PDM_SPK2_CTRL_1:
case MADERA_PDM_SPK2_CTRL_2:
case MADERA_HP1_SHORT_CIRCUIT_CTRL:
case MADERA_HP2_SHORT_CIRCUIT_CTRL:
case MADERA_HP3_SHORT_CIRCUIT_CTRL:
case MADERA_HP_TEST_CTRL_5:
case MADERA_HP_TEST_CTRL_6:
case MADERA_AIF1_BCLK_CTRL:
case MADERA_AIF1_TX_PIN_CTRL:
case MADERA_AIF1_RX_PIN_CTRL:
case MADERA_AIF1_RATE_CTRL:
case MADERA_AIF1_FORMAT:
case MADERA_AIF1_RX_BCLK_RATE:
case MADERA_AIF1_FRAME_CTRL_1:
case MADERA_AIF1_FRAME_CTRL_2:
case MADERA_AIF1_FRAME_CTRL_3:
case MADERA_AIF1_FRAME_CTRL_4:
case MADERA_AIF1_FRAME_CTRL_5:
case MADERA_AIF1_FRAME_CTRL_6:
case MADERA_AIF1_FRAME_CTRL_7:
case MADERA_AIF1_FRAME_CTRL_8:
case MADERA_AIF1_FRAME_CTRL_9:
case MADERA_AIF1_FRAME_CTRL_10:
case MADERA_AIF1_FRAME_CTRL_11:
case MADERA_AIF1_FRAME_CTRL_12:
case MADERA_AIF1_FRAME_CTRL_13:
case MADERA_AIF1_FRAME_CTRL_14:
case MADERA_AIF1_FRAME_CTRL_15:
case MADERA_AIF1_FRAME_CTRL_16:
case MADERA_AIF1_FRAME_CTRL_17:
case MADERA_AIF1_FRAME_CTRL_18:
case MADERA_AIF1_TX_ENABLES:
case MADERA_AIF1_RX_ENABLES:
case MADERA_AIF2_BCLK_CTRL:
case MADERA_AIF2_TX_PIN_CTRL:
case MADERA_AIF2_RX_PIN_CTRL:
case MADERA_AIF2_RATE_CTRL:
case MADERA_AIF2_FORMAT:
case MADERA_AIF2_RX_BCLK_RATE:
case MADERA_AIF2_FRAME_CTRL_1:
case MADERA_AIF2_FRAME_CTRL_2:
case MADERA_AIF2_FRAME_CTRL_3:
case MADERA_AIF2_FRAME_CTRL_4:
case MADERA_AIF2_FRAME_CTRL_5:
case MADERA_AIF2_FRAME_CTRL_6:
case MADERA_AIF2_FRAME_CTRL_7:
case MADERA_AIF2_FRAME_CTRL_8:
case MADERA_AIF2_FRAME_CTRL_9:
case MADERA_AIF2_FRAME_CTRL_10:
case MADERA_AIF2_FRAME_CTRL_11:
case MADERA_AIF2_FRAME_CTRL_12:
case MADERA_AIF2_FRAME_CTRL_13:
case MADERA_AIF2_FRAME_CTRL_14:
case MADERA_AIF2_FRAME_CTRL_15:
case MADERA_AIF2_FRAME_CTRL_16:
case MADERA_AIF2_FRAME_CTRL_17:
case MADERA_AIF2_FRAME_CTRL_18:
case MADERA_AIF2_TX_ENABLES:
case MADERA_AIF2_RX_ENABLES:
case MADERA_AIF3_BCLK_CTRL:
case MADERA_AIF3_TX_PIN_CTRL:
case MADERA_AIF3_RX_PIN_CTRL:
case MADERA_AIF3_RATE_CTRL:
case MADERA_AIF3_FORMAT:
case MADERA_AIF3_RX_BCLK_RATE:
case MADERA_AIF3_FRAME_CTRL_1:
case MADERA_AIF3_FRAME_CTRL_2:
case MADERA_AIF3_FRAME_CTRL_3:
case MADERA_AIF3_FRAME_CTRL_4:
case MADERA_AIF3_FRAME_CTRL_11:
case MADERA_AIF3_FRAME_CTRL_12:
case MADERA_AIF3_TX_ENABLES:
case MADERA_AIF3_RX_ENABLES:
case MADERA_AIF4_BCLK_CTRL:
case MADERA_AIF4_TX_PIN_CTRL:
case MADERA_AIF4_RX_PIN_CTRL:
case MADERA_AIF4_RATE_CTRL:
case MADERA_AIF4_FORMAT:
case MADERA_AIF4_RX_BCLK_RATE:
case MADERA_AIF4_FRAME_CTRL_1:
case MADERA_AIF4_FRAME_CTRL_2:
case MADERA_AIF4_FRAME_CTRL_3:
case MADERA_AIF4_FRAME_CTRL_4:
case MADERA_AIF4_FRAME_CTRL_11:
case MADERA_AIF4_FRAME_CTRL_12:
case MADERA_AIF4_TX_ENABLES:
case MADERA_AIF4_RX_ENABLES:
case MADERA_SPD1_TX_CONTROL:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_SLIMBUS_FRAMER_REF_GEAR:
case MADERA_SLIMBUS_RATES_1:
case MADERA_SLIMBUS_RATES_2:
case MADERA_SLIMBUS_RATES_3:
case MADERA_SLIMBUS_RATES_4:
case MADERA_SLIMBUS_RATES_5:
case MADERA_SLIMBUS_RATES_6:
case MADERA_SLIMBUS_RATES_7:
case MADERA_SLIMBUS_RATES_8:
case MADERA_SLIMBUS_RX_CHANNEL_ENABLE:
case MADERA_SLIMBUS_TX_CHANNEL_ENABLE:
case MADERA_SLIMBUS_RX_PORT_STATUS:
case MADERA_SLIMBUS_TX_PORT_STATUS:
case MADERA_PWM1MIX_INPUT_1_SOURCE:
case MADERA_PWM1MIX_INPUT_1_VOLUME:
case MADERA_PWM1MIX_INPUT_2_SOURCE:
case MADERA_PWM1MIX_INPUT_2_VOLUME:
case MADERA_PWM1MIX_INPUT_3_SOURCE:
case MADERA_PWM1MIX_INPUT_3_VOLUME:
case MADERA_PWM1MIX_INPUT_4_SOURCE:
case MADERA_PWM1MIX_INPUT_4_VOLUME:
case MADERA_PWM2MIX_INPUT_1_SOURCE:
case MADERA_PWM2MIX_INPUT_1_VOLUME:
case MADERA_PWM2MIX_INPUT_2_SOURCE:
case MADERA_PWM2MIX_INPUT_2_VOLUME:
case MADERA_PWM2MIX_INPUT_3_SOURCE:
case MADERA_PWM2MIX_INPUT_3_VOLUME:
case MADERA_PWM2MIX_INPUT_4_SOURCE:
case MADERA_PWM2MIX_INPUT_4_VOLUME:
case MADERA_OUT1LMIX_INPUT_1_SOURCE:
case MADERA_OUT1LMIX_INPUT_1_VOLUME:
case MADERA_OUT1LMIX_INPUT_2_SOURCE:
case MADERA_OUT1LMIX_INPUT_2_VOLUME:
case MADERA_OUT1LMIX_INPUT_3_SOURCE:
case MADERA_OUT1LMIX_INPUT_3_VOLUME:
case MADERA_OUT1LMIX_INPUT_4_SOURCE:
case MADERA_OUT1LMIX_INPUT_4_VOLUME:
case MADERA_OUT1RMIX_INPUT_1_SOURCE:
case MADERA_OUT1RMIX_INPUT_1_VOLUME:
case MADERA_OUT1RMIX_INPUT_2_SOURCE:
case MADERA_OUT1RMIX_INPUT_2_VOLUME:
case MADERA_OUT1RMIX_INPUT_3_SOURCE:
case MADERA_OUT1RMIX_INPUT_3_VOLUME:
case MADERA_OUT1RMIX_INPUT_4_SOURCE:
case MADERA_OUT1RMIX_INPUT_4_VOLUME:
case MADERA_OUT2LMIX_INPUT_1_SOURCE:
case MADERA_OUT2LMIX_INPUT_1_VOLUME:
case MADERA_OUT2LMIX_INPUT_2_SOURCE:
case MADERA_OUT2LMIX_INPUT_2_VOLUME:
case MADERA_OUT2LMIX_INPUT_3_SOURCE:
case MADERA_OUT2LMIX_INPUT_3_VOLUME:
case MADERA_OUT2LMIX_INPUT_4_SOURCE:
case MADERA_OUT2LMIX_INPUT_4_VOLUME:
case MADERA_OUT2RMIX_INPUT_1_SOURCE:
case MADERA_OUT2RMIX_INPUT_1_VOLUME:
case MADERA_OUT2RMIX_INPUT_2_SOURCE:
case MADERA_OUT2RMIX_INPUT_2_VOLUME:
case MADERA_OUT2RMIX_INPUT_3_SOURCE:
case MADERA_OUT2RMIX_INPUT_3_VOLUME:
case MADERA_OUT2RMIX_INPUT_4_SOURCE:
case MADERA_OUT2RMIX_INPUT_4_VOLUME:
case MADERA_OUT3LMIX_INPUT_1_SOURCE:
case MADERA_OUT3LMIX_INPUT_1_VOLUME:
case MADERA_OUT3LMIX_INPUT_2_SOURCE:
case MADERA_OUT3LMIX_INPUT_2_VOLUME:
case MADERA_OUT3LMIX_INPUT_3_SOURCE:
case MADERA_OUT3LMIX_INPUT_3_VOLUME:
case MADERA_OUT3LMIX_INPUT_4_SOURCE:
case MADERA_OUT3LMIX_INPUT_4_VOLUME:
case MADERA_OUT3RMIX_INPUT_1_SOURCE:
case MADERA_OUT3RMIX_INPUT_1_VOLUME:
case MADERA_OUT3RMIX_INPUT_2_SOURCE:
case MADERA_OUT3RMIX_INPUT_2_VOLUME:
case MADERA_OUT3RMIX_INPUT_3_SOURCE:
case MADERA_OUT3RMIX_INPUT_3_VOLUME:
case MADERA_OUT3RMIX_INPUT_4_SOURCE:
case MADERA_OUT3RMIX_INPUT_4_VOLUME:
case MADERA_OUT4LMIX_INPUT_1_SOURCE:
case MADERA_OUT4LMIX_INPUT_1_VOLUME:
case MADERA_OUT4LMIX_INPUT_2_SOURCE:
case MADERA_OUT4LMIX_INPUT_2_VOLUME:
case MADERA_OUT4LMIX_INPUT_3_SOURCE:
case MADERA_OUT4LMIX_INPUT_3_VOLUME:
case MADERA_OUT4LMIX_INPUT_4_SOURCE:
case MADERA_OUT4LMIX_INPUT_4_VOLUME:
case MADERA_OUT4RMIX_INPUT_1_SOURCE:
case MADERA_OUT4RMIX_INPUT_1_VOLUME:
case MADERA_OUT4RMIX_INPUT_2_SOURCE:
case MADERA_OUT4RMIX_INPUT_2_VOLUME:
case MADERA_OUT4RMIX_INPUT_3_SOURCE:
case MADERA_OUT4RMIX_INPUT_3_VOLUME:
case MADERA_OUT4RMIX_INPUT_4_SOURCE:
case MADERA_OUT4RMIX_INPUT_4_VOLUME:
case MADERA_OUT5LMIX_INPUT_1_SOURCE:
case MADERA_OUT5LMIX_INPUT_1_VOLUME:
case MADERA_OUT5LMIX_INPUT_2_SOURCE:
case MADERA_OUT5LMIX_INPUT_2_VOLUME:
case MADERA_OUT5LMIX_INPUT_3_SOURCE:
case MADERA_OUT5LMIX_INPUT_3_VOLUME:
case MADERA_OUT5LMIX_INPUT_4_SOURCE:
case MADERA_OUT5LMIX_INPUT_4_VOLUME:
case MADERA_OUT5RMIX_INPUT_1_SOURCE:
case MADERA_OUT5RMIX_INPUT_1_VOLUME:
case MADERA_OUT5RMIX_INPUT_2_SOURCE:
case MADERA_OUT5RMIX_INPUT_2_VOLUME:
case MADERA_OUT5RMIX_INPUT_3_SOURCE:
case MADERA_OUT5RMIX_INPUT_3_VOLUME:
case MADERA_OUT5RMIX_INPUT_4_SOURCE:
case MADERA_OUT5RMIX_INPUT_4_VOLUME:
case MADERA_OUT6LMIX_INPUT_1_SOURCE:
case MADERA_OUT6LMIX_INPUT_1_VOLUME:
case MADERA_OUT6LMIX_INPUT_2_SOURCE:
case MADERA_OUT6LMIX_INPUT_2_VOLUME:
case MADERA_OUT6LMIX_INPUT_3_SOURCE:
case MADERA_OUT6LMIX_INPUT_3_VOLUME:
case MADERA_OUT6LMIX_INPUT_4_SOURCE:
case MADERA_OUT6LMIX_INPUT_4_VOLUME:
case MADERA_OUT6RMIX_INPUT_1_SOURCE:
case MADERA_OUT6RMIX_INPUT_1_VOLUME:
case MADERA_OUT6RMIX_INPUT_2_SOURCE:
case MADERA_OUT6RMIX_INPUT_2_VOLUME:
case MADERA_OUT6RMIX_INPUT_3_SOURCE:
case MADERA_OUT6RMIX_INPUT_3_VOLUME:
case MADERA_OUT6RMIX_INPUT_4_SOURCE:
case MADERA_OUT6RMIX_INPUT_4_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF4TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF4TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF4TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF4TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF4TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF4TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF4TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF4TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF4TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF4TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF4TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF4TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF4TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF4TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF4TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF4TX2MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_4_VOLUME:
case MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_1_SOURCE:
case MADERA_EQ1MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_2_SOURCE:
case MADERA_EQ1MIX_INPUT_2_VOLUME:
case MADERA_EQ1MIX_INPUT_3_SOURCE:
case MADERA_EQ1MIX_INPUT_3_VOLUME:
case MADERA_EQ1MIX_INPUT_4_SOURCE:
case MADERA_EQ1MIX_INPUT_4_VOLUME:
case MADERA_EQ2MIX_INPUT_1_SOURCE:
case MADERA_EQ2MIX_INPUT_1_VOLUME:
case MADERA_EQ2MIX_INPUT_2_SOURCE:
case MADERA_EQ2MIX_INPUT_2_VOLUME:
case MADERA_EQ2MIX_INPUT_3_SOURCE:
case MADERA_EQ2MIX_INPUT_3_VOLUME:
case MADERA_EQ2MIX_INPUT_4_SOURCE:
case MADERA_EQ2MIX_INPUT_4_VOLUME:
case MADERA_EQ3MIX_INPUT_1_SOURCE:
case MADERA_EQ3MIX_INPUT_1_VOLUME:
case MADERA_EQ3MIX_INPUT_2_SOURCE:
case MADERA_EQ3MIX_INPUT_2_VOLUME:
case MADERA_EQ3MIX_INPUT_3_SOURCE:
case MADERA_EQ3MIX_INPUT_3_VOLUME:
case MADERA_EQ3MIX_INPUT_4_SOURCE:
case MADERA_EQ3MIX_INPUT_4_VOLUME:
case MADERA_EQ4MIX_INPUT_1_SOURCE:
case MADERA_EQ4MIX_INPUT_1_VOLUME:
case MADERA_EQ4MIX_INPUT_2_SOURCE:
case MADERA_EQ4MIX_INPUT_2_VOLUME:
case MADERA_EQ4MIX_INPUT_3_SOURCE:
case MADERA_EQ4MIX_INPUT_3_VOLUME:
case MADERA_EQ4MIX_INPUT_4_SOURCE:
case MADERA_EQ4MIX_INPUT_4_VOLUME:
case MADERA_DRC1LMIX_INPUT_1_SOURCE:
case MADERA_DRC1LMIX_INPUT_1_VOLUME:
case MADERA_DRC1LMIX_INPUT_2_SOURCE:
case MADERA_DRC1LMIX_INPUT_2_VOLUME:
case MADERA_DRC1LMIX_INPUT_3_SOURCE:
case MADERA_DRC1LMIX_INPUT_3_VOLUME:
case MADERA_DRC1LMIX_INPUT_4_SOURCE:
case MADERA_DRC1LMIX_INPUT_4_VOLUME:
case MADERA_DRC1RMIX_INPUT_1_SOURCE:
case MADERA_DRC1RMIX_INPUT_1_VOLUME:
case MADERA_DRC1RMIX_INPUT_2_SOURCE:
case MADERA_DRC1RMIX_INPUT_2_VOLUME:
case MADERA_DRC1RMIX_INPUT_3_SOURCE:
case MADERA_DRC1RMIX_INPUT_3_VOLUME:
case MADERA_DRC1RMIX_INPUT_4_SOURCE:
case MADERA_DRC1RMIX_INPUT_4_VOLUME:
case MADERA_DRC2LMIX_INPUT_1_SOURCE:
case MADERA_DRC2LMIX_INPUT_1_VOLUME:
case MADERA_DRC2LMIX_INPUT_2_SOURCE:
case MADERA_DRC2LMIX_INPUT_2_VOLUME:
case MADERA_DRC2LMIX_INPUT_3_SOURCE:
case MADERA_DRC2LMIX_INPUT_3_VOLUME:
case MADERA_DRC2LMIX_INPUT_4_SOURCE:
case MADERA_DRC2LMIX_INPUT_4_VOLUME:
case MADERA_DRC2RMIX_INPUT_1_SOURCE:
case MADERA_DRC2RMIX_INPUT_1_VOLUME:
case MADERA_DRC2RMIX_INPUT_2_SOURCE:
case MADERA_DRC2RMIX_INPUT_2_VOLUME:
case MADERA_DRC2RMIX_INPUT_3_SOURCE:
case MADERA_DRC2RMIX_INPUT_3_VOLUME:
case MADERA_DRC2RMIX_INPUT_4_SOURCE:
case MADERA_DRC2RMIX_INPUT_4_VOLUME:
case MADERA_HPLP1MIX_INPUT_1_SOURCE:
case MADERA_HPLP1MIX_INPUT_1_VOLUME:
case MADERA_HPLP1MIX_INPUT_2_SOURCE:
case MADERA_HPLP1MIX_INPUT_2_VOLUME:
case MADERA_HPLP1MIX_INPUT_3_SOURCE:
case MADERA_HPLP1MIX_INPUT_3_VOLUME:
case MADERA_HPLP1MIX_INPUT_4_SOURCE:
case MADERA_HPLP1MIX_INPUT_4_VOLUME:
case MADERA_HPLP2MIX_INPUT_1_SOURCE:
case MADERA_HPLP2MIX_INPUT_1_VOLUME:
case MADERA_HPLP2MIX_INPUT_2_SOURCE:
case MADERA_HPLP2MIX_INPUT_2_VOLUME:
case MADERA_HPLP2MIX_INPUT_3_SOURCE:
case MADERA_HPLP2MIX_INPUT_3_VOLUME:
case MADERA_HPLP2MIX_INPUT_4_SOURCE:
case MADERA_HPLP2MIX_INPUT_4_VOLUME:
case MADERA_HPLP3MIX_INPUT_1_SOURCE:
case MADERA_HPLP3MIX_INPUT_1_VOLUME:
case MADERA_HPLP3MIX_INPUT_2_SOURCE:
case MADERA_HPLP3MIX_INPUT_2_VOLUME:
case MADERA_HPLP3MIX_INPUT_3_SOURCE:
case MADERA_HPLP3MIX_INPUT_3_VOLUME:
case MADERA_HPLP3MIX_INPUT_4_SOURCE:
case MADERA_HPLP3MIX_INPUT_4_VOLUME:
case MADERA_HPLP4MIX_INPUT_1_SOURCE:
case MADERA_HPLP4MIX_INPUT_1_VOLUME:
case MADERA_HPLP4MIX_INPUT_2_SOURCE:
case MADERA_HPLP4MIX_INPUT_2_VOLUME:
case MADERA_HPLP4MIX_INPUT_3_SOURCE:
case MADERA_HPLP4MIX_INPUT_3_VOLUME:
case MADERA_HPLP4MIX_INPUT_4_SOURCE:
case MADERA_HPLP4MIX_INPUT_4_VOLUME:
case MADERA_DSP1LMIX_INPUT_1_SOURCE:
case MADERA_DSP1LMIX_INPUT_1_VOLUME:
case MADERA_DSP1LMIX_INPUT_2_SOURCE:
case MADERA_DSP1LMIX_INPUT_2_VOLUME:
case MADERA_DSP1LMIX_INPUT_3_SOURCE:
case MADERA_DSP1LMIX_INPUT_3_VOLUME:
case MADERA_DSP1LMIX_INPUT_4_SOURCE:
case MADERA_DSP1LMIX_INPUT_4_VOLUME:
case MADERA_DSP1RMIX_INPUT_1_SOURCE:
case MADERA_DSP1RMIX_INPUT_1_VOLUME:
case MADERA_DSP1RMIX_INPUT_2_SOURCE:
case MADERA_DSP1RMIX_INPUT_2_VOLUME:
case MADERA_DSP1RMIX_INPUT_3_SOURCE:
case MADERA_DSP1RMIX_INPUT_3_VOLUME:
case MADERA_DSP1RMIX_INPUT_4_SOURCE:
case MADERA_DSP1RMIX_INPUT_4_VOLUME:
case MADERA_DSP1AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP2LMIX_INPUT_1_SOURCE:
case MADERA_DSP2LMIX_INPUT_1_VOLUME:
case MADERA_DSP2LMIX_INPUT_2_SOURCE:
case MADERA_DSP2LMIX_INPUT_2_VOLUME:
case MADERA_DSP2LMIX_INPUT_3_SOURCE:
case MADERA_DSP2LMIX_INPUT_3_VOLUME:
case MADERA_DSP2LMIX_INPUT_4_SOURCE:
case MADERA_DSP2LMIX_INPUT_4_VOLUME:
case MADERA_DSP2RMIX_INPUT_1_SOURCE:
case MADERA_DSP2RMIX_INPUT_1_VOLUME:
case MADERA_DSP2RMIX_INPUT_2_SOURCE:
case MADERA_DSP2RMIX_INPUT_2_VOLUME:
case MADERA_DSP2RMIX_INPUT_3_SOURCE:
case MADERA_DSP2RMIX_INPUT_3_VOLUME:
case MADERA_DSP2RMIX_INPUT_4_SOURCE:
case MADERA_DSP2RMIX_INPUT_4_VOLUME:
case MADERA_DSP2AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP3LMIX_INPUT_1_SOURCE:
case MADERA_DSP3LMIX_INPUT_1_VOLUME:
case MADERA_DSP3LMIX_INPUT_2_SOURCE:
case MADERA_DSP3LMIX_INPUT_2_VOLUME:
case MADERA_DSP3LMIX_INPUT_3_SOURCE:
case MADERA_DSP3LMIX_INPUT_3_VOLUME:
case MADERA_DSP3LMIX_INPUT_4_SOURCE:
case MADERA_DSP3LMIX_INPUT_4_VOLUME:
case MADERA_DSP3RMIX_INPUT_1_SOURCE:
case MADERA_DSP3RMIX_INPUT_1_VOLUME:
case MADERA_DSP3RMIX_INPUT_2_SOURCE:
case MADERA_DSP3RMIX_INPUT_2_VOLUME:
case MADERA_DSP3RMIX_INPUT_3_SOURCE:
case MADERA_DSP3RMIX_INPUT_3_VOLUME:
case MADERA_DSP3RMIX_INPUT_4_SOURCE:
case MADERA_DSP3RMIX_INPUT_4_VOLUME:
case MADERA_DSP3AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP4LMIX_INPUT_1_SOURCE:
case MADERA_DSP4LMIX_INPUT_1_VOLUME:
case MADERA_DSP4LMIX_INPUT_2_SOURCE:
case MADERA_DSP4LMIX_INPUT_2_VOLUME:
case MADERA_DSP4LMIX_INPUT_3_SOURCE:
case MADERA_DSP4LMIX_INPUT_3_VOLUME:
case MADERA_DSP4LMIX_INPUT_4_SOURCE:
case MADERA_DSP4LMIX_INPUT_4_VOLUME:
case MADERA_DSP4RMIX_INPUT_1_SOURCE:
case MADERA_DSP4RMIX_INPUT_1_VOLUME:
case MADERA_DSP4RMIX_INPUT_2_SOURCE:
case MADERA_DSP4RMIX_INPUT_2_VOLUME:
case MADERA_DSP4RMIX_INPUT_3_SOURCE:
case MADERA_DSP4RMIX_INPUT_3_VOLUME:
case MADERA_DSP4RMIX_INPUT_4_SOURCE:
case MADERA_DSP4RMIX_INPUT_4_VOLUME:
case MADERA_DSP4AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP5LMIX_INPUT_1_SOURCE:
case MADERA_DSP5LMIX_INPUT_1_VOLUME:
case MADERA_DSP5LMIX_INPUT_2_SOURCE:
case MADERA_DSP5LMIX_INPUT_2_VOLUME:
case MADERA_DSP5LMIX_INPUT_3_SOURCE:
case MADERA_DSP5LMIX_INPUT_3_VOLUME:
case MADERA_DSP5LMIX_INPUT_4_SOURCE:
case MADERA_DSP5LMIX_INPUT_4_VOLUME:
case MADERA_DSP5RMIX_INPUT_1_SOURCE:
case MADERA_DSP5RMIX_INPUT_1_VOLUME:
case MADERA_DSP5RMIX_INPUT_2_SOURCE:
case MADERA_DSP5RMIX_INPUT_2_VOLUME:
case MADERA_DSP5RMIX_INPUT_3_SOURCE:
case MADERA_DSP5RMIX_INPUT_3_VOLUME:
case MADERA_DSP5RMIX_INPUT_4_SOURCE:
case MADERA_DSP5RMIX_INPUT_4_VOLUME:
case MADERA_DSP5AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX6MIX_INPUT_1_SOURCE:
case MADERA_ASRC1_1LMIX_INPUT_1_SOURCE:
case MADERA_ASRC1_1RMIX_INPUT_1_SOURCE:
case MADERA_ASRC1_2LMIX_INPUT_1_SOURCE:
case MADERA_ASRC1_2RMIX_INPUT_1_SOURCE:
case MADERA_ASRC2_1LMIX_INPUT_1_SOURCE:
case MADERA_ASRC2_1RMIX_INPUT_1_SOURCE:
case MADERA_ASRC2_2LMIX_INPUT_1_SOURCE:
case MADERA_ASRC2_2RMIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT3MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT4MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT3MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT4MIX_INPUT_1_SOURCE:
case MADERA_ISRC3DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC3DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC3INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC3INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC4DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC4DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC4INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC4INT2MIX_INPUT_1_SOURCE:
case MADERA_DSP6LMIX_INPUT_1_SOURCE:
case MADERA_DSP6LMIX_INPUT_1_VOLUME:
case MADERA_DSP6LMIX_INPUT_2_SOURCE:
case MADERA_DSP6LMIX_INPUT_2_VOLUME:
case MADERA_DSP6LMIX_INPUT_3_SOURCE:
case MADERA_DSP6LMIX_INPUT_3_VOLUME:
case MADERA_DSP6LMIX_INPUT_4_SOURCE:
case MADERA_DSP6LMIX_INPUT_4_VOLUME:
case MADERA_DSP6RMIX_INPUT_1_SOURCE:
case MADERA_DSP6RMIX_INPUT_1_VOLUME:
case MADERA_DSP6RMIX_INPUT_2_SOURCE:
case MADERA_DSP6RMIX_INPUT_2_VOLUME:
case MADERA_DSP6RMIX_INPUT_3_SOURCE:
case MADERA_DSP6RMIX_INPUT_3_VOLUME:
case MADERA_DSP6RMIX_INPUT_4_SOURCE:
case MADERA_DSP6RMIX_INPUT_4_VOLUME:
case MADERA_DSP6AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP7LMIX_INPUT_1_SOURCE:
case MADERA_DSP7LMIX_INPUT_1_VOLUME:
case MADERA_DSP7LMIX_INPUT_2_SOURCE:
case MADERA_DSP7LMIX_INPUT_2_VOLUME:
case MADERA_DSP7LMIX_INPUT_3_SOURCE:
case MADERA_DSP7LMIX_INPUT_3_VOLUME:
case MADERA_DSP7LMIX_INPUT_4_SOURCE:
case MADERA_DSP7LMIX_INPUT_4_VOLUME:
case MADERA_DSP7RMIX_INPUT_1_SOURCE:
case MADERA_DSP7RMIX_INPUT_1_VOLUME:
case MADERA_DSP7RMIX_INPUT_2_SOURCE:
case MADERA_DSP7RMIX_INPUT_2_VOLUME:
case MADERA_DSP7RMIX_INPUT_3_SOURCE:
case MADERA_DSP7RMIX_INPUT_3_VOLUME:
case MADERA_DSP7RMIX_INPUT_4_SOURCE:
case MADERA_DSP7RMIX_INPUT_4_VOLUME:
case MADERA_DSP7AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX6MIX_INPUT_1_SOURCE:
case MADERA_FX_CTRL1:
case MADERA_FX_CTRL2:
case MADERA_EQ1_1 ... MADERA_EQ1_21:
case MADERA_EQ2_1 ... MADERA_EQ2_21:
case MADERA_EQ3_1 ... MADERA_EQ3_21:
case MADERA_EQ4_1 ... MADERA_EQ4_21:
case MADERA_DRC1_CTRL1:
case MADERA_DRC1_CTRL2:
case MADERA_DRC1_CTRL3:
case MADERA_DRC1_CTRL4:
case MADERA_DRC1_CTRL5:
case MADERA_DRC2_CTRL1:
case MADERA_DRC2_CTRL2:
case MADERA_DRC2_CTRL3:
case MADERA_DRC2_CTRL4:
case MADERA_DRC2_CTRL5:
case MADERA_HPLPF1_1:
case MADERA_HPLPF1_2:
case MADERA_HPLPF2_1:
case MADERA_HPLPF2_2:
case MADERA_HPLPF3_1:
case MADERA_HPLPF3_2:
case MADERA_HPLPF4_1:
case MADERA_HPLPF4_2:
case MADERA_ASRC1_ENABLE:
case MADERA_ASRC1_STATUS:
case MADERA_ASRC1_RATE1:
case MADERA_ASRC1_RATE2:
case MADERA_ASRC2_ENABLE:
case MADERA_ASRC2_STATUS:
case MADERA_ASRC2_RATE1:
case MADERA_ASRC2_RATE2:
case MADERA_ISRC_1_CTRL_1:
case MADERA_ISRC_1_CTRL_2:
case MADERA_ISRC_1_CTRL_3:
case MADERA_ISRC_2_CTRL_1:
case MADERA_ISRC_2_CTRL_2:
case MADERA_ISRC_2_CTRL_3:
case MADERA_ISRC_3_CTRL_1:
case MADERA_ISRC_3_CTRL_2:
case MADERA_ISRC_3_CTRL_3:
case MADERA_ISRC_4_CTRL_1:
case MADERA_ISRC_4_CTRL_2:
case MADERA_ISRC_4_CTRL_3:
case MADERA_CLOCK_CONTROL:
case MADERA_ANC_SRC:
case MADERA_DSP_STATUS:
case MADERA_ANC_COEFF_START ... MADERA_ANC_COEFF_END:
case MADERA_FCL_FILTER_CONTROL:
case MADERA_FCL_ADC_REFORMATTER_CONTROL:
case MADERA_FCL_COEFF_START ... MADERA_FCL_COEFF_END:
case MADERA_FCR_FILTER_CONTROL:
case MADERA_FCR_ADC_REFORMATTER_CONTROL:
case MADERA_FCR_COEFF_START ... MADERA_FCR_COEFF_END:
case MADERA_GPIO1_CTRL_1 ... MADERA_GPIO40_CTRL_2:
case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_MASK_1 ... MADERA_IRQ1_MASK_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
case MADERA_INTERRUPT_DEBOUNCE_7:
case MADERA_IRQ1_CTRL:
return true;
default:
return false;
}
}
static bool cs47l85_16bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0:
case MADERA_WRITE_SEQUENCER_CTRL_1:
case MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_HAPTICS_STATUS:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_ASYNC_SAMPLE_RATE_1_STATUS:
case MADERA_ASYNC_SAMPLE_RATE_2_STATUS:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_HP_CTRL_2L:
case MADERA_HP_CTRL_2R:
case MADERA_HP_CTRL_3L:
case MADERA_HP_CTRL_3R:
case MADERA_DCS_HP1L_CONTROL:
case MADERA_DCS_HP1R_CONTROL:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_SLIMBUS_RX_PORT_STATUS:
case MADERA_SLIMBUS_TX_PORT_STATUS:
case MADERA_FX_CTRL2:
case MADERA_ASRC2_STATUS:
case MADERA_ASRC1_STATUS:
case MADERA_CLOCK_CONTROL:
case MADERA_IRQ1_STATUS_1 ...MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
return true;
default:
return false;
}
}
static bool cs47l85_32bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_508:
case CS47L85_OTP_HPDET_CAL_1 ... CS47L85_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_SCRATCH_2:
case MADERA_DSP2_CONFIG_1 ... MADERA_DSP2_SCRATCH_2:
case MADERA_DSP3_CONFIG_1 ... MADERA_DSP3_SCRATCH_2:
case MADERA_DSP4_CONFIG_1 ... MADERA_DSP4_SCRATCH_2:
case MADERA_DSP5_CONFIG_1 ... MADERA_DSP5_SCRATCH_2:
case MADERA_DSP6_CONFIG_1 ... MADERA_DSP6_SCRATCH_2:
case MADERA_DSP7_CONFIG_1 ... MADERA_DSP7_SCRATCH_2:
return true;
default:
return cs47l85_is_adsp_memory(reg);
}
}
static bool cs47l85_32bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_508:
case CS47L85_OTP_HPDET_CAL_1 ... CS47L85_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_SCRATCH_2:
case MADERA_DSP2_CONFIG_1 ... MADERA_DSP2_SCRATCH_2:
case MADERA_DSP3_CONFIG_1 ... MADERA_DSP3_SCRATCH_2:
case MADERA_DSP4_CONFIG_1 ... MADERA_DSP4_SCRATCH_2:
case MADERA_DSP5_CONFIG_1 ... MADERA_DSP5_SCRATCH_2:
case MADERA_DSP6_CONFIG_1 ... MADERA_DSP6_SCRATCH_2:
case MADERA_DSP7_CONFIG_1 ... MADERA_DSP7_SCRATCH_2:
return true;
default:
return cs47l85_is_adsp_memory(reg);
}
}
const struct regmap_config cs47l85_16bit_spi_regmap = {
.name = "cs47l85_16bit",
.reg_bits = 32,
.pad_bits = 16,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = 0x2fff,
.readable_reg = cs47l85_16bit_readable_register,
.volatile_reg = cs47l85_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l85_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l85_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l85_16bit_spi_regmap);
const struct regmap_config cs47l85_16bit_i2c_regmap = {
.name = "cs47l85_16bit",
.reg_bits = 32,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = 0x2fff,
.readable_reg = cs47l85_16bit_readable_register,
.volatile_reg = cs47l85_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l85_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l85_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l85_16bit_i2c_regmap);
const struct regmap_config cs47l85_32bit_spi_regmap = {
.name = "cs47l85_32bit",
.reg_bits = 32,
.reg_stride = 2,
.pad_bits = 16,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_DSP7_SCRATCH_2,
.readable_reg = cs47l85_32bit_readable_register,
.volatile_reg = cs47l85_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l85_32bit_spi_regmap);
const struct regmap_config cs47l85_32bit_i2c_regmap = {
.name = "cs47l85_32bit",
.reg_bits = 32,
.reg_stride = 2,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_DSP7_SCRATCH_2,
.readable_reg = cs47l85_32bit_readable_register,
.volatile_reg = cs47l85_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l85_32bit_i2c_regmap);
| linux-master | drivers/mfd/cs47l85-tables.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MAX10 BMC Platform Management Component Interface (PMCI) based
* interface.
*
* Copyright (C) 2020-2023 Intel Corporation.
*/
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/dfl.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel-m10-bmc.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/regmap.h>
struct m10bmc_pmci_device {
void __iomem *base;
struct intel_m10bmc m10bmc;
struct mutex flash_mutex; /* protects flash_busy and serializes flash read/read */
bool flash_busy;
};
/*
* Intel FGPA indirect register access via hardware controller/bridge.
*/
#define INDIRECT_CMD_OFF 0
#define INDIRECT_CMD_CLR 0
#define INDIRECT_CMD_RD BIT(0)
#define INDIRECT_CMD_WR BIT(1)
#define INDIRECT_CMD_ACK BIT(2)
#define INDIRECT_ADDR_OFF 0x4
#define INDIRECT_RD_OFF 0x8
#define INDIRECT_WR_OFF 0xc
#define INDIRECT_INT_US 1
#define INDIRECT_TIMEOUT_US 10000
struct indirect_ctx {
void __iomem *base;
struct device *dev;
};
static int indirect_clear_cmd(struct indirect_ctx *ctx)
{
unsigned int cmd;
int ret;
writel(INDIRECT_CMD_CLR, ctx->base + INDIRECT_CMD_OFF);
ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, cmd,
cmd == INDIRECT_CMD_CLR,
INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
if (ret)
dev_err(ctx->dev, "timed out waiting clear cmd (residual cmd=0x%x)\n", cmd);
return ret;
}
static int indirect_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct indirect_ctx *ctx = context;
unsigned int cmd, ack, tmpval;
int ret, ret2;
cmd = readl(ctx->base + INDIRECT_CMD_OFF);
if (cmd != INDIRECT_CMD_CLR)
dev_warn(ctx->dev, "residual cmd 0x%x on read entry\n", cmd);
writel(reg, ctx->base + INDIRECT_ADDR_OFF);
writel(INDIRECT_CMD_RD, ctx->base + INDIRECT_CMD_OFF);
ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, ack,
(ack & INDIRECT_CMD_ACK) == INDIRECT_CMD_ACK,
INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
if (ret)
dev_err(ctx->dev, "read timed out on reg 0x%x ack 0x%x\n", reg, ack);
else
tmpval = readl(ctx->base + INDIRECT_RD_OFF);
ret2 = indirect_clear_cmd(ctx);
if (ret)
return ret;
if (ret2)
return ret2;
*val = tmpval;
return 0;
}
static int indirect_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct indirect_ctx *ctx = context;
unsigned int cmd, ack;
int ret, ret2;
cmd = readl(ctx->base + INDIRECT_CMD_OFF);
if (cmd != INDIRECT_CMD_CLR)
dev_warn(ctx->dev, "residual cmd 0x%x on write entry\n", cmd);
writel(val, ctx->base + INDIRECT_WR_OFF);
writel(reg, ctx->base + INDIRECT_ADDR_OFF);
writel(INDIRECT_CMD_WR, ctx->base + INDIRECT_CMD_OFF);
ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, ack,
(ack & INDIRECT_CMD_ACK) == INDIRECT_CMD_ACK,
INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
if (ret)
dev_err(ctx->dev, "write timed out on reg 0x%x ack 0x%x\n", reg, ack);
ret2 = indirect_clear_cmd(ctx);
if (ret)
return ret;
return ret2;
}
static void pmci_write_fifo(void __iomem *base, const u32 *buf, size_t count)
{
while (count--)
writel(*buf++, base);
}
static void pmci_read_fifo(void __iomem *base, u32 *buf, size_t count)
{
while (count--)
*buf++ = readl(base);
}
static u32 pmci_get_write_space(struct m10bmc_pmci_device *pmci)
{
u32 val;
int ret;
ret = read_poll_timeout(readl, val,
FIELD_GET(M10BMC_N6000_FLASH_FIFO_SPACE, val) ==
M10BMC_N6000_FIFO_MAX_WORDS,
M10BMC_FLASH_INT_US, M10BMC_FLASH_TIMEOUT_US,
false, pmci->base + M10BMC_N6000_FLASH_CTRL);
if (ret == -ETIMEDOUT)
return 0;
return FIELD_GET(M10BMC_N6000_FLASH_FIFO_SPACE, val) * M10BMC_N6000_FIFO_WORD_SIZE;
}
static int pmci_flash_bulk_write(struct intel_m10bmc *m10bmc, const u8 *buf, u32 size)
{
struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
u32 blk_size, offset = 0, write_count;
while (size) {
blk_size = min(pmci_get_write_space(pmci), size);
if (blk_size == 0) {
dev_err(m10bmc->dev, "get FIFO available size fail\n");
return -EIO;
}
if (size < M10BMC_N6000_FIFO_WORD_SIZE)
break;
write_count = blk_size / M10BMC_N6000_FIFO_WORD_SIZE;
pmci_write_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO,
(u32 *)(buf + offset), write_count);
size -= blk_size;
offset += blk_size;
}
/* Handle remainder (less than M10BMC_N6000_FIFO_WORD_SIZE bytes) */
if (size) {
u32 tmp = 0;
memcpy(&tmp, buf + offset, size);
pmci_write_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO, &tmp, 1);
}
return 0;
}
static int pmci_flash_bulk_read(struct intel_m10bmc *m10bmc, u8 *buf, u32 addr, u32 size)
{
struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
u32 blk_size, offset = 0, val, full_read_count, read_count;
int ret;
while (size) {
blk_size = min_t(u32, size, M10BMC_N6000_READ_BLOCK_SIZE);
full_read_count = blk_size / M10BMC_N6000_FIFO_WORD_SIZE;
read_count = full_read_count;
if (full_read_count * M10BMC_N6000_FIFO_WORD_SIZE < blk_size)
read_count++;
writel(addr + offset, pmci->base + M10BMC_N6000_FLASH_ADDR);
writel(FIELD_PREP(M10BMC_N6000_FLASH_READ_COUNT, read_count) |
M10BMC_N6000_FLASH_RD_MODE,
pmci->base + M10BMC_N6000_FLASH_CTRL);
ret = readl_poll_timeout((pmci->base + M10BMC_N6000_FLASH_CTRL), val,
!(val & M10BMC_N6000_FLASH_BUSY),
M10BMC_FLASH_INT_US, M10BMC_FLASH_TIMEOUT_US);
if (ret) {
dev_err(m10bmc->dev, "read timed out on reading flash 0x%xn", val);
return ret;
}
pmci_read_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO,
(u32 *)(buf + offset), full_read_count);
size -= blk_size;
offset += blk_size;
if (full_read_count < read_count)
break;
writel(0, pmci->base + M10BMC_N6000_FLASH_CTRL);
}
/* Handle remainder (less than M10BMC_N6000_FIFO_WORD_SIZE bytes) */
if (size) {
u32 tmp;
pmci_read_fifo(pmci->base + M10BMC_N6000_FLASH_FIFO, &tmp, 1);
memcpy(buf + offset, &tmp, size);
writel(0, pmci->base + M10BMC_N6000_FLASH_CTRL);
}
return 0;
}
static int m10bmc_pmci_set_flash_host_mux(struct intel_m10bmc *m10bmc, bool request)
{
u32 ctrl;
int ret;
ret = regmap_update_bits(m10bmc->regmap, M10BMC_N6000_FLASH_MUX_CTRL,
M10BMC_N6000_FLASH_HOST_REQUEST,
FIELD_PREP(M10BMC_N6000_FLASH_HOST_REQUEST, request));
if (ret)
return ret;
return regmap_read_poll_timeout(m10bmc->regmap,
M10BMC_N6000_FLASH_MUX_CTRL, ctrl,
request ?
(get_flash_mux(ctrl) == M10BMC_N6000_FLASH_MUX_HOST) :
(get_flash_mux(ctrl) != M10BMC_N6000_FLASH_MUX_HOST),
M10BMC_FLASH_INT_US, M10BMC_FLASH_TIMEOUT_US);
}
static int m10bmc_pmci_flash_read(struct intel_m10bmc *m10bmc, u8 *buf, u32 addr, u32 size)
{
struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
int ret, ret2;
mutex_lock(&pmci->flash_mutex);
if (pmci->flash_busy) {
ret = -EBUSY;
goto unlock;
}
ret = m10bmc_pmci_set_flash_host_mux(m10bmc, true);
if (ret)
goto mux_fail;
ret = pmci_flash_bulk_read(m10bmc, buf, addr, size);
mux_fail:
ret2 = m10bmc_pmci_set_flash_host_mux(m10bmc, false);
unlock:
mutex_unlock(&pmci->flash_mutex);
if (ret)
return ret;
return ret2;
}
static int m10bmc_pmci_flash_write(struct intel_m10bmc *m10bmc, const u8 *buf, u32 offset, u32 size)
{
struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
int ret;
mutex_lock(&pmci->flash_mutex);
WARN_ON_ONCE(!pmci->flash_busy);
/* On write, firmware manages flash MUX */
ret = pmci_flash_bulk_write(m10bmc, buf + offset, size);
mutex_unlock(&pmci->flash_mutex);
return ret;
}
static int m10bmc_pmci_flash_lock(struct intel_m10bmc *m10bmc)
{
struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
int ret = 0;
mutex_lock(&pmci->flash_mutex);
if (pmci->flash_busy) {
ret = -EBUSY;
goto unlock;
}
pmci->flash_busy = true;
unlock:
mutex_unlock(&pmci->flash_mutex);
return ret;
}
static void m10bmc_pmci_flash_unlock(struct intel_m10bmc *m10bmc)
{
struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
mutex_lock(&pmci->flash_mutex);
WARN_ON_ONCE(!pmci->flash_busy);
pmci->flash_busy = false;
mutex_unlock(&pmci->flash_mutex);
}
static const struct intel_m10bmc_flash_bulk_ops m10bmc_pmci_flash_bulk_ops = {
.read = m10bmc_pmci_flash_read,
.write = m10bmc_pmci_flash_write,
.lock_write = m10bmc_pmci_flash_lock,
.unlock_write = m10bmc_pmci_flash_unlock,
};
static const struct regmap_range m10bmc_pmci_regmap_range[] = {
regmap_reg_range(M10BMC_N6000_SYS_BASE, M10BMC_N6000_SYS_END),
};
static const struct regmap_access_table m10bmc_pmci_access_table = {
.yes_ranges = m10bmc_pmci_regmap_range,
.n_yes_ranges = ARRAY_SIZE(m10bmc_pmci_regmap_range),
};
static struct regmap_config m10bmc_pmci_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.wr_table = &m10bmc_pmci_access_table,
.rd_table = &m10bmc_pmci_access_table,
.reg_read = &indirect_reg_read,
.reg_write = &indirect_reg_write,
.max_register = M10BMC_N6000_SYS_END,
};
static struct mfd_cell m10bmc_pmci_n6000_bmc_subdevs[] = {
{ .name = "n6000bmc-hwmon" },
{ .name = "n6000bmc-sec-update" },
};
static const struct m10bmc_csr_map m10bmc_n6000_csr_map = {
.base = M10BMC_N6000_SYS_BASE,
.build_version = M10BMC_N6000_BUILD_VER,
.fw_version = NIOS2_N6000_FW_VERSION,
.mac_low = M10BMC_N6000_MAC_LOW,
.mac_high = M10BMC_N6000_MAC_HIGH,
.doorbell = M10BMC_N6000_DOORBELL,
.auth_result = M10BMC_N6000_AUTH_RESULT,
.bmc_prog_addr = M10BMC_N6000_BMC_PROG_ADDR,
.bmc_reh_addr = M10BMC_N6000_BMC_REH_ADDR,
.bmc_magic = M10BMC_N6000_BMC_PROG_MAGIC,
.sr_prog_addr = M10BMC_N6000_SR_PROG_ADDR,
.sr_reh_addr = M10BMC_N6000_SR_REH_ADDR,
.sr_magic = M10BMC_N6000_SR_PROG_MAGIC,
.pr_prog_addr = M10BMC_N6000_PR_PROG_ADDR,
.pr_reh_addr = M10BMC_N6000_PR_REH_ADDR,
.pr_magic = M10BMC_N6000_PR_PROG_MAGIC,
.rsu_update_counter = M10BMC_N6000_STAGING_FLASH_COUNT,
};
static const struct intel_m10bmc_platform_info m10bmc_pmci_n6000 = {
.cells = m10bmc_pmci_n6000_bmc_subdevs,
.n_cells = ARRAY_SIZE(m10bmc_pmci_n6000_bmc_subdevs),
.csr_map = &m10bmc_n6000_csr_map,
};
static int m10bmc_pmci_probe(struct dfl_device *ddev)
{
struct device *dev = &ddev->dev;
struct m10bmc_pmci_device *pmci;
struct indirect_ctx *ctx;
int ret;
pmci = devm_kzalloc(dev, sizeof(*pmci), GFP_KERNEL);
if (!pmci)
return -ENOMEM;
pmci->m10bmc.flash_bulk_ops = &m10bmc_pmci_flash_bulk_ops;
pmci->m10bmc.dev = dev;
pmci->base = devm_ioremap_resource(dev, &ddev->mmio_res);
if (IS_ERR(pmci->base))
return PTR_ERR(pmci->base);
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
mutex_init(&pmci->flash_mutex);
ctx->base = pmci->base + M10BMC_N6000_INDIRECT_BASE;
ctx->dev = dev;
indirect_clear_cmd(ctx);
pmci->m10bmc.regmap = devm_regmap_init(dev, NULL, ctx, &m10bmc_pmci_regmap_config);
if (IS_ERR(pmci->m10bmc.regmap)) {
ret = PTR_ERR(pmci->m10bmc.regmap);
goto destroy_mutex;
}
ret = m10bmc_dev_init(&pmci->m10bmc, &m10bmc_pmci_n6000);
if (ret)
goto destroy_mutex;
return 0;
destroy_mutex:
mutex_destroy(&pmci->flash_mutex);
return ret;
}
static void m10bmc_pmci_remove(struct dfl_device *ddev)
{
struct intel_m10bmc *m10bmc = dev_get_drvdata(&ddev->dev);
struct m10bmc_pmci_device *pmci = container_of(m10bmc, struct m10bmc_pmci_device, m10bmc);
mutex_destroy(&pmci->flash_mutex);
}
#define FME_FEATURE_ID_M10BMC_PMCI 0x12
static const struct dfl_device_id m10bmc_pmci_ids[] = {
{ FME_ID, FME_FEATURE_ID_M10BMC_PMCI },
{ }
};
MODULE_DEVICE_TABLE(dfl, m10bmc_pmci_ids);
static struct dfl_driver m10bmc_pmci_driver = {
.drv = {
.name = "intel-m10-bmc",
.dev_groups = m10bmc_dev_groups,
},
.id_table = m10bmc_pmci_ids,
.probe = m10bmc_pmci_probe,
.remove = m10bmc_pmci_remove,
};
module_dfl_driver(m10bmc_pmci_driver);
MODULE_DESCRIPTION("MAX10 BMC PMCI-based interface");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(INTEL_M10_BMC_CORE);
| linux-master | drivers/mfd/intel-m10-bmc-pmci.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* lpc_ich.c - LPC interface for Intel ICH
*
* LPC bridge function of the Intel ICH contains many other
* functional units, such as Interrupt controllers, Timers,
* Power Management, System Management, GPIO, RTC, and LPC
* Configuration Registers.
*
* This driver is derived from lpc_sch.
*
* Copyright (c) 2017, 2021-2022 Intel Corporation
* Copyright (c) 2011 Extreme Engineering Solution, Inc.
* Author: Aaron Sierra <[email protected]>
*
* This driver supports the following I/O Controller hubs:
* (See the intel documentation on http://developer.intel.com.)
* document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
* document number 290687-002, 298242-027: 82801BA (ICH2)
* document number 290733-003, 290739-013: 82801CA (ICH3-S)
* document number 290716-001, 290718-007: 82801CAM (ICH3-M)
* document number 290744-001, 290745-025: 82801DB (ICH4)
* document number 252337-001, 252663-008: 82801DBM (ICH4-M)
* document number 273599-001, 273645-002: 82801E (C-ICH)
* document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
* document number 300641-004, 300884-013: 6300ESB
* document number 301473-002, 301474-026: 82801F (ICH6)
* document number 313082-001, 313075-006: 631xESB, 632xESB
* document number 307013-003, 307014-024: 82801G (ICH7)
* document number 322896-001, 322897-001: NM10
* document number 313056-003, 313057-017: 82801H (ICH8)
* document number 316972-004, 316973-012: 82801I (ICH9)
* document number 319973-002, 319974-002: 82801J (ICH10)
* document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
* document number 320066-003, 320257-008: EP80597 (IICH)
* document number 324645-001, 324646-001: Cougar Point (CPT)
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/acpi.h>
#include <linux/pci.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/mfd/core.h>
#include <linux/mfd/lpc_ich.h>
#include <linux/platform_data/itco_wdt.h>
#include <linux/platform_data/x86/p2sb.h>
#define ACPIBASE 0x40
#define ACPIBASE_GPE_OFF 0x28
#define ACPIBASE_GPE_END 0x2f
#define ACPIBASE_SMI_OFF 0x30
#define ACPIBASE_SMI_END 0x33
#define ACPIBASE_PMC_OFF 0x08
#define ACPIBASE_PMC_END 0x0c
#define ACPIBASE_TCO_OFF 0x60
#define ACPIBASE_TCO_END 0x7f
#define ACPICTRL_PMCBASE 0x44
#define ACPIBASE_GCS_OFF 0x3410
#define ACPIBASE_GCS_END 0x3414
#define SPIBASE_BYT 0x54
#define SPIBASE_BYT_SZ 512
#define SPIBASE_BYT_EN BIT(1)
#define BYT_BCR 0xfc
#define BYT_BCR_WPD BIT(0)
#define SPIBASE_LPT 0x3800
#define SPIBASE_LPT_SZ 512
#define BCR 0xdc
#define BCR_WPD BIT(0)
#define GPIOBASE_ICH0 0x58
#define GPIOCTRL_ICH0 0x5C
#define GPIOBASE_ICH6 0x48
#define GPIOCTRL_ICH6 0x4C
#define RCBABASE 0xf0
#define wdt_io_res(i) wdt_res(0, i)
#define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
#define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
struct lpc_ich_priv {
int chipset;
int abase; /* ACPI base */
int actrl_pbase; /* ACPI control or PMC base */
int gbase; /* GPIO base */
int gctrl; /* GPIO control */
int abase_save; /* Cached ACPI base value */
int actrl_pbase_save; /* Cached ACPI control or PMC base value */
int gctrl_save; /* Cached GPIO control value */
};
static struct resource wdt_ich_res[] = {
/* ACPI - TCO */
{
.flags = IORESOURCE_IO,
},
/* ACPI - SMI */
{
.flags = IORESOURCE_IO,
},
/* GCS or PMC */
{
.flags = IORESOURCE_MEM,
},
};
static struct resource gpio_ich_res[] = {
/* GPIO */
{
.flags = IORESOURCE_IO,
},
/* ACPI - GPE0 */
{
.flags = IORESOURCE_IO,
},
};
static struct resource intel_spi_res[] = {
{
.flags = IORESOURCE_MEM,
}
};
static struct mfd_cell lpc_ich_wdt_cell = {
.name = "iTCO_wdt",
.num_resources = ARRAY_SIZE(wdt_ich_res),
.resources = wdt_ich_res,
.ignore_resource_conflicts = true,
};
static struct mfd_cell lpc_ich_gpio_cell = {
.name = "gpio_ich",
.num_resources = ARRAY_SIZE(gpio_ich_res),
.resources = gpio_ich_res,
.ignore_resource_conflicts = true,
};
#define APL_GPIO_NORTH 0
#define APL_GPIO_NORTHWEST 1
#define APL_GPIO_WEST 2
#define APL_GPIO_SOUTHWEST 3
#define APL_GPIO_NR_DEVICES 4
/* Offset data for Apollo Lake GPIO controllers */
static resource_size_t apl_gpio_offsets[APL_GPIO_NR_DEVICES] = {
[APL_GPIO_NORTH] = 0xc50000,
[APL_GPIO_NORTHWEST] = 0xc40000,
[APL_GPIO_WEST] = 0xc70000,
[APL_GPIO_SOUTHWEST] = 0xc00000,
};
#define APL_GPIO_RESOURCE_SIZE 0x1000
#define APL_GPIO_IRQ 14
static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
[APL_GPIO_NORTH] = {
DEFINE_RES_MEM(0, 0),
DEFINE_RES_IRQ(APL_GPIO_IRQ),
},
[APL_GPIO_NORTHWEST] = {
DEFINE_RES_MEM(0, 0),
DEFINE_RES_IRQ(APL_GPIO_IRQ),
},
[APL_GPIO_WEST] = {
DEFINE_RES_MEM(0, 0),
DEFINE_RES_IRQ(APL_GPIO_IRQ),
},
[APL_GPIO_SOUTHWEST] = {
DEFINE_RES_MEM(0, 0),
DEFINE_RES_IRQ(APL_GPIO_IRQ),
},
};
static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
[APL_GPIO_NORTH] = {
.name = "apollolake-pinctrl",
.id = APL_GPIO_NORTH,
.num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]),
.resources = apl_gpio_resources[APL_GPIO_NORTH],
.ignore_resource_conflicts = true,
},
[APL_GPIO_NORTHWEST] = {
.name = "apollolake-pinctrl",
.id = APL_GPIO_NORTHWEST,
.num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]),
.resources = apl_gpio_resources[APL_GPIO_NORTHWEST],
.ignore_resource_conflicts = true,
},
[APL_GPIO_WEST] = {
.name = "apollolake-pinctrl",
.id = APL_GPIO_WEST,
.num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]),
.resources = apl_gpio_resources[APL_GPIO_WEST],
.ignore_resource_conflicts = true,
},
[APL_GPIO_SOUTHWEST] = {
.name = "apollolake-pinctrl",
.id = APL_GPIO_SOUTHWEST,
.num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]),
.resources = apl_gpio_resources[APL_GPIO_SOUTHWEST],
.ignore_resource_conflicts = true,
},
};
static struct mfd_cell lpc_ich_spi_cell = {
.name = "intel-spi",
.num_resources = ARRAY_SIZE(intel_spi_res),
.resources = intel_spi_res,
.ignore_resource_conflicts = true,
};
/* chipset related info */
enum lpc_chipsets {
LPC_ICH = 0, /* ICH */
LPC_ICH0, /* ICH0 */
LPC_ICH2, /* ICH2 */
LPC_ICH2M, /* ICH2-M */
LPC_ICH3, /* ICH3-S */
LPC_ICH3M, /* ICH3-M */
LPC_ICH4, /* ICH4 */
LPC_ICH4M, /* ICH4-M */
LPC_CICH, /* C-ICH */
LPC_ICH5, /* ICH5 & ICH5R */
LPC_6300ESB, /* 6300ESB */
LPC_ICH6, /* ICH6 & ICH6R */
LPC_ICH6M, /* ICH6-M */
LPC_ICH6W, /* ICH6W & ICH6RW */
LPC_631XESB, /* 631xESB/632xESB */
LPC_ICH7, /* ICH7 & ICH7R */
LPC_ICH7DH, /* ICH7DH */
LPC_ICH7M, /* ICH7-M & ICH7-U */
LPC_ICH7MDH, /* ICH7-M DH */
LPC_NM10, /* NM10 */
LPC_ICH8, /* ICH8 & ICH8R */
LPC_ICH8DH, /* ICH8DH */
LPC_ICH8DO, /* ICH8DO */
LPC_ICH8M, /* ICH8M */
LPC_ICH8ME, /* ICH8M-E */
LPC_ICH9, /* ICH9 */
LPC_ICH9R, /* ICH9R */
LPC_ICH9DH, /* ICH9DH */
LPC_ICH9DO, /* ICH9DO */
LPC_ICH9M, /* ICH9M */
LPC_ICH9ME, /* ICH9M-E */
LPC_ICH10, /* ICH10 */
LPC_ICH10R, /* ICH10R */
LPC_ICH10D, /* ICH10D */
LPC_ICH10DO, /* ICH10DO */
LPC_PCH, /* PCH Desktop Full Featured */
LPC_PCHM, /* PCH Mobile Full Featured */
LPC_P55, /* P55 */
LPC_PM55, /* PM55 */
LPC_H55, /* H55 */
LPC_QM57, /* QM57 */
LPC_H57, /* H57 */
LPC_HM55, /* HM55 */
LPC_Q57, /* Q57 */
LPC_HM57, /* HM57 */
LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
LPC_QS57, /* QS57 */
LPC_3400, /* 3400 */
LPC_3420, /* 3420 */
LPC_3450, /* 3450 */
LPC_EP80579, /* EP80579 */
LPC_CPT, /* Cougar Point */
LPC_CPTD, /* Cougar Point Desktop */
LPC_CPTM, /* Cougar Point Mobile */
LPC_PBG, /* Patsburg */
LPC_DH89XXCC, /* DH89xxCC */
LPC_PPT, /* Panther Point */
LPC_LPT, /* Lynx Point */
LPC_LPT_LP, /* Lynx Point-LP */
LPC_WBG, /* Wellsburg */
LPC_AVN, /* Avoton SoC */
LPC_BAYTRAIL, /* Bay Trail SoC */
LPC_COLETO, /* Coleto Creek */
LPC_WPT_LP, /* Wildcat Point-LP */
LPC_BRASWELL, /* Braswell SoC */
LPC_LEWISBURG, /* Lewisburg */
LPC_9S, /* 9 Series */
LPC_APL, /* Apollo Lake SoC */
LPC_GLK, /* Gemini Lake SoC */
LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
};
static struct lpc_ich_info lpc_chipset_info[] = {
[LPC_ICH] = {
.name = "ICH",
.iTCO_version = 1,
},
[LPC_ICH0] = {
.name = "ICH0",
.iTCO_version = 1,
},
[LPC_ICH2] = {
.name = "ICH2",
.iTCO_version = 1,
},
[LPC_ICH2M] = {
.name = "ICH2-M",
.iTCO_version = 1,
},
[LPC_ICH3] = {
.name = "ICH3-S",
.iTCO_version = 1,
},
[LPC_ICH3M] = {
.name = "ICH3-M",
.iTCO_version = 1,
},
[LPC_ICH4] = {
.name = "ICH4",
.iTCO_version = 1,
},
[LPC_ICH4M] = {
.name = "ICH4-M",
.iTCO_version = 1,
},
[LPC_CICH] = {
.name = "C-ICH",
.iTCO_version = 1,
},
[LPC_ICH5] = {
.name = "ICH5 or ICH5R",
.iTCO_version = 1,
},
[LPC_6300ESB] = {
.name = "6300ESB",
.iTCO_version = 1,
},
[LPC_ICH6] = {
.name = "ICH6 or ICH6R",
.iTCO_version = 2,
.gpio_version = ICH_V6_GPIO,
},
[LPC_ICH6M] = {
.name = "ICH6-M",
.iTCO_version = 2,
.gpio_version = ICH_V6_GPIO,
},
[LPC_ICH6W] = {
.name = "ICH6W or ICH6RW",
.iTCO_version = 2,
.gpio_version = ICH_V6_GPIO,
},
[LPC_631XESB] = {
.name = "631xESB/632xESB",
.iTCO_version = 2,
.gpio_version = ICH_V6_GPIO,
},
[LPC_ICH7] = {
.name = "ICH7 or ICH7R",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_ICH7DH] = {
.name = "ICH7DH",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_ICH7M] = {
.name = "ICH7-M or ICH7-U",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_ICH7MDH] = {
.name = "ICH7-M DH",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_NM10] = {
.name = "NM10",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_ICH8] = {
.name = "ICH8 or ICH8R",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_ICH8DH] = {
.name = "ICH8DH",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_ICH8DO] = {
.name = "ICH8DO",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_ICH8M] = {
.name = "ICH8M",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_ICH8ME] = {
.name = "ICH8M-E",
.iTCO_version = 2,
.gpio_version = ICH_V7_GPIO,
},
[LPC_ICH9] = {
.name = "ICH9",
.iTCO_version = 2,
.gpio_version = ICH_V9_GPIO,
},
[LPC_ICH9R] = {
.name = "ICH9R",
.iTCO_version = 2,
.gpio_version = ICH_V9_GPIO,
},
[LPC_ICH9DH] = {
.name = "ICH9DH",
.iTCO_version = 2,
.gpio_version = ICH_V9_GPIO,
},
[LPC_ICH9DO] = {
.name = "ICH9DO",
.iTCO_version = 2,
.gpio_version = ICH_V9_GPIO,
},
[LPC_ICH9M] = {
.name = "ICH9M",
.iTCO_version = 2,
.gpio_version = ICH_V9_GPIO,
},
[LPC_ICH9ME] = {
.name = "ICH9M-E",
.iTCO_version = 2,
.gpio_version = ICH_V9_GPIO,
},
[LPC_ICH10] = {
.name = "ICH10",
.iTCO_version = 2,
.gpio_version = ICH_V10CONS_GPIO,
},
[LPC_ICH10R] = {
.name = "ICH10R",
.iTCO_version = 2,
.gpio_version = ICH_V10CONS_GPIO,
},
[LPC_ICH10D] = {
.name = "ICH10D",
.iTCO_version = 2,
.gpio_version = ICH_V10CORP_GPIO,
},
[LPC_ICH10DO] = {
.name = "ICH10DO",
.iTCO_version = 2,
.gpio_version = ICH_V10CORP_GPIO,
},
[LPC_PCH] = {
.name = "PCH Desktop Full Featured",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_PCHM] = {
.name = "PCH Mobile Full Featured",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_P55] = {
.name = "P55",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_PM55] = {
.name = "PM55",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_H55] = {
.name = "H55",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_QM57] = {
.name = "QM57",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_H57] = {
.name = "H57",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_HM55] = {
.name = "HM55",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_Q57] = {
.name = "Q57",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_HM57] = {
.name = "HM57",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_PCHMSFF] = {
.name = "PCH Mobile SFF Full Featured",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_QS57] = {
.name = "QS57",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_3400] = {
.name = "3400",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_3420] = {
.name = "3420",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_3450] = {
.name = "3450",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_EP80579] = {
.name = "EP80579",
.iTCO_version = 2,
},
[LPC_CPT] = {
.name = "Cougar Point",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_CPTD] = {
.name = "Cougar Point Desktop",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_CPTM] = {
.name = "Cougar Point Mobile",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_PBG] = {
.name = "Patsburg",
.iTCO_version = 2,
},
[LPC_DH89XXCC] = {
.name = "DH89xxCC",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_PPT] = {
.name = "Panther Point",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_LPT] = {
.name = "Lynx Point",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
.spi_type = INTEL_SPI_LPT,
},
[LPC_LPT_LP] = {
.name = "Lynx Point_LP",
.iTCO_version = 2,
.spi_type = INTEL_SPI_LPT,
},
[LPC_WBG] = {
.name = "Wellsburg",
.iTCO_version = 2,
},
[LPC_AVN] = {
.name = "Avoton SoC",
.iTCO_version = 3,
.gpio_version = AVOTON_GPIO,
.spi_type = INTEL_SPI_BYT,
},
[LPC_BAYTRAIL] = {
.name = "Bay Trail SoC",
.iTCO_version = 3,
.spi_type = INTEL_SPI_BYT,
},
[LPC_COLETO] = {
.name = "Coleto Creek",
.iTCO_version = 2,
},
[LPC_WPT_LP] = {
.name = "Wildcat Point_LP",
.iTCO_version = 2,
.spi_type = INTEL_SPI_LPT,
},
[LPC_BRASWELL] = {
.name = "Braswell SoC",
.iTCO_version = 3,
.spi_type = INTEL_SPI_BYT,
},
[LPC_LEWISBURG] = {
.name = "Lewisburg",
.iTCO_version = 2,
},
[LPC_9S] = {
.name = "9 Series",
.iTCO_version = 2,
.gpio_version = ICH_V5_GPIO,
},
[LPC_APL] = {
.name = "Apollo Lake SoC",
.iTCO_version = 5,
.spi_type = INTEL_SPI_BXT,
},
[LPC_GLK] = {
.name = "Gemini Lake SoC",
.spi_type = INTEL_SPI_BXT,
},
[LPC_COUGARMOUNTAIN] = {
.name = "Cougar Mountain SoC",
.iTCO_version = 3,
},
};
/*
* This data only exists for exporting the supported PCI ids
* via MODULE_DEVICE_TABLE. We do not actually register a
* pci_driver, because the I/O Controller Hub has also other
* functions that probably will be registered by other drivers.
*/
static const struct pci_device_id lpc_ich_ids[] = {
{ PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
{ PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
{ PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
{ PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
{ PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
{ PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
{ PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
{ PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
{ PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
{ PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
{ PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
{ PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
{ PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
{ PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
{ PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
{ PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
{ PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
{ PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
{ PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
{ PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
{ PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
{ PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
{ PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
{ PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
{ PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
{ PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
{ PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
{ PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
{ PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
{ PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
{ PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
{ PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
{ PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
{ PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
{ PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
{ PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
{ PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
{ PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
{ PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
{ PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
{ PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
{ PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
{ PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
{ PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
{ PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
{ PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
{ PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
{ PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
{ PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
{ PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
{ PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
{ PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
{ PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
{ PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
{ PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
{ PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
{ PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
{ PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
{ PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
{ PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
{ PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
{ PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
{ PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
{ PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
{ PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
{ PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
{ PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
{ PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
{ PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
{ PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
{ PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
{ PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
{ PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
{ PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
{ PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
{ PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
{ PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
{ PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
{ PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
{ PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
{ PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
{ PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
{ PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
{ PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
{ PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
{ PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
{ PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
{ PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
{ PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
{ PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
{ PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
{ PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
{ PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
{ PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
{ 0, }, /* End of list */
};
MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
static void lpc_ich_restore_config_space(struct pci_dev *dev)
{
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
if (priv->abase_save >= 0) {
pci_write_config_byte(dev, priv->abase, priv->abase_save);
priv->abase_save = -1;
}
if (priv->actrl_pbase_save >= 0) {
pci_write_config_byte(dev, priv->actrl_pbase,
priv->actrl_pbase_save);
priv->actrl_pbase_save = -1;
}
if (priv->gctrl_save >= 0) {
pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
priv->gctrl_save = -1;
}
}
static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
{
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
u8 reg_save;
switch (lpc_chipset_info[priv->chipset].iTCO_version) {
case 3:
/*
* Some chipsets (eg Avoton) enable the ACPI space in the
* ACPI BASE register.
*/
pci_read_config_byte(dev, priv->abase, ®_save);
pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
priv->abase_save = reg_save;
break;
default:
/*
* Most chipsets enable the ACPI space in the ACPI control
* register.
*/
pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
priv->actrl_pbase_save = reg_save;
break;
}
}
static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
{
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
u8 reg_save;
pci_read_config_byte(dev, priv->gctrl, ®_save);
pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
priv->gctrl_save = reg_save;
}
static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
{
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
u8 reg_save;
pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
priv->actrl_pbase_save = reg_save;
}
static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
{
struct itco_wdt_platform_data *pdata;
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
struct lpc_ich_info *info;
struct mfd_cell *cell = &lpc_ich_wdt_cell;
pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
info = &lpc_chipset_info[priv->chipset];
pdata->version = info->iTCO_version;
strscpy(pdata->name, info->name, sizeof(pdata->name));
cell->platform_data = pdata;
cell->pdata_size = sizeof(*pdata);
return 0;
}
static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
{
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
struct mfd_cell *cell = &lpc_ich_gpio_cell;
cell->platform_data = &lpc_chipset_info[priv->chipset];
cell->pdata_size = sizeof(struct lpc_ich_info);
}
/*
* We don't check for resource conflict globally. There are 2 or 3 independent
* GPIO groups and it's enough to have access to one of these to instantiate
* the device.
*/
static int lpc_ich_check_conflict_gpio(struct resource *res)
{
int ret;
u8 use_gpio = 0;
if (resource_size(res) >= 0x50 &&
!acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
use_gpio |= 1 << 2;
if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
use_gpio |= 1 << 1;
ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
if (!ret)
use_gpio |= 1 << 0;
return use_gpio ? use_gpio : ret;
}
static int lpc_ich_init_gpio(struct pci_dev *dev)
{
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
u32 base_addr_cfg;
u32 base_addr;
int ret;
bool acpi_conflict = false;
struct resource *res;
/* Setup power management base register */
pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
base_addr = base_addr_cfg & 0x0000ff80;
if (!base_addr) {
dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
lpc_ich_gpio_cell.num_resources--;
goto gpe0_done;
}
res = &gpio_ich_res[ICH_RES_GPE0];
res->start = base_addr + ACPIBASE_GPE_OFF;
res->end = base_addr + ACPIBASE_GPE_END;
ret = acpi_check_resource_conflict(res);
if (ret) {
/*
* This isn't fatal for the GPIO, but we have to make sure that
* the platform_device subsystem doesn't see this resource
* or it will register an invalid region.
*/
lpc_ich_gpio_cell.num_resources--;
acpi_conflict = true;
} else {
lpc_ich_enable_acpi_space(dev);
}
gpe0_done:
/* Setup GPIO base register */
pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
base_addr = base_addr_cfg & 0x0000ff80;
if (!base_addr) {
dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
ret = -ENODEV;
goto gpio_done;
}
/* Older devices provide fewer GPIO and have a smaller resource size. */
res = &gpio_ich_res[ICH_RES_GPIO];
res->start = base_addr;
switch (lpc_chipset_info[priv->chipset].gpio_version) {
case ICH_V5_GPIO:
case ICH_V10CORP_GPIO:
res->end = res->start + 128 - 1;
break;
default:
res->end = res->start + 64 - 1;
break;
}
ret = lpc_ich_check_conflict_gpio(res);
if (ret < 0) {
/* this isn't necessarily fatal for the GPIO */
acpi_conflict = true;
goto gpio_done;
}
lpc_chipset_info[priv->chipset].use_gpio = ret;
lpc_ich_enable_gpio_space(dev);
lpc_ich_finalize_gpio_cell(dev);
ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
&lpc_ich_gpio_cell, 1, NULL, 0, NULL);
gpio_done:
if (acpi_conflict)
pr_warn("Resource conflict(s) found affecting %s\n",
lpc_ich_gpio_cell.name);
return ret;
}
static int lpc_ich_init_wdt(struct pci_dev *dev)
{
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
u32 base_addr_cfg;
u32 base_addr;
int ret;
struct resource *res;
/* If we have ACPI based watchdog use that instead */
if (acpi_has_watchdog())
return -ENODEV;
/* Setup power management base register */
pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
base_addr = base_addr_cfg & 0x0000ff80;
if (!base_addr) {
dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
ret = -ENODEV;
goto wdt_done;
}
res = wdt_io_res(ICH_RES_IO_TCO);
res->start = base_addr + ACPIBASE_TCO_OFF;
res->end = base_addr + ACPIBASE_TCO_END;
res = wdt_io_res(ICH_RES_IO_SMI);
res->start = base_addr + ACPIBASE_SMI_OFF;
res->end = base_addr + ACPIBASE_SMI_END;
lpc_ich_enable_acpi_space(dev);
/*
* iTCO v2:
* Get the Memory-Mapped GCS register. To get access to it
* we have to read RCBA from PCI Config space 0xf0 and use
* it as base. GCS = RCBA + ICH6_GCS(0x3410).
*
* iTCO v3:
* Get the Power Management Configuration register. To get access
* to it we have to read the PMC BASE from config space and address
* the register at offset 0x8.
*/
if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
/* Don't register iomem for TCO ver 1 */
lpc_ich_wdt_cell.num_resources--;
} else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
base_addr = base_addr_cfg & 0xffffc000;
if (!(base_addr_cfg & 1)) {
dev_notice(&dev->dev, "RCBA is disabled by "
"hardware/BIOS, device disabled\n");
ret = -ENODEV;
goto wdt_done;
}
res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
res->start = base_addr + ACPIBASE_GCS_OFF;
res->end = base_addr + ACPIBASE_GCS_END;
} else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
lpc_ich_enable_pmc_space(dev);
pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
base_addr = base_addr_cfg & 0xfffffe00;
res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
res->start = base_addr + ACPIBASE_PMC_OFF;
res->end = base_addr + ACPIBASE_PMC_END;
}
ret = lpc_ich_finalize_wdt_cell(dev);
if (ret)
goto wdt_done;
ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
&lpc_ich_wdt_cell, 1, NULL, 0, NULL);
wdt_done:
return ret;
}
static int lpc_ich_init_pinctrl(struct pci_dev *dev)
{
struct resource base;
unsigned int i;
int ret;
/* Check, if GPIO has been exported as an ACPI device */
if (acpi_dev_present("INT3452", NULL, -1))
return -EEXIST;
ret = p2sb_bar(dev->bus, 0, &base);
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) {
struct resource *mem = &apl_gpio_resources[i][0];
resource_size_t offset = apl_gpio_offsets[i];
/* Fill MEM resource */
mem->start = base.start + offset;
mem->end = base.start + offset + APL_GPIO_RESOURCE_SIZE - 1;
mem->flags = base.flags;
}
return mfd_add_devices(&dev->dev, 0, apl_gpio_devices,
ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL);
}
static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
{
u32 val;
val = readl(base + BYT_BCR);
if (!(val & BYT_BCR_WPD)) {
val |= BYT_BCR_WPD;
writel(val, base + BYT_BCR);
val = readl(base + BYT_BCR);
}
return val & BYT_BCR_WPD;
}
static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn)
{
u32 bcr;
pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
if (!(bcr & BCR_WPD)) {
bcr |= BCR_WPD;
pci_bus_write_config_dword(bus, devfn, BCR, bcr);
pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
}
return bcr & BCR_WPD;
}
static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)
{
struct pci_dev *pdev = data;
return lpc_ich_set_writeable(pdev->bus, pdev->devfn);
}
static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)
{
struct pci_dev *pdev = data;
return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2));
}
static int lpc_ich_init_spi(struct pci_dev *dev)
{
struct lpc_ich_priv *priv = pci_get_drvdata(dev);
struct resource *res = &intel_spi_res[0];
struct intel_spi_boardinfo *info;
u32 spi_base, rcba;
int ret;
info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->type = lpc_chipset_info[priv->chipset].spi_type;
switch (info->type) {
case INTEL_SPI_BYT:
pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
if (spi_base & SPIBASE_BYT_EN) {
res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
res->end = res->start + SPIBASE_BYT_SZ - 1;
info->set_writeable = lpc_ich_byt_set_writeable;
}
break;
case INTEL_SPI_LPT:
pci_read_config_dword(dev, RCBABASE, &rcba);
if (rcba & 1) {
spi_base = round_down(rcba, SPIBASE_LPT_SZ);
res->start = spi_base + SPIBASE_LPT;
res->end = res->start + SPIBASE_LPT_SZ - 1;
info->set_writeable = lpc_ich_lpt_set_writeable;
info->data = dev;
}
break;
case INTEL_SPI_BXT:
/*
* The P2SB is hidden by BIOS and we need to unhide it in
* order to read BAR of the SPI flash device. Once that is
* done we hide it again.
*/
ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res);
if (ret)
return ret;
info->set_writeable = lpc_ich_bxt_set_writeable;
info->data = dev;
break;
default:
return -EINVAL;
}
if (!res->start)
return -ENODEV;
lpc_ich_spi_cell.platform_data = info;
lpc_ich_spi_cell.pdata_size = sizeof(*info);
return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
&lpc_ich_spi_cell, 1, NULL, 0, NULL);
}
static int lpc_ich_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
struct lpc_ich_priv *priv;
int ret;
bool cell_added = false;
priv = devm_kzalloc(&dev->dev,
sizeof(struct lpc_ich_priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->chipset = id->driver_data;
priv->actrl_pbase_save = -1;
priv->abase_save = -1;
priv->abase = ACPIBASE;
priv->actrl_pbase = ACPICTRL_PMCBASE;
priv->gctrl_save = -1;
if (priv->chipset <= LPC_ICH5) {
priv->gbase = GPIOBASE_ICH0;
priv->gctrl = GPIOCTRL_ICH0;
} else {
priv->gbase = GPIOBASE_ICH6;
priv->gctrl = GPIOCTRL_ICH6;
}
pci_set_drvdata(dev, priv);
if (lpc_chipset_info[priv->chipset].iTCO_version) {
ret = lpc_ich_init_wdt(dev);
if (!ret)
cell_added = true;
}
if (lpc_chipset_info[priv->chipset].gpio_version) {
ret = lpc_ich_init_gpio(dev);
if (!ret)
cell_added = true;
}
if (priv->chipset == LPC_APL) {
ret = lpc_ich_init_pinctrl(dev);
if (!ret)
cell_added = true;
}
if (lpc_chipset_info[priv->chipset].spi_type) {
ret = lpc_ich_init_spi(dev);
if (!ret)
cell_added = true;
}
/*
* We only care if at least one or none of the cells registered
* successfully.
*/
if (!cell_added) {
dev_warn(&dev->dev, "No MFD cells added\n");
lpc_ich_restore_config_space(dev);
return -ENODEV;
}
return 0;
}
static void lpc_ich_remove(struct pci_dev *dev)
{
mfd_remove_devices(&dev->dev);
lpc_ich_restore_config_space(dev);
}
static struct pci_driver lpc_ich_driver = {
.name = "lpc_ich",
.id_table = lpc_ich_ids,
.probe = lpc_ich_probe,
.remove = lpc_ich_remove,
};
module_pci_driver(lpc_ich_driver);
MODULE_AUTHOR("Aaron Sierra <[email protected]>");
MODULE_DESCRIPTION("LPC interface for Intel ICH");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/lpc_ich.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Khadas System control Microcontroller
*
* Copyright (C) 2020 BayLibre SAS
*
* Author(s): Neil Armstrong <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/khadas-mcu.h>
#include <linux/module.h>
#include <linux/regmap.h>
static bool khadas_mcu_reg_volatile(struct device *dev, unsigned int reg)
{
if (reg >= KHADAS_MCU_USER_DATA_0_REG &&
reg < KHADAS_MCU_PWR_OFF_CMD_REG)
return true;
switch (reg) {
case KHADAS_MCU_PWR_OFF_CMD_REG:
case KHADAS_MCU_PASSWD_START_REG:
case KHADAS_MCU_CHECK_VEN_PASSWD_REG:
case KHADAS_MCU_CHECK_USER_PASSWD_REG:
case KHADAS_MCU_WOL_INIT_START_REG:
case KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG:
return true;
default:
return false;
}
}
static bool khadas_mcu_reg_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case KHADAS_MCU_PASSWD_VEN_0_REG:
case KHADAS_MCU_PASSWD_VEN_1_REG:
case KHADAS_MCU_PASSWD_VEN_2_REG:
case KHADAS_MCU_PASSWD_VEN_3_REG:
case KHADAS_MCU_PASSWD_VEN_4_REG:
case KHADAS_MCU_PASSWD_VEN_5_REG:
case KHADAS_MCU_MAC_0_REG:
case KHADAS_MCU_MAC_1_REG:
case KHADAS_MCU_MAC_2_REG:
case KHADAS_MCU_MAC_3_REG:
case KHADAS_MCU_MAC_4_REG:
case KHADAS_MCU_MAC_5_REG:
case KHADAS_MCU_USID_0_REG:
case KHADAS_MCU_USID_1_REG:
case KHADAS_MCU_USID_2_REG:
case KHADAS_MCU_USID_3_REG:
case KHADAS_MCU_USID_4_REG:
case KHADAS_MCU_USID_5_REG:
case KHADAS_MCU_VERSION_0_REG:
case KHADAS_MCU_VERSION_1_REG:
case KHADAS_MCU_DEVICE_NO_0_REG:
case KHADAS_MCU_DEVICE_NO_1_REG:
case KHADAS_MCU_FACTORY_TEST_REG:
case KHADAS_MCU_SHUTDOWN_NORMAL_STATUS_REG:
return false;
default:
return true;
}
}
static const struct regmap_config khadas_mcu_regmap_config = {
.reg_bits = 8,
.reg_stride = 1,
.val_bits = 8,
.max_register = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG,
.volatile_reg = khadas_mcu_reg_volatile,
.writeable_reg = khadas_mcu_reg_writeable,
.cache_type = REGCACHE_RBTREE,
};
static struct mfd_cell khadas_mcu_fan_cells[] = {
/* VIM1/2 Rev13+ and VIM3 only */
{ .name = "khadas-mcu-fan-ctrl", },
};
static struct mfd_cell khadas_mcu_cells[] = {
{ .name = "khadas-mcu-user-mem", },
};
static int khadas_mcu_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct khadas_mcu *ddata;
int ret;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
i2c_set_clientdata(client, ddata);
ddata->dev = dev;
ddata->regmap = devm_regmap_init_i2c(client, &khadas_mcu_regmap_config);
if (IS_ERR(ddata->regmap)) {
ret = PTR_ERR(ddata->regmap);
dev_err(dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
khadas_mcu_cells,
ARRAY_SIZE(khadas_mcu_cells),
NULL, 0, NULL);
if (ret)
return ret;
if (of_property_present(dev->of_node, "#cooling-cells"))
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
khadas_mcu_fan_cells,
ARRAY_SIZE(khadas_mcu_fan_cells),
NULL, 0, NULL);
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id khadas_mcu_of_match[] = {
{ .compatible = "khadas,mcu", },
{},
};
MODULE_DEVICE_TABLE(of, khadas_mcu_of_match);
#endif
static struct i2c_driver khadas_mcu_driver = {
.driver = {
.name = "khadas-mcu-core",
.of_match_table = of_match_ptr(khadas_mcu_of_match),
},
.probe = khadas_mcu_probe,
};
module_i2c_driver(khadas_mcu_driver);
MODULE_DESCRIPTION("Khadas MCU core driver");
MODULE_AUTHOR("Neil Armstrong <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/khadas-mcu.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019, Linaro Limited
#include <linux/clk.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/wcd934x/registers.h>
#include <linux/mfd/wcd934x/wcd934x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slimbus.h>
#define WCD934X_REGMAP_IRQ_REG(_irq, _off, _mask) \
[_irq] = { \
.reg_offset = (_off), \
.mask = (_mask), \
.type = { \
.type_reg_offset = (_off), \
.types_supported = IRQ_TYPE_EDGE_BOTH, \
.type_reg_mask = (_mask), \
.type_level_low_val = (_mask), \
.type_level_high_val = (_mask), \
.type_falling_val = 0, \
.type_rising_val = 0, \
}, \
}
static const struct mfd_cell wcd934x_devices[] = {
{
.name = "wcd934x-codec",
}, {
.name = "wcd934x-gpio",
.of_compatible = "qcom,wcd9340-gpio",
}, {
.name = "wcd934x-soundwire",
.of_compatible = "qcom,soundwire-v1.3.0",
},
};
static const struct regmap_irq wcd934x_irqs[] = {
WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_SLIMBUS, 0, BIT(0)),
WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_HPH_PA_OCPL_FAULT, 0, BIT(2)),
WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_HPH_PA_OCPR_FAULT, 0, BIT(3)),
WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_SW_DET, 1, BIT(0)),
WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_ELECT_INS_REM_DET, 1, BIT(1)),
WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_BUTTON_PRESS_DET, 1, BIT(2)),
WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET, 1, BIT(3)),
WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 1, BIT(4)),
WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_SOUNDWIRE, 2, BIT(4)),
};
static const unsigned int wcd934x_config_regs[] = {
WCD934X_INTR_LEVEL0,
};
static const struct regmap_irq_chip wcd934x_regmap_irq_chip = {
.name = "wcd934x_irq",
.status_base = WCD934X_INTR_PIN1_STATUS0,
.mask_base = WCD934X_INTR_PIN1_MASK0,
.ack_base = WCD934X_INTR_PIN1_CLEAR0,
.num_regs = 4,
.irqs = wcd934x_irqs,
.num_irqs = ARRAY_SIZE(wcd934x_irqs),
.config_base = wcd934x_config_regs,
.num_config_bases = ARRAY_SIZE(wcd934x_config_regs),
.num_config_regs = 4,
.set_type_config = regmap_irq_set_type_config_simple,
};
static bool wcd934x_is_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WCD934X_INTR_PIN1_STATUS0...WCD934X_INTR_PIN2_CLEAR3:
case WCD934X_SWR_AHB_BRIDGE_RD_DATA_0:
case WCD934X_SWR_AHB_BRIDGE_RD_DATA_1:
case WCD934X_SWR_AHB_BRIDGE_RD_DATA_2:
case WCD934X_SWR_AHB_BRIDGE_RD_DATA_3:
case WCD934X_SWR_AHB_BRIDGE_ACCESS_STATUS:
case WCD934X_ANA_MBHC_RESULT_3:
case WCD934X_ANA_MBHC_RESULT_2:
case WCD934X_ANA_MBHC_RESULT_1:
case WCD934X_ANA_MBHC_MECH:
case WCD934X_ANA_MBHC_ELECT:
case WCD934X_ANA_MBHC_ZDET:
case WCD934X_ANA_MICB2:
case WCD934X_ANA_RCO:
case WCD934X_ANA_BIAS:
return true;
default:
return false;
}
};
static const struct regmap_range_cfg wcd934x_ranges[] = {
{ .name = "WCD934X",
.range_min = 0x0,
.range_max = WCD934X_MAX_REGISTER,
.selector_reg = WCD934X_SEL_REGISTER,
.selector_mask = WCD934X_SEL_MASK,
.selector_shift = WCD934X_SEL_SHIFT,
.window_start = WCD934X_WINDOW_START,
.window_len = WCD934X_WINDOW_LENGTH,
},
};
static struct regmap_config wcd934x_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.max_register = 0xffff,
.can_multi_write = true,
.ranges = wcd934x_ranges,
.num_ranges = ARRAY_SIZE(wcd934x_ranges),
.volatile_reg = wcd934x_is_volatile_register,
};
static int wcd934x_bring_up(struct wcd934x_ddata *ddata)
{
struct regmap *regmap = ddata->regmap;
u16 id_minor, id_major;
int ret;
ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
(u8 *)&id_minor, sizeof(u16));
if (ret)
return ret;
ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2,
(u8 *)&id_major, sizeof(u16));
if (ret)
return ret;
dev_info(ddata->dev, "WCD934x chip id major 0x%x, minor 0x%x\n",
id_major, id_minor);
regmap_write(regmap, WCD934X_CODEC_RPM_RST_CTL, 0x01);
regmap_write(regmap, WCD934X_SIDO_NEW_VOUT_A_STARTUP, 0x19);
regmap_write(regmap, WCD934X_SIDO_NEW_VOUT_D_STARTUP, 0x15);
/* Add 1msec delay for VOUT to settle */
usleep_range(1000, 1100);
regmap_write(regmap, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
regmap_write(regmap, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
regmap_write(regmap, WCD934X_CODEC_RPM_RST_CTL, 0x3);
regmap_write(regmap, WCD934X_CODEC_RPM_RST_CTL, 0x7);
regmap_write(regmap, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
return 0;
}
static int wcd934x_slim_status_up(struct slim_device *sdev)
{
struct device *dev = &sdev->dev;
struct wcd934x_ddata *ddata;
int ret;
ddata = dev_get_drvdata(dev);
ddata->regmap = regmap_init_slimbus(sdev, &wcd934x_regmap_config);
if (IS_ERR(ddata->regmap)) {
dev_err(dev, "Error allocating slim regmap\n");
return PTR_ERR(ddata->regmap);
}
ret = wcd934x_bring_up(ddata);
if (ret) {
dev_err(dev, "Failed to bring up WCD934X: err = %d\n", ret);
return ret;
}
ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq,
IRQF_TRIGGER_HIGH, 0,
&wcd934x_regmap_irq_chip,
&ddata->irq_data);
if (ret) {
dev_err(dev, "Failed to add IRQ chip: err = %d\n", ret);
return ret;
}
ret = mfd_add_devices(dev, PLATFORM_DEVID_AUTO, wcd934x_devices,
ARRAY_SIZE(wcd934x_devices), NULL, 0, NULL);
if (ret) {
dev_err(dev, "Failed to add child devices: err = %d\n",
ret);
return ret;
}
return ret;
}
static int wcd934x_slim_status(struct slim_device *sdev,
enum slim_device_status status)
{
switch (status) {
case SLIM_DEVICE_STATUS_UP:
return wcd934x_slim_status_up(sdev);
case SLIM_DEVICE_STATUS_DOWN:
mfd_remove_devices(&sdev->dev);
break;
default:
return -EINVAL;
}
return 0;
}
static int wcd934x_slim_probe(struct slim_device *sdev)
{
struct device *dev = &sdev->dev;
struct device_node *np = dev->of_node;
struct wcd934x_ddata *ddata;
struct gpio_desc *reset_gpio;
int ret;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
ddata->irq = of_irq_get(np, 0);
if (ddata->irq < 0)
return dev_err_probe(ddata->dev, ddata->irq,
"Failed to get IRQ\n");
ddata->extclk = devm_clk_get(dev, "extclk");
if (IS_ERR(ddata->extclk))
return dev_err_probe(dev, PTR_ERR(ddata->extclk),
"Failed to get extclk");
ddata->supplies[0].supply = "vdd-buck";
ddata->supplies[1].supply = "vdd-buck-sido";
ddata->supplies[2].supply = "vdd-tx";
ddata->supplies[3].supply = "vdd-rx";
ddata->supplies[4].supply = "vdd-io";
ret = regulator_bulk_get(dev, WCD934X_MAX_SUPPLY, ddata->supplies);
if (ret)
return dev_err_probe(dev, ret, "Failed to get supplies\n");
ret = regulator_bulk_enable(WCD934X_MAX_SUPPLY, ddata->supplies);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable supplies\n");
/*
* For WCD934X, it takes about 600us for the Vout_A and
* Vout_D to be ready after BUCK_SIDO is powered up.
* SYS_RST_N shouldn't be pulled high during this time
*/
usleep_range(600, 650);
reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(reset_gpio)) {
ret = dev_err_probe(dev, PTR_ERR(reset_gpio),
"Failed to get reset gpio\n");
goto err_disable_regulators;
}
msleep(20);
gpiod_set_value(reset_gpio, 1);
msleep(20);
ddata->dev = dev;
dev_set_drvdata(dev, ddata);
return 0;
err_disable_regulators:
regulator_bulk_disable(WCD934X_MAX_SUPPLY, ddata->supplies);
return ret;
}
static void wcd934x_slim_remove(struct slim_device *sdev)
{
struct wcd934x_ddata *ddata = dev_get_drvdata(&sdev->dev);
regulator_bulk_disable(WCD934X_MAX_SUPPLY, ddata->supplies);
mfd_remove_devices(&sdev->dev);
}
static const struct slim_device_id wcd934x_slim_id[] = {
{ SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9340,
SLIM_DEV_IDX_WCD9340, SLIM_DEV_INSTANCE_ID_WCD9340 },
{}
};
static struct slim_driver wcd934x_slim_driver = {
.driver = {
.name = "wcd934x-slim",
},
.probe = wcd934x_slim_probe,
.remove = wcd934x_slim_remove,
.device_status = wcd934x_slim_status,
.id_table = wcd934x_slim_id,
};
module_slim_driver(wcd934x_slim_driver);
MODULE_DESCRIPTION("WCD934X slim driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("slim:217:250:*");
MODULE_AUTHOR("Srinivas Kandagatla <[email protected]>");
| linux-master | drivers/mfd/wcd934x.c |
// SPDX-License-Identifier: GPL-2.0
/*
* CS42L43 core driver
*
* Copyright (C) 2022-2023 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*/
#include <linux/bitops.h>
#include <linux/build_bug.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/firmware.h>
#include <linux/jiffies.h>
#include <linux/mfd/core.h>
#include <linux/mfd/cs42l43-regs.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw.h>
#include "cs42l43.h"
#define CS42L43_RESET_DELAY 20
#define CS42L43_SDW_ATTACH_TIMEOUT 500
#define CS42L43_SDW_DETACH_TIMEOUT 100
#define CS42L43_MCU_BOOT_STAGE1 1
#define CS42L43_MCU_BOOT_STAGE2 2
#define CS42L43_MCU_BOOT_STAGE3 3
#define CS42L43_MCU_BOOT_STAGE4 4
#define CS42L43_MCU_POLL 5000
#define CS42L43_MCU_CMD_TIMEOUT 20000
#define CS42L43_MCU_UPDATE_FORMAT 3
#define CS42L43_MCU_UPDATE_OFFSET 0x100000
#define CS42L43_MCU_UPDATE_TIMEOUT 500000
#define CS42L43_MCU_UPDATE_RETRIES 5
#define CS42L43_MCU_SUPPORTED_REV 0x2105
#define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV 0x2200
#define CS42L43_MCU_SUPPORTED_BIOS_REV 0x0001
#define CS42L43_VDDP_DELAY 50
#define CS42L43_VDDD_DELAY 1000
#define CS42L43_AUTOSUSPEND_TIME 250
struct cs42l43_patch_header {
__le16 version;
__le16 size;
u8 reserved;
u8 secure;
__le16 bss_size;
__le32 apply_addr;
__le32 checksum;
__le32 sha;
__le16 swrev;
__le16 patchid;
__le16 ipxid;
__le16 romver;
__le32 load_addr;
} __packed;
static const struct reg_sequence cs42l43_reva_patch[] = {
{ 0x4000, 0x00000055 },
{ 0x4000, 0x000000AA },
{ 0x10084, 0x00000000 },
{ 0x1741C, 0x00CD2000 },
{ 0x1718C, 0x00000003 },
{ 0x4000, 0x00000000 },
{ CS42L43_CCM_BLK_CLK_CONTROL, 0x00000002 },
{ CS42L43_HPPATHVOL, 0x011B011B },
{ CS42L43_OSC_DIV_SEL, 0x00000001 },
{ CS42L43_DACCNFG2, 0x00000005 },
{ CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 },
{ CS42L43_RELID, 0x0000000F },
};
const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
{ CS42L43_DRV_CTRL1, 0x000186C0 },
{ CS42L43_DRV_CTRL3, 0x286DB018 },
{ CS42L43_DRV_CTRL4, 0x000006D8 },
{ CS42L43_DRV_CTRL_5, 0x136C00C0 },
{ CS42L43_GPIO_CTRL1, 0x00000707 },
{ CS42L43_GPIO_CTRL2, 0x00000000 },
{ CS42L43_GPIO_FN_SEL, 0x00000000 },
{ CS42L43_MCLK_SRC_SEL, 0x00000000 },
{ CS42L43_SAMPLE_RATE1, 0x00000003 },
{ CS42L43_SAMPLE_RATE2, 0x00000003 },
{ CS42L43_SAMPLE_RATE3, 0x00000003 },
{ CS42L43_SAMPLE_RATE4, 0x00000003 },
{ CS42L43_PLL_CONTROL, 0x00000000 },
{ CS42L43_FS_SELECT1, 0x00000000 },
{ CS42L43_FS_SELECT2, 0x00000000 },
{ CS42L43_FS_SELECT3, 0x00000000 },
{ CS42L43_FS_SELECT4, 0x00000000 },
{ CS42L43_PDM_CONTROL, 0x00000000 },
{ CS42L43_ASP_CLK_CONFIG1, 0x00010001 },
{ CS42L43_ASP_CLK_CONFIG2, 0x00000000 },
{ CS42L43_OSC_DIV_SEL, 0x00000001 },
{ CS42L43_ADC_B_CTRL1, 0x00000000 },
{ CS42L43_ADC_B_CTRL2, 0x00000000 },
{ CS42L43_DECIM_HPF_WNF_CTRL1, 0x00000001 },
{ CS42L43_DECIM_HPF_WNF_CTRL2, 0x00000001 },
{ CS42L43_DECIM_HPF_WNF_CTRL3, 0x00000001 },
{ CS42L43_DECIM_HPF_WNF_CTRL4, 0x00000001 },
{ CS42L43_DMIC_PDM_CTRL, 0x00000000 },
{ CS42L43_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 },
{ CS42L43_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 },
{ CS42L43_INTP_VOLUME_CTRL1, 0x00000180 },
{ CS42L43_INTP_VOLUME_CTRL2, 0x00000180 },
{ CS42L43_AMP1_2_VOL_RAMP, 0x00000022 },
{ CS42L43_ASP_CTRL, 0x00000004 },
{ CS42L43_ASP_FSYNC_CTRL1, 0x000000FA },
{ CS42L43_ASP_FSYNC_CTRL2, 0x00000001 },
{ CS42L43_ASP_FSYNC_CTRL3, 0x00000000 },
{ CS42L43_ASP_FSYNC_CTRL4, 0x000001F4 },
{ CS42L43_ASP_DATA_CTRL, 0x0000003A },
{ CS42L43_ASP_RX_EN, 0x00000000 },
{ CS42L43_ASP_TX_EN, 0x00000000 },
{ CS42L43_ASP_RX_CH1_CTRL, 0x00170001 },
{ CS42L43_ASP_RX_CH2_CTRL, 0x00170031 },
{ CS42L43_ASP_RX_CH3_CTRL, 0x00170061 },
{ CS42L43_ASP_RX_CH4_CTRL, 0x00170091 },
{ CS42L43_ASP_RX_CH5_CTRL, 0x001700C1 },
{ CS42L43_ASP_RX_CH6_CTRL, 0x001700F1 },
{ CS42L43_ASP_TX_CH1_CTRL, 0x00170001 },
{ CS42L43_ASP_TX_CH2_CTRL, 0x00170031 },
{ CS42L43_ASP_TX_CH3_CTRL, 0x00170061 },
{ CS42L43_ASP_TX_CH4_CTRL, 0x00170091 },
{ CS42L43_ASP_TX_CH5_CTRL, 0x001700C1 },
{ CS42L43_ASP_TX_CH6_CTRL, 0x001700F1 },
{ CS42L43_ASPTX1_INPUT, 0x00800000 },
{ CS42L43_ASPTX2_INPUT, 0x00800000 },
{ CS42L43_ASPTX3_INPUT, 0x00800000 },
{ CS42L43_ASPTX4_INPUT, 0x00800000 },
{ CS42L43_ASPTX5_INPUT, 0x00800000 },
{ CS42L43_ASPTX6_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP1_CH1_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP1_CH2_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP1_CH3_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP1_CH4_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP2_CH1_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP2_CH2_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP3_CH1_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP3_CH2_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP4_CH1_INPUT, 0x00800000 },
{ CS42L43_SWIRE_DP4_CH2_INPUT, 0x00800000 },
{ CS42L43_ASRC_INT1_INPUT1, 0x00800000 },
{ CS42L43_ASRC_INT2_INPUT1, 0x00800000 },
{ CS42L43_ASRC_INT3_INPUT1, 0x00800000 },
{ CS42L43_ASRC_INT4_INPUT1, 0x00800000 },
{ CS42L43_ASRC_DEC1_INPUT1, 0x00800000 },
{ CS42L43_ASRC_DEC2_INPUT1, 0x00800000 },
{ CS42L43_ASRC_DEC3_INPUT1, 0x00800000 },
{ CS42L43_ASRC_DEC4_INPUT1, 0x00800000 },
{ CS42L43_ISRC1INT1_INPUT1, 0x00800000 },
{ CS42L43_ISRC1INT2_INPUT1, 0x00800000 },
{ CS42L43_ISRC1DEC1_INPUT1, 0x00800000 },
{ CS42L43_ISRC1DEC2_INPUT1, 0x00800000 },
{ CS42L43_ISRC2INT1_INPUT1, 0x00800000 },
{ CS42L43_ISRC2INT2_INPUT1, 0x00800000 },
{ CS42L43_ISRC2DEC1_INPUT1, 0x00800000 },
{ CS42L43_ISRC2DEC2_INPUT1, 0x00800000 },
{ CS42L43_EQ1MIX_INPUT1, 0x00800000 },
{ CS42L43_EQ1MIX_INPUT2, 0x00800000 },
{ CS42L43_EQ1MIX_INPUT3, 0x00800000 },
{ CS42L43_EQ1MIX_INPUT4, 0x00800000 },
{ CS42L43_EQ2MIX_INPUT1, 0x00800000 },
{ CS42L43_EQ2MIX_INPUT2, 0x00800000 },
{ CS42L43_EQ2MIX_INPUT3, 0x00800000 },
{ CS42L43_EQ2MIX_INPUT4, 0x00800000 },
{ CS42L43_SPDIF1_INPUT1, 0x00800000 },
{ CS42L43_SPDIF2_INPUT1, 0x00800000 },
{ CS42L43_AMP1MIX_INPUT1, 0x00800000 },
{ CS42L43_AMP1MIX_INPUT2, 0x00800000 },
{ CS42L43_AMP1MIX_INPUT3, 0x00800000 },
{ CS42L43_AMP1MIX_INPUT4, 0x00800000 },
{ CS42L43_AMP2MIX_INPUT1, 0x00800000 },
{ CS42L43_AMP2MIX_INPUT2, 0x00800000 },
{ CS42L43_AMP2MIX_INPUT3, 0x00800000 },
{ CS42L43_AMP2MIX_INPUT4, 0x00800000 },
{ CS42L43_AMP3MIX_INPUT1, 0x00800000 },
{ CS42L43_AMP3MIX_INPUT2, 0x00800000 },
{ CS42L43_AMP3MIX_INPUT3, 0x00800000 },
{ CS42L43_AMP3MIX_INPUT4, 0x00800000 },
{ CS42L43_AMP4MIX_INPUT1, 0x00800000 },
{ CS42L43_AMP4MIX_INPUT2, 0x00800000 },
{ CS42L43_AMP4MIX_INPUT3, 0x00800000 },
{ CS42L43_AMP4MIX_INPUT4, 0x00800000 },
{ CS42L43_ASRC_INT_ENABLES, 0x00000100 },
{ CS42L43_ASRC_DEC_ENABLES, 0x00000100 },
{ CS42L43_PDNCNTL, 0x00000000 },
{ CS42L43_RINGSENSE_DEB_CTRL, 0x0000001B },
{ CS42L43_TIPSENSE_DEB_CTRL, 0x0000001B },
{ CS42L43_HS2, 0x050106F3 },
{ CS42L43_STEREO_MIC_CTRL, 0x00000000 },
{ CS42L43_STEREO_MIC_CLAMP_CTRL, 0x00000001 },
{ CS42L43_BLOCK_EN2, 0x00000000 },
{ CS42L43_BLOCK_EN3, 0x00000000 },
{ CS42L43_BLOCK_EN4, 0x00000000 },
{ CS42L43_BLOCK_EN5, 0x00000000 },
{ CS42L43_BLOCK_EN6, 0x00000000 },
{ CS42L43_BLOCK_EN7, 0x00000000 },
{ CS42L43_BLOCK_EN8, 0x00000000 },
{ CS42L43_BLOCK_EN9, 0x00000000 },
{ CS42L43_BLOCK_EN10, 0x00000000 },
{ CS42L43_BLOCK_EN11, 0x00000000 },
{ CS42L43_TONE_CH1_CTRL, 0x00000000 },
{ CS42L43_TONE_CH2_CTRL, 0x00000000 },
{ CS42L43_MIC_DETECT_CONTROL_1, 0x00000003 },
{ CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL, 0x02000003 },
{ CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 },
{ CS42L43_ISRC1_CTRL, 0x00000000 },
{ CS42L43_ISRC2_CTRL, 0x00000000 },
{ CS42L43_CTRL_REG, 0x00000006 },
{ CS42L43_FDIV_FRAC, 0x40000000 },
{ CS42L43_CAL_RATIO, 0x00000080 },
{ CS42L43_SPI_CLK_CONFIG1, 0x00000000 },
{ CS42L43_SPI_CONFIG1, 0x00000000 },
{ CS42L43_SPI_CONFIG2, 0x00000000 },
{ CS42L43_SPI_CONFIG3, 0x00000001 },
{ CS42L43_SPI_CONFIG4, 0x00000000 },
{ CS42L43_TRAN_CONFIG3, 0x00000000 },
{ CS42L43_TRAN_CONFIG4, 0x00000000 },
{ CS42L43_TRAN_CONFIG5, 0x00000000 },
{ CS42L43_TRAN_CONFIG6, 0x00000000 },
{ CS42L43_TRAN_CONFIG7, 0x00000000 },
{ CS42L43_TRAN_CONFIG8, 0x00000000 },
{ CS42L43_DACCNFG1, 0x00000008 },
{ CS42L43_DACCNFG2, 0x00000005 },
{ CS42L43_HPPATHVOL, 0x011B011B },
{ CS42L43_PGAVOL, 0x00003470 },
{ CS42L43_LOADDETENA, 0x00000000 },
{ CS42L43_CTRL, 0x00000037 },
{ CS42L43_COEFF_DATA_IN0, 0x00000000 },
{ CS42L43_COEFF_RD_WR0, 0x00000000 },
{ CS42L43_START_EQZ0, 0x00000000 },
{ CS42L43_MUTE_EQ_IN0, 0x00000000 },
{ CS42L43_DECIM_MASK, 0x0000000F },
{ CS42L43_EQ_MIX_MASK, 0x0000000F },
{ CS42L43_ASP_MASK, 0x000000FF },
{ CS42L43_PLL_MASK, 0x00000003 },
{ CS42L43_SOFT_MASK, 0x0000FFFF },
{ CS42L43_SWIRE_MASK, 0x00007FFF },
{ CS42L43_MSM_MASK, 0x00000FFF },
{ CS42L43_ACC_DET_MASK, 0x00000FFF },
{ CS42L43_I2C_TGT_MASK, 0x00000003 },
{ CS42L43_SPI_MSTR_MASK, 0x00000007 },
{ CS42L43_SW_TO_SPI_BRIDGE_MASK, 0x00000001 },
{ CS42L43_OTP_MASK, 0x00000007 },
{ CS42L43_CLASS_D_AMP_MASK, 0x00003FFF },
{ CS42L43_GPIO_INT_MASK, 0x0000003F },
{ CS42L43_ASRC_MASK, 0x0000000F },
{ CS42L43_HPOUT_MASK, 0x00000003 },
};
EXPORT_SYMBOL_NS_GPL(cs42l43_reg_default, MFD_CS42L43);
bool cs42l43_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L43_DEVID:
case CS42L43_REVID:
case CS42L43_RELID:
case CS42L43_SFT_RESET:
case CS42L43_DRV_CTRL1:
case CS42L43_DRV_CTRL3:
case CS42L43_DRV_CTRL4:
case CS42L43_DRV_CTRL_5:
case CS42L43_GPIO_CTRL1:
case CS42L43_GPIO_CTRL2:
case CS42L43_GPIO_STS:
case CS42L43_GPIO_FN_SEL:
case CS42L43_MCLK_SRC_SEL:
case CS42L43_SAMPLE_RATE1 ... CS42L43_SAMPLE_RATE4:
case CS42L43_PLL_CONTROL:
case CS42L43_FS_SELECT1 ... CS42L43_FS_SELECT4:
case CS42L43_PDM_CONTROL:
case CS42L43_ASP_CLK_CONFIG1 ... CS42L43_ASP_CLK_CONFIG2:
case CS42L43_OSC_DIV_SEL:
case CS42L43_ADC_B_CTRL1 ... CS42L43_ADC_B_CTRL2:
case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4:
case CS42L43_DMIC_PDM_CTRL:
case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4:
case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2:
case CS42L43_AMP1_2_VOL_RAMP:
case CS42L43_ASP_CTRL:
case CS42L43_ASP_FSYNC_CTRL1 ... CS42L43_ASP_FSYNC_CTRL4:
case CS42L43_ASP_DATA_CTRL:
case CS42L43_ASP_RX_EN ... CS42L43_ASP_TX_EN:
case CS42L43_ASP_RX_CH1_CTRL ... CS42L43_ASP_RX_CH6_CTRL:
case CS42L43_ASP_TX_CH1_CTRL ... CS42L43_ASP_TX_CH6_CTRL:
case CS42L43_OTP_REVISION_ID:
case CS42L43_ASPTX1_INPUT:
case CS42L43_ASPTX2_INPUT:
case CS42L43_ASPTX3_INPUT:
case CS42L43_ASPTX4_INPUT:
case CS42L43_ASPTX5_INPUT:
case CS42L43_ASPTX6_INPUT:
case CS42L43_SWIRE_DP1_CH1_INPUT:
case CS42L43_SWIRE_DP1_CH2_INPUT:
case CS42L43_SWIRE_DP1_CH3_INPUT:
case CS42L43_SWIRE_DP1_CH4_INPUT:
case CS42L43_SWIRE_DP2_CH1_INPUT:
case CS42L43_SWIRE_DP2_CH2_INPUT:
case CS42L43_SWIRE_DP3_CH1_INPUT:
case CS42L43_SWIRE_DP3_CH2_INPUT:
case CS42L43_SWIRE_DP4_CH1_INPUT:
case CS42L43_SWIRE_DP4_CH2_INPUT:
case CS42L43_ASRC_INT1_INPUT1:
case CS42L43_ASRC_INT2_INPUT1:
case CS42L43_ASRC_INT3_INPUT1:
case CS42L43_ASRC_INT4_INPUT1:
case CS42L43_ASRC_DEC1_INPUT1:
case CS42L43_ASRC_DEC2_INPUT1:
case CS42L43_ASRC_DEC3_INPUT1:
case CS42L43_ASRC_DEC4_INPUT1:
case CS42L43_ISRC1INT1_INPUT1:
case CS42L43_ISRC1INT2_INPUT1:
case CS42L43_ISRC1DEC1_INPUT1:
case CS42L43_ISRC1DEC2_INPUT1:
case CS42L43_ISRC2INT1_INPUT1:
case CS42L43_ISRC2INT2_INPUT1:
case CS42L43_ISRC2DEC1_INPUT1:
case CS42L43_ISRC2DEC2_INPUT1:
case CS42L43_EQ1MIX_INPUT1 ... CS42L43_EQ1MIX_INPUT4:
case CS42L43_EQ2MIX_INPUT1 ... CS42L43_EQ2MIX_INPUT4:
case CS42L43_SPDIF1_INPUT1:
case CS42L43_SPDIF2_INPUT1:
case CS42L43_AMP1MIX_INPUT1 ... CS42L43_AMP1MIX_INPUT4:
case CS42L43_AMP2MIX_INPUT1 ... CS42L43_AMP2MIX_INPUT4:
case CS42L43_AMP3MIX_INPUT1 ... CS42L43_AMP3MIX_INPUT4:
case CS42L43_AMP4MIX_INPUT1 ... CS42L43_AMP4MIX_INPUT4:
case CS42L43_ASRC_INT_ENABLES ... CS42L43_ASRC_DEC_ENABLES:
case CS42L43_PDNCNTL:
case CS42L43_RINGSENSE_DEB_CTRL:
case CS42L43_TIPSENSE_DEB_CTRL:
case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
case CS42L43_HS2:
case CS42L43_HS_STAT:
case CS42L43_MCU_SW_INTERRUPT:
case CS42L43_STEREO_MIC_CTRL:
case CS42L43_STEREO_MIC_CLAMP_CTRL:
case CS42L43_BLOCK_EN2 ... CS42L43_BLOCK_EN11:
case CS42L43_TONE_CH1_CTRL ... CS42L43_TONE_CH2_CTRL:
case CS42L43_MIC_DETECT_CONTROL_1:
case CS42L43_DETECT_STATUS_1:
case CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL:
case CS42L43_MIC_DETECT_CONTROL_ANDROID:
case CS42L43_ISRC1_CTRL:
case CS42L43_ISRC2_CTRL:
case CS42L43_CTRL_REG:
case CS42L43_FDIV_FRAC:
case CS42L43_CAL_RATIO:
case CS42L43_SPI_CLK_CONFIG1:
case CS42L43_SPI_CONFIG1 ... CS42L43_SPI_CONFIG4:
case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG8:
case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
case CS42L43_TX_DATA:
case CS42L43_RX_DATA:
case CS42L43_DACCNFG1 ... CS42L43_DACCNFG2:
case CS42L43_HPPATHVOL:
case CS42L43_PGAVOL:
case CS42L43_LOADDETRESULTS:
case CS42L43_LOADDETENA:
case CS42L43_CTRL:
case CS42L43_COEFF_DATA_IN0:
case CS42L43_COEFF_RD_WR0:
case CS42L43_INIT_DONE0:
case CS42L43_START_EQZ0:
case CS42L43_MUTE_EQ_IN0:
case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
case CS42L43_DECIM_MASK ... CS42L43_HPOUT_MASK:
case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
case CS42L43_BOOT_CONTROL:
case CS42L43_BLOCK_EN:
case CS42L43_SHUTTER_CONTROL:
case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
return true;
default:
return false;
}
}
EXPORT_SYMBOL_NS_GPL(cs42l43_readable_register, MFD_CS42L43);
bool cs42l43_precious_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L43_SFT_RESET:
case CS42L43_TX_DATA:
case CS42L43_RX_DATA:
case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
return true;
default:
return false;
}
}
EXPORT_SYMBOL_NS_GPL(cs42l43_precious_register, MFD_CS42L43);
bool cs42l43_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L43_DEVID:
case CS42L43_REVID:
case CS42L43_RELID:
case CS42L43_GPIO_STS:
case CS42L43_OTP_REVISION_ID:
case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
case CS42L43_HS_STAT:
case CS42L43_MCU_SW_INTERRUPT:
case CS42L43_DETECT_STATUS_1:
case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG2:
case CS42L43_TRAN_CONFIG8:
case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
case CS42L43_LOADDETRESULTS:
case CS42L43_INIT_DONE0:
case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
case CS42L43_BOOT_CONTROL:
case CS42L43_BLOCK_EN:
return true;
default:
return cs42l43_precious_register(dev, reg);
}
}
EXPORT_SYMBOL_NS_GPL(cs42l43_volatile_register, MFD_CS42L43);
#define CS42L43_IRQ_OFFSET(reg) ((CS42L43_##reg##_INT) - CS42L43_DECIM_INT)
#define CS42L43_IRQ_REG(name, reg) REGMAP_IRQ_REG(CS42L43_##name, \
CS42L43_IRQ_OFFSET(reg), \
CS42L43_##name##_INT_MASK)
static const struct regmap_irq cs42l43_regmap_irqs[] = {
CS42L43_IRQ_REG(PLL_LOST_LOCK, PLL),
CS42L43_IRQ_REG(PLL_READY, PLL),
CS42L43_IRQ_REG(HP_STARTUP_DONE, MSM),
CS42L43_IRQ_REG(HP_SHUTDOWN_DONE, MSM),
CS42L43_IRQ_REG(HSDET_DONE, MSM),
CS42L43_IRQ_REG(TIPSENSE_UNPLUG_DB, MSM),
CS42L43_IRQ_REG(TIPSENSE_PLUG_DB, MSM),
CS42L43_IRQ_REG(RINGSENSE_UNPLUG_DB, MSM),
CS42L43_IRQ_REG(RINGSENSE_PLUG_DB, MSM),
CS42L43_IRQ_REG(TIPSENSE_UNPLUG_PDET, MSM),
CS42L43_IRQ_REG(TIPSENSE_PLUG_PDET, MSM),
CS42L43_IRQ_REG(RINGSENSE_UNPLUG_PDET, MSM),
CS42L43_IRQ_REG(RINGSENSE_PLUG_PDET, MSM),
CS42L43_IRQ_REG(HS2_BIAS_SENSE, ACC_DET),
CS42L43_IRQ_REG(HS1_BIAS_SENSE, ACC_DET),
CS42L43_IRQ_REG(DC_DETECT1_FALSE, ACC_DET),
CS42L43_IRQ_REG(DC_DETECT1_TRUE, ACC_DET),
CS42L43_IRQ_REG(HSBIAS_CLAMPED, ACC_DET),
CS42L43_IRQ_REG(HS3_4_BIAS_SENSE, ACC_DET),
CS42L43_IRQ_REG(AMP2_CLK_STOP_FAULT, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP1_CLK_STOP_FAULT, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP2_VDDSPK_FAULT, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP1_VDDSPK_FAULT, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP2_SHUTDOWN_DONE, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP1_SHUTDOWN_DONE, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP2_STARTUP_DONE, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP1_STARTUP_DONE, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP2_THERM_SHDN, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP1_THERM_SHDN, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP2_THERM_WARN, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP1_THERM_WARN, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP2_SCDET, CLASS_D_AMP),
CS42L43_IRQ_REG(AMP1_SCDET, CLASS_D_AMP),
CS42L43_IRQ_REG(GPIO3_FALL, GPIO),
CS42L43_IRQ_REG(GPIO3_RISE, GPIO),
CS42L43_IRQ_REG(GPIO2_FALL, GPIO),
CS42L43_IRQ_REG(GPIO2_RISE, GPIO),
CS42L43_IRQ_REG(GPIO1_FALL, GPIO),
CS42L43_IRQ_REG(GPIO1_RISE, GPIO),
CS42L43_IRQ_REG(HP_ILIMIT, HPOUT),
CS42L43_IRQ_REG(HP_LOADDET_DONE, HPOUT),
};
static const struct regmap_irq_chip cs42l43_irq_chip = {
.name = "cs42l43",
.status_base = CS42L43_DECIM_INT,
.mask_base = CS42L43_DECIM_MASK,
.num_regs = 16,
.irqs = cs42l43_regmap_irqs,
.num_irqs = ARRAY_SIZE(cs42l43_regmap_irqs),
.runtime_pm = true,
};
static const char * const cs42l43_core_supplies[] = {
"vdd-a", "vdd-io", "vdd-cp",
};
static const char * const cs42l43_parent_supplies[] = { "vdd-amp" };
static const struct mfd_cell cs42l43_devs[] = {
{ .name = "cs42l43-pinctrl", },
{ .name = "cs42l43-spi", },
{
.name = "cs42l43-codec",
.parent_supplies = cs42l43_parent_supplies,
.num_parent_supplies = ARRAY_SIZE(cs42l43_parent_supplies),
},
};
/*
* If the device is connected over Soundwire, as well as soft resetting the
* device, this function will also way for the device to detach from the bus
* before returning.
*/
static int cs42l43_soft_reset(struct cs42l43 *cs42l43)
{
static const struct reg_sequence reset[] = {
{ CS42L43_SFT_RESET, CS42L43_SFT_RESET_VAL },
};
reinit_completion(&cs42l43->device_detach);
/*
* Apply cache only because the soft reset will cause the device to
* detach from the soundwire bus.
*/
regcache_cache_only(cs42l43->regmap, true);
regmap_multi_reg_write_bypassed(cs42l43->regmap, reset, ARRAY_SIZE(reset));
msleep(CS42L43_RESET_DELAY);
if (cs42l43->sdw) {
unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_DETACH_TIMEOUT);
unsigned long time;
time = wait_for_completion_timeout(&cs42l43->device_detach, timeout);
if (!time) {
dev_err(cs42l43->dev, "Timed out waiting for device detach\n");
return -ETIMEDOUT;
}
}
return -EAGAIN;
}
/*
* This function is essentially a no-op on I2C, but will wait for the device to
* attach when the device is used on a SoundWire bus.
*/
static int cs42l43_wait_for_attach(struct cs42l43 *cs42l43)
{
if (!cs42l43->attached) {
unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_ATTACH_TIMEOUT);
unsigned long time;
time = wait_for_completion_timeout(&cs42l43->device_attach, timeout);
if (!time) {
dev_err(cs42l43->dev, "Timed out waiting for device re-attach\n");
return -ETIMEDOUT;
}
}
regcache_cache_only(cs42l43->regmap, false);
/* The hardware requires enabling OSC_DIV before doing any SoundWire reads. */
if (cs42l43->sdw)
regmap_write(cs42l43->regmap, CS42L43_OSC_DIV_SEL,
CS42L43_OSC_DIV2_EN_MASK);
return 0;
}
/*
* This function will advance the firmware into boot stage 3 from boot stage 2.
* Boot stage 3 is required to send commands to the firmware. This is achieved
* by setting the firmware NEED configuration register to zero, this indicates
* no configuration is required forcing the firmware to advance to boot stage 3.
*
* Later revisions of the firmware require the use of an alternative register
* for this purpose, which is indicated through the shadow flag.
*/
static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow)
{
unsigned int need_reg = CS42L43_NEED_CONFIGS;
unsigned int val;
int ret;
if (shadow)
need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS;
regmap_write(cs42l43->regmap, need_reg, 0);
ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_BOOT_STATUS,
val, (val == CS42L43_MCU_BOOT_STAGE3),
CS42L43_MCU_POLL, CS42L43_MCU_CMD_TIMEOUT);
if (ret) {
dev_err(cs42l43->dev, "Failed to move to stage 3: %d, 0x%x\n", ret, val);
return ret;
}
return -EAGAIN;
}
/*
* This function will return the firmware to boot stage 2 from boot stage 3.
* Boot stage 2 is required to apply updates to the firmware. This is achieved
* by setting the firmware NEED configuration register to FW_PATCH_NEED_CFG,
* setting the HAVE configuration register to 0, and soft resetting. The
* firmware will see it is missing a patch configuration and will pause in boot
* stage 2.
*
* Note: Unlike cs42l43_mcu_stage_2_3 there is no need to consider the shadow
* register here as the driver will only return to boot stage 2 if the firmware
* requires update which means the revision does not include shadow register
* support.
*/
static int cs42l43_mcu_stage_3_2(struct cs42l43 *cs42l43)
{
regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_NEED_CONFIGS,
CS42L43_FW_PATCH_NEED_CFG_MASK);
regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS, 0);
return cs42l43_soft_reset(cs42l43);
}
/*
* Disable the firmware running on the device such that the driver can access
* the registers without fear of the MCU changing them under it.
*/
static int cs42l43_mcu_disable(struct cs42l43 *cs42l43)
{
unsigned int val;
int ret;
regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG,
CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL);
regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION,
CS42L43_FW_MM_CTRL_MCU_SEL_MASK);
regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK);
regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
(val & CS42L43_CONTROL_APPLIED_INT_MASK),
CS42L43_MCU_POLL, CS42L43_MCU_CMD_TIMEOUT);
if (ret) {
dev_err(cs42l43->dev, "Failed to disable firmware: %d, 0x%x\n", ret, val);
return ret;
}
/* Soft reset to clear any register state the firmware left behind. */
return cs42l43_soft_reset(cs42l43);
}
/*
* Callback to load firmware updates.
*/
static void cs42l43_mcu_load_firmware(const struct firmware *firmware, void *context)
{
struct cs42l43 *cs42l43 = context;
const struct cs42l43_patch_header *hdr;
unsigned int loadaddr, val;
int ret;
if (!firmware) {
dev_err(cs42l43->dev, "Failed to load firmware\n");
cs42l43->firmware_error = -ENODEV;
goto err;
}
hdr = (const struct cs42l43_patch_header *)&firmware->data[0];
loadaddr = le32_to_cpu(hdr->load_addr);
if (le16_to_cpu(hdr->version) != CS42L43_MCU_UPDATE_FORMAT) {
dev_err(cs42l43->dev, "Bad firmware file format: %d\n", hdr->version);
cs42l43->firmware_error = -EINVAL;
goto err_release;
}
regmap_write(cs42l43->regmap, CS42L43_PATCH_START_ADDR, loadaddr);
regmap_bulk_write(cs42l43->regmap, loadaddr + CS42L43_MCU_UPDATE_OFFSET,
&firmware->data[0], firmware->size / sizeof(u32));
regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_PATCH_IND_MASK);
regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
(val & CS42L43_PATCH_APPLIED_INT_MASK),
CS42L43_MCU_POLL, CS42L43_MCU_UPDATE_TIMEOUT);
if (ret) {
dev_err(cs42l43->dev, "Failed to update firmware: %d, 0x%x\n", ret, val);
cs42l43->firmware_error = ret;
goto err_release;
}
err_release:
release_firmware(firmware);
err:
complete(&cs42l43->firmware_download);
}
/*
* The process of updating the firmware is split into a series of steps, at the
* end of each step a soft reset of the device might be required which will
* require the driver to wait for the device to re-attach on the SoundWire bus,
* if that control bus is being used.
*/
static int cs42l43_mcu_update_step(struct cs42l43 *cs42l43)
{
unsigned int mcu_rev, bios_rev, boot_status, secure_cfg;
bool patched, shadow;
int ret;
/* Clear any stale software interrupt bits. */
regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev);
ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_STATUS, &boot_status);
if (ret) {
dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret);
return ret;
}
ret = regmap_read(cs42l43->regmap, CS42L43_MCU_SW_REV, &mcu_rev);
if (ret) {
dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret);
return ret;
}
bios_rev = (((mcu_rev & CS42L43_BIOS_MAJOR_REV_MASK) << 12) |
((mcu_rev & CS42L43_BIOS_MINOR_REV_MASK) << 4) |
((mcu_rev & CS42L43_BIOS_SUBMINOR_REV_MASK) >> 8)) >>
CS42L43_BIOS_MAJOR_REV_SHIFT;
mcu_rev = ((mcu_rev & CS42L43_FW_MAJOR_REV_MASK) << 12) |
((mcu_rev & CS42L43_FW_MINOR_REV_MASK) << 4) |
((mcu_rev & CS42L43_FW_SUBMINOR_REV_MASK) >> 8);
/*
* The firmware has two revision numbers bringing either of them up to a
* supported version will provide the features the driver requires.
*/
patched = mcu_rev >= CS42L43_MCU_SUPPORTED_REV ||
bios_rev >= CS42L43_MCU_SUPPORTED_BIOS_REV;
/*
* Later versions of the firmwware require the driver to access some
* features through a set of shadow registers.
*/
shadow = mcu_rev >= CS42L43_MCU_SHADOW_REGS_REQUIRED_REV;
ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_CONTROL, &secure_cfg);
if (ret) {
dev_err(cs42l43->dev, "Failed to read security settings: %d\n", ret);
return ret;
}
cs42l43->hw_lock = secure_cfg & CS42L43_LOCK_HW_STS_MASK;
if (!patched && cs42l43->hw_lock) {
dev_err(cs42l43->dev, "Unpatched secure device\n");
return -EPERM;
}
dev_dbg(cs42l43->dev, "Firmware(0x%x, 0x%x) in boot stage %d\n",
mcu_rev, bios_rev, boot_status);
switch (boot_status) {
case CS42L43_MCU_BOOT_STAGE2:
if (!patched) {
ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
"cs42l43.bin", cs42l43->dev,
GFP_KERNEL, cs42l43,
cs42l43_mcu_load_firmware);
if (ret) {
dev_err(cs42l43->dev, "Failed to request firmware: %d\n", ret);
return ret;
}
wait_for_completion(&cs42l43->firmware_download);
if (cs42l43->firmware_error)
return cs42l43->firmware_error;
return -EAGAIN;
} else {
return cs42l43_mcu_stage_2_3(cs42l43, shadow);
}
case CS42L43_MCU_BOOT_STAGE3:
if (patched)
return cs42l43_mcu_disable(cs42l43);
else
return cs42l43_mcu_stage_3_2(cs42l43);
case CS42L43_MCU_BOOT_STAGE4:
return 0;
default:
dev_err(cs42l43->dev, "Invalid boot status: %d\n", boot_status);
return -EINVAL;
}
}
/*
* Update the firmware running on the device.
*/
static int cs42l43_mcu_update(struct cs42l43 *cs42l43)
{
int i, ret;
for (i = 0; i < CS42L43_MCU_UPDATE_RETRIES; i++) {
ret = cs42l43_mcu_update_step(cs42l43);
if (ret != -EAGAIN)
return ret;
ret = cs42l43_wait_for_attach(cs42l43);
if (ret)
return ret;
}
dev_err(cs42l43->dev, "Failed retrying update\n");
return -ETIMEDOUT;
}
static int cs42l43_irq_config(struct cs42l43 *cs42l43)
{
struct irq_data *irq_data;
unsigned long irq_flags;
int ret;
if (cs42l43->sdw)
cs42l43->irq = cs42l43->sdw->irq;
cs42l43->irq_chip = cs42l43_irq_chip;
cs42l43->irq_chip.irq_drv_data = cs42l43;
irq_data = irq_get_irq_data(cs42l43->irq);
if (!irq_data) {
dev_err(cs42l43->dev, "Invalid IRQ: %d\n", cs42l43->irq);
return -EINVAL;
}
irq_flags = irqd_get_trigger_type(irq_data);
switch (irq_flags) {
case IRQF_TRIGGER_LOW:
case IRQF_TRIGGER_HIGH:
case IRQF_TRIGGER_RISING:
case IRQF_TRIGGER_FALLING:
break;
case IRQ_TYPE_NONE:
default:
irq_flags = IRQF_TRIGGER_LOW;
break;
}
irq_flags |= IRQF_ONESHOT;
ret = devm_regmap_add_irq_chip(cs42l43->dev, cs42l43->regmap,
cs42l43->irq, irq_flags, 0,
&cs42l43->irq_chip, &cs42l43->irq_data);
if (ret) {
dev_err(cs42l43->dev, "Failed to add IRQ chip: %d\n", ret);
return ret;
}
dev_dbg(cs42l43->dev, "Configured IRQ %d with flags 0x%lx\n",
cs42l43->irq, irq_flags);
return 0;
}
static void cs42l43_boot_work(struct work_struct *work)
{
struct cs42l43 *cs42l43 = container_of(work, struct cs42l43, boot_work);
unsigned int devid, revid, otp;
int ret;
ret = cs42l43_wait_for_attach(cs42l43);
if (ret)
goto err;
ret = regmap_read(cs42l43->regmap, CS42L43_DEVID, &devid);
if (ret) {
dev_err(cs42l43->dev, "Failed to read devid: %d\n", ret);
goto err;
}
switch (devid) {
case CS42L43_DEVID_VAL:
break;
default:
dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid);
goto err;
}
ret = regmap_read(cs42l43->regmap, CS42L43_REVID, &revid);
if (ret) {
dev_err(cs42l43->dev, "Failed to read rev: %d\n", ret);
goto err;
}
ret = regmap_read(cs42l43->regmap, CS42L43_OTP_REVISION_ID, &otp);
if (ret) {
dev_err(cs42l43->dev, "Failed to read otp rev: %d\n", ret);
goto err;
}
dev_info(cs42l43->dev,
"devid: 0x%06x, rev: 0x%02x, otp: 0x%02x\n", devid, revid, otp);
ret = cs42l43_mcu_update(cs42l43);
if (ret)
goto err;
ret = regmap_register_patch(cs42l43->regmap, cs42l43_reva_patch,
ARRAY_SIZE(cs42l43_reva_patch));
if (ret) {
dev_err(cs42l43->dev, "Failed to apply register patch: %d\n", ret);
goto err;
}
ret = cs42l43_irq_config(cs42l43);
if (ret)
goto err;
ret = devm_mfd_add_devices(cs42l43->dev, PLATFORM_DEVID_NONE,
cs42l43_devs, ARRAY_SIZE(cs42l43_devs),
NULL, 0, NULL);
if (ret) {
dev_err(cs42l43->dev, "Failed to add subdevices: %d\n", ret);
goto err;
}
pm_runtime_mark_last_busy(cs42l43->dev);
pm_runtime_put_autosuspend(cs42l43->dev);
return;
err:
pm_runtime_put_sync(cs42l43->dev);
cs42l43_dev_remove(cs42l43);
}
static int cs42l43_power_up(struct cs42l43 *cs42l43)
{
int ret;
ret = regulator_enable(cs42l43->vdd_p);
if (ret) {
dev_err(cs42l43->dev, "Failed to enable vdd-p: %d\n", ret);
return ret;
}
/* vdd-p must be on for 50uS before any other supply */
usleep_range(CS42L43_VDDP_DELAY, 2 * CS42L43_VDDP_DELAY);
gpiod_set_value_cansleep(cs42l43->reset, 1);
ret = regulator_bulk_enable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
if (ret) {
dev_err(cs42l43->dev, "Failed to enable core supplies: %d\n", ret);
goto err_reset;
}
ret = regulator_enable(cs42l43->vdd_d);
if (ret) {
dev_err(cs42l43->dev, "Failed to enable vdd-d: %d\n", ret);
goto err_core_supplies;
}
usleep_range(CS42L43_VDDD_DELAY, 2 * CS42L43_VDDD_DELAY);
return 0;
err_core_supplies:
regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
err_reset:
gpiod_set_value_cansleep(cs42l43->reset, 0);
regulator_disable(cs42l43->vdd_p);
return ret;
}
static int cs42l43_power_down(struct cs42l43 *cs42l43)
{
int ret;
ret = regulator_disable(cs42l43->vdd_d);
if (ret) {
dev_err(cs42l43->dev, "Failed to disable vdd-d: %d\n", ret);
return ret;
}
ret = regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
if (ret) {
dev_err(cs42l43->dev, "Failed to disable core supplies: %d\n", ret);
return ret;
}
gpiod_set_value_cansleep(cs42l43->reset, 0);
ret = regulator_disable(cs42l43->vdd_p);
if (ret) {
dev_err(cs42l43->dev, "Failed to disable vdd-p: %d\n", ret);
return ret;
}
return 0;
}
int cs42l43_dev_probe(struct cs42l43 *cs42l43)
{
int i, ret;
dev_set_drvdata(cs42l43->dev, cs42l43);
mutex_init(&cs42l43->pll_lock);
init_completion(&cs42l43->device_attach);
init_completion(&cs42l43->device_detach);
init_completion(&cs42l43->firmware_download);
INIT_WORK(&cs42l43->boot_work, cs42l43_boot_work);
regcache_cache_only(cs42l43->regmap, true);
cs42l43->reset = devm_gpiod_get_optional(cs42l43->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(cs42l43->reset))
return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->reset),
"Failed to get reset\n");
cs42l43->vdd_p = devm_regulator_get(cs42l43->dev, "vdd-p");
if (IS_ERR(cs42l43->vdd_p))
return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_p),
"Failed to get vdd-p\n");
cs42l43->vdd_d = devm_regulator_get(cs42l43->dev, "vdd-d");
if (IS_ERR(cs42l43->vdd_d))
return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_d),
"Failed to get vdd-d\n");
BUILD_BUG_ON(ARRAY_SIZE(cs42l43_core_supplies) != CS42L43_N_SUPPLIES);
for (i = 0; i < CS42L43_N_SUPPLIES; i++)
cs42l43->core_supplies[i].supply = cs42l43_core_supplies[i];
ret = devm_regulator_bulk_get(cs42l43->dev, CS42L43_N_SUPPLIES,
cs42l43->core_supplies);
if (ret)
return dev_err_probe(cs42l43->dev, ret,
"Failed to get core supplies\n");
ret = cs42l43_power_up(cs42l43);
if (ret)
return ret;
pm_runtime_set_autosuspend_delay(cs42l43->dev, CS42L43_AUTOSUSPEND_TIME);
pm_runtime_use_autosuspend(cs42l43->dev);
pm_runtime_set_active(cs42l43->dev);
/*
* The device is already powered up, but keep it from suspending until
* the boot work runs.
*/
pm_runtime_get_noresume(cs42l43->dev);
devm_pm_runtime_enable(cs42l43->dev);
queue_work(system_long_wq, &cs42l43->boot_work);
return 0;
}
EXPORT_SYMBOL_NS_GPL(cs42l43_dev_probe, MFD_CS42L43);
void cs42l43_dev_remove(struct cs42l43 *cs42l43)
{
cs42l43_power_down(cs42l43);
}
EXPORT_SYMBOL_NS_GPL(cs42l43_dev_remove, MFD_CS42L43);
static int cs42l43_suspend(struct device *dev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
int ret;
/*
* Don't care about being resumed here, but the driver does want
* force_resume to always trigger an actual resume, so that register
* state for the MCU/GPIOs is returned as soon as possible after system
* resume. force_resume will resume if the reference count is resumed on
* suspend hence the get_noresume.
*/
pm_runtime_get_noresume(dev);
ret = pm_runtime_force_suspend(dev);
if (ret) {
dev_err(cs42l43->dev, "Failed to force suspend: %d\n", ret);
pm_runtime_put_noidle(dev);
return ret;
}
pm_runtime_put_noidle(dev);
ret = cs42l43_power_down(cs42l43);
if (ret)
return ret;
return 0;
}
static int cs42l43_resume(struct device *dev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
int ret;
ret = cs42l43_power_up(cs42l43);
if (ret)
return ret;
ret = pm_runtime_force_resume(dev);
if (ret) {
dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret);
return ret;
}
return 0;
}
static int cs42l43_runtime_suspend(struct device *dev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
/*
* Whilst the driver doesn't power the chip down here, going into runtime
* suspend lets the SoundWire bus power down, which means the driver
* can't communicate with the device any more.
*/
regcache_cache_only(cs42l43->regmap, true);
return 0;
}
static int cs42l43_runtime_resume(struct device *dev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
unsigned int reset_canary;
int ret;
ret = cs42l43_wait_for_attach(cs42l43);
if (ret)
return ret;
ret = regmap_read(cs42l43->regmap, CS42L43_RELID, &reset_canary);
if (ret) {
dev_err(cs42l43->dev, "Failed to check reset canary: %d\n", ret);
goto err;
}
if (!reset_canary) {
/*
* If the canary has cleared the chip has reset, re-handle the
* MCU and mark the cache as dirty to indicate the chip reset.
*/
ret = cs42l43_mcu_update(cs42l43);
if (ret)
goto err;
regcache_mark_dirty(cs42l43->regmap);
}
ret = regcache_sync(cs42l43->regmap);
if (ret) {
dev_err(cs42l43->dev, "Failed to restore register cache: %d\n", ret);
goto err;
}
return 0;
err:
regcache_cache_only(cs42l43->regmap, true);
return ret;
}
EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = {
SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume)
RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL)
};
MODULE_DESCRIPTION("CS42L43 Core Driver");
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE("cs42l43.bin");
| linux-master | drivers/mfd/cs42l43.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* tps65910.c -- TI TPS6591x chip family multi-function driver
*
* Copyright 2010 Texas Instruments Inc.
*
* Author: Graeme Gregory <[email protected]>
* Author: Jorge Eduardo Candelaria <[email protected]>
*/
#include <linux/init.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/mfd/core.h>
#include <linux/regmap.h>
#include <linux/mfd/tps65910.h>
#include <linux/of.h>
#include <linux/of_device.h>
static const struct resource rtc_resources[] = {
{
.start = TPS65910_IRQ_RTC_ALARM,
.end = TPS65910_IRQ_RTC_ALARM,
.flags = IORESOURCE_IRQ,
}
};
static const struct mfd_cell tps65910s[] = {
{
.name = "tps65910-gpio",
},
{
.name = "tps65910-pmic",
},
{
.name = "tps65910-rtc",
.num_resources = ARRAY_SIZE(rtc_resources),
.resources = &rtc_resources[0],
},
{
.name = "tps65910-power",
},
};
static const struct regmap_irq tps65911_irqs[] = {
/* INT_STS */
[TPS65911_IRQ_PWRHOLD_F] = {
.mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65911_IRQ_VBAT_VMHI] = {
.mask = INT_MSK_VMBHI_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65911_IRQ_PWRON] = {
.mask = INT_MSK_PWRON_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65911_IRQ_PWRON_LP] = {
.mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65911_IRQ_PWRHOLD_R] = {
.mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65911_IRQ_HOTDIE] = {
.mask = INT_MSK_HOTDIE_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65911_IRQ_RTC_ALARM] = {
.mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65911_IRQ_RTC_PERIOD] = {
.mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
.reg_offset = 0,
},
/* INT_STS2 */
[TPS65911_IRQ_GPIO0_R] = {
.mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
.reg_offset = 1,
},
[TPS65911_IRQ_GPIO0_F] = {
.mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
.reg_offset = 1,
},
[TPS65911_IRQ_GPIO1_R] = {
.mask = INT_MSK2_GPIO1_R_IT_MSK_MASK,
.reg_offset = 1,
},
[TPS65911_IRQ_GPIO1_F] = {
.mask = INT_MSK2_GPIO1_F_IT_MSK_MASK,
.reg_offset = 1,
},
[TPS65911_IRQ_GPIO2_R] = {
.mask = INT_MSK2_GPIO2_R_IT_MSK_MASK,
.reg_offset = 1,
},
[TPS65911_IRQ_GPIO2_F] = {
.mask = INT_MSK2_GPIO2_F_IT_MSK_MASK,
.reg_offset = 1,
},
[TPS65911_IRQ_GPIO3_R] = {
.mask = INT_MSK2_GPIO3_R_IT_MSK_MASK,
.reg_offset = 1,
},
[TPS65911_IRQ_GPIO3_F] = {
.mask = INT_MSK2_GPIO3_F_IT_MSK_MASK,
.reg_offset = 1,
},
/* INT_STS2 */
[TPS65911_IRQ_GPIO4_R] = {
.mask = INT_MSK3_GPIO4_R_IT_MSK_MASK,
.reg_offset = 2,
},
[TPS65911_IRQ_GPIO4_F] = {
.mask = INT_MSK3_GPIO4_F_IT_MSK_MASK,
.reg_offset = 2,
},
[TPS65911_IRQ_GPIO5_R] = {
.mask = INT_MSK3_GPIO5_R_IT_MSK_MASK,
.reg_offset = 2,
},
[TPS65911_IRQ_GPIO5_F] = {
.mask = INT_MSK3_GPIO5_F_IT_MSK_MASK,
.reg_offset = 2,
},
[TPS65911_IRQ_WTCHDG] = {
.mask = INT_MSK3_WTCHDG_IT_MSK_MASK,
.reg_offset = 2,
},
[TPS65911_IRQ_VMBCH2_H] = {
.mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK,
.reg_offset = 2,
},
[TPS65911_IRQ_VMBCH2_L] = {
.mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK,
.reg_offset = 2,
},
[TPS65911_IRQ_PWRDN] = {
.mask = INT_MSK3_PWRDN_IT_MSK_MASK,
.reg_offset = 2,
},
};
static const struct regmap_irq tps65910_irqs[] = {
/* INT_STS */
[TPS65910_IRQ_VBAT_VMBDCH] = {
.mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65910_IRQ_VBAT_VMHI] = {
.mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65910_IRQ_PWRON] = {
.mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65910_IRQ_PWRON_LP] = {
.mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65910_IRQ_PWRHOLD] = {
.mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65910_IRQ_HOTDIE] = {
.mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65910_IRQ_RTC_ALARM] = {
.mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK,
.reg_offset = 0,
},
[TPS65910_IRQ_RTC_PERIOD] = {
.mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK,
.reg_offset = 0,
},
/* INT_STS2 */
[TPS65910_IRQ_GPIO_R] = {
.mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK,
.reg_offset = 1,
},
[TPS65910_IRQ_GPIO_F] = {
.mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK,
.reg_offset = 1,
},
};
static struct regmap_irq_chip tps65911_irq_chip = {
.name = "tps65910",
.irqs = tps65911_irqs,
.num_irqs = ARRAY_SIZE(tps65911_irqs),
.num_regs = 3,
.irq_reg_stride = 2,
.status_base = TPS65910_INT_STS,
.mask_base = TPS65910_INT_MSK,
.ack_base = TPS65910_INT_STS,
};
static struct regmap_irq_chip tps65910_irq_chip = {
.name = "tps65910",
.irqs = tps65910_irqs,
.num_irqs = ARRAY_SIZE(tps65910_irqs),
.num_regs = 2,
.irq_reg_stride = 2,
.status_base = TPS65910_INT_STS,
.mask_base = TPS65910_INT_MSK,
.ack_base = TPS65910_INT_STS,
};
static int tps65910_irq_init(struct tps65910 *tps65910, int irq,
struct tps65910_platform_data *pdata)
{
int ret;
static struct regmap_irq_chip *tps6591x_irqs_chip;
if (!irq) {
dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n");
return -EINVAL;
}
if (!pdata) {
dev_warn(tps65910->dev, "No interrupt support, no pdata\n");
return -EINVAL;
}
switch (tps65910_chip_id(tps65910)) {
case TPS65910:
tps6591x_irqs_chip = &tps65910_irq_chip;
break;
case TPS65911:
tps6591x_irqs_chip = &tps65911_irq_chip;
break;
}
tps65910->chip_irq = irq;
ret = devm_regmap_add_irq_chip(tps65910->dev, tps65910->regmap,
tps65910->chip_irq,
IRQF_ONESHOT, pdata->irq_base,
tps6591x_irqs_chip, &tps65910->irq_data);
if (ret < 0) {
dev_warn(tps65910->dev, "Failed to add irq_chip %d\n", ret);
tps65910->chip_irq = 0;
}
return ret;
}
static bool is_volatile_reg(struct device *dev, unsigned int reg)
{
struct tps65910 *tps65910 = dev_get_drvdata(dev);
/*
* Caching all regulator registers.
* All regualator register address range is same for
* TPS65910 and TPS65911
*/
if ((reg >= TPS65910_VIO) && (reg <= TPS65910_VDAC)) {
/* Check for non-existing register */
if (tps65910_chip_id(tps65910) == TPS65910)
if ((reg == TPS65911_VDDCTRL_OP) ||
(reg == TPS65911_VDDCTRL_SR))
return true;
return false;
}
return true;
}
static const struct regmap_config tps65910_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = is_volatile_reg,
.max_register = TPS65910_MAX_REGISTER - 1,
.cache_type = REGCACHE_RBTREE,
};
static int tps65910_ck32k_init(struct tps65910 *tps65910,
struct tps65910_board *pmic_pdata)
{
int ret;
if (!pmic_pdata->en_ck32k_xtal)
return 0;
ret = regmap_clear_bits(tps65910->regmap, TPS65910_DEVCTRL,
DEVCTRL_CK32K_CTRL_MASK);
if (ret < 0) {
dev_err(tps65910->dev, "clear ck32k_ctrl failed: %d\n", ret);
return ret;
}
return 0;
}
static int tps65910_sleepinit(struct tps65910 *tps65910,
struct tps65910_board *pmic_pdata)
{
struct device *dev;
int ret;
if (!pmic_pdata->en_dev_slp)
return 0;
dev = tps65910->dev;
/* enabling SLEEP device state */
ret = regmap_set_bits(tps65910->regmap, TPS65910_DEVCTRL,
DEVCTRL_DEV_SLP_MASK);
if (ret < 0) {
dev_err(dev, "set dev_slp failed: %d\n", ret);
goto err_sleep_init;
}
if (pmic_pdata->slp_keepon.therm_keepon) {
ret = regmap_set_bits(tps65910->regmap,
TPS65910_SLEEP_KEEP_RES_ON,
SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK);
if (ret < 0) {
dev_err(dev, "set therm_keepon failed: %d\n", ret);
goto disable_dev_slp;
}
}
if (pmic_pdata->slp_keepon.clkout32k_keepon) {
ret = regmap_set_bits(tps65910->regmap,
TPS65910_SLEEP_KEEP_RES_ON,
SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK);
if (ret < 0) {
dev_err(dev, "set clkout32k_keepon failed: %d\n", ret);
goto disable_dev_slp;
}
}
if (pmic_pdata->slp_keepon.i2chs_keepon) {
ret = regmap_set_bits(tps65910->regmap,
TPS65910_SLEEP_KEEP_RES_ON,
SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK);
if (ret < 0) {
dev_err(dev, "set i2chs_keepon failed: %d\n", ret);
goto disable_dev_slp;
}
}
return 0;
disable_dev_slp:
regmap_clear_bits(tps65910->regmap, TPS65910_DEVCTRL,
DEVCTRL_DEV_SLP_MASK);
err_sleep_init:
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id tps65910_of_match[] = {
{ .compatible = "ti,tps65910", .data = (void *)TPS65910},
{ .compatible = "ti,tps65911", .data = (void *)TPS65911},
{ },
};
static struct tps65910_board *tps65910_parse_dt(struct i2c_client *client,
unsigned long *chip_id)
{
struct device_node *np = client->dev.of_node;
struct tps65910_board *board_info;
unsigned int prop;
const struct of_device_id *match;
int ret;
match = of_match_device(tps65910_of_match, &client->dev);
if (!match) {
dev_err(&client->dev, "Failed to find matching dt id\n");
return NULL;
}
*chip_id = (unsigned long)match->data;
board_info = devm_kzalloc(&client->dev, sizeof(*board_info),
GFP_KERNEL);
if (!board_info)
return NULL;
ret = of_property_read_u32(np, "ti,vmbch-threshold", &prop);
if (!ret)
board_info->vmbch_threshold = prop;
ret = of_property_read_u32(np, "ti,vmbch2-threshold", &prop);
if (!ret)
board_info->vmbch2_threshold = prop;
prop = of_property_read_bool(np, "ti,en-ck32k-xtal");
board_info->en_ck32k_xtal = prop;
prop = of_property_read_bool(np, "ti,sleep-enable");
board_info->en_dev_slp = prop;
prop = of_property_read_bool(np, "ti,sleep-keep-therm");
board_info->slp_keepon.therm_keepon = prop;
prop = of_property_read_bool(np, "ti,sleep-keep-ck32k");
board_info->slp_keepon.clkout32k_keepon = prop;
prop = of_property_read_bool(np, "ti,sleep-keep-hsclk");
board_info->slp_keepon.i2chs_keepon = prop;
board_info->irq = client->irq;
board_info->irq_base = -1;
board_info->pm_off = of_property_read_bool(np,
"ti,system-power-controller");
return board_info;
}
#else
static inline
struct tps65910_board *tps65910_parse_dt(struct i2c_client *client,
unsigned long *chip_id)
{
return NULL;
}
#endif
static struct i2c_client *tps65910_i2c_client;
static void tps65910_power_off(void)
{
struct tps65910 *tps65910;
tps65910 = dev_get_drvdata(&tps65910_i2c_client->dev);
regmap_update_bits(tps65910->regmap, TPS65910_DEVCTRL,
DEVCTRL_DEV_OFF_MASK | DEVCTRL_DEV_ON_MASK,
DEVCTRL_DEV_OFF_MASK);
}
static int tps65910_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct tps65910 *tps65910;
struct tps65910_board *pmic_plat_data;
struct tps65910_board *of_pmic_plat_data = NULL;
struct tps65910_platform_data *init_data;
unsigned long chip_id = id->driver_data;
int ret;
pmic_plat_data = dev_get_platdata(&i2c->dev);
if (!pmic_plat_data && i2c->dev.of_node) {
pmic_plat_data = tps65910_parse_dt(i2c, &chip_id);
of_pmic_plat_data = pmic_plat_data;
}
if (!pmic_plat_data)
return -EINVAL;
init_data = devm_kzalloc(&i2c->dev, sizeof(*init_data), GFP_KERNEL);
if (init_data == NULL)
return -ENOMEM;
tps65910 = devm_kzalloc(&i2c->dev, sizeof(*tps65910), GFP_KERNEL);
if (tps65910 == NULL)
return -ENOMEM;
tps65910->of_plat_data = of_pmic_plat_data;
i2c_set_clientdata(i2c, tps65910);
tps65910->dev = &i2c->dev;
tps65910->i2c_client = i2c;
tps65910->id = chip_id;
/* Work around silicon erratum SWCZ010: the tps65910 may miss the
* first I2C transfer. So issue a dummy transfer before the first
* real transfer.
*/
i2c_master_send(i2c, "", 1);
tps65910->regmap = devm_regmap_init_i2c(i2c, &tps65910_regmap_config);
if (IS_ERR(tps65910->regmap)) {
ret = PTR_ERR(tps65910->regmap);
dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
return ret;
}
init_data->irq = pmic_plat_data->irq;
init_data->irq_base = pmic_plat_data->irq_base;
tps65910_irq_init(tps65910, init_data->irq, init_data);
tps65910_ck32k_init(tps65910, pmic_plat_data);
tps65910_sleepinit(tps65910, pmic_plat_data);
if (pmic_plat_data->pm_off && !pm_power_off) {
/*
* The PWR_OFF bit needs to be set separately, before
* transitioning to the OFF state. It enables the "sequential"
* power-off mode on TPS65911, it's a NO-OP on TPS65910.
*/
ret = regmap_set_bits(tps65910->regmap, TPS65910_DEVCTRL,
DEVCTRL_PWR_OFF_MASK);
if (ret) {
dev_err(&i2c->dev, "failed to set power-off mode: %d\n",
ret);
return ret;
}
tps65910_i2c_client = i2c;
pm_power_off = tps65910_power_off;
}
ret = devm_mfd_add_devices(tps65910->dev, -1,
tps65910s, ARRAY_SIZE(tps65910s),
NULL, 0,
regmap_irq_get_domain(tps65910->irq_data));
if (ret < 0) {
dev_err(&i2c->dev, "mfd_add_devices failed: %d\n", ret);
return ret;
}
return ret;
}
static const struct i2c_device_id tps65910_i2c_id[] = {
{ "tps65910", TPS65910 },
{ "tps65911", TPS65911 },
{ }
};
static struct i2c_driver tps65910_i2c_driver = {
.driver = {
.name = "tps65910",
.of_match_table = of_match_ptr(tps65910_of_match),
},
.probe = tps65910_i2c_probe,
.id_table = tps65910_i2c_id,
};
static int __init tps65910_i2c_init(void)
{
return i2c_add_driver(&tps65910_i2c_driver);
}
/* init early so consumer devices can complete system boot */
subsys_initcall(tps65910_i2c_init);
| linux-master | drivers/mfd/tps65910.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Regmap tables for CS47L35 codec
*
* Copyright (C) 2015-2017 Cirrus Logic
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
static const struct reg_sequence cs47l35_reva_16_patch[] = {
{ 0x460, 0x0c40 },
{ 0x461, 0xcd1a },
{ 0x462, 0x0c40 },
{ 0x463, 0xb53b },
{ 0x464, 0x0c40 },
{ 0x465, 0x7503 },
{ 0x466, 0x0c40 },
{ 0x467, 0x4a41 },
{ 0x468, 0x0041 },
{ 0x469, 0x3491 },
{ 0x46a, 0x0841 },
{ 0x46b, 0x1f50 },
{ 0x46c, 0x0446 },
{ 0x46d, 0x14ed },
{ 0x46e, 0x0446 },
{ 0x46f, 0x1455 },
{ 0x470, 0x04c6 },
{ 0x471, 0x1220 },
{ 0x472, 0x04c6 },
{ 0x473, 0x040f },
{ 0x474, 0x04ce },
{ 0x475, 0x0339 },
{ 0x476, 0x05df },
{ 0x477, 0x028f },
{ 0x478, 0x05df },
{ 0x479, 0x0209 },
{ 0x47a, 0x05df },
{ 0x47b, 0x00cf },
{ 0x47c, 0x05df },
{ 0x47d, 0x0001 },
{ 0x47e, 0x07ff },
};
int cs47l35_patch(struct madera *madera)
{
int ret;
ret = regmap_register_patch(madera->regmap, cs47l35_reva_16_patch,
ARRAY_SIZE(cs47l35_reva_16_patch));
if (ret < 0)
dev_err(madera->dev, "Error applying patch: %d\n", ret);
return ret;
}
EXPORT_SYMBOL_GPL(cs47l35_patch);
static const struct reg_default cs47l35_reg_default[] = {
{ 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */
{ 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4*/
{ 0x00000066, 0x01ff }, /* R102 (0x66) - Always On Triggers Sequence Select 1*/
{ 0x00000067, 0x01ff }, /* R103 (0x67) - Always On Triggers Sequence Select 2*/
{ 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */
{ 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics phase 1 intensity */
{ 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics phase 1 duration */
{ 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics phase 2 intensity */
{ 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics phase 2 duration */
{ 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics phase 3 intensity */
{ 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics phase 3 duration */
{ 0x000000A0, 0x0000 }, /* R160 (0xa0) - Comfort Noise Generator */
{ 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32k 1 */
{ 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 (0x102) - Sample rate 1 */
{ 0x00000103, 0x0011 }, /* R259 (0x103) - Sample rate 2 */
{ 0x00000104, 0x0011 }, /* R260 (0x104) - Sample rate 3 */
{ 0x00000120, 0x0305 }, /* R288 (0x120) - DSP Clock 1 */
{ 0x00000122, 0x0000 }, /* R290 (0x122) - DSP Clock 2 */
{ 0x00000149, 0x0000 }, /* R329 (0x149) - Output system clock */
{ 0x0000014a, 0x0000 }, /* R330 (0x14a) - Output async clock */
{ 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */
{ 0x00000171, 0x0002 }, /* R369 (0x171) - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 (0x172) - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 (0x173) - FLL1 Control 3 */
{ 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */
{ 0x00000175, 0x0000 }, /* R373 (0x175) - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */
{ 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */
{ 0x0000017a, 0x2906 }, /* R378 (0x17a) - FLL1 EFS2 */
{ 0x0000017f, 0x0000 }, /* R383 (0x17f) - FLL1 Synchroniser 1 */
{ 0x00000180, 0x0000 }, /* R384 (0x180) - FLL1 Synchroniser 2 */
{ 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 3 */
{ 0x00000182, 0x0000 }, /* R386 (0x182) - FLL1 Synchroniser 4 */
{ 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 5 */
{ 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 6 */
{ 0x00000185, 0x0001 }, /* R389 (0x185) - FLL1 Synchroniser 7 */
{ 0x00000187, 0x0000 }, /* R391 (0x187) - FLL1 Spread Spectrum */
{ 0x00000188, 0x000c }, /* R392 (0x188) - FLL1 GPIO Clock */
{ 0x00000200, 0x0006 }, /* R512 (0x200) - Mic Charge Pump 1 */
{ 0x0000020b, 0x0400 }, /* R523 (0x20b) - HP Charge Pump 8 */
{ 0x00000213, 0x03e4 }, /* R531 (0x213) - LDO2 Control 1 */
{ 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */
{ 0x00000219, 0x00e6 }, /* R537 (0x219) - Mic Bias Ctrl 2 */
{ 0x0000021c, 0x0022 }, /* R540 (0x21c) - Mic Bias Ctrl 5 */
{ 0x0000021e, 0x0022 }, /* R542 (0x21e) - Mic Bias Ctrl 6 */
{ 0x0000027e, 0x0000 }, /* R638 (0x27e) - EDRE HP stereo control */
{ 0x00000293, 0x0080 }, /* R659 (0x293) - Accessory Detect Mode 1 */
{ 0x0000029b, 0x0000 }, /* R667 (0x29b) - Headphone Detect 1 */
{ 0x000002a3, 0x1102 }, /* R675 (0x2a3) - Mic Detect Control 1 */
{ 0x000002a4, 0x009f }, /* R676 (0x2a4) - Mic Detect Control 2 */
{ 0x000002a6, 0x3d3d }, /* R678 (0x2a6) - Mic Detect Level 1 */
{ 0x000002a7, 0x3d3d }, /* R679 (0x2a7) - Mic Detect Level 2 */
{ 0x000002a8, 0x333d }, /* R680 (0x2a8) - Mic Detect Level 3 */
{ 0x000002a9, 0x202d }, /* R681 (0x2a9) - Mic Detect Level 4 */
{ 0x000002c6, 0x0010 }, /* R710 (0x2c5) - Mic Clamp control */
{ 0x000002c8, 0x0000 }, /* R712 (0x2c8) - GP switch 1 */
{ 0x000002d3, 0x0000 }, /* R723 (0x2d3) - Jack detect analogue */
{ 0x00000300, 0x0000 }, /* R768 (0x300) - Input Enables */
{ 0x00000308, 0x0000 }, /* R776 (0x308) - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */
{ 0x0000030c, 0x0002 }, /* R780 (0x30c) - HPF Control */
{ 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */
{ 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */
{ 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */
{ 0x00000318, 0x0080 }, /* R792 (0x318) - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */
{ 0x0000031a, 0x0500 }, /* R794 (0x31a) - DMIC2L Control */
{ 0x0000031c, 0x0080 }, /* R796 (0x31c) - IN2R Control */
{ 0x0000031d, 0x0180 }, /* R797 (0x31d) - ADC Digital Volume 2R */
{ 0x0000031e, 0x0000 }, /* R798 (0x31e) - DMIC2R Control */
{ 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 (0x408) - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */
{ 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */
{ 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */
{ 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */
{ 0x00000428, 0x0000 }, /* R1064 (0x428) - Output Path Config 4L */
{ 0x00000429, 0x0180 }, /* R1065 (0x429) - DAC Digital Volume 4L */
{ 0x0000042b, 0x0040 }, /* R1067 (0x42b) - Noise Gate Select 4L */
{ 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */
{ 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */
{ 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */
{ 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */
{ 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */
{ 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */
{ 0x00000451, 0x0000 }, /* R1105 (0x451) - DAC AEC Control 2 */
{ 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 CTRL 1 */
{ 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 CTRL 2 */
{ 0x000004a0, 0x3080 }, /* R1184 (0x4a0) - HP1 Short Circuit Ctrl */
{ 0x000004a8, 0x7120 }, /* R1192 (0x4a8) - HP Test Ctrl 5 */
{ 0x000004a9, 0x7120 }, /* R1193 (0x4a9) - HP Test Ctrl 6 */
{ 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */
{ 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */
{ 0x0000050a, 0x0001 }, /* R1290 (0x50a) - AIF1 Frame Ctrl 4 */
{ 0x0000050b, 0x0002 }, /* R1291 (0x50b) - AIF1 Frame Ctrl 5 */
{ 0x0000050c, 0x0003 }, /* R1292 (0x50c) - AIF1 Frame Ctrl 6 */
{ 0x0000050d, 0x0004 }, /* R1293 (0x50d) - AIF1 Frame Ctrl 7 */
{ 0x0000050e, 0x0005 }, /* R1294 (0x50e) - AIF1 Frame Ctrl 8 */
{ 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */
{ 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */
{ 0x0000051a, 0x0000 }, /* R1306 (0x51a) - AIF1 Rx Enables */
{ 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */
{ 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */
{ 0x0000054a, 0x0001 }, /* R1354 (0x54a) - AIF2 Frame Ctrl 4 */
{ 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */
{ 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */
{ 0x0000055a, 0x0000 }, /* R1370 (0x55a) - AIF2 Rx Enables */
{ 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */
{ 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */
{ 0x0000058a, 0x0001 }, /* R1418 (0x58a) - AIF3 Frame Ctrl 4 */
{ 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */
{ 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */
{ 0x0000059a, 0x0000 }, /* R1434 (0x59a) - AIF3 Rx Enables */
{ 0x000005c2, 0x0000 }, /* R1474 (0x5c2) - SPD1 TX Control */
{ 0x000005e3, 0x0000 }, /* R1507 (0x5e3) - SLIMbus Framer Ref Gear */
{ 0x000005e5, 0x0000 }, /* R1509 (0x5e5) - SLIMbus Rates 1 */
{ 0x000005e6, 0x0000 }, /* R1510 (0x5e6) - SLIMbus Rates 2 */
{ 0x000005e7, 0x0000 }, /* R1511 (0x5e7) - SLIMbus Rates 3 */
{ 0x000005e9, 0x0000 }, /* R1513 (0x5e9) - SLIMbus Rates 5 */
{ 0x000005ea, 0x0000 }, /* R1514 (0x5ea) - SLIMbus Rates 6 */
{ 0x000005eb, 0x0000 }, /* R1515 (0x5eb) - SLIMbus Rates 7 */
{ 0x000005f5, 0x0000 }, /* R1525 (0x5f5) - SLIMbus RX Channel Enable */
{ 0x000005f6, 0x0000 }, /* R1526 (0x5f6) - SLIMbus TX Channel Enable */
{ 0x00000640, 0x0000 }, /* R1600 (0x640) - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 (0x641) - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 (0x642) - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 (0x643) - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 (0x644) - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 (0x645) - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 (0x646) - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 (0x647) - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 (0x648) - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 (0x649) - PWM2MIX Input 1 Volume */
{ 0x0000064a, 0x0000 }, /* R1610 (0x64a) - PWM2MIX Input 2 Source */
{ 0x0000064b, 0x0080 }, /* R1611 (0x64b) - PWM2MIX Input 2 Volume */
{ 0x0000064c, 0x0000 }, /* R1612 (0x64c) - PWM2MIX Input 3 Source */
{ 0x0000064d, 0x0080 }, /* R1613 (0x64d) - PWM2MIX Input 3 Volume */
{ 0x0000064e, 0x0000 }, /* R1614 (0x64e) - PWM2MIX Input 4 Source */
{ 0x0000064f, 0x0080 }, /* R1615 (0x64f) - PWM2MIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 (0x680) - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 (0x681) - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 (0x682) - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 (0x683) - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 (0x684) - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 (0x685) - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 (0x686) - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 (0x687) - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 (0x688) - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 (0x689) - OUT1RMIX Input 1 Volume */
{ 0x0000068a, 0x0000 }, /* R1674 (0x68a) - OUT1RMIX Input 2 Source */
{ 0x0000068b, 0x0080 }, /* R1675 (0x68b) - OUT1RMIX Input 2 Volume */
{ 0x0000068c, 0x0000 }, /* R1672 (0x68c) - OUT1RMIX Input 3 Source */
{ 0x0000068d, 0x0080 }, /* R1673 (0x68d) - OUT1RMIX Input 3 Volume */
{ 0x0000068e, 0x0000 }, /* R1674 (0x68e) - OUT1RMIX Input 4 Source */
{ 0x0000068f, 0x0080 }, /* R1675 (0x68f) - OUT1RMIX Input 4 Volume */
{ 0x000006b0, 0x0000 }, /* R1712 (0x6b0) - OUT4LMIX Input 1 Source */
{ 0x000006b1, 0x0080 }, /* R1713 (0x6b1) - OUT4LMIX Input 1 Volume */
{ 0x000006b2, 0x0000 }, /* R1714 (0x6b2) - OUT4LMIX Input 2 Source */
{ 0x000006b3, 0x0080 }, /* R1715 (0x6b3) - OUT4LMIX Input 2 Volume */
{ 0x000006b4, 0x0000 }, /* R1716 (0x6b4) - OUT4LMIX Input 3 Source */
{ 0x000006b5, 0x0080 }, /* R1717 (0x6b5) - OUT4LMIX Input 3 Volume */
{ 0x000006b6, 0x0000 }, /* R1718 (0x6b6) - OUT4LMIX Input 4 Source */
{ 0x000006b7, 0x0080 }, /* R1719 (0x6b7) - OUT4LMIX Input 4 Volume */
{ 0x000006c0, 0x0000 }, /* R1728 (0x6c0) - OUT5LMIX Input 1 Source */
{ 0x000006c1, 0x0080 }, /* R1729 (0x6c1) - OUT5LMIX Input 1 Volume */
{ 0x000006c2, 0x0000 }, /* R1730 (0x6c2) - OUT5LMIX Input 2 Source */
{ 0x000006c3, 0x0080 }, /* R1731 (0x6c3) - OUT5LMIX Input 2 Volume */
{ 0x000006c4, 0x0000 }, /* R1732 (0x6c4) - OUT5LMIX Input 3 Source */
{ 0x000006c5, 0x0080 }, /* R1733 (0x6c5) - OUT5LMIX Input 3 Volume */
{ 0x000006c6, 0x0000 }, /* R1734 (0x6c6) - OUT5LMIX Input 4 Source */
{ 0x000006c7, 0x0080 }, /* R1735 (0x6c7) - OUT5LMIX Input 4 Volume */
{ 0x000006c8, 0x0000 }, /* R1736 (0x6c8) - OUT5RMIX Input 1 Source */
{ 0x000006c9, 0x0080 }, /* R1737 (0x6c9) - OUT5RMIX Input 1 Volume */
{ 0x000006ca, 0x0000 }, /* R1738 (0x6ca) - OUT5RMIX Input 2 Source */
{ 0x000006cb, 0x0080 }, /* R1739 (0x6cb) - OUT5RMIX Input 2 Volume */
{ 0x000006cc, 0x0000 }, /* R1740 (0x6cc) - OUT5RMIX Input 3 Source */
{ 0x000006cd, 0x0080 }, /* R1741 (0x6cd) - OUT5RMIX Input 3 Volume */
{ 0x000006ce, 0x0000 }, /* R1742 (0x6ce) - OUT5RMIX Input 4 Source */
{ 0x000006cf, 0x0080 }, /* R1743 (0x6cf) - OUT5RMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 (0x700) - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 (0x701) - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 (0x702) - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 (0x703) - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 (0x704) - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 (0x705) - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 (0x706) - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 (0x707) - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 (0x708) - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 (0x709) - AIF1TX2MIX Input 1 Volume */
{ 0x0000070a, 0x0000 }, /* R1802 (0x70a) - AIF1TX2MIX Input 2 Source */
{ 0x0000070b, 0x0080 }, /* R1803 (0x70b) - AIF1TX2MIX Input 2 Volume */
{ 0x0000070c, 0x0000 }, /* R1804 (0x70c) - AIF1TX2MIX Input 3 Source */
{ 0x0000070d, 0x0080 }, /* R1805 (0x70d) - AIF1TX2MIX Input 3 Volume */
{ 0x0000070e, 0x0000 }, /* R1806 (0x70e) - AIF1TX2MIX Input 4 Source */
{ 0x0000070f, 0x0080 }, /* R1807 (0x70f) - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 (0x710) - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 (0x711) - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 (0x712) - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 (0x713) - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 (0x714) - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 (0x715) - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 (0x716) - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 (0x717) - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 (0x718) - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 (0x719) - AIF1TX4MIX Input 1 Volume */
{ 0x0000071a, 0x0000 }, /* R1818 (0x71a) - AIF1TX4MIX Input 2 Source */
{ 0x0000071b, 0x0080 }, /* R1819 (0x71b) - AIF1TX4MIX Input 2 Volume */
{ 0x0000071c, 0x0000 }, /* R1820 (0x71c) - AIF1TX4MIX Input 3 Source */
{ 0x0000071d, 0x0080 }, /* R1821 (0x71d) - AIF1TX4MIX Input 3 Volume */
{ 0x0000071e, 0x0000 }, /* R1822 (0x71e) - AIF1TX4MIX Input 4 Source */
{ 0x0000071f, 0x0080 }, /* R1823 (0x71f) - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 (0x720) - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 (0x721) - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 (0x722) - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 (0x723) - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 (0x724) - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 (0x725) - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 (0x726) - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 (0x727) - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 (0x728) - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 (0x729) - AIF1TX6MIX Input 1 Volume */
{ 0x0000072a, 0x0000 }, /* R1834 (0x72a) - AIF1TX6MIX Input 2 Source */
{ 0x0000072b, 0x0080 }, /* R1835 (0x72b) - AIF1TX6MIX Input 2 Volume */
{ 0x0000072c, 0x0000 }, /* R1836 (0x72c) - AIF1TX6MIX Input 3 Source */
{ 0x0000072d, 0x0080 }, /* R1837 (0x72d) - AIF1TX6MIX Input 3 Volume */
{ 0x0000072e, 0x0000 }, /* R1838 (0x72e) - AIF1TX6MIX Input 4 Source */
{ 0x0000072f, 0x0080 }, /* R1839 (0x72f) - AIF1TX6MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 (0x740) - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 (0x741) - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 (0x742) - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 (0x743) - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 (0x744) - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 (0x745) - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 (0x746) - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 (0x747) - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 (0x748) - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 (0x749) - AIF2TX2MIX Input 1 Volume */
{ 0x0000074a, 0x0000 }, /* R1866 (0x74a) - AIF2TX2MIX Input 2 Source */
{ 0x0000074b, 0x0080 }, /* R1867 (0x74b) - AIF2TX2MIX Input 2 Volume */
{ 0x0000074c, 0x0000 }, /* R1868 (0x74c) - AIF2TX2MIX Input 3 Source */
{ 0x0000074d, 0x0080 }, /* R1869 (0x74d) - AIF2TX2MIX Input 3 Volume */
{ 0x0000074e, 0x0000 }, /* R1870 (0x74e) - AIF2TX2MIX Input 4 Source */
{ 0x0000074f, 0x0080 }, /* R1871 (0x74f) - AIF2TX2MIX Input 4 Volume */
{ 0x00000780, 0x0000 }, /* R1920 (0x780) - AIF3TX1MIX Input 1 Source */
{ 0x00000781, 0x0080 }, /* R1921 (0x781) - AIF3TX1MIX Input 1 Volume */
{ 0x00000782, 0x0000 }, /* R1922 (0x782) - AIF3TX1MIX Input 2 Source */
{ 0x00000783, 0x0080 }, /* R1923 (0x783) - AIF3TX1MIX Input 2 Volume */
{ 0x00000784, 0x0000 }, /* R1924 (0x784) - AIF3TX1MIX Input 3 Source */
{ 0x00000785, 0x0080 }, /* R1925 (0x785) - AIF3TX1MIX Input 3 Volume */
{ 0x00000786, 0x0000 }, /* R1926 (0x786) - AIF3TX1MIX Input 4 Source */
{ 0x00000787, 0x0080 }, /* R1927 (0x787) - AIF3TX1MIX Input 4 Volume */
{ 0x00000788, 0x0000 }, /* R1928 (0x788) - AIF3TX2MIX Input 1 Source */
{ 0x00000789, 0x0080 }, /* R1929 (0x789) - AIF3TX2MIX Input 1 Volume */
{ 0x0000078a, 0x0000 }, /* R1930 (0x78a) - AIF3TX2MIX Input 2 Source */
{ 0x0000078b, 0x0080 }, /* R1931 (0x78b) - AIF3TX2MIX Input 2 Volume */
{ 0x0000078c, 0x0000 }, /* R1932 (0x78c) - AIF3TX2MIX Input 3 Source */
{ 0x0000078d, 0x0080 }, /* R1933 (0x78d) - AIF3TX2MIX Input 3 Volume */
{ 0x0000078e, 0x0000 }, /* R1934 (0x78e) - AIF3TX2MIX Input 4 Source */
{ 0x0000078f, 0x0080 }, /* R1935 (0x78f) - AIF3TX2MIX Input 4 Volume */
{ 0x000007c0, 0x0000 }, /* R1984 (0x7c0) - SLIMTX1MIX Input 1 Source */
{ 0x000007c1, 0x0080 }, /* R1985 (0x7c1) - SLIMTX1MIX Input 1 Volume */
{ 0x000007c2, 0x0000 }, /* R1986 (0x7c2) - SLIMTX1MIX Input 2 Source */
{ 0x000007c3, 0x0080 }, /* R1987 (0x7c3) - SLIMTX1MIX Input 2 Volume */
{ 0x000007c4, 0x0000 }, /* R1988 (0x7c4) - SLIMTX1MIX Input 3 Source */
{ 0x000007c5, 0x0080 }, /* R1989 (0x7c5) - SLIMTX1MIX Input 3 Volume */
{ 0x000007c6, 0x0000 }, /* R1990 (0x7c6) - SLIMTX1MIX Input 4 Source */
{ 0x000007c7, 0x0080 }, /* R1991 (0x7c7) - SLIMTX1MIX Input 4 Volume */
{ 0x000007c8, 0x0000 }, /* R1992 (0x7c8) - SLIMTX2MIX Input 1 Source */
{ 0x000007c9, 0x0080 }, /* R1993 (0x7c9) - SLIMTX2MIX Input 1 Volume */
{ 0x000007ca, 0x0000 }, /* R1994 (0x7ca) - SLIMTX2MIX Input 2 Source */
{ 0x000007cb, 0x0080 }, /* R1995 (0x7cb) - SLIMTX2MIX Input 2 Volume */
{ 0x000007cc, 0x0000 }, /* R1996 (0x7cc) - SLIMTX2MIX Input 3 Source */
{ 0x000007cd, 0x0080 }, /* R1997 (0x7cd) - SLIMTX2MIX Input 3 Volume */
{ 0x000007ce, 0x0000 }, /* R1998 (0x7ce) - SLIMTX2MIX Input 4 Source */
{ 0x000007cf, 0x0080 }, /* R1999 (0x7cf) - SLIMTX2MIX Input 4 Volume */
{ 0x000007d0, 0x0000 }, /* R2000 (0x7d0) - SLIMTX3MIX Input 1 Source */
{ 0x000007d1, 0x0080 }, /* R2001 (0x7d1) - SLIMTX3MIX Input 1 Volume */
{ 0x000007d2, 0x0000 }, /* R2002 (0x7d2) - SLIMTX3MIX Input 2 Source */
{ 0x000007d3, 0x0080 }, /* R2003 (0x7d3) - SLIMTX3MIX Input 2 Volume */
{ 0x000007d4, 0x0000 }, /* R2004 (0x7d4) - SLIMTX3MIX Input 3 Source */
{ 0x000007d5, 0x0080 }, /* R2005 (0x7d5) - SLIMTX3MIX Input 3 Volume */
{ 0x000007d6, 0x0000 }, /* R2006 (0x7d6) - SLIMTX3MIX Input 4 Source */
{ 0x000007d7, 0x0080 }, /* R2007 (0x7d7) - SLIMTX3MIX Input 4 Volume */
{ 0x000007d8, 0x0000 }, /* R2008 (0x7d8) - SLIMTX4MIX Input 1 Source */
{ 0x000007d9, 0x0080 }, /* R2009 (0x7d9) - SLIMTX4MIX Input 1 Volume */
{ 0x000007da, 0x0000 }, /* R2010 (0x7da) - SLIMTX4MIX Input 2 Source */
{ 0x000007db, 0x0080 }, /* R2011 (0x7db) - SLIMTX4MIX Input 2 Volume */
{ 0x000007dc, 0x0000 }, /* R2012 (0x7dc) - SLIMTX4MIX Input 3 Source */
{ 0x000007dd, 0x0080 }, /* R2013 (0x7dd) - SLIMTX4MIX Input 3 Volume */
{ 0x000007de, 0x0000 }, /* R2014 (0x7de) - SLIMTX4MIX Input 4 Source */
{ 0x000007df, 0x0080 }, /* R2015 (0x7df) - SLIMTX4MIX Input 4 Volume */
{ 0x000007e0, 0x0000 }, /* R2016 (0x7e0) - SLIMTX5MIX Input 1 Source */
{ 0x000007e1, 0x0080 }, /* R2017 (0x7e1) - SLIMTX5MIX Input 1 Volume */
{ 0x000007e2, 0x0000 }, /* R2018 (0x7e2) - SLIMTX5MIX Input 2 Source */
{ 0x000007e3, 0x0080 }, /* R2019 (0x7e3) - SLIMTX5MIX Input 2 Volume */
{ 0x000007e4, 0x0000 }, /* R2020 (0x7e4) - SLIMTX5MIX Input 3 Source */
{ 0x000007e5, 0x0080 }, /* R2021 (0x7e5) - SLIMTX5MIX Input 3 Volume */
{ 0x000007e6, 0x0000 }, /* R2022 (0x7e6) - SLIMTX5MIX Input 4 Source */
{ 0x000007e7, 0x0080 }, /* R2023 (0x7e7) - SLIMTX5MIX Input 4 Volume */
{ 0x000007e8, 0x0000 }, /* R2024 (0x7e8) - SLIMTX6MIX Input 1 Source */
{ 0x000007e9, 0x0080 }, /* R2025 (0x7e9) - SLIMTX6MIX Input 1 Volume */
{ 0x000007ea, 0x0000 }, /* R2026 (0x7ea) - SLIMTX6MIX Input 2 Source */
{ 0x000007eb, 0x0080 }, /* R2027 (0x7eb) - SLIMTX6MIX Input 2 Volume */
{ 0x000007ec, 0x0000 }, /* R2028 (0x7ec) - SLIMTX6MIX Input 3 Source */
{ 0x000007ed, 0x0080 }, /* R2029 (0x7ed) - SLIMTX6MIX Input 3 Volume */
{ 0x000007ee, 0x0000 }, /* R2030 (0x7ee) - SLIMTX6MIX Input 4 Source */
{ 0x000007ef, 0x0080 }, /* R2031 (0x7ef) - SLIMTX6MIX Input 4 Volume */
{ 0x00000800, 0x0000 }, /* R2048 (0x800) - SPDIF1TX1MIX Input 1 Source*/
{ 0x00000801, 0x0080 }, /* R2049 (0x801) - SPDIF1TX1MIX Input 1 Volume*/
{ 0x00000808, 0x0000 }, /* R2056 (0x808) - SPDIF1TX2MIX Input 1 Source*/
{ 0x00000809, 0x0080 }, /* R2057 (0x809) - SPDIF1TX2MIX Input 1 Volume*/
{ 0x00000880, 0x0000 }, /* R2176 (0x880) - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 (0x881) - EQ1MIX Input 1 Volume */
{ 0x00000882, 0x0000 }, /* R2178 (0x882) - EQ1MIX Input 2 Source */
{ 0x00000883, 0x0080 }, /* R2179 (0x883) - EQ1MIX Input 2 Volume */
{ 0x00000884, 0x0000 }, /* R2180 (0x884) - EQ1MIX Input 3 Source */
{ 0x00000885, 0x0080 }, /* R2181 (0x885) - EQ1MIX Input 3 Volume */
{ 0x00000886, 0x0000 }, /* R2182 (0x886) - EQ1MIX Input 4 Source */
{ 0x00000887, 0x0080 }, /* R2183 (0x887) - EQ1MIX Input 4 Volume */
{ 0x00000888, 0x0000 }, /* R2184 (0x888) - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 (0x889) - EQ2MIX Input 1 Volume */
{ 0x0000088a, 0x0000 }, /* R2186 (0x88a) - EQ2MIX Input 2 Source */
{ 0x0000088b, 0x0080 }, /* R2187 (0x88b) - EQ2MIX Input 2 Volume */
{ 0x0000088c, 0x0000 }, /* R2188 (0x88c) - EQ2MIX Input 3 Source */
{ 0x0000088d, 0x0080 }, /* R2189 (0x88d) - EQ2MIX Input 3 Volume */
{ 0x0000088e, 0x0000 }, /* R2190 (0x88e) - EQ2MIX Input 4 Source */
{ 0x0000088f, 0x0080 }, /* R2191 (0x88f) - EQ2MIX Input 4 Volume */
{ 0x00000890, 0x0000 }, /* R2192 (0x890) - EQ3MIX Input 1 Source */
{ 0x00000891, 0x0080 }, /* R2193 (0x891) - EQ3MIX Input 1 Volume */
{ 0x00000892, 0x0000 }, /* R2194 (0x892) - EQ3MIX Input 2 Source */
{ 0x00000893, 0x0080 }, /* R2195 (0x893) - EQ3MIX Input 2 Volume */
{ 0x00000894, 0x0000 }, /* R2196 (0x894) - EQ3MIX Input 3 Source */
{ 0x00000895, 0x0080 }, /* R2197 (0x895) - EQ3MIX Input 3 Volume */
{ 0x00000896, 0x0000 }, /* R2198 (0x896) - EQ3MIX Input 4 Source */
{ 0x00000897, 0x0080 }, /* R2199 (0x897) - EQ3MIX Input 4 Volume */
{ 0x00000898, 0x0000 }, /* R2200 (0x898) - EQ4MIX Input 1 Source */
{ 0x00000899, 0x0080 }, /* R2201 (0x899) - EQ4MIX Input 1 Volume */
{ 0x0000089a, 0x0000 }, /* R2202 (0x89a) - EQ4MIX Input 2 Source */
{ 0x0000089b, 0x0080 }, /* R2203 (0x89b) - EQ4MIX Input 2 Volume */
{ 0x0000089c, 0x0000 }, /* R2204 (0x89c) - EQ4MIX Input 3 Source */
{ 0x0000089d, 0x0080 }, /* R2205 (0x89d) - EQ4MIX Input 3 Volume */
{ 0x0000089e, 0x0000 }, /* R2206 (0x89e) - EQ4MIX Input 4 Source */
{ 0x0000089f, 0x0080 }, /* R2207 (0x89f) - EQ4MIX Input 4 Volume */
{ 0x000008c0, 0x0000 }, /* R2240 (0x8c0) - DRC1LMIX Input 1 Source */
{ 0x000008c1, 0x0080 }, /* R2241 (0x8c1) - DRC1LMIX Input 1 Volume */
{ 0x000008c2, 0x0000 }, /* R2242 (0x8c2) - DRC1LMIX Input 2 Source */
{ 0x000008c3, 0x0080 }, /* R2243 (0x8c3) - DRC1LMIX Input 2 Volume */
{ 0x000008c4, 0x0000 }, /* R2244 (0x8c4) - DRC1LMIX Input 3 Source */
{ 0x000008c5, 0x0080 }, /* R2245 (0x8c5) - DRC1LMIX Input 3 Volume */
{ 0x000008c6, 0x0000 }, /* R2246 (0x8c6) - DRC1LMIX Input 4 Source */
{ 0x000008c7, 0x0080 }, /* R2247 (0x8c7) - DRC1LMIX Input 4 Volume */
{ 0x000008c8, 0x0000 }, /* R2248 (0x8c8) - DRC1RMIX Input 1 Source */
{ 0x000008c9, 0x0080 }, /* R2249 (0x8c9) - DRC1RMIX Input 1 Volume */
{ 0x000008ca, 0x0000 }, /* R2250 (0x8ca) - DRC1RMIX Input 2 Source */
{ 0x000008cb, 0x0080 }, /* R2251 (0x8cb) - DRC1RMIX Input 2 Volume */
{ 0x000008cc, 0x0000 }, /* R2252 (0x8cc) - DRC1RMIX Input 3 Source */
{ 0x000008cd, 0x0080 }, /* R2253 (0x8cd) - DRC1RMIX Input 3 Volume */
{ 0x000008ce, 0x0000 }, /* R2254 (0x8ce) - DRC1RMIX Input 4 Source */
{ 0x000008cf, 0x0080 }, /* R2255 (0x8cf) - DRC1RMIX Input 4 Volume */
{ 0x000008d0, 0x0000 }, /* R2256 (0x8d0) - DRC2LMIX Input 1 Source */
{ 0x000008d1, 0x0080 }, /* R2257 (0x8d1) - DRC2LMIX Input 1 Volume */
{ 0x000008d2, 0x0000 }, /* R2258 (0x8d2) - DRC2LMIX Input 2 Source */
{ 0x000008d3, 0x0080 }, /* R2259 (0x8d3) - DRC2LMIX Input 2 Volume */
{ 0x000008d4, 0x0000 }, /* R2260 (0x8d4) - DRC2LMIX Input 3 Source */
{ 0x000008d5, 0x0080 }, /* R2261 (0x8d5) - DRC2LMIX Input 3 Volume */
{ 0x000008d6, 0x0000 }, /* R2262 (0x8d6) - DRC2LMIX Input 4 Source */
{ 0x000008d7, 0x0080 }, /* R2263 (0x8d7) - DRC2LMIX Input 4 Volume */
{ 0x000008d8, 0x0000 }, /* R2264 (0x8d8) - DRC2RMIX Input 1 Source */
{ 0x000008d9, 0x0080 }, /* R2265 (0x8d9) - DRC2RMIX Input 1 Volume */
{ 0x000008da, 0x0000 }, /* R2266 (0x8da) - DRC2RMIX Input 2 Source */
{ 0x000008db, 0x0080 }, /* R2267 (0x8db) - DRC2RMIX Input 2 Volume */
{ 0x000008dc, 0x0000 }, /* R2268 (0x8dc) - DRC2RMIX Input 3 Source */
{ 0x000008dd, 0x0080 }, /* R2269 (0x8dd) - DRC2RMIX Input 3 Volume */
{ 0x000008de, 0x0000 }, /* R2270 (0x8de) - DRC2RMIX Input 4 Source */
{ 0x000008df, 0x0080 }, /* R2271 (0x8df) - DRC2RMIX Input 4 Volume */
{ 0x00000900, 0x0000 }, /* R2304 (0x900) - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 (0x901) - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 (0x902) - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 (0x903) - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 (0x904) - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 (0x905) - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 (0x906) - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 (0x907) - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 (0x908) - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 (0x909) - HPLP2MIX Input 1 Volume */
{ 0x0000090a, 0x0000 }, /* R2314 (0x90a) - HPLP2MIX Input 2 Source */
{ 0x0000090b, 0x0080 }, /* R2315 (0x90b) - HPLP2MIX Input 2 Volume */
{ 0x0000090c, 0x0000 }, /* R2316 (0x90c) - HPLP2MIX Input 3 Source */
{ 0x0000090d, 0x0080 }, /* R2317 (0x90d) - HPLP2MIX Input 3 Volume */
{ 0x0000090e, 0x0000 }, /* R2318 (0x90e) - HPLP2MIX Input 4 Source */
{ 0x0000090f, 0x0080 }, /* R2319 (0x90f) - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 (0x910) - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 (0x911) - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 (0x912) - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 (0x913) - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 (0x914) - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 (0x915) - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 (0x916) - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 (0x917) - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 (0x918) - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 (0x919) - HPLP4MIX Input 1 Volume */
{ 0x0000091a, 0x0000 }, /* R2330 (0x91a) - HPLP4MIX Input 2 Source */
{ 0x0000091b, 0x0080 }, /* R2331 (0x91b) - HPLP4MIX Input 2 Volume */
{ 0x0000091c, 0x0000 }, /* R2332 (0x91c) - HPLP4MIX Input 3 Source */
{ 0x0000091d, 0x0080 }, /* R2333 (0x91d) - HPLP4MIX Input 3 Volume */
{ 0x0000091e, 0x0000 }, /* R2334 (0x91e) - HPLP4MIX Input 4 Source */
{ 0x0000091f, 0x0080 }, /* R2335 (0x91f) - HPLP4MIX Input 4 Volume */
{ 0x00000940, 0x0000 }, /* R2368 (0x940) - DSP1LMIX Input 1 Source */
{ 0x00000941, 0x0080 }, /* R2369 (0x941) - DSP1LMIX Input 1 Volume */
{ 0x00000942, 0x0000 }, /* R2370 (0x942) - DSP1LMIX Input 2 Source */
{ 0x00000943, 0x0080 }, /* R2371 (0x943) - DSP1LMIX Input 2 Volume */
{ 0x00000944, 0x0000 }, /* R2372 (0x944) - DSP1LMIX Input 3 Source */
{ 0x00000945, 0x0080 }, /* R2373 (0x945) - DSP1LMIX Input 3 Volume */
{ 0x00000946, 0x0000 }, /* R2374 (0x946) - DSP1LMIX Input 4 Source */
{ 0x00000947, 0x0080 }, /* R2375 (0x947) - DSP1LMIX Input 4 Volume */
{ 0x00000948, 0x0000 }, /* R2376 (0x948) - DSP1RMIX Input 1 Source */
{ 0x00000949, 0x0080 }, /* R2377 (0x949) - DSP1RMIX Input 1 Volume */
{ 0x0000094a, 0x0000 }, /* R2378 (0x94a) - DSP1RMIX Input 2 Source */
{ 0x0000094b, 0x0080 }, /* R2379 (0x94b) - DSP1RMIX Input 2 Volume */
{ 0x0000094c, 0x0000 }, /* R2380 (0x94c) - DSP1RMIX Input 3 Source */
{ 0x0000094d, 0x0080 }, /* R2381 (0x94d) - DSP1RMIX Input 3 Volume */
{ 0x0000094e, 0x0000 }, /* R2382 (0x94e) - DSP1RMIX Input 4 Source */
{ 0x0000094f, 0x0080 }, /* R2383 (0x94f) - DSP1RMIX Input 4 Volume */
{ 0x00000950, 0x0000 }, /* R2384 (0x950) - DSP1AUX1MIX Input 1 Source */
{ 0x00000958, 0x0000 }, /* R2392 (0x958) - DSP1AUX2MIX Input 1 Source */
{ 0x00000960, 0x0000 }, /* R2400 (0x960) - DSP1AUX3MIX Input 1 Source */
{ 0x00000968, 0x0000 }, /* R2408 (0x968) - DSP1AUX4MIX Input 1 Source */
{ 0x00000970, 0x0000 }, /* R2416 (0x970) - DSP1AUX5MIX Input 1 Source */
{ 0x00000978, 0x0000 }, /* R2424 (0x978) - DSP1AUX6MIX Input 1 Source */
{ 0x00000980, 0x0000 }, /* R2432 (0x980) - DSP2LMIX Input 1 Source */
{ 0x00000981, 0x0080 }, /* R2433 (0x981) - DSP2LMIX Input 1 Volume */
{ 0x00000982, 0x0000 }, /* R2434 (0x982) - DSP2LMIX Input 2 Source */
{ 0x00000983, 0x0080 }, /* R2435 (0x983) - DSP2LMIX Input 2 Volume */
{ 0x00000984, 0x0000 }, /* R2436 (0x984) - DSP2LMIX Input 3 Source */
{ 0x00000985, 0x0080 }, /* R2437 (0x985) - DSP2LMIX Input 3 Volume */
{ 0x00000986, 0x0000 }, /* R2438 (0x986) - DSP2LMIX Input 4 Source */
{ 0x00000987, 0x0080 }, /* R2439 (0x987) - DSP2LMIX Input 4 Volume */
{ 0x00000988, 0x0000 }, /* R2440 (0x988) - DSP2RMIX Input 1 Source */
{ 0x00000989, 0x0080 }, /* R2441 (0x989) - DSP2RMIX Input 1 Volume */
{ 0x0000098a, 0x0000 }, /* R2442 (0x98a) - DSP2RMIX Input 2 Source */
{ 0x0000098b, 0x0080 }, /* R2443 (0x98b) - DSP2RMIX Input 2 Volume */
{ 0x0000098c, 0x0000 }, /* R2444 (0x98c) - DSP2RMIX Input 3 Source */
{ 0x0000098d, 0x0080 }, /* R2445 (0x98d) - DSP2RMIX Input 3 Volume */
{ 0x0000098e, 0x0000 }, /* R2446 (0x98e) - DSP2RMIX Input 4 Source */
{ 0x0000098f, 0x0080 }, /* R2447 (0x98f) - DSP2RMIX Input 4 Volume */
{ 0x00000990, 0x0000 }, /* R2448 (0x990) - DSP2AUX1MIX Input 1 Source */
{ 0x00000998, 0x0000 }, /* R2456 (0x998) - DSP2AUX2MIX Input 1 Source */
{ 0x000009a0, 0x0000 }, /* R2464 (0x9a0) - DSP2AUX3MIX Input 1 Source */
{ 0x000009a8, 0x0000 }, /* R2472 (0x9a8) - DSP2AUX4MIX Input 1 Source */
{ 0x000009b0, 0x0000 }, /* R2480 (0x9b0) - DSP2AUX5MIX Input 1 Source */
{ 0x000009b8, 0x0000 }, /* R2488 (0x9b8) - DSP2AUX6MIX Input 1 Source */
{ 0x000009c0, 0x0000 }, /* R2496 (0x9c0) - DSP3LMIX Input 1 Source */
{ 0x000009c1, 0x0080 }, /* R2497 (0x9c1) - DSP3LMIX Input 1 Volume */
{ 0x000009c2, 0x0000 }, /* R2498 (0x9c2) - DSP3LMIX Input 2 Source */
{ 0x000009c3, 0x0080 }, /* R2499 (0x9c3) - DSP3LMIX Input 2 Volume */
{ 0x000009c4, 0x0000 }, /* R2500 (0x9c4) - DSP3LMIX Input 3 Source */
{ 0x000009c5, 0x0080 }, /* R2501 (0x9c5) - DSP3LMIX Input 3 Volume */
{ 0x000009c6, 0x0000 }, /* R2502 (0x9c6) - DSP3LMIX Input 4 Source */
{ 0x000009c7, 0x0080 }, /* R2503 (0x9c7) - DSP3LMIX Input 4 Volume */
{ 0x000009c8, 0x0000 }, /* R2504 (0x9c8) - DSP3RMIX Input 1 Source */
{ 0x000009c9, 0x0080 }, /* R2505 (0x9c9) - DSP3RMIX Input 1 Volume */
{ 0x000009ca, 0x0000 }, /* R2506 (0x9ca) - DSP3RMIX Input 2 Source */
{ 0x000009cb, 0x0080 }, /* R2507 (0x9cb) - DSP3RMIX Input 2 Volume */
{ 0x000009cc, 0x0000 }, /* R2508 (0x9cc) - DSP3RMIX Input 3 Source */
{ 0x000009cd, 0x0080 }, /* R2509 (0x9cd) - DSP3RMIX Input 3 Volume */
{ 0x000009ce, 0x0000 }, /* R2510 (0x9ce) - DSP3RMIX Input 4 Source */
{ 0x000009cf, 0x0080 }, /* R2511 (0x9cf) - DSP3RMIX Input 4 Volume */
{ 0x000009d0, 0x0000 }, /* R2512 (0x9d0) - DSP3AUX1MIX Input 1 Source */
{ 0x000009d8, 0x0000 }, /* R2520 (0x9d8) - DSP3AUX2MIX Input 1 Source */
{ 0x000009e0, 0x0000 }, /* R2528 (0x9e0) - DSP3AUX3MIX Input 1 Source */
{ 0x000009e8, 0x0000 }, /* R2536 (0x9e8) - DSP3AUX4MIX Input 1 Source */
{ 0x000009f0, 0x0000 }, /* R2544 (0x9f0) - DSP3AUX5MIX Input 1 Source */
{ 0x000009f8, 0x0000 }, /* R2552 (0x9f8) - DSP3AUX6MIX Input 1 Source */
{ 0x00000b00, 0x0000 }, /* R2816 (0xb00) - ISRC1DEC1MIX Input 1 Source*/
{ 0x00000b08, 0x0000 }, /* R2824 (0xb08) - ISRC1DEC2MIX Input 1 Source*/
{ 0x00000b10, 0x0000 }, /* R2832 (0xb10) - ISRC1DEC3MIX Input 1 Source*/
{ 0x00000b18, 0x0000 }, /* R2840 (0xb18) - ISRC1DEC4MIX Input 1 Source*/
{ 0x00000b20, 0x0000 }, /* R2848 (0xb20) - ISRC1INT1MIX Input 1 Source*/
{ 0x00000b28, 0x0000 }, /* R2856 (0xb28) - ISRC1INT2MIX Input 1 Source*/
{ 0x00000b30, 0x0000 }, /* R2864 (0xb30) - ISRC1INT3MIX Input 1 Source*/
{ 0x00000b38, 0x0000 }, /* R2872 (0xb38) - ISRC1INT4MIX Input 1 Source*/
{ 0x00000b40, 0x0000 }, /* R2880 (0xb40) - ISRC2DEC1MIX Input 1 Source*/
{ 0x00000b48, 0x0000 }, /* R2888 (0xb48) - ISRC2DEC2MIX Input 1 Source*/
{ 0x00000b50, 0x0000 }, /* R2896 (0xb50) - ISRC2DEC3MIX Input 1 Source*/
{ 0x00000b58, 0x0000 }, /* R2904 (0xb58) - ISRC2DEC4MIX Input 1 Source*/
{ 0x00000b60, 0x0000 }, /* R2912 (0xb60) - ISRC2INT1MIX Input 1 Source*/
{ 0x00000b68, 0x0000 }, /* R2920 (0xb68) - ISRC2INT2MIX Input 1 Source*/
{ 0x00000b70, 0x0000 }, /* R2928 (0xb70) - ISRC2INT3MIX Input 1 Source*/
{ 0x00000b78, 0x0000 }, /* R2936 (0xb78) - ISRC2INT4MIX Input 1 Source*/
{ 0x00000e00, 0x0000 }, /* R3584 (0xe00) - FX Ctrl1 */
{ 0x00000e10, 0x6318 }, /* R3600 (0xe10) - EQ1_1 */
{ 0x00000e11, 0x6300 }, /* R3601 (0xe11) - EQ1_2 */
{ 0x00000e12, 0x0fc8 }, /* R3602 (0xe12) - EQ1_3 */
{ 0x00000e13, 0x03fe }, /* R3603 (0xe13) - EQ1_4 */
{ 0x00000e14, 0x00e0 }, /* R3604 (0xe14) - EQ1_5 */
{ 0x00000e15, 0x1ec4 }, /* R3605 (0xe15) - EQ1_6 */
{ 0x00000e16, 0xf136 }, /* R3606 (0xe16) - EQ1_7 */
{ 0x00000e17, 0x0409 }, /* R3607 (0xe17) - EQ1_8 */
{ 0x00000e18, 0x04cc }, /* R3608 (0xe18) - EQ1_9 */
{ 0x00000e19, 0x1c9b }, /* R3609 (0xe19) - EQ1_10 */
{ 0x00000e1a, 0xf337 }, /* R3610 (0xe1a) - EQ1_11 */
{ 0x00000e1b, 0x040b }, /* R3611 (0xe1b) - EQ1_12 */
{ 0x00000e1c, 0x0cbb }, /* R3612 (0xe1c) - EQ1_13 */
{ 0x00000e1d, 0x16f8 }, /* R3613 (0xe1d) - EQ1_14 */
{ 0x00000e1e, 0xf7d9 }, /* R3614 (0xe1e) - EQ1_15 */
{ 0x00000e1f, 0x040a }, /* R3615 (0xe1f) - EQ1_16 */
{ 0x00000e20, 0x1f14 }, /* R3616 (0xe20) - EQ1_17 */
{ 0x00000e21, 0x058c }, /* R3617 (0xe21) - EQ1_18 */
{ 0x00000e22, 0x0563 }, /* R3618 (0xe22) - EQ1_19 */
{ 0x00000e23, 0x4000 }, /* R3619 (0xe23) - EQ1_20 */
{ 0x00000e24, 0x0b75 }, /* R3620 (0xe24) - EQ1_21 */
{ 0x00000e26, 0x6318 }, /* R3622 (0xe26) - EQ2_1 */
{ 0x00000e27, 0x6300 }, /* R3623 (0xe27) - EQ2_2 */
{ 0x00000e28, 0x0fc8 }, /* R3624 (0xe28) - EQ2_3 */
{ 0x00000e29, 0x03fe }, /* R3625 (0xe29) - EQ2_4 */
{ 0x00000e2a, 0x00e0 }, /* R3626 (0xe2a) - EQ2_5 */
{ 0x00000e2b, 0x1ec4 }, /* R3627 (0xe2b) - EQ2_6 */
{ 0x00000e2c, 0xf136 }, /* R3628 (0xe2c) - EQ2_7 */
{ 0x00000e2d, 0x0409 }, /* R3629 (0xe2d) - EQ2_8 */
{ 0x00000e2e, 0x04cc }, /* R3630 (0xe2e) - EQ2_9 */
{ 0x00000e2f, 0x1c9b }, /* R3631 (0xe2f) - EQ2_10 */
{ 0x00000e30, 0xf337 }, /* R3632 (0xe30) - EQ2_11 */
{ 0x00000e31, 0x040b }, /* R3633 (0xe31) - EQ2_12 */
{ 0x00000e32, 0x0cbb }, /* R3634 (0xe32) - EQ2_13 */
{ 0x00000e33, 0x16f8 }, /* R3635 (0xe33) - EQ2_14 */
{ 0x00000e34, 0xf7d9 }, /* R3636 (0xe34) - EQ2_15 */
{ 0x00000e35, 0x040a }, /* R3637 (0xe35) - EQ2_16 */
{ 0x00000e36, 0x1f14 }, /* R3638 (0xe36) - EQ2_17 */
{ 0x00000e37, 0x058c }, /* R3639 (0xe37) - EQ2_18 */
{ 0x00000e38, 0x0563 }, /* R3640 (0xe38) - EQ2_19 */
{ 0x00000e39, 0x4000 }, /* R3641 (0xe39) - EQ2_20 */
{ 0x00000e3a, 0x0b75 }, /* R3642 (0xe3a) - EQ2_21 */
{ 0x00000e3c, 0x6318 }, /* R3644 (0xe3c) - EQ3_1 */
{ 0x00000e3d, 0x6300 }, /* R3645 (0xe3d) - EQ3_2 */
{ 0x00000e3e, 0x0fc8 }, /* R3646 (0xe3e) - EQ3_3 */
{ 0x00000e3f, 0x03fe }, /* R3647 (0xe3f) - EQ3_4 */
{ 0x00000e40, 0x00e0 }, /* R3648 (0xe40) - EQ3_5 */
{ 0x00000e41, 0x1ec4 }, /* R3649 (0xe41) - EQ3_6 */
{ 0x00000e42, 0xf136 }, /* R3650 (0xe42) - EQ3_7 */
{ 0x00000e43, 0x0409 }, /* R3651 (0xe43) - EQ3_8 */
{ 0x00000e44, 0x04cc }, /* R3652 (0xe44) - EQ3_9 */
{ 0x00000e45, 0x1c9b }, /* R3653 (0xe45) - EQ3_10 */
{ 0x00000e46, 0xf337 }, /* R3654 (0xe46) - EQ3_11 */
{ 0x00000e47, 0x040b }, /* R3655 (0xe47) - EQ3_12 */
{ 0x00000e48, 0x0cbb }, /* R3656 (0xe48) - EQ3_13 */
{ 0x00000e49, 0x16f8 }, /* R3657 (0xe49) - EQ3_14 */
{ 0x00000e4a, 0xf7d9 }, /* R3658 (0xe4a) - EQ3_15 */
{ 0x00000e4b, 0x040a }, /* R3659 (0xe4b) - EQ3_16 */
{ 0x00000e4c, 0x1f14 }, /* R3660 (0xe4c) - EQ3_17 */
{ 0x00000e4d, 0x058c }, /* R3661 (0xe4d) - EQ3_18 */
{ 0x00000e4e, 0x0563 }, /* R3662 (0xe4e) - EQ3_19 */
{ 0x00000e4f, 0x4000 }, /* R3663 (0xe4f) - EQ3_20 */
{ 0x00000e50, 0x0b75 }, /* R3664 (0xe50) - EQ3_21 */
{ 0x00000e52, 0x6318 }, /* R3666 (0xe52) - EQ4_1 */
{ 0x00000e53, 0x6300 }, /* R3667 (0xe53) - EQ4_2 */
{ 0x00000e54, 0x0fc8 }, /* R3668 (0xe54) - EQ4_3 */
{ 0x00000e55, 0x03fe }, /* R3669 (0xe55) - EQ4_4 */
{ 0x00000e56, 0x00e0 }, /* R3670 (0xe56) - EQ4_5 */
{ 0x00000e57, 0x1ec4 }, /* R3671 (0xe57) - EQ4_6 */
{ 0x00000e58, 0xf136 }, /* R3672 (0xe58) - EQ4_7 */
{ 0x00000e59, 0x0409 }, /* R3673 (0xe59) - EQ4_8 */
{ 0x00000e5a, 0x04cc }, /* R3674 (0xe5a) - EQ4_9 */
{ 0x00000e5b, 0x1c9b }, /* R3675 (0xe5b) - EQ4_10 */
{ 0x00000e5c, 0xf337 }, /* R3676 (0xe5c) - EQ4_11 */
{ 0x00000e5d, 0x040b }, /* R3677 (0xe5d) - EQ4_12 */
{ 0x00000e5e, 0x0cbb }, /* R3678 (0xe5e) - EQ4_13 */
{ 0x00000e5f, 0x16f8 }, /* R3679 (0xe5f) - EQ4_14 */
{ 0x00000e60, 0xf7d9 }, /* R3680 (0xe60) - EQ4_15 */
{ 0x00000e61, 0x040a }, /* R3681 (0xe61) - EQ4_16 */
{ 0x00000e62, 0x1f14 }, /* R3682 (0xe62) - EQ4_17 */
{ 0x00000e63, 0x058c }, /* R3683 (0xe63) - EQ4_18 */
{ 0x00000e64, 0x0563 }, /* R3684 (0xe64) - EQ4_19 */
{ 0x00000e65, 0x4000 }, /* R3685 (0xe65) - EQ4_20 */
{ 0x00000e66, 0x0b75 }, /* R3686 (0xe66) - EQ4_21 */
{ 0x00000e80, 0x0018 }, /* R3712 (0xe80) - DRC1 ctrl1 */
{ 0x00000e81, 0x0933 }, /* R3713 (0xe81) - DRC1 ctrl2 */
{ 0x00000e82, 0x0018 }, /* R3714 (0xe82) - DRC1 ctrl3 */
{ 0x00000e83, 0x0000 }, /* R3715 (0xe83) - DRC1 ctrl4 */
{ 0x00000e84, 0x0000 }, /* R3716 (0xe84) - DRC1 ctrl5 */
{ 0x00000e88, 0x0018 }, /* R3720 (0xe88) - DRC2 ctrl1 */
{ 0x00000e89, 0x0933 }, /* R3721 (0xe89) - DRC2 ctrl2 */
{ 0x00000e8a, 0x0018 }, /* R3722 (0xe8a) - DRC2 ctrl3 */
{ 0x00000e8b, 0x0000 }, /* R3723 (0xe8b) - DRC2 ctrl4 */
{ 0x00000e8c, 0x0000 }, /* R3724 (0xe8c) - DRC2 ctrl5 */
{ 0x00000ec0, 0x0000 }, /* R3776 (0xec0) - HPLPF1_1 */
{ 0x00000ec1, 0x0000 }, /* R3777 (0xec1) - HPLPF1_2 */
{ 0x00000ec4, 0x0000 }, /* R3780 (0xec4) - HPLPF2_1 */
{ 0x00000ec5, 0x0000 }, /* R3781 (0xec5) - HPLPF2_2 */
{ 0x00000ec8, 0x0000 }, /* R3784 (0xec8) - HPLPF3_1 */
{ 0x00000ec9, 0x0000 }, /* R3785 (0xec9) - HPLPF3_2 */
{ 0x00000ecc, 0x0000 }, /* R3788 (0xecc) - HPLPF4_1 */
{ 0x00000ecd, 0x0000 }, /* R3789 (0xecd) - HPLPF4_2 */
{ 0x00000ef0, 0x0000 }, /* R3824 (0xef0) - ISRC 1 CTRL 1 */
{ 0x00000ef1, 0x0001 }, /* R3825 (0xef1) - ISRC 1 CTRL 2 */
{ 0x00000ef2, 0x0000 }, /* R3826 (0xef2) - ISRC 1 CTRL 3 */
{ 0x00000ef3, 0x0000 }, /* R3827 (0xef3) - ISRC 2 CTRL 1 */
{ 0x00000ef4, 0x0001 }, /* R3828 (0xef4) - ISRC 2 CTRL 2 */
{ 0x00000ef5, 0x0000 }, /* R3829 (0xef5) - ISRC 2 CTRL 3 */
{ 0x00001700, 0x2001 }, /* R5888 (0x1700) - GPIO1 Control 1 */
{ 0x00001701, 0xf000 }, /* R5889 (0x1701) - GPIO1 Control 2 */
{ 0x00001702, 0x2001 }, /* R5890 (0x1702) - GPIO2 Control 1 */
{ 0x00001703, 0xf000 }, /* R5891 (0x1703) - GPIO2 Control 2 */
{ 0x00001704, 0x2001 }, /* R5892 (0x1704) - GPIO3 Control 1 */
{ 0x00001705, 0xf000 }, /* R5893 (0x1705) - GPIO3 Control 2 */
{ 0x00001706, 0x2001 }, /* R5894 (0x1706) - GPIO4 Control 1 */
{ 0x00001707, 0xf000 }, /* R5895 (0x1707) - GPIO4 Control 2 */
{ 0x00001708, 0x2001 }, /* R5896 (0x1708) - GPIO5 Control 1 */
{ 0x00001709, 0xf000 }, /* R5897 (0x1709) - GPIO5 Control 2 */
{ 0x0000170a, 0x2001 }, /* R5898 (0x170a) - GPIO6 Control 1 */
{ 0x0000170b, 0xf000 }, /* R5899 (0x170b) - GPIO6 Control 2 */
{ 0x0000170c, 0x2001 }, /* R5900 (0x170c) - GPIO7 Control 1 */
{ 0x0000170d, 0xf000 }, /* R5901 (0x170d) - GPIO7 Control 2 */
{ 0x0000170e, 0x2001 }, /* R5902 (0x170e) - GPIO8 Control 1 */
{ 0x0000170f, 0xf000 }, /* R5903 (0x170f) - GPIO8 Control 2 */
{ 0x00001710, 0x2001 }, /* R5904 (0x1710) - GPIO9 Control 1 */
{ 0x00001711, 0xf000 }, /* R5905 (0x1711) - GPIO9 Control 2 */
{ 0x00001712, 0x2001 }, /* R5906 (0x1712) - GPIO10 Control 1 */
{ 0x00001713, 0xf000 }, /* R5907 (0x1713) - GPIO10 Control 2 */
{ 0x00001714, 0x2001 }, /* R5908 (0x1714) - GPIO11 Control 1 */
{ 0x00001715, 0xf000 }, /* R5909 (0x1715) - GPIO11 Control 2 */
{ 0x00001716, 0x2001 }, /* R5910 (0x1716) - GPIO12 Control 1 */
{ 0x00001717, 0xf000 }, /* R5911 (0x1717) - GPIO12 Control 2 */
{ 0x00001718, 0x2001 }, /* R5912 (0x1718) - GPIO13 Control 1 */
{ 0x00001719, 0xf000 }, /* R5913 (0x1719) - GPIO13 Control 2 */
{ 0x0000171a, 0x2001 }, /* R5914 (0x171a) - GPIO14 Control 1 */
{ 0x0000171b, 0xf000 }, /* R5915 (0x171b) - GPIO14 Control 2 */
{ 0x0000171c, 0x2001 }, /* R5916 (0x171c) - GPIO15 Control 1 */
{ 0x0000171d, 0xf000 }, /* R5917 (0x171d) - GPIO15 Control 2 */
{ 0x0000171e, 0x2001 }, /* R5918 (0x171e) - GPIO16 Control 1 */
{ 0x0000171f, 0xf000 }, /* R5919 (0x171f) - GPIO16 Control 2 */
{ 0x00001840, 0xffff }, /* R6208 (0x1840) - IRQ1 Mask 1 */
{ 0x00001841, 0xffff }, /* R6209 (0x1841) - IRQ1 Mask 2 */
{ 0x00001842, 0xffff }, /* R6210 (0x1842) - IRQ1 Mask 3 */
{ 0x00001843, 0xffff }, /* R6211 (0x1843) - IRQ1 Mask 4 */
{ 0x00001844, 0xffff }, /* R6212 (0x1844) - IRQ1 Mask 5 */
{ 0x00001845, 0xffff }, /* R6213 (0x1845) - IRQ1 Mask 6 */
{ 0x00001846, 0xffff }, /* R6214 (0x1846) - IRQ1 Mask 7 */
{ 0x00001847, 0xffff }, /* R6215 (0x1847) - IRQ1 Mask 8 */
{ 0x00001848, 0xffff }, /* R6216 (0x1848) - IRQ1 Mask 9 */
{ 0x00001849, 0xffff }, /* R6217 (0x1849) - IRQ1 Mask 10 */
{ 0x0000184a, 0xffff }, /* R6218 (0x184a) - IRQ1 Mask 11 */
{ 0x0000184b, 0xffff }, /* R6219 (0x184b) - IRQ1 Mask 12 */
{ 0x0000184c, 0xffff }, /* R6220 (0x184c) - IRQ1 Mask 13 */
{ 0x0000184d, 0xffff }, /* R6221 (0x184d) - IRQ1 Mask 14 */
{ 0x0000184e, 0xffff }, /* R6222 (0x184e) - IRQ1 Mask 15 */
{ 0x0000184f, 0xffff }, /* R6223 (0x184f) - IRQ1 Mask 16 */
{ 0x00001850, 0xffff }, /* R6224 (0x1850) - IRQ1 Mask 17 */
{ 0x00001851, 0xffff }, /* R6225 (0x1851) - IRQ1 Mask 18 */
{ 0x00001852, 0xffff }, /* R6226 (0x1852) - IRQ1 Mask 19 */
{ 0x00001853, 0xffff }, /* R6227 (0x1853) - IRQ1 Mask 20 */
{ 0x00001854, 0xffff }, /* R6228 (0x1854) - IRQ1 Mask 21 */
{ 0x00001855, 0xffff }, /* R6229 (0x1855) - IRQ1 Mask 22 */
{ 0x00001856, 0xffff }, /* R6230 (0x1856) - IRQ1 Mask 23 */
{ 0x00001857, 0xffff }, /* R6231 (0x1857) - IRQ1 Mask 24 */
{ 0x00001858, 0xffff }, /* R6232 (0x1858) - IRQ1 Mask 25 */
{ 0x00001859, 0xffff }, /* R6233 (0x1859) - IRQ1 Mask 26 */
{ 0x0000185a, 0xffff }, /* R6234 (0x185a) - IRQ1 Mask 27 */
{ 0x0000185b, 0xffff }, /* R6235 (0x185b) - IRQ1 Mask 28 */
{ 0x0000185c, 0xffff }, /* R6236 (0x185c) - IRQ1 Mask 29 */
{ 0x0000185d, 0xffff }, /* R6237 (0x185d) - IRQ1 Mask 30 */
{ 0x0000185e, 0xffff }, /* R6238 (0x185e) - IRQ1 Mask 31 */
{ 0x0000185f, 0xffff }, /* R6239 (0x185f) - IRQ1 Mask 32 */
{ 0x00001860, 0xffff }, /* R6240 (0x1860) - IRQ1 Mask 33 */
{ 0x00001a06, 0x0000 }, /* R6662 (0x1a06) - Interrupt Debounce 7 */
{ 0x00001a80, 0x4400 }, /* R6784 (0x1a80) - IRQ1 CTRL */
};
static bool cs47l35_is_adsp_memory(unsigned int reg)
{
switch (reg) {
case 0x080000 ... 0x085ffe:
case 0x0a0000 ... 0x0a7ffe:
case 0x0c0000 ... 0x0c1ffe:
case 0x0e0000 ... 0x0e1ffe:
case 0x100000 ... 0x10effe:
case 0x120000 ... 0x12bffe:
case 0x136000 ... 0x137ffe:
case 0x140000 ... 0x14bffe:
case 0x160000 ... 0x161ffe:
case 0x180000 ... 0x18effe:
case 0x1a0000 ... 0x1b1ffe:
case 0x1b6000 ... 0x1b7ffe:
case 0x1c0000 ... 0x1cbffe:
case 0x1e0000 ... 0x1e1ffe:
return true;
default:
return false;
}
}
static bool cs47l35_16bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0:
case MADERA_WRITE_SEQUENCER_CTRL_1:
case MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_TONE_GENERATOR_1:
case MADERA_TONE_GENERATOR_2:
case MADERA_TONE_GENERATOR_3:
case MADERA_TONE_GENERATOR_4:
case MADERA_TONE_GENERATOR_5:
case MADERA_PWM_DRIVE_1:
case MADERA_PWM_DRIVE_2:
case MADERA_PWM_DRIVE_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
case MADERA_HAPTICS_CONTROL_1:
case MADERA_HAPTICS_CONTROL_2:
case MADERA_HAPTICS_PHASE_1_INTENSITY:
case MADERA_HAPTICS_PHASE_1_DURATION:
case MADERA_HAPTICS_PHASE_2_INTENSITY:
case MADERA_HAPTICS_PHASE_2_DURATION:
case MADERA_HAPTICS_PHASE_3_INTENSITY:
case MADERA_HAPTICS_PHASE_3_DURATION:
case MADERA_HAPTICS_STATUS:
case MADERA_COMFORT_NOISE_GENERATOR:
case MADERA_CLOCK_32K_1:
case MADERA_SYSTEM_CLOCK_1:
case MADERA_SAMPLE_RATE_1:
case MADERA_SAMPLE_RATE_2:
case MADERA_SAMPLE_RATE_3:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_DSP_CLOCK_1:
case MADERA_DSP_CLOCK_2:
case MADERA_OUTPUT_SYSTEM_CLOCK:
case MADERA_OUTPUT_ASYNC_CLOCK:
case MADERA_RATE_ESTIMATOR_1:
case MADERA_RATE_ESTIMATOR_2:
case MADERA_RATE_ESTIMATOR_3:
case MADERA_RATE_ESTIMATOR_4:
case MADERA_RATE_ESTIMATOR_5:
case MADERA_FLL1_CONTROL_1:
case MADERA_FLL1_CONTROL_2:
case MADERA_FLL1_CONTROL_3:
case MADERA_FLL1_CONTROL_4:
case MADERA_FLL1_CONTROL_5:
case MADERA_FLL1_CONTROL_6:
case MADERA_FLL1_CONTROL_7:
case MADERA_FLL1_EFS_2:
case CS47L35_FLL1_SYNCHRONISER_1:
case CS47L35_FLL1_SYNCHRONISER_2:
case CS47L35_FLL1_SYNCHRONISER_3:
case CS47L35_FLL1_SYNCHRONISER_4:
case CS47L35_FLL1_SYNCHRONISER_5:
case CS47L35_FLL1_SYNCHRONISER_6:
case CS47L35_FLL1_SYNCHRONISER_7:
case CS47L35_FLL1_SPREAD_SPECTRUM:
case CS47L35_FLL1_GPIO_CLOCK:
case MADERA_MIC_CHARGE_PUMP_1:
case MADERA_HP_CHARGE_PUMP_8:
case MADERA_LDO2_CONTROL_1:
case MADERA_MIC_BIAS_CTRL_1:
case MADERA_MIC_BIAS_CTRL_2:
case MADERA_MIC_BIAS_CTRL_5:
case MADERA_MIC_BIAS_CTRL_6:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_DCS_HP1L_CONTROL:
case MADERA_DCS_HP1R_CONTROL:
case MADERA_EDRE_HP_STEREO_CONTROL:
case MADERA_ACCESSORY_DETECT_MODE_1:
case MADERA_HEADPHONE_DETECT_1:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_MICD_CLAMP_CONTROL:
case MADERA_MIC_DETECT_1_CONTROL_1:
case MADERA_MIC_DETECT_1_CONTROL_2:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_LEVEL_1:
case MADERA_MIC_DETECT_1_LEVEL_2:
case MADERA_MIC_DETECT_1_LEVEL_3:
case MADERA_MIC_DETECT_1_LEVEL_4:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_GP_SWITCH_1:
case MADERA_JACK_DETECT_ANALOGUE:
case MADERA_INPUT_ENABLES:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_INPUT_RATE:
case MADERA_INPUT_VOLUME_RAMP:
case MADERA_HPF_CONTROL:
case MADERA_IN1L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1L:
case MADERA_DMIC1L_CONTROL:
case MADERA_IN1R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1R:
case MADERA_DMIC1R_CONTROL:
case MADERA_IN2L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2L:
case MADERA_DMIC2L_CONTROL:
case MADERA_IN2R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2R:
case MADERA_DMIC2R_CONTROL:
case MADERA_OUTPUT_ENABLES_1:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_OUTPUT_RATE_1:
case MADERA_OUTPUT_VOLUME_RAMP:
case MADERA_OUTPUT_PATH_CONFIG_1L:
case MADERA_DAC_DIGITAL_VOLUME_1L:
case MADERA_NOISE_GATE_SELECT_1L:
case MADERA_OUTPUT_PATH_CONFIG_1R:
case MADERA_DAC_DIGITAL_VOLUME_1R:
case MADERA_NOISE_GATE_SELECT_1R:
case MADERA_OUTPUT_PATH_CONFIG_4L:
case MADERA_DAC_DIGITAL_VOLUME_4L:
case MADERA_NOISE_GATE_SELECT_4L:
case MADERA_OUTPUT_PATH_CONFIG_5L:
case MADERA_DAC_DIGITAL_VOLUME_5L:
case MADERA_NOISE_GATE_SELECT_5L:
case MADERA_OUTPUT_PATH_CONFIG_5R:
case MADERA_DAC_DIGITAL_VOLUME_5R:
case MADERA_NOISE_GATE_SELECT_5R:
case MADERA_DAC_AEC_CONTROL_1:
case MADERA_DAC_AEC_CONTROL_2:
case MADERA_NOISE_GATE_CONTROL:
case MADERA_PDM_SPK1_CTRL_1:
case MADERA_PDM_SPK1_CTRL_2:
case MADERA_HP1_SHORT_CIRCUIT_CTRL:
case MADERA_HP_TEST_CTRL_5:
case MADERA_HP_TEST_CTRL_6:
case MADERA_AIF1_BCLK_CTRL:
case MADERA_AIF1_TX_PIN_CTRL:
case MADERA_AIF1_RX_PIN_CTRL:
case MADERA_AIF1_RATE_CTRL:
case MADERA_AIF1_FORMAT:
case MADERA_AIF1_RX_BCLK_RATE:
case MADERA_AIF1_FRAME_CTRL_1:
case MADERA_AIF1_FRAME_CTRL_2:
case MADERA_AIF1_FRAME_CTRL_3:
case MADERA_AIF1_FRAME_CTRL_4:
case MADERA_AIF1_FRAME_CTRL_5:
case MADERA_AIF1_FRAME_CTRL_6:
case MADERA_AIF1_FRAME_CTRL_7:
case MADERA_AIF1_FRAME_CTRL_8:
case MADERA_AIF1_FRAME_CTRL_11:
case MADERA_AIF1_FRAME_CTRL_12:
case MADERA_AIF1_FRAME_CTRL_13:
case MADERA_AIF1_FRAME_CTRL_14:
case MADERA_AIF1_FRAME_CTRL_15:
case MADERA_AIF1_FRAME_CTRL_16:
case MADERA_AIF1_TX_ENABLES:
case MADERA_AIF1_RX_ENABLES:
case MADERA_AIF2_BCLK_CTRL:
case MADERA_AIF2_TX_PIN_CTRL:
case MADERA_AIF2_RX_PIN_CTRL:
case MADERA_AIF2_RATE_CTRL:
case MADERA_AIF2_FORMAT:
case MADERA_AIF2_RX_BCLK_RATE:
case MADERA_AIF2_FRAME_CTRL_1:
case MADERA_AIF2_FRAME_CTRL_2:
case MADERA_AIF2_FRAME_CTRL_3:
case MADERA_AIF2_FRAME_CTRL_4:
case MADERA_AIF2_FRAME_CTRL_11:
case MADERA_AIF2_FRAME_CTRL_12:
case MADERA_AIF2_TX_ENABLES:
case MADERA_AIF2_RX_ENABLES:
case MADERA_AIF3_BCLK_CTRL:
case MADERA_AIF3_TX_PIN_CTRL:
case MADERA_AIF3_RX_PIN_CTRL:
case MADERA_AIF3_RATE_CTRL:
case MADERA_AIF3_FORMAT:
case MADERA_AIF3_RX_BCLK_RATE:
case MADERA_AIF3_FRAME_CTRL_1:
case MADERA_AIF3_FRAME_CTRL_2:
case MADERA_AIF3_FRAME_CTRL_3:
case MADERA_AIF3_FRAME_CTRL_4:
case MADERA_AIF3_FRAME_CTRL_11:
case MADERA_AIF3_FRAME_CTRL_12:
case MADERA_AIF3_TX_ENABLES:
case MADERA_AIF3_RX_ENABLES:
case MADERA_SPD1_TX_CONTROL:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_SLIMBUS_FRAMER_REF_GEAR:
case MADERA_SLIMBUS_RATES_1:
case MADERA_SLIMBUS_RATES_2:
case MADERA_SLIMBUS_RATES_3:
case MADERA_SLIMBUS_RATES_5:
case MADERA_SLIMBUS_RATES_6:
case MADERA_SLIMBUS_RATES_7:
case MADERA_SLIMBUS_RX_CHANNEL_ENABLE:
case MADERA_SLIMBUS_TX_CHANNEL_ENABLE:
case MADERA_SLIMBUS_RX_PORT_STATUS:
case MADERA_SLIMBUS_TX_PORT_STATUS:
case MADERA_PWM1MIX_INPUT_1_SOURCE:
case MADERA_PWM1MIX_INPUT_1_VOLUME:
case MADERA_PWM1MIX_INPUT_2_SOURCE:
case MADERA_PWM1MIX_INPUT_2_VOLUME:
case MADERA_PWM1MIX_INPUT_3_SOURCE:
case MADERA_PWM1MIX_INPUT_3_VOLUME:
case MADERA_PWM1MIX_INPUT_4_SOURCE:
case MADERA_PWM1MIX_INPUT_4_VOLUME:
case MADERA_PWM2MIX_INPUT_1_SOURCE:
case MADERA_PWM2MIX_INPUT_1_VOLUME:
case MADERA_PWM2MIX_INPUT_2_SOURCE:
case MADERA_PWM2MIX_INPUT_2_VOLUME:
case MADERA_PWM2MIX_INPUT_3_SOURCE:
case MADERA_PWM2MIX_INPUT_3_VOLUME:
case MADERA_PWM2MIX_INPUT_4_SOURCE:
case MADERA_PWM2MIX_INPUT_4_VOLUME:
case MADERA_OUT1LMIX_INPUT_1_SOURCE:
case MADERA_OUT1LMIX_INPUT_1_VOLUME:
case MADERA_OUT1LMIX_INPUT_2_SOURCE:
case MADERA_OUT1LMIX_INPUT_2_VOLUME:
case MADERA_OUT1LMIX_INPUT_3_SOURCE:
case MADERA_OUT1LMIX_INPUT_3_VOLUME:
case MADERA_OUT1LMIX_INPUT_4_SOURCE:
case MADERA_OUT1LMIX_INPUT_4_VOLUME:
case MADERA_OUT1RMIX_INPUT_1_SOURCE:
case MADERA_OUT1RMIX_INPUT_1_VOLUME:
case MADERA_OUT1RMIX_INPUT_2_SOURCE:
case MADERA_OUT1RMIX_INPUT_2_VOLUME:
case MADERA_OUT1RMIX_INPUT_3_SOURCE:
case MADERA_OUT1RMIX_INPUT_3_VOLUME:
case MADERA_OUT1RMIX_INPUT_4_SOURCE:
case MADERA_OUT1RMIX_INPUT_4_VOLUME:
case MADERA_OUT4LMIX_INPUT_1_SOURCE:
case MADERA_OUT4LMIX_INPUT_1_VOLUME:
case MADERA_OUT4LMIX_INPUT_2_SOURCE:
case MADERA_OUT4LMIX_INPUT_2_VOLUME:
case MADERA_OUT4LMIX_INPUT_3_SOURCE:
case MADERA_OUT4LMIX_INPUT_3_VOLUME:
case MADERA_OUT4LMIX_INPUT_4_SOURCE:
case MADERA_OUT4LMIX_INPUT_4_VOLUME:
case MADERA_OUT5LMIX_INPUT_1_SOURCE:
case MADERA_OUT5LMIX_INPUT_1_VOLUME:
case MADERA_OUT5LMIX_INPUT_2_SOURCE:
case MADERA_OUT5LMIX_INPUT_2_VOLUME:
case MADERA_OUT5LMIX_INPUT_3_SOURCE:
case MADERA_OUT5LMIX_INPUT_3_VOLUME:
case MADERA_OUT5LMIX_INPUT_4_SOURCE:
case MADERA_OUT5LMIX_INPUT_4_VOLUME:
case MADERA_OUT5RMIX_INPUT_1_SOURCE:
case MADERA_OUT5RMIX_INPUT_1_VOLUME:
case MADERA_OUT5RMIX_INPUT_2_SOURCE:
case MADERA_OUT5RMIX_INPUT_2_VOLUME:
case MADERA_OUT5RMIX_INPUT_3_SOURCE:
case MADERA_OUT5RMIX_INPUT_3_VOLUME:
case MADERA_OUT5RMIX_INPUT_4_SOURCE:
case MADERA_OUT5RMIX_INPUT_4_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_4_VOLUME:
case MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_1_SOURCE:
case MADERA_EQ1MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_2_SOURCE:
case MADERA_EQ1MIX_INPUT_2_VOLUME:
case MADERA_EQ1MIX_INPUT_3_SOURCE:
case MADERA_EQ1MIX_INPUT_3_VOLUME:
case MADERA_EQ1MIX_INPUT_4_SOURCE:
case MADERA_EQ1MIX_INPUT_4_VOLUME:
case MADERA_EQ2MIX_INPUT_1_SOURCE:
case MADERA_EQ2MIX_INPUT_1_VOLUME:
case MADERA_EQ2MIX_INPUT_2_SOURCE:
case MADERA_EQ2MIX_INPUT_2_VOLUME:
case MADERA_EQ2MIX_INPUT_3_SOURCE:
case MADERA_EQ2MIX_INPUT_3_VOLUME:
case MADERA_EQ2MIX_INPUT_4_SOURCE:
case MADERA_EQ2MIX_INPUT_4_VOLUME:
case MADERA_EQ3MIX_INPUT_1_SOURCE:
case MADERA_EQ3MIX_INPUT_1_VOLUME:
case MADERA_EQ3MIX_INPUT_2_SOURCE:
case MADERA_EQ3MIX_INPUT_2_VOLUME:
case MADERA_EQ3MIX_INPUT_3_SOURCE:
case MADERA_EQ3MIX_INPUT_3_VOLUME:
case MADERA_EQ3MIX_INPUT_4_SOURCE:
case MADERA_EQ3MIX_INPUT_4_VOLUME:
case MADERA_EQ4MIX_INPUT_1_SOURCE:
case MADERA_EQ4MIX_INPUT_1_VOLUME:
case MADERA_EQ4MIX_INPUT_2_SOURCE:
case MADERA_EQ4MIX_INPUT_2_VOLUME:
case MADERA_EQ4MIX_INPUT_3_SOURCE:
case MADERA_EQ4MIX_INPUT_3_VOLUME:
case MADERA_EQ4MIX_INPUT_4_SOURCE:
case MADERA_EQ4MIX_INPUT_4_VOLUME:
case MADERA_DRC1LMIX_INPUT_1_SOURCE:
case MADERA_DRC1LMIX_INPUT_1_VOLUME:
case MADERA_DRC1LMIX_INPUT_2_SOURCE:
case MADERA_DRC1LMIX_INPUT_2_VOLUME:
case MADERA_DRC1LMIX_INPUT_3_SOURCE:
case MADERA_DRC1LMIX_INPUT_3_VOLUME:
case MADERA_DRC1LMIX_INPUT_4_SOURCE:
case MADERA_DRC1LMIX_INPUT_4_VOLUME:
case MADERA_DRC1RMIX_INPUT_1_SOURCE:
case MADERA_DRC1RMIX_INPUT_1_VOLUME:
case MADERA_DRC1RMIX_INPUT_2_SOURCE:
case MADERA_DRC1RMIX_INPUT_2_VOLUME:
case MADERA_DRC1RMIX_INPUT_3_SOURCE:
case MADERA_DRC1RMIX_INPUT_3_VOLUME:
case MADERA_DRC1RMIX_INPUT_4_SOURCE:
case MADERA_DRC1RMIX_INPUT_4_VOLUME:
case MADERA_DRC2LMIX_INPUT_1_SOURCE:
case MADERA_DRC2LMIX_INPUT_1_VOLUME:
case MADERA_DRC2LMIX_INPUT_2_SOURCE:
case MADERA_DRC2LMIX_INPUT_2_VOLUME:
case MADERA_DRC2LMIX_INPUT_3_SOURCE:
case MADERA_DRC2LMIX_INPUT_3_VOLUME:
case MADERA_DRC2LMIX_INPUT_4_SOURCE:
case MADERA_DRC2LMIX_INPUT_4_VOLUME:
case MADERA_DRC2RMIX_INPUT_1_SOURCE:
case MADERA_DRC2RMIX_INPUT_1_VOLUME:
case MADERA_DRC2RMIX_INPUT_2_SOURCE:
case MADERA_DRC2RMIX_INPUT_2_VOLUME:
case MADERA_DRC2RMIX_INPUT_3_SOURCE:
case MADERA_DRC2RMIX_INPUT_3_VOLUME:
case MADERA_DRC2RMIX_INPUT_4_SOURCE:
case MADERA_DRC2RMIX_INPUT_4_VOLUME:
case MADERA_HPLP1MIX_INPUT_1_SOURCE:
case MADERA_HPLP1MIX_INPUT_1_VOLUME:
case MADERA_HPLP1MIX_INPUT_2_SOURCE:
case MADERA_HPLP1MIX_INPUT_2_VOLUME:
case MADERA_HPLP1MIX_INPUT_3_SOURCE:
case MADERA_HPLP1MIX_INPUT_3_VOLUME:
case MADERA_HPLP1MIX_INPUT_4_SOURCE:
case MADERA_HPLP1MIX_INPUT_4_VOLUME:
case MADERA_HPLP2MIX_INPUT_1_SOURCE:
case MADERA_HPLP2MIX_INPUT_1_VOLUME:
case MADERA_HPLP2MIX_INPUT_2_SOURCE:
case MADERA_HPLP2MIX_INPUT_2_VOLUME:
case MADERA_HPLP2MIX_INPUT_3_SOURCE:
case MADERA_HPLP2MIX_INPUT_3_VOLUME:
case MADERA_HPLP2MIX_INPUT_4_SOURCE:
case MADERA_HPLP2MIX_INPUT_4_VOLUME:
case MADERA_HPLP3MIX_INPUT_1_SOURCE:
case MADERA_HPLP3MIX_INPUT_1_VOLUME:
case MADERA_HPLP3MIX_INPUT_2_SOURCE:
case MADERA_HPLP3MIX_INPUT_2_VOLUME:
case MADERA_HPLP3MIX_INPUT_3_SOURCE:
case MADERA_HPLP3MIX_INPUT_3_VOLUME:
case MADERA_HPLP3MIX_INPUT_4_SOURCE:
case MADERA_HPLP3MIX_INPUT_4_VOLUME:
case MADERA_HPLP4MIX_INPUT_1_SOURCE:
case MADERA_HPLP4MIX_INPUT_1_VOLUME:
case MADERA_HPLP4MIX_INPUT_2_SOURCE:
case MADERA_HPLP4MIX_INPUT_2_VOLUME:
case MADERA_HPLP4MIX_INPUT_3_SOURCE:
case MADERA_HPLP4MIX_INPUT_3_VOLUME:
case MADERA_HPLP4MIX_INPUT_4_SOURCE:
case MADERA_HPLP4MIX_INPUT_4_VOLUME:
case MADERA_DSP1LMIX_INPUT_1_SOURCE:
case MADERA_DSP1LMIX_INPUT_1_VOLUME:
case MADERA_DSP1LMIX_INPUT_2_SOURCE:
case MADERA_DSP1LMIX_INPUT_2_VOLUME:
case MADERA_DSP1LMIX_INPUT_3_SOURCE:
case MADERA_DSP1LMIX_INPUT_3_VOLUME:
case MADERA_DSP1LMIX_INPUT_4_SOURCE:
case MADERA_DSP1LMIX_INPUT_4_VOLUME:
case MADERA_DSP1RMIX_INPUT_1_SOURCE:
case MADERA_DSP1RMIX_INPUT_1_VOLUME:
case MADERA_DSP1RMIX_INPUT_2_SOURCE:
case MADERA_DSP1RMIX_INPUT_2_VOLUME:
case MADERA_DSP1RMIX_INPUT_3_SOURCE:
case MADERA_DSP1RMIX_INPUT_3_VOLUME:
case MADERA_DSP1RMIX_INPUT_4_SOURCE:
case MADERA_DSP1RMIX_INPUT_4_VOLUME:
case MADERA_DSP1AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP2LMIX_INPUT_1_SOURCE:
case MADERA_DSP2LMIX_INPUT_1_VOLUME:
case MADERA_DSP2LMIX_INPUT_2_SOURCE:
case MADERA_DSP2LMIX_INPUT_2_VOLUME:
case MADERA_DSP2LMIX_INPUT_3_SOURCE:
case MADERA_DSP2LMIX_INPUT_3_VOLUME:
case MADERA_DSP2LMIX_INPUT_4_SOURCE:
case MADERA_DSP2LMIX_INPUT_4_VOLUME:
case MADERA_DSP2RMIX_INPUT_1_SOURCE:
case MADERA_DSP2RMIX_INPUT_1_VOLUME:
case MADERA_DSP2RMIX_INPUT_2_SOURCE:
case MADERA_DSP2RMIX_INPUT_2_VOLUME:
case MADERA_DSP2RMIX_INPUT_3_SOURCE:
case MADERA_DSP2RMIX_INPUT_3_VOLUME:
case MADERA_DSP2RMIX_INPUT_4_SOURCE:
case MADERA_DSP2RMIX_INPUT_4_VOLUME:
case MADERA_DSP2AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP3LMIX_INPUT_1_SOURCE:
case MADERA_DSP3LMIX_INPUT_1_VOLUME:
case MADERA_DSP3LMIX_INPUT_2_SOURCE:
case MADERA_DSP3LMIX_INPUT_2_VOLUME:
case MADERA_DSP3LMIX_INPUT_3_SOURCE:
case MADERA_DSP3LMIX_INPUT_3_VOLUME:
case MADERA_DSP3LMIX_INPUT_4_SOURCE:
case MADERA_DSP3LMIX_INPUT_4_VOLUME:
case MADERA_DSP3RMIX_INPUT_1_SOURCE:
case MADERA_DSP3RMIX_INPUT_1_VOLUME:
case MADERA_DSP3RMIX_INPUT_2_SOURCE:
case MADERA_DSP3RMIX_INPUT_2_VOLUME:
case MADERA_DSP3RMIX_INPUT_3_SOURCE:
case MADERA_DSP3RMIX_INPUT_3_VOLUME:
case MADERA_DSP3RMIX_INPUT_4_SOURCE:
case MADERA_DSP3RMIX_INPUT_4_VOLUME:
case MADERA_DSP3AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX6MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT3MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT4MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT3MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT4MIX_INPUT_1_SOURCE:
case MADERA_FX_CTRL1:
case MADERA_FX_CTRL2:
case MADERA_EQ1_1 ... MADERA_EQ1_21:
case MADERA_EQ2_1 ... MADERA_EQ2_21:
case MADERA_EQ3_1 ... MADERA_EQ3_21:
case MADERA_EQ4_1 ... MADERA_EQ4_21:
case MADERA_DRC1_CTRL1:
case MADERA_DRC1_CTRL2:
case MADERA_DRC1_CTRL3:
case MADERA_DRC1_CTRL4:
case MADERA_DRC1_CTRL5:
case MADERA_DRC2_CTRL1:
case MADERA_DRC2_CTRL2:
case MADERA_DRC2_CTRL3:
case MADERA_DRC2_CTRL4:
case MADERA_DRC2_CTRL5:
case MADERA_HPLPF1_1:
case MADERA_HPLPF1_2:
case MADERA_HPLPF2_1:
case MADERA_HPLPF2_2:
case MADERA_HPLPF3_1:
case MADERA_HPLPF3_2:
case MADERA_HPLPF4_1:
case MADERA_HPLPF4_2:
case MADERA_ISRC_1_CTRL_1:
case MADERA_ISRC_1_CTRL_2:
case MADERA_ISRC_1_CTRL_3:
case MADERA_ISRC_2_CTRL_1:
case MADERA_ISRC_2_CTRL_2:
case MADERA_ISRC_2_CTRL_3:
case MADERA_GPIO1_CTRL_1 ... MADERA_GPIO16_CTRL_2:
case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_MASK_1 ... MADERA_IRQ1_MASK_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
case MADERA_INTERRUPT_DEBOUNCE_7:
case MADERA_IRQ1_CTRL:
return true;
default:
return false;
}
}
static bool cs47l35_16bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0:
case MADERA_WRITE_SEQUENCER_CTRL_1:
case MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_HAPTICS_STATUS:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_DCS_HP1L_CONTROL:
case MADERA_DCS_HP1R_CONTROL:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_SLIMBUS_RX_PORT_STATUS:
case MADERA_SLIMBUS_TX_PORT_STATUS:
case MADERA_FX_CTRL2:
case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
return true;
default:
return false;
}
}
static bool cs47l35_32bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_252:
case CS47L35_OTP_HPDET_CAL_1 ... CS47L35_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_SCRATCH_2:
case MADERA_DSP2_CONFIG_1 ... MADERA_DSP2_SCRATCH_2:
case MADERA_DSP3_CONFIG_1 ... MADERA_DSP3_SCRATCH_2:
return true;
default:
return cs47l35_is_adsp_memory(reg);
}
}
static bool cs47l35_32bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_252:
case CS47L35_OTP_HPDET_CAL_1 ... CS47L35_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_SCRATCH_2:
case MADERA_DSP2_CONFIG_1 ... MADERA_DSP2_SCRATCH_2:
case MADERA_DSP3_CONFIG_1 ... MADERA_DSP3_SCRATCH_2:
return true;
default:
return cs47l35_is_adsp_memory(reg);
}
}
const struct regmap_config cs47l35_16bit_spi_regmap = {
.name = "cs47l35_16bit",
.reg_bits = 32,
.pad_bits = 16,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = 0x1b00,
.readable_reg = cs47l35_16bit_readable_register,
.volatile_reg = cs47l35_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l35_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l35_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l35_16bit_spi_regmap);
const struct regmap_config cs47l35_16bit_i2c_regmap = {
.name = "cs47l35_16bit",
.reg_bits = 32,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = 0x1b00,
.readable_reg = cs47l35_16bit_readable_register,
.volatile_reg = cs47l35_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l35_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l35_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l35_16bit_i2c_regmap);
const struct regmap_config cs47l35_32bit_spi_regmap = {
.name = "cs47l35_32bit",
.reg_bits = 32,
.reg_stride = 2,
.pad_bits = 16,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_DSP3_SCRATCH_2,
.readable_reg = cs47l35_32bit_readable_register,
.volatile_reg = cs47l35_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l35_32bit_spi_regmap);
const struct regmap_config cs47l35_32bit_i2c_regmap = {
.name = "cs47l35_32bit",
.reg_bits = 32,
.reg_stride = 2,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_DSP3_SCRATCH_2,
.readable_reg = cs47l35_32bit_readable_register,
.volatile_reg = cs47l35_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l35_32bit_i2c_regmap);
| linux-master | drivers/mfd/cs47l35-tables.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MFD core driver for X-Powers' AC100 Audio Codec IC
*
* The AC100 is a highly integrated audio codec and RTC subsystem designed
* for mobile applications. It has 3 I2S/PCM interfaces, a 2 channel DAC,
* a 2 channel ADC with 5 inputs and a builtin mixer. The RTC subsystem has
* 3 clock outputs.
*
* The audio codec and RTC parts are completely separate, sharing only the
* host interface for access to its registers.
*
* Copyright (2016) Chen-Yu Tsai
*
* Author: Chen-Yu Tsai <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/ac100.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/sunxi-rsb.h>
static const struct regmap_range ac100_writeable_ranges[] = {
regmap_reg_range(AC100_CHIP_AUDIO_RST, AC100_I2S_SR_CTRL),
regmap_reg_range(AC100_I2S1_CLK_CTRL, AC100_I2S1_MXR_GAIN),
regmap_reg_range(AC100_I2S2_CLK_CTRL, AC100_I2S2_MXR_GAIN),
regmap_reg_range(AC100_I2S3_CLK_CTRL, AC100_I2S3_SIG_PATH_CTRL),
regmap_reg_range(AC100_ADC_DIG_CTRL, AC100_ADC_VOL_CTRL),
regmap_reg_range(AC100_HMIC_CTRL1, AC100_HMIC_STATUS),
regmap_reg_range(AC100_DAC_DIG_CTRL, AC100_DAC_MXR_GAIN),
regmap_reg_range(AC100_ADC_APC_CTRL, AC100_LINEOUT_CTRL),
regmap_reg_range(AC100_ADC_DAP_L_CTRL, AC100_ADC_DAP_OPT),
regmap_reg_range(AC100_DAC_DAP_CTRL, AC100_DAC_DAP_OPT),
regmap_reg_range(AC100_ADC_DAP_ENA, AC100_DAC_DAP_ENA),
regmap_reg_range(AC100_SRC1_CTRL1, AC100_SRC1_CTRL2),
regmap_reg_range(AC100_SRC2_CTRL1, AC100_SRC2_CTRL2),
regmap_reg_range(AC100_CLK32K_ANALOG_CTRL, AC100_CLKOUT_CTRL3),
regmap_reg_range(AC100_RTC_RST, AC100_RTC_UPD),
regmap_reg_range(AC100_ALM_INT_ENA, AC100_ALM_INT_STA),
regmap_reg_range(AC100_ALM_SEC, AC100_RTC_GP(15)),
};
static const struct regmap_range ac100_volatile_ranges[] = {
regmap_reg_range(AC100_CHIP_AUDIO_RST, AC100_PLL_CTRL2),
regmap_reg_range(AC100_HMIC_STATUS, AC100_HMIC_STATUS),
regmap_reg_range(AC100_ADC_DAP_L_STA, AC100_ADC_DAP_L_STA),
regmap_reg_range(AC100_SRC1_CTRL1, AC100_SRC1_CTRL1),
regmap_reg_range(AC100_SRC1_CTRL3, AC100_SRC2_CTRL1),
regmap_reg_range(AC100_SRC2_CTRL3, AC100_SRC2_CTRL4),
regmap_reg_range(AC100_RTC_RST, AC100_RTC_RST),
regmap_reg_range(AC100_RTC_SEC, AC100_ALM_INT_STA),
regmap_reg_range(AC100_ALM_SEC, AC100_ALM_UPD),
};
static const struct regmap_access_table ac100_writeable_table = {
.yes_ranges = ac100_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(ac100_writeable_ranges),
};
static const struct regmap_access_table ac100_volatile_table = {
.yes_ranges = ac100_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(ac100_volatile_ranges),
};
static const struct regmap_config ac100_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.wr_table = &ac100_writeable_table,
.volatile_table = &ac100_volatile_table,
.max_register = AC100_RTC_GP(15),
.cache_type = REGCACHE_RBTREE,
};
static struct mfd_cell ac100_cells[] = {
{
.name = "ac100-codec",
.of_compatible = "x-powers,ac100-codec",
}, {
.name = "ac100-rtc",
.of_compatible = "x-powers,ac100-rtc",
},
};
static int ac100_rsb_probe(struct sunxi_rsb_device *rdev)
{
struct ac100_dev *ac100;
int ret;
ac100 = devm_kzalloc(&rdev->dev, sizeof(*ac100), GFP_KERNEL);
if (!ac100)
return -ENOMEM;
ac100->dev = &rdev->dev;
sunxi_rsb_device_set_drvdata(rdev, ac100);
ac100->regmap = devm_regmap_init_sunxi_rsb(rdev, &ac100_regmap_config);
if (IS_ERR(ac100->regmap)) {
ret = PTR_ERR(ac100->regmap);
dev_err(ac100->dev, "regmap init failed: %d\n", ret);
return ret;
}
ret = devm_mfd_add_devices(ac100->dev, PLATFORM_DEVID_NONE, ac100_cells,
ARRAY_SIZE(ac100_cells), NULL, 0, NULL);
if (ret) {
dev_err(ac100->dev, "failed to add MFD devices: %d\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id ac100_of_match[] = {
{ .compatible = "x-powers,ac100" },
{ },
};
MODULE_DEVICE_TABLE(of, ac100_of_match);
static struct sunxi_rsb_driver ac100_rsb_driver = {
.driver = {
.name = "ac100",
.of_match_table = of_match_ptr(ac100_of_match),
},
.probe = ac100_rsb_probe,
};
module_sunxi_rsb_driver(ac100_rsb_driver);
MODULE_DESCRIPTION("Audio codec MFD core driver for AC100");
MODULE_AUTHOR("Chen-Yu Tsai <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/ac100.c |
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